1 /* 2 * Copyright (c) 2009-2010 Chelsio, Inc. All rights reserved. 3 * 4 * This software is available to you under a choice of one of two 5 * licenses. You may choose to be licensed under the terms of the GNU 6 * General Public License (GPL) Version 2, available from the file 7 * COPYING in the main directory of this source tree, or the 8 * OpenIB.org BSD license below: 9 * 10 * Redistribution and use in source and binary forms, with or 11 * without modification, are permitted provided that the following 12 * conditions are met: 13 * 14 * - Redistributions of source code must retain the above 15 * copyright notice, this list of conditions and the following 16 * disclaimer. 17 * - Redistributions in binary form must reproduce the above 18 * copyright notice, this list of conditions and the following 19 * disclaimer in the documentation and/or other materials 20 * provided with the distribution. 21 * 22 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, 23 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF 24 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND 25 * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS 26 * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN 27 * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN 28 * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE 29 * SOFTWARE. 30 */ 31 #ifndef __IW_CXGB4_H__ 32 #define __IW_CXGB4_H__ 33 34 #include <linux/mutex.h> 35 #include <linux/list.h> 36 #include <linux/spinlock.h> 37 #include <linux/idr.h> 38 #include <linux/completion.h> 39 #include <linux/netdevice.h> 40 #include <linux/sched/mm.h> 41 #include <linux/pci.h> 42 #include <linux/dma-mapping.h> 43 #include <linux/inet.h> 44 #include <linux/wait.h> 45 #include <linux/kref.h> 46 #include <linux/timer.h> 47 #include <linux/io.h> 48 #include <linux/workqueue.h> 49 50 #include <asm/byteorder.h> 51 52 #include <net/net_namespace.h> 53 54 #include <rdma/ib_verbs.h> 55 #include <rdma/iw_cm.h> 56 #include <rdma/rdma_netlink.h> 57 #include <rdma/iw_portmap.h> 58 #include <rdma/restrack.h> 59 60 #include "cxgb4.h" 61 #include "cxgb4_uld.h" 62 #include "l2t.h" 63 #include <rdma/cxgb4-abi.h> 64 65 #define DRV_NAME "iw_cxgb4" 66 #define MOD DRV_NAME ":" 67 68 #ifdef pr_fmt 69 #undef pr_fmt 70 #endif 71 72 #define pr_fmt(fmt) KBUILD_MODNAME ": " fmt 73 74 #include "t4.h" 75 76 #define PBL_OFF(rdev_p, a) ((a) - (rdev_p)->lldi.vr->pbl.start) 77 #define RQT_OFF(rdev_p, a) ((a) - (rdev_p)->lldi.vr->rq.start) 78 79 static inline void *cplhdr(struct sk_buff *skb) 80 { 81 return skb->data; 82 } 83 84 #define C4IW_ID_TABLE_F_RANDOM 1 /* Pseudo-randomize the id's returned */ 85 #define C4IW_ID_TABLE_F_EMPTY 2 /* Table is initially empty */ 86 87 struct c4iw_id_table { 88 u32 flags; 89 u32 start; /* logical minimal id */ 90 u32 last; /* hint for find */ 91 u32 max; 92 spinlock_t lock; 93 unsigned long *table; 94 }; 95 96 struct c4iw_resource { 97 struct c4iw_id_table tpt_table; 98 struct c4iw_id_table qid_table; 99 struct c4iw_id_table pdid_table; 100 struct c4iw_id_table srq_table; 101 }; 102 103 struct c4iw_qid_list { 104 struct list_head entry; 105 u32 qid; 106 }; 107 108 struct c4iw_dev_ucontext { 109 struct list_head qpids; 110 struct list_head cqids; 111 struct mutex lock; 112 struct kref kref; 113 }; 114 115 enum c4iw_rdev_flags { 116 T4_FATAL_ERROR = (1<<0), 117 T4_STATUS_PAGE_DISABLED = (1<<1), 118 }; 119 120 struct c4iw_stat { 121 u64 total; 122 u64 cur; 123 u64 max; 124 u64 fail; 125 }; 126 127 struct c4iw_stats { 128 struct mutex lock; 129 struct c4iw_stat qid; 130 struct c4iw_stat pd; 131 struct c4iw_stat stag; 132 struct c4iw_stat pbl; 133 struct c4iw_stat rqt; 134 struct c4iw_stat srqt; 135 struct c4iw_stat srq; 136 struct c4iw_stat ocqp; 137 u64 db_full; 138 u64 db_empty; 139 u64 db_drop; 140 u64 db_state_transitions; 141 u64 db_fc_interruptions; 142 u64 tcam_full; 143 u64 act_ofld_conn_fails; 144 u64 pas_ofld_conn_fails; 145 u64 neg_adv; 146 }; 147 148 struct c4iw_hw_queue { 149 int t4_eq_status_entries; 150 int t4_max_eq_size; 151 int t4_max_iq_size; 152 int t4_max_rq_size; 153 int t4_max_sq_size; 154 int t4_max_qp_depth; 155 int t4_max_cq_depth; 156 int t4_stat_len; 157 }; 158 159 struct wr_log_entry { 160 ktime_t post_host_time; 161 ktime_t poll_host_time; 162 u64 post_sge_ts; 163 u64 cqe_sge_ts; 164 u64 poll_sge_ts; 165 u16 qid; 166 u16 wr_id; 167 u8 opcode; 168 u8 valid; 169 }; 170 171 struct c4iw_rdev { 172 struct c4iw_resource resource; 173 u32 qpmask; 174 u32 cqmask; 175 struct c4iw_dev_ucontext uctx; 176 struct gen_pool *pbl_pool; 177 struct gen_pool *rqt_pool; 178 struct gen_pool *ocqp_pool; 179 u32 flags; 180 struct cxgb4_lld_info lldi; 181 unsigned long bar2_pa; 182 void __iomem *bar2_kva; 183 unsigned long oc_mw_pa; 184 void __iomem *oc_mw_kva; 185 struct c4iw_stats stats; 186 struct c4iw_hw_queue hw_queue; 187 struct t4_dev_status_page *status_page; 188 atomic_t wr_log_idx; 189 struct wr_log_entry *wr_log; 190 int wr_log_size; 191 struct workqueue_struct *free_workq; 192 struct completion rqt_compl; 193 struct completion pbl_compl; 194 struct kref rqt_kref; 195 struct kref pbl_kref; 196 }; 197 198 static inline int c4iw_fatal_error(struct c4iw_rdev *rdev) 199 { 200 return rdev->flags & T4_FATAL_ERROR; 201 } 202 203 static inline int c4iw_num_stags(struct c4iw_rdev *rdev) 204 { 205 return (int)(rdev->lldi.vr->stag.size >> 5); 206 } 207 208 #define C4IW_WR_TO (60*HZ) 209 210 struct c4iw_wr_wait { 211 struct completion completion; 212 int ret; 213 struct kref kref; 214 }; 215 216 void _c4iw_free_wr_wait(struct kref *kref); 217 218 static inline void c4iw_put_wr_wait(struct c4iw_wr_wait *wr_waitp) 219 { 220 pr_debug("wr_wait %p ref before put %u\n", wr_waitp, 221 kref_read(&wr_waitp->kref)); 222 WARN_ON(kref_read(&wr_waitp->kref) == 0); 223 kref_put(&wr_waitp->kref, _c4iw_free_wr_wait); 224 } 225 226 static inline void c4iw_get_wr_wait(struct c4iw_wr_wait *wr_waitp) 227 { 228 pr_debug("wr_wait %p ref before get %u\n", wr_waitp, 229 kref_read(&wr_waitp->kref)); 230 WARN_ON(kref_read(&wr_waitp->kref) == 0); 231 kref_get(&wr_waitp->kref); 232 } 233 234 static inline void c4iw_init_wr_wait(struct c4iw_wr_wait *wr_waitp) 235 { 236 wr_waitp->ret = 0; 237 init_completion(&wr_waitp->completion); 238 } 239 240 static inline void _c4iw_wake_up(struct c4iw_wr_wait *wr_waitp, int ret, 241 bool deref) 242 { 243 wr_waitp->ret = ret; 244 complete(&wr_waitp->completion); 245 if (deref) 246 c4iw_put_wr_wait(wr_waitp); 247 } 248 249 static inline void c4iw_wake_up_noref(struct c4iw_wr_wait *wr_waitp, int ret) 250 { 251 _c4iw_wake_up(wr_waitp, ret, false); 252 } 253 254 static inline void c4iw_wake_up_deref(struct c4iw_wr_wait *wr_waitp, int ret) 255 { 256 _c4iw_wake_up(wr_waitp, ret, true); 257 } 258 259 static inline int c4iw_wait_for_reply(struct c4iw_rdev *rdev, 260 struct c4iw_wr_wait *wr_waitp, 261 u32 hwtid, u32 qpid, 262 const char *func) 263 { 264 int ret; 265 266 if (c4iw_fatal_error(rdev)) { 267 wr_waitp->ret = -EIO; 268 goto out; 269 } 270 271 ret = wait_for_completion_timeout(&wr_waitp->completion, C4IW_WR_TO); 272 if (!ret) { 273 pr_err("%s - Device %s not responding (disabling device) - tid %u qpid %u\n", 274 func, pci_name(rdev->lldi.pdev), hwtid, qpid); 275 rdev->flags |= T4_FATAL_ERROR; 276 wr_waitp->ret = -EIO; 277 goto out; 278 } 279 if (wr_waitp->ret) 280 pr_debug("%s: FW reply %d tid %u qpid %u\n", 281 pci_name(rdev->lldi.pdev), wr_waitp->ret, hwtid, qpid); 282 out: 283 return wr_waitp->ret; 284 } 285 286 int c4iw_ofld_send(struct c4iw_rdev *rdev, struct sk_buff *skb); 287 288 static inline int c4iw_ref_send_wait(struct c4iw_rdev *rdev, 289 struct sk_buff *skb, 290 struct c4iw_wr_wait *wr_waitp, 291 u32 hwtid, u32 qpid, 292 const char *func) 293 { 294 int ret; 295 296 pr_debug("%s wr_wait %p hwtid %u qpid %u\n", func, wr_waitp, hwtid, 297 qpid); 298 c4iw_get_wr_wait(wr_waitp); 299 ret = c4iw_ofld_send(rdev, skb); 300 if (ret) { 301 c4iw_put_wr_wait(wr_waitp); 302 return ret; 303 } 304 return c4iw_wait_for_reply(rdev, wr_waitp, hwtid, qpid, func); 305 } 306 307 enum db_state { 308 NORMAL = 0, 309 FLOW_CONTROL = 1, 310 RECOVERY = 2, 311 STOPPED = 3 312 }; 313 314 struct c4iw_dev { 315 struct ib_device ibdev; 316 struct c4iw_rdev rdev; 317 u32 device_cap_flags; 318 struct idr cqidr; 319 struct idr qpidr; 320 struct idr mmidr; 321 spinlock_t lock; 322 struct mutex db_mutex; 323 struct dentry *debugfs_root; 324 enum db_state db_state; 325 struct idr hwtid_idr; 326 struct idr atid_idr; 327 struct idr stid_idr; 328 struct list_head db_fc_list; 329 u32 avail_ird; 330 wait_queue_head_t wait; 331 }; 332 333 struct uld_ctx { 334 struct list_head entry; 335 struct cxgb4_lld_info lldi; 336 struct c4iw_dev *dev; 337 struct work_struct reg_work; 338 }; 339 340 static inline struct c4iw_dev *to_c4iw_dev(struct ib_device *ibdev) 341 { 342 return container_of(ibdev, struct c4iw_dev, ibdev); 343 } 344 345 static inline struct c4iw_dev *rdev_to_c4iw_dev(struct c4iw_rdev *rdev) 346 { 347 return container_of(rdev, struct c4iw_dev, rdev); 348 } 349 350 static inline struct c4iw_cq *get_chp(struct c4iw_dev *rhp, u32 cqid) 351 { 352 return idr_find(&rhp->cqidr, cqid); 353 } 354 355 static inline struct c4iw_qp *get_qhp(struct c4iw_dev *rhp, u32 qpid) 356 { 357 return idr_find(&rhp->qpidr, qpid); 358 } 359 360 static inline struct c4iw_mr *get_mhp(struct c4iw_dev *rhp, u32 mmid) 361 { 362 return idr_find(&rhp->mmidr, mmid); 363 } 364 365 static inline int _insert_handle(struct c4iw_dev *rhp, struct idr *idr, 366 void *handle, u32 id, int lock) 367 { 368 int ret; 369 370 if (lock) { 371 idr_preload(GFP_KERNEL); 372 spin_lock_irq(&rhp->lock); 373 } 374 375 ret = idr_alloc(idr, handle, id, id + 1, GFP_ATOMIC); 376 377 if (lock) { 378 spin_unlock_irq(&rhp->lock); 379 idr_preload_end(); 380 } 381 382 return ret < 0 ? ret : 0; 383 } 384 385 static inline int insert_handle(struct c4iw_dev *rhp, struct idr *idr, 386 void *handle, u32 id) 387 { 388 return _insert_handle(rhp, idr, handle, id, 1); 389 } 390 391 static inline int insert_handle_nolock(struct c4iw_dev *rhp, struct idr *idr, 392 void *handle, u32 id) 393 { 394 return _insert_handle(rhp, idr, handle, id, 0); 395 } 396 397 static inline void _remove_handle(struct c4iw_dev *rhp, struct idr *idr, 398 u32 id, int lock) 399 { 400 if (lock) 401 spin_lock_irq(&rhp->lock); 402 idr_remove(idr, id); 403 if (lock) 404 spin_unlock_irq(&rhp->lock); 405 } 406 407 static inline void remove_handle(struct c4iw_dev *rhp, struct idr *idr, u32 id) 408 { 409 _remove_handle(rhp, idr, id, 1); 410 } 411 412 static inline void remove_handle_nolock(struct c4iw_dev *rhp, 413 struct idr *idr, u32 id) 414 { 415 _remove_handle(rhp, idr, id, 0); 416 } 417 418 extern uint c4iw_max_read_depth; 419 420 static inline int cur_max_read_depth(struct c4iw_dev *dev) 421 { 422 return min(dev->rdev.lldi.max_ordird_qp, c4iw_max_read_depth); 423 } 424 425 struct c4iw_pd { 426 struct ib_pd ibpd; 427 u32 pdid; 428 struct c4iw_dev *rhp; 429 }; 430 431 static inline struct c4iw_pd *to_c4iw_pd(struct ib_pd *ibpd) 432 { 433 return container_of(ibpd, struct c4iw_pd, ibpd); 434 } 435 436 struct tpt_attributes { 437 u64 len; 438 u64 va_fbo; 439 enum fw_ri_mem_perms perms; 440 u32 stag; 441 u32 pdid; 442 u32 qpid; 443 u32 pbl_addr; 444 u32 pbl_size; 445 u32 state:1; 446 u32 type:2; 447 u32 rsvd:1; 448 u32 remote_invaliate_disable:1; 449 u32 zbva:1; 450 u32 mw_bind_enable:1; 451 u32 page_size:5; 452 }; 453 454 struct c4iw_mr { 455 struct ib_mr ibmr; 456 struct ib_umem *umem; 457 struct c4iw_dev *rhp; 458 struct sk_buff *dereg_skb; 459 u64 kva; 460 struct tpt_attributes attr; 461 u64 *mpl; 462 dma_addr_t mpl_addr; 463 u32 max_mpl_len; 464 u32 mpl_len; 465 struct c4iw_wr_wait *wr_waitp; 466 }; 467 468 static inline struct c4iw_mr *to_c4iw_mr(struct ib_mr *ibmr) 469 { 470 return container_of(ibmr, struct c4iw_mr, ibmr); 471 } 472 473 struct c4iw_mw { 474 struct ib_mw ibmw; 475 struct c4iw_dev *rhp; 476 struct sk_buff *dereg_skb; 477 u64 kva; 478 struct tpt_attributes attr; 479 struct c4iw_wr_wait *wr_waitp; 480 }; 481 482 static inline struct c4iw_mw *to_c4iw_mw(struct ib_mw *ibmw) 483 { 484 return container_of(ibmw, struct c4iw_mw, ibmw); 485 } 486 487 struct c4iw_cq { 488 struct ib_cq ibcq; 489 struct c4iw_dev *rhp; 490 struct sk_buff *destroy_skb; 491 struct t4_cq cq; 492 spinlock_t lock; 493 spinlock_t comp_handler_lock; 494 atomic_t refcnt; 495 wait_queue_head_t wait; 496 struct c4iw_wr_wait *wr_waitp; 497 }; 498 499 static inline struct c4iw_cq *to_c4iw_cq(struct ib_cq *ibcq) 500 { 501 return container_of(ibcq, struct c4iw_cq, ibcq); 502 } 503 504 struct c4iw_mpa_attributes { 505 u8 initiator; 506 u8 recv_marker_enabled; 507 u8 xmit_marker_enabled; 508 u8 crc_enabled; 509 u8 enhanced_rdma_conn; 510 u8 version; 511 u8 p2p_type; 512 }; 513 514 struct c4iw_qp_attributes { 515 u32 scq; 516 u32 rcq; 517 u32 sq_num_entries; 518 u32 rq_num_entries; 519 u32 sq_max_sges; 520 u32 sq_max_sges_rdma_write; 521 u32 rq_max_sges; 522 u32 state; 523 u8 enable_rdma_read; 524 u8 enable_rdma_write; 525 u8 enable_bind; 526 u8 enable_mmid0_fastreg; 527 u32 max_ord; 528 u32 max_ird; 529 u32 pd; 530 u32 next_state; 531 char terminate_buffer[52]; 532 u32 terminate_msg_len; 533 u8 is_terminate_local; 534 struct c4iw_mpa_attributes mpa_attr; 535 struct c4iw_ep *llp_stream_handle; 536 u8 layer_etype; 537 u8 ecode; 538 u16 sq_db_inc; 539 u16 rq_db_inc; 540 u8 send_term; 541 }; 542 543 struct c4iw_qp { 544 struct ib_qp ibqp; 545 struct list_head db_fc_entry; 546 struct c4iw_dev *rhp; 547 struct c4iw_ep *ep; 548 struct c4iw_qp_attributes attr; 549 struct t4_wq wq; 550 spinlock_t lock; 551 struct mutex mutex; 552 struct kref kref; 553 wait_queue_head_t wait; 554 int sq_sig_all; 555 struct c4iw_srq *srq; 556 struct work_struct free_work; 557 struct c4iw_ucontext *ucontext; 558 struct c4iw_wr_wait *wr_waitp; 559 }; 560 561 static inline struct c4iw_qp *to_c4iw_qp(struct ib_qp *ibqp) 562 { 563 return container_of(ibqp, struct c4iw_qp, ibqp); 564 } 565 566 struct c4iw_srq { 567 struct ib_srq ibsrq; 568 struct list_head db_fc_entry; 569 struct c4iw_dev *rhp; 570 struct t4_srq wq; 571 struct sk_buff *destroy_skb; 572 u32 srq_limit; 573 u32 pdid; 574 int idx; 575 u32 flags; 576 spinlock_t lock; /* protects srq */ 577 struct c4iw_wr_wait *wr_waitp; 578 bool armed; 579 }; 580 581 static inline struct c4iw_srq *to_c4iw_srq(struct ib_srq *ibsrq) 582 { 583 return container_of(ibsrq, struct c4iw_srq, ibsrq); 584 } 585 586 struct c4iw_ucontext { 587 struct ib_ucontext ibucontext; 588 struct c4iw_dev_ucontext uctx; 589 u32 key; 590 spinlock_t mmap_lock; 591 struct list_head mmaps; 592 bool is_32b_cqe; 593 }; 594 595 static inline struct c4iw_ucontext *to_c4iw_ucontext(struct ib_ucontext *c) 596 { 597 return container_of(c, struct c4iw_ucontext, ibucontext); 598 } 599 600 struct c4iw_mm_entry { 601 struct list_head entry; 602 u64 addr; 603 u32 key; 604 unsigned len; 605 }; 606 607 static inline struct c4iw_mm_entry *remove_mmap(struct c4iw_ucontext *ucontext, 608 u32 key, unsigned len) 609 { 610 struct list_head *pos, *nxt; 611 struct c4iw_mm_entry *mm; 612 613 spin_lock(&ucontext->mmap_lock); 614 list_for_each_safe(pos, nxt, &ucontext->mmaps) { 615 616 mm = list_entry(pos, struct c4iw_mm_entry, entry); 617 if (mm->key == key && mm->len == len) { 618 list_del_init(&mm->entry); 619 spin_unlock(&ucontext->mmap_lock); 620 pr_debug("key 0x%x addr 0x%llx len %d\n", key, 621 (unsigned long long)mm->addr, mm->len); 622 return mm; 623 } 624 } 625 spin_unlock(&ucontext->mmap_lock); 626 return NULL; 627 } 628 629 static inline void insert_mmap(struct c4iw_ucontext *ucontext, 630 struct c4iw_mm_entry *mm) 631 { 632 spin_lock(&ucontext->mmap_lock); 633 pr_debug("key 0x%x addr 0x%llx len %d\n", 634 mm->key, (unsigned long long)mm->addr, mm->len); 635 list_add_tail(&mm->entry, &ucontext->mmaps); 636 spin_unlock(&ucontext->mmap_lock); 637 } 638 639 enum c4iw_qp_attr_mask { 640 C4IW_QP_ATTR_NEXT_STATE = 1 << 0, 641 C4IW_QP_ATTR_SQ_DB = 1<<1, 642 C4IW_QP_ATTR_RQ_DB = 1<<2, 643 C4IW_QP_ATTR_ENABLE_RDMA_READ = 1 << 7, 644 C4IW_QP_ATTR_ENABLE_RDMA_WRITE = 1 << 8, 645 C4IW_QP_ATTR_ENABLE_RDMA_BIND = 1 << 9, 646 C4IW_QP_ATTR_MAX_ORD = 1 << 11, 647 C4IW_QP_ATTR_MAX_IRD = 1 << 12, 648 C4IW_QP_ATTR_LLP_STREAM_HANDLE = 1 << 22, 649 C4IW_QP_ATTR_STREAM_MSG_BUFFER = 1 << 23, 650 C4IW_QP_ATTR_MPA_ATTR = 1 << 24, 651 C4IW_QP_ATTR_QP_CONTEXT_ACTIVATE = 1 << 25, 652 C4IW_QP_ATTR_VALID_MODIFY = (C4IW_QP_ATTR_ENABLE_RDMA_READ | 653 C4IW_QP_ATTR_ENABLE_RDMA_WRITE | 654 C4IW_QP_ATTR_MAX_ORD | 655 C4IW_QP_ATTR_MAX_IRD | 656 C4IW_QP_ATTR_LLP_STREAM_HANDLE | 657 C4IW_QP_ATTR_STREAM_MSG_BUFFER | 658 C4IW_QP_ATTR_MPA_ATTR | 659 C4IW_QP_ATTR_QP_CONTEXT_ACTIVATE) 660 }; 661 662 int c4iw_modify_qp(struct c4iw_dev *rhp, 663 struct c4iw_qp *qhp, 664 enum c4iw_qp_attr_mask mask, 665 struct c4iw_qp_attributes *attrs, 666 int internal); 667 668 enum c4iw_qp_state { 669 C4IW_QP_STATE_IDLE, 670 C4IW_QP_STATE_RTS, 671 C4IW_QP_STATE_ERROR, 672 C4IW_QP_STATE_TERMINATE, 673 C4IW_QP_STATE_CLOSING, 674 C4IW_QP_STATE_TOT 675 }; 676 677 static inline int c4iw_convert_state(enum ib_qp_state ib_state) 678 { 679 switch (ib_state) { 680 case IB_QPS_RESET: 681 case IB_QPS_INIT: 682 return C4IW_QP_STATE_IDLE; 683 case IB_QPS_RTS: 684 return C4IW_QP_STATE_RTS; 685 case IB_QPS_SQD: 686 return C4IW_QP_STATE_CLOSING; 687 case IB_QPS_SQE: 688 return C4IW_QP_STATE_TERMINATE; 689 case IB_QPS_ERR: 690 return C4IW_QP_STATE_ERROR; 691 default: 692 return -1; 693 } 694 } 695 696 static inline int to_ib_qp_state(int c4iw_qp_state) 697 { 698 switch (c4iw_qp_state) { 699 case C4IW_QP_STATE_IDLE: 700 return IB_QPS_INIT; 701 case C4IW_QP_STATE_RTS: 702 return IB_QPS_RTS; 703 case C4IW_QP_STATE_CLOSING: 704 return IB_QPS_SQD; 705 case C4IW_QP_STATE_TERMINATE: 706 return IB_QPS_SQE; 707 case C4IW_QP_STATE_ERROR: 708 return IB_QPS_ERR; 709 } 710 return IB_QPS_ERR; 711 } 712 713 static inline u32 c4iw_ib_to_tpt_access(int a) 714 { 715 return (a & IB_ACCESS_REMOTE_WRITE ? FW_RI_MEM_ACCESS_REM_WRITE : 0) | 716 (a & IB_ACCESS_REMOTE_READ ? FW_RI_MEM_ACCESS_REM_READ : 0) | 717 (a & IB_ACCESS_LOCAL_WRITE ? FW_RI_MEM_ACCESS_LOCAL_WRITE : 0) | 718 FW_RI_MEM_ACCESS_LOCAL_READ; 719 } 720 721 static inline u32 c4iw_ib_to_tpt_bind_access(int acc) 722 { 723 return (acc & IB_ACCESS_REMOTE_WRITE ? FW_RI_MEM_ACCESS_REM_WRITE : 0) | 724 (acc & IB_ACCESS_REMOTE_READ ? FW_RI_MEM_ACCESS_REM_READ : 0); 725 } 726 727 enum c4iw_mmid_state { 728 C4IW_STAG_STATE_VALID, 729 C4IW_STAG_STATE_INVALID 730 }; 731 732 #define C4IW_NODE_DESC "cxgb4 Chelsio Communications" 733 734 #define MPA_KEY_REQ "MPA ID Req Frame" 735 #define MPA_KEY_REP "MPA ID Rep Frame" 736 737 #define MPA_MAX_PRIVATE_DATA 256 738 #define MPA_ENHANCED_RDMA_CONN 0x10 739 #define MPA_REJECT 0x20 740 #define MPA_CRC 0x40 741 #define MPA_MARKERS 0x80 742 #define MPA_FLAGS_MASK 0xE0 743 744 #define MPA_V2_PEER2PEER_MODEL 0x8000 745 #define MPA_V2_ZERO_LEN_FPDU_RTR 0x4000 746 #define MPA_V2_RDMA_WRITE_RTR 0x8000 747 #define MPA_V2_RDMA_READ_RTR 0x4000 748 #define MPA_V2_IRD_ORD_MASK 0x3FFF 749 750 #define c4iw_put_ep(ep) { \ 751 pr_debug("put_ep ep %p refcnt %d\n", \ 752 ep, kref_read(&((ep)->kref))); \ 753 WARN_ON(kref_read(&((ep)->kref)) < 1); \ 754 kref_put(&((ep)->kref), _c4iw_free_ep); \ 755 } 756 757 #define c4iw_get_ep(ep) { \ 758 pr_debug("get_ep ep %p, refcnt %d\n", \ 759 ep, kref_read(&((ep)->kref))); \ 760 kref_get(&((ep)->kref)); \ 761 } 762 void _c4iw_free_ep(struct kref *kref); 763 764 struct mpa_message { 765 u8 key[16]; 766 u8 flags; 767 u8 revision; 768 __be16 private_data_size; 769 u8 private_data[0]; 770 }; 771 772 struct mpa_v2_conn_params { 773 __be16 ird; 774 __be16 ord; 775 }; 776 777 struct terminate_message { 778 u8 layer_etype; 779 u8 ecode; 780 __be16 hdrct_rsvd; 781 u8 len_hdrs[0]; 782 }; 783 784 #define TERM_MAX_LENGTH (sizeof(struct terminate_message) + 2 + 18 + 28) 785 786 enum c4iw_layers_types { 787 LAYER_RDMAP = 0x00, 788 LAYER_DDP = 0x10, 789 LAYER_MPA = 0x20, 790 RDMAP_LOCAL_CATA = 0x00, 791 RDMAP_REMOTE_PROT = 0x01, 792 RDMAP_REMOTE_OP = 0x02, 793 DDP_LOCAL_CATA = 0x00, 794 DDP_TAGGED_ERR = 0x01, 795 DDP_UNTAGGED_ERR = 0x02, 796 DDP_LLP = 0x03 797 }; 798 799 enum c4iw_rdma_ecodes { 800 RDMAP_INV_STAG = 0x00, 801 RDMAP_BASE_BOUNDS = 0x01, 802 RDMAP_ACC_VIOL = 0x02, 803 RDMAP_STAG_NOT_ASSOC = 0x03, 804 RDMAP_TO_WRAP = 0x04, 805 RDMAP_INV_VERS = 0x05, 806 RDMAP_INV_OPCODE = 0x06, 807 RDMAP_STREAM_CATA = 0x07, 808 RDMAP_GLOBAL_CATA = 0x08, 809 RDMAP_CANT_INV_STAG = 0x09, 810 RDMAP_UNSPECIFIED = 0xff 811 }; 812 813 enum c4iw_ddp_ecodes { 814 DDPT_INV_STAG = 0x00, 815 DDPT_BASE_BOUNDS = 0x01, 816 DDPT_STAG_NOT_ASSOC = 0x02, 817 DDPT_TO_WRAP = 0x03, 818 DDPT_INV_VERS = 0x04, 819 DDPU_INV_QN = 0x01, 820 DDPU_INV_MSN_NOBUF = 0x02, 821 DDPU_INV_MSN_RANGE = 0x03, 822 DDPU_INV_MO = 0x04, 823 DDPU_MSG_TOOBIG = 0x05, 824 DDPU_INV_VERS = 0x06 825 }; 826 827 enum c4iw_mpa_ecodes { 828 MPA_CRC_ERR = 0x02, 829 MPA_MARKER_ERR = 0x03, 830 MPA_LOCAL_CATA = 0x05, 831 MPA_INSUFF_IRD = 0x06, 832 MPA_NOMATCH_RTR = 0x07, 833 }; 834 835 enum c4iw_ep_state { 836 IDLE = 0, 837 LISTEN, 838 CONNECTING, 839 MPA_REQ_WAIT, 840 MPA_REQ_SENT, 841 MPA_REQ_RCVD, 842 MPA_REP_SENT, 843 FPDU_MODE, 844 ABORTING, 845 CLOSING, 846 MORIBUND, 847 DEAD, 848 }; 849 850 enum c4iw_ep_flags { 851 PEER_ABORT_IN_PROGRESS = 0, 852 ABORT_REQ_IN_PROGRESS = 1, 853 RELEASE_RESOURCES = 2, 854 CLOSE_SENT = 3, 855 TIMEOUT = 4, 856 QP_REFERENCED = 5, 857 STOP_MPA_TIMER = 7, 858 }; 859 860 enum c4iw_ep_history { 861 ACT_OPEN_REQ = 0, 862 ACT_OFLD_CONN = 1, 863 ACT_OPEN_RPL = 2, 864 ACT_ESTAB = 3, 865 PASS_ACCEPT_REQ = 4, 866 PASS_ESTAB = 5, 867 ABORT_UPCALL = 6, 868 ESTAB_UPCALL = 7, 869 CLOSE_UPCALL = 8, 870 ULP_ACCEPT = 9, 871 ULP_REJECT = 10, 872 TIMEDOUT = 11, 873 PEER_ABORT = 12, 874 PEER_CLOSE = 13, 875 CONNREQ_UPCALL = 14, 876 ABORT_CONN = 15, 877 DISCONN_UPCALL = 16, 878 EP_DISC_CLOSE = 17, 879 EP_DISC_ABORT = 18, 880 CONN_RPL_UPCALL = 19, 881 ACT_RETRY_NOMEM = 20, 882 ACT_RETRY_INUSE = 21, 883 CLOSE_CON_RPL = 22, 884 EP_DISC_FAIL = 24, 885 QP_REFED = 25, 886 QP_DEREFED = 26, 887 CM_ID_REFED = 27, 888 CM_ID_DEREFED = 28, 889 }; 890 891 enum conn_pre_alloc_buffers { 892 CN_ABORT_REQ_BUF, 893 CN_ABORT_RPL_BUF, 894 CN_CLOSE_CON_REQ_BUF, 895 CN_DESTROY_BUF, 896 CN_FLOWC_BUF, 897 CN_MAX_CON_BUF 898 }; 899 900 enum { 901 FLOWC_LEN = offsetof(struct fw_flowc_wr, mnemval[FW_FLOWC_MNEM_MAX]) 902 }; 903 904 union cpl_wr_size { 905 struct cpl_abort_req abrt_req; 906 struct cpl_abort_rpl abrt_rpl; 907 struct fw_ri_wr ri_req; 908 struct cpl_close_con_req close_req; 909 char flowc_buf[FLOWC_LEN]; 910 }; 911 912 struct c4iw_ep_common { 913 struct iw_cm_id *cm_id; 914 struct c4iw_qp *qp; 915 struct c4iw_dev *dev; 916 struct sk_buff_head ep_skb_list; 917 enum c4iw_ep_state state; 918 struct kref kref; 919 struct mutex mutex; 920 struct sockaddr_storage local_addr; 921 struct sockaddr_storage remote_addr; 922 struct c4iw_wr_wait *wr_waitp; 923 unsigned long flags; 924 unsigned long history; 925 }; 926 927 struct c4iw_listen_ep { 928 struct c4iw_ep_common com; 929 unsigned int stid; 930 int backlog; 931 }; 932 933 struct c4iw_ep_stats { 934 unsigned connect_neg_adv; 935 unsigned abort_neg_adv; 936 }; 937 938 struct c4iw_ep { 939 struct c4iw_ep_common com; 940 struct c4iw_ep *parent_ep; 941 struct timer_list timer; 942 struct list_head entry; 943 unsigned int atid; 944 u32 hwtid; 945 u32 snd_seq; 946 u32 rcv_seq; 947 struct l2t_entry *l2t; 948 struct dst_entry *dst; 949 struct sk_buff *mpa_skb; 950 struct c4iw_mpa_attributes mpa_attr; 951 u8 mpa_pkt[sizeof(struct mpa_message) + MPA_MAX_PRIVATE_DATA]; 952 unsigned int mpa_pkt_len; 953 u32 ird; 954 u32 ord; 955 u32 smac_idx; 956 u32 tx_chan; 957 u32 mtu; 958 u16 mss; 959 u16 emss; 960 u16 plen; 961 u16 rss_qid; 962 u16 txq_idx; 963 u16 ctrlq_idx; 964 u8 tos; 965 u8 retry_with_mpa_v1; 966 u8 tried_with_mpa_v1; 967 unsigned int retry_count; 968 int snd_win; 969 int rcv_win; 970 u32 snd_wscale; 971 struct c4iw_ep_stats stats; 972 u32 srqe_idx; 973 u32 rx_pdu_out_cnt; 974 struct sk_buff *peer_abort_skb; 975 }; 976 977 static inline struct c4iw_ep *to_ep(struct iw_cm_id *cm_id) 978 { 979 return cm_id->provider_data; 980 } 981 982 static inline struct c4iw_listen_ep *to_listen_ep(struct iw_cm_id *cm_id) 983 { 984 return cm_id->provider_data; 985 } 986 987 static inline int ocqp_supported(const struct cxgb4_lld_info *infop) 988 { 989 #if defined(__i386__) || defined(__x86_64__) || defined(CONFIG_PPC64) 990 return infop->vr->ocq.size > 0; 991 #else 992 return 0; 993 #endif 994 } 995 996 u32 c4iw_id_alloc(struct c4iw_id_table *alloc); 997 void c4iw_id_free(struct c4iw_id_table *alloc, u32 obj); 998 int c4iw_id_table_alloc(struct c4iw_id_table *alloc, u32 start, u32 num, 999 u32 reserved, u32 flags); 1000 void c4iw_id_table_free(struct c4iw_id_table *alloc); 1001 1002 typedef int (*c4iw_handler_func)(struct c4iw_dev *dev, struct sk_buff *skb); 1003 1004 int c4iw_ep_redirect(void *ctx, struct dst_entry *old, struct dst_entry *new, 1005 struct l2t_entry *l2t); 1006 void c4iw_put_qpid(struct c4iw_rdev *rdev, u32 qpid, 1007 struct c4iw_dev_ucontext *uctx); 1008 u32 c4iw_get_resource(struct c4iw_id_table *id_table); 1009 void c4iw_put_resource(struct c4iw_id_table *id_table, u32 entry); 1010 int c4iw_init_resource(struct c4iw_rdev *rdev, u32 nr_tpt, 1011 u32 nr_pdid, u32 nr_srqt); 1012 int c4iw_init_ctrl_qp(struct c4iw_rdev *rdev); 1013 int c4iw_pblpool_create(struct c4iw_rdev *rdev); 1014 int c4iw_rqtpool_create(struct c4iw_rdev *rdev); 1015 int c4iw_ocqp_pool_create(struct c4iw_rdev *rdev); 1016 void c4iw_pblpool_destroy(struct c4iw_rdev *rdev); 1017 void c4iw_rqtpool_destroy(struct c4iw_rdev *rdev); 1018 void c4iw_ocqp_pool_destroy(struct c4iw_rdev *rdev); 1019 void c4iw_destroy_resource(struct c4iw_resource *rscp); 1020 int c4iw_destroy_ctrl_qp(struct c4iw_rdev *rdev); 1021 void c4iw_register_device(struct work_struct *work); 1022 void c4iw_unregister_device(struct c4iw_dev *dev); 1023 int __init c4iw_cm_init(void); 1024 void c4iw_cm_term(void); 1025 void c4iw_release_dev_ucontext(struct c4iw_rdev *rdev, 1026 struct c4iw_dev_ucontext *uctx); 1027 void c4iw_init_dev_ucontext(struct c4iw_rdev *rdev, 1028 struct c4iw_dev_ucontext *uctx); 1029 int c4iw_poll_cq(struct ib_cq *ibcq, int num_entries, struct ib_wc *wc); 1030 int c4iw_post_send(struct ib_qp *ibqp, const struct ib_send_wr *wr, 1031 const struct ib_send_wr **bad_wr); 1032 int c4iw_post_receive(struct ib_qp *ibqp, const struct ib_recv_wr *wr, 1033 const struct ib_recv_wr **bad_wr); 1034 int c4iw_connect(struct iw_cm_id *cm_id, struct iw_cm_conn_param *conn_param); 1035 int c4iw_create_listen(struct iw_cm_id *cm_id, int backlog); 1036 int c4iw_destroy_listen(struct iw_cm_id *cm_id); 1037 int c4iw_accept_cr(struct iw_cm_id *cm_id, struct iw_cm_conn_param *conn_param); 1038 int c4iw_reject_cr(struct iw_cm_id *cm_id, const void *pdata, u8 pdata_len); 1039 void c4iw_qp_add_ref(struct ib_qp *qp); 1040 void c4iw_qp_rem_ref(struct ib_qp *qp); 1041 struct ib_mr *c4iw_alloc_mr(struct ib_pd *pd, 1042 enum ib_mr_type mr_type, 1043 u32 max_num_sg); 1044 int c4iw_map_mr_sg(struct ib_mr *ibmr, struct scatterlist *sg, int sg_nents, 1045 unsigned int *sg_offset); 1046 int c4iw_dealloc_mw(struct ib_mw *mw); 1047 void c4iw_dealloc(struct uld_ctx *ctx); 1048 struct ib_mw *c4iw_alloc_mw(struct ib_pd *pd, enum ib_mw_type type, 1049 struct ib_udata *udata); 1050 struct ib_mr *c4iw_reg_user_mr(struct ib_pd *pd, u64 start, 1051 u64 length, u64 virt, int acc, 1052 struct ib_udata *udata); 1053 struct ib_mr *c4iw_get_dma_mr(struct ib_pd *pd, int acc); 1054 int c4iw_dereg_mr(struct ib_mr *ib_mr); 1055 int c4iw_destroy_cq(struct ib_cq *ib_cq); 1056 struct ib_cq *c4iw_create_cq(struct ib_device *ibdev, 1057 const struct ib_cq_init_attr *attr, 1058 struct ib_ucontext *ib_context, 1059 struct ib_udata *udata); 1060 int c4iw_arm_cq(struct ib_cq *ibcq, enum ib_cq_notify_flags flags); 1061 int c4iw_modify_srq(struct ib_srq *ib_srq, struct ib_srq_attr *attr, 1062 enum ib_srq_attr_mask srq_attr_mask, 1063 struct ib_udata *udata); 1064 int c4iw_destroy_srq(struct ib_srq *ib_srq); 1065 struct ib_srq *c4iw_create_srq(struct ib_pd *pd, 1066 struct ib_srq_init_attr *attrs, 1067 struct ib_udata *udata); 1068 int c4iw_destroy_qp(struct ib_qp *ib_qp); 1069 struct ib_qp *c4iw_create_qp(struct ib_pd *pd, 1070 struct ib_qp_init_attr *attrs, 1071 struct ib_udata *udata); 1072 int c4iw_ib_modify_qp(struct ib_qp *ibqp, struct ib_qp_attr *attr, 1073 int attr_mask, struct ib_udata *udata); 1074 int c4iw_ib_query_qp(struct ib_qp *ibqp, struct ib_qp_attr *attr, 1075 int attr_mask, struct ib_qp_init_attr *init_attr); 1076 struct ib_qp *c4iw_get_qp(struct ib_device *dev, int qpn); 1077 u32 c4iw_rqtpool_alloc(struct c4iw_rdev *rdev, int size); 1078 void c4iw_rqtpool_free(struct c4iw_rdev *rdev, u32 addr, int size); 1079 u32 c4iw_pblpool_alloc(struct c4iw_rdev *rdev, int size); 1080 void c4iw_pblpool_free(struct c4iw_rdev *rdev, u32 addr, int size); 1081 u32 c4iw_ocqp_pool_alloc(struct c4iw_rdev *rdev, int size); 1082 void c4iw_ocqp_pool_free(struct c4iw_rdev *rdev, u32 addr, int size); 1083 void c4iw_flush_hw_cq(struct c4iw_cq *chp, struct c4iw_qp *flush_qhp); 1084 void c4iw_count_rcqes(struct t4_cq *cq, struct t4_wq *wq, int *count); 1085 int c4iw_ep_disconnect(struct c4iw_ep *ep, int abrupt, gfp_t gfp); 1086 int c4iw_flush_rq(struct t4_wq *wq, struct t4_cq *cq, int count); 1087 int c4iw_flush_sq(struct c4iw_qp *qhp); 1088 int c4iw_ev_handler(struct c4iw_dev *rnicp, u32 qid); 1089 u16 c4iw_rqes_posted(struct c4iw_qp *qhp); 1090 int c4iw_post_terminate(struct c4iw_qp *qhp, struct t4_cqe *err_cqe); 1091 u32 c4iw_get_cqid(struct c4iw_rdev *rdev, struct c4iw_dev_ucontext *uctx); 1092 void c4iw_put_cqid(struct c4iw_rdev *rdev, u32 qid, 1093 struct c4iw_dev_ucontext *uctx); 1094 u32 c4iw_get_qpid(struct c4iw_rdev *rdev, struct c4iw_dev_ucontext *uctx); 1095 void c4iw_put_qpid(struct c4iw_rdev *rdev, u32 qid, 1096 struct c4iw_dev_ucontext *uctx); 1097 void c4iw_ev_dispatch(struct c4iw_dev *dev, struct t4_cqe *err_cqe); 1098 1099 extern struct cxgb4_client t4c_client; 1100 extern c4iw_handler_func c4iw_handlers[NUM_CPL_CMDS]; 1101 void __iomem *c4iw_bar2_addrs(struct c4iw_rdev *rdev, unsigned int qid, 1102 enum cxgb4_bar2_qtype qtype, 1103 unsigned int *pbar2_qid, u64 *pbar2_pa); 1104 int c4iw_alloc_srq_idx(struct c4iw_rdev *rdev); 1105 void c4iw_free_srq_idx(struct c4iw_rdev *rdev, int idx); 1106 extern void c4iw_log_wr_stats(struct t4_wq *wq, struct t4_cqe *cqe); 1107 extern int c4iw_wr_log; 1108 extern int db_fc_threshold; 1109 extern int db_coalescing_threshold; 1110 extern int use_dsgl; 1111 void c4iw_invalidate_mr(struct c4iw_dev *rhp, u32 rkey); 1112 void c4iw_dispatch_srq_limit_reached_event(struct c4iw_srq *srq); 1113 void c4iw_copy_wr_to_srq(struct t4_srq *srq, union t4_recv_wr *wqe, u8 len16); 1114 void c4iw_flush_srqidx(struct c4iw_qp *qhp, u32 srqidx); 1115 int c4iw_post_srq_recv(struct ib_srq *ibsrq, const struct ib_recv_wr *wr, 1116 const struct ib_recv_wr **bad_wr); 1117 struct c4iw_wr_wait *c4iw_alloc_wr_wait(gfp_t gfp); 1118 1119 typedef int c4iw_restrack_func(struct sk_buff *msg, 1120 struct rdma_restrack_entry *res); 1121 extern c4iw_restrack_func *c4iw_restrack_funcs[RDMA_RESTRACK_MAX]; 1122 1123 #endif 1124