1 /* 2 * Copyright (c) 2009-2010 Chelsio, Inc. All rights reserved. 3 * 4 * This software is available to you under a choice of one of two 5 * licenses. You may choose to be licensed under the terms of the GNU 6 * General Public License (GPL) Version 2, available from the file 7 * COPYING in the main directory of this source tree, or the 8 * OpenIB.org BSD license below: 9 * 10 * Redistribution and use in source and binary forms, with or 11 * without modification, are permitted provided that the following 12 * conditions are met: 13 * 14 * - Redistributions of source code must retain the above 15 * copyright notice, this list of conditions and the following 16 * disclaimer. 17 * - Redistributions in binary form must reproduce the above 18 * copyright notice, this list of conditions and the following 19 * disclaimer in the documentation and/or other materials 20 * provided with the distribution. 21 * 22 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, 23 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF 24 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND 25 * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS 26 * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN 27 * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN 28 * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE 29 * SOFTWARE. 30 */ 31 #ifndef __IW_CXGB4_H__ 32 #define __IW_CXGB4_H__ 33 34 #include <linux/mutex.h> 35 #include <linux/list.h> 36 #include <linux/spinlock.h> 37 #include <linux/idr.h> 38 #include <linux/completion.h> 39 #include <linux/netdevice.h> 40 #include <linux/sched.h> 41 #include <linux/pci.h> 42 #include <linux/dma-mapping.h> 43 #include <linux/inet.h> 44 #include <linux/wait.h> 45 #include <linux/kref.h> 46 #include <linux/timer.h> 47 #include <linux/io.h> 48 49 #include <asm/byteorder.h> 50 51 #include <net/net_namespace.h> 52 53 #include <rdma/ib_verbs.h> 54 #include <rdma/iw_cm.h> 55 56 #include "cxgb4.h" 57 #include "cxgb4_uld.h" 58 #include "l2t.h" 59 #include "user.h" 60 61 #define DRV_NAME "iw_cxgb4" 62 #define MOD DRV_NAME ":" 63 64 extern int c4iw_debug; 65 #define PDBG(fmt, args...) \ 66 do { \ 67 if (c4iw_debug) \ 68 printk(MOD fmt, ## args); \ 69 } while (0) 70 71 #include "t4.h" 72 73 #define PBL_OFF(rdev_p, a) ((a) - (rdev_p)->lldi.vr->pbl.start) 74 #define RQT_OFF(rdev_p, a) ((a) - (rdev_p)->lldi.vr->rq.start) 75 76 static inline void *cplhdr(struct sk_buff *skb) 77 { 78 return skb->data; 79 } 80 81 #define C4IW_ID_TABLE_F_RANDOM 1 /* Pseudo-randomize the id's returned */ 82 #define C4IW_ID_TABLE_F_EMPTY 2 /* Table is initially empty */ 83 84 struct c4iw_id_table { 85 u32 flags; 86 u32 start; /* logical minimal id */ 87 u32 last; /* hint for find */ 88 u32 max; 89 spinlock_t lock; 90 unsigned long *table; 91 }; 92 93 struct c4iw_resource { 94 struct c4iw_id_table tpt_table; 95 struct c4iw_id_table qid_table; 96 struct c4iw_id_table pdid_table; 97 }; 98 99 struct c4iw_qid_list { 100 struct list_head entry; 101 u32 qid; 102 }; 103 104 struct c4iw_dev_ucontext { 105 struct list_head qpids; 106 struct list_head cqids; 107 struct mutex lock; 108 }; 109 110 enum c4iw_rdev_flags { 111 T4_FATAL_ERROR = (1<<0), 112 T4_STATUS_PAGE_DISABLED = (1<<1), 113 }; 114 115 struct c4iw_stat { 116 u64 total; 117 u64 cur; 118 u64 max; 119 u64 fail; 120 }; 121 122 struct c4iw_stats { 123 struct mutex lock; 124 struct c4iw_stat qid; 125 struct c4iw_stat pd; 126 struct c4iw_stat stag; 127 struct c4iw_stat pbl; 128 struct c4iw_stat rqt; 129 struct c4iw_stat ocqp; 130 u64 db_full; 131 u64 db_empty; 132 u64 db_drop; 133 u64 db_state_transitions; 134 u64 db_fc_interruptions; 135 u64 tcam_full; 136 u64 act_ofld_conn_fails; 137 u64 pas_ofld_conn_fails; 138 }; 139 140 struct c4iw_rdev { 141 struct c4iw_resource resource; 142 unsigned long qpshift; 143 u32 qpmask; 144 unsigned long cqshift; 145 u32 cqmask; 146 struct c4iw_dev_ucontext uctx; 147 struct gen_pool *pbl_pool; 148 struct gen_pool *rqt_pool; 149 struct gen_pool *ocqp_pool; 150 u32 flags; 151 struct cxgb4_lld_info lldi; 152 unsigned long oc_mw_pa; 153 void __iomem *oc_mw_kva; 154 struct c4iw_stats stats; 155 struct t4_dev_status_page *status_page; 156 }; 157 158 static inline int c4iw_fatal_error(struct c4iw_rdev *rdev) 159 { 160 return rdev->flags & T4_FATAL_ERROR; 161 } 162 163 static inline int c4iw_num_stags(struct c4iw_rdev *rdev) 164 { 165 return min((int)T4_MAX_NUM_STAG, (int)(rdev->lldi.vr->stag.size >> 5)); 166 } 167 168 #define C4IW_WR_TO (30*HZ) 169 170 struct c4iw_wr_wait { 171 struct completion completion; 172 int ret; 173 }; 174 175 static inline void c4iw_init_wr_wait(struct c4iw_wr_wait *wr_waitp) 176 { 177 wr_waitp->ret = 0; 178 init_completion(&wr_waitp->completion); 179 } 180 181 static inline void c4iw_wake_up(struct c4iw_wr_wait *wr_waitp, int ret) 182 { 183 wr_waitp->ret = ret; 184 complete(&wr_waitp->completion); 185 } 186 187 static inline int c4iw_wait_for_reply(struct c4iw_rdev *rdev, 188 struct c4iw_wr_wait *wr_waitp, 189 u32 hwtid, u32 qpid, 190 const char *func) 191 { 192 unsigned to = C4IW_WR_TO; 193 int ret; 194 195 do { 196 ret = wait_for_completion_timeout(&wr_waitp->completion, to); 197 if (!ret) { 198 printk(KERN_ERR MOD "%s - Device %s not responding - " 199 "tid %u qpid %u\n", func, 200 pci_name(rdev->lldi.pdev), hwtid, qpid); 201 if (c4iw_fatal_error(rdev)) { 202 wr_waitp->ret = -EIO; 203 break; 204 } 205 to = to << 2; 206 } 207 } while (!ret); 208 if (wr_waitp->ret) 209 PDBG("%s: FW reply %d tid %u qpid %u\n", 210 pci_name(rdev->lldi.pdev), wr_waitp->ret, hwtid, qpid); 211 return wr_waitp->ret; 212 } 213 214 enum db_state { 215 NORMAL = 0, 216 FLOW_CONTROL = 1, 217 RECOVERY = 2, 218 STOPPED = 3 219 }; 220 221 struct c4iw_dev { 222 struct ib_device ibdev; 223 struct c4iw_rdev rdev; 224 u32 device_cap_flags; 225 struct idr cqidr; 226 struct idr qpidr; 227 struct idr mmidr; 228 spinlock_t lock; 229 struct mutex db_mutex; 230 struct dentry *debugfs_root; 231 enum db_state db_state; 232 struct idr hwtid_idr; 233 struct idr atid_idr; 234 struct idr stid_idr; 235 struct list_head db_fc_list; 236 }; 237 238 static inline struct c4iw_dev *to_c4iw_dev(struct ib_device *ibdev) 239 { 240 return container_of(ibdev, struct c4iw_dev, ibdev); 241 } 242 243 static inline struct c4iw_dev *rdev_to_c4iw_dev(struct c4iw_rdev *rdev) 244 { 245 return container_of(rdev, struct c4iw_dev, rdev); 246 } 247 248 static inline struct c4iw_cq *get_chp(struct c4iw_dev *rhp, u32 cqid) 249 { 250 return idr_find(&rhp->cqidr, cqid); 251 } 252 253 static inline struct c4iw_qp *get_qhp(struct c4iw_dev *rhp, u32 qpid) 254 { 255 return idr_find(&rhp->qpidr, qpid); 256 } 257 258 static inline struct c4iw_mr *get_mhp(struct c4iw_dev *rhp, u32 mmid) 259 { 260 return idr_find(&rhp->mmidr, mmid); 261 } 262 263 static inline int _insert_handle(struct c4iw_dev *rhp, struct idr *idr, 264 void *handle, u32 id, int lock) 265 { 266 int ret; 267 268 if (lock) { 269 idr_preload(GFP_KERNEL); 270 spin_lock_irq(&rhp->lock); 271 } 272 273 ret = idr_alloc(idr, handle, id, id + 1, GFP_ATOMIC); 274 275 if (lock) { 276 spin_unlock_irq(&rhp->lock); 277 idr_preload_end(); 278 } 279 280 BUG_ON(ret == -ENOSPC); 281 return ret < 0 ? ret : 0; 282 } 283 284 static inline int insert_handle(struct c4iw_dev *rhp, struct idr *idr, 285 void *handle, u32 id) 286 { 287 return _insert_handle(rhp, idr, handle, id, 1); 288 } 289 290 static inline int insert_handle_nolock(struct c4iw_dev *rhp, struct idr *idr, 291 void *handle, u32 id) 292 { 293 return _insert_handle(rhp, idr, handle, id, 0); 294 } 295 296 static inline void _remove_handle(struct c4iw_dev *rhp, struct idr *idr, 297 u32 id, int lock) 298 { 299 if (lock) 300 spin_lock_irq(&rhp->lock); 301 idr_remove(idr, id); 302 if (lock) 303 spin_unlock_irq(&rhp->lock); 304 } 305 306 static inline void remove_handle(struct c4iw_dev *rhp, struct idr *idr, u32 id) 307 { 308 _remove_handle(rhp, idr, id, 1); 309 } 310 311 static inline void remove_handle_nolock(struct c4iw_dev *rhp, 312 struct idr *idr, u32 id) 313 { 314 _remove_handle(rhp, idr, id, 0); 315 } 316 317 struct c4iw_pd { 318 struct ib_pd ibpd; 319 u32 pdid; 320 struct c4iw_dev *rhp; 321 }; 322 323 static inline struct c4iw_pd *to_c4iw_pd(struct ib_pd *ibpd) 324 { 325 return container_of(ibpd, struct c4iw_pd, ibpd); 326 } 327 328 struct tpt_attributes { 329 u64 len; 330 u64 va_fbo; 331 enum fw_ri_mem_perms perms; 332 u32 stag; 333 u32 pdid; 334 u32 qpid; 335 u32 pbl_addr; 336 u32 pbl_size; 337 u32 state:1; 338 u32 type:2; 339 u32 rsvd:1; 340 u32 remote_invaliate_disable:1; 341 u32 zbva:1; 342 u32 mw_bind_enable:1; 343 u32 page_size:5; 344 }; 345 346 struct c4iw_mr { 347 struct ib_mr ibmr; 348 struct ib_umem *umem; 349 struct c4iw_dev *rhp; 350 u64 kva; 351 struct tpt_attributes attr; 352 }; 353 354 static inline struct c4iw_mr *to_c4iw_mr(struct ib_mr *ibmr) 355 { 356 return container_of(ibmr, struct c4iw_mr, ibmr); 357 } 358 359 struct c4iw_mw { 360 struct ib_mw ibmw; 361 struct c4iw_dev *rhp; 362 u64 kva; 363 struct tpt_attributes attr; 364 }; 365 366 static inline struct c4iw_mw *to_c4iw_mw(struct ib_mw *ibmw) 367 { 368 return container_of(ibmw, struct c4iw_mw, ibmw); 369 } 370 371 struct c4iw_fr_page_list { 372 struct ib_fast_reg_page_list ibpl; 373 DEFINE_DMA_UNMAP_ADDR(mapping); 374 dma_addr_t dma_addr; 375 struct c4iw_dev *dev; 376 int pll_len; 377 }; 378 379 static inline struct c4iw_fr_page_list *to_c4iw_fr_page_list( 380 struct ib_fast_reg_page_list *ibpl) 381 { 382 return container_of(ibpl, struct c4iw_fr_page_list, ibpl); 383 } 384 385 struct c4iw_cq { 386 struct ib_cq ibcq; 387 struct c4iw_dev *rhp; 388 struct t4_cq cq; 389 spinlock_t lock; 390 spinlock_t comp_handler_lock; 391 atomic_t refcnt; 392 wait_queue_head_t wait; 393 }; 394 395 static inline struct c4iw_cq *to_c4iw_cq(struct ib_cq *ibcq) 396 { 397 return container_of(ibcq, struct c4iw_cq, ibcq); 398 } 399 400 struct c4iw_mpa_attributes { 401 u8 initiator; 402 u8 recv_marker_enabled; 403 u8 xmit_marker_enabled; 404 u8 crc_enabled; 405 u8 enhanced_rdma_conn; 406 u8 version; 407 u8 p2p_type; 408 }; 409 410 struct c4iw_qp_attributes { 411 u32 scq; 412 u32 rcq; 413 u32 sq_num_entries; 414 u32 rq_num_entries; 415 u32 sq_max_sges; 416 u32 sq_max_sges_rdma_write; 417 u32 rq_max_sges; 418 u32 state; 419 u8 enable_rdma_read; 420 u8 enable_rdma_write; 421 u8 enable_bind; 422 u8 enable_mmid0_fastreg; 423 u32 max_ord; 424 u32 max_ird; 425 u32 pd; 426 u32 next_state; 427 char terminate_buffer[52]; 428 u32 terminate_msg_len; 429 u8 is_terminate_local; 430 struct c4iw_mpa_attributes mpa_attr; 431 struct c4iw_ep *llp_stream_handle; 432 u8 layer_etype; 433 u8 ecode; 434 u16 sq_db_inc; 435 u16 rq_db_inc; 436 }; 437 438 struct c4iw_qp { 439 struct ib_qp ibqp; 440 struct list_head db_fc_entry; 441 struct c4iw_dev *rhp; 442 struct c4iw_ep *ep; 443 struct c4iw_qp_attributes attr; 444 struct t4_wq wq; 445 spinlock_t lock; 446 struct mutex mutex; 447 atomic_t refcnt; 448 wait_queue_head_t wait; 449 struct timer_list timer; 450 int sq_sig_all; 451 }; 452 453 static inline struct c4iw_qp *to_c4iw_qp(struct ib_qp *ibqp) 454 { 455 return container_of(ibqp, struct c4iw_qp, ibqp); 456 } 457 458 struct c4iw_ucontext { 459 struct ib_ucontext ibucontext; 460 struct c4iw_dev_ucontext uctx; 461 u32 key; 462 spinlock_t mmap_lock; 463 struct list_head mmaps; 464 }; 465 466 static inline struct c4iw_ucontext *to_c4iw_ucontext(struct ib_ucontext *c) 467 { 468 return container_of(c, struct c4iw_ucontext, ibucontext); 469 } 470 471 struct c4iw_mm_entry { 472 struct list_head entry; 473 u64 addr; 474 u32 key; 475 unsigned len; 476 }; 477 478 static inline struct c4iw_mm_entry *remove_mmap(struct c4iw_ucontext *ucontext, 479 u32 key, unsigned len) 480 { 481 struct list_head *pos, *nxt; 482 struct c4iw_mm_entry *mm; 483 484 spin_lock(&ucontext->mmap_lock); 485 list_for_each_safe(pos, nxt, &ucontext->mmaps) { 486 487 mm = list_entry(pos, struct c4iw_mm_entry, entry); 488 if (mm->key == key && mm->len == len) { 489 list_del_init(&mm->entry); 490 spin_unlock(&ucontext->mmap_lock); 491 PDBG("%s key 0x%x addr 0x%llx len %d\n", __func__, 492 key, (unsigned long long) mm->addr, mm->len); 493 return mm; 494 } 495 } 496 spin_unlock(&ucontext->mmap_lock); 497 return NULL; 498 } 499 500 static inline void insert_mmap(struct c4iw_ucontext *ucontext, 501 struct c4iw_mm_entry *mm) 502 { 503 spin_lock(&ucontext->mmap_lock); 504 PDBG("%s key 0x%x addr 0x%llx len %d\n", __func__, 505 mm->key, (unsigned long long) mm->addr, mm->len); 506 list_add_tail(&mm->entry, &ucontext->mmaps); 507 spin_unlock(&ucontext->mmap_lock); 508 } 509 510 enum c4iw_qp_attr_mask { 511 C4IW_QP_ATTR_NEXT_STATE = 1 << 0, 512 C4IW_QP_ATTR_SQ_DB = 1<<1, 513 C4IW_QP_ATTR_RQ_DB = 1<<2, 514 C4IW_QP_ATTR_ENABLE_RDMA_READ = 1 << 7, 515 C4IW_QP_ATTR_ENABLE_RDMA_WRITE = 1 << 8, 516 C4IW_QP_ATTR_ENABLE_RDMA_BIND = 1 << 9, 517 C4IW_QP_ATTR_MAX_ORD = 1 << 11, 518 C4IW_QP_ATTR_MAX_IRD = 1 << 12, 519 C4IW_QP_ATTR_LLP_STREAM_HANDLE = 1 << 22, 520 C4IW_QP_ATTR_STREAM_MSG_BUFFER = 1 << 23, 521 C4IW_QP_ATTR_MPA_ATTR = 1 << 24, 522 C4IW_QP_ATTR_QP_CONTEXT_ACTIVATE = 1 << 25, 523 C4IW_QP_ATTR_VALID_MODIFY = (C4IW_QP_ATTR_ENABLE_RDMA_READ | 524 C4IW_QP_ATTR_ENABLE_RDMA_WRITE | 525 C4IW_QP_ATTR_MAX_ORD | 526 C4IW_QP_ATTR_MAX_IRD | 527 C4IW_QP_ATTR_LLP_STREAM_HANDLE | 528 C4IW_QP_ATTR_STREAM_MSG_BUFFER | 529 C4IW_QP_ATTR_MPA_ATTR | 530 C4IW_QP_ATTR_QP_CONTEXT_ACTIVATE) 531 }; 532 533 int c4iw_modify_qp(struct c4iw_dev *rhp, 534 struct c4iw_qp *qhp, 535 enum c4iw_qp_attr_mask mask, 536 struct c4iw_qp_attributes *attrs, 537 int internal); 538 539 enum c4iw_qp_state { 540 C4IW_QP_STATE_IDLE, 541 C4IW_QP_STATE_RTS, 542 C4IW_QP_STATE_ERROR, 543 C4IW_QP_STATE_TERMINATE, 544 C4IW_QP_STATE_CLOSING, 545 C4IW_QP_STATE_TOT 546 }; 547 548 static inline int c4iw_convert_state(enum ib_qp_state ib_state) 549 { 550 switch (ib_state) { 551 case IB_QPS_RESET: 552 case IB_QPS_INIT: 553 return C4IW_QP_STATE_IDLE; 554 case IB_QPS_RTS: 555 return C4IW_QP_STATE_RTS; 556 case IB_QPS_SQD: 557 return C4IW_QP_STATE_CLOSING; 558 case IB_QPS_SQE: 559 return C4IW_QP_STATE_TERMINATE; 560 case IB_QPS_ERR: 561 return C4IW_QP_STATE_ERROR; 562 default: 563 return -1; 564 } 565 } 566 567 static inline int to_ib_qp_state(int c4iw_qp_state) 568 { 569 switch (c4iw_qp_state) { 570 case C4IW_QP_STATE_IDLE: 571 return IB_QPS_INIT; 572 case C4IW_QP_STATE_RTS: 573 return IB_QPS_RTS; 574 case C4IW_QP_STATE_CLOSING: 575 return IB_QPS_SQD; 576 case C4IW_QP_STATE_TERMINATE: 577 return IB_QPS_SQE; 578 case C4IW_QP_STATE_ERROR: 579 return IB_QPS_ERR; 580 } 581 return IB_QPS_ERR; 582 } 583 584 static inline u32 c4iw_ib_to_tpt_access(int a) 585 { 586 return (a & IB_ACCESS_REMOTE_WRITE ? FW_RI_MEM_ACCESS_REM_WRITE : 0) | 587 (a & IB_ACCESS_REMOTE_READ ? FW_RI_MEM_ACCESS_REM_READ : 0) | 588 (a & IB_ACCESS_LOCAL_WRITE ? FW_RI_MEM_ACCESS_LOCAL_WRITE : 0) | 589 FW_RI_MEM_ACCESS_LOCAL_READ; 590 } 591 592 static inline u32 c4iw_ib_to_tpt_bind_access(int acc) 593 { 594 return (acc & IB_ACCESS_REMOTE_WRITE ? FW_RI_MEM_ACCESS_REM_WRITE : 0) | 595 (acc & IB_ACCESS_REMOTE_READ ? FW_RI_MEM_ACCESS_REM_READ : 0); 596 } 597 598 enum c4iw_mmid_state { 599 C4IW_STAG_STATE_VALID, 600 C4IW_STAG_STATE_INVALID 601 }; 602 603 #define C4IW_NODE_DESC "cxgb4 Chelsio Communications" 604 605 #define MPA_KEY_REQ "MPA ID Req Frame" 606 #define MPA_KEY_REP "MPA ID Rep Frame" 607 608 #define MPA_MAX_PRIVATE_DATA 256 609 #define MPA_ENHANCED_RDMA_CONN 0x10 610 #define MPA_REJECT 0x20 611 #define MPA_CRC 0x40 612 #define MPA_MARKERS 0x80 613 #define MPA_FLAGS_MASK 0xE0 614 615 #define MPA_V2_PEER2PEER_MODEL 0x8000 616 #define MPA_V2_ZERO_LEN_FPDU_RTR 0x4000 617 #define MPA_V2_RDMA_WRITE_RTR 0x8000 618 #define MPA_V2_RDMA_READ_RTR 0x4000 619 #define MPA_V2_IRD_ORD_MASK 0x3FFF 620 621 #define c4iw_put_ep(ep) { \ 622 PDBG("put_ep (via %s:%u) ep %p refcnt %d\n", __func__, __LINE__, \ 623 ep, atomic_read(&((ep)->kref.refcount))); \ 624 WARN_ON(atomic_read(&((ep)->kref.refcount)) < 1); \ 625 kref_put(&((ep)->kref), _c4iw_free_ep); \ 626 } 627 628 #define c4iw_get_ep(ep) { \ 629 PDBG("get_ep (via %s:%u) ep %p, refcnt %d\n", __func__, __LINE__, \ 630 ep, atomic_read(&((ep)->kref.refcount))); \ 631 kref_get(&((ep)->kref)); \ 632 } 633 void _c4iw_free_ep(struct kref *kref); 634 635 struct mpa_message { 636 u8 key[16]; 637 u8 flags; 638 u8 revision; 639 __be16 private_data_size; 640 u8 private_data[0]; 641 }; 642 643 struct mpa_v2_conn_params { 644 __be16 ird; 645 __be16 ord; 646 }; 647 648 struct terminate_message { 649 u8 layer_etype; 650 u8 ecode; 651 __be16 hdrct_rsvd; 652 u8 len_hdrs[0]; 653 }; 654 655 #define TERM_MAX_LENGTH (sizeof(struct terminate_message) + 2 + 18 + 28) 656 657 enum c4iw_layers_types { 658 LAYER_RDMAP = 0x00, 659 LAYER_DDP = 0x10, 660 LAYER_MPA = 0x20, 661 RDMAP_LOCAL_CATA = 0x00, 662 RDMAP_REMOTE_PROT = 0x01, 663 RDMAP_REMOTE_OP = 0x02, 664 DDP_LOCAL_CATA = 0x00, 665 DDP_TAGGED_ERR = 0x01, 666 DDP_UNTAGGED_ERR = 0x02, 667 DDP_LLP = 0x03 668 }; 669 670 enum c4iw_rdma_ecodes { 671 RDMAP_INV_STAG = 0x00, 672 RDMAP_BASE_BOUNDS = 0x01, 673 RDMAP_ACC_VIOL = 0x02, 674 RDMAP_STAG_NOT_ASSOC = 0x03, 675 RDMAP_TO_WRAP = 0x04, 676 RDMAP_INV_VERS = 0x05, 677 RDMAP_INV_OPCODE = 0x06, 678 RDMAP_STREAM_CATA = 0x07, 679 RDMAP_GLOBAL_CATA = 0x08, 680 RDMAP_CANT_INV_STAG = 0x09, 681 RDMAP_UNSPECIFIED = 0xff 682 }; 683 684 enum c4iw_ddp_ecodes { 685 DDPT_INV_STAG = 0x00, 686 DDPT_BASE_BOUNDS = 0x01, 687 DDPT_STAG_NOT_ASSOC = 0x02, 688 DDPT_TO_WRAP = 0x03, 689 DDPT_INV_VERS = 0x04, 690 DDPU_INV_QN = 0x01, 691 DDPU_INV_MSN_NOBUF = 0x02, 692 DDPU_INV_MSN_RANGE = 0x03, 693 DDPU_INV_MO = 0x04, 694 DDPU_MSG_TOOBIG = 0x05, 695 DDPU_INV_VERS = 0x06 696 }; 697 698 enum c4iw_mpa_ecodes { 699 MPA_CRC_ERR = 0x02, 700 MPA_MARKER_ERR = 0x03, 701 MPA_LOCAL_CATA = 0x05, 702 MPA_INSUFF_IRD = 0x06, 703 MPA_NOMATCH_RTR = 0x07, 704 }; 705 706 enum c4iw_ep_state { 707 IDLE = 0, 708 LISTEN, 709 CONNECTING, 710 MPA_REQ_WAIT, 711 MPA_REQ_SENT, 712 MPA_REQ_RCVD, 713 MPA_REP_SENT, 714 FPDU_MODE, 715 ABORTING, 716 CLOSING, 717 MORIBUND, 718 DEAD, 719 }; 720 721 enum c4iw_ep_flags { 722 PEER_ABORT_IN_PROGRESS = 0, 723 ABORT_REQ_IN_PROGRESS = 1, 724 RELEASE_RESOURCES = 2, 725 CLOSE_SENT = 3, 726 TIMEOUT = 4, 727 QP_REFERENCED = 5, 728 }; 729 730 enum c4iw_ep_history { 731 ACT_OPEN_REQ = 0, 732 ACT_OFLD_CONN = 1, 733 ACT_OPEN_RPL = 2, 734 ACT_ESTAB = 3, 735 PASS_ACCEPT_REQ = 4, 736 PASS_ESTAB = 5, 737 ABORT_UPCALL = 6, 738 ESTAB_UPCALL = 7, 739 CLOSE_UPCALL = 8, 740 ULP_ACCEPT = 9, 741 ULP_REJECT = 10, 742 TIMEDOUT = 11, 743 PEER_ABORT = 12, 744 PEER_CLOSE = 13, 745 CONNREQ_UPCALL = 14, 746 ABORT_CONN = 15, 747 DISCONN_UPCALL = 16, 748 EP_DISC_CLOSE = 17, 749 EP_DISC_ABORT = 18, 750 CONN_RPL_UPCALL = 19, 751 ACT_RETRY_NOMEM = 20, 752 ACT_RETRY_INUSE = 21 753 }; 754 755 struct c4iw_ep_common { 756 struct iw_cm_id *cm_id; 757 struct c4iw_qp *qp; 758 struct c4iw_dev *dev; 759 enum c4iw_ep_state state; 760 struct kref kref; 761 struct mutex mutex; 762 struct sockaddr_storage local_addr; 763 struct sockaddr_storage remote_addr; 764 struct c4iw_wr_wait wr_wait; 765 unsigned long flags; 766 unsigned long history; 767 }; 768 769 struct c4iw_listen_ep { 770 struct c4iw_ep_common com; 771 unsigned int stid; 772 int backlog; 773 }; 774 775 struct c4iw_ep { 776 struct c4iw_ep_common com; 777 struct c4iw_ep *parent_ep; 778 struct timer_list timer; 779 struct list_head entry; 780 unsigned int atid; 781 u32 hwtid; 782 u32 snd_seq; 783 u32 rcv_seq; 784 struct l2t_entry *l2t; 785 struct dst_entry *dst; 786 struct sk_buff *mpa_skb; 787 struct c4iw_mpa_attributes mpa_attr; 788 u8 mpa_pkt[sizeof(struct mpa_message) + MPA_MAX_PRIVATE_DATA]; 789 unsigned int mpa_pkt_len; 790 u32 ird; 791 u32 ord; 792 u32 smac_idx; 793 u32 tx_chan; 794 u32 mtu; 795 u16 mss; 796 u16 emss; 797 u16 plen; 798 u16 rss_qid; 799 u16 txq_idx; 800 u16 ctrlq_idx; 801 u8 tos; 802 u8 retry_with_mpa_v1; 803 u8 tried_with_mpa_v1; 804 unsigned int retry_count; 805 }; 806 807 static inline struct c4iw_ep *to_ep(struct iw_cm_id *cm_id) 808 { 809 return cm_id->provider_data; 810 } 811 812 static inline struct c4iw_listen_ep *to_listen_ep(struct iw_cm_id *cm_id) 813 { 814 return cm_id->provider_data; 815 } 816 817 static inline int compute_wscale(int win) 818 { 819 int wscale = 0; 820 821 while (wscale < 14 && (65535<<wscale) < win) 822 wscale++; 823 return wscale; 824 } 825 826 static inline int ocqp_supported(const struct cxgb4_lld_info *infop) 827 { 828 #if defined(__i386__) || defined(__x86_64__) || defined(CONFIG_PPC64) 829 return infop->vr->ocq.size > 0; 830 #else 831 return 0; 832 #endif 833 } 834 835 u32 c4iw_id_alloc(struct c4iw_id_table *alloc); 836 void c4iw_id_free(struct c4iw_id_table *alloc, u32 obj); 837 int c4iw_id_table_alloc(struct c4iw_id_table *alloc, u32 start, u32 num, 838 u32 reserved, u32 flags); 839 void c4iw_id_table_free(struct c4iw_id_table *alloc); 840 841 typedef int (*c4iw_handler_func)(struct c4iw_dev *dev, struct sk_buff *skb); 842 843 int c4iw_ep_redirect(void *ctx, struct dst_entry *old, struct dst_entry *new, 844 struct l2t_entry *l2t); 845 void c4iw_put_qpid(struct c4iw_rdev *rdev, u32 qpid, 846 struct c4iw_dev_ucontext *uctx); 847 u32 c4iw_get_resource(struct c4iw_id_table *id_table); 848 void c4iw_put_resource(struct c4iw_id_table *id_table, u32 entry); 849 int c4iw_init_resource(struct c4iw_rdev *rdev, u32 nr_tpt, u32 nr_pdid); 850 int c4iw_init_ctrl_qp(struct c4iw_rdev *rdev); 851 int c4iw_pblpool_create(struct c4iw_rdev *rdev); 852 int c4iw_rqtpool_create(struct c4iw_rdev *rdev); 853 int c4iw_ocqp_pool_create(struct c4iw_rdev *rdev); 854 void c4iw_pblpool_destroy(struct c4iw_rdev *rdev); 855 void c4iw_rqtpool_destroy(struct c4iw_rdev *rdev); 856 void c4iw_ocqp_pool_destroy(struct c4iw_rdev *rdev); 857 void c4iw_destroy_resource(struct c4iw_resource *rscp); 858 int c4iw_destroy_ctrl_qp(struct c4iw_rdev *rdev); 859 int c4iw_register_device(struct c4iw_dev *dev); 860 void c4iw_unregister_device(struct c4iw_dev *dev); 861 int __init c4iw_cm_init(void); 862 void __exit c4iw_cm_term(void); 863 void c4iw_release_dev_ucontext(struct c4iw_rdev *rdev, 864 struct c4iw_dev_ucontext *uctx); 865 void c4iw_init_dev_ucontext(struct c4iw_rdev *rdev, 866 struct c4iw_dev_ucontext *uctx); 867 int c4iw_poll_cq(struct ib_cq *ibcq, int num_entries, struct ib_wc *wc); 868 int c4iw_post_send(struct ib_qp *ibqp, struct ib_send_wr *wr, 869 struct ib_send_wr **bad_wr); 870 int c4iw_post_receive(struct ib_qp *ibqp, struct ib_recv_wr *wr, 871 struct ib_recv_wr **bad_wr); 872 int c4iw_bind_mw(struct ib_qp *qp, struct ib_mw *mw, 873 struct ib_mw_bind *mw_bind); 874 int c4iw_connect(struct iw_cm_id *cm_id, struct iw_cm_conn_param *conn_param); 875 int c4iw_create_listen(struct iw_cm_id *cm_id, int backlog); 876 int c4iw_destroy_listen(struct iw_cm_id *cm_id); 877 int c4iw_accept_cr(struct iw_cm_id *cm_id, struct iw_cm_conn_param *conn_param); 878 int c4iw_reject_cr(struct iw_cm_id *cm_id, const void *pdata, u8 pdata_len); 879 void c4iw_qp_add_ref(struct ib_qp *qp); 880 void c4iw_qp_rem_ref(struct ib_qp *qp); 881 void c4iw_free_fastreg_pbl(struct ib_fast_reg_page_list *page_list); 882 struct ib_fast_reg_page_list *c4iw_alloc_fastreg_pbl( 883 struct ib_device *device, 884 int page_list_len); 885 struct ib_mr *c4iw_alloc_fast_reg_mr(struct ib_pd *pd, int pbl_depth); 886 int c4iw_dealloc_mw(struct ib_mw *mw); 887 struct ib_mw *c4iw_alloc_mw(struct ib_pd *pd, enum ib_mw_type type); 888 struct ib_mr *c4iw_reg_user_mr(struct ib_pd *pd, u64 start, 889 u64 length, u64 virt, int acc, 890 struct ib_udata *udata); 891 struct ib_mr *c4iw_get_dma_mr(struct ib_pd *pd, int acc); 892 struct ib_mr *c4iw_register_phys_mem(struct ib_pd *pd, 893 struct ib_phys_buf *buffer_list, 894 int num_phys_buf, 895 int acc, 896 u64 *iova_start); 897 int c4iw_reregister_phys_mem(struct ib_mr *mr, 898 int mr_rereg_mask, 899 struct ib_pd *pd, 900 struct ib_phys_buf *buffer_list, 901 int num_phys_buf, 902 int acc, u64 *iova_start); 903 int c4iw_dereg_mr(struct ib_mr *ib_mr); 904 int c4iw_destroy_cq(struct ib_cq *ib_cq); 905 struct ib_cq *c4iw_create_cq(struct ib_device *ibdev, int entries, 906 int vector, 907 struct ib_ucontext *ib_context, 908 struct ib_udata *udata); 909 int c4iw_resize_cq(struct ib_cq *cq, int cqe, struct ib_udata *udata); 910 int c4iw_arm_cq(struct ib_cq *ibcq, enum ib_cq_notify_flags flags); 911 int c4iw_destroy_qp(struct ib_qp *ib_qp); 912 struct ib_qp *c4iw_create_qp(struct ib_pd *pd, 913 struct ib_qp_init_attr *attrs, 914 struct ib_udata *udata); 915 int c4iw_ib_modify_qp(struct ib_qp *ibqp, struct ib_qp_attr *attr, 916 int attr_mask, struct ib_udata *udata); 917 int c4iw_ib_query_qp(struct ib_qp *ibqp, struct ib_qp_attr *attr, 918 int attr_mask, struct ib_qp_init_attr *init_attr); 919 struct ib_qp *c4iw_get_qp(struct ib_device *dev, int qpn); 920 u32 c4iw_rqtpool_alloc(struct c4iw_rdev *rdev, int size); 921 void c4iw_rqtpool_free(struct c4iw_rdev *rdev, u32 addr, int size); 922 u32 c4iw_pblpool_alloc(struct c4iw_rdev *rdev, int size); 923 void c4iw_pblpool_free(struct c4iw_rdev *rdev, u32 addr, int size); 924 u32 c4iw_ocqp_pool_alloc(struct c4iw_rdev *rdev, int size); 925 void c4iw_ocqp_pool_free(struct c4iw_rdev *rdev, u32 addr, int size); 926 int c4iw_ofld_send(struct c4iw_rdev *rdev, struct sk_buff *skb); 927 void c4iw_flush_hw_cq(struct c4iw_cq *chp); 928 void c4iw_count_rcqes(struct t4_cq *cq, struct t4_wq *wq, int *count); 929 int c4iw_ep_disconnect(struct c4iw_ep *ep, int abrupt, gfp_t gfp); 930 int c4iw_flush_rq(struct t4_wq *wq, struct t4_cq *cq, int count); 931 int c4iw_flush_sq(struct c4iw_qp *qhp); 932 int c4iw_ev_handler(struct c4iw_dev *rnicp, u32 qid); 933 u16 c4iw_rqes_posted(struct c4iw_qp *qhp); 934 int c4iw_post_terminate(struct c4iw_qp *qhp, struct t4_cqe *err_cqe); 935 u32 c4iw_get_cqid(struct c4iw_rdev *rdev, struct c4iw_dev_ucontext *uctx); 936 void c4iw_put_cqid(struct c4iw_rdev *rdev, u32 qid, 937 struct c4iw_dev_ucontext *uctx); 938 u32 c4iw_get_qpid(struct c4iw_rdev *rdev, struct c4iw_dev_ucontext *uctx); 939 void c4iw_put_qpid(struct c4iw_rdev *rdev, u32 qid, 940 struct c4iw_dev_ucontext *uctx); 941 void c4iw_ev_dispatch(struct c4iw_dev *dev, struct t4_cqe *err_cqe); 942 943 extern struct cxgb4_client t4c_client; 944 extern c4iw_handler_func c4iw_handlers[NUM_CPL_CMDS]; 945 extern int c4iw_max_read_depth; 946 extern int db_fc_threshold; 947 extern int db_coalescing_threshold; 948 extern int use_dsgl; 949 950 951 #endif 952