1 /* 2 * Copyright (c) 2009-2010 Chelsio, Inc. All rights reserved. 3 * 4 * This software is available to you under a choice of one of two 5 * licenses. You may choose to be licensed under the terms of the GNU 6 * General Public License (GPL) Version 2, available from the file 7 * COPYING in the main directory of this source tree, or the 8 * OpenIB.org BSD license below: 9 * 10 * Redistribution and use in source and binary forms, with or 11 * without modification, are permitted provided that the following 12 * conditions are met: 13 * 14 * - Redistributions of source code must retain the above 15 * copyright notice, this list of conditions and the following 16 * disclaimer. 17 * - Redistributions in binary form must reproduce the above 18 * copyright notice, this list of conditions and the following 19 * disclaimer in the documentation and/or other materials 20 * provided with the distribution. 21 * 22 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, 23 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF 24 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND 25 * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS 26 * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN 27 * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN 28 * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE 29 * SOFTWARE. 30 */ 31 #ifndef __IW_CXGB4_H__ 32 #define __IW_CXGB4_H__ 33 34 #include <linux/mutex.h> 35 #include <linux/list.h> 36 #include <linux/spinlock.h> 37 #include <linux/idr.h> 38 #include <linux/completion.h> 39 #include <linux/netdevice.h> 40 #include <linux/sched.h> 41 #include <linux/pci.h> 42 #include <linux/dma-mapping.h> 43 #include <linux/inet.h> 44 #include <linux/wait.h> 45 #include <linux/kref.h> 46 #include <linux/timer.h> 47 #include <linux/io.h> 48 #include <linux/kfifo.h> 49 50 #include <asm/byteorder.h> 51 52 #include <net/net_namespace.h> 53 54 #include <rdma/ib_verbs.h> 55 #include <rdma/iw_cm.h> 56 57 #include "cxgb4.h" 58 #include "cxgb4_uld.h" 59 #include "l2t.h" 60 #include "user.h" 61 62 #define DRV_NAME "iw_cxgb4" 63 #define MOD DRV_NAME ":" 64 65 extern int c4iw_debug; 66 #define PDBG(fmt, args...) \ 67 do { \ 68 if (c4iw_debug) \ 69 printk(MOD fmt, ## args); \ 70 } while (0) 71 72 #include "t4.h" 73 74 #define PBL_OFF(rdev_p, a) ((a) - (rdev_p)->lldi.vr->pbl.start) 75 #define RQT_OFF(rdev_p, a) ((a) - (rdev_p)->lldi.vr->rq.start) 76 77 static inline void *cplhdr(struct sk_buff *skb) 78 { 79 return skb->data; 80 } 81 82 struct c4iw_resource { 83 struct kfifo tpt_fifo; 84 spinlock_t tpt_fifo_lock; 85 struct kfifo qid_fifo; 86 spinlock_t qid_fifo_lock; 87 struct kfifo pdid_fifo; 88 spinlock_t pdid_fifo_lock; 89 }; 90 91 struct c4iw_qid_list { 92 struct list_head entry; 93 u32 qid; 94 }; 95 96 struct c4iw_dev_ucontext { 97 struct list_head qpids; 98 struct list_head cqids; 99 struct mutex lock; 100 }; 101 102 enum c4iw_rdev_flags { 103 T4_FATAL_ERROR = (1<<0), 104 }; 105 106 struct c4iw_rdev { 107 struct c4iw_resource resource; 108 unsigned long qpshift; 109 u32 qpmask; 110 unsigned long cqshift; 111 u32 cqmask; 112 struct c4iw_dev_ucontext uctx; 113 struct gen_pool *pbl_pool; 114 struct gen_pool *rqt_pool; 115 struct gen_pool *ocqp_pool; 116 u32 flags; 117 struct cxgb4_lld_info lldi; 118 unsigned long oc_mw_pa; 119 void __iomem *oc_mw_kva; 120 }; 121 122 static inline int c4iw_fatal_error(struct c4iw_rdev *rdev) 123 { 124 return rdev->flags & T4_FATAL_ERROR; 125 } 126 127 static inline int c4iw_num_stags(struct c4iw_rdev *rdev) 128 { 129 return min((int)T4_MAX_NUM_STAG, (int)(rdev->lldi.vr->stag.size >> 5)); 130 } 131 132 #define C4IW_WR_TO (10*HZ) 133 134 struct c4iw_wr_wait { 135 struct completion completion; 136 int ret; 137 }; 138 139 static inline void c4iw_init_wr_wait(struct c4iw_wr_wait *wr_waitp) 140 { 141 wr_waitp->ret = 0; 142 init_completion(&wr_waitp->completion); 143 } 144 145 static inline void c4iw_wake_up(struct c4iw_wr_wait *wr_waitp, int ret) 146 { 147 wr_waitp->ret = ret; 148 complete(&wr_waitp->completion); 149 } 150 151 static inline int c4iw_wait_for_reply(struct c4iw_rdev *rdev, 152 struct c4iw_wr_wait *wr_waitp, 153 u32 hwtid, u32 qpid, 154 const char *func) 155 { 156 unsigned to = C4IW_WR_TO; 157 int ret; 158 159 do { 160 ret = wait_for_completion_timeout(&wr_waitp->completion, to); 161 if (!ret) { 162 printk(KERN_ERR MOD "%s - Device %s not responding - " 163 "tid %u qpid %u\n", func, 164 pci_name(rdev->lldi.pdev), hwtid, qpid); 165 if (c4iw_fatal_error(rdev)) { 166 wr_waitp->ret = -EIO; 167 break; 168 } 169 to = to << 2; 170 } 171 } while (!ret); 172 if (wr_waitp->ret) 173 PDBG("%s: FW reply %d tid %u qpid %u\n", 174 pci_name(rdev->lldi.pdev), wr_waitp->ret, hwtid, qpid); 175 return wr_waitp->ret; 176 } 177 178 struct c4iw_dev { 179 struct ib_device ibdev; 180 struct c4iw_rdev rdev; 181 u32 device_cap_flags; 182 struct idr cqidr; 183 struct idr qpidr; 184 struct idr mmidr; 185 spinlock_t lock; 186 struct dentry *debugfs_root; 187 }; 188 189 static inline struct c4iw_dev *to_c4iw_dev(struct ib_device *ibdev) 190 { 191 return container_of(ibdev, struct c4iw_dev, ibdev); 192 } 193 194 static inline struct c4iw_dev *rdev_to_c4iw_dev(struct c4iw_rdev *rdev) 195 { 196 return container_of(rdev, struct c4iw_dev, rdev); 197 } 198 199 static inline struct c4iw_cq *get_chp(struct c4iw_dev *rhp, u32 cqid) 200 { 201 return idr_find(&rhp->cqidr, cqid); 202 } 203 204 static inline struct c4iw_qp *get_qhp(struct c4iw_dev *rhp, u32 qpid) 205 { 206 return idr_find(&rhp->qpidr, qpid); 207 } 208 209 static inline struct c4iw_mr *get_mhp(struct c4iw_dev *rhp, u32 mmid) 210 { 211 return idr_find(&rhp->mmidr, mmid); 212 } 213 214 static inline int insert_handle(struct c4iw_dev *rhp, struct idr *idr, 215 void *handle, u32 id) 216 { 217 int ret; 218 int newid; 219 220 do { 221 if (!idr_pre_get(idr, GFP_KERNEL)) 222 return -ENOMEM; 223 spin_lock_irq(&rhp->lock); 224 ret = idr_get_new_above(idr, handle, id, &newid); 225 BUG_ON(newid != id); 226 spin_unlock_irq(&rhp->lock); 227 } while (ret == -EAGAIN); 228 229 return ret; 230 } 231 232 static inline void remove_handle(struct c4iw_dev *rhp, struct idr *idr, u32 id) 233 { 234 spin_lock_irq(&rhp->lock); 235 idr_remove(idr, id); 236 spin_unlock_irq(&rhp->lock); 237 } 238 239 struct c4iw_pd { 240 struct ib_pd ibpd; 241 u32 pdid; 242 struct c4iw_dev *rhp; 243 }; 244 245 static inline struct c4iw_pd *to_c4iw_pd(struct ib_pd *ibpd) 246 { 247 return container_of(ibpd, struct c4iw_pd, ibpd); 248 } 249 250 struct tpt_attributes { 251 u64 len; 252 u64 va_fbo; 253 enum fw_ri_mem_perms perms; 254 u32 stag; 255 u32 pdid; 256 u32 qpid; 257 u32 pbl_addr; 258 u32 pbl_size; 259 u32 state:1; 260 u32 type:2; 261 u32 rsvd:1; 262 u32 remote_invaliate_disable:1; 263 u32 zbva:1; 264 u32 mw_bind_enable:1; 265 u32 page_size:5; 266 }; 267 268 struct c4iw_mr { 269 struct ib_mr ibmr; 270 struct ib_umem *umem; 271 struct c4iw_dev *rhp; 272 u64 kva; 273 struct tpt_attributes attr; 274 }; 275 276 static inline struct c4iw_mr *to_c4iw_mr(struct ib_mr *ibmr) 277 { 278 return container_of(ibmr, struct c4iw_mr, ibmr); 279 } 280 281 struct c4iw_mw { 282 struct ib_mw ibmw; 283 struct c4iw_dev *rhp; 284 u64 kva; 285 struct tpt_attributes attr; 286 }; 287 288 static inline struct c4iw_mw *to_c4iw_mw(struct ib_mw *ibmw) 289 { 290 return container_of(ibmw, struct c4iw_mw, ibmw); 291 } 292 293 struct c4iw_fr_page_list { 294 struct ib_fast_reg_page_list ibpl; 295 DEFINE_DMA_UNMAP_ADDR(mapping); 296 dma_addr_t dma_addr; 297 struct c4iw_dev *dev; 298 int size; 299 }; 300 301 static inline struct c4iw_fr_page_list *to_c4iw_fr_page_list( 302 struct ib_fast_reg_page_list *ibpl) 303 { 304 return container_of(ibpl, struct c4iw_fr_page_list, ibpl); 305 } 306 307 struct c4iw_cq { 308 struct ib_cq ibcq; 309 struct c4iw_dev *rhp; 310 struct t4_cq cq; 311 spinlock_t lock; 312 atomic_t refcnt; 313 wait_queue_head_t wait; 314 }; 315 316 static inline struct c4iw_cq *to_c4iw_cq(struct ib_cq *ibcq) 317 { 318 return container_of(ibcq, struct c4iw_cq, ibcq); 319 } 320 321 struct c4iw_mpa_attributes { 322 u8 initiator; 323 u8 recv_marker_enabled; 324 u8 xmit_marker_enabled; 325 u8 crc_enabled; 326 u8 version; 327 u8 p2p_type; 328 }; 329 330 struct c4iw_qp_attributes { 331 u32 scq; 332 u32 rcq; 333 u32 sq_num_entries; 334 u32 rq_num_entries; 335 u32 sq_max_sges; 336 u32 sq_max_sges_rdma_write; 337 u32 rq_max_sges; 338 u32 state; 339 u8 enable_rdma_read; 340 u8 enable_rdma_write; 341 u8 enable_bind; 342 u8 enable_mmid0_fastreg; 343 u32 max_ord; 344 u32 max_ird; 345 u32 pd; 346 u32 next_state; 347 char terminate_buffer[52]; 348 u32 terminate_msg_len; 349 u8 is_terminate_local; 350 struct c4iw_mpa_attributes mpa_attr; 351 struct c4iw_ep *llp_stream_handle; 352 }; 353 354 struct c4iw_qp { 355 struct ib_qp ibqp; 356 struct c4iw_dev *rhp; 357 struct c4iw_ep *ep; 358 struct c4iw_qp_attributes attr; 359 struct t4_wq wq; 360 spinlock_t lock; 361 struct mutex mutex; 362 atomic_t refcnt; 363 wait_queue_head_t wait; 364 struct timer_list timer; 365 }; 366 367 static inline struct c4iw_qp *to_c4iw_qp(struct ib_qp *ibqp) 368 { 369 return container_of(ibqp, struct c4iw_qp, ibqp); 370 } 371 372 struct c4iw_ucontext { 373 struct ib_ucontext ibucontext; 374 struct c4iw_dev_ucontext uctx; 375 u32 key; 376 spinlock_t mmap_lock; 377 struct list_head mmaps; 378 }; 379 380 static inline struct c4iw_ucontext *to_c4iw_ucontext(struct ib_ucontext *c) 381 { 382 return container_of(c, struct c4iw_ucontext, ibucontext); 383 } 384 385 struct c4iw_mm_entry { 386 struct list_head entry; 387 u64 addr; 388 u32 key; 389 unsigned len; 390 }; 391 392 static inline struct c4iw_mm_entry *remove_mmap(struct c4iw_ucontext *ucontext, 393 u32 key, unsigned len) 394 { 395 struct list_head *pos, *nxt; 396 struct c4iw_mm_entry *mm; 397 398 spin_lock(&ucontext->mmap_lock); 399 list_for_each_safe(pos, nxt, &ucontext->mmaps) { 400 401 mm = list_entry(pos, struct c4iw_mm_entry, entry); 402 if (mm->key == key && mm->len == len) { 403 list_del_init(&mm->entry); 404 spin_unlock(&ucontext->mmap_lock); 405 PDBG("%s key 0x%x addr 0x%llx len %d\n", __func__, 406 key, (unsigned long long) mm->addr, mm->len); 407 return mm; 408 } 409 } 410 spin_unlock(&ucontext->mmap_lock); 411 return NULL; 412 } 413 414 static inline void insert_mmap(struct c4iw_ucontext *ucontext, 415 struct c4iw_mm_entry *mm) 416 { 417 spin_lock(&ucontext->mmap_lock); 418 PDBG("%s key 0x%x addr 0x%llx len %d\n", __func__, 419 mm->key, (unsigned long long) mm->addr, mm->len); 420 list_add_tail(&mm->entry, &ucontext->mmaps); 421 spin_unlock(&ucontext->mmap_lock); 422 } 423 424 enum c4iw_qp_attr_mask { 425 C4IW_QP_ATTR_NEXT_STATE = 1 << 0, 426 C4IW_QP_ATTR_ENABLE_RDMA_READ = 1 << 7, 427 C4IW_QP_ATTR_ENABLE_RDMA_WRITE = 1 << 8, 428 C4IW_QP_ATTR_ENABLE_RDMA_BIND = 1 << 9, 429 C4IW_QP_ATTR_MAX_ORD = 1 << 11, 430 C4IW_QP_ATTR_MAX_IRD = 1 << 12, 431 C4IW_QP_ATTR_LLP_STREAM_HANDLE = 1 << 22, 432 C4IW_QP_ATTR_STREAM_MSG_BUFFER = 1 << 23, 433 C4IW_QP_ATTR_MPA_ATTR = 1 << 24, 434 C4IW_QP_ATTR_QP_CONTEXT_ACTIVATE = 1 << 25, 435 C4IW_QP_ATTR_VALID_MODIFY = (C4IW_QP_ATTR_ENABLE_RDMA_READ | 436 C4IW_QP_ATTR_ENABLE_RDMA_WRITE | 437 C4IW_QP_ATTR_MAX_ORD | 438 C4IW_QP_ATTR_MAX_IRD | 439 C4IW_QP_ATTR_LLP_STREAM_HANDLE | 440 C4IW_QP_ATTR_STREAM_MSG_BUFFER | 441 C4IW_QP_ATTR_MPA_ATTR | 442 C4IW_QP_ATTR_QP_CONTEXT_ACTIVATE) 443 }; 444 445 int c4iw_modify_qp(struct c4iw_dev *rhp, 446 struct c4iw_qp *qhp, 447 enum c4iw_qp_attr_mask mask, 448 struct c4iw_qp_attributes *attrs, 449 int internal); 450 451 enum c4iw_qp_state { 452 C4IW_QP_STATE_IDLE, 453 C4IW_QP_STATE_RTS, 454 C4IW_QP_STATE_ERROR, 455 C4IW_QP_STATE_TERMINATE, 456 C4IW_QP_STATE_CLOSING, 457 C4IW_QP_STATE_TOT 458 }; 459 460 static inline int c4iw_convert_state(enum ib_qp_state ib_state) 461 { 462 switch (ib_state) { 463 case IB_QPS_RESET: 464 case IB_QPS_INIT: 465 return C4IW_QP_STATE_IDLE; 466 case IB_QPS_RTS: 467 return C4IW_QP_STATE_RTS; 468 case IB_QPS_SQD: 469 return C4IW_QP_STATE_CLOSING; 470 case IB_QPS_SQE: 471 return C4IW_QP_STATE_TERMINATE; 472 case IB_QPS_ERR: 473 return C4IW_QP_STATE_ERROR; 474 default: 475 return -1; 476 } 477 } 478 479 static inline u32 c4iw_ib_to_tpt_access(int a) 480 { 481 return (a & IB_ACCESS_REMOTE_WRITE ? FW_RI_MEM_ACCESS_REM_WRITE : 0) | 482 (a & IB_ACCESS_REMOTE_READ ? FW_RI_MEM_ACCESS_REM_READ : 0) | 483 (a & IB_ACCESS_LOCAL_WRITE ? FW_RI_MEM_ACCESS_LOCAL_WRITE : 0) | 484 FW_RI_MEM_ACCESS_LOCAL_READ; 485 } 486 487 static inline u32 c4iw_ib_to_tpt_bind_access(int acc) 488 { 489 return (acc & IB_ACCESS_REMOTE_WRITE ? FW_RI_MEM_ACCESS_REM_WRITE : 0) | 490 (acc & IB_ACCESS_REMOTE_READ ? FW_RI_MEM_ACCESS_REM_READ : 0); 491 } 492 493 enum c4iw_mmid_state { 494 C4IW_STAG_STATE_VALID, 495 C4IW_STAG_STATE_INVALID 496 }; 497 498 #define C4IW_NODE_DESC "cxgb4 Chelsio Communications" 499 500 #define MPA_KEY_REQ "MPA ID Req Frame" 501 #define MPA_KEY_REP "MPA ID Rep Frame" 502 503 #define MPA_MAX_PRIVATE_DATA 256 504 #define MPA_REJECT 0x20 505 #define MPA_CRC 0x40 506 #define MPA_MARKERS 0x80 507 #define MPA_FLAGS_MASK 0xE0 508 509 #define c4iw_put_ep(ep) { \ 510 PDBG("put_ep (via %s:%u) ep %p refcnt %d\n", __func__, __LINE__, \ 511 ep, atomic_read(&((ep)->kref.refcount))); \ 512 WARN_ON(atomic_read(&((ep)->kref.refcount)) < 1); \ 513 kref_put(&((ep)->kref), _c4iw_free_ep); \ 514 } 515 516 #define c4iw_get_ep(ep) { \ 517 PDBG("get_ep (via %s:%u) ep %p, refcnt %d\n", __func__, __LINE__, \ 518 ep, atomic_read(&((ep)->kref.refcount))); \ 519 kref_get(&((ep)->kref)); \ 520 } 521 void _c4iw_free_ep(struct kref *kref); 522 523 struct mpa_message { 524 u8 key[16]; 525 u8 flags; 526 u8 revision; 527 __be16 private_data_size; 528 u8 private_data[0]; 529 }; 530 531 struct terminate_message { 532 u8 layer_etype; 533 u8 ecode; 534 __be16 hdrct_rsvd; 535 u8 len_hdrs[0]; 536 }; 537 538 #define TERM_MAX_LENGTH (sizeof(struct terminate_message) + 2 + 18 + 28) 539 540 enum c4iw_layers_types { 541 LAYER_RDMAP = 0x00, 542 LAYER_DDP = 0x10, 543 LAYER_MPA = 0x20, 544 RDMAP_LOCAL_CATA = 0x00, 545 RDMAP_REMOTE_PROT = 0x01, 546 RDMAP_REMOTE_OP = 0x02, 547 DDP_LOCAL_CATA = 0x00, 548 DDP_TAGGED_ERR = 0x01, 549 DDP_UNTAGGED_ERR = 0x02, 550 DDP_LLP = 0x03 551 }; 552 553 enum c4iw_rdma_ecodes { 554 RDMAP_INV_STAG = 0x00, 555 RDMAP_BASE_BOUNDS = 0x01, 556 RDMAP_ACC_VIOL = 0x02, 557 RDMAP_STAG_NOT_ASSOC = 0x03, 558 RDMAP_TO_WRAP = 0x04, 559 RDMAP_INV_VERS = 0x05, 560 RDMAP_INV_OPCODE = 0x06, 561 RDMAP_STREAM_CATA = 0x07, 562 RDMAP_GLOBAL_CATA = 0x08, 563 RDMAP_CANT_INV_STAG = 0x09, 564 RDMAP_UNSPECIFIED = 0xff 565 }; 566 567 enum c4iw_ddp_ecodes { 568 DDPT_INV_STAG = 0x00, 569 DDPT_BASE_BOUNDS = 0x01, 570 DDPT_STAG_NOT_ASSOC = 0x02, 571 DDPT_TO_WRAP = 0x03, 572 DDPT_INV_VERS = 0x04, 573 DDPU_INV_QN = 0x01, 574 DDPU_INV_MSN_NOBUF = 0x02, 575 DDPU_INV_MSN_RANGE = 0x03, 576 DDPU_INV_MO = 0x04, 577 DDPU_MSG_TOOBIG = 0x05, 578 DDPU_INV_VERS = 0x06 579 }; 580 581 enum c4iw_mpa_ecodes { 582 MPA_CRC_ERR = 0x02, 583 MPA_MARKER_ERR = 0x03 584 }; 585 586 enum c4iw_ep_state { 587 IDLE = 0, 588 LISTEN, 589 CONNECTING, 590 MPA_REQ_WAIT, 591 MPA_REQ_SENT, 592 MPA_REQ_RCVD, 593 MPA_REP_SENT, 594 FPDU_MODE, 595 ABORTING, 596 CLOSING, 597 MORIBUND, 598 DEAD, 599 }; 600 601 enum c4iw_ep_flags { 602 PEER_ABORT_IN_PROGRESS = 0, 603 ABORT_REQ_IN_PROGRESS = 1, 604 RELEASE_RESOURCES = 2, 605 CLOSE_SENT = 3, 606 }; 607 608 struct c4iw_ep_common { 609 struct iw_cm_id *cm_id; 610 struct c4iw_qp *qp; 611 struct c4iw_dev *dev; 612 enum c4iw_ep_state state; 613 struct kref kref; 614 struct mutex mutex; 615 struct sockaddr_in local_addr; 616 struct sockaddr_in remote_addr; 617 struct c4iw_wr_wait wr_wait; 618 unsigned long flags; 619 }; 620 621 struct c4iw_listen_ep { 622 struct c4iw_ep_common com; 623 unsigned int stid; 624 int backlog; 625 }; 626 627 struct c4iw_ep { 628 struct c4iw_ep_common com; 629 struct c4iw_ep *parent_ep; 630 struct timer_list timer; 631 struct list_head entry; 632 unsigned int atid; 633 u32 hwtid; 634 u32 snd_seq; 635 u32 rcv_seq; 636 struct l2t_entry *l2t; 637 struct dst_entry *dst; 638 struct sk_buff *mpa_skb; 639 struct c4iw_mpa_attributes mpa_attr; 640 u8 mpa_pkt[sizeof(struct mpa_message) + MPA_MAX_PRIVATE_DATA]; 641 unsigned int mpa_pkt_len; 642 u32 ird; 643 u32 ord; 644 u32 smac_idx; 645 u32 tx_chan; 646 u32 mtu; 647 u16 mss; 648 u16 emss; 649 u16 plen; 650 u16 rss_qid; 651 u16 txq_idx; 652 u16 ctrlq_idx; 653 u8 tos; 654 }; 655 656 static inline struct c4iw_ep *to_ep(struct iw_cm_id *cm_id) 657 { 658 return cm_id->provider_data; 659 } 660 661 static inline struct c4iw_listen_ep *to_listen_ep(struct iw_cm_id *cm_id) 662 { 663 return cm_id->provider_data; 664 } 665 666 static inline int compute_wscale(int win) 667 { 668 int wscale = 0; 669 670 while (wscale < 14 && (65535<<wscale) < win) 671 wscale++; 672 return wscale; 673 } 674 675 typedef int (*c4iw_handler_func)(struct c4iw_dev *dev, struct sk_buff *skb); 676 677 int c4iw_ep_redirect(void *ctx, struct dst_entry *old, struct dst_entry *new, 678 struct l2t_entry *l2t); 679 void c4iw_put_qpid(struct c4iw_rdev *rdev, u32 qpid, 680 struct c4iw_dev_ucontext *uctx); 681 u32 c4iw_get_resource(struct kfifo *fifo, spinlock_t *lock); 682 void c4iw_put_resource(struct kfifo *fifo, u32 entry, spinlock_t *lock); 683 int c4iw_init_resource(struct c4iw_rdev *rdev, u32 nr_tpt, u32 nr_pdid); 684 int c4iw_init_ctrl_qp(struct c4iw_rdev *rdev); 685 int c4iw_pblpool_create(struct c4iw_rdev *rdev); 686 int c4iw_rqtpool_create(struct c4iw_rdev *rdev); 687 int c4iw_ocqp_pool_create(struct c4iw_rdev *rdev); 688 void c4iw_pblpool_destroy(struct c4iw_rdev *rdev); 689 void c4iw_rqtpool_destroy(struct c4iw_rdev *rdev); 690 void c4iw_ocqp_pool_destroy(struct c4iw_rdev *rdev); 691 void c4iw_destroy_resource(struct c4iw_resource *rscp); 692 int c4iw_destroy_ctrl_qp(struct c4iw_rdev *rdev); 693 int c4iw_register_device(struct c4iw_dev *dev); 694 void c4iw_unregister_device(struct c4iw_dev *dev); 695 int __init c4iw_cm_init(void); 696 void __exit c4iw_cm_term(void); 697 void c4iw_release_dev_ucontext(struct c4iw_rdev *rdev, 698 struct c4iw_dev_ucontext *uctx); 699 void c4iw_init_dev_ucontext(struct c4iw_rdev *rdev, 700 struct c4iw_dev_ucontext *uctx); 701 int c4iw_poll_cq(struct ib_cq *ibcq, int num_entries, struct ib_wc *wc); 702 int c4iw_post_send(struct ib_qp *ibqp, struct ib_send_wr *wr, 703 struct ib_send_wr **bad_wr); 704 int c4iw_post_receive(struct ib_qp *ibqp, struct ib_recv_wr *wr, 705 struct ib_recv_wr **bad_wr); 706 int c4iw_bind_mw(struct ib_qp *qp, struct ib_mw *mw, 707 struct ib_mw_bind *mw_bind); 708 int c4iw_connect(struct iw_cm_id *cm_id, struct iw_cm_conn_param *conn_param); 709 int c4iw_create_listen(struct iw_cm_id *cm_id, int backlog); 710 int c4iw_destroy_listen(struct iw_cm_id *cm_id); 711 int c4iw_accept_cr(struct iw_cm_id *cm_id, struct iw_cm_conn_param *conn_param); 712 int c4iw_reject_cr(struct iw_cm_id *cm_id, const void *pdata, u8 pdata_len); 713 void c4iw_qp_add_ref(struct ib_qp *qp); 714 void c4iw_qp_rem_ref(struct ib_qp *qp); 715 void c4iw_free_fastreg_pbl(struct ib_fast_reg_page_list *page_list); 716 struct ib_fast_reg_page_list *c4iw_alloc_fastreg_pbl( 717 struct ib_device *device, 718 int page_list_len); 719 struct ib_mr *c4iw_alloc_fast_reg_mr(struct ib_pd *pd, int pbl_depth); 720 int c4iw_dealloc_mw(struct ib_mw *mw); 721 struct ib_mw *c4iw_alloc_mw(struct ib_pd *pd); 722 struct ib_mr *c4iw_reg_user_mr(struct ib_pd *pd, u64 start, 723 u64 length, u64 virt, int acc, 724 struct ib_udata *udata); 725 struct ib_mr *c4iw_get_dma_mr(struct ib_pd *pd, int acc); 726 struct ib_mr *c4iw_register_phys_mem(struct ib_pd *pd, 727 struct ib_phys_buf *buffer_list, 728 int num_phys_buf, 729 int acc, 730 u64 *iova_start); 731 int c4iw_reregister_phys_mem(struct ib_mr *mr, 732 int mr_rereg_mask, 733 struct ib_pd *pd, 734 struct ib_phys_buf *buffer_list, 735 int num_phys_buf, 736 int acc, u64 *iova_start); 737 int c4iw_dereg_mr(struct ib_mr *ib_mr); 738 int c4iw_destroy_cq(struct ib_cq *ib_cq); 739 struct ib_cq *c4iw_create_cq(struct ib_device *ibdev, int entries, 740 int vector, 741 struct ib_ucontext *ib_context, 742 struct ib_udata *udata); 743 int c4iw_resize_cq(struct ib_cq *cq, int cqe, struct ib_udata *udata); 744 int c4iw_arm_cq(struct ib_cq *ibcq, enum ib_cq_notify_flags flags); 745 int c4iw_destroy_qp(struct ib_qp *ib_qp); 746 struct ib_qp *c4iw_create_qp(struct ib_pd *pd, 747 struct ib_qp_init_attr *attrs, 748 struct ib_udata *udata); 749 int c4iw_ib_modify_qp(struct ib_qp *ibqp, struct ib_qp_attr *attr, 750 int attr_mask, struct ib_udata *udata); 751 struct ib_qp *c4iw_get_qp(struct ib_device *dev, int qpn); 752 u32 c4iw_rqtpool_alloc(struct c4iw_rdev *rdev, int size); 753 void c4iw_rqtpool_free(struct c4iw_rdev *rdev, u32 addr, int size); 754 u32 c4iw_pblpool_alloc(struct c4iw_rdev *rdev, int size); 755 void c4iw_pblpool_free(struct c4iw_rdev *rdev, u32 addr, int size); 756 u32 c4iw_ocqp_pool_alloc(struct c4iw_rdev *rdev, int size); 757 void c4iw_ocqp_pool_free(struct c4iw_rdev *rdev, u32 addr, int size); 758 int c4iw_ofld_send(struct c4iw_rdev *rdev, struct sk_buff *skb); 759 void c4iw_flush_hw_cq(struct t4_cq *cq); 760 void c4iw_count_rcqes(struct t4_cq *cq, struct t4_wq *wq, int *count); 761 void c4iw_count_scqes(struct t4_cq *cq, struct t4_wq *wq, int *count); 762 int c4iw_ep_disconnect(struct c4iw_ep *ep, int abrupt, gfp_t gfp); 763 int c4iw_flush_rq(struct t4_wq *wq, struct t4_cq *cq, int count); 764 int c4iw_flush_sq(struct t4_wq *wq, struct t4_cq *cq, int count); 765 int c4iw_ev_handler(struct c4iw_dev *rnicp, u32 qid); 766 u16 c4iw_rqes_posted(struct c4iw_qp *qhp); 767 int c4iw_post_terminate(struct c4iw_qp *qhp, struct t4_cqe *err_cqe); 768 u32 c4iw_get_cqid(struct c4iw_rdev *rdev, struct c4iw_dev_ucontext *uctx); 769 void c4iw_put_cqid(struct c4iw_rdev *rdev, u32 qid, 770 struct c4iw_dev_ucontext *uctx); 771 u32 c4iw_get_qpid(struct c4iw_rdev *rdev, struct c4iw_dev_ucontext *uctx); 772 void c4iw_put_qpid(struct c4iw_rdev *rdev, u32 qid, 773 struct c4iw_dev_ucontext *uctx); 774 void c4iw_ev_dispatch(struct c4iw_dev *dev, struct t4_cqe *err_cqe); 775 776 extern struct cxgb4_client t4c_client; 777 extern c4iw_handler_func c4iw_handlers[NUM_CPL_CMDS]; 778 extern int c4iw_max_read_depth; 779 780 #endif 781