1 /* 2 * Copyright (c) 2009-2010 Chelsio, Inc. All rights reserved. 3 * 4 * This software is available to you under a choice of one of two 5 * licenses. You may choose to be licensed under the terms of the GNU 6 * General Public License (GPL) Version 2, available from the file 7 * COPYING in the main directory of this source tree, or the 8 * OpenIB.org BSD license below: 9 * 10 * Redistribution and use in source and binary forms, with or 11 * without modification, are permitted provided that the following 12 * conditions are met: 13 * 14 * - Redistributions of source code must retain the above 15 * copyright notice, this list of conditions and the following 16 * disclaimer. 17 * - Redistributions in binary form must reproduce the above 18 * copyright notice, this list of conditions and the following 19 * disclaimer in the documentation and/or other materials 20 * provided with the distribution. 21 * 22 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, 23 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF 24 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND 25 * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS 26 * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN 27 * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN 28 * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE 29 * SOFTWARE. 30 */ 31 #ifndef __IW_CXGB4_H__ 32 #define __IW_CXGB4_H__ 33 34 #include <linux/mutex.h> 35 #include <linux/list.h> 36 #include <linux/spinlock.h> 37 #include <linux/idr.h> 38 #include <linux/completion.h> 39 #include <linux/netdevice.h> 40 #include <linux/sched/mm.h> 41 #include <linux/pci.h> 42 #include <linux/dma-mapping.h> 43 #include <linux/inet.h> 44 #include <linux/wait.h> 45 #include <linux/kref.h> 46 #include <linux/timer.h> 47 #include <linux/io.h> 48 #include <linux/workqueue.h> 49 50 #include <asm/byteorder.h> 51 52 #include <net/net_namespace.h> 53 54 #include <rdma/ib_verbs.h> 55 #include <rdma/iw_cm.h> 56 #include <rdma/rdma_netlink.h> 57 #include <rdma/iw_portmap.h> 58 59 #include "cxgb4.h" 60 #include "cxgb4_uld.h" 61 #include "l2t.h" 62 #include <rdma/cxgb4-abi.h> 63 64 #define DRV_NAME "iw_cxgb4" 65 #define MOD DRV_NAME ":" 66 67 #ifdef pr_fmt 68 #undef pr_fmt 69 #endif 70 71 #define pr_fmt(fmt) KBUILD_MODNAME ": " fmt 72 73 #include "t4.h" 74 75 #define PBL_OFF(rdev_p, a) ((a) - (rdev_p)->lldi.vr->pbl.start) 76 #define RQT_OFF(rdev_p, a) ((a) - (rdev_p)->lldi.vr->rq.start) 77 78 static inline void *cplhdr(struct sk_buff *skb) 79 { 80 return skb->data; 81 } 82 83 #define C4IW_ID_TABLE_F_RANDOM 1 /* Pseudo-randomize the id's returned */ 84 #define C4IW_ID_TABLE_F_EMPTY 2 /* Table is initially empty */ 85 86 struct c4iw_id_table { 87 u32 flags; 88 u32 start; /* logical minimal id */ 89 u32 last; /* hint for find */ 90 u32 max; 91 spinlock_t lock; 92 unsigned long *table; 93 }; 94 95 struct c4iw_resource { 96 struct c4iw_id_table tpt_table; 97 struct c4iw_id_table qid_table; 98 struct c4iw_id_table pdid_table; 99 }; 100 101 struct c4iw_qid_list { 102 struct list_head entry; 103 u32 qid; 104 }; 105 106 struct c4iw_dev_ucontext { 107 struct list_head qpids; 108 struct list_head cqids; 109 struct mutex lock; 110 struct kref kref; 111 }; 112 113 enum c4iw_rdev_flags { 114 T4_FATAL_ERROR = (1<<0), 115 T4_STATUS_PAGE_DISABLED = (1<<1), 116 }; 117 118 struct c4iw_stat { 119 u64 total; 120 u64 cur; 121 u64 max; 122 u64 fail; 123 }; 124 125 struct c4iw_stats { 126 struct mutex lock; 127 struct c4iw_stat qid; 128 struct c4iw_stat pd; 129 struct c4iw_stat stag; 130 struct c4iw_stat pbl; 131 struct c4iw_stat rqt; 132 struct c4iw_stat ocqp; 133 u64 db_full; 134 u64 db_empty; 135 u64 db_drop; 136 u64 db_state_transitions; 137 u64 db_fc_interruptions; 138 u64 tcam_full; 139 u64 act_ofld_conn_fails; 140 u64 pas_ofld_conn_fails; 141 u64 neg_adv; 142 }; 143 144 struct c4iw_hw_queue { 145 int t4_eq_status_entries; 146 int t4_max_eq_size; 147 int t4_max_iq_size; 148 int t4_max_rq_size; 149 int t4_max_sq_size; 150 int t4_max_qp_depth; 151 int t4_max_cq_depth; 152 int t4_stat_len; 153 }; 154 155 struct wr_log_entry { 156 ktime_t post_host_time; 157 ktime_t poll_host_time; 158 u64 post_sge_ts; 159 u64 cqe_sge_ts; 160 u64 poll_sge_ts; 161 u16 qid; 162 u16 wr_id; 163 u8 opcode; 164 u8 valid; 165 }; 166 167 struct c4iw_rdev { 168 struct c4iw_resource resource; 169 u32 qpmask; 170 u32 cqmask; 171 struct c4iw_dev_ucontext uctx; 172 struct gen_pool *pbl_pool; 173 struct gen_pool *rqt_pool; 174 struct gen_pool *ocqp_pool; 175 u32 flags; 176 struct cxgb4_lld_info lldi; 177 unsigned long bar2_pa; 178 void __iomem *bar2_kva; 179 unsigned long oc_mw_pa; 180 void __iomem *oc_mw_kva; 181 struct c4iw_stats stats; 182 struct c4iw_hw_queue hw_queue; 183 struct t4_dev_status_page *status_page; 184 atomic_t wr_log_idx; 185 struct wr_log_entry *wr_log; 186 int wr_log_size; 187 struct workqueue_struct *free_workq; 188 struct completion rqt_compl; 189 struct completion pbl_compl; 190 struct kref rqt_kref; 191 struct kref pbl_kref; 192 }; 193 194 static inline int c4iw_fatal_error(struct c4iw_rdev *rdev) 195 { 196 return rdev->flags & T4_FATAL_ERROR; 197 } 198 199 static inline int c4iw_num_stags(struct c4iw_rdev *rdev) 200 { 201 return (int)(rdev->lldi.vr->stag.size >> 5); 202 } 203 204 #define C4IW_WR_TO (60*HZ) 205 206 struct c4iw_wr_wait { 207 struct completion completion; 208 int ret; 209 struct kref kref; 210 }; 211 212 void _c4iw_free_wr_wait(struct kref *kref); 213 214 static inline void c4iw_put_wr_wait(struct c4iw_wr_wait *wr_waitp) 215 { 216 pr_debug("wr_wait %p ref before put %u\n", wr_waitp, 217 kref_read(&wr_waitp->kref)); 218 WARN_ON(kref_read(&wr_waitp->kref) == 0); 219 kref_put(&wr_waitp->kref, _c4iw_free_wr_wait); 220 } 221 222 static inline void c4iw_get_wr_wait(struct c4iw_wr_wait *wr_waitp) 223 { 224 pr_debug("wr_wait %p ref before get %u\n", wr_waitp, 225 kref_read(&wr_waitp->kref)); 226 WARN_ON(kref_read(&wr_waitp->kref) == 0); 227 kref_get(&wr_waitp->kref); 228 } 229 230 static inline void c4iw_init_wr_wait(struct c4iw_wr_wait *wr_waitp) 231 { 232 wr_waitp->ret = 0; 233 init_completion(&wr_waitp->completion); 234 } 235 236 static inline void _c4iw_wake_up(struct c4iw_wr_wait *wr_waitp, int ret, 237 bool deref) 238 { 239 wr_waitp->ret = ret; 240 complete(&wr_waitp->completion); 241 if (deref) 242 c4iw_put_wr_wait(wr_waitp); 243 } 244 245 static inline void c4iw_wake_up_noref(struct c4iw_wr_wait *wr_waitp, int ret) 246 { 247 _c4iw_wake_up(wr_waitp, ret, false); 248 } 249 250 static inline void c4iw_wake_up_deref(struct c4iw_wr_wait *wr_waitp, int ret) 251 { 252 _c4iw_wake_up(wr_waitp, ret, true); 253 } 254 255 static inline int c4iw_wait_for_reply(struct c4iw_rdev *rdev, 256 struct c4iw_wr_wait *wr_waitp, 257 u32 hwtid, u32 qpid, 258 const char *func) 259 { 260 int ret; 261 262 if (c4iw_fatal_error(rdev)) { 263 wr_waitp->ret = -EIO; 264 goto out; 265 } 266 267 ret = wait_for_completion_timeout(&wr_waitp->completion, C4IW_WR_TO); 268 if (!ret) { 269 pr_err("%s - Device %s not responding (disabling device) - tid %u qpid %u\n", 270 func, pci_name(rdev->lldi.pdev), hwtid, qpid); 271 rdev->flags |= T4_FATAL_ERROR; 272 wr_waitp->ret = -EIO; 273 goto out; 274 } 275 if (wr_waitp->ret) 276 pr_debug("%s: FW reply %d tid %u qpid %u\n", 277 pci_name(rdev->lldi.pdev), wr_waitp->ret, hwtid, qpid); 278 out: 279 return wr_waitp->ret; 280 } 281 282 int c4iw_ofld_send(struct c4iw_rdev *rdev, struct sk_buff *skb); 283 284 static inline int c4iw_ref_send_wait(struct c4iw_rdev *rdev, 285 struct sk_buff *skb, 286 struct c4iw_wr_wait *wr_waitp, 287 u32 hwtid, u32 qpid, 288 const char *func) 289 { 290 int ret; 291 292 pr_debug("%s wr_wait %p hwtid %u qpid %u\n", func, wr_waitp, hwtid, 293 qpid); 294 c4iw_get_wr_wait(wr_waitp); 295 ret = c4iw_ofld_send(rdev, skb); 296 if (ret) { 297 c4iw_put_wr_wait(wr_waitp); 298 return ret; 299 } 300 return c4iw_wait_for_reply(rdev, wr_waitp, hwtid, qpid, func); 301 } 302 303 enum db_state { 304 NORMAL = 0, 305 FLOW_CONTROL = 1, 306 RECOVERY = 2, 307 STOPPED = 3 308 }; 309 310 struct c4iw_dev { 311 struct ib_device ibdev; 312 struct c4iw_rdev rdev; 313 u32 device_cap_flags; 314 struct idr cqidr; 315 struct idr qpidr; 316 struct idr mmidr; 317 spinlock_t lock; 318 struct mutex db_mutex; 319 struct dentry *debugfs_root; 320 enum db_state db_state; 321 struct idr hwtid_idr; 322 struct idr atid_idr; 323 struct idr stid_idr; 324 struct list_head db_fc_list; 325 u32 avail_ird; 326 wait_queue_head_t wait; 327 }; 328 329 struct uld_ctx { 330 struct list_head entry; 331 struct cxgb4_lld_info lldi; 332 struct c4iw_dev *dev; 333 struct work_struct reg_work; 334 }; 335 336 static inline struct c4iw_dev *to_c4iw_dev(struct ib_device *ibdev) 337 { 338 return container_of(ibdev, struct c4iw_dev, ibdev); 339 } 340 341 static inline struct c4iw_dev *rdev_to_c4iw_dev(struct c4iw_rdev *rdev) 342 { 343 return container_of(rdev, struct c4iw_dev, rdev); 344 } 345 346 static inline struct c4iw_cq *get_chp(struct c4iw_dev *rhp, u32 cqid) 347 { 348 return idr_find(&rhp->cqidr, cqid); 349 } 350 351 static inline struct c4iw_qp *get_qhp(struct c4iw_dev *rhp, u32 qpid) 352 { 353 return idr_find(&rhp->qpidr, qpid); 354 } 355 356 static inline struct c4iw_mr *get_mhp(struct c4iw_dev *rhp, u32 mmid) 357 { 358 return idr_find(&rhp->mmidr, mmid); 359 } 360 361 static inline int _insert_handle(struct c4iw_dev *rhp, struct idr *idr, 362 void *handle, u32 id, int lock) 363 { 364 int ret; 365 366 if (lock) { 367 idr_preload(GFP_KERNEL); 368 spin_lock_irq(&rhp->lock); 369 } 370 371 ret = idr_alloc(idr, handle, id, id + 1, GFP_ATOMIC); 372 373 if (lock) { 374 spin_unlock_irq(&rhp->lock); 375 idr_preload_end(); 376 } 377 378 return ret < 0 ? ret : 0; 379 } 380 381 static inline int insert_handle(struct c4iw_dev *rhp, struct idr *idr, 382 void *handle, u32 id) 383 { 384 return _insert_handle(rhp, idr, handle, id, 1); 385 } 386 387 static inline int insert_handle_nolock(struct c4iw_dev *rhp, struct idr *idr, 388 void *handle, u32 id) 389 { 390 return _insert_handle(rhp, idr, handle, id, 0); 391 } 392 393 static inline void _remove_handle(struct c4iw_dev *rhp, struct idr *idr, 394 u32 id, int lock) 395 { 396 if (lock) 397 spin_lock_irq(&rhp->lock); 398 idr_remove(idr, id); 399 if (lock) 400 spin_unlock_irq(&rhp->lock); 401 } 402 403 static inline void remove_handle(struct c4iw_dev *rhp, struct idr *idr, u32 id) 404 { 405 _remove_handle(rhp, idr, id, 1); 406 } 407 408 static inline void remove_handle_nolock(struct c4iw_dev *rhp, 409 struct idr *idr, u32 id) 410 { 411 _remove_handle(rhp, idr, id, 0); 412 } 413 414 extern uint c4iw_max_read_depth; 415 416 static inline int cur_max_read_depth(struct c4iw_dev *dev) 417 { 418 return min(dev->rdev.lldi.max_ordird_qp, c4iw_max_read_depth); 419 } 420 421 struct c4iw_pd { 422 struct ib_pd ibpd; 423 u32 pdid; 424 struct c4iw_dev *rhp; 425 }; 426 427 static inline struct c4iw_pd *to_c4iw_pd(struct ib_pd *ibpd) 428 { 429 return container_of(ibpd, struct c4iw_pd, ibpd); 430 } 431 432 struct tpt_attributes { 433 u64 len; 434 u64 va_fbo; 435 enum fw_ri_mem_perms perms; 436 u32 stag; 437 u32 pdid; 438 u32 qpid; 439 u32 pbl_addr; 440 u32 pbl_size; 441 u32 state:1; 442 u32 type:2; 443 u32 rsvd:1; 444 u32 remote_invaliate_disable:1; 445 u32 zbva:1; 446 u32 mw_bind_enable:1; 447 u32 page_size:5; 448 }; 449 450 struct c4iw_mr { 451 struct ib_mr ibmr; 452 struct ib_umem *umem; 453 struct c4iw_dev *rhp; 454 struct sk_buff *dereg_skb; 455 u64 kva; 456 struct tpt_attributes attr; 457 u64 *mpl; 458 dma_addr_t mpl_addr; 459 u32 max_mpl_len; 460 u32 mpl_len; 461 struct c4iw_wr_wait *wr_waitp; 462 }; 463 464 static inline struct c4iw_mr *to_c4iw_mr(struct ib_mr *ibmr) 465 { 466 return container_of(ibmr, struct c4iw_mr, ibmr); 467 } 468 469 struct c4iw_mw { 470 struct ib_mw ibmw; 471 struct c4iw_dev *rhp; 472 struct sk_buff *dereg_skb; 473 u64 kva; 474 struct tpt_attributes attr; 475 struct c4iw_wr_wait *wr_waitp; 476 }; 477 478 static inline struct c4iw_mw *to_c4iw_mw(struct ib_mw *ibmw) 479 { 480 return container_of(ibmw, struct c4iw_mw, ibmw); 481 } 482 483 struct c4iw_cq { 484 struct ib_cq ibcq; 485 struct c4iw_dev *rhp; 486 struct sk_buff *destroy_skb; 487 struct t4_cq cq; 488 spinlock_t lock; 489 spinlock_t comp_handler_lock; 490 atomic_t refcnt; 491 wait_queue_head_t wait; 492 struct c4iw_wr_wait *wr_waitp; 493 }; 494 495 static inline struct c4iw_cq *to_c4iw_cq(struct ib_cq *ibcq) 496 { 497 return container_of(ibcq, struct c4iw_cq, ibcq); 498 } 499 500 struct c4iw_mpa_attributes { 501 u8 initiator; 502 u8 recv_marker_enabled; 503 u8 xmit_marker_enabled; 504 u8 crc_enabled; 505 u8 enhanced_rdma_conn; 506 u8 version; 507 u8 p2p_type; 508 }; 509 510 struct c4iw_qp_attributes { 511 u32 scq; 512 u32 rcq; 513 u32 sq_num_entries; 514 u32 rq_num_entries; 515 u32 sq_max_sges; 516 u32 sq_max_sges_rdma_write; 517 u32 rq_max_sges; 518 u32 state; 519 u8 enable_rdma_read; 520 u8 enable_rdma_write; 521 u8 enable_bind; 522 u8 enable_mmid0_fastreg; 523 u32 max_ord; 524 u32 max_ird; 525 u32 pd; 526 u32 next_state; 527 char terminate_buffer[52]; 528 u32 terminate_msg_len; 529 u8 is_terminate_local; 530 struct c4iw_mpa_attributes mpa_attr; 531 struct c4iw_ep *llp_stream_handle; 532 u8 layer_etype; 533 u8 ecode; 534 u16 sq_db_inc; 535 u16 rq_db_inc; 536 u8 send_term; 537 }; 538 539 struct c4iw_qp { 540 struct ib_qp ibqp; 541 struct list_head db_fc_entry; 542 struct c4iw_dev *rhp; 543 struct c4iw_ep *ep; 544 struct c4iw_qp_attributes attr; 545 struct t4_wq wq; 546 spinlock_t lock; 547 struct mutex mutex; 548 struct kref kref; 549 wait_queue_head_t wait; 550 int sq_sig_all; 551 struct work_struct free_work; 552 struct c4iw_ucontext *ucontext; 553 struct c4iw_wr_wait *wr_waitp; 554 }; 555 556 static inline struct c4iw_qp *to_c4iw_qp(struct ib_qp *ibqp) 557 { 558 return container_of(ibqp, struct c4iw_qp, ibqp); 559 } 560 561 struct c4iw_ucontext { 562 struct ib_ucontext ibucontext; 563 struct c4iw_dev_ucontext uctx; 564 u32 key; 565 spinlock_t mmap_lock; 566 struct list_head mmaps; 567 struct kref kref; 568 }; 569 570 static inline struct c4iw_ucontext *to_c4iw_ucontext(struct ib_ucontext *c) 571 { 572 return container_of(c, struct c4iw_ucontext, ibucontext); 573 } 574 575 void _c4iw_free_ucontext(struct kref *kref); 576 577 static inline void c4iw_put_ucontext(struct c4iw_ucontext *ucontext) 578 { 579 kref_put(&ucontext->kref, _c4iw_free_ucontext); 580 } 581 582 static inline void c4iw_get_ucontext(struct c4iw_ucontext *ucontext) 583 { 584 kref_get(&ucontext->kref); 585 } 586 587 struct c4iw_mm_entry { 588 struct list_head entry; 589 u64 addr; 590 u32 key; 591 unsigned len; 592 }; 593 594 static inline struct c4iw_mm_entry *remove_mmap(struct c4iw_ucontext *ucontext, 595 u32 key, unsigned len) 596 { 597 struct list_head *pos, *nxt; 598 struct c4iw_mm_entry *mm; 599 600 spin_lock(&ucontext->mmap_lock); 601 list_for_each_safe(pos, nxt, &ucontext->mmaps) { 602 603 mm = list_entry(pos, struct c4iw_mm_entry, entry); 604 if (mm->key == key && mm->len == len) { 605 list_del_init(&mm->entry); 606 spin_unlock(&ucontext->mmap_lock); 607 pr_debug("key 0x%x addr 0x%llx len %d\n", key, 608 (unsigned long long)mm->addr, mm->len); 609 return mm; 610 } 611 } 612 spin_unlock(&ucontext->mmap_lock); 613 return NULL; 614 } 615 616 static inline void insert_mmap(struct c4iw_ucontext *ucontext, 617 struct c4iw_mm_entry *mm) 618 { 619 spin_lock(&ucontext->mmap_lock); 620 pr_debug("key 0x%x addr 0x%llx len %d\n", 621 mm->key, (unsigned long long)mm->addr, mm->len); 622 list_add_tail(&mm->entry, &ucontext->mmaps); 623 spin_unlock(&ucontext->mmap_lock); 624 } 625 626 enum c4iw_qp_attr_mask { 627 C4IW_QP_ATTR_NEXT_STATE = 1 << 0, 628 C4IW_QP_ATTR_SQ_DB = 1<<1, 629 C4IW_QP_ATTR_RQ_DB = 1<<2, 630 C4IW_QP_ATTR_ENABLE_RDMA_READ = 1 << 7, 631 C4IW_QP_ATTR_ENABLE_RDMA_WRITE = 1 << 8, 632 C4IW_QP_ATTR_ENABLE_RDMA_BIND = 1 << 9, 633 C4IW_QP_ATTR_MAX_ORD = 1 << 11, 634 C4IW_QP_ATTR_MAX_IRD = 1 << 12, 635 C4IW_QP_ATTR_LLP_STREAM_HANDLE = 1 << 22, 636 C4IW_QP_ATTR_STREAM_MSG_BUFFER = 1 << 23, 637 C4IW_QP_ATTR_MPA_ATTR = 1 << 24, 638 C4IW_QP_ATTR_QP_CONTEXT_ACTIVATE = 1 << 25, 639 C4IW_QP_ATTR_VALID_MODIFY = (C4IW_QP_ATTR_ENABLE_RDMA_READ | 640 C4IW_QP_ATTR_ENABLE_RDMA_WRITE | 641 C4IW_QP_ATTR_MAX_ORD | 642 C4IW_QP_ATTR_MAX_IRD | 643 C4IW_QP_ATTR_LLP_STREAM_HANDLE | 644 C4IW_QP_ATTR_STREAM_MSG_BUFFER | 645 C4IW_QP_ATTR_MPA_ATTR | 646 C4IW_QP_ATTR_QP_CONTEXT_ACTIVATE) 647 }; 648 649 int c4iw_modify_qp(struct c4iw_dev *rhp, 650 struct c4iw_qp *qhp, 651 enum c4iw_qp_attr_mask mask, 652 struct c4iw_qp_attributes *attrs, 653 int internal); 654 655 enum c4iw_qp_state { 656 C4IW_QP_STATE_IDLE, 657 C4IW_QP_STATE_RTS, 658 C4IW_QP_STATE_ERROR, 659 C4IW_QP_STATE_TERMINATE, 660 C4IW_QP_STATE_CLOSING, 661 C4IW_QP_STATE_TOT 662 }; 663 664 static inline int c4iw_convert_state(enum ib_qp_state ib_state) 665 { 666 switch (ib_state) { 667 case IB_QPS_RESET: 668 case IB_QPS_INIT: 669 return C4IW_QP_STATE_IDLE; 670 case IB_QPS_RTS: 671 return C4IW_QP_STATE_RTS; 672 case IB_QPS_SQD: 673 return C4IW_QP_STATE_CLOSING; 674 case IB_QPS_SQE: 675 return C4IW_QP_STATE_TERMINATE; 676 case IB_QPS_ERR: 677 return C4IW_QP_STATE_ERROR; 678 default: 679 return -1; 680 } 681 } 682 683 static inline int to_ib_qp_state(int c4iw_qp_state) 684 { 685 switch (c4iw_qp_state) { 686 case C4IW_QP_STATE_IDLE: 687 return IB_QPS_INIT; 688 case C4IW_QP_STATE_RTS: 689 return IB_QPS_RTS; 690 case C4IW_QP_STATE_CLOSING: 691 return IB_QPS_SQD; 692 case C4IW_QP_STATE_TERMINATE: 693 return IB_QPS_SQE; 694 case C4IW_QP_STATE_ERROR: 695 return IB_QPS_ERR; 696 } 697 return IB_QPS_ERR; 698 } 699 700 static inline u32 c4iw_ib_to_tpt_access(int a) 701 { 702 return (a & IB_ACCESS_REMOTE_WRITE ? FW_RI_MEM_ACCESS_REM_WRITE : 0) | 703 (a & IB_ACCESS_REMOTE_READ ? FW_RI_MEM_ACCESS_REM_READ : 0) | 704 (a & IB_ACCESS_LOCAL_WRITE ? FW_RI_MEM_ACCESS_LOCAL_WRITE : 0) | 705 FW_RI_MEM_ACCESS_LOCAL_READ; 706 } 707 708 static inline u32 c4iw_ib_to_tpt_bind_access(int acc) 709 { 710 return (acc & IB_ACCESS_REMOTE_WRITE ? FW_RI_MEM_ACCESS_REM_WRITE : 0) | 711 (acc & IB_ACCESS_REMOTE_READ ? FW_RI_MEM_ACCESS_REM_READ : 0); 712 } 713 714 enum c4iw_mmid_state { 715 C4IW_STAG_STATE_VALID, 716 C4IW_STAG_STATE_INVALID 717 }; 718 719 #define C4IW_NODE_DESC "cxgb4 Chelsio Communications" 720 721 #define MPA_KEY_REQ "MPA ID Req Frame" 722 #define MPA_KEY_REP "MPA ID Rep Frame" 723 724 #define MPA_MAX_PRIVATE_DATA 256 725 #define MPA_ENHANCED_RDMA_CONN 0x10 726 #define MPA_REJECT 0x20 727 #define MPA_CRC 0x40 728 #define MPA_MARKERS 0x80 729 #define MPA_FLAGS_MASK 0xE0 730 731 #define MPA_V2_PEER2PEER_MODEL 0x8000 732 #define MPA_V2_ZERO_LEN_FPDU_RTR 0x4000 733 #define MPA_V2_RDMA_WRITE_RTR 0x8000 734 #define MPA_V2_RDMA_READ_RTR 0x4000 735 #define MPA_V2_IRD_ORD_MASK 0x3FFF 736 737 #define c4iw_put_ep(ep) { \ 738 pr_debug("put_ep ep %p refcnt %d\n", \ 739 ep, kref_read(&((ep)->kref))); \ 740 WARN_ON(kref_read(&((ep)->kref)) < 1); \ 741 kref_put(&((ep)->kref), _c4iw_free_ep); \ 742 } 743 744 #define c4iw_get_ep(ep) { \ 745 pr_debug("get_ep ep %p, refcnt %d\n", \ 746 ep, kref_read(&((ep)->kref))); \ 747 kref_get(&((ep)->kref)); \ 748 } 749 void _c4iw_free_ep(struct kref *kref); 750 751 struct mpa_message { 752 u8 key[16]; 753 u8 flags; 754 u8 revision; 755 __be16 private_data_size; 756 u8 private_data[0]; 757 }; 758 759 struct mpa_v2_conn_params { 760 __be16 ird; 761 __be16 ord; 762 }; 763 764 struct terminate_message { 765 u8 layer_etype; 766 u8 ecode; 767 __be16 hdrct_rsvd; 768 u8 len_hdrs[0]; 769 }; 770 771 #define TERM_MAX_LENGTH (sizeof(struct terminate_message) + 2 + 18 + 28) 772 773 enum c4iw_layers_types { 774 LAYER_RDMAP = 0x00, 775 LAYER_DDP = 0x10, 776 LAYER_MPA = 0x20, 777 RDMAP_LOCAL_CATA = 0x00, 778 RDMAP_REMOTE_PROT = 0x01, 779 RDMAP_REMOTE_OP = 0x02, 780 DDP_LOCAL_CATA = 0x00, 781 DDP_TAGGED_ERR = 0x01, 782 DDP_UNTAGGED_ERR = 0x02, 783 DDP_LLP = 0x03 784 }; 785 786 enum c4iw_rdma_ecodes { 787 RDMAP_INV_STAG = 0x00, 788 RDMAP_BASE_BOUNDS = 0x01, 789 RDMAP_ACC_VIOL = 0x02, 790 RDMAP_STAG_NOT_ASSOC = 0x03, 791 RDMAP_TO_WRAP = 0x04, 792 RDMAP_INV_VERS = 0x05, 793 RDMAP_INV_OPCODE = 0x06, 794 RDMAP_STREAM_CATA = 0x07, 795 RDMAP_GLOBAL_CATA = 0x08, 796 RDMAP_CANT_INV_STAG = 0x09, 797 RDMAP_UNSPECIFIED = 0xff 798 }; 799 800 enum c4iw_ddp_ecodes { 801 DDPT_INV_STAG = 0x00, 802 DDPT_BASE_BOUNDS = 0x01, 803 DDPT_STAG_NOT_ASSOC = 0x02, 804 DDPT_TO_WRAP = 0x03, 805 DDPT_INV_VERS = 0x04, 806 DDPU_INV_QN = 0x01, 807 DDPU_INV_MSN_NOBUF = 0x02, 808 DDPU_INV_MSN_RANGE = 0x03, 809 DDPU_INV_MO = 0x04, 810 DDPU_MSG_TOOBIG = 0x05, 811 DDPU_INV_VERS = 0x06 812 }; 813 814 enum c4iw_mpa_ecodes { 815 MPA_CRC_ERR = 0x02, 816 MPA_MARKER_ERR = 0x03, 817 MPA_LOCAL_CATA = 0x05, 818 MPA_INSUFF_IRD = 0x06, 819 MPA_NOMATCH_RTR = 0x07, 820 }; 821 822 enum c4iw_ep_state { 823 IDLE = 0, 824 LISTEN, 825 CONNECTING, 826 MPA_REQ_WAIT, 827 MPA_REQ_SENT, 828 MPA_REQ_RCVD, 829 MPA_REP_SENT, 830 FPDU_MODE, 831 ABORTING, 832 CLOSING, 833 MORIBUND, 834 DEAD, 835 }; 836 837 enum c4iw_ep_flags { 838 PEER_ABORT_IN_PROGRESS = 0, 839 ABORT_REQ_IN_PROGRESS = 1, 840 RELEASE_RESOURCES = 2, 841 CLOSE_SENT = 3, 842 TIMEOUT = 4, 843 QP_REFERENCED = 5, 844 STOP_MPA_TIMER = 7, 845 }; 846 847 enum c4iw_ep_history { 848 ACT_OPEN_REQ = 0, 849 ACT_OFLD_CONN = 1, 850 ACT_OPEN_RPL = 2, 851 ACT_ESTAB = 3, 852 PASS_ACCEPT_REQ = 4, 853 PASS_ESTAB = 5, 854 ABORT_UPCALL = 6, 855 ESTAB_UPCALL = 7, 856 CLOSE_UPCALL = 8, 857 ULP_ACCEPT = 9, 858 ULP_REJECT = 10, 859 TIMEDOUT = 11, 860 PEER_ABORT = 12, 861 PEER_CLOSE = 13, 862 CONNREQ_UPCALL = 14, 863 ABORT_CONN = 15, 864 DISCONN_UPCALL = 16, 865 EP_DISC_CLOSE = 17, 866 EP_DISC_ABORT = 18, 867 CONN_RPL_UPCALL = 19, 868 ACT_RETRY_NOMEM = 20, 869 ACT_RETRY_INUSE = 21, 870 CLOSE_CON_RPL = 22, 871 EP_DISC_FAIL = 24, 872 QP_REFED = 25, 873 QP_DEREFED = 26, 874 CM_ID_REFED = 27, 875 CM_ID_DEREFED = 28, 876 }; 877 878 enum conn_pre_alloc_buffers { 879 CN_ABORT_REQ_BUF, 880 CN_ABORT_RPL_BUF, 881 CN_CLOSE_CON_REQ_BUF, 882 CN_DESTROY_BUF, 883 CN_FLOWC_BUF, 884 CN_MAX_CON_BUF 885 }; 886 887 #define FLOWC_LEN 80 888 union cpl_wr_size { 889 struct cpl_abort_req abrt_req; 890 struct cpl_abort_rpl abrt_rpl; 891 struct fw_ri_wr ri_req; 892 struct cpl_close_con_req close_req; 893 char flowc_buf[FLOWC_LEN]; 894 }; 895 896 struct c4iw_ep_common { 897 struct iw_cm_id *cm_id; 898 struct c4iw_qp *qp; 899 struct c4iw_dev *dev; 900 struct sk_buff_head ep_skb_list; 901 enum c4iw_ep_state state; 902 struct kref kref; 903 struct mutex mutex; 904 struct sockaddr_storage local_addr; 905 struct sockaddr_storage remote_addr; 906 struct c4iw_wr_wait *wr_waitp; 907 unsigned long flags; 908 unsigned long history; 909 }; 910 911 struct c4iw_listen_ep { 912 struct c4iw_ep_common com; 913 unsigned int stid; 914 int backlog; 915 }; 916 917 struct c4iw_ep_stats { 918 unsigned connect_neg_adv; 919 unsigned abort_neg_adv; 920 }; 921 922 struct c4iw_ep { 923 struct c4iw_ep_common com; 924 struct c4iw_ep *parent_ep; 925 struct timer_list timer; 926 struct list_head entry; 927 unsigned int atid; 928 u32 hwtid; 929 u32 snd_seq; 930 u32 rcv_seq; 931 struct l2t_entry *l2t; 932 struct dst_entry *dst; 933 struct sk_buff *mpa_skb; 934 struct c4iw_mpa_attributes mpa_attr; 935 u8 mpa_pkt[sizeof(struct mpa_message) + MPA_MAX_PRIVATE_DATA]; 936 unsigned int mpa_pkt_len; 937 u32 ird; 938 u32 ord; 939 u32 smac_idx; 940 u32 tx_chan; 941 u32 mtu; 942 u16 mss; 943 u16 emss; 944 u16 plen; 945 u16 rss_qid; 946 u16 txq_idx; 947 u16 ctrlq_idx; 948 u8 tos; 949 u8 retry_with_mpa_v1; 950 u8 tried_with_mpa_v1; 951 unsigned int retry_count; 952 int snd_win; 953 int rcv_win; 954 struct c4iw_ep_stats stats; 955 }; 956 957 static inline struct c4iw_ep *to_ep(struct iw_cm_id *cm_id) 958 { 959 return cm_id->provider_data; 960 } 961 962 static inline struct c4iw_listen_ep *to_listen_ep(struct iw_cm_id *cm_id) 963 { 964 return cm_id->provider_data; 965 } 966 967 static inline int ocqp_supported(const struct cxgb4_lld_info *infop) 968 { 969 #if defined(__i386__) || defined(__x86_64__) || defined(CONFIG_PPC64) 970 return infop->vr->ocq.size > 0; 971 #else 972 return 0; 973 #endif 974 } 975 976 u32 c4iw_id_alloc(struct c4iw_id_table *alloc); 977 void c4iw_id_free(struct c4iw_id_table *alloc, u32 obj); 978 int c4iw_id_table_alloc(struct c4iw_id_table *alloc, u32 start, u32 num, 979 u32 reserved, u32 flags); 980 void c4iw_id_table_free(struct c4iw_id_table *alloc); 981 982 typedef int (*c4iw_handler_func)(struct c4iw_dev *dev, struct sk_buff *skb); 983 984 int c4iw_ep_redirect(void *ctx, struct dst_entry *old, struct dst_entry *new, 985 struct l2t_entry *l2t); 986 void c4iw_put_qpid(struct c4iw_rdev *rdev, u32 qpid, 987 struct c4iw_dev_ucontext *uctx); 988 u32 c4iw_get_resource(struct c4iw_id_table *id_table); 989 void c4iw_put_resource(struct c4iw_id_table *id_table, u32 entry); 990 int c4iw_init_resource(struct c4iw_rdev *rdev, u32 nr_tpt, u32 nr_pdid); 991 int c4iw_init_ctrl_qp(struct c4iw_rdev *rdev); 992 int c4iw_pblpool_create(struct c4iw_rdev *rdev); 993 int c4iw_rqtpool_create(struct c4iw_rdev *rdev); 994 int c4iw_ocqp_pool_create(struct c4iw_rdev *rdev); 995 void c4iw_pblpool_destroy(struct c4iw_rdev *rdev); 996 void c4iw_rqtpool_destroy(struct c4iw_rdev *rdev); 997 void c4iw_ocqp_pool_destroy(struct c4iw_rdev *rdev); 998 void c4iw_destroy_resource(struct c4iw_resource *rscp); 999 int c4iw_destroy_ctrl_qp(struct c4iw_rdev *rdev); 1000 void c4iw_register_device(struct work_struct *work); 1001 void c4iw_unregister_device(struct c4iw_dev *dev); 1002 int __init c4iw_cm_init(void); 1003 void c4iw_cm_term(void); 1004 void c4iw_release_dev_ucontext(struct c4iw_rdev *rdev, 1005 struct c4iw_dev_ucontext *uctx); 1006 void c4iw_init_dev_ucontext(struct c4iw_rdev *rdev, 1007 struct c4iw_dev_ucontext *uctx); 1008 int c4iw_poll_cq(struct ib_cq *ibcq, int num_entries, struct ib_wc *wc); 1009 int c4iw_post_send(struct ib_qp *ibqp, struct ib_send_wr *wr, 1010 struct ib_send_wr **bad_wr); 1011 int c4iw_post_receive(struct ib_qp *ibqp, struct ib_recv_wr *wr, 1012 struct ib_recv_wr **bad_wr); 1013 int c4iw_connect(struct iw_cm_id *cm_id, struct iw_cm_conn_param *conn_param); 1014 int c4iw_create_listen(struct iw_cm_id *cm_id, int backlog); 1015 int c4iw_destroy_listen(struct iw_cm_id *cm_id); 1016 int c4iw_accept_cr(struct iw_cm_id *cm_id, struct iw_cm_conn_param *conn_param); 1017 int c4iw_reject_cr(struct iw_cm_id *cm_id, const void *pdata, u8 pdata_len); 1018 void c4iw_qp_add_ref(struct ib_qp *qp); 1019 void c4iw_qp_rem_ref(struct ib_qp *qp); 1020 struct ib_mr *c4iw_alloc_mr(struct ib_pd *pd, 1021 enum ib_mr_type mr_type, 1022 u32 max_num_sg); 1023 int c4iw_map_mr_sg(struct ib_mr *ibmr, struct scatterlist *sg, int sg_nents, 1024 unsigned int *sg_offset); 1025 int c4iw_dealloc_mw(struct ib_mw *mw); 1026 void c4iw_dealloc(struct uld_ctx *ctx); 1027 struct ib_mw *c4iw_alloc_mw(struct ib_pd *pd, enum ib_mw_type type, 1028 struct ib_udata *udata); 1029 struct ib_mr *c4iw_reg_user_mr(struct ib_pd *pd, u64 start, 1030 u64 length, u64 virt, int acc, 1031 struct ib_udata *udata); 1032 struct ib_mr *c4iw_get_dma_mr(struct ib_pd *pd, int acc); 1033 int c4iw_dereg_mr(struct ib_mr *ib_mr); 1034 int c4iw_destroy_cq(struct ib_cq *ib_cq); 1035 struct ib_cq *c4iw_create_cq(struct ib_device *ibdev, 1036 const struct ib_cq_init_attr *attr, 1037 struct ib_ucontext *ib_context, 1038 struct ib_udata *udata); 1039 int c4iw_resize_cq(struct ib_cq *cq, int cqe, struct ib_udata *udata); 1040 int c4iw_arm_cq(struct ib_cq *ibcq, enum ib_cq_notify_flags flags); 1041 int c4iw_destroy_qp(struct ib_qp *ib_qp); 1042 struct ib_qp *c4iw_create_qp(struct ib_pd *pd, 1043 struct ib_qp_init_attr *attrs, 1044 struct ib_udata *udata); 1045 int c4iw_ib_modify_qp(struct ib_qp *ibqp, struct ib_qp_attr *attr, 1046 int attr_mask, struct ib_udata *udata); 1047 int c4iw_ib_query_qp(struct ib_qp *ibqp, struct ib_qp_attr *attr, 1048 int attr_mask, struct ib_qp_init_attr *init_attr); 1049 struct ib_qp *c4iw_get_qp(struct ib_device *dev, int qpn); 1050 u32 c4iw_rqtpool_alloc(struct c4iw_rdev *rdev, int size); 1051 void c4iw_rqtpool_free(struct c4iw_rdev *rdev, u32 addr, int size); 1052 u32 c4iw_pblpool_alloc(struct c4iw_rdev *rdev, int size); 1053 void c4iw_pblpool_free(struct c4iw_rdev *rdev, u32 addr, int size); 1054 u32 c4iw_ocqp_pool_alloc(struct c4iw_rdev *rdev, int size); 1055 void c4iw_ocqp_pool_free(struct c4iw_rdev *rdev, u32 addr, int size); 1056 void c4iw_flush_hw_cq(struct c4iw_cq *chp, struct c4iw_qp *flush_qhp); 1057 void c4iw_count_rcqes(struct t4_cq *cq, struct t4_wq *wq, int *count); 1058 int c4iw_ep_disconnect(struct c4iw_ep *ep, int abrupt, gfp_t gfp); 1059 int c4iw_flush_rq(struct t4_wq *wq, struct t4_cq *cq, int count); 1060 int c4iw_flush_sq(struct c4iw_qp *qhp); 1061 int c4iw_ev_handler(struct c4iw_dev *rnicp, u32 qid); 1062 u16 c4iw_rqes_posted(struct c4iw_qp *qhp); 1063 int c4iw_post_terminate(struct c4iw_qp *qhp, struct t4_cqe *err_cqe); 1064 u32 c4iw_get_cqid(struct c4iw_rdev *rdev, struct c4iw_dev_ucontext *uctx); 1065 void c4iw_put_cqid(struct c4iw_rdev *rdev, u32 qid, 1066 struct c4iw_dev_ucontext *uctx); 1067 u32 c4iw_get_qpid(struct c4iw_rdev *rdev, struct c4iw_dev_ucontext *uctx); 1068 void c4iw_put_qpid(struct c4iw_rdev *rdev, u32 qid, 1069 struct c4iw_dev_ucontext *uctx); 1070 void c4iw_ev_dispatch(struct c4iw_dev *dev, struct t4_cqe *err_cqe); 1071 1072 extern struct cxgb4_client t4c_client; 1073 extern c4iw_handler_func c4iw_handlers[NUM_CPL_CMDS]; 1074 void __iomem *c4iw_bar2_addrs(struct c4iw_rdev *rdev, unsigned int qid, 1075 enum cxgb4_bar2_qtype qtype, 1076 unsigned int *pbar2_qid, u64 *pbar2_pa); 1077 extern void c4iw_log_wr_stats(struct t4_wq *wq, struct t4_cqe *cqe); 1078 extern int c4iw_wr_log; 1079 extern int db_fc_threshold; 1080 extern int db_coalescing_threshold; 1081 extern int use_dsgl; 1082 void c4iw_invalidate_mr(struct c4iw_dev *rhp, u32 rkey); 1083 struct c4iw_wr_wait *c4iw_alloc_wr_wait(gfp_t gfp); 1084 1085 #endif 1086