1 /* 2 * Copyright (c) 2009-2010 Chelsio, Inc. All rights reserved. 3 * 4 * This software is available to you under a choice of one of two 5 * licenses. You may choose to be licensed under the terms of the GNU 6 * General Public License (GPL) Version 2, available from the file 7 * COPYING in the main directory of this source tree, or the 8 * OpenIB.org BSD license below: 9 * 10 * Redistribution and use in source and binary forms, with or 11 * without modification, are permitted provided that the following 12 * conditions are met: 13 * 14 * - Redistributions of source code must retain the above 15 * copyright notice, this list of conditions and the following 16 * disclaimer. 17 * - Redistributions in binary form must reproduce the above 18 * copyright notice, this list of conditions and the following 19 * disclaimer in the documentation and/or other materials 20 * provided with the distribution. 21 * 22 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, 23 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF 24 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND 25 * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS 26 * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN 27 * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN 28 * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE 29 * SOFTWARE. 30 */ 31 #ifndef __IW_CXGB4_H__ 32 #define __IW_CXGB4_H__ 33 34 #include <linux/mutex.h> 35 #include <linux/list.h> 36 #include <linux/spinlock.h> 37 #include <linux/idr.h> 38 #include <linux/completion.h> 39 #include <linux/netdevice.h> 40 #include <linux/sched.h> 41 #include <linux/pci.h> 42 #include <linux/dma-mapping.h> 43 #include <linux/inet.h> 44 #include <linux/wait.h> 45 #include <linux/kref.h> 46 #include <linux/timer.h> 47 #include <linux/io.h> 48 49 #include <asm/byteorder.h> 50 51 #include <net/net_namespace.h> 52 53 #include <rdma/ib_verbs.h> 54 #include <rdma/iw_cm.h> 55 #include <rdma/rdma_netlink.h> 56 #include <rdma/iw_portmap.h> 57 58 #include "cxgb4.h" 59 #include "cxgb4_uld.h" 60 #include "l2t.h" 61 #include "user.h" 62 63 #define DRV_NAME "iw_cxgb4" 64 #define MOD DRV_NAME ":" 65 66 extern int c4iw_debug; 67 #define PDBG(fmt, args...) \ 68 do { \ 69 if (c4iw_debug) \ 70 printk(MOD fmt, ## args); \ 71 } while (0) 72 73 #include "t4.h" 74 75 #define PBL_OFF(rdev_p, a) ((a) - (rdev_p)->lldi.vr->pbl.start) 76 #define RQT_OFF(rdev_p, a) ((a) - (rdev_p)->lldi.vr->rq.start) 77 78 static inline void *cplhdr(struct sk_buff *skb) 79 { 80 return skb->data; 81 } 82 83 #define C4IW_ID_TABLE_F_RANDOM 1 /* Pseudo-randomize the id's returned */ 84 #define C4IW_ID_TABLE_F_EMPTY 2 /* Table is initially empty */ 85 86 struct c4iw_id_table { 87 u32 flags; 88 u32 start; /* logical minimal id */ 89 u32 last; /* hint for find */ 90 u32 max; 91 spinlock_t lock; 92 unsigned long *table; 93 }; 94 95 struct c4iw_resource { 96 struct c4iw_id_table tpt_table; 97 struct c4iw_id_table qid_table; 98 struct c4iw_id_table pdid_table; 99 }; 100 101 struct c4iw_qid_list { 102 struct list_head entry; 103 u32 qid; 104 }; 105 106 struct c4iw_dev_ucontext { 107 struct list_head qpids; 108 struct list_head cqids; 109 struct mutex lock; 110 }; 111 112 enum c4iw_rdev_flags { 113 T4_FATAL_ERROR = (1<<0), 114 T4_STATUS_PAGE_DISABLED = (1<<1), 115 }; 116 117 struct c4iw_stat { 118 u64 total; 119 u64 cur; 120 u64 max; 121 u64 fail; 122 }; 123 124 struct c4iw_stats { 125 struct mutex lock; 126 struct c4iw_stat qid; 127 struct c4iw_stat pd; 128 struct c4iw_stat stag; 129 struct c4iw_stat pbl; 130 struct c4iw_stat rqt; 131 struct c4iw_stat ocqp; 132 u64 db_full; 133 u64 db_empty; 134 u64 db_drop; 135 u64 db_state_transitions; 136 u64 db_fc_interruptions; 137 u64 tcam_full; 138 u64 act_ofld_conn_fails; 139 u64 pas_ofld_conn_fails; 140 }; 141 142 struct c4iw_hw_queue { 143 int t4_eq_status_entries; 144 int t4_max_eq_size; 145 int t4_max_iq_size; 146 int t4_max_rq_size; 147 int t4_max_sq_size; 148 int t4_max_qp_depth; 149 int t4_max_cq_depth; 150 int t4_stat_len; 151 }; 152 153 struct wr_log_entry { 154 struct timespec post_host_ts; 155 struct timespec poll_host_ts; 156 u64 post_sge_ts; 157 u64 cqe_sge_ts; 158 u64 poll_sge_ts; 159 u16 qid; 160 u16 wr_id; 161 u8 opcode; 162 u8 valid; 163 }; 164 165 struct c4iw_rdev { 166 struct c4iw_resource resource; 167 unsigned long qpshift; 168 u32 qpmask; 169 unsigned long cqshift; 170 u32 cqmask; 171 struct c4iw_dev_ucontext uctx; 172 struct gen_pool *pbl_pool; 173 struct gen_pool *rqt_pool; 174 struct gen_pool *ocqp_pool; 175 u32 flags; 176 struct cxgb4_lld_info lldi; 177 unsigned long bar2_pa; 178 void __iomem *bar2_kva; 179 unsigned long oc_mw_pa; 180 void __iomem *oc_mw_kva; 181 struct c4iw_stats stats; 182 struct c4iw_hw_queue hw_queue; 183 struct t4_dev_status_page *status_page; 184 atomic_t wr_log_idx; 185 struct wr_log_entry *wr_log; 186 int wr_log_size; 187 }; 188 189 static inline int c4iw_fatal_error(struct c4iw_rdev *rdev) 190 { 191 return rdev->flags & T4_FATAL_ERROR; 192 } 193 194 static inline int c4iw_num_stags(struct c4iw_rdev *rdev) 195 { 196 return (int)(rdev->lldi.vr->stag.size >> 5); 197 } 198 199 #define C4IW_WR_TO (60*HZ) 200 201 struct c4iw_wr_wait { 202 struct completion completion; 203 int ret; 204 }; 205 206 static inline void c4iw_init_wr_wait(struct c4iw_wr_wait *wr_waitp) 207 { 208 wr_waitp->ret = 0; 209 init_completion(&wr_waitp->completion); 210 } 211 212 static inline void c4iw_wake_up(struct c4iw_wr_wait *wr_waitp, int ret) 213 { 214 wr_waitp->ret = ret; 215 complete(&wr_waitp->completion); 216 } 217 218 static inline int c4iw_wait_for_reply(struct c4iw_rdev *rdev, 219 struct c4iw_wr_wait *wr_waitp, 220 u32 hwtid, u32 qpid, 221 const char *func) 222 { 223 int ret; 224 225 if (c4iw_fatal_error(rdev)) { 226 wr_waitp->ret = -EIO; 227 goto out; 228 } 229 230 ret = wait_for_completion_timeout(&wr_waitp->completion, C4IW_WR_TO); 231 if (!ret) { 232 PDBG("%s - Device %s not responding (disabling device) - tid %u qpid %u\n", 233 func, pci_name(rdev->lldi.pdev), hwtid, qpid); 234 rdev->flags |= T4_FATAL_ERROR; 235 wr_waitp->ret = -EIO; 236 } 237 out: 238 if (wr_waitp->ret) 239 PDBG("%s: FW reply %d tid %u qpid %u\n", 240 pci_name(rdev->lldi.pdev), wr_waitp->ret, hwtid, qpid); 241 return wr_waitp->ret; 242 } 243 244 enum db_state { 245 NORMAL = 0, 246 FLOW_CONTROL = 1, 247 RECOVERY = 2, 248 STOPPED = 3 249 }; 250 251 struct c4iw_dev { 252 struct ib_device ibdev; 253 struct c4iw_rdev rdev; 254 u32 device_cap_flags; 255 struct idr cqidr; 256 struct idr qpidr; 257 struct idr mmidr; 258 spinlock_t lock; 259 struct mutex db_mutex; 260 struct dentry *debugfs_root; 261 enum db_state db_state; 262 struct idr hwtid_idr; 263 struct idr atid_idr; 264 struct idr stid_idr; 265 struct list_head db_fc_list; 266 u32 avail_ird; 267 }; 268 269 static inline struct c4iw_dev *to_c4iw_dev(struct ib_device *ibdev) 270 { 271 return container_of(ibdev, struct c4iw_dev, ibdev); 272 } 273 274 static inline struct c4iw_dev *rdev_to_c4iw_dev(struct c4iw_rdev *rdev) 275 { 276 return container_of(rdev, struct c4iw_dev, rdev); 277 } 278 279 static inline struct c4iw_cq *get_chp(struct c4iw_dev *rhp, u32 cqid) 280 { 281 return idr_find(&rhp->cqidr, cqid); 282 } 283 284 static inline struct c4iw_qp *get_qhp(struct c4iw_dev *rhp, u32 qpid) 285 { 286 return idr_find(&rhp->qpidr, qpid); 287 } 288 289 static inline struct c4iw_mr *get_mhp(struct c4iw_dev *rhp, u32 mmid) 290 { 291 return idr_find(&rhp->mmidr, mmid); 292 } 293 294 static inline int _insert_handle(struct c4iw_dev *rhp, struct idr *idr, 295 void *handle, u32 id, int lock) 296 { 297 int ret; 298 299 if (lock) { 300 idr_preload(GFP_KERNEL); 301 spin_lock_irq(&rhp->lock); 302 } 303 304 ret = idr_alloc(idr, handle, id, id + 1, GFP_ATOMIC); 305 306 if (lock) { 307 spin_unlock_irq(&rhp->lock); 308 idr_preload_end(); 309 } 310 311 BUG_ON(ret == -ENOSPC); 312 return ret < 0 ? ret : 0; 313 } 314 315 static inline int insert_handle(struct c4iw_dev *rhp, struct idr *idr, 316 void *handle, u32 id) 317 { 318 return _insert_handle(rhp, idr, handle, id, 1); 319 } 320 321 static inline int insert_handle_nolock(struct c4iw_dev *rhp, struct idr *idr, 322 void *handle, u32 id) 323 { 324 return _insert_handle(rhp, idr, handle, id, 0); 325 } 326 327 static inline void _remove_handle(struct c4iw_dev *rhp, struct idr *idr, 328 u32 id, int lock) 329 { 330 if (lock) 331 spin_lock_irq(&rhp->lock); 332 idr_remove(idr, id); 333 if (lock) 334 spin_unlock_irq(&rhp->lock); 335 } 336 337 static inline void remove_handle(struct c4iw_dev *rhp, struct idr *idr, u32 id) 338 { 339 _remove_handle(rhp, idr, id, 1); 340 } 341 342 static inline void remove_handle_nolock(struct c4iw_dev *rhp, 343 struct idr *idr, u32 id) 344 { 345 _remove_handle(rhp, idr, id, 0); 346 } 347 348 extern uint c4iw_max_read_depth; 349 350 static inline int cur_max_read_depth(struct c4iw_dev *dev) 351 { 352 return min(dev->rdev.lldi.max_ordird_qp, c4iw_max_read_depth); 353 } 354 355 struct c4iw_pd { 356 struct ib_pd ibpd; 357 u32 pdid; 358 struct c4iw_dev *rhp; 359 }; 360 361 static inline struct c4iw_pd *to_c4iw_pd(struct ib_pd *ibpd) 362 { 363 return container_of(ibpd, struct c4iw_pd, ibpd); 364 } 365 366 struct tpt_attributes { 367 u64 len; 368 u64 va_fbo; 369 enum fw_ri_mem_perms perms; 370 u32 stag; 371 u32 pdid; 372 u32 qpid; 373 u32 pbl_addr; 374 u32 pbl_size; 375 u32 state:1; 376 u32 type:2; 377 u32 rsvd:1; 378 u32 remote_invaliate_disable:1; 379 u32 zbva:1; 380 u32 mw_bind_enable:1; 381 u32 page_size:5; 382 }; 383 384 struct c4iw_mr { 385 struct ib_mr ibmr; 386 struct ib_umem *umem; 387 struct c4iw_dev *rhp; 388 u64 kva; 389 struct tpt_attributes attr; 390 }; 391 392 static inline struct c4iw_mr *to_c4iw_mr(struct ib_mr *ibmr) 393 { 394 return container_of(ibmr, struct c4iw_mr, ibmr); 395 } 396 397 struct c4iw_mw { 398 struct ib_mw ibmw; 399 struct c4iw_dev *rhp; 400 u64 kva; 401 struct tpt_attributes attr; 402 }; 403 404 static inline struct c4iw_mw *to_c4iw_mw(struct ib_mw *ibmw) 405 { 406 return container_of(ibmw, struct c4iw_mw, ibmw); 407 } 408 409 struct c4iw_fr_page_list { 410 struct ib_fast_reg_page_list ibpl; 411 DEFINE_DMA_UNMAP_ADDR(mapping); 412 dma_addr_t dma_addr; 413 struct c4iw_dev *dev; 414 int pll_len; 415 }; 416 417 static inline struct c4iw_fr_page_list *to_c4iw_fr_page_list( 418 struct ib_fast_reg_page_list *ibpl) 419 { 420 return container_of(ibpl, struct c4iw_fr_page_list, ibpl); 421 } 422 423 struct c4iw_cq { 424 struct ib_cq ibcq; 425 struct c4iw_dev *rhp; 426 struct t4_cq cq; 427 spinlock_t lock; 428 spinlock_t comp_handler_lock; 429 atomic_t refcnt; 430 wait_queue_head_t wait; 431 }; 432 433 static inline struct c4iw_cq *to_c4iw_cq(struct ib_cq *ibcq) 434 { 435 return container_of(ibcq, struct c4iw_cq, ibcq); 436 } 437 438 struct c4iw_mpa_attributes { 439 u8 initiator; 440 u8 recv_marker_enabled; 441 u8 xmit_marker_enabled; 442 u8 crc_enabled; 443 u8 enhanced_rdma_conn; 444 u8 version; 445 u8 p2p_type; 446 }; 447 448 struct c4iw_qp_attributes { 449 u32 scq; 450 u32 rcq; 451 u32 sq_num_entries; 452 u32 rq_num_entries; 453 u32 sq_max_sges; 454 u32 sq_max_sges_rdma_write; 455 u32 rq_max_sges; 456 u32 state; 457 u8 enable_rdma_read; 458 u8 enable_rdma_write; 459 u8 enable_bind; 460 u8 enable_mmid0_fastreg; 461 u32 max_ord; 462 u32 max_ird; 463 u32 pd; 464 u32 next_state; 465 char terminate_buffer[52]; 466 u32 terminate_msg_len; 467 u8 is_terminate_local; 468 struct c4iw_mpa_attributes mpa_attr; 469 struct c4iw_ep *llp_stream_handle; 470 u8 layer_etype; 471 u8 ecode; 472 u16 sq_db_inc; 473 u16 rq_db_inc; 474 u8 send_term; 475 }; 476 477 struct c4iw_qp { 478 struct ib_qp ibqp; 479 struct list_head db_fc_entry; 480 struct c4iw_dev *rhp; 481 struct c4iw_ep *ep; 482 struct c4iw_qp_attributes attr; 483 struct t4_wq wq; 484 spinlock_t lock; 485 struct mutex mutex; 486 atomic_t refcnt; 487 wait_queue_head_t wait; 488 struct timer_list timer; 489 int sq_sig_all; 490 }; 491 492 static inline struct c4iw_qp *to_c4iw_qp(struct ib_qp *ibqp) 493 { 494 return container_of(ibqp, struct c4iw_qp, ibqp); 495 } 496 497 struct c4iw_ucontext { 498 struct ib_ucontext ibucontext; 499 struct c4iw_dev_ucontext uctx; 500 u32 key; 501 spinlock_t mmap_lock; 502 struct list_head mmaps; 503 }; 504 505 static inline struct c4iw_ucontext *to_c4iw_ucontext(struct ib_ucontext *c) 506 { 507 return container_of(c, struct c4iw_ucontext, ibucontext); 508 } 509 510 struct c4iw_mm_entry { 511 struct list_head entry; 512 u64 addr; 513 u32 key; 514 unsigned len; 515 }; 516 517 static inline struct c4iw_mm_entry *remove_mmap(struct c4iw_ucontext *ucontext, 518 u32 key, unsigned len) 519 { 520 struct list_head *pos, *nxt; 521 struct c4iw_mm_entry *mm; 522 523 spin_lock(&ucontext->mmap_lock); 524 list_for_each_safe(pos, nxt, &ucontext->mmaps) { 525 526 mm = list_entry(pos, struct c4iw_mm_entry, entry); 527 if (mm->key == key && mm->len == len) { 528 list_del_init(&mm->entry); 529 spin_unlock(&ucontext->mmap_lock); 530 PDBG("%s key 0x%x addr 0x%llx len %d\n", __func__, 531 key, (unsigned long long) mm->addr, mm->len); 532 return mm; 533 } 534 } 535 spin_unlock(&ucontext->mmap_lock); 536 return NULL; 537 } 538 539 static inline void insert_mmap(struct c4iw_ucontext *ucontext, 540 struct c4iw_mm_entry *mm) 541 { 542 spin_lock(&ucontext->mmap_lock); 543 PDBG("%s key 0x%x addr 0x%llx len %d\n", __func__, 544 mm->key, (unsigned long long) mm->addr, mm->len); 545 list_add_tail(&mm->entry, &ucontext->mmaps); 546 spin_unlock(&ucontext->mmap_lock); 547 } 548 549 enum c4iw_qp_attr_mask { 550 C4IW_QP_ATTR_NEXT_STATE = 1 << 0, 551 C4IW_QP_ATTR_SQ_DB = 1<<1, 552 C4IW_QP_ATTR_RQ_DB = 1<<2, 553 C4IW_QP_ATTR_ENABLE_RDMA_READ = 1 << 7, 554 C4IW_QP_ATTR_ENABLE_RDMA_WRITE = 1 << 8, 555 C4IW_QP_ATTR_ENABLE_RDMA_BIND = 1 << 9, 556 C4IW_QP_ATTR_MAX_ORD = 1 << 11, 557 C4IW_QP_ATTR_MAX_IRD = 1 << 12, 558 C4IW_QP_ATTR_LLP_STREAM_HANDLE = 1 << 22, 559 C4IW_QP_ATTR_STREAM_MSG_BUFFER = 1 << 23, 560 C4IW_QP_ATTR_MPA_ATTR = 1 << 24, 561 C4IW_QP_ATTR_QP_CONTEXT_ACTIVATE = 1 << 25, 562 C4IW_QP_ATTR_VALID_MODIFY = (C4IW_QP_ATTR_ENABLE_RDMA_READ | 563 C4IW_QP_ATTR_ENABLE_RDMA_WRITE | 564 C4IW_QP_ATTR_MAX_ORD | 565 C4IW_QP_ATTR_MAX_IRD | 566 C4IW_QP_ATTR_LLP_STREAM_HANDLE | 567 C4IW_QP_ATTR_STREAM_MSG_BUFFER | 568 C4IW_QP_ATTR_MPA_ATTR | 569 C4IW_QP_ATTR_QP_CONTEXT_ACTIVATE) 570 }; 571 572 int c4iw_modify_qp(struct c4iw_dev *rhp, 573 struct c4iw_qp *qhp, 574 enum c4iw_qp_attr_mask mask, 575 struct c4iw_qp_attributes *attrs, 576 int internal); 577 578 enum c4iw_qp_state { 579 C4IW_QP_STATE_IDLE, 580 C4IW_QP_STATE_RTS, 581 C4IW_QP_STATE_ERROR, 582 C4IW_QP_STATE_TERMINATE, 583 C4IW_QP_STATE_CLOSING, 584 C4IW_QP_STATE_TOT 585 }; 586 587 static inline int c4iw_convert_state(enum ib_qp_state ib_state) 588 { 589 switch (ib_state) { 590 case IB_QPS_RESET: 591 case IB_QPS_INIT: 592 return C4IW_QP_STATE_IDLE; 593 case IB_QPS_RTS: 594 return C4IW_QP_STATE_RTS; 595 case IB_QPS_SQD: 596 return C4IW_QP_STATE_CLOSING; 597 case IB_QPS_SQE: 598 return C4IW_QP_STATE_TERMINATE; 599 case IB_QPS_ERR: 600 return C4IW_QP_STATE_ERROR; 601 default: 602 return -1; 603 } 604 } 605 606 static inline int to_ib_qp_state(int c4iw_qp_state) 607 { 608 switch (c4iw_qp_state) { 609 case C4IW_QP_STATE_IDLE: 610 return IB_QPS_INIT; 611 case C4IW_QP_STATE_RTS: 612 return IB_QPS_RTS; 613 case C4IW_QP_STATE_CLOSING: 614 return IB_QPS_SQD; 615 case C4IW_QP_STATE_TERMINATE: 616 return IB_QPS_SQE; 617 case C4IW_QP_STATE_ERROR: 618 return IB_QPS_ERR; 619 } 620 return IB_QPS_ERR; 621 } 622 623 static inline u32 c4iw_ib_to_tpt_access(int a) 624 { 625 return (a & IB_ACCESS_REMOTE_WRITE ? FW_RI_MEM_ACCESS_REM_WRITE : 0) | 626 (a & IB_ACCESS_REMOTE_READ ? FW_RI_MEM_ACCESS_REM_READ : 0) | 627 (a & IB_ACCESS_LOCAL_WRITE ? FW_RI_MEM_ACCESS_LOCAL_WRITE : 0) | 628 FW_RI_MEM_ACCESS_LOCAL_READ; 629 } 630 631 static inline u32 c4iw_ib_to_tpt_bind_access(int acc) 632 { 633 return (acc & IB_ACCESS_REMOTE_WRITE ? FW_RI_MEM_ACCESS_REM_WRITE : 0) | 634 (acc & IB_ACCESS_REMOTE_READ ? FW_RI_MEM_ACCESS_REM_READ : 0); 635 } 636 637 enum c4iw_mmid_state { 638 C4IW_STAG_STATE_VALID, 639 C4IW_STAG_STATE_INVALID 640 }; 641 642 #define C4IW_NODE_DESC "cxgb4 Chelsio Communications" 643 644 #define MPA_KEY_REQ "MPA ID Req Frame" 645 #define MPA_KEY_REP "MPA ID Rep Frame" 646 647 #define MPA_MAX_PRIVATE_DATA 256 648 #define MPA_ENHANCED_RDMA_CONN 0x10 649 #define MPA_REJECT 0x20 650 #define MPA_CRC 0x40 651 #define MPA_MARKERS 0x80 652 #define MPA_FLAGS_MASK 0xE0 653 654 #define MPA_V2_PEER2PEER_MODEL 0x8000 655 #define MPA_V2_ZERO_LEN_FPDU_RTR 0x4000 656 #define MPA_V2_RDMA_WRITE_RTR 0x8000 657 #define MPA_V2_RDMA_READ_RTR 0x4000 658 #define MPA_V2_IRD_ORD_MASK 0x3FFF 659 660 #define c4iw_put_ep(ep) { \ 661 PDBG("put_ep (via %s:%u) ep %p refcnt %d\n", __func__, __LINE__, \ 662 ep, atomic_read(&((ep)->kref.refcount))); \ 663 WARN_ON(atomic_read(&((ep)->kref.refcount)) < 1); \ 664 kref_put(&((ep)->kref), _c4iw_free_ep); \ 665 } 666 667 #define c4iw_get_ep(ep) { \ 668 PDBG("get_ep (via %s:%u) ep %p, refcnt %d\n", __func__, __LINE__, \ 669 ep, atomic_read(&((ep)->kref.refcount))); \ 670 kref_get(&((ep)->kref)); \ 671 } 672 void _c4iw_free_ep(struct kref *kref); 673 674 struct mpa_message { 675 u8 key[16]; 676 u8 flags; 677 u8 revision; 678 __be16 private_data_size; 679 u8 private_data[0]; 680 }; 681 682 struct mpa_v2_conn_params { 683 __be16 ird; 684 __be16 ord; 685 }; 686 687 struct terminate_message { 688 u8 layer_etype; 689 u8 ecode; 690 __be16 hdrct_rsvd; 691 u8 len_hdrs[0]; 692 }; 693 694 #define TERM_MAX_LENGTH (sizeof(struct terminate_message) + 2 + 18 + 28) 695 696 enum c4iw_layers_types { 697 LAYER_RDMAP = 0x00, 698 LAYER_DDP = 0x10, 699 LAYER_MPA = 0x20, 700 RDMAP_LOCAL_CATA = 0x00, 701 RDMAP_REMOTE_PROT = 0x01, 702 RDMAP_REMOTE_OP = 0x02, 703 DDP_LOCAL_CATA = 0x00, 704 DDP_TAGGED_ERR = 0x01, 705 DDP_UNTAGGED_ERR = 0x02, 706 DDP_LLP = 0x03 707 }; 708 709 enum c4iw_rdma_ecodes { 710 RDMAP_INV_STAG = 0x00, 711 RDMAP_BASE_BOUNDS = 0x01, 712 RDMAP_ACC_VIOL = 0x02, 713 RDMAP_STAG_NOT_ASSOC = 0x03, 714 RDMAP_TO_WRAP = 0x04, 715 RDMAP_INV_VERS = 0x05, 716 RDMAP_INV_OPCODE = 0x06, 717 RDMAP_STREAM_CATA = 0x07, 718 RDMAP_GLOBAL_CATA = 0x08, 719 RDMAP_CANT_INV_STAG = 0x09, 720 RDMAP_UNSPECIFIED = 0xff 721 }; 722 723 enum c4iw_ddp_ecodes { 724 DDPT_INV_STAG = 0x00, 725 DDPT_BASE_BOUNDS = 0x01, 726 DDPT_STAG_NOT_ASSOC = 0x02, 727 DDPT_TO_WRAP = 0x03, 728 DDPT_INV_VERS = 0x04, 729 DDPU_INV_QN = 0x01, 730 DDPU_INV_MSN_NOBUF = 0x02, 731 DDPU_INV_MSN_RANGE = 0x03, 732 DDPU_INV_MO = 0x04, 733 DDPU_MSG_TOOBIG = 0x05, 734 DDPU_INV_VERS = 0x06 735 }; 736 737 enum c4iw_mpa_ecodes { 738 MPA_CRC_ERR = 0x02, 739 MPA_MARKER_ERR = 0x03, 740 MPA_LOCAL_CATA = 0x05, 741 MPA_INSUFF_IRD = 0x06, 742 MPA_NOMATCH_RTR = 0x07, 743 }; 744 745 enum c4iw_ep_state { 746 IDLE = 0, 747 LISTEN, 748 CONNECTING, 749 MPA_REQ_WAIT, 750 MPA_REQ_SENT, 751 MPA_REQ_RCVD, 752 MPA_REP_SENT, 753 FPDU_MODE, 754 ABORTING, 755 CLOSING, 756 MORIBUND, 757 DEAD, 758 }; 759 760 enum c4iw_ep_flags { 761 PEER_ABORT_IN_PROGRESS = 0, 762 ABORT_REQ_IN_PROGRESS = 1, 763 RELEASE_RESOURCES = 2, 764 CLOSE_SENT = 3, 765 TIMEOUT = 4, 766 QP_REFERENCED = 5, 767 RELEASE_MAPINFO = 6, 768 }; 769 770 enum c4iw_ep_history { 771 ACT_OPEN_REQ = 0, 772 ACT_OFLD_CONN = 1, 773 ACT_OPEN_RPL = 2, 774 ACT_ESTAB = 3, 775 PASS_ACCEPT_REQ = 4, 776 PASS_ESTAB = 5, 777 ABORT_UPCALL = 6, 778 ESTAB_UPCALL = 7, 779 CLOSE_UPCALL = 8, 780 ULP_ACCEPT = 9, 781 ULP_REJECT = 10, 782 TIMEDOUT = 11, 783 PEER_ABORT = 12, 784 PEER_CLOSE = 13, 785 CONNREQ_UPCALL = 14, 786 ABORT_CONN = 15, 787 DISCONN_UPCALL = 16, 788 EP_DISC_CLOSE = 17, 789 EP_DISC_ABORT = 18, 790 CONN_RPL_UPCALL = 19, 791 ACT_RETRY_NOMEM = 20, 792 ACT_RETRY_INUSE = 21 793 }; 794 795 struct c4iw_ep_common { 796 struct iw_cm_id *cm_id; 797 struct c4iw_qp *qp; 798 struct c4iw_dev *dev; 799 enum c4iw_ep_state state; 800 struct kref kref; 801 struct mutex mutex; 802 struct sockaddr_storage local_addr; 803 struct sockaddr_storage remote_addr; 804 struct sockaddr_storage mapped_local_addr; 805 struct sockaddr_storage mapped_remote_addr; 806 struct c4iw_wr_wait wr_wait; 807 unsigned long flags; 808 unsigned long history; 809 }; 810 811 struct c4iw_listen_ep { 812 struct c4iw_ep_common com; 813 unsigned int stid; 814 int backlog; 815 }; 816 817 struct c4iw_ep { 818 struct c4iw_ep_common com; 819 struct c4iw_ep *parent_ep; 820 struct timer_list timer; 821 struct list_head entry; 822 unsigned int atid; 823 u32 hwtid; 824 u32 snd_seq; 825 u32 rcv_seq; 826 struct l2t_entry *l2t; 827 struct dst_entry *dst; 828 struct sk_buff *mpa_skb; 829 struct c4iw_mpa_attributes mpa_attr; 830 u8 mpa_pkt[sizeof(struct mpa_message) + MPA_MAX_PRIVATE_DATA]; 831 unsigned int mpa_pkt_len; 832 u32 ird; 833 u32 ord; 834 u32 smac_idx; 835 u32 tx_chan; 836 u32 mtu; 837 u16 mss; 838 u16 emss; 839 u16 plen; 840 u16 rss_qid; 841 u16 txq_idx; 842 u16 ctrlq_idx; 843 u8 tos; 844 u8 retry_with_mpa_v1; 845 u8 tried_with_mpa_v1; 846 unsigned int retry_count; 847 int snd_win; 848 int rcv_win; 849 }; 850 851 static inline void print_addr(struct c4iw_ep_common *epc, const char *func, 852 const char *msg) 853 { 854 855 #define SINA(a) (&(((struct sockaddr_in *)(a))->sin_addr.s_addr)) 856 #define SINP(a) ntohs(((struct sockaddr_in *)(a))->sin_port) 857 #define SIN6A(a) (&(((struct sockaddr_in6 *)(a))->sin6_addr)) 858 #define SIN6P(a) ntohs(((struct sockaddr_in6 *)(a))->sin6_port) 859 860 if (c4iw_debug) { 861 switch (epc->local_addr.ss_family) { 862 case AF_INET: 863 PDBG("%s %s %pI4:%u/%u <-> %pI4:%u/%u\n", 864 func, msg, SINA(&epc->local_addr), 865 SINP(&epc->local_addr), 866 SINP(&epc->mapped_local_addr), 867 SINA(&epc->remote_addr), 868 SINP(&epc->remote_addr), 869 SINP(&epc->mapped_remote_addr)); 870 break; 871 case AF_INET6: 872 PDBG("%s %s %pI6:%u/%u <-> %pI6:%u/%u\n", 873 func, msg, SIN6A(&epc->local_addr), 874 SIN6P(&epc->local_addr), 875 SIN6P(&epc->mapped_local_addr), 876 SIN6A(&epc->remote_addr), 877 SIN6P(&epc->remote_addr), 878 SIN6P(&epc->mapped_remote_addr)); 879 break; 880 default: 881 break; 882 } 883 } 884 #undef SINA 885 #undef SINP 886 #undef SIN6A 887 #undef SIN6P 888 } 889 890 static inline struct c4iw_ep *to_ep(struct iw_cm_id *cm_id) 891 { 892 return cm_id->provider_data; 893 } 894 895 static inline struct c4iw_listen_ep *to_listen_ep(struct iw_cm_id *cm_id) 896 { 897 return cm_id->provider_data; 898 } 899 900 static inline int compute_wscale(int win) 901 { 902 int wscale = 0; 903 904 while (wscale < 14 && (65535<<wscale) < win) 905 wscale++; 906 return wscale; 907 } 908 909 static inline int ocqp_supported(const struct cxgb4_lld_info *infop) 910 { 911 #if defined(__i386__) || defined(__x86_64__) || defined(CONFIG_PPC64) 912 return infop->vr->ocq.size > 0; 913 #else 914 return 0; 915 #endif 916 } 917 918 u32 c4iw_id_alloc(struct c4iw_id_table *alloc); 919 void c4iw_id_free(struct c4iw_id_table *alloc, u32 obj); 920 int c4iw_id_table_alloc(struct c4iw_id_table *alloc, u32 start, u32 num, 921 u32 reserved, u32 flags); 922 void c4iw_id_table_free(struct c4iw_id_table *alloc); 923 924 typedef int (*c4iw_handler_func)(struct c4iw_dev *dev, struct sk_buff *skb); 925 926 int c4iw_ep_redirect(void *ctx, struct dst_entry *old, struct dst_entry *new, 927 struct l2t_entry *l2t); 928 void c4iw_put_qpid(struct c4iw_rdev *rdev, u32 qpid, 929 struct c4iw_dev_ucontext *uctx); 930 u32 c4iw_get_resource(struct c4iw_id_table *id_table); 931 void c4iw_put_resource(struct c4iw_id_table *id_table, u32 entry); 932 int c4iw_init_resource(struct c4iw_rdev *rdev, u32 nr_tpt, u32 nr_pdid); 933 int c4iw_init_ctrl_qp(struct c4iw_rdev *rdev); 934 int c4iw_pblpool_create(struct c4iw_rdev *rdev); 935 int c4iw_rqtpool_create(struct c4iw_rdev *rdev); 936 int c4iw_ocqp_pool_create(struct c4iw_rdev *rdev); 937 void c4iw_pblpool_destroy(struct c4iw_rdev *rdev); 938 void c4iw_rqtpool_destroy(struct c4iw_rdev *rdev); 939 void c4iw_ocqp_pool_destroy(struct c4iw_rdev *rdev); 940 void c4iw_destroy_resource(struct c4iw_resource *rscp); 941 int c4iw_destroy_ctrl_qp(struct c4iw_rdev *rdev); 942 int c4iw_register_device(struct c4iw_dev *dev); 943 void c4iw_unregister_device(struct c4iw_dev *dev); 944 int __init c4iw_cm_init(void); 945 void c4iw_cm_term(void); 946 void c4iw_release_dev_ucontext(struct c4iw_rdev *rdev, 947 struct c4iw_dev_ucontext *uctx); 948 void c4iw_init_dev_ucontext(struct c4iw_rdev *rdev, 949 struct c4iw_dev_ucontext *uctx); 950 int c4iw_poll_cq(struct ib_cq *ibcq, int num_entries, struct ib_wc *wc); 951 int c4iw_post_send(struct ib_qp *ibqp, struct ib_send_wr *wr, 952 struct ib_send_wr **bad_wr); 953 int c4iw_post_receive(struct ib_qp *ibqp, struct ib_recv_wr *wr, 954 struct ib_recv_wr **bad_wr); 955 int c4iw_bind_mw(struct ib_qp *qp, struct ib_mw *mw, 956 struct ib_mw_bind *mw_bind); 957 int c4iw_connect(struct iw_cm_id *cm_id, struct iw_cm_conn_param *conn_param); 958 int c4iw_create_listen(struct iw_cm_id *cm_id, int backlog); 959 int c4iw_destroy_listen(struct iw_cm_id *cm_id); 960 int c4iw_accept_cr(struct iw_cm_id *cm_id, struct iw_cm_conn_param *conn_param); 961 int c4iw_reject_cr(struct iw_cm_id *cm_id, const void *pdata, u8 pdata_len); 962 void c4iw_qp_add_ref(struct ib_qp *qp); 963 void c4iw_qp_rem_ref(struct ib_qp *qp); 964 void c4iw_free_fastreg_pbl(struct ib_fast_reg_page_list *page_list); 965 struct ib_fast_reg_page_list *c4iw_alloc_fastreg_pbl( 966 struct ib_device *device, 967 int page_list_len); 968 struct ib_mr *c4iw_alloc_fast_reg_mr(struct ib_pd *pd, int pbl_depth); 969 int c4iw_dealloc_mw(struct ib_mw *mw); 970 struct ib_mw *c4iw_alloc_mw(struct ib_pd *pd, enum ib_mw_type type); 971 struct ib_mr *c4iw_reg_user_mr(struct ib_pd *pd, u64 start, 972 u64 length, u64 virt, int acc, 973 struct ib_udata *udata); 974 struct ib_mr *c4iw_get_dma_mr(struct ib_pd *pd, int acc); 975 struct ib_mr *c4iw_register_phys_mem(struct ib_pd *pd, 976 struct ib_phys_buf *buffer_list, 977 int num_phys_buf, 978 int acc, 979 u64 *iova_start); 980 int c4iw_reregister_phys_mem(struct ib_mr *mr, 981 int mr_rereg_mask, 982 struct ib_pd *pd, 983 struct ib_phys_buf *buffer_list, 984 int num_phys_buf, 985 int acc, u64 *iova_start); 986 int c4iw_dereg_mr(struct ib_mr *ib_mr); 987 int c4iw_destroy_cq(struct ib_cq *ib_cq); 988 struct ib_cq *c4iw_create_cq(struct ib_device *ibdev, int entries, 989 int vector, 990 struct ib_ucontext *ib_context, 991 struct ib_udata *udata); 992 int c4iw_resize_cq(struct ib_cq *cq, int cqe, struct ib_udata *udata); 993 int c4iw_arm_cq(struct ib_cq *ibcq, enum ib_cq_notify_flags flags); 994 int c4iw_destroy_qp(struct ib_qp *ib_qp); 995 struct ib_qp *c4iw_create_qp(struct ib_pd *pd, 996 struct ib_qp_init_attr *attrs, 997 struct ib_udata *udata); 998 int c4iw_ib_modify_qp(struct ib_qp *ibqp, struct ib_qp_attr *attr, 999 int attr_mask, struct ib_udata *udata); 1000 int c4iw_ib_query_qp(struct ib_qp *ibqp, struct ib_qp_attr *attr, 1001 int attr_mask, struct ib_qp_init_attr *init_attr); 1002 struct ib_qp *c4iw_get_qp(struct ib_device *dev, int qpn); 1003 u32 c4iw_rqtpool_alloc(struct c4iw_rdev *rdev, int size); 1004 void c4iw_rqtpool_free(struct c4iw_rdev *rdev, u32 addr, int size); 1005 u32 c4iw_pblpool_alloc(struct c4iw_rdev *rdev, int size); 1006 void c4iw_pblpool_free(struct c4iw_rdev *rdev, u32 addr, int size); 1007 u32 c4iw_ocqp_pool_alloc(struct c4iw_rdev *rdev, int size); 1008 void c4iw_ocqp_pool_free(struct c4iw_rdev *rdev, u32 addr, int size); 1009 int c4iw_ofld_send(struct c4iw_rdev *rdev, struct sk_buff *skb); 1010 void c4iw_flush_hw_cq(struct c4iw_cq *chp); 1011 void c4iw_count_rcqes(struct t4_cq *cq, struct t4_wq *wq, int *count); 1012 int c4iw_ep_disconnect(struct c4iw_ep *ep, int abrupt, gfp_t gfp); 1013 int c4iw_flush_rq(struct t4_wq *wq, struct t4_cq *cq, int count); 1014 int c4iw_flush_sq(struct c4iw_qp *qhp); 1015 int c4iw_ev_handler(struct c4iw_dev *rnicp, u32 qid); 1016 u16 c4iw_rqes_posted(struct c4iw_qp *qhp); 1017 int c4iw_post_terminate(struct c4iw_qp *qhp, struct t4_cqe *err_cqe); 1018 u32 c4iw_get_cqid(struct c4iw_rdev *rdev, struct c4iw_dev_ucontext *uctx); 1019 void c4iw_put_cqid(struct c4iw_rdev *rdev, u32 qid, 1020 struct c4iw_dev_ucontext *uctx); 1021 u32 c4iw_get_qpid(struct c4iw_rdev *rdev, struct c4iw_dev_ucontext *uctx); 1022 void c4iw_put_qpid(struct c4iw_rdev *rdev, u32 qid, 1023 struct c4iw_dev_ucontext *uctx); 1024 void c4iw_ev_dispatch(struct c4iw_dev *dev, struct t4_cqe *err_cqe); 1025 1026 extern struct cxgb4_client t4c_client; 1027 extern c4iw_handler_func c4iw_handlers[NUM_CPL_CMDS]; 1028 extern void c4iw_log_wr_stats(struct t4_wq *wq, struct t4_cqe *cqe); 1029 extern int c4iw_wr_log; 1030 extern int db_fc_threshold; 1031 extern int db_coalescing_threshold; 1032 extern int use_dsgl; 1033 1034 1035 #endif 1036