1 /* 2 * Copyright (c) 2009-2010 Chelsio, Inc. All rights reserved. 3 * 4 * This software is available to you under a choice of one of two 5 * licenses. You may choose to be licensed under the terms of the GNU 6 * General Public License (GPL) Version 2, available from the file 7 * COPYING in the main directory of this source tree, or the 8 * OpenIB.org BSD license below: 9 * 10 * Redistribution and use in source and binary forms, with or 11 * without modification, are permitted provided that the following 12 * conditions are met: 13 * 14 * - Redistributions of source code must retain the above 15 * copyright notice, this list of conditions and the following 16 * disclaimer. 17 * - Redistributions in binary form must reproduce the above 18 * copyright notice, this list of conditions and the following 19 * disclaimer in the documentation and/or other materials 20 * provided with the distribution. 21 * 22 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, 23 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF 24 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND 25 * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS 26 * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN 27 * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN 28 * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE 29 * SOFTWARE. 30 */ 31 #ifndef __IW_CXGB4_H__ 32 #define __IW_CXGB4_H__ 33 34 #include <linux/mutex.h> 35 #include <linux/list.h> 36 #include <linux/spinlock.h> 37 #include <linux/idr.h> 38 #include <linux/completion.h> 39 #include <linux/netdevice.h> 40 #include <linux/sched.h> 41 #include <linux/pci.h> 42 #include <linux/dma-mapping.h> 43 #include <linux/inet.h> 44 #include <linux/wait.h> 45 #include <linux/kref.h> 46 #include <linux/timer.h> 47 #include <linux/io.h> 48 49 #include <asm/byteorder.h> 50 51 #include <net/net_namespace.h> 52 53 #include <rdma/ib_verbs.h> 54 #include <rdma/iw_cm.h> 55 #include <rdma/rdma_netlink.h> 56 #include <rdma/iw_portmap.h> 57 58 #include "cxgb4.h" 59 #include "cxgb4_uld.h" 60 #include "l2t.h" 61 #include "user.h" 62 63 #define DRV_NAME "iw_cxgb4" 64 #define MOD DRV_NAME ":" 65 66 extern int c4iw_debug; 67 #define PDBG(fmt, args...) \ 68 do { \ 69 if (c4iw_debug) \ 70 printk(MOD fmt, ## args); \ 71 } while (0) 72 73 #include "t4.h" 74 75 #define PBL_OFF(rdev_p, a) ((a) - (rdev_p)->lldi.vr->pbl.start) 76 #define RQT_OFF(rdev_p, a) ((a) - (rdev_p)->lldi.vr->rq.start) 77 78 static inline void *cplhdr(struct sk_buff *skb) 79 { 80 return skb->data; 81 } 82 83 #define C4IW_ID_TABLE_F_RANDOM 1 /* Pseudo-randomize the id's returned */ 84 #define C4IW_ID_TABLE_F_EMPTY 2 /* Table is initially empty */ 85 86 struct c4iw_id_table { 87 u32 flags; 88 u32 start; /* logical minimal id */ 89 u32 last; /* hint for find */ 90 u32 max; 91 spinlock_t lock; 92 unsigned long *table; 93 }; 94 95 struct c4iw_resource { 96 struct c4iw_id_table tpt_table; 97 struct c4iw_id_table qid_table; 98 struct c4iw_id_table pdid_table; 99 }; 100 101 struct c4iw_qid_list { 102 struct list_head entry; 103 u32 qid; 104 }; 105 106 struct c4iw_dev_ucontext { 107 struct list_head qpids; 108 struct list_head cqids; 109 struct mutex lock; 110 }; 111 112 enum c4iw_rdev_flags { 113 T4_FATAL_ERROR = (1<<0), 114 T4_STATUS_PAGE_DISABLED = (1<<1), 115 }; 116 117 struct c4iw_stat { 118 u64 total; 119 u64 cur; 120 u64 max; 121 u64 fail; 122 }; 123 124 struct c4iw_stats { 125 struct mutex lock; 126 struct c4iw_stat qid; 127 struct c4iw_stat pd; 128 struct c4iw_stat stag; 129 struct c4iw_stat pbl; 130 struct c4iw_stat rqt; 131 struct c4iw_stat ocqp; 132 u64 db_full; 133 u64 db_empty; 134 u64 db_drop; 135 u64 db_state_transitions; 136 u64 db_fc_interruptions; 137 u64 tcam_full; 138 u64 act_ofld_conn_fails; 139 u64 pas_ofld_conn_fails; 140 u64 neg_adv; 141 }; 142 143 struct c4iw_hw_queue { 144 int t4_eq_status_entries; 145 int t4_max_eq_size; 146 int t4_max_iq_size; 147 int t4_max_rq_size; 148 int t4_max_sq_size; 149 int t4_max_qp_depth; 150 int t4_max_cq_depth; 151 int t4_stat_len; 152 }; 153 154 struct wr_log_entry { 155 struct timespec post_host_ts; 156 struct timespec poll_host_ts; 157 u64 post_sge_ts; 158 u64 cqe_sge_ts; 159 u64 poll_sge_ts; 160 u16 qid; 161 u16 wr_id; 162 u8 opcode; 163 u8 valid; 164 }; 165 166 struct c4iw_rdev { 167 struct c4iw_resource resource; 168 u32 qpmask; 169 u32 cqmask; 170 struct c4iw_dev_ucontext uctx; 171 struct gen_pool *pbl_pool; 172 struct gen_pool *rqt_pool; 173 struct gen_pool *ocqp_pool; 174 u32 flags; 175 struct cxgb4_lld_info lldi; 176 unsigned long bar2_pa; 177 void __iomem *bar2_kva; 178 unsigned long oc_mw_pa; 179 void __iomem *oc_mw_kva; 180 struct c4iw_stats stats; 181 struct c4iw_hw_queue hw_queue; 182 struct t4_dev_status_page *status_page; 183 atomic_t wr_log_idx; 184 struct wr_log_entry *wr_log; 185 int wr_log_size; 186 }; 187 188 static inline int c4iw_fatal_error(struct c4iw_rdev *rdev) 189 { 190 return rdev->flags & T4_FATAL_ERROR; 191 } 192 193 static inline int c4iw_num_stags(struct c4iw_rdev *rdev) 194 { 195 return (int)(rdev->lldi.vr->stag.size >> 5); 196 } 197 198 #define C4IW_WR_TO (60*HZ) 199 200 struct c4iw_wr_wait { 201 struct completion completion; 202 int ret; 203 }; 204 205 static inline void c4iw_init_wr_wait(struct c4iw_wr_wait *wr_waitp) 206 { 207 wr_waitp->ret = 0; 208 init_completion(&wr_waitp->completion); 209 } 210 211 static inline void c4iw_wake_up(struct c4iw_wr_wait *wr_waitp, int ret) 212 { 213 wr_waitp->ret = ret; 214 complete(&wr_waitp->completion); 215 } 216 217 static inline int c4iw_wait_for_reply(struct c4iw_rdev *rdev, 218 struct c4iw_wr_wait *wr_waitp, 219 u32 hwtid, u32 qpid, 220 const char *func) 221 { 222 int ret; 223 224 if (c4iw_fatal_error(rdev)) { 225 wr_waitp->ret = -EIO; 226 goto out; 227 } 228 229 ret = wait_for_completion_timeout(&wr_waitp->completion, C4IW_WR_TO); 230 if (!ret) { 231 PDBG("%s - Device %s not responding (disabling device) - tid %u qpid %u\n", 232 func, pci_name(rdev->lldi.pdev), hwtid, qpid); 233 rdev->flags |= T4_FATAL_ERROR; 234 wr_waitp->ret = -EIO; 235 } 236 out: 237 if (wr_waitp->ret) 238 PDBG("%s: FW reply %d tid %u qpid %u\n", 239 pci_name(rdev->lldi.pdev), wr_waitp->ret, hwtid, qpid); 240 return wr_waitp->ret; 241 } 242 243 enum db_state { 244 NORMAL = 0, 245 FLOW_CONTROL = 1, 246 RECOVERY = 2, 247 STOPPED = 3 248 }; 249 250 struct c4iw_dev { 251 struct ib_device ibdev; 252 struct c4iw_rdev rdev; 253 u32 device_cap_flags; 254 struct idr cqidr; 255 struct idr qpidr; 256 struct idr mmidr; 257 spinlock_t lock; 258 struct mutex db_mutex; 259 struct dentry *debugfs_root; 260 enum db_state db_state; 261 struct idr hwtid_idr; 262 struct idr atid_idr; 263 struct idr stid_idr; 264 struct list_head db_fc_list; 265 u32 avail_ird; 266 }; 267 268 static inline struct c4iw_dev *to_c4iw_dev(struct ib_device *ibdev) 269 { 270 return container_of(ibdev, struct c4iw_dev, ibdev); 271 } 272 273 static inline struct c4iw_dev *rdev_to_c4iw_dev(struct c4iw_rdev *rdev) 274 { 275 return container_of(rdev, struct c4iw_dev, rdev); 276 } 277 278 static inline struct c4iw_cq *get_chp(struct c4iw_dev *rhp, u32 cqid) 279 { 280 return idr_find(&rhp->cqidr, cqid); 281 } 282 283 static inline struct c4iw_qp *get_qhp(struct c4iw_dev *rhp, u32 qpid) 284 { 285 return idr_find(&rhp->qpidr, qpid); 286 } 287 288 static inline struct c4iw_mr *get_mhp(struct c4iw_dev *rhp, u32 mmid) 289 { 290 return idr_find(&rhp->mmidr, mmid); 291 } 292 293 static inline int _insert_handle(struct c4iw_dev *rhp, struct idr *idr, 294 void *handle, u32 id, int lock) 295 { 296 int ret; 297 298 if (lock) { 299 idr_preload(GFP_KERNEL); 300 spin_lock_irq(&rhp->lock); 301 } 302 303 ret = idr_alloc(idr, handle, id, id + 1, GFP_ATOMIC); 304 305 if (lock) { 306 spin_unlock_irq(&rhp->lock); 307 idr_preload_end(); 308 } 309 310 BUG_ON(ret == -ENOSPC); 311 return ret < 0 ? ret : 0; 312 } 313 314 static inline int insert_handle(struct c4iw_dev *rhp, struct idr *idr, 315 void *handle, u32 id) 316 { 317 return _insert_handle(rhp, idr, handle, id, 1); 318 } 319 320 static inline int insert_handle_nolock(struct c4iw_dev *rhp, struct idr *idr, 321 void *handle, u32 id) 322 { 323 return _insert_handle(rhp, idr, handle, id, 0); 324 } 325 326 static inline void _remove_handle(struct c4iw_dev *rhp, struct idr *idr, 327 u32 id, int lock) 328 { 329 if (lock) 330 spin_lock_irq(&rhp->lock); 331 idr_remove(idr, id); 332 if (lock) 333 spin_unlock_irq(&rhp->lock); 334 } 335 336 static inline void remove_handle(struct c4iw_dev *rhp, struct idr *idr, u32 id) 337 { 338 _remove_handle(rhp, idr, id, 1); 339 } 340 341 static inline void remove_handle_nolock(struct c4iw_dev *rhp, 342 struct idr *idr, u32 id) 343 { 344 _remove_handle(rhp, idr, id, 0); 345 } 346 347 extern uint c4iw_max_read_depth; 348 349 static inline int cur_max_read_depth(struct c4iw_dev *dev) 350 { 351 return min(dev->rdev.lldi.max_ordird_qp, c4iw_max_read_depth); 352 } 353 354 struct c4iw_pd { 355 struct ib_pd ibpd; 356 u32 pdid; 357 struct c4iw_dev *rhp; 358 }; 359 360 static inline struct c4iw_pd *to_c4iw_pd(struct ib_pd *ibpd) 361 { 362 return container_of(ibpd, struct c4iw_pd, ibpd); 363 } 364 365 struct tpt_attributes { 366 u64 len; 367 u64 va_fbo; 368 enum fw_ri_mem_perms perms; 369 u32 stag; 370 u32 pdid; 371 u32 qpid; 372 u32 pbl_addr; 373 u32 pbl_size; 374 u32 state:1; 375 u32 type:2; 376 u32 rsvd:1; 377 u32 remote_invaliate_disable:1; 378 u32 zbva:1; 379 u32 mw_bind_enable:1; 380 u32 page_size:5; 381 }; 382 383 struct c4iw_mr { 384 struct ib_mr ibmr; 385 struct ib_umem *umem; 386 struct c4iw_dev *rhp; 387 struct sk_buff *dereg_skb; 388 u64 kva; 389 struct tpt_attributes attr; 390 u64 *mpl; 391 dma_addr_t mpl_addr; 392 u32 max_mpl_len; 393 u32 mpl_len; 394 }; 395 396 static inline struct c4iw_mr *to_c4iw_mr(struct ib_mr *ibmr) 397 { 398 return container_of(ibmr, struct c4iw_mr, ibmr); 399 } 400 401 struct c4iw_mw { 402 struct ib_mw ibmw; 403 struct c4iw_dev *rhp; 404 struct sk_buff *dereg_skb; 405 u64 kva; 406 struct tpt_attributes attr; 407 }; 408 409 static inline struct c4iw_mw *to_c4iw_mw(struct ib_mw *ibmw) 410 { 411 return container_of(ibmw, struct c4iw_mw, ibmw); 412 } 413 414 struct c4iw_cq { 415 struct ib_cq ibcq; 416 struct c4iw_dev *rhp; 417 struct sk_buff *destroy_skb; 418 struct t4_cq cq; 419 spinlock_t lock; 420 spinlock_t comp_handler_lock; 421 atomic_t refcnt; 422 wait_queue_head_t wait; 423 }; 424 425 static inline struct c4iw_cq *to_c4iw_cq(struct ib_cq *ibcq) 426 { 427 return container_of(ibcq, struct c4iw_cq, ibcq); 428 } 429 430 struct c4iw_mpa_attributes { 431 u8 initiator; 432 u8 recv_marker_enabled; 433 u8 xmit_marker_enabled; 434 u8 crc_enabled; 435 u8 enhanced_rdma_conn; 436 u8 version; 437 u8 p2p_type; 438 }; 439 440 struct c4iw_qp_attributes { 441 u32 scq; 442 u32 rcq; 443 u32 sq_num_entries; 444 u32 rq_num_entries; 445 u32 sq_max_sges; 446 u32 sq_max_sges_rdma_write; 447 u32 rq_max_sges; 448 u32 state; 449 u8 enable_rdma_read; 450 u8 enable_rdma_write; 451 u8 enable_bind; 452 u8 enable_mmid0_fastreg; 453 u32 max_ord; 454 u32 max_ird; 455 u32 pd; 456 u32 next_state; 457 char terminate_buffer[52]; 458 u32 terminate_msg_len; 459 u8 is_terminate_local; 460 struct c4iw_mpa_attributes mpa_attr; 461 struct c4iw_ep *llp_stream_handle; 462 u8 layer_etype; 463 u8 ecode; 464 u16 sq_db_inc; 465 u16 rq_db_inc; 466 u8 send_term; 467 }; 468 469 struct c4iw_qp { 470 struct ib_qp ibqp; 471 struct list_head db_fc_entry; 472 struct c4iw_dev *rhp; 473 struct c4iw_ep *ep; 474 struct c4iw_qp_attributes attr; 475 struct t4_wq wq; 476 spinlock_t lock; 477 struct mutex mutex; 478 struct kref kref; 479 wait_queue_head_t wait; 480 struct timer_list timer; 481 int sq_sig_all; 482 struct completion rq_drained; 483 struct completion sq_drained; 484 }; 485 486 static inline struct c4iw_qp *to_c4iw_qp(struct ib_qp *ibqp) 487 { 488 return container_of(ibqp, struct c4iw_qp, ibqp); 489 } 490 491 struct c4iw_ucontext { 492 struct ib_ucontext ibucontext; 493 struct c4iw_dev_ucontext uctx; 494 u32 key; 495 spinlock_t mmap_lock; 496 struct list_head mmaps; 497 }; 498 499 static inline struct c4iw_ucontext *to_c4iw_ucontext(struct ib_ucontext *c) 500 { 501 return container_of(c, struct c4iw_ucontext, ibucontext); 502 } 503 504 struct c4iw_mm_entry { 505 struct list_head entry; 506 u64 addr; 507 u32 key; 508 unsigned len; 509 }; 510 511 static inline struct c4iw_mm_entry *remove_mmap(struct c4iw_ucontext *ucontext, 512 u32 key, unsigned len) 513 { 514 struct list_head *pos, *nxt; 515 struct c4iw_mm_entry *mm; 516 517 spin_lock(&ucontext->mmap_lock); 518 list_for_each_safe(pos, nxt, &ucontext->mmaps) { 519 520 mm = list_entry(pos, struct c4iw_mm_entry, entry); 521 if (mm->key == key && mm->len == len) { 522 list_del_init(&mm->entry); 523 spin_unlock(&ucontext->mmap_lock); 524 PDBG("%s key 0x%x addr 0x%llx len %d\n", __func__, 525 key, (unsigned long long) mm->addr, mm->len); 526 return mm; 527 } 528 } 529 spin_unlock(&ucontext->mmap_lock); 530 return NULL; 531 } 532 533 static inline void insert_mmap(struct c4iw_ucontext *ucontext, 534 struct c4iw_mm_entry *mm) 535 { 536 spin_lock(&ucontext->mmap_lock); 537 PDBG("%s key 0x%x addr 0x%llx len %d\n", __func__, 538 mm->key, (unsigned long long) mm->addr, mm->len); 539 list_add_tail(&mm->entry, &ucontext->mmaps); 540 spin_unlock(&ucontext->mmap_lock); 541 } 542 543 enum c4iw_qp_attr_mask { 544 C4IW_QP_ATTR_NEXT_STATE = 1 << 0, 545 C4IW_QP_ATTR_SQ_DB = 1<<1, 546 C4IW_QP_ATTR_RQ_DB = 1<<2, 547 C4IW_QP_ATTR_ENABLE_RDMA_READ = 1 << 7, 548 C4IW_QP_ATTR_ENABLE_RDMA_WRITE = 1 << 8, 549 C4IW_QP_ATTR_ENABLE_RDMA_BIND = 1 << 9, 550 C4IW_QP_ATTR_MAX_ORD = 1 << 11, 551 C4IW_QP_ATTR_MAX_IRD = 1 << 12, 552 C4IW_QP_ATTR_LLP_STREAM_HANDLE = 1 << 22, 553 C4IW_QP_ATTR_STREAM_MSG_BUFFER = 1 << 23, 554 C4IW_QP_ATTR_MPA_ATTR = 1 << 24, 555 C4IW_QP_ATTR_QP_CONTEXT_ACTIVATE = 1 << 25, 556 C4IW_QP_ATTR_VALID_MODIFY = (C4IW_QP_ATTR_ENABLE_RDMA_READ | 557 C4IW_QP_ATTR_ENABLE_RDMA_WRITE | 558 C4IW_QP_ATTR_MAX_ORD | 559 C4IW_QP_ATTR_MAX_IRD | 560 C4IW_QP_ATTR_LLP_STREAM_HANDLE | 561 C4IW_QP_ATTR_STREAM_MSG_BUFFER | 562 C4IW_QP_ATTR_MPA_ATTR | 563 C4IW_QP_ATTR_QP_CONTEXT_ACTIVATE) 564 }; 565 566 int c4iw_modify_qp(struct c4iw_dev *rhp, 567 struct c4iw_qp *qhp, 568 enum c4iw_qp_attr_mask mask, 569 struct c4iw_qp_attributes *attrs, 570 int internal); 571 572 enum c4iw_qp_state { 573 C4IW_QP_STATE_IDLE, 574 C4IW_QP_STATE_RTS, 575 C4IW_QP_STATE_ERROR, 576 C4IW_QP_STATE_TERMINATE, 577 C4IW_QP_STATE_CLOSING, 578 C4IW_QP_STATE_TOT 579 }; 580 581 static inline int c4iw_convert_state(enum ib_qp_state ib_state) 582 { 583 switch (ib_state) { 584 case IB_QPS_RESET: 585 case IB_QPS_INIT: 586 return C4IW_QP_STATE_IDLE; 587 case IB_QPS_RTS: 588 return C4IW_QP_STATE_RTS; 589 case IB_QPS_SQD: 590 return C4IW_QP_STATE_CLOSING; 591 case IB_QPS_SQE: 592 return C4IW_QP_STATE_TERMINATE; 593 case IB_QPS_ERR: 594 return C4IW_QP_STATE_ERROR; 595 default: 596 return -1; 597 } 598 } 599 600 static inline int to_ib_qp_state(int c4iw_qp_state) 601 { 602 switch (c4iw_qp_state) { 603 case C4IW_QP_STATE_IDLE: 604 return IB_QPS_INIT; 605 case C4IW_QP_STATE_RTS: 606 return IB_QPS_RTS; 607 case C4IW_QP_STATE_CLOSING: 608 return IB_QPS_SQD; 609 case C4IW_QP_STATE_TERMINATE: 610 return IB_QPS_SQE; 611 case C4IW_QP_STATE_ERROR: 612 return IB_QPS_ERR; 613 } 614 return IB_QPS_ERR; 615 } 616 617 static inline u32 c4iw_ib_to_tpt_access(int a) 618 { 619 return (a & IB_ACCESS_REMOTE_WRITE ? FW_RI_MEM_ACCESS_REM_WRITE : 0) | 620 (a & IB_ACCESS_REMOTE_READ ? FW_RI_MEM_ACCESS_REM_READ : 0) | 621 (a & IB_ACCESS_LOCAL_WRITE ? FW_RI_MEM_ACCESS_LOCAL_WRITE : 0) | 622 FW_RI_MEM_ACCESS_LOCAL_READ; 623 } 624 625 static inline u32 c4iw_ib_to_tpt_bind_access(int acc) 626 { 627 return (acc & IB_ACCESS_REMOTE_WRITE ? FW_RI_MEM_ACCESS_REM_WRITE : 0) | 628 (acc & IB_ACCESS_REMOTE_READ ? FW_RI_MEM_ACCESS_REM_READ : 0); 629 } 630 631 enum c4iw_mmid_state { 632 C4IW_STAG_STATE_VALID, 633 C4IW_STAG_STATE_INVALID 634 }; 635 636 #define C4IW_NODE_DESC "cxgb4 Chelsio Communications" 637 638 #define MPA_KEY_REQ "MPA ID Req Frame" 639 #define MPA_KEY_REP "MPA ID Rep Frame" 640 641 #define MPA_MAX_PRIVATE_DATA 256 642 #define MPA_ENHANCED_RDMA_CONN 0x10 643 #define MPA_REJECT 0x20 644 #define MPA_CRC 0x40 645 #define MPA_MARKERS 0x80 646 #define MPA_FLAGS_MASK 0xE0 647 648 #define MPA_V2_PEER2PEER_MODEL 0x8000 649 #define MPA_V2_ZERO_LEN_FPDU_RTR 0x4000 650 #define MPA_V2_RDMA_WRITE_RTR 0x8000 651 #define MPA_V2_RDMA_READ_RTR 0x4000 652 #define MPA_V2_IRD_ORD_MASK 0x3FFF 653 654 #define c4iw_put_ep(ep) { \ 655 PDBG("put_ep (via %s:%u) ep %p refcnt %d\n", __func__, __LINE__, \ 656 ep, atomic_read(&((ep)->kref.refcount))); \ 657 WARN_ON(atomic_read(&((ep)->kref.refcount)) < 1); \ 658 kref_put(&((ep)->kref), _c4iw_free_ep); \ 659 } 660 661 #define c4iw_get_ep(ep) { \ 662 PDBG("get_ep (via %s:%u) ep %p, refcnt %d\n", __func__, __LINE__, \ 663 ep, atomic_read(&((ep)->kref.refcount))); \ 664 kref_get(&((ep)->kref)); \ 665 } 666 void _c4iw_free_ep(struct kref *kref); 667 668 struct mpa_message { 669 u8 key[16]; 670 u8 flags; 671 u8 revision; 672 __be16 private_data_size; 673 u8 private_data[0]; 674 }; 675 676 struct mpa_v2_conn_params { 677 __be16 ird; 678 __be16 ord; 679 }; 680 681 struct terminate_message { 682 u8 layer_etype; 683 u8 ecode; 684 __be16 hdrct_rsvd; 685 u8 len_hdrs[0]; 686 }; 687 688 #define TERM_MAX_LENGTH (sizeof(struct terminate_message) + 2 + 18 + 28) 689 690 enum c4iw_layers_types { 691 LAYER_RDMAP = 0x00, 692 LAYER_DDP = 0x10, 693 LAYER_MPA = 0x20, 694 RDMAP_LOCAL_CATA = 0x00, 695 RDMAP_REMOTE_PROT = 0x01, 696 RDMAP_REMOTE_OP = 0x02, 697 DDP_LOCAL_CATA = 0x00, 698 DDP_TAGGED_ERR = 0x01, 699 DDP_UNTAGGED_ERR = 0x02, 700 DDP_LLP = 0x03 701 }; 702 703 enum c4iw_rdma_ecodes { 704 RDMAP_INV_STAG = 0x00, 705 RDMAP_BASE_BOUNDS = 0x01, 706 RDMAP_ACC_VIOL = 0x02, 707 RDMAP_STAG_NOT_ASSOC = 0x03, 708 RDMAP_TO_WRAP = 0x04, 709 RDMAP_INV_VERS = 0x05, 710 RDMAP_INV_OPCODE = 0x06, 711 RDMAP_STREAM_CATA = 0x07, 712 RDMAP_GLOBAL_CATA = 0x08, 713 RDMAP_CANT_INV_STAG = 0x09, 714 RDMAP_UNSPECIFIED = 0xff 715 }; 716 717 enum c4iw_ddp_ecodes { 718 DDPT_INV_STAG = 0x00, 719 DDPT_BASE_BOUNDS = 0x01, 720 DDPT_STAG_NOT_ASSOC = 0x02, 721 DDPT_TO_WRAP = 0x03, 722 DDPT_INV_VERS = 0x04, 723 DDPU_INV_QN = 0x01, 724 DDPU_INV_MSN_NOBUF = 0x02, 725 DDPU_INV_MSN_RANGE = 0x03, 726 DDPU_INV_MO = 0x04, 727 DDPU_MSG_TOOBIG = 0x05, 728 DDPU_INV_VERS = 0x06 729 }; 730 731 enum c4iw_mpa_ecodes { 732 MPA_CRC_ERR = 0x02, 733 MPA_MARKER_ERR = 0x03, 734 MPA_LOCAL_CATA = 0x05, 735 MPA_INSUFF_IRD = 0x06, 736 MPA_NOMATCH_RTR = 0x07, 737 }; 738 739 enum c4iw_ep_state { 740 IDLE = 0, 741 LISTEN, 742 CONNECTING, 743 MPA_REQ_WAIT, 744 MPA_REQ_SENT, 745 MPA_REQ_RCVD, 746 MPA_REP_SENT, 747 FPDU_MODE, 748 ABORTING, 749 CLOSING, 750 MORIBUND, 751 DEAD, 752 }; 753 754 enum c4iw_ep_flags { 755 PEER_ABORT_IN_PROGRESS = 0, 756 ABORT_REQ_IN_PROGRESS = 1, 757 RELEASE_RESOURCES = 2, 758 CLOSE_SENT = 3, 759 TIMEOUT = 4, 760 QP_REFERENCED = 5, 761 STOP_MPA_TIMER = 7, 762 }; 763 764 enum c4iw_ep_history { 765 ACT_OPEN_REQ = 0, 766 ACT_OFLD_CONN = 1, 767 ACT_OPEN_RPL = 2, 768 ACT_ESTAB = 3, 769 PASS_ACCEPT_REQ = 4, 770 PASS_ESTAB = 5, 771 ABORT_UPCALL = 6, 772 ESTAB_UPCALL = 7, 773 CLOSE_UPCALL = 8, 774 ULP_ACCEPT = 9, 775 ULP_REJECT = 10, 776 TIMEDOUT = 11, 777 PEER_ABORT = 12, 778 PEER_CLOSE = 13, 779 CONNREQ_UPCALL = 14, 780 ABORT_CONN = 15, 781 DISCONN_UPCALL = 16, 782 EP_DISC_CLOSE = 17, 783 EP_DISC_ABORT = 18, 784 CONN_RPL_UPCALL = 19, 785 ACT_RETRY_NOMEM = 20, 786 ACT_RETRY_INUSE = 21, 787 CLOSE_CON_RPL = 22, 788 EP_DISC_FAIL = 24, 789 QP_REFED = 25, 790 QP_DEREFED = 26, 791 CM_ID_REFED = 27, 792 CM_ID_DEREFED = 28, 793 }; 794 795 enum conn_pre_alloc_buffers { 796 CN_ABORT_REQ_BUF, 797 CN_ABORT_RPL_BUF, 798 CN_CLOSE_CON_REQ_BUF, 799 CN_DESTROY_BUF, 800 CN_FLOWC_BUF, 801 CN_MAX_CON_BUF 802 }; 803 804 #define FLOWC_LEN 80 805 union cpl_wr_size { 806 struct cpl_abort_req abrt_req; 807 struct cpl_abort_rpl abrt_rpl; 808 struct fw_ri_wr ri_req; 809 struct cpl_close_con_req close_req; 810 char flowc_buf[FLOWC_LEN]; 811 }; 812 813 struct c4iw_ep_common { 814 struct iw_cm_id *cm_id; 815 struct c4iw_qp *qp; 816 struct c4iw_dev *dev; 817 struct sk_buff_head ep_skb_list; 818 enum c4iw_ep_state state; 819 struct kref kref; 820 struct mutex mutex; 821 struct sockaddr_storage local_addr; 822 struct sockaddr_storage remote_addr; 823 struct c4iw_wr_wait wr_wait; 824 unsigned long flags; 825 unsigned long history; 826 }; 827 828 struct c4iw_listen_ep { 829 struct c4iw_ep_common com; 830 unsigned int stid; 831 int backlog; 832 }; 833 834 struct c4iw_ep_stats { 835 unsigned connect_neg_adv; 836 unsigned abort_neg_adv; 837 }; 838 839 struct c4iw_ep { 840 struct c4iw_ep_common com; 841 struct c4iw_ep *parent_ep; 842 struct timer_list timer; 843 struct list_head entry; 844 unsigned int atid; 845 u32 hwtid; 846 u32 snd_seq; 847 u32 rcv_seq; 848 struct l2t_entry *l2t; 849 struct dst_entry *dst; 850 struct sk_buff *mpa_skb; 851 struct c4iw_mpa_attributes mpa_attr; 852 u8 mpa_pkt[sizeof(struct mpa_message) + MPA_MAX_PRIVATE_DATA]; 853 unsigned int mpa_pkt_len; 854 u32 ird; 855 u32 ord; 856 u32 smac_idx; 857 u32 tx_chan; 858 u32 mtu; 859 u16 mss; 860 u16 emss; 861 u16 plen; 862 u16 rss_qid; 863 u16 txq_idx; 864 u16 ctrlq_idx; 865 u8 tos; 866 u8 retry_with_mpa_v1; 867 u8 tried_with_mpa_v1; 868 unsigned int retry_count; 869 int snd_win; 870 int rcv_win; 871 struct c4iw_ep_stats stats; 872 }; 873 874 static inline struct c4iw_ep *to_ep(struct iw_cm_id *cm_id) 875 { 876 return cm_id->provider_data; 877 } 878 879 static inline struct c4iw_listen_ep *to_listen_ep(struct iw_cm_id *cm_id) 880 { 881 return cm_id->provider_data; 882 } 883 884 static inline int compute_wscale(int win) 885 { 886 int wscale = 0; 887 888 while (wscale < 14 && (65535<<wscale) < win) 889 wscale++; 890 return wscale; 891 } 892 893 static inline int ocqp_supported(const struct cxgb4_lld_info *infop) 894 { 895 #if defined(__i386__) || defined(__x86_64__) || defined(CONFIG_PPC64) 896 return infop->vr->ocq.size > 0; 897 #else 898 return 0; 899 #endif 900 } 901 902 u32 c4iw_id_alloc(struct c4iw_id_table *alloc); 903 void c4iw_id_free(struct c4iw_id_table *alloc, u32 obj); 904 int c4iw_id_table_alloc(struct c4iw_id_table *alloc, u32 start, u32 num, 905 u32 reserved, u32 flags); 906 void c4iw_id_table_free(struct c4iw_id_table *alloc); 907 908 typedef int (*c4iw_handler_func)(struct c4iw_dev *dev, struct sk_buff *skb); 909 910 int c4iw_ep_redirect(void *ctx, struct dst_entry *old, struct dst_entry *new, 911 struct l2t_entry *l2t); 912 void c4iw_put_qpid(struct c4iw_rdev *rdev, u32 qpid, 913 struct c4iw_dev_ucontext *uctx); 914 u32 c4iw_get_resource(struct c4iw_id_table *id_table); 915 void c4iw_put_resource(struct c4iw_id_table *id_table, u32 entry); 916 int c4iw_init_resource(struct c4iw_rdev *rdev, u32 nr_tpt, u32 nr_pdid); 917 int c4iw_init_ctrl_qp(struct c4iw_rdev *rdev); 918 int c4iw_pblpool_create(struct c4iw_rdev *rdev); 919 int c4iw_rqtpool_create(struct c4iw_rdev *rdev); 920 int c4iw_ocqp_pool_create(struct c4iw_rdev *rdev); 921 void c4iw_pblpool_destroy(struct c4iw_rdev *rdev); 922 void c4iw_rqtpool_destroy(struct c4iw_rdev *rdev); 923 void c4iw_ocqp_pool_destroy(struct c4iw_rdev *rdev); 924 void c4iw_destroy_resource(struct c4iw_resource *rscp); 925 int c4iw_destroy_ctrl_qp(struct c4iw_rdev *rdev); 926 int c4iw_register_device(struct c4iw_dev *dev); 927 void c4iw_unregister_device(struct c4iw_dev *dev); 928 int __init c4iw_cm_init(void); 929 void c4iw_cm_term(void); 930 void c4iw_release_dev_ucontext(struct c4iw_rdev *rdev, 931 struct c4iw_dev_ucontext *uctx); 932 void c4iw_init_dev_ucontext(struct c4iw_rdev *rdev, 933 struct c4iw_dev_ucontext *uctx); 934 int c4iw_poll_cq(struct ib_cq *ibcq, int num_entries, struct ib_wc *wc); 935 int c4iw_post_send(struct ib_qp *ibqp, struct ib_send_wr *wr, 936 struct ib_send_wr **bad_wr); 937 int c4iw_post_receive(struct ib_qp *ibqp, struct ib_recv_wr *wr, 938 struct ib_recv_wr **bad_wr); 939 int c4iw_connect(struct iw_cm_id *cm_id, struct iw_cm_conn_param *conn_param); 940 int c4iw_create_listen(struct iw_cm_id *cm_id, int backlog); 941 int c4iw_destroy_listen(struct iw_cm_id *cm_id); 942 int c4iw_accept_cr(struct iw_cm_id *cm_id, struct iw_cm_conn_param *conn_param); 943 int c4iw_reject_cr(struct iw_cm_id *cm_id, const void *pdata, u8 pdata_len); 944 void c4iw_qp_add_ref(struct ib_qp *qp); 945 void c4iw_qp_rem_ref(struct ib_qp *qp); 946 struct ib_mr *c4iw_alloc_mr(struct ib_pd *pd, 947 enum ib_mr_type mr_type, 948 u32 max_num_sg); 949 int c4iw_map_mr_sg(struct ib_mr *ibmr, struct scatterlist *sg, int sg_nents, 950 unsigned int *sg_offset); 951 int c4iw_dealloc_mw(struct ib_mw *mw); 952 struct ib_mw *c4iw_alloc_mw(struct ib_pd *pd, enum ib_mw_type type, 953 struct ib_udata *udata); 954 struct ib_mr *c4iw_reg_user_mr(struct ib_pd *pd, u64 start, 955 u64 length, u64 virt, int acc, 956 struct ib_udata *udata); 957 struct ib_mr *c4iw_get_dma_mr(struct ib_pd *pd, int acc); 958 int c4iw_dereg_mr(struct ib_mr *ib_mr); 959 int c4iw_destroy_cq(struct ib_cq *ib_cq); 960 struct ib_cq *c4iw_create_cq(struct ib_device *ibdev, 961 const struct ib_cq_init_attr *attr, 962 struct ib_ucontext *ib_context, 963 struct ib_udata *udata); 964 int c4iw_resize_cq(struct ib_cq *cq, int cqe, struct ib_udata *udata); 965 int c4iw_arm_cq(struct ib_cq *ibcq, enum ib_cq_notify_flags flags); 966 int c4iw_destroy_qp(struct ib_qp *ib_qp); 967 struct ib_qp *c4iw_create_qp(struct ib_pd *pd, 968 struct ib_qp_init_attr *attrs, 969 struct ib_udata *udata); 970 int c4iw_ib_modify_qp(struct ib_qp *ibqp, struct ib_qp_attr *attr, 971 int attr_mask, struct ib_udata *udata); 972 int c4iw_ib_query_qp(struct ib_qp *ibqp, struct ib_qp_attr *attr, 973 int attr_mask, struct ib_qp_init_attr *init_attr); 974 struct ib_qp *c4iw_get_qp(struct ib_device *dev, int qpn); 975 u32 c4iw_rqtpool_alloc(struct c4iw_rdev *rdev, int size); 976 void c4iw_rqtpool_free(struct c4iw_rdev *rdev, u32 addr, int size); 977 u32 c4iw_pblpool_alloc(struct c4iw_rdev *rdev, int size); 978 void c4iw_pblpool_free(struct c4iw_rdev *rdev, u32 addr, int size); 979 u32 c4iw_ocqp_pool_alloc(struct c4iw_rdev *rdev, int size); 980 void c4iw_ocqp_pool_free(struct c4iw_rdev *rdev, u32 addr, int size); 981 int c4iw_ofld_send(struct c4iw_rdev *rdev, struct sk_buff *skb); 982 void c4iw_flush_hw_cq(struct c4iw_cq *chp); 983 void c4iw_count_rcqes(struct t4_cq *cq, struct t4_wq *wq, int *count); 984 int c4iw_ep_disconnect(struct c4iw_ep *ep, int abrupt, gfp_t gfp); 985 int c4iw_flush_rq(struct t4_wq *wq, struct t4_cq *cq, int count); 986 int c4iw_flush_sq(struct c4iw_qp *qhp); 987 int c4iw_ev_handler(struct c4iw_dev *rnicp, u32 qid); 988 u16 c4iw_rqes_posted(struct c4iw_qp *qhp); 989 int c4iw_post_terminate(struct c4iw_qp *qhp, struct t4_cqe *err_cqe); 990 u32 c4iw_get_cqid(struct c4iw_rdev *rdev, struct c4iw_dev_ucontext *uctx); 991 void c4iw_put_cqid(struct c4iw_rdev *rdev, u32 qid, 992 struct c4iw_dev_ucontext *uctx); 993 u32 c4iw_get_qpid(struct c4iw_rdev *rdev, struct c4iw_dev_ucontext *uctx); 994 void c4iw_put_qpid(struct c4iw_rdev *rdev, u32 qid, 995 struct c4iw_dev_ucontext *uctx); 996 void c4iw_ev_dispatch(struct c4iw_dev *dev, struct t4_cqe *err_cqe); 997 998 extern struct cxgb4_client t4c_client; 999 extern c4iw_handler_func c4iw_handlers[NUM_CPL_CMDS]; 1000 void __iomem *c4iw_bar2_addrs(struct c4iw_rdev *rdev, unsigned int qid, 1001 enum cxgb4_bar2_qtype qtype, 1002 unsigned int *pbar2_qid, u64 *pbar2_pa); 1003 extern void c4iw_log_wr_stats(struct t4_wq *wq, struct t4_cqe *cqe); 1004 extern int c4iw_wr_log; 1005 extern int db_fc_threshold; 1006 extern int db_coalescing_threshold; 1007 extern int use_dsgl; 1008 void c4iw_drain_rq(struct ib_qp *qp); 1009 void c4iw_drain_sq(struct ib_qp *qp); 1010 1011 1012 #endif 1013