1 /* 2 * Copyright (c) 2009-2010 Chelsio, Inc. All rights reserved. 3 * 4 * This software is available to you under a choice of one of two 5 * licenses. You may choose to be licensed under the terms of the GNU 6 * General Public License (GPL) Version 2, available from the file 7 * COPYING in the main directory of this source tree, or the 8 * OpenIB.org BSD license below: 9 * 10 * Redistribution and use in source and binary forms, with or 11 * without modification, are permitted provided that the following 12 * conditions are met: 13 * 14 * - Redistributions of source code must retain the above 15 * copyright notice, this list of conditions and the following 16 * disclaimer. 17 * 18 * - Redistributions in binary form must reproduce the above 19 * copyright notice, this list of conditions and the following 20 * disclaimer in the documentation and/or other materials 21 * provided with the distribution. 22 * 23 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, 24 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF 25 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND 26 * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS 27 * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN 28 * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN 29 * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE 30 * SOFTWARE. 31 */ 32 #include <linux/module.h> 33 #include <linux/moduleparam.h> 34 #include <linux/debugfs.h> 35 #include <linux/vmalloc.h> 36 #include <linux/math64.h> 37 38 #include <rdma/ib_verbs.h> 39 40 #include "iw_cxgb4.h" 41 42 #define DRV_VERSION "0.1" 43 44 MODULE_AUTHOR("Steve Wise"); 45 MODULE_DESCRIPTION("Chelsio T4/T5 RDMA Driver"); 46 MODULE_LICENSE("Dual BSD/GPL"); 47 48 static int allow_db_fc_on_t5; 49 module_param(allow_db_fc_on_t5, int, 0644); 50 MODULE_PARM_DESC(allow_db_fc_on_t5, 51 "Allow DB Flow Control on T5 (default = 0)"); 52 53 static int allow_db_coalescing_on_t5; 54 module_param(allow_db_coalescing_on_t5, int, 0644); 55 MODULE_PARM_DESC(allow_db_coalescing_on_t5, 56 "Allow DB Coalescing on T5 (default = 0)"); 57 58 int c4iw_wr_log = 0; 59 module_param(c4iw_wr_log, int, 0444); 60 MODULE_PARM_DESC(c4iw_wr_log, "Enables logging of work request timing data."); 61 62 static int c4iw_wr_log_size_order = 12; 63 module_param(c4iw_wr_log_size_order, int, 0444); 64 MODULE_PARM_DESC(c4iw_wr_log_size_order, 65 "Number of entries (log2) in the work request timing log."); 66 67 static LIST_HEAD(uld_ctx_list); 68 static DEFINE_MUTEX(dev_mutex); 69 struct workqueue_struct *reg_workq; 70 71 #define DB_FC_RESUME_SIZE 64 72 #define DB_FC_RESUME_DELAY 1 73 #define DB_FC_DRAIN_THRESH 0 74 75 static struct dentry *c4iw_debugfs_root; 76 77 struct c4iw_debugfs_data { 78 struct c4iw_dev *devp; 79 char *buf; 80 int bufsize; 81 int pos; 82 }; 83 84 static int count_idrs(int id, void *p, void *data) 85 { 86 int *countp = data; 87 88 *countp = *countp + 1; 89 return 0; 90 } 91 92 static ssize_t debugfs_read(struct file *file, char __user *buf, size_t count, 93 loff_t *ppos) 94 { 95 struct c4iw_debugfs_data *d = file->private_data; 96 97 return simple_read_from_buffer(buf, count, ppos, d->buf, d->pos); 98 } 99 100 void c4iw_log_wr_stats(struct t4_wq *wq, struct t4_cqe *cqe) 101 { 102 struct wr_log_entry le; 103 int idx; 104 105 if (!wq->rdev->wr_log) 106 return; 107 108 idx = (atomic_inc_return(&wq->rdev->wr_log_idx) - 1) & 109 (wq->rdev->wr_log_size - 1); 110 le.poll_sge_ts = cxgb4_read_sge_timestamp(wq->rdev->lldi.ports[0]); 111 getnstimeofday(&le.poll_host_ts); 112 le.valid = 1; 113 le.cqe_sge_ts = CQE_TS(cqe); 114 if (SQ_TYPE(cqe)) { 115 le.qid = wq->sq.qid; 116 le.opcode = CQE_OPCODE(cqe); 117 le.post_host_ts = wq->sq.sw_sq[wq->sq.cidx].host_ts; 118 le.post_sge_ts = wq->sq.sw_sq[wq->sq.cidx].sge_ts; 119 le.wr_id = CQE_WRID_SQ_IDX(cqe); 120 } else { 121 le.qid = wq->rq.qid; 122 le.opcode = FW_RI_RECEIVE; 123 le.post_host_ts = wq->rq.sw_rq[wq->rq.cidx].host_ts; 124 le.post_sge_ts = wq->rq.sw_rq[wq->rq.cidx].sge_ts; 125 le.wr_id = CQE_WRID_MSN(cqe); 126 } 127 wq->rdev->wr_log[idx] = le; 128 } 129 130 static int wr_log_show(struct seq_file *seq, void *v) 131 { 132 struct c4iw_dev *dev = seq->private; 133 struct timespec prev_ts = {0, 0}; 134 struct wr_log_entry *lep; 135 int prev_ts_set = 0; 136 int idx, end; 137 138 #define ts2ns(ts) div64_u64((ts) * dev->rdev.lldi.cclk_ps, 1000) 139 140 idx = atomic_read(&dev->rdev.wr_log_idx) & 141 (dev->rdev.wr_log_size - 1); 142 end = idx - 1; 143 if (end < 0) 144 end = dev->rdev.wr_log_size - 1; 145 lep = &dev->rdev.wr_log[idx]; 146 while (idx != end) { 147 if (lep->valid) { 148 if (!prev_ts_set) { 149 prev_ts_set = 1; 150 prev_ts = lep->poll_host_ts; 151 } 152 seq_printf(seq, "%04u: sec %lu nsec %lu qid %u opcode " 153 "%u %s 0x%x host_wr_delta sec %lu nsec %lu " 154 "post_sge_ts 0x%llx cqe_sge_ts 0x%llx " 155 "poll_sge_ts 0x%llx post_poll_delta_ns %llu " 156 "cqe_poll_delta_ns %llu\n", 157 idx, 158 timespec_sub(lep->poll_host_ts, 159 prev_ts).tv_sec, 160 timespec_sub(lep->poll_host_ts, 161 prev_ts).tv_nsec, 162 lep->qid, lep->opcode, 163 lep->opcode == FW_RI_RECEIVE ? 164 "msn" : "wrid", 165 lep->wr_id, 166 timespec_sub(lep->poll_host_ts, 167 lep->post_host_ts).tv_sec, 168 timespec_sub(lep->poll_host_ts, 169 lep->post_host_ts).tv_nsec, 170 lep->post_sge_ts, lep->cqe_sge_ts, 171 lep->poll_sge_ts, 172 ts2ns(lep->poll_sge_ts - lep->post_sge_ts), 173 ts2ns(lep->poll_sge_ts - lep->cqe_sge_ts)); 174 prev_ts = lep->poll_host_ts; 175 } 176 idx++; 177 if (idx > (dev->rdev.wr_log_size - 1)) 178 idx = 0; 179 lep = &dev->rdev.wr_log[idx]; 180 } 181 #undef ts2ns 182 return 0; 183 } 184 185 static int wr_log_open(struct inode *inode, struct file *file) 186 { 187 return single_open(file, wr_log_show, inode->i_private); 188 } 189 190 static ssize_t wr_log_clear(struct file *file, const char __user *buf, 191 size_t count, loff_t *pos) 192 { 193 struct c4iw_dev *dev = ((struct seq_file *)file->private_data)->private; 194 int i; 195 196 if (dev->rdev.wr_log) 197 for (i = 0; i < dev->rdev.wr_log_size; i++) 198 dev->rdev.wr_log[i].valid = 0; 199 return count; 200 } 201 202 static const struct file_operations wr_log_debugfs_fops = { 203 .owner = THIS_MODULE, 204 .open = wr_log_open, 205 .release = single_release, 206 .read = seq_read, 207 .llseek = seq_lseek, 208 .write = wr_log_clear, 209 }; 210 211 static struct sockaddr_in zero_sin = { 212 .sin_family = AF_INET, 213 }; 214 215 static struct sockaddr_in6 zero_sin6 = { 216 .sin6_family = AF_INET6, 217 }; 218 219 static void set_ep_sin_addrs(struct c4iw_ep *ep, 220 struct sockaddr_in **lsin, 221 struct sockaddr_in **rsin, 222 struct sockaddr_in **m_lsin, 223 struct sockaddr_in **m_rsin) 224 { 225 struct iw_cm_id *id = ep->com.cm_id; 226 227 *lsin = (struct sockaddr_in *)&ep->com.local_addr; 228 *rsin = (struct sockaddr_in *)&ep->com.remote_addr; 229 if (id) { 230 *m_lsin = (struct sockaddr_in *)&id->m_local_addr; 231 *m_rsin = (struct sockaddr_in *)&id->m_remote_addr; 232 } else { 233 *m_lsin = &zero_sin; 234 *m_rsin = &zero_sin; 235 } 236 } 237 238 static void set_ep_sin6_addrs(struct c4iw_ep *ep, 239 struct sockaddr_in6 **lsin6, 240 struct sockaddr_in6 **rsin6, 241 struct sockaddr_in6 **m_lsin6, 242 struct sockaddr_in6 **m_rsin6) 243 { 244 struct iw_cm_id *id = ep->com.cm_id; 245 246 *lsin6 = (struct sockaddr_in6 *)&ep->com.local_addr; 247 *rsin6 = (struct sockaddr_in6 *)&ep->com.remote_addr; 248 if (id) { 249 *m_lsin6 = (struct sockaddr_in6 *)&id->m_local_addr; 250 *m_rsin6 = (struct sockaddr_in6 *)&id->m_remote_addr; 251 } else { 252 *m_lsin6 = &zero_sin6; 253 *m_rsin6 = &zero_sin6; 254 } 255 } 256 257 static int dump_qp(int id, void *p, void *data) 258 { 259 struct c4iw_qp *qp = p; 260 struct c4iw_debugfs_data *qpd = data; 261 int space; 262 int cc; 263 264 if (id != qp->wq.sq.qid) 265 return 0; 266 267 space = qpd->bufsize - qpd->pos - 1; 268 if (space == 0) 269 return 1; 270 271 if (qp->ep) { 272 struct c4iw_ep *ep = qp->ep; 273 274 if (ep->com.local_addr.ss_family == AF_INET) { 275 struct sockaddr_in *lsin; 276 struct sockaddr_in *rsin; 277 struct sockaddr_in *m_lsin; 278 struct sockaddr_in *m_rsin; 279 280 set_ep_sin_addrs(ep, &lsin, &rsin, &m_lsin, &m_rsin); 281 cc = snprintf(qpd->buf + qpd->pos, space, 282 "rc qp sq id %u rq id %u state %u " 283 "onchip %u ep tid %u state %u " 284 "%pI4:%u/%u->%pI4:%u/%u\n", 285 qp->wq.sq.qid, qp->wq.rq.qid, 286 (int)qp->attr.state, 287 qp->wq.sq.flags & T4_SQ_ONCHIP, 288 ep->hwtid, (int)ep->com.state, 289 &lsin->sin_addr, ntohs(lsin->sin_port), 290 ntohs(m_lsin->sin_port), 291 &rsin->sin_addr, ntohs(rsin->sin_port), 292 ntohs(m_rsin->sin_port)); 293 } else { 294 struct sockaddr_in6 *lsin6; 295 struct sockaddr_in6 *rsin6; 296 struct sockaddr_in6 *m_lsin6; 297 struct sockaddr_in6 *m_rsin6; 298 299 set_ep_sin6_addrs(ep, &lsin6, &rsin6, &m_lsin6, 300 &m_rsin6); 301 cc = snprintf(qpd->buf + qpd->pos, space, 302 "rc qp sq id %u rq id %u state %u " 303 "onchip %u ep tid %u state %u " 304 "%pI6:%u/%u->%pI6:%u/%u\n", 305 qp->wq.sq.qid, qp->wq.rq.qid, 306 (int)qp->attr.state, 307 qp->wq.sq.flags & T4_SQ_ONCHIP, 308 ep->hwtid, (int)ep->com.state, 309 &lsin6->sin6_addr, 310 ntohs(lsin6->sin6_port), 311 ntohs(m_lsin6->sin6_port), 312 &rsin6->sin6_addr, 313 ntohs(rsin6->sin6_port), 314 ntohs(m_rsin6->sin6_port)); 315 } 316 } else 317 cc = snprintf(qpd->buf + qpd->pos, space, 318 "qp sq id %u rq id %u state %u onchip %u\n", 319 qp->wq.sq.qid, qp->wq.rq.qid, 320 (int)qp->attr.state, 321 qp->wq.sq.flags & T4_SQ_ONCHIP); 322 if (cc < space) 323 qpd->pos += cc; 324 return 0; 325 } 326 327 static int qp_release(struct inode *inode, struct file *file) 328 { 329 struct c4iw_debugfs_data *qpd = file->private_data; 330 if (!qpd) { 331 pr_info("%s null qpd?\n", __func__); 332 return 0; 333 } 334 vfree(qpd->buf); 335 kfree(qpd); 336 return 0; 337 } 338 339 static int qp_open(struct inode *inode, struct file *file) 340 { 341 struct c4iw_debugfs_data *qpd; 342 int count = 1; 343 344 qpd = kmalloc(sizeof *qpd, GFP_KERNEL); 345 if (!qpd) 346 return -ENOMEM; 347 348 qpd->devp = inode->i_private; 349 qpd->pos = 0; 350 351 spin_lock_irq(&qpd->devp->lock); 352 idr_for_each(&qpd->devp->qpidr, count_idrs, &count); 353 spin_unlock_irq(&qpd->devp->lock); 354 355 qpd->bufsize = count * 180; 356 qpd->buf = vmalloc(qpd->bufsize); 357 if (!qpd->buf) { 358 kfree(qpd); 359 return -ENOMEM; 360 } 361 362 spin_lock_irq(&qpd->devp->lock); 363 idr_for_each(&qpd->devp->qpidr, dump_qp, qpd); 364 spin_unlock_irq(&qpd->devp->lock); 365 366 qpd->buf[qpd->pos++] = 0; 367 file->private_data = qpd; 368 return 0; 369 } 370 371 static const struct file_operations qp_debugfs_fops = { 372 .owner = THIS_MODULE, 373 .open = qp_open, 374 .release = qp_release, 375 .read = debugfs_read, 376 .llseek = default_llseek, 377 }; 378 379 static int dump_stag(int id, void *p, void *data) 380 { 381 struct c4iw_debugfs_data *stagd = data; 382 int space; 383 int cc; 384 struct fw_ri_tpte tpte; 385 int ret; 386 387 space = stagd->bufsize - stagd->pos - 1; 388 if (space == 0) 389 return 1; 390 391 ret = cxgb4_read_tpte(stagd->devp->rdev.lldi.ports[0], (u32)id<<8, 392 (__be32 *)&tpte); 393 if (ret) { 394 dev_err(&stagd->devp->rdev.lldi.pdev->dev, 395 "%s cxgb4_read_tpte err %d\n", __func__, ret); 396 return ret; 397 } 398 cc = snprintf(stagd->buf + stagd->pos, space, 399 "stag: idx 0x%x valid %d key 0x%x state %d pdid %d " 400 "perm 0x%x ps %d len 0x%llx va 0x%llx\n", 401 (u32)id<<8, 402 FW_RI_TPTE_VALID_G(ntohl(tpte.valid_to_pdid)), 403 FW_RI_TPTE_STAGKEY_G(ntohl(tpte.valid_to_pdid)), 404 FW_RI_TPTE_STAGSTATE_G(ntohl(tpte.valid_to_pdid)), 405 FW_RI_TPTE_PDID_G(ntohl(tpte.valid_to_pdid)), 406 FW_RI_TPTE_PERM_G(ntohl(tpte.locread_to_qpid)), 407 FW_RI_TPTE_PS_G(ntohl(tpte.locread_to_qpid)), 408 ((u64)ntohl(tpte.len_hi) << 32) | ntohl(tpte.len_lo), 409 ((u64)ntohl(tpte.va_hi) << 32) | ntohl(tpte.va_lo_fbo)); 410 if (cc < space) 411 stagd->pos += cc; 412 return 0; 413 } 414 415 static int stag_release(struct inode *inode, struct file *file) 416 { 417 struct c4iw_debugfs_data *stagd = file->private_data; 418 if (!stagd) { 419 pr_info("%s null stagd?\n", __func__); 420 return 0; 421 } 422 vfree(stagd->buf); 423 kfree(stagd); 424 return 0; 425 } 426 427 static int stag_open(struct inode *inode, struct file *file) 428 { 429 struct c4iw_debugfs_data *stagd; 430 int ret = 0; 431 int count = 1; 432 433 stagd = kmalloc(sizeof *stagd, GFP_KERNEL); 434 if (!stagd) { 435 ret = -ENOMEM; 436 goto out; 437 } 438 stagd->devp = inode->i_private; 439 stagd->pos = 0; 440 441 spin_lock_irq(&stagd->devp->lock); 442 idr_for_each(&stagd->devp->mmidr, count_idrs, &count); 443 spin_unlock_irq(&stagd->devp->lock); 444 445 stagd->bufsize = count * 256; 446 stagd->buf = vmalloc(stagd->bufsize); 447 if (!stagd->buf) { 448 ret = -ENOMEM; 449 goto err1; 450 } 451 452 spin_lock_irq(&stagd->devp->lock); 453 idr_for_each(&stagd->devp->mmidr, dump_stag, stagd); 454 spin_unlock_irq(&stagd->devp->lock); 455 456 stagd->buf[stagd->pos++] = 0; 457 file->private_data = stagd; 458 goto out; 459 err1: 460 kfree(stagd); 461 out: 462 return ret; 463 } 464 465 static const struct file_operations stag_debugfs_fops = { 466 .owner = THIS_MODULE, 467 .open = stag_open, 468 .release = stag_release, 469 .read = debugfs_read, 470 .llseek = default_llseek, 471 }; 472 473 static char *db_state_str[] = {"NORMAL", "FLOW_CONTROL", "RECOVERY", "STOPPED"}; 474 475 static int stats_show(struct seq_file *seq, void *v) 476 { 477 struct c4iw_dev *dev = seq->private; 478 479 seq_printf(seq, " Object: %10s %10s %10s %10s\n", "Total", "Current", 480 "Max", "Fail"); 481 seq_printf(seq, " PDID: %10llu %10llu %10llu %10llu\n", 482 dev->rdev.stats.pd.total, dev->rdev.stats.pd.cur, 483 dev->rdev.stats.pd.max, dev->rdev.stats.pd.fail); 484 seq_printf(seq, " QID: %10llu %10llu %10llu %10llu\n", 485 dev->rdev.stats.qid.total, dev->rdev.stats.qid.cur, 486 dev->rdev.stats.qid.max, dev->rdev.stats.qid.fail); 487 seq_printf(seq, " TPTMEM: %10llu %10llu %10llu %10llu\n", 488 dev->rdev.stats.stag.total, dev->rdev.stats.stag.cur, 489 dev->rdev.stats.stag.max, dev->rdev.stats.stag.fail); 490 seq_printf(seq, " PBLMEM: %10llu %10llu %10llu %10llu\n", 491 dev->rdev.stats.pbl.total, dev->rdev.stats.pbl.cur, 492 dev->rdev.stats.pbl.max, dev->rdev.stats.pbl.fail); 493 seq_printf(seq, " RQTMEM: %10llu %10llu %10llu %10llu\n", 494 dev->rdev.stats.rqt.total, dev->rdev.stats.rqt.cur, 495 dev->rdev.stats.rqt.max, dev->rdev.stats.rqt.fail); 496 seq_printf(seq, " OCQPMEM: %10llu %10llu %10llu %10llu\n", 497 dev->rdev.stats.ocqp.total, dev->rdev.stats.ocqp.cur, 498 dev->rdev.stats.ocqp.max, dev->rdev.stats.ocqp.fail); 499 seq_printf(seq, " DB FULL: %10llu\n", dev->rdev.stats.db_full); 500 seq_printf(seq, " DB EMPTY: %10llu\n", dev->rdev.stats.db_empty); 501 seq_printf(seq, " DB DROP: %10llu\n", dev->rdev.stats.db_drop); 502 seq_printf(seq, " DB State: %s Transitions %llu FC Interruptions %llu\n", 503 db_state_str[dev->db_state], 504 dev->rdev.stats.db_state_transitions, 505 dev->rdev.stats.db_fc_interruptions); 506 seq_printf(seq, "TCAM_FULL: %10llu\n", dev->rdev.stats.tcam_full); 507 seq_printf(seq, "ACT_OFLD_CONN_FAILS: %10llu\n", 508 dev->rdev.stats.act_ofld_conn_fails); 509 seq_printf(seq, "PAS_OFLD_CONN_FAILS: %10llu\n", 510 dev->rdev.stats.pas_ofld_conn_fails); 511 seq_printf(seq, "NEG_ADV_RCVD: %10llu\n", dev->rdev.stats.neg_adv); 512 seq_printf(seq, "AVAILABLE IRD: %10u\n", dev->avail_ird); 513 return 0; 514 } 515 516 static int stats_open(struct inode *inode, struct file *file) 517 { 518 return single_open(file, stats_show, inode->i_private); 519 } 520 521 static ssize_t stats_clear(struct file *file, const char __user *buf, 522 size_t count, loff_t *pos) 523 { 524 struct c4iw_dev *dev = ((struct seq_file *)file->private_data)->private; 525 526 mutex_lock(&dev->rdev.stats.lock); 527 dev->rdev.stats.pd.max = 0; 528 dev->rdev.stats.pd.fail = 0; 529 dev->rdev.stats.qid.max = 0; 530 dev->rdev.stats.qid.fail = 0; 531 dev->rdev.stats.stag.max = 0; 532 dev->rdev.stats.stag.fail = 0; 533 dev->rdev.stats.pbl.max = 0; 534 dev->rdev.stats.pbl.fail = 0; 535 dev->rdev.stats.rqt.max = 0; 536 dev->rdev.stats.rqt.fail = 0; 537 dev->rdev.stats.ocqp.max = 0; 538 dev->rdev.stats.ocqp.fail = 0; 539 dev->rdev.stats.db_full = 0; 540 dev->rdev.stats.db_empty = 0; 541 dev->rdev.stats.db_drop = 0; 542 dev->rdev.stats.db_state_transitions = 0; 543 dev->rdev.stats.tcam_full = 0; 544 dev->rdev.stats.act_ofld_conn_fails = 0; 545 dev->rdev.stats.pas_ofld_conn_fails = 0; 546 mutex_unlock(&dev->rdev.stats.lock); 547 return count; 548 } 549 550 static const struct file_operations stats_debugfs_fops = { 551 .owner = THIS_MODULE, 552 .open = stats_open, 553 .release = single_release, 554 .read = seq_read, 555 .llseek = seq_lseek, 556 .write = stats_clear, 557 }; 558 559 static int dump_ep(int id, void *p, void *data) 560 { 561 struct c4iw_ep *ep = p; 562 struct c4iw_debugfs_data *epd = data; 563 int space; 564 int cc; 565 566 space = epd->bufsize - epd->pos - 1; 567 if (space == 0) 568 return 1; 569 570 if (ep->com.local_addr.ss_family == AF_INET) { 571 struct sockaddr_in *lsin; 572 struct sockaddr_in *rsin; 573 struct sockaddr_in *m_lsin; 574 struct sockaddr_in *m_rsin; 575 576 set_ep_sin_addrs(ep, &lsin, &rsin, &m_lsin, &m_rsin); 577 cc = snprintf(epd->buf + epd->pos, space, 578 "ep %p cm_id %p qp %p state %d flags 0x%lx " 579 "history 0x%lx hwtid %d atid %d " 580 "conn_na %u abort_na %u " 581 "%pI4:%d/%d <-> %pI4:%d/%d\n", 582 ep, ep->com.cm_id, ep->com.qp, 583 (int)ep->com.state, ep->com.flags, 584 ep->com.history, ep->hwtid, ep->atid, 585 ep->stats.connect_neg_adv, 586 ep->stats.abort_neg_adv, 587 &lsin->sin_addr, ntohs(lsin->sin_port), 588 ntohs(m_lsin->sin_port), 589 &rsin->sin_addr, ntohs(rsin->sin_port), 590 ntohs(m_rsin->sin_port)); 591 } else { 592 struct sockaddr_in6 *lsin6; 593 struct sockaddr_in6 *rsin6; 594 struct sockaddr_in6 *m_lsin6; 595 struct sockaddr_in6 *m_rsin6; 596 597 set_ep_sin6_addrs(ep, &lsin6, &rsin6, &m_lsin6, &m_rsin6); 598 cc = snprintf(epd->buf + epd->pos, space, 599 "ep %p cm_id %p qp %p state %d flags 0x%lx " 600 "history 0x%lx hwtid %d atid %d " 601 "conn_na %u abort_na %u " 602 "%pI6:%d/%d <-> %pI6:%d/%d\n", 603 ep, ep->com.cm_id, ep->com.qp, 604 (int)ep->com.state, ep->com.flags, 605 ep->com.history, ep->hwtid, ep->atid, 606 ep->stats.connect_neg_adv, 607 ep->stats.abort_neg_adv, 608 &lsin6->sin6_addr, ntohs(lsin6->sin6_port), 609 ntohs(m_lsin6->sin6_port), 610 &rsin6->sin6_addr, ntohs(rsin6->sin6_port), 611 ntohs(m_rsin6->sin6_port)); 612 } 613 if (cc < space) 614 epd->pos += cc; 615 return 0; 616 } 617 618 static int dump_listen_ep(int id, void *p, void *data) 619 { 620 struct c4iw_listen_ep *ep = p; 621 struct c4iw_debugfs_data *epd = data; 622 int space; 623 int cc; 624 625 space = epd->bufsize - epd->pos - 1; 626 if (space == 0) 627 return 1; 628 629 if (ep->com.local_addr.ss_family == AF_INET) { 630 struct sockaddr_in *lsin = (struct sockaddr_in *) 631 &ep->com.cm_id->local_addr; 632 struct sockaddr_in *m_lsin = (struct sockaddr_in *) 633 &ep->com.cm_id->m_local_addr; 634 635 cc = snprintf(epd->buf + epd->pos, space, 636 "ep %p cm_id %p state %d flags 0x%lx stid %d " 637 "backlog %d %pI4:%d/%d\n", 638 ep, ep->com.cm_id, (int)ep->com.state, 639 ep->com.flags, ep->stid, ep->backlog, 640 &lsin->sin_addr, ntohs(lsin->sin_port), 641 ntohs(m_lsin->sin_port)); 642 } else { 643 struct sockaddr_in6 *lsin6 = (struct sockaddr_in6 *) 644 &ep->com.cm_id->local_addr; 645 struct sockaddr_in6 *m_lsin6 = (struct sockaddr_in6 *) 646 &ep->com.cm_id->m_local_addr; 647 648 cc = snprintf(epd->buf + epd->pos, space, 649 "ep %p cm_id %p state %d flags 0x%lx stid %d " 650 "backlog %d %pI6:%d/%d\n", 651 ep, ep->com.cm_id, (int)ep->com.state, 652 ep->com.flags, ep->stid, ep->backlog, 653 &lsin6->sin6_addr, ntohs(lsin6->sin6_port), 654 ntohs(m_lsin6->sin6_port)); 655 } 656 if (cc < space) 657 epd->pos += cc; 658 return 0; 659 } 660 661 static int ep_release(struct inode *inode, struct file *file) 662 { 663 struct c4iw_debugfs_data *epd = file->private_data; 664 if (!epd) { 665 pr_info("%s null qpd?\n", __func__); 666 return 0; 667 } 668 vfree(epd->buf); 669 kfree(epd); 670 return 0; 671 } 672 673 static int ep_open(struct inode *inode, struct file *file) 674 { 675 struct c4iw_debugfs_data *epd; 676 int ret = 0; 677 int count = 1; 678 679 epd = kmalloc(sizeof(*epd), GFP_KERNEL); 680 if (!epd) { 681 ret = -ENOMEM; 682 goto out; 683 } 684 epd->devp = inode->i_private; 685 epd->pos = 0; 686 687 spin_lock_irq(&epd->devp->lock); 688 idr_for_each(&epd->devp->hwtid_idr, count_idrs, &count); 689 idr_for_each(&epd->devp->atid_idr, count_idrs, &count); 690 idr_for_each(&epd->devp->stid_idr, count_idrs, &count); 691 spin_unlock_irq(&epd->devp->lock); 692 693 epd->bufsize = count * 240; 694 epd->buf = vmalloc(epd->bufsize); 695 if (!epd->buf) { 696 ret = -ENOMEM; 697 goto err1; 698 } 699 700 spin_lock_irq(&epd->devp->lock); 701 idr_for_each(&epd->devp->hwtid_idr, dump_ep, epd); 702 idr_for_each(&epd->devp->atid_idr, dump_ep, epd); 703 idr_for_each(&epd->devp->stid_idr, dump_listen_ep, epd); 704 spin_unlock_irq(&epd->devp->lock); 705 706 file->private_data = epd; 707 goto out; 708 err1: 709 kfree(epd); 710 out: 711 return ret; 712 } 713 714 static const struct file_operations ep_debugfs_fops = { 715 .owner = THIS_MODULE, 716 .open = ep_open, 717 .release = ep_release, 718 .read = debugfs_read, 719 }; 720 721 static int setup_debugfs(struct c4iw_dev *devp) 722 { 723 if (!devp->debugfs_root) 724 return -1; 725 726 debugfs_create_file_size("qps", S_IWUSR, devp->debugfs_root, 727 (void *)devp, &qp_debugfs_fops, 4096); 728 729 debugfs_create_file_size("stags", S_IWUSR, devp->debugfs_root, 730 (void *)devp, &stag_debugfs_fops, 4096); 731 732 debugfs_create_file_size("stats", S_IWUSR, devp->debugfs_root, 733 (void *)devp, &stats_debugfs_fops, 4096); 734 735 debugfs_create_file_size("eps", S_IWUSR, devp->debugfs_root, 736 (void *)devp, &ep_debugfs_fops, 4096); 737 738 if (c4iw_wr_log) 739 debugfs_create_file_size("wr_log", S_IWUSR, devp->debugfs_root, 740 (void *)devp, &wr_log_debugfs_fops, 4096); 741 return 0; 742 } 743 744 void c4iw_release_dev_ucontext(struct c4iw_rdev *rdev, 745 struct c4iw_dev_ucontext *uctx) 746 { 747 struct list_head *pos, *nxt; 748 struct c4iw_qid_list *entry; 749 750 mutex_lock(&uctx->lock); 751 list_for_each_safe(pos, nxt, &uctx->qpids) { 752 entry = list_entry(pos, struct c4iw_qid_list, entry); 753 list_del_init(&entry->entry); 754 if (!(entry->qid & rdev->qpmask)) { 755 c4iw_put_resource(&rdev->resource.qid_table, 756 entry->qid); 757 mutex_lock(&rdev->stats.lock); 758 rdev->stats.qid.cur -= rdev->qpmask + 1; 759 mutex_unlock(&rdev->stats.lock); 760 } 761 kfree(entry); 762 } 763 764 list_for_each_safe(pos, nxt, &uctx->cqids) { 765 entry = list_entry(pos, struct c4iw_qid_list, entry); 766 list_del_init(&entry->entry); 767 kfree(entry); 768 } 769 mutex_unlock(&uctx->lock); 770 } 771 772 void c4iw_init_dev_ucontext(struct c4iw_rdev *rdev, 773 struct c4iw_dev_ucontext *uctx) 774 { 775 INIT_LIST_HEAD(&uctx->qpids); 776 INIT_LIST_HEAD(&uctx->cqids); 777 mutex_init(&uctx->lock); 778 } 779 780 /* Caller takes care of locking if needed */ 781 static int c4iw_rdev_open(struct c4iw_rdev *rdev) 782 { 783 int err; 784 785 c4iw_init_dev_ucontext(rdev, &rdev->uctx); 786 787 /* 788 * This implementation assumes udb_density == ucq_density! Eventually 789 * we might need to support this but for now fail the open. Also the 790 * cqid and qpid range must match for now. 791 */ 792 if (rdev->lldi.udb_density != rdev->lldi.ucq_density) { 793 pr_err("%s: unsupported udb/ucq densities %u/%u\n", 794 pci_name(rdev->lldi.pdev), rdev->lldi.udb_density, 795 rdev->lldi.ucq_density); 796 return -EINVAL; 797 } 798 if (rdev->lldi.vr->qp.start != rdev->lldi.vr->cq.start || 799 rdev->lldi.vr->qp.size != rdev->lldi.vr->cq.size) { 800 pr_err("%s: unsupported qp and cq id ranges qp start %u size %u cq start %u size %u\n", 801 pci_name(rdev->lldi.pdev), rdev->lldi.vr->qp.start, 802 rdev->lldi.vr->qp.size, rdev->lldi.vr->cq.size, 803 rdev->lldi.vr->cq.size); 804 return -EINVAL; 805 } 806 807 rdev->qpmask = rdev->lldi.udb_density - 1; 808 rdev->cqmask = rdev->lldi.ucq_density - 1; 809 pr_debug("dev %s stag start 0x%0x size 0x%0x num stags %d pbl start 0x%0x size 0x%0x rq start 0x%0x size 0x%0x qp qid start %u size %u cq qid start %u size %u\n", 810 pci_name(rdev->lldi.pdev), rdev->lldi.vr->stag.start, 811 rdev->lldi.vr->stag.size, c4iw_num_stags(rdev), 812 rdev->lldi.vr->pbl.start, 813 rdev->lldi.vr->pbl.size, rdev->lldi.vr->rq.start, 814 rdev->lldi.vr->rq.size, 815 rdev->lldi.vr->qp.start, 816 rdev->lldi.vr->qp.size, 817 rdev->lldi.vr->cq.start, 818 rdev->lldi.vr->cq.size); 819 pr_debug("udb %pR db_reg %p gts_reg %p qpmask 0x%x cqmask 0x%x\n", 820 &rdev->lldi.pdev->resource[2], 821 rdev->lldi.db_reg, rdev->lldi.gts_reg, 822 rdev->qpmask, rdev->cqmask); 823 824 if (c4iw_num_stags(rdev) == 0) 825 return -EINVAL; 826 827 rdev->stats.pd.total = T4_MAX_NUM_PD; 828 rdev->stats.stag.total = rdev->lldi.vr->stag.size; 829 rdev->stats.pbl.total = rdev->lldi.vr->pbl.size; 830 rdev->stats.rqt.total = rdev->lldi.vr->rq.size; 831 rdev->stats.ocqp.total = rdev->lldi.vr->ocq.size; 832 rdev->stats.qid.total = rdev->lldi.vr->qp.size; 833 834 err = c4iw_init_resource(rdev, c4iw_num_stags(rdev), T4_MAX_NUM_PD); 835 if (err) { 836 pr_err("error %d initializing resources\n", err); 837 return err; 838 } 839 err = c4iw_pblpool_create(rdev); 840 if (err) { 841 pr_err("error %d initializing pbl pool\n", err); 842 goto destroy_resource; 843 } 844 err = c4iw_rqtpool_create(rdev); 845 if (err) { 846 pr_err("error %d initializing rqt pool\n", err); 847 goto destroy_pblpool; 848 } 849 err = c4iw_ocqp_pool_create(rdev); 850 if (err) { 851 pr_err("error %d initializing ocqp pool\n", err); 852 goto destroy_rqtpool; 853 } 854 rdev->status_page = (struct t4_dev_status_page *) 855 __get_free_page(GFP_KERNEL); 856 if (!rdev->status_page) { 857 err = -ENOMEM; 858 goto destroy_ocqp_pool; 859 } 860 rdev->status_page->qp_start = rdev->lldi.vr->qp.start; 861 rdev->status_page->qp_size = rdev->lldi.vr->qp.size; 862 rdev->status_page->cq_start = rdev->lldi.vr->cq.start; 863 rdev->status_page->cq_size = rdev->lldi.vr->cq.size; 864 865 if (c4iw_wr_log) { 866 rdev->wr_log = kzalloc((1 << c4iw_wr_log_size_order) * 867 sizeof(*rdev->wr_log), GFP_KERNEL); 868 if (rdev->wr_log) { 869 rdev->wr_log_size = 1 << c4iw_wr_log_size_order; 870 atomic_set(&rdev->wr_log_idx, 0); 871 } 872 } 873 874 rdev->free_workq = create_singlethread_workqueue("iw_cxgb4_free"); 875 if (!rdev->free_workq) { 876 err = -ENOMEM; 877 goto err_free_status_page_and_wr_log; 878 } 879 880 rdev->status_page->db_off = 0; 881 882 return 0; 883 err_free_status_page_and_wr_log: 884 if (c4iw_wr_log && rdev->wr_log) 885 kfree(rdev->wr_log); 886 free_page((unsigned long)rdev->status_page); 887 destroy_ocqp_pool: 888 c4iw_ocqp_pool_destroy(rdev); 889 destroy_rqtpool: 890 c4iw_rqtpool_destroy(rdev); 891 destroy_pblpool: 892 c4iw_pblpool_destroy(rdev); 893 destroy_resource: 894 c4iw_destroy_resource(&rdev->resource); 895 return err; 896 } 897 898 static void c4iw_rdev_close(struct c4iw_rdev *rdev) 899 { 900 destroy_workqueue(rdev->free_workq); 901 kfree(rdev->wr_log); 902 c4iw_release_dev_ucontext(rdev, &rdev->uctx); 903 free_page((unsigned long)rdev->status_page); 904 c4iw_pblpool_destroy(rdev); 905 c4iw_rqtpool_destroy(rdev); 906 c4iw_ocqp_pool_destroy(rdev); 907 c4iw_destroy_resource(&rdev->resource); 908 } 909 910 void c4iw_dealloc(struct uld_ctx *ctx) 911 { 912 c4iw_rdev_close(&ctx->dev->rdev); 913 WARN_ON_ONCE(!idr_is_empty(&ctx->dev->cqidr)); 914 idr_destroy(&ctx->dev->cqidr); 915 WARN_ON_ONCE(!idr_is_empty(&ctx->dev->qpidr)); 916 idr_destroy(&ctx->dev->qpidr); 917 WARN_ON_ONCE(!idr_is_empty(&ctx->dev->mmidr)); 918 idr_destroy(&ctx->dev->mmidr); 919 wait_event(ctx->dev->wait, idr_is_empty(&ctx->dev->hwtid_idr)); 920 idr_destroy(&ctx->dev->hwtid_idr); 921 idr_destroy(&ctx->dev->stid_idr); 922 idr_destroy(&ctx->dev->atid_idr); 923 if (ctx->dev->rdev.bar2_kva) 924 iounmap(ctx->dev->rdev.bar2_kva); 925 if (ctx->dev->rdev.oc_mw_kva) 926 iounmap(ctx->dev->rdev.oc_mw_kva); 927 ib_dealloc_device(&ctx->dev->ibdev); 928 ctx->dev = NULL; 929 } 930 931 static void c4iw_remove(struct uld_ctx *ctx) 932 { 933 pr_debug("c4iw_dev %p\n", ctx->dev); 934 c4iw_unregister_device(ctx->dev); 935 c4iw_dealloc(ctx); 936 } 937 938 static int rdma_supported(const struct cxgb4_lld_info *infop) 939 { 940 return infop->vr->stag.size > 0 && infop->vr->pbl.size > 0 && 941 infop->vr->rq.size > 0 && infop->vr->qp.size > 0 && 942 infop->vr->cq.size > 0; 943 } 944 945 static struct c4iw_dev *c4iw_alloc(const struct cxgb4_lld_info *infop) 946 { 947 struct c4iw_dev *devp; 948 int ret; 949 950 if (!rdma_supported(infop)) { 951 pr_info("%s: RDMA not supported on this device\n", 952 pci_name(infop->pdev)); 953 return ERR_PTR(-ENOSYS); 954 } 955 if (!ocqp_supported(infop)) 956 pr_info("%s: On-Chip Queues not supported on this device\n", 957 pci_name(infop->pdev)); 958 959 devp = (struct c4iw_dev *)ib_alloc_device(sizeof(*devp)); 960 if (!devp) { 961 pr_err("Cannot allocate ib device\n"); 962 return ERR_PTR(-ENOMEM); 963 } 964 devp->rdev.lldi = *infop; 965 966 /* init various hw-queue params based on lld info */ 967 pr_debug("Ing. padding boundary is %d, egrsstatuspagesize = %d\n", 968 devp->rdev.lldi.sge_ingpadboundary, 969 devp->rdev.lldi.sge_egrstatuspagesize); 970 971 devp->rdev.hw_queue.t4_eq_status_entries = 972 devp->rdev.lldi.sge_egrstatuspagesize / 64; 973 devp->rdev.hw_queue.t4_max_eq_size = 65520; 974 devp->rdev.hw_queue.t4_max_iq_size = 65520; 975 devp->rdev.hw_queue.t4_max_rq_size = 8192 - 976 devp->rdev.hw_queue.t4_eq_status_entries - 1; 977 devp->rdev.hw_queue.t4_max_sq_size = 978 devp->rdev.hw_queue.t4_max_eq_size - 979 devp->rdev.hw_queue.t4_eq_status_entries - 1; 980 devp->rdev.hw_queue.t4_max_qp_depth = 981 devp->rdev.hw_queue.t4_max_rq_size; 982 devp->rdev.hw_queue.t4_max_cq_depth = 983 devp->rdev.hw_queue.t4_max_iq_size - 2; 984 devp->rdev.hw_queue.t4_stat_len = 985 devp->rdev.lldi.sge_egrstatuspagesize; 986 987 /* 988 * For T5/T6 devices, we map all of BAR2 with WC. 989 * For T4 devices with onchip qp mem, we map only that part 990 * of BAR2 with WC. 991 */ 992 devp->rdev.bar2_pa = pci_resource_start(devp->rdev.lldi.pdev, 2); 993 if (!is_t4(devp->rdev.lldi.adapter_type)) { 994 devp->rdev.bar2_kva = ioremap_wc(devp->rdev.bar2_pa, 995 pci_resource_len(devp->rdev.lldi.pdev, 2)); 996 if (!devp->rdev.bar2_kva) { 997 pr_err("Unable to ioremap BAR2\n"); 998 ib_dealloc_device(&devp->ibdev); 999 return ERR_PTR(-EINVAL); 1000 } 1001 } else if (ocqp_supported(infop)) { 1002 devp->rdev.oc_mw_pa = 1003 pci_resource_start(devp->rdev.lldi.pdev, 2) + 1004 pci_resource_len(devp->rdev.lldi.pdev, 2) - 1005 roundup_pow_of_two(devp->rdev.lldi.vr->ocq.size); 1006 devp->rdev.oc_mw_kva = ioremap_wc(devp->rdev.oc_mw_pa, 1007 devp->rdev.lldi.vr->ocq.size); 1008 if (!devp->rdev.oc_mw_kva) { 1009 pr_err("Unable to ioremap onchip mem\n"); 1010 ib_dealloc_device(&devp->ibdev); 1011 return ERR_PTR(-EINVAL); 1012 } 1013 } 1014 1015 pr_debug("ocq memory: hw_start 0x%x size %u mw_pa 0x%lx mw_kva %p\n", 1016 devp->rdev.lldi.vr->ocq.start, devp->rdev.lldi.vr->ocq.size, 1017 devp->rdev.oc_mw_pa, devp->rdev.oc_mw_kva); 1018 1019 ret = c4iw_rdev_open(&devp->rdev); 1020 if (ret) { 1021 pr_err("Unable to open CXIO rdev err %d\n", ret); 1022 ib_dealloc_device(&devp->ibdev); 1023 return ERR_PTR(ret); 1024 } 1025 1026 idr_init(&devp->cqidr); 1027 idr_init(&devp->qpidr); 1028 idr_init(&devp->mmidr); 1029 idr_init(&devp->hwtid_idr); 1030 idr_init(&devp->stid_idr); 1031 idr_init(&devp->atid_idr); 1032 spin_lock_init(&devp->lock); 1033 mutex_init(&devp->rdev.stats.lock); 1034 mutex_init(&devp->db_mutex); 1035 INIT_LIST_HEAD(&devp->db_fc_list); 1036 init_waitqueue_head(&devp->wait); 1037 devp->avail_ird = devp->rdev.lldi.max_ird_adapter; 1038 1039 if (c4iw_debugfs_root) { 1040 devp->debugfs_root = debugfs_create_dir( 1041 pci_name(devp->rdev.lldi.pdev), 1042 c4iw_debugfs_root); 1043 setup_debugfs(devp); 1044 } 1045 1046 1047 return devp; 1048 } 1049 1050 static void *c4iw_uld_add(const struct cxgb4_lld_info *infop) 1051 { 1052 struct uld_ctx *ctx; 1053 static int vers_printed; 1054 int i; 1055 1056 if (!vers_printed++) 1057 pr_info("Chelsio T4/T5 RDMA Driver - version %s\n", 1058 DRV_VERSION); 1059 1060 ctx = kzalloc(sizeof *ctx, GFP_KERNEL); 1061 if (!ctx) { 1062 ctx = ERR_PTR(-ENOMEM); 1063 goto out; 1064 } 1065 ctx->lldi = *infop; 1066 1067 pr_debug("found device %s nchan %u nrxq %u ntxq %u nports %u\n", 1068 pci_name(ctx->lldi.pdev), 1069 ctx->lldi.nchan, ctx->lldi.nrxq, 1070 ctx->lldi.ntxq, ctx->lldi.nports); 1071 1072 mutex_lock(&dev_mutex); 1073 list_add_tail(&ctx->entry, &uld_ctx_list); 1074 mutex_unlock(&dev_mutex); 1075 1076 for (i = 0; i < ctx->lldi.nrxq; i++) 1077 pr_debug("rxqid[%u] %u\n", i, ctx->lldi.rxq_ids[i]); 1078 out: 1079 return ctx; 1080 } 1081 1082 static inline struct sk_buff *copy_gl_to_skb_pkt(const struct pkt_gl *gl, 1083 const __be64 *rsp, 1084 u32 pktshift) 1085 { 1086 struct sk_buff *skb; 1087 1088 /* 1089 * Allocate space for cpl_pass_accept_req which will be synthesized by 1090 * driver. Once the driver synthesizes the request the skb will go 1091 * through the regular cpl_pass_accept_req processing. 1092 * The math here assumes sizeof cpl_pass_accept_req >= sizeof 1093 * cpl_rx_pkt. 1094 */ 1095 skb = alloc_skb(gl->tot_len + sizeof(struct cpl_pass_accept_req) + 1096 sizeof(struct rss_header) - pktshift, GFP_ATOMIC); 1097 if (unlikely(!skb)) 1098 return NULL; 1099 1100 __skb_put(skb, gl->tot_len + sizeof(struct cpl_pass_accept_req) + 1101 sizeof(struct rss_header) - pktshift); 1102 1103 /* 1104 * This skb will contain: 1105 * rss_header from the rspq descriptor (1 flit) 1106 * cpl_rx_pkt struct from the rspq descriptor (2 flits) 1107 * space for the difference between the size of an 1108 * rx_pkt and pass_accept_req cpl (1 flit) 1109 * the packet data from the gl 1110 */ 1111 skb_copy_to_linear_data(skb, rsp, sizeof(struct cpl_pass_accept_req) + 1112 sizeof(struct rss_header)); 1113 skb_copy_to_linear_data_offset(skb, sizeof(struct rss_header) + 1114 sizeof(struct cpl_pass_accept_req), 1115 gl->va + pktshift, 1116 gl->tot_len - pktshift); 1117 return skb; 1118 } 1119 1120 static inline int recv_rx_pkt(struct c4iw_dev *dev, const struct pkt_gl *gl, 1121 const __be64 *rsp) 1122 { 1123 unsigned int opcode = *(u8 *)rsp; 1124 struct sk_buff *skb; 1125 1126 if (opcode != CPL_RX_PKT) 1127 goto out; 1128 1129 skb = copy_gl_to_skb_pkt(gl , rsp, dev->rdev.lldi.sge_pktshift); 1130 if (skb == NULL) 1131 goto out; 1132 1133 if (c4iw_handlers[opcode] == NULL) { 1134 pr_info("%s no handler opcode 0x%x...\n", __func__, opcode); 1135 kfree_skb(skb); 1136 goto out; 1137 } 1138 c4iw_handlers[opcode](dev, skb); 1139 return 1; 1140 out: 1141 return 0; 1142 } 1143 1144 static int c4iw_uld_rx_handler(void *handle, const __be64 *rsp, 1145 const struct pkt_gl *gl) 1146 { 1147 struct uld_ctx *ctx = handle; 1148 struct c4iw_dev *dev = ctx->dev; 1149 struct sk_buff *skb; 1150 u8 opcode; 1151 1152 if (gl == NULL) { 1153 /* omit RSS and rsp_ctrl at end of descriptor */ 1154 unsigned int len = 64 - sizeof(struct rsp_ctrl) - 8; 1155 1156 skb = alloc_skb(256, GFP_ATOMIC); 1157 if (!skb) 1158 goto nomem; 1159 __skb_put(skb, len); 1160 skb_copy_to_linear_data(skb, &rsp[1], len); 1161 } else if (gl == CXGB4_MSG_AN) { 1162 const struct rsp_ctrl *rc = (void *)rsp; 1163 1164 u32 qid = be32_to_cpu(rc->pldbuflen_qid); 1165 c4iw_ev_handler(dev, qid); 1166 return 0; 1167 } else if (unlikely(*(u8 *)rsp != *(u8 *)gl->va)) { 1168 if (recv_rx_pkt(dev, gl, rsp)) 1169 return 0; 1170 1171 pr_info("%s: unexpected FL contents at %p, RSS %#llx, FL %#llx, len %u\n", 1172 pci_name(ctx->lldi.pdev), gl->va, 1173 be64_to_cpu(*rsp), 1174 be64_to_cpu(*(__force __be64 *)gl->va), 1175 gl->tot_len); 1176 1177 return 0; 1178 } else { 1179 skb = cxgb4_pktgl_to_skb(gl, 128, 128); 1180 if (unlikely(!skb)) 1181 goto nomem; 1182 } 1183 1184 opcode = *(u8 *)rsp; 1185 if (c4iw_handlers[opcode]) { 1186 c4iw_handlers[opcode](dev, skb); 1187 } else { 1188 pr_info("%s no handler opcode 0x%x...\n", __func__, opcode); 1189 kfree_skb(skb); 1190 } 1191 1192 return 0; 1193 nomem: 1194 return -1; 1195 } 1196 1197 static int c4iw_uld_state_change(void *handle, enum cxgb4_state new_state) 1198 { 1199 struct uld_ctx *ctx = handle; 1200 1201 pr_debug("new_state %u\n", new_state); 1202 switch (new_state) { 1203 case CXGB4_STATE_UP: 1204 pr_info("%s: Up\n", pci_name(ctx->lldi.pdev)); 1205 if (!ctx->dev) { 1206 ctx->dev = c4iw_alloc(&ctx->lldi); 1207 if (IS_ERR(ctx->dev)) { 1208 pr_err("%s: initialization failed: %ld\n", 1209 pci_name(ctx->lldi.pdev), 1210 PTR_ERR(ctx->dev)); 1211 ctx->dev = NULL; 1212 break; 1213 } 1214 1215 INIT_WORK(&ctx->reg_work, c4iw_register_device); 1216 queue_work(reg_workq, &ctx->reg_work); 1217 } 1218 break; 1219 case CXGB4_STATE_DOWN: 1220 pr_info("%s: Down\n", pci_name(ctx->lldi.pdev)); 1221 if (ctx->dev) 1222 c4iw_remove(ctx); 1223 break; 1224 case CXGB4_STATE_START_RECOVERY: 1225 pr_info("%s: Fatal Error\n", pci_name(ctx->lldi.pdev)); 1226 if (ctx->dev) { 1227 struct ib_event event; 1228 1229 ctx->dev->rdev.flags |= T4_FATAL_ERROR; 1230 memset(&event, 0, sizeof event); 1231 event.event = IB_EVENT_DEVICE_FATAL; 1232 event.device = &ctx->dev->ibdev; 1233 ib_dispatch_event(&event); 1234 c4iw_remove(ctx); 1235 } 1236 break; 1237 case CXGB4_STATE_DETACH: 1238 pr_info("%s: Detach\n", pci_name(ctx->lldi.pdev)); 1239 if (ctx->dev) 1240 c4iw_remove(ctx); 1241 break; 1242 } 1243 return 0; 1244 } 1245 1246 static int disable_qp_db(int id, void *p, void *data) 1247 { 1248 struct c4iw_qp *qp = p; 1249 1250 t4_disable_wq_db(&qp->wq); 1251 return 0; 1252 } 1253 1254 static void stop_queues(struct uld_ctx *ctx) 1255 { 1256 unsigned long flags; 1257 1258 spin_lock_irqsave(&ctx->dev->lock, flags); 1259 ctx->dev->rdev.stats.db_state_transitions++; 1260 ctx->dev->db_state = STOPPED; 1261 if (ctx->dev->rdev.flags & T4_STATUS_PAGE_DISABLED) 1262 idr_for_each(&ctx->dev->qpidr, disable_qp_db, NULL); 1263 else 1264 ctx->dev->rdev.status_page->db_off = 1; 1265 spin_unlock_irqrestore(&ctx->dev->lock, flags); 1266 } 1267 1268 static int enable_qp_db(int id, void *p, void *data) 1269 { 1270 struct c4iw_qp *qp = p; 1271 1272 t4_enable_wq_db(&qp->wq); 1273 return 0; 1274 } 1275 1276 static void resume_rc_qp(struct c4iw_qp *qp) 1277 { 1278 spin_lock(&qp->lock); 1279 t4_ring_sq_db(&qp->wq, qp->wq.sq.wq_pidx_inc, NULL); 1280 qp->wq.sq.wq_pidx_inc = 0; 1281 t4_ring_rq_db(&qp->wq, qp->wq.rq.wq_pidx_inc, NULL); 1282 qp->wq.rq.wq_pidx_inc = 0; 1283 spin_unlock(&qp->lock); 1284 } 1285 1286 static void resume_a_chunk(struct uld_ctx *ctx) 1287 { 1288 int i; 1289 struct c4iw_qp *qp; 1290 1291 for (i = 0; i < DB_FC_RESUME_SIZE; i++) { 1292 qp = list_first_entry(&ctx->dev->db_fc_list, struct c4iw_qp, 1293 db_fc_entry); 1294 list_del_init(&qp->db_fc_entry); 1295 resume_rc_qp(qp); 1296 if (list_empty(&ctx->dev->db_fc_list)) 1297 break; 1298 } 1299 } 1300 1301 static void resume_queues(struct uld_ctx *ctx) 1302 { 1303 spin_lock_irq(&ctx->dev->lock); 1304 if (ctx->dev->db_state != STOPPED) 1305 goto out; 1306 ctx->dev->db_state = FLOW_CONTROL; 1307 while (1) { 1308 if (list_empty(&ctx->dev->db_fc_list)) { 1309 WARN_ON(ctx->dev->db_state != FLOW_CONTROL); 1310 ctx->dev->db_state = NORMAL; 1311 ctx->dev->rdev.stats.db_state_transitions++; 1312 if (ctx->dev->rdev.flags & T4_STATUS_PAGE_DISABLED) { 1313 idr_for_each(&ctx->dev->qpidr, enable_qp_db, 1314 NULL); 1315 } else { 1316 ctx->dev->rdev.status_page->db_off = 0; 1317 } 1318 break; 1319 } else { 1320 if (cxgb4_dbfifo_count(ctx->dev->rdev.lldi.ports[0], 1) 1321 < (ctx->dev->rdev.lldi.dbfifo_int_thresh << 1322 DB_FC_DRAIN_THRESH)) { 1323 resume_a_chunk(ctx); 1324 } 1325 if (!list_empty(&ctx->dev->db_fc_list)) { 1326 spin_unlock_irq(&ctx->dev->lock); 1327 if (DB_FC_RESUME_DELAY) { 1328 set_current_state(TASK_UNINTERRUPTIBLE); 1329 schedule_timeout(DB_FC_RESUME_DELAY); 1330 } 1331 spin_lock_irq(&ctx->dev->lock); 1332 if (ctx->dev->db_state != FLOW_CONTROL) 1333 break; 1334 } 1335 } 1336 } 1337 out: 1338 if (ctx->dev->db_state != NORMAL) 1339 ctx->dev->rdev.stats.db_fc_interruptions++; 1340 spin_unlock_irq(&ctx->dev->lock); 1341 } 1342 1343 struct qp_list { 1344 unsigned idx; 1345 struct c4iw_qp **qps; 1346 }; 1347 1348 static int add_and_ref_qp(int id, void *p, void *data) 1349 { 1350 struct qp_list *qp_listp = data; 1351 struct c4iw_qp *qp = p; 1352 1353 c4iw_qp_add_ref(&qp->ibqp); 1354 qp_listp->qps[qp_listp->idx++] = qp; 1355 return 0; 1356 } 1357 1358 static int count_qps(int id, void *p, void *data) 1359 { 1360 unsigned *countp = data; 1361 (*countp)++; 1362 return 0; 1363 } 1364 1365 static void deref_qps(struct qp_list *qp_list) 1366 { 1367 int idx; 1368 1369 for (idx = 0; idx < qp_list->idx; idx++) 1370 c4iw_qp_rem_ref(&qp_list->qps[idx]->ibqp); 1371 } 1372 1373 static void recover_lost_dbs(struct uld_ctx *ctx, struct qp_list *qp_list) 1374 { 1375 int idx; 1376 int ret; 1377 1378 for (idx = 0; idx < qp_list->idx; idx++) { 1379 struct c4iw_qp *qp = qp_list->qps[idx]; 1380 1381 spin_lock_irq(&qp->rhp->lock); 1382 spin_lock(&qp->lock); 1383 ret = cxgb4_sync_txq_pidx(qp->rhp->rdev.lldi.ports[0], 1384 qp->wq.sq.qid, 1385 t4_sq_host_wq_pidx(&qp->wq), 1386 t4_sq_wq_size(&qp->wq)); 1387 if (ret) { 1388 pr_err("%s: Fatal error - DB overflow recovery failed - error syncing SQ qid %u\n", 1389 pci_name(ctx->lldi.pdev), qp->wq.sq.qid); 1390 spin_unlock(&qp->lock); 1391 spin_unlock_irq(&qp->rhp->lock); 1392 return; 1393 } 1394 qp->wq.sq.wq_pidx_inc = 0; 1395 1396 ret = cxgb4_sync_txq_pidx(qp->rhp->rdev.lldi.ports[0], 1397 qp->wq.rq.qid, 1398 t4_rq_host_wq_pidx(&qp->wq), 1399 t4_rq_wq_size(&qp->wq)); 1400 1401 if (ret) { 1402 pr_err("%s: Fatal error - DB overflow recovery failed - error syncing RQ qid %u\n", 1403 pci_name(ctx->lldi.pdev), qp->wq.rq.qid); 1404 spin_unlock(&qp->lock); 1405 spin_unlock_irq(&qp->rhp->lock); 1406 return; 1407 } 1408 qp->wq.rq.wq_pidx_inc = 0; 1409 spin_unlock(&qp->lock); 1410 spin_unlock_irq(&qp->rhp->lock); 1411 1412 /* Wait for the dbfifo to drain */ 1413 while (cxgb4_dbfifo_count(qp->rhp->rdev.lldi.ports[0], 1) > 0) { 1414 set_current_state(TASK_UNINTERRUPTIBLE); 1415 schedule_timeout(usecs_to_jiffies(10)); 1416 } 1417 } 1418 } 1419 1420 static void recover_queues(struct uld_ctx *ctx) 1421 { 1422 int count = 0; 1423 struct qp_list qp_list; 1424 int ret; 1425 1426 /* slow everybody down */ 1427 set_current_state(TASK_UNINTERRUPTIBLE); 1428 schedule_timeout(usecs_to_jiffies(1000)); 1429 1430 /* flush the SGE contexts */ 1431 ret = cxgb4_flush_eq_cache(ctx->dev->rdev.lldi.ports[0]); 1432 if (ret) { 1433 pr_err("%s: Fatal error - DB overflow recovery failed\n", 1434 pci_name(ctx->lldi.pdev)); 1435 return; 1436 } 1437 1438 /* Count active queues so we can build a list of queues to recover */ 1439 spin_lock_irq(&ctx->dev->lock); 1440 WARN_ON(ctx->dev->db_state != STOPPED); 1441 ctx->dev->db_state = RECOVERY; 1442 idr_for_each(&ctx->dev->qpidr, count_qps, &count); 1443 1444 qp_list.qps = kzalloc(count * sizeof *qp_list.qps, GFP_ATOMIC); 1445 if (!qp_list.qps) { 1446 spin_unlock_irq(&ctx->dev->lock); 1447 return; 1448 } 1449 qp_list.idx = 0; 1450 1451 /* add and ref each qp so it doesn't get freed */ 1452 idr_for_each(&ctx->dev->qpidr, add_and_ref_qp, &qp_list); 1453 1454 spin_unlock_irq(&ctx->dev->lock); 1455 1456 /* now traverse the list in a safe context to recover the db state*/ 1457 recover_lost_dbs(ctx, &qp_list); 1458 1459 /* we're almost done! deref the qps and clean up */ 1460 deref_qps(&qp_list); 1461 kfree(qp_list.qps); 1462 1463 spin_lock_irq(&ctx->dev->lock); 1464 WARN_ON(ctx->dev->db_state != RECOVERY); 1465 ctx->dev->db_state = STOPPED; 1466 spin_unlock_irq(&ctx->dev->lock); 1467 } 1468 1469 static int c4iw_uld_control(void *handle, enum cxgb4_control control, ...) 1470 { 1471 struct uld_ctx *ctx = handle; 1472 1473 switch (control) { 1474 case CXGB4_CONTROL_DB_FULL: 1475 stop_queues(ctx); 1476 ctx->dev->rdev.stats.db_full++; 1477 break; 1478 case CXGB4_CONTROL_DB_EMPTY: 1479 resume_queues(ctx); 1480 mutex_lock(&ctx->dev->rdev.stats.lock); 1481 ctx->dev->rdev.stats.db_empty++; 1482 mutex_unlock(&ctx->dev->rdev.stats.lock); 1483 break; 1484 case CXGB4_CONTROL_DB_DROP: 1485 recover_queues(ctx); 1486 mutex_lock(&ctx->dev->rdev.stats.lock); 1487 ctx->dev->rdev.stats.db_drop++; 1488 mutex_unlock(&ctx->dev->rdev.stats.lock); 1489 break; 1490 default: 1491 pr_warn("%s: unknown control cmd %u\n", 1492 pci_name(ctx->lldi.pdev), control); 1493 break; 1494 } 1495 return 0; 1496 } 1497 1498 static struct cxgb4_uld_info c4iw_uld_info = { 1499 .name = DRV_NAME, 1500 .nrxq = MAX_ULD_QSETS, 1501 .ntxq = MAX_ULD_QSETS, 1502 .rxq_size = 511, 1503 .ciq = true, 1504 .lro = false, 1505 .add = c4iw_uld_add, 1506 .rx_handler = c4iw_uld_rx_handler, 1507 .state_change = c4iw_uld_state_change, 1508 .control = c4iw_uld_control, 1509 }; 1510 1511 void _c4iw_free_wr_wait(struct kref *kref) 1512 { 1513 struct c4iw_wr_wait *wr_waitp; 1514 1515 wr_waitp = container_of(kref, struct c4iw_wr_wait, kref); 1516 pr_debug("Free wr_wait %p\n", wr_waitp); 1517 kfree(wr_waitp); 1518 } 1519 1520 struct c4iw_wr_wait *c4iw_alloc_wr_wait(gfp_t gfp) 1521 { 1522 struct c4iw_wr_wait *wr_waitp; 1523 1524 wr_waitp = kzalloc(sizeof(*wr_waitp), gfp); 1525 if (wr_waitp) { 1526 kref_init(&wr_waitp->kref); 1527 pr_debug("wr_wait %p\n", wr_waitp); 1528 } 1529 return wr_waitp; 1530 } 1531 1532 static int __init c4iw_init_module(void) 1533 { 1534 int err; 1535 1536 err = c4iw_cm_init(); 1537 if (err) 1538 return err; 1539 1540 c4iw_debugfs_root = debugfs_create_dir(DRV_NAME, NULL); 1541 if (!c4iw_debugfs_root) 1542 pr_warn("could not create debugfs entry, continuing\n"); 1543 1544 reg_workq = create_singlethread_workqueue("Register_iWARP_device"); 1545 if (!reg_workq) { 1546 pr_err("Failed creating workqueue to register iwarp device\n"); 1547 return -ENOMEM; 1548 } 1549 1550 cxgb4_register_uld(CXGB4_ULD_RDMA, &c4iw_uld_info); 1551 1552 return 0; 1553 } 1554 1555 static void __exit c4iw_exit_module(void) 1556 { 1557 struct uld_ctx *ctx, *tmp; 1558 1559 mutex_lock(&dev_mutex); 1560 list_for_each_entry_safe(ctx, tmp, &uld_ctx_list, entry) { 1561 if (ctx->dev) 1562 c4iw_remove(ctx); 1563 kfree(ctx); 1564 } 1565 mutex_unlock(&dev_mutex); 1566 flush_workqueue(reg_workq); 1567 destroy_workqueue(reg_workq); 1568 cxgb4_unregister_uld(CXGB4_ULD_RDMA); 1569 c4iw_cm_term(); 1570 debugfs_remove_recursive(c4iw_debugfs_root); 1571 } 1572 1573 module_init(c4iw_init_module); 1574 module_exit(c4iw_exit_module); 1575