1 /* 2 * Copyright (c) 2009-2010 Chelsio, Inc. All rights reserved. 3 * 4 * This software is available to you under a choice of one of two 5 * licenses. You may choose to be licensed under the terms of the GNU 6 * General Public License (GPL) Version 2, available from the file 7 * COPYING in the main directory of this source tree, or the 8 * OpenIB.org BSD license below: 9 * 10 * Redistribution and use in source and binary forms, with or 11 * without modification, are permitted provided that the following 12 * conditions are met: 13 * 14 * - Redistributions of source code must retain the above 15 * copyright notice, this list of conditions and the following 16 * disclaimer. 17 * 18 * - Redistributions in binary form must reproduce the above 19 * copyright notice, this list of conditions and the following 20 * disclaimer in the documentation and/or other materials 21 * provided with the distribution. 22 * 23 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, 24 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF 25 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND 26 * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS 27 * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN 28 * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN 29 * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE 30 * SOFTWARE. 31 */ 32 #include <linux/module.h> 33 #include <linux/moduleparam.h> 34 #include <linux/debugfs.h> 35 #include <linux/vmalloc.h> 36 #include <linux/math64.h> 37 38 #include <rdma/ib_verbs.h> 39 40 #include "iw_cxgb4.h" 41 42 #define DRV_VERSION "0.1" 43 44 MODULE_AUTHOR("Steve Wise"); 45 MODULE_DESCRIPTION("Chelsio T4/T5 RDMA Driver"); 46 MODULE_LICENSE("Dual BSD/GPL"); 47 48 static int allow_db_fc_on_t5; 49 module_param(allow_db_fc_on_t5, int, 0644); 50 MODULE_PARM_DESC(allow_db_fc_on_t5, 51 "Allow DB Flow Control on T5 (default = 0)"); 52 53 static int allow_db_coalescing_on_t5; 54 module_param(allow_db_coalescing_on_t5, int, 0644); 55 MODULE_PARM_DESC(allow_db_coalescing_on_t5, 56 "Allow DB Coalescing on T5 (default = 0)"); 57 58 int c4iw_wr_log = 0; 59 module_param(c4iw_wr_log, int, 0444); 60 MODULE_PARM_DESC(c4iw_wr_log, "Enables logging of work request timing data."); 61 62 static int c4iw_wr_log_size_order = 12; 63 module_param(c4iw_wr_log_size_order, int, 0444); 64 MODULE_PARM_DESC(c4iw_wr_log_size_order, 65 "Number of entries (log2) in the work request timing log."); 66 67 struct uld_ctx { 68 struct list_head entry; 69 struct cxgb4_lld_info lldi; 70 struct c4iw_dev *dev; 71 }; 72 73 static LIST_HEAD(uld_ctx_list); 74 static DEFINE_MUTEX(dev_mutex); 75 76 #define DB_FC_RESUME_SIZE 64 77 #define DB_FC_RESUME_DELAY 1 78 #define DB_FC_DRAIN_THRESH 0 79 80 static struct dentry *c4iw_debugfs_root; 81 82 struct c4iw_debugfs_data { 83 struct c4iw_dev *devp; 84 char *buf; 85 int bufsize; 86 int pos; 87 }; 88 89 static int count_idrs(int id, void *p, void *data) 90 { 91 int *countp = data; 92 93 *countp = *countp + 1; 94 return 0; 95 } 96 97 static ssize_t debugfs_read(struct file *file, char __user *buf, size_t count, 98 loff_t *ppos) 99 { 100 struct c4iw_debugfs_data *d = file->private_data; 101 102 return simple_read_from_buffer(buf, count, ppos, d->buf, d->pos); 103 } 104 105 void c4iw_log_wr_stats(struct t4_wq *wq, struct t4_cqe *cqe) 106 { 107 struct wr_log_entry le; 108 int idx; 109 110 if (!wq->rdev->wr_log) 111 return; 112 113 idx = (atomic_inc_return(&wq->rdev->wr_log_idx) - 1) & 114 (wq->rdev->wr_log_size - 1); 115 le.poll_sge_ts = cxgb4_read_sge_timestamp(wq->rdev->lldi.ports[0]); 116 getnstimeofday(&le.poll_host_ts); 117 le.valid = 1; 118 le.cqe_sge_ts = CQE_TS(cqe); 119 if (SQ_TYPE(cqe)) { 120 le.qid = wq->sq.qid; 121 le.opcode = CQE_OPCODE(cqe); 122 le.post_host_ts = wq->sq.sw_sq[wq->sq.cidx].host_ts; 123 le.post_sge_ts = wq->sq.sw_sq[wq->sq.cidx].sge_ts; 124 le.wr_id = CQE_WRID_SQ_IDX(cqe); 125 } else { 126 le.qid = wq->rq.qid; 127 le.opcode = FW_RI_RECEIVE; 128 le.post_host_ts = wq->rq.sw_rq[wq->rq.cidx].host_ts; 129 le.post_sge_ts = wq->rq.sw_rq[wq->rq.cidx].sge_ts; 130 le.wr_id = CQE_WRID_MSN(cqe); 131 } 132 wq->rdev->wr_log[idx] = le; 133 } 134 135 static int wr_log_show(struct seq_file *seq, void *v) 136 { 137 struct c4iw_dev *dev = seq->private; 138 struct timespec prev_ts = {0, 0}; 139 struct wr_log_entry *lep; 140 int prev_ts_set = 0; 141 int idx, end; 142 143 #define ts2ns(ts) div64_u64((ts) * dev->rdev.lldi.cclk_ps, 1000) 144 145 idx = atomic_read(&dev->rdev.wr_log_idx) & 146 (dev->rdev.wr_log_size - 1); 147 end = idx - 1; 148 if (end < 0) 149 end = dev->rdev.wr_log_size - 1; 150 lep = &dev->rdev.wr_log[idx]; 151 while (idx != end) { 152 if (lep->valid) { 153 if (!prev_ts_set) { 154 prev_ts_set = 1; 155 prev_ts = lep->poll_host_ts; 156 } 157 seq_printf(seq, "%04u: sec %lu nsec %lu qid %u opcode " 158 "%u %s 0x%x host_wr_delta sec %lu nsec %lu " 159 "post_sge_ts 0x%llx cqe_sge_ts 0x%llx " 160 "poll_sge_ts 0x%llx post_poll_delta_ns %llu " 161 "cqe_poll_delta_ns %llu\n", 162 idx, 163 timespec_sub(lep->poll_host_ts, 164 prev_ts).tv_sec, 165 timespec_sub(lep->poll_host_ts, 166 prev_ts).tv_nsec, 167 lep->qid, lep->opcode, 168 lep->opcode == FW_RI_RECEIVE ? 169 "msn" : "wrid", 170 lep->wr_id, 171 timespec_sub(lep->poll_host_ts, 172 lep->post_host_ts).tv_sec, 173 timespec_sub(lep->poll_host_ts, 174 lep->post_host_ts).tv_nsec, 175 lep->post_sge_ts, lep->cqe_sge_ts, 176 lep->poll_sge_ts, 177 ts2ns(lep->poll_sge_ts - lep->post_sge_ts), 178 ts2ns(lep->poll_sge_ts - lep->cqe_sge_ts)); 179 prev_ts = lep->poll_host_ts; 180 } 181 idx++; 182 if (idx > (dev->rdev.wr_log_size - 1)) 183 idx = 0; 184 lep = &dev->rdev.wr_log[idx]; 185 } 186 #undef ts2ns 187 return 0; 188 } 189 190 static int wr_log_open(struct inode *inode, struct file *file) 191 { 192 return single_open(file, wr_log_show, inode->i_private); 193 } 194 195 static ssize_t wr_log_clear(struct file *file, const char __user *buf, 196 size_t count, loff_t *pos) 197 { 198 struct c4iw_dev *dev = ((struct seq_file *)file->private_data)->private; 199 int i; 200 201 if (dev->rdev.wr_log) 202 for (i = 0; i < dev->rdev.wr_log_size; i++) 203 dev->rdev.wr_log[i].valid = 0; 204 return count; 205 } 206 207 static const struct file_operations wr_log_debugfs_fops = { 208 .owner = THIS_MODULE, 209 .open = wr_log_open, 210 .release = single_release, 211 .read = seq_read, 212 .llseek = seq_lseek, 213 .write = wr_log_clear, 214 }; 215 216 static struct sockaddr_in zero_sin = { 217 .sin_family = AF_INET, 218 }; 219 220 static struct sockaddr_in6 zero_sin6 = { 221 .sin6_family = AF_INET6, 222 }; 223 224 static void set_ep_sin_addrs(struct c4iw_ep *ep, 225 struct sockaddr_in **lsin, 226 struct sockaddr_in **rsin, 227 struct sockaddr_in **m_lsin, 228 struct sockaddr_in **m_rsin) 229 { 230 struct iw_cm_id *id = ep->com.cm_id; 231 232 *lsin = (struct sockaddr_in *)&ep->com.local_addr; 233 *rsin = (struct sockaddr_in *)&ep->com.remote_addr; 234 if (id) { 235 *m_lsin = (struct sockaddr_in *)&id->m_local_addr; 236 *m_rsin = (struct sockaddr_in *)&id->m_remote_addr; 237 } else { 238 *m_lsin = &zero_sin; 239 *m_rsin = &zero_sin; 240 } 241 } 242 243 static void set_ep_sin6_addrs(struct c4iw_ep *ep, 244 struct sockaddr_in6 **lsin6, 245 struct sockaddr_in6 **rsin6, 246 struct sockaddr_in6 **m_lsin6, 247 struct sockaddr_in6 **m_rsin6) 248 { 249 struct iw_cm_id *id = ep->com.cm_id; 250 251 *lsin6 = (struct sockaddr_in6 *)&ep->com.local_addr; 252 *rsin6 = (struct sockaddr_in6 *)&ep->com.remote_addr; 253 if (id) { 254 *m_lsin6 = (struct sockaddr_in6 *)&id->m_local_addr; 255 *m_rsin6 = (struct sockaddr_in6 *)&id->m_remote_addr; 256 } else { 257 *m_lsin6 = &zero_sin6; 258 *m_rsin6 = &zero_sin6; 259 } 260 } 261 262 static int dump_qp(int id, void *p, void *data) 263 { 264 struct c4iw_qp *qp = p; 265 struct c4iw_debugfs_data *qpd = data; 266 int space; 267 int cc; 268 269 if (id != qp->wq.sq.qid) 270 return 0; 271 272 space = qpd->bufsize - qpd->pos - 1; 273 if (space == 0) 274 return 1; 275 276 if (qp->ep) { 277 struct c4iw_ep *ep = qp->ep; 278 279 if (ep->com.local_addr.ss_family == AF_INET) { 280 struct sockaddr_in *lsin; 281 struct sockaddr_in *rsin; 282 struct sockaddr_in *m_lsin; 283 struct sockaddr_in *m_rsin; 284 285 set_ep_sin_addrs(ep, &lsin, &rsin, &m_lsin, &m_rsin); 286 cc = snprintf(qpd->buf + qpd->pos, space, 287 "rc qp sq id %u rq id %u state %u " 288 "onchip %u ep tid %u state %u " 289 "%pI4:%u/%u->%pI4:%u/%u\n", 290 qp->wq.sq.qid, qp->wq.rq.qid, 291 (int)qp->attr.state, 292 qp->wq.sq.flags & T4_SQ_ONCHIP, 293 ep->hwtid, (int)ep->com.state, 294 &lsin->sin_addr, ntohs(lsin->sin_port), 295 ntohs(m_lsin->sin_port), 296 &rsin->sin_addr, ntohs(rsin->sin_port), 297 ntohs(m_rsin->sin_port)); 298 } else { 299 struct sockaddr_in6 *lsin6; 300 struct sockaddr_in6 *rsin6; 301 struct sockaddr_in6 *m_lsin6; 302 struct sockaddr_in6 *m_rsin6; 303 304 set_ep_sin6_addrs(ep, &lsin6, &rsin6, &m_lsin6, 305 &m_rsin6); 306 cc = snprintf(qpd->buf + qpd->pos, space, 307 "rc qp sq id %u rq id %u state %u " 308 "onchip %u ep tid %u state %u " 309 "%pI6:%u/%u->%pI6:%u/%u\n", 310 qp->wq.sq.qid, qp->wq.rq.qid, 311 (int)qp->attr.state, 312 qp->wq.sq.flags & T4_SQ_ONCHIP, 313 ep->hwtid, (int)ep->com.state, 314 &lsin6->sin6_addr, 315 ntohs(lsin6->sin6_port), 316 ntohs(m_lsin6->sin6_port), 317 &rsin6->sin6_addr, 318 ntohs(rsin6->sin6_port), 319 ntohs(m_rsin6->sin6_port)); 320 } 321 } else 322 cc = snprintf(qpd->buf + qpd->pos, space, 323 "qp sq id %u rq id %u state %u onchip %u\n", 324 qp->wq.sq.qid, qp->wq.rq.qid, 325 (int)qp->attr.state, 326 qp->wq.sq.flags & T4_SQ_ONCHIP); 327 if (cc < space) 328 qpd->pos += cc; 329 return 0; 330 } 331 332 static int qp_release(struct inode *inode, struct file *file) 333 { 334 struct c4iw_debugfs_data *qpd = file->private_data; 335 if (!qpd) { 336 pr_info("%s null qpd?\n", __func__); 337 return 0; 338 } 339 vfree(qpd->buf); 340 kfree(qpd); 341 return 0; 342 } 343 344 static int qp_open(struct inode *inode, struct file *file) 345 { 346 struct c4iw_debugfs_data *qpd; 347 int count = 1; 348 349 qpd = kmalloc(sizeof *qpd, GFP_KERNEL); 350 if (!qpd) 351 return -ENOMEM; 352 353 qpd->devp = inode->i_private; 354 qpd->pos = 0; 355 356 spin_lock_irq(&qpd->devp->lock); 357 idr_for_each(&qpd->devp->qpidr, count_idrs, &count); 358 spin_unlock_irq(&qpd->devp->lock); 359 360 qpd->bufsize = count * 180; 361 qpd->buf = vmalloc(qpd->bufsize); 362 if (!qpd->buf) { 363 kfree(qpd); 364 return -ENOMEM; 365 } 366 367 spin_lock_irq(&qpd->devp->lock); 368 idr_for_each(&qpd->devp->qpidr, dump_qp, qpd); 369 spin_unlock_irq(&qpd->devp->lock); 370 371 qpd->buf[qpd->pos++] = 0; 372 file->private_data = qpd; 373 return 0; 374 } 375 376 static const struct file_operations qp_debugfs_fops = { 377 .owner = THIS_MODULE, 378 .open = qp_open, 379 .release = qp_release, 380 .read = debugfs_read, 381 .llseek = default_llseek, 382 }; 383 384 static int dump_stag(int id, void *p, void *data) 385 { 386 struct c4iw_debugfs_data *stagd = data; 387 int space; 388 int cc; 389 struct fw_ri_tpte tpte; 390 int ret; 391 392 space = stagd->bufsize - stagd->pos - 1; 393 if (space == 0) 394 return 1; 395 396 ret = cxgb4_read_tpte(stagd->devp->rdev.lldi.ports[0], (u32)id<<8, 397 (__be32 *)&tpte); 398 if (ret) { 399 dev_err(&stagd->devp->rdev.lldi.pdev->dev, 400 "%s cxgb4_read_tpte err %d\n", __func__, ret); 401 return ret; 402 } 403 cc = snprintf(stagd->buf + stagd->pos, space, 404 "stag: idx 0x%x valid %d key 0x%x state %d pdid %d " 405 "perm 0x%x ps %d len 0x%llx va 0x%llx\n", 406 (u32)id<<8, 407 FW_RI_TPTE_VALID_G(ntohl(tpte.valid_to_pdid)), 408 FW_RI_TPTE_STAGKEY_G(ntohl(tpte.valid_to_pdid)), 409 FW_RI_TPTE_STAGSTATE_G(ntohl(tpte.valid_to_pdid)), 410 FW_RI_TPTE_PDID_G(ntohl(tpte.valid_to_pdid)), 411 FW_RI_TPTE_PERM_G(ntohl(tpte.locread_to_qpid)), 412 FW_RI_TPTE_PS_G(ntohl(tpte.locread_to_qpid)), 413 ((u64)ntohl(tpte.len_hi) << 32) | ntohl(tpte.len_lo), 414 ((u64)ntohl(tpte.va_hi) << 32) | ntohl(tpte.va_lo_fbo)); 415 if (cc < space) 416 stagd->pos += cc; 417 return 0; 418 } 419 420 static int stag_release(struct inode *inode, struct file *file) 421 { 422 struct c4iw_debugfs_data *stagd = file->private_data; 423 if (!stagd) { 424 pr_info("%s null stagd?\n", __func__); 425 return 0; 426 } 427 vfree(stagd->buf); 428 kfree(stagd); 429 return 0; 430 } 431 432 static int stag_open(struct inode *inode, struct file *file) 433 { 434 struct c4iw_debugfs_data *stagd; 435 int ret = 0; 436 int count = 1; 437 438 stagd = kmalloc(sizeof *stagd, GFP_KERNEL); 439 if (!stagd) { 440 ret = -ENOMEM; 441 goto out; 442 } 443 stagd->devp = inode->i_private; 444 stagd->pos = 0; 445 446 spin_lock_irq(&stagd->devp->lock); 447 idr_for_each(&stagd->devp->mmidr, count_idrs, &count); 448 spin_unlock_irq(&stagd->devp->lock); 449 450 stagd->bufsize = count * 256; 451 stagd->buf = vmalloc(stagd->bufsize); 452 if (!stagd->buf) { 453 ret = -ENOMEM; 454 goto err1; 455 } 456 457 spin_lock_irq(&stagd->devp->lock); 458 idr_for_each(&stagd->devp->mmidr, dump_stag, stagd); 459 spin_unlock_irq(&stagd->devp->lock); 460 461 stagd->buf[stagd->pos++] = 0; 462 file->private_data = stagd; 463 goto out; 464 err1: 465 kfree(stagd); 466 out: 467 return ret; 468 } 469 470 static const struct file_operations stag_debugfs_fops = { 471 .owner = THIS_MODULE, 472 .open = stag_open, 473 .release = stag_release, 474 .read = debugfs_read, 475 .llseek = default_llseek, 476 }; 477 478 static char *db_state_str[] = {"NORMAL", "FLOW_CONTROL", "RECOVERY", "STOPPED"}; 479 480 static int stats_show(struct seq_file *seq, void *v) 481 { 482 struct c4iw_dev *dev = seq->private; 483 484 seq_printf(seq, " Object: %10s %10s %10s %10s\n", "Total", "Current", 485 "Max", "Fail"); 486 seq_printf(seq, " PDID: %10llu %10llu %10llu %10llu\n", 487 dev->rdev.stats.pd.total, dev->rdev.stats.pd.cur, 488 dev->rdev.stats.pd.max, dev->rdev.stats.pd.fail); 489 seq_printf(seq, " QID: %10llu %10llu %10llu %10llu\n", 490 dev->rdev.stats.qid.total, dev->rdev.stats.qid.cur, 491 dev->rdev.stats.qid.max, dev->rdev.stats.qid.fail); 492 seq_printf(seq, " TPTMEM: %10llu %10llu %10llu %10llu\n", 493 dev->rdev.stats.stag.total, dev->rdev.stats.stag.cur, 494 dev->rdev.stats.stag.max, dev->rdev.stats.stag.fail); 495 seq_printf(seq, " PBLMEM: %10llu %10llu %10llu %10llu\n", 496 dev->rdev.stats.pbl.total, dev->rdev.stats.pbl.cur, 497 dev->rdev.stats.pbl.max, dev->rdev.stats.pbl.fail); 498 seq_printf(seq, " RQTMEM: %10llu %10llu %10llu %10llu\n", 499 dev->rdev.stats.rqt.total, dev->rdev.stats.rqt.cur, 500 dev->rdev.stats.rqt.max, dev->rdev.stats.rqt.fail); 501 seq_printf(seq, " OCQPMEM: %10llu %10llu %10llu %10llu\n", 502 dev->rdev.stats.ocqp.total, dev->rdev.stats.ocqp.cur, 503 dev->rdev.stats.ocqp.max, dev->rdev.stats.ocqp.fail); 504 seq_printf(seq, " DB FULL: %10llu\n", dev->rdev.stats.db_full); 505 seq_printf(seq, " DB EMPTY: %10llu\n", dev->rdev.stats.db_empty); 506 seq_printf(seq, " DB DROP: %10llu\n", dev->rdev.stats.db_drop); 507 seq_printf(seq, " DB State: %s Transitions %llu FC Interruptions %llu\n", 508 db_state_str[dev->db_state], 509 dev->rdev.stats.db_state_transitions, 510 dev->rdev.stats.db_fc_interruptions); 511 seq_printf(seq, "TCAM_FULL: %10llu\n", dev->rdev.stats.tcam_full); 512 seq_printf(seq, "ACT_OFLD_CONN_FAILS: %10llu\n", 513 dev->rdev.stats.act_ofld_conn_fails); 514 seq_printf(seq, "PAS_OFLD_CONN_FAILS: %10llu\n", 515 dev->rdev.stats.pas_ofld_conn_fails); 516 seq_printf(seq, "NEG_ADV_RCVD: %10llu\n", dev->rdev.stats.neg_adv); 517 seq_printf(seq, "AVAILABLE IRD: %10u\n", dev->avail_ird); 518 return 0; 519 } 520 521 static int stats_open(struct inode *inode, struct file *file) 522 { 523 return single_open(file, stats_show, inode->i_private); 524 } 525 526 static ssize_t stats_clear(struct file *file, const char __user *buf, 527 size_t count, loff_t *pos) 528 { 529 struct c4iw_dev *dev = ((struct seq_file *)file->private_data)->private; 530 531 mutex_lock(&dev->rdev.stats.lock); 532 dev->rdev.stats.pd.max = 0; 533 dev->rdev.stats.pd.fail = 0; 534 dev->rdev.stats.qid.max = 0; 535 dev->rdev.stats.qid.fail = 0; 536 dev->rdev.stats.stag.max = 0; 537 dev->rdev.stats.stag.fail = 0; 538 dev->rdev.stats.pbl.max = 0; 539 dev->rdev.stats.pbl.fail = 0; 540 dev->rdev.stats.rqt.max = 0; 541 dev->rdev.stats.rqt.fail = 0; 542 dev->rdev.stats.ocqp.max = 0; 543 dev->rdev.stats.ocqp.fail = 0; 544 dev->rdev.stats.db_full = 0; 545 dev->rdev.stats.db_empty = 0; 546 dev->rdev.stats.db_drop = 0; 547 dev->rdev.stats.db_state_transitions = 0; 548 dev->rdev.stats.tcam_full = 0; 549 dev->rdev.stats.act_ofld_conn_fails = 0; 550 dev->rdev.stats.pas_ofld_conn_fails = 0; 551 mutex_unlock(&dev->rdev.stats.lock); 552 return count; 553 } 554 555 static const struct file_operations stats_debugfs_fops = { 556 .owner = THIS_MODULE, 557 .open = stats_open, 558 .release = single_release, 559 .read = seq_read, 560 .llseek = seq_lseek, 561 .write = stats_clear, 562 }; 563 564 static int dump_ep(int id, void *p, void *data) 565 { 566 struct c4iw_ep *ep = p; 567 struct c4iw_debugfs_data *epd = data; 568 int space; 569 int cc; 570 571 space = epd->bufsize - epd->pos - 1; 572 if (space == 0) 573 return 1; 574 575 if (ep->com.local_addr.ss_family == AF_INET) { 576 struct sockaddr_in *lsin; 577 struct sockaddr_in *rsin; 578 struct sockaddr_in *m_lsin; 579 struct sockaddr_in *m_rsin; 580 581 set_ep_sin_addrs(ep, &lsin, &rsin, &m_lsin, &m_rsin); 582 cc = snprintf(epd->buf + epd->pos, space, 583 "ep %p cm_id %p qp %p state %d flags 0x%lx " 584 "history 0x%lx hwtid %d atid %d " 585 "conn_na %u abort_na %u " 586 "%pI4:%d/%d <-> %pI4:%d/%d\n", 587 ep, ep->com.cm_id, ep->com.qp, 588 (int)ep->com.state, ep->com.flags, 589 ep->com.history, ep->hwtid, ep->atid, 590 ep->stats.connect_neg_adv, 591 ep->stats.abort_neg_adv, 592 &lsin->sin_addr, ntohs(lsin->sin_port), 593 ntohs(m_lsin->sin_port), 594 &rsin->sin_addr, ntohs(rsin->sin_port), 595 ntohs(m_rsin->sin_port)); 596 } else { 597 struct sockaddr_in6 *lsin6; 598 struct sockaddr_in6 *rsin6; 599 struct sockaddr_in6 *m_lsin6; 600 struct sockaddr_in6 *m_rsin6; 601 602 set_ep_sin6_addrs(ep, &lsin6, &rsin6, &m_lsin6, &m_rsin6); 603 cc = snprintf(epd->buf + epd->pos, space, 604 "ep %p cm_id %p qp %p state %d flags 0x%lx " 605 "history 0x%lx hwtid %d atid %d " 606 "conn_na %u abort_na %u " 607 "%pI6:%d/%d <-> %pI6:%d/%d\n", 608 ep, ep->com.cm_id, ep->com.qp, 609 (int)ep->com.state, ep->com.flags, 610 ep->com.history, ep->hwtid, ep->atid, 611 ep->stats.connect_neg_adv, 612 ep->stats.abort_neg_adv, 613 &lsin6->sin6_addr, ntohs(lsin6->sin6_port), 614 ntohs(m_lsin6->sin6_port), 615 &rsin6->sin6_addr, ntohs(rsin6->sin6_port), 616 ntohs(m_rsin6->sin6_port)); 617 } 618 if (cc < space) 619 epd->pos += cc; 620 return 0; 621 } 622 623 static int dump_listen_ep(int id, void *p, void *data) 624 { 625 struct c4iw_listen_ep *ep = p; 626 struct c4iw_debugfs_data *epd = data; 627 int space; 628 int cc; 629 630 space = epd->bufsize - epd->pos - 1; 631 if (space == 0) 632 return 1; 633 634 if (ep->com.local_addr.ss_family == AF_INET) { 635 struct sockaddr_in *lsin = (struct sockaddr_in *) 636 &ep->com.cm_id->local_addr; 637 struct sockaddr_in *m_lsin = (struct sockaddr_in *) 638 &ep->com.cm_id->m_local_addr; 639 640 cc = snprintf(epd->buf + epd->pos, space, 641 "ep %p cm_id %p state %d flags 0x%lx stid %d " 642 "backlog %d %pI4:%d/%d\n", 643 ep, ep->com.cm_id, (int)ep->com.state, 644 ep->com.flags, ep->stid, ep->backlog, 645 &lsin->sin_addr, ntohs(lsin->sin_port), 646 ntohs(m_lsin->sin_port)); 647 } else { 648 struct sockaddr_in6 *lsin6 = (struct sockaddr_in6 *) 649 &ep->com.cm_id->local_addr; 650 struct sockaddr_in6 *m_lsin6 = (struct sockaddr_in6 *) 651 &ep->com.cm_id->m_local_addr; 652 653 cc = snprintf(epd->buf + epd->pos, space, 654 "ep %p cm_id %p state %d flags 0x%lx stid %d " 655 "backlog %d %pI6:%d/%d\n", 656 ep, ep->com.cm_id, (int)ep->com.state, 657 ep->com.flags, ep->stid, ep->backlog, 658 &lsin6->sin6_addr, ntohs(lsin6->sin6_port), 659 ntohs(m_lsin6->sin6_port)); 660 } 661 if (cc < space) 662 epd->pos += cc; 663 return 0; 664 } 665 666 static int ep_release(struct inode *inode, struct file *file) 667 { 668 struct c4iw_debugfs_data *epd = file->private_data; 669 if (!epd) { 670 pr_info("%s null qpd?\n", __func__); 671 return 0; 672 } 673 vfree(epd->buf); 674 kfree(epd); 675 return 0; 676 } 677 678 static int ep_open(struct inode *inode, struct file *file) 679 { 680 struct c4iw_debugfs_data *epd; 681 int ret = 0; 682 int count = 1; 683 684 epd = kmalloc(sizeof(*epd), GFP_KERNEL); 685 if (!epd) { 686 ret = -ENOMEM; 687 goto out; 688 } 689 epd->devp = inode->i_private; 690 epd->pos = 0; 691 692 spin_lock_irq(&epd->devp->lock); 693 idr_for_each(&epd->devp->hwtid_idr, count_idrs, &count); 694 idr_for_each(&epd->devp->atid_idr, count_idrs, &count); 695 idr_for_each(&epd->devp->stid_idr, count_idrs, &count); 696 spin_unlock_irq(&epd->devp->lock); 697 698 epd->bufsize = count * 240; 699 epd->buf = vmalloc(epd->bufsize); 700 if (!epd->buf) { 701 ret = -ENOMEM; 702 goto err1; 703 } 704 705 spin_lock_irq(&epd->devp->lock); 706 idr_for_each(&epd->devp->hwtid_idr, dump_ep, epd); 707 idr_for_each(&epd->devp->atid_idr, dump_ep, epd); 708 idr_for_each(&epd->devp->stid_idr, dump_listen_ep, epd); 709 spin_unlock_irq(&epd->devp->lock); 710 711 file->private_data = epd; 712 goto out; 713 err1: 714 kfree(epd); 715 out: 716 return ret; 717 } 718 719 static const struct file_operations ep_debugfs_fops = { 720 .owner = THIS_MODULE, 721 .open = ep_open, 722 .release = ep_release, 723 .read = debugfs_read, 724 }; 725 726 static int setup_debugfs(struct c4iw_dev *devp) 727 { 728 if (!devp->debugfs_root) 729 return -1; 730 731 debugfs_create_file_size("qps", S_IWUSR, devp->debugfs_root, 732 (void *)devp, &qp_debugfs_fops, 4096); 733 734 debugfs_create_file_size("stags", S_IWUSR, devp->debugfs_root, 735 (void *)devp, &stag_debugfs_fops, 4096); 736 737 debugfs_create_file_size("stats", S_IWUSR, devp->debugfs_root, 738 (void *)devp, &stats_debugfs_fops, 4096); 739 740 debugfs_create_file_size("eps", S_IWUSR, devp->debugfs_root, 741 (void *)devp, &ep_debugfs_fops, 4096); 742 743 if (c4iw_wr_log) 744 debugfs_create_file_size("wr_log", S_IWUSR, devp->debugfs_root, 745 (void *)devp, &wr_log_debugfs_fops, 4096); 746 return 0; 747 } 748 749 void c4iw_release_dev_ucontext(struct c4iw_rdev *rdev, 750 struct c4iw_dev_ucontext *uctx) 751 { 752 struct list_head *pos, *nxt; 753 struct c4iw_qid_list *entry; 754 755 mutex_lock(&uctx->lock); 756 list_for_each_safe(pos, nxt, &uctx->qpids) { 757 entry = list_entry(pos, struct c4iw_qid_list, entry); 758 list_del_init(&entry->entry); 759 if (!(entry->qid & rdev->qpmask)) { 760 c4iw_put_resource(&rdev->resource.qid_table, 761 entry->qid); 762 mutex_lock(&rdev->stats.lock); 763 rdev->stats.qid.cur -= rdev->qpmask + 1; 764 mutex_unlock(&rdev->stats.lock); 765 } 766 kfree(entry); 767 } 768 769 list_for_each_safe(pos, nxt, &uctx->cqids) { 770 entry = list_entry(pos, struct c4iw_qid_list, entry); 771 list_del_init(&entry->entry); 772 kfree(entry); 773 } 774 mutex_unlock(&uctx->lock); 775 } 776 777 void c4iw_init_dev_ucontext(struct c4iw_rdev *rdev, 778 struct c4iw_dev_ucontext *uctx) 779 { 780 INIT_LIST_HEAD(&uctx->qpids); 781 INIT_LIST_HEAD(&uctx->cqids); 782 mutex_init(&uctx->lock); 783 } 784 785 /* Caller takes care of locking if needed */ 786 static int c4iw_rdev_open(struct c4iw_rdev *rdev) 787 { 788 int err; 789 790 c4iw_init_dev_ucontext(rdev, &rdev->uctx); 791 792 /* 793 * This implementation assumes udb_density == ucq_density! Eventually 794 * we might need to support this but for now fail the open. Also the 795 * cqid and qpid range must match for now. 796 */ 797 if (rdev->lldi.udb_density != rdev->lldi.ucq_density) { 798 pr_err("%s: unsupported udb/ucq densities %u/%u\n", 799 pci_name(rdev->lldi.pdev), rdev->lldi.udb_density, 800 rdev->lldi.ucq_density); 801 return -EINVAL; 802 } 803 if (rdev->lldi.vr->qp.start != rdev->lldi.vr->cq.start || 804 rdev->lldi.vr->qp.size != rdev->lldi.vr->cq.size) { 805 pr_err("%s: unsupported qp and cq id ranges qp start %u size %u cq start %u size %u\n", 806 pci_name(rdev->lldi.pdev), rdev->lldi.vr->qp.start, 807 rdev->lldi.vr->qp.size, rdev->lldi.vr->cq.size, 808 rdev->lldi.vr->cq.size); 809 return -EINVAL; 810 } 811 812 rdev->qpmask = rdev->lldi.udb_density - 1; 813 rdev->cqmask = rdev->lldi.ucq_density - 1; 814 pr_debug("%s dev %s stag start 0x%0x size 0x%0x num stags %d pbl start 0x%0x size 0x%0x rq start 0x%0x size 0x%0x qp qid start %u size %u cq qid start %u size %u\n", 815 __func__, pci_name(rdev->lldi.pdev), rdev->lldi.vr->stag.start, 816 rdev->lldi.vr->stag.size, c4iw_num_stags(rdev), 817 rdev->lldi.vr->pbl.start, 818 rdev->lldi.vr->pbl.size, rdev->lldi.vr->rq.start, 819 rdev->lldi.vr->rq.size, 820 rdev->lldi.vr->qp.start, 821 rdev->lldi.vr->qp.size, 822 rdev->lldi.vr->cq.start, 823 rdev->lldi.vr->cq.size); 824 pr_debug("udb %pR db_reg %p gts_reg %p qpmask 0x%x cqmask 0x%x\n", 825 &rdev->lldi.pdev->resource[2], 826 rdev->lldi.db_reg, rdev->lldi.gts_reg, 827 rdev->qpmask, rdev->cqmask); 828 829 if (c4iw_num_stags(rdev) == 0) 830 return -EINVAL; 831 832 rdev->stats.pd.total = T4_MAX_NUM_PD; 833 rdev->stats.stag.total = rdev->lldi.vr->stag.size; 834 rdev->stats.pbl.total = rdev->lldi.vr->pbl.size; 835 rdev->stats.rqt.total = rdev->lldi.vr->rq.size; 836 rdev->stats.ocqp.total = rdev->lldi.vr->ocq.size; 837 rdev->stats.qid.total = rdev->lldi.vr->qp.size; 838 839 err = c4iw_init_resource(rdev, c4iw_num_stags(rdev), T4_MAX_NUM_PD); 840 if (err) { 841 pr_err("error %d initializing resources\n", err); 842 return err; 843 } 844 err = c4iw_pblpool_create(rdev); 845 if (err) { 846 pr_err("error %d initializing pbl pool\n", err); 847 goto destroy_resource; 848 } 849 err = c4iw_rqtpool_create(rdev); 850 if (err) { 851 pr_err("error %d initializing rqt pool\n", err); 852 goto destroy_pblpool; 853 } 854 err = c4iw_ocqp_pool_create(rdev); 855 if (err) { 856 pr_err("error %d initializing ocqp pool\n", err); 857 goto destroy_rqtpool; 858 } 859 rdev->status_page = (struct t4_dev_status_page *) 860 __get_free_page(GFP_KERNEL); 861 if (!rdev->status_page) { 862 err = -ENOMEM; 863 goto destroy_ocqp_pool; 864 } 865 rdev->status_page->qp_start = rdev->lldi.vr->qp.start; 866 rdev->status_page->qp_size = rdev->lldi.vr->qp.size; 867 rdev->status_page->cq_start = rdev->lldi.vr->cq.start; 868 rdev->status_page->cq_size = rdev->lldi.vr->cq.size; 869 870 if (c4iw_wr_log) { 871 rdev->wr_log = kzalloc((1 << c4iw_wr_log_size_order) * 872 sizeof(*rdev->wr_log), GFP_KERNEL); 873 if (rdev->wr_log) { 874 rdev->wr_log_size = 1 << c4iw_wr_log_size_order; 875 atomic_set(&rdev->wr_log_idx, 0); 876 } 877 } 878 879 rdev->free_workq = create_singlethread_workqueue("iw_cxgb4_free"); 880 if (!rdev->free_workq) { 881 err = -ENOMEM; 882 goto err_free_status_page_and_wr_log; 883 } 884 885 rdev->status_page->db_off = 0; 886 887 return 0; 888 err_free_status_page_and_wr_log: 889 if (c4iw_wr_log && rdev->wr_log) 890 kfree(rdev->wr_log); 891 free_page((unsigned long)rdev->status_page); 892 destroy_ocqp_pool: 893 c4iw_ocqp_pool_destroy(rdev); 894 destroy_rqtpool: 895 c4iw_rqtpool_destroy(rdev); 896 destroy_pblpool: 897 c4iw_pblpool_destroy(rdev); 898 destroy_resource: 899 c4iw_destroy_resource(&rdev->resource); 900 return err; 901 } 902 903 static void c4iw_rdev_close(struct c4iw_rdev *rdev) 904 { 905 destroy_workqueue(rdev->free_workq); 906 kfree(rdev->wr_log); 907 c4iw_release_dev_ucontext(rdev, &rdev->uctx); 908 free_page((unsigned long)rdev->status_page); 909 c4iw_pblpool_destroy(rdev); 910 c4iw_rqtpool_destroy(rdev); 911 c4iw_ocqp_pool_destroy(rdev); 912 c4iw_destroy_resource(&rdev->resource); 913 } 914 915 static void c4iw_dealloc(struct uld_ctx *ctx) 916 { 917 c4iw_rdev_close(&ctx->dev->rdev); 918 WARN_ON_ONCE(!idr_is_empty(&ctx->dev->cqidr)); 919 idr_destroy(&ctx->dev->cqidr); 920 WARN_ON_ONCE(!idr_is_empty(&ctx->dev->qpidr)); 921 idr_destroy(&ctx->dev->qpidr); 922 WARN_ON_ONCE(!idr_is_empty(&ctx->dev->mmidr)); 923 idr_destroy(&ctx->dev->mmidr); 924 wait_event(ctx->dev->wait, idr_is_empty(&ctx->dev->hwtid_idr)); 925 idr_destroy(&ctx->dev->hwtid_idr); 926 idr_destroy(&ctx->dev->stid_idr); 927 idr_destroy(&ctx->dev->atid_idr); 928 if (ctx->dev->rdev.bar2_kva) 929 iounmap(ctx->dev->rdev.bar2_kva); 930 if (ctx->dev->rdev.oc_mw_kva) 931 iounmap(ctx->dev->rdev.oc_mw_kva); 932 ib_dealloc_device(&ctx->dev->ibdev); 933 ctx->dev = NULL; 934 } 935 936 static void c4iw_remove(struct uld_ctx *ctx) 937 { 938 pr_debug("%s c4iw_dev %p\n", __func__, ctx->dev); 939 c4iw_unregister_device(ctx->dev); 940 c4iw_dealloc(ctx); 941 } 942 943 static int rdma_supported(const struct cxgb4_lld_info *infop) 944 { 945 return infop->vr->stag.size > 0 && infop->vr->pbl.size > 0 && 946 infop->vr->rq.size > 0 && infop->vr->qp.size > 0 && 947 infop->vr->cq.size > 0; 948 } 949 950 static struct c4iw_dev *c4iw_alloc(const struct cxgb4_lld_info *infop) 951 { 952 struct c4iw_dev *devp; 953 int ret; 954 955 if (!rdma_supported(infop)) { 956 pr_info("%s: RDMA not supported on this device\n", 957 pci_name(infop->pdev)); 958 return ERR_PTR(-ENOSYS); 959 } 960 if (!ocqp_supported(infop)) 961 pr_info("%s: On-Chip Queues not supported on this device\n", 962 pci_name(infop->pdev)); 963 964 devp = (struct c4iw_dev *)ib_alloc_device(sizeof(*devp)); 965 if (!devp) { 966 pr_err("Cannot allocate ib device\n"); 967 return ERR_PTR(-ENOMEM); 968 } 969 devp->rdev.lldi = *infop; 970 971 /* init various hw-queue params based on lld info */ 972 pr_debug("%s: Ing. padding boundary is %d, egrsstatuspagesize = %d\n", 973 __func__, devp->rdev.lldi.sge_ingpadboundary, 974 devp->rdev.lldi.sge_egrstatuspagesize); 975 976 devp->rdev.hw_queue.t4_eq_status_entries = 977 devp->rdev.lldi.sge_egrstatuspagesize / 64; 978 devp->rdev.hw_queue.t4_max_eq_size = 65520; 979 devp->rdev.hw_queue.t4_max_iq_size = 65520; 980 devp->rdev.hw_queue.t4_max_rq_size = 8192 - 981 devp->rdev.hw_queue.t4_eq_status_entries - 1; 982 devp->rdev.hw_queue.t4_max_sq_size = 983 devp->rdev.hw_queue.t4_max_eq_size - 984 devp->rdev.hw_queue.t4_eq_status_entries - 1; 985 devp->rdev.hw_queue.t4_max_qp_depth = 986 devp->rdev.hw_queue.t4_max_rq_size; 987 devp->rdev.hw_queue.t4_max_cq_depth = 988 devp->rdev.hw_queue.t4_max_iq_size - 2; 989 devp->rdev.hw_queue.t4_stat_len = 990 devp->rdev.lldi.sge_egrstatuspagesize; 991 992 /* 993 * For T5/T6 devices, we map all of BAR2 with WC. 994 * For T4 devices with onchip qp mem, we map only that part 995 * of BAR2 with WC. 996 */ 997 devp->rdev.bar2_pa = pci_resource_start(devp->rdev.lldi.pdev, 2); 998 if (!is_t4(devp->rdev.lldi.adapter_type)) { 999 devp->rdev.bar2_kva = ioremap_wc(devp->rdev.bar2_pa, 1000 pci_resource_len(devp->rdev.lldi.pdev, 2)); 1001 if (!devp->rdev.bar2_kva) { 1002 pr_err("Unable to ioremap BAR2\n"); 1003 ib_dealloc_device(&devp->ibdev); 1004 return ERR_PTR(-EINVAL); 1005 } 1006 } else if (ocqp_supported(infop)) { 1007 devp->rdev.oc_mw_pa = 1008 pci_resource_start(devp->rdev.lldi.pdev, 2) + 1009 pci_resource_len(devp->rdev.lldi.pdev, 2) - 1010 roundup_pow_of_two(devp->rdev.lldi.vr->ocq.size); 1011 devp->rdev.oc_mw_kva = ioremap_wc(devp->rdev.oc_mw_pa, 1012 devp->rdev.lldi.vr->ocq.size); 1013 if (!devp->rdev.oc_mw_kva) { 1014 pr_err("Unable to ioremap onchip mem\n"); 1015 ib_dealloc_device(&devp->ibdev); 1016 return ERR_PTR(-EINVAL); 1017 } 1018 } 1019 1020 pr_debug("ocq memory: hw_start 0x%x size %u mw_pa 0x%lx mw_kva %p\n", 1021 devp->rdev.lldi.vr->ocq.start, devp->rdev.lldi.vr->ocq.size, 1022 devp->rdev.oc_mw_pa, devp->rdev.oc_mw_kva); 1023 1024 ret = c4iw_rdev_open(&devp->rdev); 1025 if (ret) { 1026 pr_err("Unable to open CXIO rdev err %d\n", ret); 1027 ib_dealloc_device(&devp->ibdev); 1028 return ERR_PTR(ret); 1029 } 1030 1031 idr_init(&devp->cqidr); 1032 idr_init(&devp->qpidr); 1033 idr_init(&devp->mmidr); 1034 idr_init(&devp->hwtid_idr); 1035 idr_init(&devp->stid_idr); 1036 idr_init(&devp->atid_idr); 1037 spin_lock_init(&devp->lock); 1038 mutex_init(&devp->rdev.stats.lock); 1039 mutex_init(&devp->db_mutex); 1040 INIT_LIST_HEAD(&devp->db_fc_list); 1041 init_waitqueue_head(&devp->wait); 1042 devp->avail_ird = devp->rdev.lldi.max_ird_adapter; 1043 1044 if (c4iw_debugfs_root) { 1045 devp->debugfs_root = debugfs_create_dir( 1046 pci_name(devp->rdev.lldi.pdev), 1047 c4iw_debugfs_root); 1048 setup_debugfs(devp); 1049 } 1050 1051 1052 return devp; 1053 } 1054 1055 static void *c4iw_uld_add(const struct cxgb4_lld_info *infop) 1056 { 1057 struct uld_ctx *ctx; 1058 static int vers_printed; 1059 int i; 1060 1061 if (!vers_printed++) 1062 pr_info("Chelsio T4/T5 RDMA Driver - version %s\n", 1063 DRV_VERSION); 1064 1065 ctx = kzalloc(sizeof *ctx, GFP_KERNEL); 1066 if (!ctx) { 1067 ctx = ERR_PTR(-ENOMEM); 1068 goto out; 1069 } 1070 ctx->lldi = *infop; 1071 1072 pr_debug("%s found device %s nchan %u nrxq %u ntxq %u nports %u\n", 1073 __func__, pci_name(ctx->lldi.pdev), 1074 ctx->lldi.nchan, ctx->lldi.nrxq, 1075 ctx->lldi.ntxq, ctx->lldi.nports); 1076 1077 mutex_lock(&dev_mutex); 1078 list_add_tail(&ctx->entry, &uld_ctx_list); 1079 mutex_unlock(&dev_mutex); 1080 1081 for (i = 0; i < ctx->lldi.nrxq; i++) 1082 pr_debug("rxqid[%u] %u\n", i, ctx->lldi.rxq_ids[i]); 1083 out: 1084 return ctx; 1085 } 1086 1087 static inline struct sk_buff *copy_gl_to_skb_pkt(const struct pkt_gl *gl, 1088 const __be64 *rsp, 1089 u32 pktshift) 1090 { 1091 struct sk_buff *skb; 1092 1093 /* 1094 * Allocate space for cpl_pass_accept_req which will be synthesized by 1095 * driver. Once the driver synthesizes the request the skb will go 1096 * through the regular cpl_pass_accept_req processing. 1097 * The math here assumes sizeof cpl_pass_accept_req >= sizeof 1098 * cpl_rx_pkt. 1099 */ 1100 skb = alloc_skb(gl->tot_len + sizeof(struct cpl_pass_accept_req) + 1101 sizeof(struct rss_header) - pktshift, GFP_ATOMIC); 1102 if (unlikely(!skb)) 1103 return NULL; 1104 1105 __skb_put(skb, gl->tot_len + sizeof(struct cpl_pass_accept_req) + 1106 sizeof(struct rss_header) - pktshift); 1107 1108 /* 1109 * This skb will contain: 1110 * rss_header from the rspq descriptor (1 flit) 1111 * cpl_rx_pkt struct from the rspq descriptor (2 flits) 1112 * space for the difference between the size of an 1113 * rx_pkt and pass_accept_req cpl (1 flit) 1114 * the packet data from the gl 1115 */ 1116 skb_copy_to_linear_data(skb, rsp, sizeof(struct cpl_pass_accept_req) + 1117 sizeof(struct rss_header)); 1118 skb_copy_to_linear_data_offset(skb, sizeof(struct rss_header) + 1119 sizeof(struct cpl_pass_accept_req), 1120 gl->va + pktshift, 1121 gl->tot_len - pktshift); 1122 return skb; 1123 } 1124 1125 static inline int recv_rx_pkt(struct c4iw_dev *dev, const struct pkt_gl *gl, 1126 const __be64 *rsp) 1127 { 1128 unsigned int opcode = *(u8 *)rsp; 1129 struct sk_buff *skb; 1130 1131 if (opcode != CPL_RX_PKT) 1132 goto out; 1133 1134 skb = copy_gl_to_skb_pkt(gl , rsp, dev->rdev.lldi.sge_pktshift); 1135 if (skb == NULL) 1136 goto out; 1137 1138 if (c4iw_handlers[opcode] == NULL) { 1139 pr_info("%s no handler opcode 0x%x...\n", __func__, opcode); 1140 kfree_skb(skb); 1141 goto out; 1142 } 1143 c4iw_handlers[opcode](dev, skb); 1144 return 1; 1145 out: 1146 return 0; 1147 } 1148 1149 static int c4iw_uld_rx_handler(void *handle, const __be64 *rsp, 1150 const struct pkt_gl *gl) 1151 { 1152 struct uld_ctx *ctx = handle; 1153 struct c4iw_dev *dev = ctx->dev; 1154 struct sk_buff *skb; 1155 u8 opcode; 1156 1157 if (gl == NULL) { 1158 /* omit RSS and rsp_ctrl at end of descriptor */ 1159 unsigned int len = 64 - sizeof(struct rsp_ctrl) - 8; 1160 1161 skb = alloc_skb(256, GFP_ATOMIC); 1162 if (!skb) 1163 goto nomem; 1164 __skb_put(skb, len); 1165 skb_copy_to_linear_data(skb, &rsp[1], len); 1166 } else if (gl == CXGB4_MSG_AN) { 1167 const struct rsp_ctrl *rc = (void *)rsp; 1168 1169 u32 qid = be32_to_cpu(rc->pldbuflen_qid); 1170 c4iw_ev_handler(dev, qid); 1171 return 0; 1172 } else if (unlikely(*(u8 *)rsp != *(u8 *)gl->va)) { 1173 if (recv_rx_pkt(dev, gl, rsp)) 1174 return 0; 1175 1176 pr_info("%s: unexpected FL contents at %p, RSS %#llx, FL %#llx, len %u\n", 1177 pci_name(ctx->lldi.pdev), gl->va, 1178 be64_to_cpu(*rsp), 1179 be64_to_cpu(*(__force __be64 *)gl->va), 1180 gl->tot_len); 1181 1182 return 0; 1183 } else { 1184 skb = cxgb4_pktgl_to_skb(gl, 128, 128); 1185 if (unlikely(!skb)) 1186 goto nomem; 1187 } 1188 1189 opcode = *(u8 *)rsp; 1190 if (c4iw_handlers[opcode]) { 1191 c4iw_handlers[opcode](dev, skb); 1192 } else { 1193 pr_info("%s no handler opcode 0x%x...\n", __func__, opcode); 1194 kfree_skb(skb); 1195 } 1196 1197 return 0; 1198 nomem: 1199 return -1; 1200 } 1201 1202 static int c4iw_uld_state_change(void *handle, enum cxgb4_state new_state) 1203 { 1204 struct uld_ctx *ctx = handle; 1205 1206 pr_debug("%s new_state %u\n", __func__, new_state); 1207 switch (new_state) { 1208 case CXGB4_STATE_UP: 1209 pr_info("%s: Up\n", pci_name(ctx->lldi.pdev)); 1210 if (!ctx->dev) { 1211 int ret; 1212 1213 ctx->dev = c4iw_alloc(&ctx->lldi); 1214 if (IS_ERR(ctx->dev)) { 1215 pr_err("%s: initialization failed: %ld\n", 1216 pci_name(ctx->lldi.pdev), 1217 PTR_ERR(ctx->dev)); 1218 ctx->dev = NULL; 1219 break; 1220 } 1221 ret = c4iw_register_device(ctx->dev); 1222 if (ret) { 1223 pr_err("%s: RDMA registration failed: %d\n", 1224 pci_name(ctx->lldi.pdev), ret); 1225 c4iw_dealloc(ctx); 1226 } 1227 } 1228 break; 1229 case CXGB4_STATE_DOWN: 1230 pr_info("%s: Down\n", pci_name(ctx->lldi.pdev)); 1231 if (ctx->dev) 1232 c4iw_remove(ctx); 1233 break; 1234 case CXGB4_STATE_START_RECOVERY: 1235 pr_info("%s: Fatal Error\n", pci_name(ctx->lldi.pdev)); 1236 if (ctx->dev) { 1237 struct ib_event event; 1238 1239 ctx->dev->rdev.flags |= T4_FATAL_ERROR; 1240 memset(&event, 0, sizeof event); 1241 event.event = IB_EVENT_DEVICE_FATAL; 1242 event.device = &ctx->dev->ibdev; 1243 ib_dispatch_event(&event); 1244 c4iw_remove(ctx); 1245 } 1246 break; 1247 case CXGB4_STATE_DETACH: 1248 pr_info("%s: Detach\n", pci_name(ctx->lldi.pdev)); 1249 if (ctx->dev) 1250 c4iw_remove(ctx); 1251 break; 1252 } 1253 return 0; 1254 } 1255 1256 static int disable_qp_db(int id, void *p, void *data) 1257 { 1258 struct c4iw_qp *qp = p; 1259 1260 t4_disable_wq_db(&qp->wq); 1261 return 0; 1262 } 1263 1264 static void stop_queues(struct uld_ctx *ctx) 1265 { 1266 unsigned long flags; 1267 1268 spin_lock_irqsave(&ctx->dev->lock, flags); 1269 ctx->dev->rdev.stats.db_state_transitions++; 1270 ctx->dev->db_state = STOPPED; 1271 if (ctx->dev->rdev.flags & T4_STATUS_PAGE_DISABLED) 1272 idr_for_each(&ctx->dev->qpidr, disable_qp_db, NULL); 1273 else 1274 ctx->dev->rdev.status_page->db_off = 1; 1275 spin_unlock_irqrestore(&ctx->dev->lock, flags); 1276 } 1277 1278 static int enable_qp_db(int id, void *p, void *data) 1279 { 1280 struct c4iw_qp *qp = p; 1281 1282 t4_enable_wq_db(&qp->wq); 1283 return 0; 1284 } 1285 1286 static void resume_rc_qp(struct c4iw_qp *qp) 1287 { 1288 spin_lock(&qp->lock); 1289 t4_ring_sq_db(&qp->wq, qp->wq.sq.wq_pidx_inc, NULL); 1290 qp->wq.sq.wq_pidx_inc = 0; 1291 t4_ring_rq_db(&qp->wq, qp->wq.rq.wq_pidx_inc, NULL); 1292 qp->wq.rq.wq_pidx_inc = 0; 1293 spin_unlock(&qp->lock); 1294 } 1295 1296 static void resume_a_chunk(struct uld_ctx *ctx) 1297 { 1298 int i; 1299 struct c4iw_qp *qp; 1300 1301 for (i = 0; i < DB_FC_RESUME_SIZE; i++) { 1302 qp = list_first_entry(&ctx->dev->db_fc_list, struct c4iw_qp, 1303 db_fc_entry); 1304 list_del_init(&qp->db_fc_entry); 1305 resume_rc_qp(qp); 1306 if (list_empty(&ctx->dev->db_fc_list)) 1307 break; 1308 } 1309 } 1310 1311 static void resume_queues(struct uld_ctx *ctx) 1312 { 1313 spin_lock_irq(&ctx->dev->lock); 1314 if (ctx->dev->db_state != STOPPED) 1315 goto out; 1316 ctx->dev->db_state = FLOW_CONTROL; 1317 while (1) { 1318 if (list_empty(&ctx->dev->db_fc_list)) { 1319 WARN_ON(ctx->dev->db_state != FLOW_CONTROL); 1320 ctx->dev->db_state = NORMAL; 1321 ctx->dev->rdev.stats.db_state_transitions++; 1322 if (ctx->dev->rdev.flags & T4_STATUS_PAGE_DISABLED) { 1323 idr_for_each(&ctx->dev->qpidr, enable_qp_db, 1324 NULL); 1325 } else { 1326 ctx->dev->rdev.status_page->db_off = 0; 1327 } 1328 break; 1329 } else { 1330 if (cxgb4_dbfifo_count(ctx->dev->rdev.lldi.ports[0], 1) 1331 < (ctx->dev->rdev.lldi.dbfifo_int_thresh << 1332 DB_FC_DRAIN_THRESH)) { 1333 resume_a_chunk(ctx); 1334 } 1335 if (!list_empty(&ctx->dev->db_fc_list)) { 1336 spin_unlock_irq(&ctx->dev->lock); 1337 if (DB_FC_RESUME_DELAY) { 1338 set_current_state(TASK_UNINTERRUPTIBLE); 1339 schedule_timeout(DB_FC_RESUME_DELAY); 1340 } 1341 spin_lock_irq(&ctx->dev->lock); 1342 if (ctx->dev->db_state != FLOW_CONTROL) 1343 break; 1344 } 1345 } 1346 } 1347 out: 1348 if (ctx->dev->db_state != NORMAL) 1349 ctx->dev->rdev.stats.db_fc_interruptions++; 1350 spin_unlock_irq(&ctx->dev->lock); 1351 } 1352 1353 struct qp_list { 1354 unsigned idx; 1355 struct c4iw_qp **qps; 1356 }; 1357 1358 static int add_and_ref_qp(int id, void *p, void *data) 1359 { 1360 struct qp_list *qp_listp = data; 1361 struct c4iw_qp *qp = p; 1362 1363 c4iw_qp_add_ref(&qp->ibqp); 1364 qp_listp->qps[qp_listp->idx++] = qp; 1365 return 0; 1366 } 1367 1368 static int count_qps(int id, void *p, void *data) 1369 { 1370 unsigned *countp = data; 1371 (*countp)++; 1372 return 0; 1373 } 1374 1375 static void deref_qps(struct qp_list *qp_list) 1376 { 1377 int idx; 1378 1379 for (idx = 0; idx < qp_list->idx; idx++) 1380 c4iw_qp_rem_ref(&qp_list->qps[idx]->ibqp); 1381 } 1382 1383 static void recover_lost_dbs(struct uld_ctx *ctx, struct qp_list *qp_list) 1384 { 1385 int idx; 1386 int ret; 1387 1388 for (idx = 0; idx < qp_list->idx; idx++) { 1389 struct c4iw_qp *qp = qp_list->qps[idx]; 1390 1391 spin_lock_irq(&qp->rhp->lock); 1392 spin_lock(&qp->lock); 1393 ret = cxgb4_sync_txq_pidx(qp->rhp->rdev.lldi.ports[0], 1394 qp->wq.sq.qid, 1395 t4_sq_host_wq_pidx(&qp->wq), 1396 t4_sq_wq_size(&qp->wq)); 1397 if (ret) { 1398 pr_err("%s: Fatal error - DB overflow recovery failed - error syncing SQ qid %u\n", 1399 pci_name(ctx->lldi.pdev), qp->wq.sq.qid); 1400 spin_unlock(&qp->lock); 1401 spin_unlock_irq(&qp->rhp->lock); 1402 return; 1403 } 1404 qp->wq.sq.wq_pidx_inc = 0; 1405 1406 ret = cxgb4_sync_txq_pidx(qp->rhp->rdev.lldi.ports[0], 1407 qp->wq.rq.qid, 1408 t4_rq_host_wq_pidx(&qp->wq), 1409 t4_rq_wq_size(&qp->wq)); 1410 1411 if (ret) { 1412 pr_err("%s: Fatal error - DB overflow recovery failed - error syncing RQ qid %u\n", 1413 pci_name(ctx->lldi.pdev), qp->wq.rq.qid); 1414 spin_unlock(&qp->lock); 1415 spin_unlock_irq(&qp->rhp->lock); 1416 return; 1417 } 1418 qp->wq.rq.wq_pidx_inc = 0; 1419 spin_unlock(&qp->lock); 1420 spin_unlock_irq(&qp->rhp->lock); 1421 1422 /* Wait for the dbfifo to drain */ 1423 while (cxgb4_dbfifo_count(qp->rhp->rdev.lldi.ports[0], 1) > 0) { 1424 set_current_state(TASK_UNINTERRUPTIBLE); 1425 schedule_timeout(usecs_to_jiffies(10)); 1426 } 1427 } 1428 } 1429 1430 static void recover_queues(struct uld_ctx *ctx) 1431 { 1432 int count = 0; 1433 struct qp_list qp_list; 1434 int ret; 1435 1436 /* slow everybody down */ 1437 set_current_state(TASK_UNINTERRUPTIBLE); 1438 schedule_timeout(usecs_to_jiffies(1000)); 1439 1440 /* flush the SGE contexts */ 1441 ret = cxgb4_flush_eq_cache(ctx->dev->rdev.lldi.ports[0]); 1442 if (ret) { 1443 pr_err("%s: Fatal error - DB overflow recovery failed\n", 1444 pci_name(ctx->lldi.pdev)); 1445 return; 1446 } 1447 1448 /* Count active queues so we can build a list of queues to recover */ 1449 spin_lock_irq(&ctx->dev->lock); 1450 WARN_ON(ctx->dev->db_state != STOPPED); 1451 ctx->dev->db_state = RECOVERY; 1452 idr_for_each(&ctx->dev->qpidr, count_qps, &count); 1453 1454 qp_list.qps = kzalloc(count * sizeof *qp_list.qps, GFP_ATOMIC); 1455 if (!qp_list.qps) { 1456 spin_unlock_irq(&ctx->dev->lock); 1457 return; 1458 } 1459 qp_list.idx = 0; 1460 1461 /* add and ref each qp so it doesn't get freed */ 1462 idr_for_each(&ctx->dev->qpidr, add_and_ref_qp, &qp_list); 1463 1464 spin_unlock_irq(&ctx->dev->lock); 1465 1466 /* now traverse the list in a safe context to recover the db state*/ 1467 recover_lost_dbs(ctx, &qp_list); 1468 1469 /* we're almost done! deref the qps and clean up */ 1470 deref_qps(&qp_list); 1471 kfree(qp_list.qps); 1472 1473 spin_lock_irq(&ctx->dev->lock); 1474 WARN_ON(ctx->dev->db_state != RECOVERY); 1475 ctx->dev->db_state = STOPPED; 1476 spin_unlock_irq(&ctx->dev->lock); 1477 } 1478 1479 static int c4iw_uld_control(void *handle, enum cxgb4_control control, ...) 1480 { 1481 struct uld_ctx *ctx = handle; 1482 1483 switch (control) { 1484 case CXGB4_CONTROL_DB_FULL: 1485 stop_queues(ctx); 1486 ctx->dev->rdev.stats.db_full++; 1487 break; 1488 case CXGB4_CONTROL_DB_EMPTY: 1489 resume_queues(ctx); 1490 mutex_lock(&ctx->dev->rdev.stats.lock); 1491 ctx->dev->rdev.stats.db_empty++; 1492 mutex_unlock(&ctx->dev->rdev.stats.lock); 1493 break; 1494 case CXGB4_CONTROL_DB_DROP: 1495 recover_queues(ctx); 1496 mutex_lock(&ctx->dev->rdev.stats.lock); 1497 ctx->dev->rdev.stats.db_drop++; 1498 mutex_unlock(&ctx->dev->rdev.stats.lock); 1499 break; 1500 default: 1501 pr_warn("%s: unknown control cmd %u\n", 1502 pci_name(ctx->lldi.pdev), control); 1503 break; 1504 } 1505 return 0; 1506 } 1507 1508 static struct cxgb4_uld_info c4iw_uld_info = { 1509 .name = DRV_NAME, 1510 .nrxq = MAX_ULD_QSETS, 1511 .ntxq = MAX_ULD_QSETS, 1512 .rxq_size = 511, 1513 .ciq = true, 1514 .lro = false, 1515 .add = c4iw_uld_add, 1516 .rx_handler = c4iw_uld_rx_handler, 1517 .state_change = c4iw_uld_state_change, 1518 .control = c4iw_uld_control, 1519 }; 1520 1521 static int __init c4iw_init_module(void) 1522 { 1523 int err; 1524 1525 err = c4iw_cm_init(); 1526 if (err) 1527 return err; 1528 1529 c4iw_debugfs_root = debugfs_create_dir(DRV_NAME, NULL); 1530 if (!c4iw_debugfs_root) 1531 pr_warn("could not create debugfs entry, continuing\n"); 1532 1533 cxgb4_register_uld(CXGB4_ULD_RDMA, &c4iw_uld_info); 1534 1535 return 0; 1536 } 1537 1538 static void __exit c4iw_exit_module(void) 1539 { 1540 struct uld_ctx *ctx, *tmp; 1541 1542 mutex_lock(&dev_mutex); 1543 list_for_each_entry_safe(ctx, tmp, &uld_ctx_list, entry) { 1544 if (ctx->dev) 1545 c4iw_remove(ctx); 1546 kfree(ctx); 1547 } 1548 mutex_unlock(&dev_mutex); 1549 cxgb4_unregister_uld(CXGB4_ULD_RDMA); 1550 c4iw_cm_term(); 1551 debugfs_remove_recursive(c4iw_debugfs_root); 1552 } 1553 1554 module_init(c4iw_init_module); 1555 module_exit(c4iw_exit_module); 1556