1 /* 2 * Copyright (c) 2009-2010 Chelsio, Inc. All rights reserved. 3 * 4 * This software is available to you under a choice of one of two 5 * licenses. You may choose to be licensed under the terms of the GNU 6 * General Public License (GPL) Version 2, available from the file 7 * COPYING in the main directory of this source tree, or the 8 * OpenIB.org BSD license below: 9 * 10 * Redistribution and use in source and binary forms, with or 11 * without modification, are permitted provided that the following 12 * conditions are met: 13 * 14 * - Redistributions of source code must retain the above 15 * copyright notice, this list of conditions and the following 16 * disclaimer. 17 * 18 * - Redistributions in binary form must reproduce the above 19 * copyright notice, this list of conditions and the following 20 * disclaimer in the documentation and/or other materials 21 * provided with the distribution. 22 * 23 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, 24 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF 25 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND 26 * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS 27 * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN 28 * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN 29 * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE 30 * SOFTWARE. 31 */ 32 33 #include "iw_cxgb4.h" 34 35 static int destroy_cq(struct c4iw_rdev *rdev, struct t4_cq *cq, 36 struct c4iw_dev_ucontext *uctx) 37 { 38 struct fw_ri_res_wr *res_wr; 39 struct fw_ri_res *res; 40 int wr_len; 41 struct c4iw_wr_wait wr_wait; 42 struct sk_buff *skb; 43 int ret; 44 45 wr_len = sizeof *res_wr + sizeof *res; 46 skb = alloc_skb(wr_len, GFP_KERNEL); 47 if (!skb) 48 return -ENOMEM; 49 set_wr_txq(skb, CPL_PRIORITY_CONTROL, 0); 50 51 res_wr = (struct fw_ri_res_wr *)__skb_put(skb, wr_len); 52 memset(res_wr, 0, wr_len); 53 res_wr->op_nres = cpu_to_be32( 54 FW_WR_OP(FW_RI_RES_WR) | 55 V_FW_RI_RES_WR_NRES(1) | 56 FW_WR_COMPL(1)); 57 res_wr->len16_pkd = cpu_to_be32(DIV_ROUND_UP(wr_len, 16)); 58 res_wr->cookie = (unsigned long) &wr_wait; 59 res = res_wr->res; 60 res->u.cq.restype = FW_RI_RES_TYPE_CQ; 61 res->u.cq.op = FW_RI_RES_OP_RESET; 62 res->u.cq.iqid = cpu_to_be32(cq->cqid); 63 64 c4iw_init_wr_wait(&wr_wait); 65 ret = c4iw_ofld_send(rdev, skb); 66 if (!ret) { 67 ret = c4iw_wait_for_reply(rdev, &wr_wait, 0, 0, __func__); 68 } 69 70 kfree(cq->sw_queue); 71 dma_free_coherent(&(rdev->lldi.pdev->dev), 72 cq->memsize, cq->queue, 73 dma_unmap_addr(cq, mapping)); 74 c4iw_put_cqid(rdev, cq->cqid, uctx); 75 return ret; 76 } 77 78 static int create_cq(struct c4iw_rdev *rdev, struct t4_cq *cq, 79 struct c4iw_dev_ucontext *uctx) 80 { 81 struct fw_ri_res_wr *res_wr; 82 struct fw_ri_res *res; 83 int wr_len; 84 int user = (uctx != &rdev->uctx); 85 struct c4iw_wr_wait wr_wait; 86 int ret; 87 struct sk_buff *skb; 88 89 cq->cqid = c4iw_get_cqid(rdev, uctx); 90 if (!cq->cqid) { 91 ret = -ENOMEM; 92 goto err1; 93 } 94 95 if (!user) { 96 cq->sw_queue = kzalloc(cq->memsize, GFP_KERNEL); 97 if (!cq->sw_queue) { 98 ret = -ENOMEM; 99 goto err2; 100 } 101 } 102 cq->queue = dma_alloc_coherent(&rdev->lldi.pdev->dev, cq->memsize, 103 &cq->dma_addr, GFP_KERNEL); 104 if (!cq->queue) { 105 ret = -ENOMEM; 106 goto err3; 107 } 108 dma_unmap_addr_set(cq, mapping, cq->dma_addr); 109 memset(cq->queue, 0, cq->memsize); 110 111 /* build fw_ri_res_wr */ 112 wr_len = sizeof *res_wr + sizeof *res; 113 114 skb = alloc_skb(wr_len, GFP_KERNEL); 115 if (!skb) { 116 ret = -ENOMEM; 117 goto err4; 118 } 119 set_wr_txq(skb, CPL_PRIORITY_CONTROL, 0); 120 121 res_wr = (struct fw_ri_res_wr *)__skb_put(skb, wr_len); 122 memset(res_wr, 0, wr_len); 123 res_wr->op_nres = cpu_to_be32( 124 FW_WR_OP(FW_RI_RES_WR) | 125 V_FW_RI_RES_WR_NRES(1) | 126 FW_WR_COMPL(1)); 127 res_wr->len16_pkd = cpu_to_be32(DIV_ROUND_UP(wr_len, 16)); 128 res_wr->cookie = (unsigned long) &wr_wait; 129 res = res_wr->res; 130 res->u.cq.restype = FW_RI_RES_TYPE_CQ; 131 res->u.cq.op = FW_RI_RES_OP_WRITE; 132 res->u.cq.iqid = cpu_to_be32(cq->cqid); 133 res->u.cq.iqandst_to_iqandstindex = cpu_to_be32( 134 V_FW_RI_RES_WR_IQANUS(0) | 135 V_FW_RI_RES_WR_IQANUD(1) | 136 F_FW_RI_RES_WR_IQANDST | 137 V_FW_RI_RES_WR_IQANDSTINDEX(*rdev->lldi.rxq_ids)); 138 res->u.cq.iqdroprss_to_iqesize = cpu_to_be16( 139 F_FW_RI_RES_WR_IQDROPRSS | 140 V_FW_RI_RES_WR_IQPCIECH(2) | 141 V_FW_RI_RES_WR_IQINTCNTTHRESH(0) | 142 F_FW_RI_RES_WR_IQO | 143 V_FW_RI_RES_WR_IQESIZE(1)); 144 res->u.cq.iqsize = cpu_to_be16(cq->size); 145 res->u.cq.iqaddr = cpu_to_be64(cq->dma_addr); 146 147 c4iw_init_wr_wait(&wr_wait); 148 149 ret = c4iw_ofld_send(rdev, skb); 150 if (ret) 151 goto err4; 152 PDBG("%s wait_event wr_wait %p\n", __func__, &wr_wait); 153 ret = c4iw_wait_for_reply(rdev, &wr_wait, 0, 0, __func__); 154 if (ret) 155 goto err4; 156 157 cq->gen = 1; 158 cq->gts = rdev->lldi.gts_reg; 159 cq->rdev = rdev; 160 if (user) { 161 cq->ugts = (u64)pci_resource_start(rdev->lldi.pdev, 2) + 162 (cq->cqid << rdev->cqshift); 163 cq->ugts &= PAGE_MASK; 164 } 165 return 0; 166 err4: 167 dma_free_coherent(&rdev->lldi.pdev->dev, cq->memsize, cq->queue, 168 dma_unmap_addr(cq, mapping)); 169 err3: 170 kfree(cq->sw_queue); 171 err2: 172 c4iw_put_cqid(rdev, cq->cqid, uctx); 173 err1: 174 return ret; 175 } 176 177 static void insert_recv_cqe(struct t4_wq *wq, struct t4_cq *cq) 178 { 179 struct t4_cqe cqe; 180 181 PDBG("%s wq %p cq %p sw_cidx %u sw_pidx %u\n", __func__, 182 wq, cq, cq->sw_cidx, cq->sw_pidx); 183 memset(&cqe, 0, sizeof(cqe)); 184 cqe.header = cpu_to_be32(V_CQE_STATUS(T4_ERR_SWFLUSH) | 185 V_CQE_OPCODE(FW_RI_SEND) | 186 V_CQE_TYPE(0) | 187 V_CQE_SWCQE(1) | 188 V_CQE_QPID(wq->sq.qid)); 189 cqe.bits_type_ts = cpu_to_be64(V_CQE_GENBIT((u64)cq->gen)); 190 cq->sw_queue[cq->sw_pidx] = cqe; 191 t4_swcq_produce(cq); 192 } 193 194 int c4iw_flush_rq(struct t4_wq *wq, struct t4_cq *cq, int count) 195 { 196 int flushed = 0; 197 int in_use = wq->rq.in_use - count; 198 199 BUG_ON(in_use < 0); 200 PDBG("%s wq %p cq %p rq.in_use %u skip count %u\n", __func__, 201 wq, cq, wq->rq.in_use, count); 202 while (in_use--) { 203 insert_recv_cqe(wq, cq); 204 flushed++; 205 } 206 return flushed; 207 } 208 209 static void insert_sq_cqe(struct t4_wq *wq, struct t4_cq *cq, 210 struct t4_swsqe *swcqe) 211 { 212 struct t4_cqe cqe; 213 214 PDBG("%s wq %p cq %p sw_cidx %u sw_pidx %u\n", __func__, 215 wq, cq, cq->sw_cidx, cq->sw_pidx); 216 memset(&cqe, 0, sizeof(cqe)); 217 cqe.header = cpu_to_be32(V_CQE_STATUS(T4_ERR_SWFLUSH) | 218 V_CQE_OPCODE(swcqe->opcode) | 219 V_CQE_TYPE(1) | 220 V_CQE_SWCQE(1) | 221 V_CQE_QPID(wq->sq.qid)); 222 CQE_WRID_SQ_IDX(&cqe) = swcqe->idx; 223 cqe.bits_type_ts = cpu_to_be64(V_CQE_GENBIT((u64)cq->gen)); 224 cq->sw_queue[cq->sw_pidx] = cqe; 225 t4_swcq_produce(cq); 226 } 227 228 static void advance_oldest_read(struct t4_wq *wq); 229 230 int c4iw_flush_sq(struct c4iw_qp *qhp) 231 { 232 int flushed = 0; 233 struct t4_wq *wq = &qhp->wq; 234 struct c4iw_cq *chp = to_c4iw_cq(qhp->ibqp.send_cq); 235 struct t4_cq *cq = &chp->cq; 236 int idx; 237 struct t4_swsqe *swsqe; 238 int error = (qhp->attr.state != C4IW_QP_STATE_CLOSING && 239 qhp->attr.state != C4IW_QP_STATE_IDLE); 240 241 if (wq->sq.flush_cidx == -1) 242 wq->sq.flush_cidx = wq->sq.cidx; 243 idx = wq->sq.flush_cidx; 244 BUG_ON(idx >= wq->sq.size); 245 while (idx != wq->sq.pidx) { 246 if (error) { 247 swsqe = &wq->sq.sw_sq[idx]; 248 BUG_ON(swsqe->flushed); 249 swsqe->flushed = 1; 250 insert_sq_cqe(wq, cq, swsqe); 251 if (wq->sq.oldest_read == swsqe) { 252 BUG_ON(swsqe->opcode != FW_RI_READ_REQ); 253 advance_oldest_read(wq); 254 } 255 flushed++; 256 } else { 257 t4_sq_consume(wq); 258 } 259 if (++idx == wq->sq.size) 260 idx = 0; 261 } 262 wq->sq.flush_cidx += flushed; 263 if (wq->sq.flush_cidx >= wq->sq.size) 264 wq->sq.flush_cidx -= wq->sq.size; 265 return flushed; 266 } 267 268 static void flush_completed_wrs(struct t4_wq *wq, struct t4_cq *cq) 269 { 270 struct t4_swsqe *swsqe; 271 int cidx; 272 273 if (wq->sq.flush_cidx == -1) 274 wq->sq.flush_cidx = wq->sq.cidx; 275 cidx = wq->sq.flush_cidx; 276 BUG_ON(cidx > wq->sq.size); 277 278 while (cidx != wq->sq.pidx) { 279 swsqe = &wq->sq.sw_sq[cidx]; 280 if (!swsqe->signaled) { 281 if (++cidx == wq->sq.size) 282 cidx = 0; 283 } else if (swsqe->complete) { 284 285 BUG_ON(swsqe->flushed); 286 287 /* 288 * Insert this completed cqe into the swcq. 289 */ 290 PDBG("%s moving cqe into swcq sq idx %u cq idx %u\n", 291 __func__, cidx, cq->sw_pidx); 292 swsqe->cqe.header |= htonl(V_CQE_SWCQE(1)); 293 cq->sw_queue[cq->sw_pidx] = swsqe->cqe; 294 t4_swcq_produce(cq); 295 swsqe->flushed = 1; 296 if (++cidx == wq->sq.size) 297 cidx = 0; 298 wq->sq.flush_cidx = cidx; 299 } else 300 break; 301 } 302 } 303 304 static void create_read_req_cqe(struct t4_wq *wq, struct t4_cqe *hw_cqe, 305 struct t4_cqe *read_cqe) 306 { 307 read_cqe->u.scqe.cidx = wq->sq.oldest_read->idx; 308 read_cqe->len = htonl(wq->sq.oldest_read->read_len); 309 read_cqe->header = htonl(V_CQE_QPID(CQE_QPID(hw_cqe)) | 310 V_CQE_SWCQE(SW_CQE(hw_cqe)) | 311 V_CQE_OPCODE(FW_RI_READ_REQ) | 312 V_CQE_TYPE(1)); 313 read_cqe->bits_type_ts = hw_cqe->bits_type_ts; 314 } 315 316 static void advance_oldest_read(struct t4_wq *wq) 317 { 318 319 u32 rptr = wq->sq.oldest_read - wq->sq.sw_sq + 1; 320 321 if (rptr == wq->sq.size) 322 rptr = 0; 323 while (rptr != wq->sq.pidx) { 324 wq->sq.oldest_read = &wq->sq.sw_sq[rptr]; 325 326 if (wq->sq.oldest_read->opcode == FW_RI_READ_REQ) 327 return; 328 if (++rptr == wq->sq.size) 329 rptr = 0; 330 } 331 wq->sq.oldest_read = NULL; 332 } 333 334 /* 335 * Move all CQEs from the HWCQ into the SWCQ. 336 * Deal with out-of-order and/or completions that complete 337 * prior unsignalled WRs. 338 */ 339 void c4iw_flush_hw_cq(struct c4iw_cq *chp) 340 { 341 struct t4_cqe *hw_cqe, *swcqe, read_cqe; 342 struct c4iw_qp *qhp; 343 struct t4_swsqe *swsqe; 344 int ret; 345 346 PDBG("%s cqid 0x%x\n", __func__, chp->cq.cqid); 347 ret = t4_next_hw_cqe(&chp->cq, &hw_cqe); 348 349 /* 350 * This logic is similar to poll_cq(), but not quite the same 351 * unfortunately. Need to move pertinent HW CQEs to the SW CQ but 352 * also do any translation magic that poll_cq() normally does. 353 */ 354 while (!ret) { 355 qhp = get_qhp(chp->rhp, CQE_QPID(hw_cqe)); 356 357 /* 358 * drop CQEs with no associated QP 359 */ 360 if (qhp == NULL) 361 goto next_cqe; 362 363 if (CQE_OPCODE(hw_cqe) == FW_RI_TERMINATE) 364 goto next_cqe; 365 366 if (CQE_OPCODE(hw_cqe) == FW_RI_READ_RESP) { 367 368 /* 369 * drop peer2peer RTR reads. 370 */ 371 if (CQE_WRID_STAG(hw_cqe) == 1) 372 goto next_cqe; 373 374 /* 375 * Eat completions for unsignaled read WRs. 376 */ 377 if (!qhp->wq.sq.oldest_read->signaled) { 378 advance_oldest_read(&qhp->wq); 379 goto next_cqe; 380 } 381 382 /* 383 * Don't write to the HWCQ, create a new read req CQE 384 * in local memory and move it into the swcq. 385 */ 386 create_read_req_cqe(&qhp->wq, hw_cqe, &read_cqe); 387 hw_cqe = &read_cqe; 388 advance_oldest_read(&qhp->wq); 389 } 390 391 /* if its a SQ completion, then do the magic to move all the 392 * unsignaled and now in-order completions into the swcq. 393 */ 394 if (SQ_TYPE(hw_cqe)) { 395 swsqe = &qhp->wq.sq.sw_sq[CQE_WRID_SQ_IDX(hw_cqe)]; 396 swsqe->cqe = *hw_cqe; 397 swsqe->complete = 1; 398 flush_completed_wrs(&qhp->wq, &chp->cq); 399 } else { 400 swcqe = &chp->cq.sw_queue[chp->cq.sw_pidx]; 401 *swcqe = *hw_cqe; 402 swcqe->header |= cpu_to_be32(V_CQE_SWCQE(1)); 403 t4_swcq_produce(&chp->cq); 404 } 405 next_cqe: 406 t4_hwcq_consume(&chp->cq); 407 ret = t4_next_hw_cqe(&chp->cq, &hw_cqe); 408 } 409 } 410 411 static int cqe_completes_wr(struct t4_cqe *cqe, struct t4_wq *wq) 412 { 413 if (CQE_OPCODE(cqe) == FW_RI_TERMINATE) 414 return 0; 415 416 if ((CQE_OPCODE(cqe) == FW_RI_RDMA_WRITE) && RQ_TYPE(cqe)) 417 return 0; 418 419 if ((CQE_OPCODE(cqe) == FW_RI_READ_RESP) && SQ_TYPE(cqe)) 420 return 0; 421 422 if (CQE_SEND_OPCODE(cqe) && RQ_TYPE(cqe) && t4_rq_empty(wq)) 423 return 0; 424 return 1; 425 } 426 427 void c4iw_count_rcqes(struct t4_cq *cq, struct t4_wq *wq, int *count) 428 { 429 struct t4_cqe *cqe; 430 u32 ptr; 431 432 *count = 0; 433 PDBG("%s count zero %d\n", __func__, *count); 434 ptr = cq->sw_cidx; 435 while (ptr != cq->sw_pidx) { 436 cqe = &cq->sw_queue[ptr]; 437 if (RQ_TYPE(cqe) && (CQE_OPCODE(cqe) != FW_RI_READ_RESP) && 438 (CQE_QPID(cqe) == wq->sq.qid) && cqe_completes_wr(cqe, wq)) 439 (*count)++; 440 if (++ptr == cq->size) 441 ptr = 0; 442 } 443 PDBG("%s cq %p count %d\n", __func__, cq, *count); 444 } 445 446 /* 447 * poll_cq 448 * 449 * Caller must: 450 * check the validity of the first CQE, 451 * supply the wq assicated with the qpid. 452 * 453 * credit: cq credit to return to sge. 454 * cqe_flushed: 1 iff the CQE is flushed. 455 * cqe: copy of the polled CQE. 456 * 457 * return value: 458 * 0 CQE returned ok. 459 * -EAGAIN CQE skipped, try again. 460 * -EOVERFLOW CQ overflow detected. 461 */ 462 static int poll_cq(struct t4_wq *wq, struct t4_cq *cq, struct t4_cqe *cqe, 463 u8 *cqe_flushed, u64 *cookie, u32 *credit) 464 { 465 int ret = 0; 466 struct t4_cqe *hw_cqe, read_cqe; 467 468 *cqe_flushed = 0; 469 *credit = 0; 470 ret = t4_next_cqe(cq, &hw_cqe); 471 if (ret) 472 return ret; 473 474 PDBG("%s CQE OVF %u qpid 0x%0x genbit %u type %u status 0x%0x" 475 " opcode 0x%0x len 0x%0x wrid_hi_stag 0x%x wrid_low_msn 0x%x\n", 476 __func__, CQE_OVFBIT(hw_cqe), CQE_QPID(hw_cqe), 477 CQE_GENBIT(hw_cqe), CQE_TYPE(hw_cqe), CQE_STATUS(hw_cqe), 478 CQE_OPCODE(hw_cqe), CQE_LEN(hw_cqe), CQE_WRID_HI(hw_cqe), 479 CQE_WRID_LOW(hw_cqe)); 480 481 /* 482 * skip cqe's not affiliated with a QP. 483 */ 484 if (wq == NULL) { 485 ret = -EAGAIN; 486 goto skip_cqe; 487 } 488 489 /* 490 * skip hw cqe's if the wq is flushed. 491 */ 492 if (wq->flushed && !SW_CQE(hw_cqe)) { 493 ret = -EAGAIN; 494 goto skip_cqe; 495 } 496 497 /* 498 * skip TERMINATE cqes... 499 */ 500 if (CQE_OPCODE(hw_cqe) == FW_RI_TERMINATE) { 501 ret = -EAGAIN; 502 goto skip_cqe; 503 } 504 505 /* 506 * Gotta tweak READ completions: 507 * 1) the cqe doesn't contain the sq_wptr from the wr. 508 * 2) opcode not reflected from the wr. 509 * 3) read_len not reflected from the wr. 510 * 4) cq_type is RQ_TYPE not SQ_TYPE. 511 */ 512 if (RQ_TYPE(hw_cqe) && (CQE_OPCODE(hw_cqe) == FW_RI_READ_RESP)) { 513 514 /* 515 * If this is an unsolicited read response, then the read 516 * was generated by the kernel driver as part of peer-2-peer 517 * connection setup. So ignore the completion. 518 */ 519 if (CQE_WRID_STAG(hw_cqe) == 1) { 520 if (CQE_STATUS(hw_cqe)) 521 t4_set_wq_in_error(wq); 522 ret = -EAGAIN; 523 goto skip_cqe; 524 } 525 526 /* 527 * Eat completions for unsignaled read WRs. 528 */ 529 if (!wq->sq.oldest_read->signaled) { 530 advance_oldest_read(wq); 531 ret = -EAGAIN; 532 goto skip_cqe; 533 } 534 535 /* 536 * Don't write to the HWCQ, so create a new read req CQE 537 * in local memory. 538 */ 539 create_read_req_cqe(wq, hw_cqe, &read_cqe); 540 hw_cqe = &read_cqe; 541 advance_oldest_read(wq); 542 } 543 544 if (CQE_STATUS(hw_cqe) || t4_wq_in_error(wq)) { 545 *cqe_flushed = (CQE_STATUS(hw_cqe) == T4_ERR_SWFLUSH); 546 t4_set_wq_in_error(wq); 547 } 548 549 /* 550 * RECV completion. 551 */ 552 if (RQ_TYPE(hw_cqe)) { 553 554 /* 555 * HW only validates 4 bits of MSN. So we must validate that 556 * the MSN in the SEND is the next expected MSN. If its not, 557 * then we complete this with T4_ERR_MSN and mark the wq in 558 * error. 559 */ 560 561 if (t4_rq_empty(wq)) { 562 t4_set_wq_in_error(wq); 563 ret = -EAGAIN; 564 goto skip_cqe; 565 } 566 if (unlikely((CQE_WRID_MSN(hw_cqe) != (wq->rq.msn)))) { 567 t4_set_wq_in_error(wq); 568 hw_cqe->header |= htonl(V_CQE_STATUS(T4_ERR_MSN)); 569 goto proc_cqe; 570 } 571 goto proc_cqe; 572 } 573 574 /* 575 * If we get here its a send completion. 576 * 577 * Handle out of order completion. These get stuffed 578 * in the SW SQ. Then the SW SQ is walked to move any 579 * now in-order completions into the SW CQ. This handles 580 * 2 cases: 581 * 1) reaping unsignaled WRs when the first subsequent 582 * signaled WR is completed. 583 * 2) out of order read completions. 584 */ 585 if (!SW_CQE(hw_cqe) && (CQE_WRID_SQ_IDX(hw_cqe) != wq->sq.cidx)) { 586 struct t4_swsqe *swsqe; 587 588 PDBG("%s out of order completion going in sw_sq at idx %u\n", 589 __func__, CQE_WRID_SQ_IDX(hw_cqe)); 590 swsqe = &wq->sq.sw_sq[CQE_WRID_SQ_IDX(hw_cqe)]; 591 swsqe->cqe = *hw_cqe; 592 swsqe->complete = 1; 593 ret = -EAGAIN; 594 goto flush_wq; 595 } 596 597 proc_cqe: 598 *cqe = *hw_cqe; 599 600 /* 601 * Reap the associated WR(s) that are freed up with this 602 * completion. 603 */ 604 if (SQ_TYPE(hw_cqe)) { 605 int idx = CQE_WRID_SQ_IDX(hw_cqe); 606 BUG_ON(idx > wq->sq.size); 607 608 /* 609 * Account for any unsignaled completions completed by 610 * this signaled completion. In this case, cidx points 611 * to the first unsignaled one, and idx points to the 612 * signaled one. So adjust in_use based on this delta. 613 * if this is not completing any unsigned wrs, then the 614 * delta will be 0. Handle wrapping also! 615 */ 616 if (idx < wq->sq.cidx) 617 wq->sq.in_use -= wq->sq.size + idx - wq->sq.cidx; 618 else 619 wq->sq.in_use -= idx - wq->sq.cidx; 620 BUG_ON(wq->sq.in_use < 0 && wq->sq.in_use < wq->sq.size); 621 622 wq->sq.cidx = (uint16_t)idx; 623 PDBG("%s completing sq idx %u\n", __func__, wq->sq.cidx); 624 *cookie = wq->sq.sw_sq[wq->sq.cidx].wr_id; 625 t4_sq_consume(wq); 626 } else { 627 PDBG("%s completing rq idx %u\n", __func__, wq->rq.cidx); 628 *cookie = wq->rq.sw_rq[wq->rq.cidx].wr_id; 629 BUG_ON(t4_rq_empty(wq)); 630 t4_rq_consume(wq); 631 goto skip_cqe; 632 } 633 634 flush_wq: 635 /* 636 * Flush any completed cqes that are now in-order. 637 */ 638 flush_completed_wrs(wq, cq); 639 640 skip_cqe: 641 if (SW_CQE(hw_cqe)) { 642 PDBG("%s cq %p cqid 0x%x skip sw cqe cidx %u\n", 643 __func__, cq, cq->cqid, cq->sw_cidx); 644 t4_swcq_consume(cq); 645 } else { 646 PDBG("%s cq %p cqid 0x%x skip hw cqe cidx %u\n", 647 __func__, cq, cq->cqid, cq->cidx); 648 t4_hwcq_consume(cq); 649 } 650 return ret; 651 } 652 653 /* 654 * Get one cq entry from c4iw and map it to openib. 655 * 656 * Returns: 657 * 0 cqe returned 658 * -ENODATA EMPTY; 659 * -EAGAIN caller must try again 660 * any other -errno fatal error 661 */ 662 static int c4iw_poll_cq_one(struct c4iw_cq *chp, struct ib_wc *wc) 663 { 664 struct c4iw_qp *qhp = NULL; 665 struct t4_cqe cqe = {0, 0}, *rd_cqe; 666 struct t4_wq *wq; 667 u32 credit = 0; 668 u8 cqe_flushed; 669 u64 cookie = 0; 670 int ret; 671 672 ret = t4_next_cqe(&chp->cq, &rd_cqe); 673 674 if (ret) 675 return ret; 676 677 qhp = get_qhp(chp->rhp, CQE_QPID(rd_cqe)); 678 if (!qhp) 679 wq = NULL; 680 else { 681 spin_lock(&qhp->lock); 682 wq = &(qhp->wq); 683 } 684 ret = poll_cq(wq, &(chp->cq), &cqe, &cqe_flushed, &cookie, &credit); 685 if (ret) 686 goto out; 687 688 wc->wr_id = cookie; 689 wc->qp = &qhp->ibqp; 690 wc->vendor_err = CQE_STATUS(&cqe); 691 wc->wc_flags = 0; 692 693 PDBG("%s qpid 0x%x type %d opcode %d status 0x%x len %u wrid hi 0x%x " 694 "lo 0x%x cookie 0x%llx\n", __func__, CQE_QPID(&cqe), 695 CQE_TYPE(&cqe), CQE_OPCODE(&cqe), CQE_STATUS(&cqe), CQE_LEN(&cqe), 696 CQE_WRID_HI(&cqe), CQE_WRID_LOW(&cqe), (unsigned long long)cookie); 697 698 if (CQE_TYPE(&cqe) == 0) { 699 if (!CQE_STATUS(&cqe)) 700 wc->byte_len = CQE_LEN(&cqe); 701 else 702 wc->byte_len = 0; 703 wc->opcode = IB_WC_RECV; 704 if (CQE_OPCODE(&cqe) == FW_RI_SEND_WITH_INV || 705 CQE_OPCODE(&cqe) == FW_RI_SEND_WITH_SE_INV) { 706 wc->ex.invalidate_rkey = CQE_WRID_STAG(&cqe); 707 wc->wc_flags |= IB_WC_WITH_INVALIDATE; 708 } 709 } else { 710 switch (CQE_OPCODE(&cqe)) { 711 case FW_RI_RDMA_WRITE: 712 wc->opcode = IB_WC_RDMA_WRITE; 713 break; 714 case FW_RI_READ_REQ: 715 wc->opcode = IB_WC_RDMA_READ; 716 wc->byte_len = CQE_LEN(&cqe); 717 break; 718 case FW_RI_SEND_WITH_INV: 719 case FW_RI_SEND_WITH_SE_INV: 720 wc->opcode = IB_WC_SEND; 721 wc->wc_flags |= IB_WC_WITH_INVALIDATE; 722 break; 723 case FW_RI_SEND: 724 case FW_RI_SEND_WITH_SE: 725 wc->opcode = IB_WC_SEND; 726 break; 727 case FW_RI_BIND_MW: 728 wc->opcode = IB_WC_BIND_MW; 729 break; 730 731 case FW_RI_LOCAL_INV: 732 wc->opcode = IB_WC_LOCAL_INV; 733 break; 734 case FW_RI_FAST_REGISTER: 735 wc->opcode = IB_WC_FAST_REG_MR; 736 break; 737 default: 738 printk(KERN_ERR MOD "Unexpected opcode %d " 739 "in the CQE received for QPID=0x%0x\n", 740 CQE_OPCODE(&cqe), CQE_QPID(&cqe)); 741 ret = -EINVAL; 742 goto out; 743 } 744 } 745 746 if (cqe_flushed) 747 wc->status = IB_WC_WR_FLUSH_ERR; 748 else { 749 750 switch (CQE_STATUS(&cqe)) { 751 case T4_ERR_SUCCESS: 752 wc->status = IB_WC_SUCCESS; 753 break; 754 case T4_ERR_STAG: 755 wc->status = IB_WC_LOC_ACCESS_ERR; 756 break; 757 case T4_ERR_PDID: 758 wc->status = IB_WC_LOC_PROT_ERR; 759 break; 760 case T4_ERR_QPID: 761 case T4_ERR_ACCESS: 762 wc->status = IB_WC_LOC_ACCESS_ERR; 763 break; 764 case T4_ERR_WRAP: 765 wc->status = IB_WC_GENERAL_ERR; 766 break; 767 case T4_ERR_BOUND: 768 wc->status = IB_WC_LOC_LEN_ERR; 769 break; 770 case T4_ERR_INVALIDATE_SHARED_MR: 771 case T4_ERR_INVALIDATE_MR_WITH_MW_BOUND: 772 wc->status = IB_WC_MW_BIND_ERR; 773 break; 774 case T4_ERR_CRC: 775 case T4_ERR_MARKER: 776 case T4_ERR_PDU_LEN_ERR: 777 case T4_ERR_OUT_OF_RQE: 778 case T4_ERR_DDP_VERSION: 779 case T4_ERR_RDMA_VERSION: 780 case T4_ERR_DDP_QUEUE_NUM: 781 case T4_ERR_MSN: 782 case T4_ERR_TBIT: 783 case T4_ERR_MO: 784 case T4_ERR_MSN_RANGE: 785 case T4_ERR_IRD_OVERFLOW: 786 case T4_ERR_OPCODE: 787 case T4_ERR_INTERNAL_ERR: 788 wc->status = IB_WC_FATAL_ERR; 789 break; 790 case T4_ERR_SWFLUSH: 791 wc->status = IB_WC_WR_FLUSH_ERR; 792 break; 793 default: 794 printk(KERN_ERR MOD 795 "Unexpected cqe_status 0x%x for QPID=0x%0x\n", 796 CQE_STATUS(&cqe), CQE_QPID(&cqe)); 797 ret = -EINVAL; 798 } 799 } 800 out: 801 if (wq) 802 spin_unlock(&qhp->lock); 803 return ret; 804 } 805 806 int c4iw_poll_cq(struct ib_cq *ibcq, int num_entries, struct ib_wc *wc) 807 { 808 struct c4iw_cq *chp; 809 unsigned long flags; 810 int npolled; 811 int err = 0; 812 813 chp = to_c4iw_cq(ibcq); 814 815 spin_lock_irqsave(&chp->lock, flags); 816 for (npolled = 0; npolled < num_entries; ++npolled) { 817 do { 818 err = c4iw_poll_cq_one(chp, wc + npolled); 819 } while (err == -EAGAIN); 820 if (err) 821 break; 822 } 823 spin_unlock_irqrestore(&chp->lock, flags); 824 return !err || err == -ENODATA ? npolled : err; 825 } 826 827 int c4iw_destroy_cq(struct ib_cq *ib_cq) 828 { 829 struct c4iw_cq *chp; 830 struct c4iw_ucontext *ucontext; 831 832 PDBG("%s ib_cq %p\n", __func__, ib_cq); 833 chp = to_c4iw_cq(ib_cq); 834 835 remove_handle(chp->rhp, &chp->rhp->cqidr, chp->cq.cqid); 836 atomic_dec(&chp->refcnt); 837 wait_event(chp->wait, !atomic_read(&chp->refcnt)); 838 839 ucontext = ib_cq->uobject ? to_c4iw_ucontext(ib_cq->uobject->context) 840 : NULL; 841 destroy_cq(&chp->rhp->rdev, &chp->cq, 842 ucontext ? &ucontext->uctx : &chp->cq.rdev->uctx); 843 kfree(chp); 844 return 0; 845 } 846 847 struct ib_cq *c4iw_create_cq(struct ib_device *ibdev, int entries, 848 int vector, struct ib_ucontext *ib_context, 849 struct ib_udata *udata) 850 { 851 struct c4iw_dev *rhp; 852 struct c4iw_cq *chp; 853 struct c4iw_create_cq_resp uresp; 854 struct c4iw_ucontext *ucontext = NULL; 855 int ret; 856 size_t memsize, hwentries; 857 struct c4iw_mm_entry *mm, *mm2; 858 859 PDBG("%s ib_dev %p entries %d\n", __func__, ibdev, entries); 860 861 rhp = to_c4iw_dev(ibdev); 862 863 chp = kzalloc(sizeof(*chp), GFP_KERNEL); 864 if (!chp) 865 return ERR_PTR(-ENOMEM); 866 867 if (ib_context) 868 ucontext = to_c4iw_ucontext(ib_context); 869 870 /* account for the status page. */ 871 entries++; 872 873 /* IQ needs one extra entry to differentiate full vs empty. */ 874 entries++; 875 876 /* 877 * entries must be multiple of 16 for HW. 878 */ 879 entries = roundup(entries, 16); 880 881 /* 882 * Make actual HW queue 2x to avoid cdix_inc overflows. 883 */ 884 hwentries = entries * 2; 885 886 /* 887 * Make HW queue at least 64 entries so GTS updates aren't too 888 * frequent. 889 */ 890 if (hwentries < 64) 891 hwentries = 64; 892 893 memsize = hwentries * sizeof *chp->cq.queue; 894 895 /* 896 * memsize must be a multiple of the page size if its a user cq. 897 */ 898 if (ucontext) { 899 memsize = roundup(memsize, PAGE_SIZE); 900 hwentries = memsize / sizeof *chp->cq.queue; 901 while (hwentries > T4_MAX_IQ_SIZE) { 902 memsize -= PAGE_SIZE; 903 hwentries = memsize / sizeof *chp->cq.queue; 904 } 905 } 906 chp->cq.size = hwentries; 907 chp->cq.memsize = memsize; 908 909 ret = create_cq(&rhp->rdev, &chp->cq, 910 ucontext ? &ucontext->uctx : &rhp->rdev.uctx); 911 if (ret) 912 goto err1; 913 914 chp->rhp = rhp; 915 chp->cq.size--; /* status page */ 916 chp->ibcq.cqe = entries - 2; 917 spin_lock_init(&chp->lock); 918 spin_lock_init(&chp->comp_handler_lock); 919 atomic_set(&chp->refcnt, 1); 920 init_waitqueue_head(&chp->wait); 921 ret = insert_handle(rhp, &rhp->cqidr, chp, chp->cq.cqid); 922 if (ret) 923 goto err2; 924 925 if (ucontext) { 926 mm = kmalloc(sizeof *mm, GFP_KERNEL); 927 if (!mm) 928 goto err3; 929 mm2 = kmalloc(sizeof *mm2, GFP_KERNEL); 930 if (!mm2) 931 goto err4; 932 933 uresp.qid_mask = rhp->rdev.cqmask; 934 uresp.cqid = chp->cq.cqid; 935 uresp.size = chp->cq.size; 936 uresp.memsize = chp->cq.memsize; 937 spin_lock(&ucontext->mmap_lock); 938 uresp.key = ucontext->key; 939 ucontext->key += PAGE_SIZE; 940 uresp.gts_key = ucontext->key; 941 ucontext->key += PAGE_SIZE; 942 spin_unlock(&ucontext->mmap_lock); 943 ret = ib_copy_to_udata(udata, &uresp, sizeof uresp); 944 if (ret) 945 goto err5; 946 947 mm->key = uresp.key; 948 mm->addr = virt_to_phys(chp->cq.queue); 949 mm->len = chp->cq.memsize; 950 insert_mmap(ucontext, mm); 951 952 mm2->key = uresp.gts_key; 953 mm2->addr = chp->cq.ugts; 954 mm2->len = PAGE_SIZE; 955 insert_mmap(ucontext, mm2); 956 } 957 PDBG("%s cqid 0x%0x chp %p size %u memsize %zu, dma_addr 0x%0llx\n", 958 __func__, chp->cq.cqid, chp, chp->cq.size, 959 chp->cq.memsize, 960 (unsigned long long) chp->cq.dma_addr); 961 return &chp->ibcq; 962 err5: 963 kfree(mm2); 964 err4: 965 kfree(mm); 966 err3: 967 remove_handle(rhp, &rhp->cqidr, chp->cq.cqid); 968 err2: 969 destroy_cq(&chp->rhp->rdev, &chp->cq, 970 ucontext ? &ucontext->uctx : &rhp->rdev.uctx); 971 err1: 972 kfree(chp); 973 return ERR_PTR(ret); 974 } 975 976 int c4iw_resize_cq(struct ib_cq *cq, int cqe, struct ib_udata *udata) 977 { 978 return -ENOSYS; 979 } 980 981 int c4iw_arm_cq(struct ib_cq *ibcq, enum ib_cq_notify_flags flags) 982 { 983 struct c4iw_cq *chp; 984 int ret; 985 unsigned long flag; 986 987 chp = to_c4iw_cq(ibcq); 988 spin_lock_irqsave(&chp->lock, flag); 989 ret = t4_arm_cq(&chp->cq, 990 (flags & IB_CQ_SOLICITED_MASK) == IB_CQ_SOLICITED); 991 spin_unlock_irqrestore(&chp->lock, flag); 992 if (ret && !(flags & IB_CQ_REPORT_MISSED_EVENTS)) 993 ret = 0; 994 return ret; 995 } 996