1 /* 2 * Broadcom NetXtreme-E RoCE driver. 3 * 4 * Copyright (c) 2016 - 2017, Broadcom. All rights reserved. The term 5 * Broadcom refers to Broadcom Limited and/or its subsidiaries. 6 * 7 * This software is available to you under a choice of one of two 8 * licenses. You may choose to be licensed under the terms of the GNU 9 * General Public License (GPL) Version 2, available from the file 10 * COPYING in the main directory of this source tree, or the 11 * BSD license below: 12 * 13 * Redistribution and use in source and binary forms, with or without 14 * modification, are permitted provided that the following conditions 15 * are met: 16 * 17 * 1. Redistributions of source code must retain the above copyright 18 * notice, this list of conditions and the following disclaimer. 19 * 2. Redistributions in binary form must reproduce the above copyright 20 * notice, this list of conditions and the following disclaimer in 21 * the documentation and/or other materials provided with the 22 * distribution. 23 * 24 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' 25 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, 26 * THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR 27 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS 28 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 29 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 30 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR 31 * BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, 32 * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE 33 * OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN 34 * IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 35 * 36 * Description: RoCE HSI File - Autogenerated 37 */ 38 39 #ifndef __BNXT_RE_HSI_H__ 40 #define __BNXT_RE_HSI_H__ 41 42 /* include bnxt_hsi.h from bnxt_en driver */ 43 #include "bnxt_hsi.h" 44 45 /* CMP Door Bell Format (4 bytes) */ 46 struct cmpl_doorbell { 47 __le32 key_mask_valid_idx; 48 #define CMPL_DOORBELL_IDX_MASK 0xffffffUL 49 #define CMPL_DOORBELL_IDX_SFT 0 50 #define CMPL_DOORBELL_RESERVED_MASK 0x3000000UL 51 #define CMPL_DOORBELL_RESERVED_SFT 24 52 #define CMPL_DOORBELL_IDX_VALID 0x4000000UL 53 #define CMPL_DOORBELL_MASK 0x8000000UL 54 #define CMPL_DOORBELL_KEY_MASK 0xf0000000UL 55 #define CMPL_DOORBELL_KEY_SFT 28 56 #define CMPL_DOORBELL_KEY_CMPL (0x2UL << 28) 57 }; 58 59 /* Status Door Bell Format (4 bytes) */ 60 struct status_doorbell { 61 __le32 key_idx; 62 #define STATUS_DOORBELL_IDX_MASK 0xffffffUL 63 #define STATUS_DOORBELL_IDX_SFT 0 64 #define STATUS_DOORBELL_RESERVED_MASK 0xf000000UL 65 #define STATUS_DOORBELL_RESERVED_SFT 24 66 #define STATUS_DOORBELL_KEY_MASK 0xf0000000UL 67 #define STATUS_DOORBELL_KEY_SFT 28 68 #define STATUS_DOORBELL_KEY_STAT (0x3UL << 28) 69 }; 70 71 /* RoCE Host Structures */ 72 73 /* Doorbell Structures */ 74 /* dbc_dbc (size:64b/8B) */ 75 struct dbc_dbc { 76 __le32 index; 77 #define DBC_DBC_INDEX_MASK 0xffffffUL 78 #define DBC_DBC_INDEX_SFT 0 79 __le32 type_path_xid; 80 #define DBC_DBC_XID_MASK 0xfffffUL 81 #define DBC_DBC_XID_SFT 0 82 #define DBC_DBC_PATH_MASK 0x3000000UL 83 #define DBC_DBC_PATH_SFT 24 84 #define DBC_DBC_PATH_ROCE (0x0UL << 24) 85 #define DBC_DBC_PATH_L2 (0x1UL << 24) 86 #define DBC_DBC_PATH_ENGINE (0x2UL << 24) 87 #define DBC_DBC_PATH_LAST DBC_DBC_PATH_ENGINE 88 #define DBC_DBC_DEBUG_TRACE 0x8000000UL 89 #define DBC_DBC_TYPE_MASK 0xf0000000UL 90 #define DBC_DBC_TYPE_SFT 28 91 #define DBC_DBC_TYPE_SQ (0x0UL << 28) 92 #define DBC_DBC_TYPE_RQ (0x1UL << 28) 93 #define DBC_DBC_TYPE_SRQ (0x2UL << 28) 94 #define DBC_DBC_TYPE_SRQ_ARM (0x3UL << 28) 95 #define DBC_DBC_TYPE_CQ (0x4UL << 28) 96 #define DBC_DBC_TYPE_CQ_ARMSE (0x5UL << 28) 97 #define DBC_DBC_TYPE_CQ_ARMALL (0x6UL << 28) 98 #define DBC_DBC_TYPE_CQ_ARMENA (0x7UL << 28) 99 #define DBC_DBC_TYPE_SRQ_ARMENA (0x8UL << 28) 100 #define DBC_DBC_TYPE_CQ_CUTOFF_ACK (0x9UL << 28) 101 #define DBC_DBC_TYPE_NQ (0xaUL << 28) 102 #define DBC_DBC_TYPE_NQ_ARM (0xbUL << 28) 103 #define DBC_DBC_TYPE_NULL (0xfUL << 28) 104 #define DBC_DBC_TYPE_LAST DBC_DBC_TYPE_NULL 105 }; 106 107 /* dbc_dbc32 (size:32b/4B) */ 108 struct dbc_dbc32 { 109 __le32 type_abs_incr_xid; 110 #define DBC_DBC32_XID_MASK 0xfffffUL 111 #define DBC_DBC32_XID_SFT 0 112 #define DBC_DBC32_PATH_MASK 0xc00000UL 113 #define DBC_DBC32_PATH_SFT 22 114 #define DBC_DBC32_PATH_ROCE (0x0UL << 22) 115 #define DBC_DBC32_PATH_L2 (0x1UL << 22) 116 #define DBC_DBC32_PATH_LAST DBC_DBC32_PATH_L2 117 #define DBC_DBC32_INCR_MASK 0xf000000UL 118 #define DBC_DBC32_INCR_SFT 24 119 #define DBC_DBC32_ABS 0x10000000UL 120 #define DBC_DBC32_TYPE_MASK 0xe0000000UL 121 #define DBC_DBC32_TYPE_SFT 29 122 #define DBC_DBC32_TYPE_SQ (0x0UL << 29) 123 #define DBC_DBC32_TYPE_LAST DBC_DBC32_TYPE_SQ 124 }; 125 126 /* SQ WQE Structures */ 127 /* Base SQ WQE (8 bytes) */ 128 struct sq_base { 129 u8 wqe_type; 130 #define SQ_BASE_WQE_TYPE_SEND 0x0UL 131 #define SQ_BASE_WQE_TYPE_SEND_W_IMMEAD 0x1UL 132 #define SQ_BASE_WQE_TYPE_SEND_W_INVALID 0x2UL 133 #define SQ_BASE_WQE_TYPE_WRITE_WQE 0x4UL 134 #define SQ_BASE_WQE_TYPE_WRITE_W_IMMEAD 0x5UL 135 #define SQ_BASE_WQE_TYPE_READ_WQE 0x6UL 136 #define SQ_BASE_WQE_TYPE_ATOMIC_CS 0x8UL 137 #define SQ_BASE_WQE_TYPE_ATOMIC_FA 0xbUL 138 #define SQ_BASE_WQE_TYPE_LOCAL_INVALID 0xcUL 139 #define SQ_BASE_WQE_TYPE_FR_PMR 0xdUL 140 #define SQ_BASE_WQE_TYPE_BIND 0xeUL 141 u8 unused_0[7]; 142 }; 143 144 /* WQE SGE (16 bytes) */ 145 struct sq_sge { 146 __le64 va_or_pa; 147 __le32 l_key; 148 __le32 size; 149 }; 150 151 /* PSN Search Structure (8 bytes) */ 152 struct sq_psn_search { 153 __le32 opcode_start_psn; 154 #define SQ_PSN_SEARCH_START_PSN_MASK 0xffffffUL 155 #define SQ_PSN_SEARCH_START_PSN_SFT 0 156 #define SQ_PSN_SEARCH_OPCODE_MASK 0xff000000UL 157 #define SQ_PSN_SEARCH_OPCODE_SFT 24 158 __le32 flags_next_psn; 159 #define SQ_PSN_SEARCH_NEXT_PSN_MASK 0xffffffUL 160 #define SQ_PSN_SEARCH_NEXT_PSN_SFT 0 161 #define SQ_PSN_SEARCH_FLAGS_MASK 0xff000000UL 162 #define SQ_PSN_SEARCH_FLAGS_SFT 24 163 }; 164 165 /* sq_psn_search_ext (size:128b/16B) */ 166 struct sq_psn_search_ext { 167 __le32 opcode_start_psn; 168 #define SQ_PSN_SEARCH_EXT_START_PSN_MASK 0xffffffUL 169 #define SQ_PSN_SEARCH_EXT_START_PSN_SFT 0 170 #define SQ_PSN_SEARCH_EXT_OPCODE_MASK 0xff000000UL 171 #define SQ_PSN_SEARCH_EXT_OPCODE_SFT 24 172 __le32 flags_next_psn; 173 #define SQ_PSN_SEARCH_EXT_NEXT_PSN_MASK 0xffffffUL 174 #define SQ_PSN_SEARCH_EXT_NEXT_PSN_SFT 0 175 #define SQ_PSN_SEARCH_EXT_FLAGS_MASK 0xff000000UL 176 #define SQ_PSN_SEARCH_EXT_FLAGS_SFT 24 177 __le16 start_slot_idx; 178 __le16 reserved16; 179 __le32 reserved32; 180 }; 181 182 /* Send SQ WQE (40 bytes) */ 183 struct sq_send { 184 u8 wqe_type; 185 #define SQ_SEND_WQE_TYPE_SEND 0x0UL 186 #define SQ_SEND_WQE_TYPE_SEND_W_IMMEAD 0x1UL 187 #define SQ_SEND_WQE_TYPE_SEND_W_INVALID 0x2UL 188 u8 flags; 189 #define SQ_SEND_FLAGS_SIGNAL_COMP 0x1UL 190 #define SQ_SEND_FLAGS_RD_OR_ATOMIC_FENCE 0x2UL 191 #define SQ_SEND_FLAGS_UC_FENCE 0x4UL 192 #define SQ_SEND_FLAGS_SE 0x8UL 193 #define SQ_SEND_FLAGS_INLINE 0x10UL 194 u8 wqe_size; 195 u8 reserved8_1; 196 __le32 inv_key_or_imm_data; 197 __le32 length; 198 __le32 q_key; 199 __le32 dst_qp; 200 #define SQ_SEND_DST_QP_MASK 0xffffffUL 201 #define SQ_SEND_DST_QP_SFT 0 202 #define SQ_SEND_RESERVED8_2_MASK 0xff000000UL 203 #define SQ_SEND_RESERVED8_2_SFT 24 204 __le32 avid; 205 #define SQ_SEND_AVID_MASK 0xfffffUL 206 #define SQ_SEND_AVID_SFT 0 207 #define SQ_SEND_RESERVED_AVID_MASK 0xfff00000UL 208 #define SQ_SEND_RESERVED_AVID_SFT 20 209 __le64 reserved64; 210 __le32 data[24]; 211 }; 212 213 /* Send Raw Ethernet and QP1 SQ WQE (40 bytes) */ 214 struct sq_send_raweth_qp1 { 215 u8 wqe_type; 216 #define SQ_SEND_RAWETH_QP1_WQE_TYPE_SEND 0x0UL 217 u8 flags; 218 #define SQ_SEND_RAWETH_QP1_FLAGS_SIGNAL_COMP 0x1UL 219 #define SQ_SEND_RAWETH_QP1_FLAGS_RD_OR_ATOMIC_FENCE 0x2UL 220 #define SQ_SEND_RAWETH_QP1_FLAGS_UC_FENCE 0x4UL 221 #define SQ_SEND_RAWETH_QP1_FLAGS_SE 0x8UL 222 #define SQ_SEND_RAWETH_QP1_FLAGS_INLINE 0x10UL 223 u8 wqe_size; 224 u8 reserved8; 225 __le16 lflags; 226 #define SQ_SEND_RAWETH_QP1_LFLAGS_TCP_UDP_CHKSUM 0x1UL 227 #define SQ_SEND_RAWETH_QP1_LFLAGS_IP_CHKSUM 0x2UL 228 #define SQ_SEND_RAWETH_QP1_LFLAGS_NOCRC 0x4UL 229 #define SQ_SEND_RAWETH_QP1_LFLAGS_STAMP 0x8UL 230 #define SQ_SEND_RAWETH_QP1_LFLAGS_T_IP_CHKSUM 0x10UL 231 #define SQ_SEND_RAWETH_QP1_LFLAGS_RESERVED1_1 0x20UL 232 #define SQ_SEND_RAWETH_QP1_LFLAGS_RESERVED1_2 0x40UL 233 #define SQ_SEND_RAWETH_QP1_LFLAGS_RESERVED1_3 0x80UL 234 #define SQ_SEND_RAWETH_QP1_LFLAGS_ROCE_CRC 0x100UL 235 #define SQ_SEND_RAWETH_QP1_LFLAGS_FCOE_CRC 0x200UL 236 __le16 cfa_action; 237 __le32 length; 238 __le32 reserved32_1; 239 __le32 cfa_meta; 240 #define SQ_SEND_RAWETH_QP1_CFA_META_VLAN_VID_MASK 0xfffUL 241 #define SQ_SEND_RAWETH_QP1_CFA_META_VLAN_VID_SFT 0 242 #define SQ_SEND_RAWETH_QP1_CFA_META_VLAN_DE 0x1000UL 243 #define SQ_SEND_RAWETH_QP1_CFA_META_VLAN_PRI_MASK 0xe000UL 244 #define SQ_SEND_RAWETH_QP1_CFA_META_VLAN_PRI_SFT 13 245 #define SQ_SEND_RAWETH_QP1_CFA_META_VLAN_TPID_MASK 0x70000UL 246 #define SQ_SEND_RAWETH_QP1_CFA_META_VLAN_TPID_SFT 16 247 #define SQ_SEND_RAWETH_QP1_CFA_META_VLAN_TPID_TPID88A8 (0x0UL << 16) 248 #define SQ_SEND_RAWETH_QP1_CFA_META_VLAN_TPID_TPID8100 (0x1UL << 16) 249 #define SQ_SEND_RAWETH_QP1_CFA_META_VLAN_TPID_TPID9100 (0x2UL << 16) 250 #define SQ_SEND_RAWETH_QP1_CFA_META_VLAN_TPID_TPID9200 (0x3UL << 16) 251 #define SQ_SEND_RAWETH_QP1_CFA_META_VLAN_TPID_TPID9300 (0x4UL << 16) 252 #define SQ_SEND_RAWETH_QP1_CFA_META_VLAN_TPID_TPIDCFG (0x5UL << 16) 253 #define SQ_SEND_RAWETH_QP1_CFA_META_VLAN_TPID_LAST \ 254 SQ_SEND_RAWETH_QP1_CFA_META_VLAN_TPID_TPIDCFG 255 #define SQ_SEND_RAWETH_QP1_CFA_META_VLAN_RESERVED_MASK 0xff80000UL 256 #define SQ_SEND_RAWETH_QP1_CFA_META_VLAN_RESERVED_SFT 19 257 #define SQ_SEND_RAWETH_QP1_CFA_META_KEY_MASK 0xf0000000UL 258 #define SQ_SEND_RAWETH_QP1_CFA_META_KEY_SFT 28 259 #define SQ_SEND_RAWETH_QP1_CFA_META_KEY_NONE (0x0UL << 28) 260 #define SQ_SEND_RAWETH_QP1_CFA_META_KEY_VLAN_TAG (0x1UL << 28) 261 #define SQ_SEND_RAWETH_QP1_CFA_META_KEY_LAST \ 262 SQ_SEND_RAWETH_QP1_CFA_META_KEY_VLAN_TAG 263 __le32 reserved32_2; 264 __le64 reserved64; 265 __le32 data[24]; 266 }; 267 268 /* RDMA SQ WQE (40 bytes) */ 269 struct sq_rdma { 270 u8 wqe_type; 271 #define SQ_RDMA_WQE_TYPE_WRITE_WQE 0x4UL 272 #define SQ_RDMA_WQE_TYPE_WRITE_W_IMMEAD 0x5UL 273 #define SQ_RDMA_WQE_TYPE_READ_WQE 0x6UL 274 u8 flags; 275 #define SQ_RDMA_FLAGS_SIGNAL_COMP 0x1UL 276 #define SQ_RDMA_FLAGS_RD_OR_ATOMIC_FENCE 0x2UL 277 #define SQ_RDMA_FLAGS_UC_FENCE 0x4UL 278 #define SQ_RDMA_FLAGS_SE 0x8UL 279 #define SQ_RDMA_FLAGS_INLINE 0x10UL 280 u8 wqe_size; 281 u8 reserved8; 282 __le32 imm_data; 283 __le32 length; 284 __le32 reserved32_1; 285 __le64 remote_va; 286 __le32 remote_key; 287 __le32 reserved32_2; 288 __le32 data[24]; 289 }; 290 291 /* Atomic SQ WQE (40 bytes) */ 292 struct sq_atomic { 293 u8 wqe_type; 294 #define SQ_ATOMIC_WQE_TYPE_ATOMIC_CS 0x8UL 295 #define SQ_ATOMIC_WQE_TYPE_ATOMIC_FA 0xbUL 296 u8 flags; 297 #define SQ_ATOMIC_FLAGS_SIGNAL_COMP 0x1UL 298 #define SQ_ATOMIC_FLAGS_RD_OR_ATOMIC_FENCE 0x2UL 299 #define SQ_ATOMIC_FLAGS_UC_FENCE 0x4UL 300 #define SQ_ATOMIC_FLAGS_SE 0x8UL 301 #define SQ_ATOMIC_FLAGS_INLINE 0x10UL 302 __le16 reserved16; 303 __le32 remote_key; 304 __le64 remote_va; 305 __le64 swap_data; 306 __le64 cmp_data; 307 __le32 data[24]; 308 }; 309 310 /* Local Invalidate SQ WQE (40 bytes) */ 311 struct sq_localinvalidate { 312 u8 wqe_type; 313 #define SQ_LOCALINVALIDATE_WQE_TYPE_LOCAL_INVALID 0xcUL 314 u8 flags; 315 #define SQ_LOCALINVALIDATE_FLAGS_SIGNAL_COMP 0x1UL 316 #define SQ_LOCALINVALIDATE_FLAGS_RD_OR_ATOMIC_FENCE 0x2UL 317 #define SQ_LOCALINVALIDATE_FLAGS_UC_FENCE 0x4UL 318 #define SQ_LOCALINVALIDATE_FLAGS_SE 0x8UL 319 #define SQ_LOCALINVALIDATE_FLAGS_INLINE 0x10UL 320 __le16 reserved16; 321 __le32 inv_l_key; 322 __le64 reserved64; 323 __le32 reserved128[4]; 324 __le32 data[24]; 325 }; 326 327 /* FR-PMR SQ WQE (40 bytes) */ 328 struct sq_fr_pmr { 329 u8 wqe_type; 330 #define SQ_FR_PMR_WQE_TYPE_FR_PMR 0xdUL 331 u8 flags; 332 #define SQ_FR_PMR_FLAGS_SIGNAL_COMP 0x1UL 333 #define SQ_FR_PMR_FLAGS_RD_OR_ATOMIC_FENCE 0x2UL 334 #define SQ_FR_PMR_FLAGS_UC_FENCE 0x4UL 335 #define SQ_FR_PMR_FLAGS_SE 0x8UL 336 #define SQ_FR_PMR_FLAGS_INLINE 0x10UL 337 u8 access_cntl; 338 #define SQ_FR_PMR_ACCESS_CNTL_LOCAL_WRITE 0x1UL 339 #define SQ_FR_PMR_ACCESS_CNTL_REMOTE_READ 0x2UL 340 #define SQ_FR_PMR_ACCESS_CNTL_REMOTE_WRITE 0x4UL 341 #define SQ_FR_PMR_ACCESS_CNTL_REMOTE_ATOMIC 0x8UL 342 #define SQ_FR_PMR_ACCESS_CNTL_WINDOW_BIND 0x10UL 343 u8 zero_based_page_size_log; 344 #define SQ_FR_PMR_PAGE_SIZE_LOG_MASK 0x1fUL 345 #define SQ_FR_PMR_PAGE_SIZE_LOG_SFT 0 346 #define SQ_FR_PMR_PAGE_SIZE_LOG_PGSZ_4K 0x0UL 347 #define SQ_FR_PMR_PAGE_SIZE_LOG_PGSZ_8K 0x1UL 348 #define SQ_FR_PMR_PAGE_SIZE_LOG_PGSZ_64K 0x4UL 349 #define SQ_FR_PMR_PAGE_SIZE_LOG_PGSZ_256K 0x6UL 350 #define SQ_FR_PMR_PAGE_SIZE_LOG_PGSZ_1M 0x8UL 351 #define SQ_FR_PMR_PAGE_SIZE_LOG_PGSZ_2M 0x9UL 352 #define SQ_FR_PMR_PAGE_SIZE_LOG_PGSZ_4M 0xaUL 353 #define SQ_FR_PMR_PAGE_SIZE_LOG_PGSZ_1G 0x12UL 354 #define SQ_FR_PMR_ZERO_BASED 0x20UL 355 #define SQ_FR_PMR_RESERVED2_MASK 0xc0UL 356 #define SQ_FR_PMR_RESERVED2_SFT 6 357 __le32 l_key; 358 u8 length[5]; 359 u8 reserved8_1; 360 u8 reserved8_2; 361 u8 numlevels_pbl_page_size_log; 362 #define SQ_FR_PMR_PBL_PAGE_SIZE_LOG_MASK 0x1fUL 363 #define SQ_FR_PMR_PBL_PAGE_SIZE_LOG_SFT 0 364 #define SQ_FR_PMR_PBL_PAGE_SIZE_LOG_PGSZ_4K 0x0UL 365 #define SQ_FR_PMR_PBL_PAGE_SIZE_LOG_PGSZ_8K 0x1UL 366 #define SQ_FR_PMR_PBL_PAGE_SIZE_LOG_PGSZ_64K 0x4UL 367 #define SQ_FR_PMR_PBL_PAGE_SIZE_LOG_PGSZ_256K 0x6UL 368 #define SQ_FR_PMR_PBL_PAGE_SIZE_LOG_PGSZ_1M 0x8UL 369 #define SQ_FR_PMR_PBL_PAGE_SIZE_LOG_PGSZ_2M 0x9UL 370 #define SQ_FR_PMR_PBL_PAGE_SIZE_LOG_PGSZ_4M 0xaUL 371 #define SQ_FR_PMR_PBL_PAGE_SIZE_LOG_PGSZ_1G 0x12UL 372 #define SQ_FR_PMR_RESERVED1 0x20UL 373 #define SQ_FR_PMR_NUMLEVELS_MASK 0xc0UL 374 #define SQ_FR_PMR_NUMLEVELS_SFT 6 375 #define SQ_FR_PMR_NUMLEVELS_PHYSICAL (0x0UL << 6) 376 #define SQ_FR_PMR_NUMLEVELS_LAYER1 (0x1UL << 6) 377 #define SQ_FR_PMR_NUMLEVELS_LAYER2 (0x2UL << 6) 378 __le64 pblptr; 379 __le64 va; 380 __le32 data[24]; 381 }; 382 383 /* Bind SQ WQE (40 bytes) */ 384 struct sq_bind { 385 u8 wqe_type; 386 #define SQ_BIND_WQE_TYPE_BIND 0xeUL 387 u8 flags; 388 #define SQ_BIND_FLAGS_SIGNAL_COMP 0x1UL 389 #define SQ_BIND_FLAGS_RD_OR_ATOMIC_FENCE 0x2UL 390 #define SQ_BIND_FLAGS_UC_FENCE 0x4UL 391 #define SQ_BIND_FLAGS_SE 0x8UL 392 #define SQ_BIND_FLAGS_INLINE 0x10UL 393 u8 access_cntl; 394 #define SQ_BIND_ACCESS_CNTL_LOCAL_WRITE 0x1UL 395 #define SQ_BIND_ACCESS_CNTL_REMOTE_READ 0x2UL 396 #define SQ_BIND_ACCESS_CNTL_REMOTE_WRITE 0x4UL 397 #define SQ_BIND_ACCESS_CNTL_REMOTE_ATOMIC 0x8UL 398 #define SQ_BIND_ACCESS_CNTL_WINDOW_BIND 0x10UL 399 u8 reserved8_1; 400 u8 mw_type_zero_based; 401 #define SQ_BIND_ZERO_BASED 0x1UL 402 #define SQ_BIND_MW_TYPE 0x2UL 403 #define SQ_BIND_MW_TYPE_TYPE1 (0x0UL << 1) 404 #define SQ_BIND_MW_TYPE_TYPE2 (0x1UL << 1) 405 #define SQ_BIND_RESERVED6_MASK 0xfcUL 406 #define SQ_BIND_RESERVED6_SFT 2 407 u8 reserved8_2; 408 __le16 reserved16; 409 __le32 parent_l_key; 410 __le32 l_key; 411 __le64 va; 412 u8 length[5]; 413 u8 data_reserved24[99]; 414 #define SQ_BIND_RESERVED24_MASK 0xffffff00UL 415 #define SQ_BIND_RESERVED24_SFT 8 416 #define SQ_BIND_DATA_MASK 0xffffffffUL 417 #define SQ_BIND_DATA_SFT 0 418 }; 419 420 /* RQ/SRQ WQE Structures */ 421 /* RQ/SRQ WQE (40 bytes) */ 422 struct rq_wqe { 423 u8 wqe_type; 424 #define RQ_WQE_WQE_TYPE_RCV 0x80UL 425 u8 flags; 426 u8 wqe_size; 427 u8 reserved8; 428 __le32 reserved32; 429 __le32 wr_id[2]; 430 #define RQ_WQE_WR_ID_MASK 0xfffffUL 431 #define RQ_WQE_WR_ID_SFT 0 432 #define RQ_WQE_RESERVED44_MASK 0xfff00000UL 433 #define RQ_WQE_RESERVED44_SFT 20 434 __le32 reserved128[4]; 435 __le32 data[24]; 436 }; 437 438 /* CQ CQE Structures */ 439 /* Base CQE (32 bytes) */ 440 struct cq_base { 441 __le64 reserved64_1; 442 __le64 reserved64_2; 443 __le64 reserved64_3; 444 u8 cqe_type_toggle; 445 #define CQ_BASE_TOGGLE 0x1UL 446 #define CQ_BASE_CQE_TYPE_MASK 0x1eUL 447 #define CQ_BASE_CQE_TYPE_SFT 1 448 #define CQ_BASE_CQE_TYPE_REQ (0x0UL << 1) 449 #define CQ_BASE_CQE_TYPE_RES_RC (0x1UL << 1) 450 #define CQ_BASE_CQE_TYPE_RES_UD (0x2UL << 1) 451 #define CQ_BASE_CQE_TYPE_RES_RAWETH_QP1 (0x3UL << 1) 452 #define CQ_BASE_CQE_TYPE_TERMINAL (0xeUL << 1) 453 #define CQ_BASE_CQE_TYPE_CUT_OFF (0xfUL << 1) 454 #define CQ_BASE_RESERVED3_MASK 0xe0UL 455 #define CQ_BASE_RESERVED3_SFT 5 456 u8 status; 457 __le16 reserved16; 458 __le32 reserved32; 459 }; 460 461 /* Requester CQ CQE (32 bytes) */ 462 struct cq_req { 463 __le64 qp_handle; 464 __le16 sq_cons_idx; 465 __le16 reserved16_1; 466 __le32 reserved32_2; 467 __le64 reserved64; 468 u8 cqe_type_toggle; 469 #define CQ_REQ_TOGGLE 0x1UL 470 #define CQ_REQ_CQE_TYPE_MASK 0x1eUL 471 #define CQ_REQ_CQE_TYPE_SFT 1 472 #define CQ_REQ_CQE_TYPE_REQ (0x0UL << 1) 473 #define CQ_REQ_RESERVED3_MASK 0xe0UL 474 #define CQ_REQ_RESERVED3_SFT 5 475 u8 status; 476 #define CQ_REQ_STATUS_OK 0x0UL 477 #define CQ_REQ_STATUS_BAD_RESPONSE_ERR 0x1UL 478 #define CQ_REQ_STATUS_LOCAL_LENGTH_ERR 0x2UL 479 #define CQ_REQ_STATUS_LOCAL_QP_OPERATION_ERR 0x3UL 480 #define CQ_REQ_STATUS_LOCAL_PROTECTION_ERR 0x4UL 481 #define CQ_REQ_STATUS_MEMORY_MGT_OPERATION_ERR 0x5UL 482 #define CQ_REQ_STATUS_REMOTE_INVALID_REQUEST_ERR 0x6UL 483 #define CQ_REQ_STATUS_REMOTE_ACCESS_ERR 0x7UL 484 #define CQ_REQ_STATUS_REMOTE_OPERATION_ERR 0x8UL 485 #define CQ_REQ_STATUS_RNR_NAK_RETRY_CNT_ERR 0x9UL 486 #define CQ_REQ_STATUS_TRANSPORT_RETRY_CNT_ERR 0xaUL 487 #define CQ_REQ_STATUS_WORK_REQUEST_FLUSHED_ERR 0xbUL 488 __le16 reserved16_2; 489 __le32 reserved32_1; 490 }; 491 492 /* Responder RC CQE (32 bytes) */ 493 struct cq_res_rc { 494 __le32 length; 495 __le32 imm_data_or_inv_r_key; 496 __le64 qp_handle; 497 __le64 mr_handle; 498 u8 cqe_type_toggle; 499 #define CQ_RES_RC_TOGGLE 0x1UL 500 #define CQ_RES_RC_CQE_TYPE_MASK 0x1eUL 501 #define CQ_RES_RC_CQE_TYPE_SFT 1 502 #define CQ_RES_RC_CQE_TYPE_RES_RC (0x1UL << 1) 503 #define CQ_RES_RC_RESERVED3_MASK 0xe0UL 504 #define CQ_RES_RC_RESERVED3_SFT 5 505 u8 status; 506 #define CQ_RES_RC_STATUS_OK 0x0UL 507 #define CQ_RES_RC_STATUS_LOCAL_ACCESS_ERROR 0x1UL 508 #define CQ_RES_RC_STATUS_LOCAL_LENGTH_ERR 0x2UL 509 #define CQ_RES_RC_STATUS_LOCAL_PROTECTION_ERR 0x3UL 510 #define CQ_RES_RC_STATUS_LOCAL_QP_OPERATION_ERR 0x4UL 511 #define CQ_RES_RC_STATUS_MEMORY_MGT_OPERATION_ERR 0x5UL 512 #define CQ_RES_RC_STATUS_REMOTE_INVALID_REQUEST_ERR 0x6UL 513 #define CQ_RES_RC_STATUS_WORK_REQUEST_FLUSHED_ERR 0x7UL 514 #define CQ_RES_RC_STATUS_HW_FLUSH_ERR 0x8UL 515 __le16 flags; 516 #define CQ_RES_RC_FLAGS_SRQ 0x1UL 517 #define CQ_RES_RC_FLAGS_SRQ_RQ (0x0UL << 0) 518 #define CQ_RES_RC_FLAGS_SRQ_SRQ (0x1UL << 0) 519 #define CQ_RES_RC_FLAGS_SRQ_LAST CQ_RES_RC_FLAGS_SRQ_SRQ 520 #define CQ_RES_RC_FLAGS_IMM 0x2UL 521 #define CQ_RES_RC_FLAGS_INV 0x4UL 522 #define CQ_RES_RC_FLAGS_RDMA 0x8UL 523 #define CQ_RES_RC_FLAGS_RDMA_SEND (0x0UL << 3) 524 #define CQ_RES_RC_FLAGS_RDMA_RDMA_WRITE (0x1UL << 3) 525 #define CQ_RES_RC_FLAGS_RDMA_LAST CQ_RES_RC_FLAGS_RDMA_RDMA_WRITE 526 __le32 srq_or_rq_wr_id; 527 #define CQ_RES_RC_SRQ_OR_RQ_WR_ID_MASK 0xfffffUL 528 #define CQ_RES_RC_SRQ_OR_RQ_WR_ID_SFT 0 529 #define CQ_RES_RC_RESERVED12_MASK 0xfff00000UL 530 #define CQ_RES_RC_RESERVED12_SFT 20 531 }; 532 533 /* Responder UD CQE (32 bytes) */ 534 struct cq_res_ud { 535 __le16 length; 536 #define CQ_RES_UD_LENGTH_MASK 0x3fffUL 537 #define CQ_RES_UD_LENGTH_SFT 0 538 __le16 cfa_metadata; 539 #define CQ_RES_UD_CFA_METADATA_VID_MASK 0xfffUL 540 #define CQ_RES_UD_CFA_METADATA_VID_SFT 0 541 #define CQ_RES_UD_CFA_METADATA_DE 0x1000UL 542 #define CQ_RES_UD_CFA_METADATA_PRI_MASK 0xe000UL 543 #define CQ_RES_UD_CFA_METADATA_PRI_SFT 13 544 __le32 imm_data; 545 __le64 qp_handle; 546 __le16 src_mac[3]; 547 __le16 src_qp_low; 548 u8 cqe_type_toggle; 549 #define CQ_RES_UD_TOGGLE 0x1UL 550 #define CQ_RES_UD_CQE_TYPE_MASK 0x1eUL 551 #define CQ_RES_UD_CQE_TYPE_SFT 1 552 #define CQ_RES_UD_CQE_TYPE_RES_UD (0x2UL << 1) 553 u8 status; 554 #define CQ_RES_UD_STATUS_OK 0x0UL 555 #define CQ_RES_UD_STATUS_LOCAL_ACCESS_ERROR 0x1UL 556 #define CQ_RES_UD_STATUS_HW_LOCAL_LENGTH_ERR 0x2UL 557 #define CQ_RES_UD_STATUS_LOCAL_PROTECTION_ERR 0x3UL 558 #define CQ_RES_UD_STATUS_LOCAL_QP_OPERATION_ERR 0x4UL 559 #define CQ_RES_UD_STATUS_MEMORY_MGT_OPERATION_ERR 0x5UL 560 #define CQ_RES_UD_STATUS_WORK_REQUEST_FLUSHED_ERR 0x7UL 561 #define CQ_RES_UD_STATUS_HW_FLUSH_ERR 0x8UL 562 __le16 flags; 563 #define CQ_RES_UD_FLAGS_SRQ 0x1UL 564 #define CQ_RES_UD_FLAGS_SRQ_RQ (0x0UL << 0) 565 #define CQ_RES_UD_FLAGS_SRQ_SRQ (0x1UL << 0) 566 #define CQ_RES_UD_FLAGS_SRQ_LAST CQ_RES_UD_FLAGS_SRQ_SRQ 567 #define CQ_RES_UD_FLAGS_IMM 0x2UL 568 #define CQ_RES_UD_FLAGS_UNUSED_MASK 0xcUL 569 #define CQ_RES_UD_FLAGS_UNUSED_SFT 2 570 #define CQ_RES_UD_FLAGS_ROCE_IP_VER_MASK 0x30UL 571 #define CQ_RES_UD_FLAGS_ROCE_IP_VER_SFT 4 572 #define CQ_RES_UD_FLAGS_ROCE_IP_VER_V1 (0x0UL << 4) 573 #define CQ_RES_UD_FLAGS_ROCE_IP_VER_V2IPV4 (0x2UL << 4) 574 #define CQ_RES_UD_FLAGS_ROCE_IP_VER_V2IPV6 (0x3UL << 4) 575 #define CQ_RES_UD_FLAGS_ROCE_IP_VER_LAST \ 576 CQ_RES_UD_FLAGS_ROCE_IP_VER_V2IPV6 577 #define CQ_RES_UD_FLAGS_META_FORMAT_MASK 0x3c0UL 578 #define CQ_RES_UD_FLAGS_META_FORMAT_SFT 6 579 #define CQ_RES_UD_FLAGS_META_FORMAT_NONE (0x0UL << 6) 580 #define CQ_RES_UD_FLAGS_META_FORMAT_VLAN (0x1UL << 6) 581 #define CQ_RES_UD_FLAGS_META_FORMAT_TUNNEL_ID (0x2UL << 6) 582 #define CQ_RES_UD_FLAGS_META_FORMAT_CHDR_DATA (0x3UL << 6) 583 #define CQ_RES_UD_FLAGS_META_FORMAT_HDR_OFFSET (0x4UL << 6) 584 #define CQ_RES_UD_FLAGS_META_FORMAT_LAST \ 585 CQ_RES_UD_FLAGS_META_FORMAT_HDR_OFFSET 586 #define CQ_RES_UD_FLAGS_EXT_META_FORMAT_MASK 0xc00UL 587 #define CQ_RES_UD_FLAGS_EXT_META_FORMAT_SFT 10 588 589 __le32 src_qp_high_srq_or_rq_wr_id; 590 #define CQ_RES_UD_SRQ_OR_RQ_WR_ID_MASK 0xfffffUL 591 #define CQ_RES_UD_SRQ_OR_RQ_WR_ID_SFT 0 592 #define CQ_RES_UD_SRC_QP_HIGH_MASK 0xff000000UL 593 #define CQ_RES_UD_SRC_QP_HIGH_SFT 24 594 }; 595 596 /* Responder RawEth and QP1 CQE (32 bytes) */ 597 struct cq_res_raweth_qp1 { 598 __le16 length; 599 #define CQ_RES_RAWETH_QP1_LENGTH_MASK 0x3fffUL 600 #define CQ_RES_RAWETH_QP1_LENGTH_SFT 0 601 #define CQ_RES_RAWETH_QP1_RESERVED2_MASK 0xc000UL 602 #define CQ_RES_RAWETH_QP1_RESERVED2_SFT 14 603 __le16 raweth_qp1_flags; 604 #define CQ_RES_RAWETH_QP1_RAWETH_QP1_FLAGS_ERROR 0x1UL 605 #define CQ_RES_RAWETH_QP1_RAWETH_QP1_FLAGS_RESERVED5_1_MASK 0x3eUL 606 #define CQ_RES_RAWETH_QP1_RAWETH_QP1_FLAGS_RESERVED5_1_SFT 1 607 #define CQ_RES_RAWETH_QP1_RAWETH_QP1_FLAGS_ITYPE_MASK 0x3c0UL 608 #define CQ_RES_RAWETH_QP1_RAWETH_QP1_FLAGS_ITYPE_SFT 6 609 #define CQ_RES_RAWETH_QP1_RAWETH_QP1_FLAGS_ITYPE_NOT_KNOWN (0x0UL << 6) 610 #define CQ_RES_RAWETH_QP1_RAWETH_QP1_FLAGS_ITYPE_IP (0x1UL << 6) 611 #define CQ_RES_RAWETH_QP1_RAWETH_QP1_FLAGS_ITYPE_TCP (0x2UL << 6) 612 #define CQ_RES_RAWETH_QP1_RAWETH_QP1_FLAGS_ITYPE_UDP (0x3UL << 6) 613 #define CQ_RES_RAWETH_QP1_RAWETH_QP1_FLAGS_ITYPE_FCOE (0x4UL << 6) 614 #define CQ_RES_RAWETH_QP1_RAWETH_QP1_FLAGS_ITYPE_ROCE (0x5UL << 6) 615 #define CQ_RES_RAWETH_QP1_RAWETH_QP1_FLAGS_ITYPE_ICMP (0x7UL << 6) 616 #define CQ_RES_RAWETH_QP1_RAWETH_QP1_FLAGS_ITYPE_PTP_WO_TIMESTAMP \ 617 (0x8UL << 6) 618 #define CQ_RES_RAWETH_QP1_RAWETH_QP1_FLAGS_ITYPE_PTP_W_TIMESTAMP \ 619 (0x9UL << 6) 620 #define CQ_RES_RAWETH_QP1_RAWETH_QP1_FLAGS_ITYPE_LAST \ 621 CQ_RES_RAWETH_QP1_RAWETH_QP1_FLAGS_ITYPE_PTP_W_TIMESTAMP 622 #define CQ_RES_RAWETH_QP1_RAWETH_QP1_FLAGS_MASK 0x3ffUL 623 #define CQ_RES_RAWETH_QP1_RAWETH_QP1_FLAGS_SFT 0 624 #define CQ_RES_RAWETH_QP1_RESERVED6_MASK 0xfc00UL 625 #define CQ_RES_RAWETH_QP1_RESERVED6_SFT 10 626 __le16 raweth_qp1_errors; 627 #define CQ_RES_RAWETH_QP1_RAWETH_QP1_ERRORS_RESERVED4_MASK 0xfUL 628 #define CQ_RES_RAWETH_QP1_RAWETH_QP1_ERRORS_RESERVED4_SFT 0 629 #define CQ_RES_RAWETH_QP1_RAWETH_QP1_ERRORS_IP_CS_ERROR 0x10UL 630 #define CQ_RES_RAWETH_QP1_RAWETH_QP1_ERRORS_L4_CS_ERROR 0x20UL 631 #define CQ_RES_RAWETH_QP1_RAWETH_QP1_ERRORS_T_IP_CS_ERROR 0x40UL 632 #define CQ_RES_RAWETH_QP1_RAWETH_QP1_ERRORS_T_L4_CS_ERROR 0x80UL 633 #define CQ_RES_RAWETH_QP1_RAWETH_QP1_ERRORS_CRC_ERROR 0x100UL 634 #define CQ_RES_RAWETH_QP1_RAWETH_QP1_ERRORS_T_PKT_ERROR_MASK 0xe00UL 635 #define CQ_RES_RAWETH_QP1_RAWETH_QP1_ERRORS_T_PKT_ERROR_SFT 9 636 #define CQ_RES_RAWETH_QP1_RAWETH_QP1_ERRORS_T_PKT_ERROR_NO_ERROR \ 637 (0x0UL << 9) 638 #define \ 639 CQ_RES_RAWETH_QP1_RAWETH_QP1_ERRORS_T_PKT_ERROR_T_L3_BAD_VERSION \ 640 (0x1UL << 9) 641 #define \ 642 CQ_RES_RAWETH_QP1_RAWETH_QP1_ERRORS_T_PKT_ERROR_T_L3_BAD_HDR_LEN \ 643 (0x2UL << 9) 644 #define \ 645 CQ_RES_RAWETH_QP1_RAWETH_QP1_ERRORS_T_PKT_ERROR_TUNNEL_TOTAL_ERROR \ 646 (0x3UL << 9) 647 #define \ 648 CQ_RES_RAWETH_QP1_RAWETH_QP1_ERRORS_T_PKT_ERROR_T_IP_TOTAL_ERROR \ 649 (0x4UL << 9) 650 #define \ 651 CQ_RES_RAWETH_QP1_RAWETH_QP1_ERRORS_T_PKT_ERROR_T_UDP_TOTAL_ERROR \ 652 (0x5UL << 9) 653 #define \ 654 CQ_RES_RAWETH_QP1_RAWETH_QP1_ERRORS_T_PKT_ERROR_T_L3_BAD_TTL \ 655 (0x6UL << 9) 656 #define CQ_RES_RAWETH_QP1_RAWETH_QP1_ERRORS_T_PKT_ERROR_LAST \ 657 CQ_RES_RAWETH_QP1_RAWETH_QP1_ERRORS_T_PKT_ERROR_T_L3_BAD_TTL 658 #define CQ_RES_RAWETH_QP1_RAWETH_QP1_ERRORS_PKT_ERROR_MASK 0xf000UL 659 #define CQ_RES_RAWETH_QP1_RAWETH_QP1_ERRORS_PKT_ERROR_SFT 12 660 #define CQ_RES_RAWETH_QP1_RAWETH_QP1_ERRORS_PKT_ERROR_NO_ERROR \ 661 (0x0UL << 12) 662 #define CQ_RES_RAWETH_QP1_RAWETH_QP1_ERRORS_PKT_ERROR_L3_BAD_VERSION \ 663 (0x1UL << 12) 664 #define CQ_RES_RAWETH_QP1_RAWETH_QP1_ERRORS_PKT_ERROR_L3_BAD_HDR_LEN \ 665 (0x2UL << 12) 666 #define CQ_RES_RAWETH_QP1_RAWETH_QP1_ERRORS_PKT_ERROR_L3_BAD_TTL \ 667 (0x3UL << 12) 668 #define CQ_RES_RAWETH_QP1_RAWETH_QP1_ERRORS_PKT_ERROR_IP_TOTAL_ERROR \ 669 (0x4UL << 12) 670 #define CQ_RES_RAWETH_QP1_RAWETH_QP1_ERRORS_PKT_ERROR_UDP_TOTAL_ERROR \ 671 (0x5UL << 12) 672 #define CQ_RES_RAWETH_QP1_RAWETH_QP1_ERRORS_PKT_ERROR_L4_BAD_HDR_LEN \ 673 (0x6UL << 12) 674 #define \ 675 CQ_RES_RAWETH_QP1_RAWETH_QP1_ERRORS_PKT_ERROR_L4_BAD_HDR_LEN_TOO_SMALL\ 676 (0x7UL << 12) 677 #define CQ_RES_RAWETH_QP1_RAWETH_QP1_ERRORS_PKT_ERROR_L4_BAD_OPT_LEN \ 678 (0x8UL << 12) 679 #define CQ_RES_RAWETH_QP1_RAWETH_QP1_ERRORS_PKT_ERROR_LAST \ 680 CQ_RES_RAWETH_QP1_RAWETH_QP1_ERRORS_PKT_ERROR_L4_BAD_OPT_LEN 681 __le16 raweth_qp1_cfa_code; 682 __le64 qp_handle; 683 __le32 raweth_qp1_flags2; 684 #define CQ_RES_RAWETH_QP1_RAWETH_QP1_FLAGS2_IP_CS_CALC 0x1UL 685 #define CQ_RES_RAWETH_QP1_RAWETH_QP1_FLAGS2_L4_CS_CALC 0x2UL 686 #define CQ_RES_RAWETH_QP1_RAWETH_QP1_FLAGS2_T_IP_CS_CALC 0x4UL 687 #define CQ_RES_RAWETH_QP1_RAWETH_QP1_FLAGS2_T_L4_CS_CALC 0x8UL 688 #define CQ_RES_RAWETH_QP1_RAWETH_QP1_FLAGS2_META_FORMAT_MASK 0xf0UL 689 #define CQ_RES_RAWETH_QP1_RAWETH_QP1_FLAGS2_META_FORMAT_SFT 4 690 #define CQ_RES_RAWETH_QP1_RAWETH_QP1_FLAGS2_META_FORMAT_NONE \ 691 (0x0UL << 4) 692 #define CQ_RES_RAWETH_QP1_RAWETH_QP1_FLAGS2_META_FORMAT_VLAN \ 693 (0x1UL << 4) 694 #define CQ_RES_RAWETH_QP1_RAWETH_QP1_FLAGS2_META_FORMAT_LAST\ 695 CQ_RES_RAWETH_QP1_RAWETH_QP1_FLAGS2_META_FORMAT_VLAN 696 #define CQ_RES_RAWETH_QP1_RAWETH_QP1_FLAGS2_IP_TYPE 0x100UL 697 __le32 raweth_qp1_metadata; 698 #define CQ_RES_RAWETH_QP1_RAWETH_QP1_METADATA_VID_MASK 0xfffUL 699 #define CQ_RES_RAWETH_QP1_RAWETH_QP1_METADATA_VID_SFT 0 700 #define CQ_RES_RAWETH_QP1_RAWETH_QP1_METADATA_DE 0x1000UL 701 #define CQ_RES_RAWETH_QP1_RAWETH_QP1_METADATA_PRI_MASK 0xe000UL 702 #define CQ_RES_RAWETH_QP1_RAWETH_QP1_METADATA_PRI_SFT 13 703 #define CQ_RES_RAWETH_QP1_RAWETH_QP1_METADATA_TPID_MASK 0xffff0000UL 704 #define CQ_RES_RAWETH_QP1_RAWETH_QP1_METADATA_TPID_SFT 16 705 u8 cqe_type_toggle; 706 #define CQ_RES_RAWETH_QP1_TOGGLE 0x1UL 707 #define CQ_RES_RAWETH_QP1_CQE_TYPE_MASK 0x1eUL 708 #define CQ_RES_RAWETH_QP1_CQE_TYPE_SFT 1 709 #define CQ_RES_RAWETH_QP1_CQE_TYPE_RES_RAWETH_QP1 (0x3UL << 1) 710 #define CQ_RES_RAWETH_QP1_RESERVED3_MASK 0xe0UL 711 #define CQ_RES_RAWETH_QP1_RESERVED3_SFT 5 712 u8 status; 713 #define CQ_RES_RAWETH_QP1_STATUS_OK 0x0UL 714 #define CQ_RES_RAWETH_QP1_STATUS_LOCAL_ACCESS_ERROR 0x1UL 715 #define CQ_RES_RAWETH_QP1_STATUS_HW_LOCAL_LENGTH_ERR 0x2UL 716 #define CQ_RES_RAWETH_QP1_STATUS_LOCAL_PROTECTION_ERR 0x3UL 717 #define CQ_RES_RAWETH_QP1_STATUS_LOCAL_QP_OPERATION_ERR 0x4UL 718 #define CQ_RES_RAWETH_QP1_STATUS_MEMORY_MGT_OPERATION_ERR 0x5UL 719 #define CQ_RES_RAWETH_QP1_STATUS_WORK_REQUEST_FLUSHED_ERR 0x7UL 720 #define CQ_RES_RAWETH_QP1_STATUS_HW_FLUSH_ERR 0x8UL 721 __le16 flags; 722 #define CQ_RES_RAWETH_QP1_FLAGS_SRQ 0x1UL 723 #define CQ_RES_RAWETH_QP1_FLAGS_SRQ_RQ 0x0UL 724 #define CQ_RES_RAWETH_QP1_FLAGS_SRQ_SRQ 0x1UL 725 #define CQ_RES_RAWETH_QP1_FLAGS_SRQ_LAST \ 726 CQ_RES_RAWETH_QP1_FLAGS_SRQ_SRQ 727 __le32 raweth_qp1_payload_offset_srq_or_rq_wr_id; 728 #define CQ_RES_RAWETH_QP1_SRQ_OR_RQ_WR_ID_MASK 0xfffffUL 729 #define CQ_RES_RAWETH_QP1_SRQ_OR_RQ_WR_ID_SFT 0 730 #define CQ_RES_RAWETH_QP1_RESERVED4_MASK 0xf00000UL 731 #define CQ_RES_RAWETH_QP1_RESERVED4_SFT 20 732 #define CQ_RES_RAWETH_QP1_RAWETH_QP1_PAYLOAD_OFFSET_MASK 0xff000000UL 733 #define CQ_RES_RAWETH_QP1_RAWETH_QP1_PAYLOAD_OFFSET_SFT 24 734 }; 735 736 /* Terminal CQE (32 bytes) */ 737 struct cq_terminal { 738 __le64 qp_handle; 739 __le16 sq_cons_idx; 740 __le16 rq_cons_idx; 741 __le32 reserved32_1; 742 __le64 reserved64_3; 743 u8 cqe_type_toggle; 744 #define CQ_TERMINAL_TOGGLE 0x1UL 745 #define CQ_TERMINAL_CQE_TYPE_MASK 0x1eUL 746 #define CQ_TERMINAL_CQE_TYPE_SFT 1 747 #define CQ_TERMINAL_CQE_TYPE_TERMINAL (0xeUL << 1) 748 #define CQ_TERMINAL_RESERVED3_MASK 0xe0UL 749 #define CQ_TERMINAL_RESERVED3_SFT 5 750 u8 status; 751 #define CQ_TERMINAL_STATUS_OK 0x0UL 752 __le16 reserved16; 753 __le32 reserved32_2; 754 }; 755 756 /* Cutoff CQE (32 bytes) */ 757 struct cq_cutoff { 758 __le64 reserved64_1; 759 __le64 reserved64_2; 760 __le64 reserved64_3; 761 u8 cqe_type_toggle; 762 #define CQ_CUTOFF_TOGGLE 0x1UL 763 #define CQ_CUTOFF_CQE_TYPE_MASK 0x1eUL 764 #define CQ_CUTOFF_CQE_TYPE_SFT 1 765 #define CQ_CUTOFF_CQE_TYPE_CUT_OFF (0xfUL << 1) 766 #define CQ_CUTOFF_RESERVED3_MASK 0xe0UL 767 #define CQ_CUTOFF_RESERVED3_SFT 5 768 u8 status; 769 #define CQ_CUTOFF_STATUS_OK 0x0UL 770 __le16 reserved16; 771 __le32 reserved32; 772 }; 773 774 /* Notification Queue (NQ) Structures */ 775 /* Base NQ Record (16 bytes) */ 776 struct nq_base { 777 __le16 info10_type; 778 #define NQ_BASE_TYPE_MASK 0x3fUL 779 #define NQ_BASE_TYPE_SFT 0 780 #define NQ_BASE_TYPE_CQ_NOTIFICATION 0x30UL 781 #define NQ_BASE_TYPE_SRQ_EVENT 0x32UL 782 #define NQ_BASE_TYPE_DBQ_EVENT 0x34UL 783 #define NQ_BASE_TYPE_QP_EVENT 0x38UL 784 #define NQ_BASE_TYPE_FUNC_EVENT 0x3aUL 785 #define NQ_BASE_INFO10_MASK 0xffc0UL 786 #define NQ_BASE_INFO10_SFT 6 787 __le16 info16; 788 __le32 info32; 789 __le32 info63_v[2]; 790 #define NQ_BASE_V 0x1UL 791 #define NQ_BASE_INFO63_MASK 0xfffffffeUL 792 #define NQ_BASE_INFO63_SFT 1 793 }; 794 795 /* Completion Queue Notification (16 bytes) */ 796 struct nq_cn { 797 __le16 type; 798 #define NQ_CN_TYPE_MASK 0x3fUL 799 #define NQ_CN_TYPE_SFT 0 800 #define NQ_CN_TYPE_CQ_NOTIFICATION 0x30UL 801 #define NQ_CN_RESERVED9_MASK 0xffc0UL 802 #define NQ_CN_RESERVED9_SFT 6 803 __le16 reserved16; 804 __le32 cq_handle_low; 805 __le32 v; 806 #define NQ_CN_V 0x1UL 807 #define NQ_CN_RESERVED31_MASK 0xfffffffeUL 808 #define NQ_CN_RESERVED31_SFT 1 809 __le32 cq_handle_high; 810 }; 811 812 /* SRQ Event Notification (16 bytes) */ 813 struct nq_srq_event { 814 u8 type; 815 #define NQ_SRQ_EVENT_TYPE_MASK 0x3fUL 816 #define NQ_SRQ_EVENT_TYPE_SFT 0 817 #define NQ_SRQ_EVENT_TYPE_SRQ_EVENT 0x32UL 818 #define NQ_SRQ_EVENT_RESERVED1_MASK 0xc0UL 819 #define NQ_SRQ_EVENT_RESERVED1_SFT 6 820 u8 event; 821 #define NQ_SRQ_EVENT_EVENT_SRQ_THRESHOLD_EVENT 0x1UL 822 __le16 reserved16; 823 __le32 srq_handle_low; 824 __le32 v; 825 #define NQ_SRQ_EVENT_V 0x1UL 826 #define NQ_SRQ_EVENT_RESERVED31_MASK 0xfffffffeUL 827 #define NQ_SRQ_EVENT_RESERVED31_SFT 1 828 __le32 srq_handle_high; 829 }; 830 831 /* DBQ Async Event Notification (16 bytes) */ 832 struct nq_dbq_event { 833 u8 type; 834 #define NQ_DBQ_EVENT_TYPE_MASK 0x3fUL 835 #define NQ_DBQ_EVENT_TYPE_SFT 0 836 #define NQ_DBQ_EVENT_TYPE_DBQ_EVENT 0x34UL 837 #define NQ_DBQ_EVENT_RESERVED1_MASK 0xc0UL 838 #define NQ_DBQ_EVENT_RESERVED1_SFT 6 839 u8 event; 840 #define NQ_DBQ_EVENT_EVENT_DBQ_THRESHOLD_EVENT 0x1UL 841 __le16 db_pfid; 842 #define NQ_DBQ_EVENT_DB_PFID_MASK 0xfUL 843 #define NQ_DBQ_EVENT_DB_PFID_SFT 0 844 #define NQ_DBQ_EVENT_RESERVED12_MASK 0xfff0UL 845 #define NQ_DBQ_EVENT_RESERVED12_SFT 4 846 __le32 db_dpi; 847 #define NQ_DBQ_EVENT_DB_DPI_MASK 0xfffffUL 848 #define NQ_DBQ_EVENT_DB_DPI_SFT 0 849 #define NQ_DBQ_EVENT_RESERVED12_2_MASK 0xfff00000UL 850 #define NQ_DBQ_EVENT_RESERVED12_2_SFT 20 851 __le32 v; 852 #define NQ_DBQ_EVENT_V 0x1UL 853 #define NQ_DBQ_EVENT_RESERVED32_MASK 0xfffffffeUL 854 #define NQ_DBQ_EVENT_RESERVED32_SFT 1 855 __le32 db_type_db_xid; 856 #define NQ_DBQ_EVENT_DB_XID_MASK 0xfffffUL 857 #define NQ_DBQ_EVENT_DB_XID_SFT 0 858 #define NQ_DBQ_EVENT_RESERVED8_MASK 0xff00000UL 859 #define NQ_DBQ_EVENT_RESERVED8_SFT 20 860 #define NQ_DBQ_EVENT_DB_TYPE_MASK 0xf0000000UL 861 #define NQ_DBQ_EVENT_DB_TYPE_SFT 28 862 }; 863 864 /* Read Request/Response Queue Structures */ 865 /* Input Read Request Queue (IRRQ) Message (32 bytes) */ 866 struct xrrq_irrq { 867 __le16 credits_type; 868 #define XRRQ_IRRQ_TYPE 0x1UL 869 #define XRRQ_IRRQ_TYPE_READ_REQ 0x0UL 870 #define XRRQ_IRRQ_TYPE_ATOMIC_REQ 0x1UL 871 #define XRRQ_IRRQ_RESERVED10_MASK 0x7feUL 872 #define XRRQ_IRRQ_RESERVED10_SFT 1 873 #define XRRQ_IRRQ_CREDITS_MASK 0xf800UL 874 #define XRRQ_IRRQ_CREDITS_SFT 11 875 __le16 reserved16; 876 __le32 reserved32; 877 __le32 psn; 878 #define XRRQ_IRRQ_PSN_MASK 0xffffffUL 879 #define XRRQ_IRRQ_PSN_SFT 0 880 #define XRRQ_IRRQ_RESERVED8_1_MASK 0xff000000UL 881 #define XRRQ_IRRQ_RESERVED8_1_SFT 24 882 __le32 msn; 883 #define XRRQ_IRRQ_MSN_MASK 0xffffffUL 884 #define XRRQ_IRRQ_MSN_SFT 0 885 #define XRRQ_IRRQ_RESERVED8_2_MASK 0xff000000UL 886 #define XRRQ_IRRQ_RESERVED8_2_SFT 24 887 __le64 va_or_atomic_result; 888 __le32 rdma_r_key; 889 __le32 length; 890 }; 891 892 /* Output Read Request Queue (ORRQ) Message (32 bytes) */ 893 struct xrrq_orrq { 894 __le16 num_sges_type; 895 #define XRRQ_ORRQ_TYPE 0x1UL 896 #define XRRQ_ORRQ_TYPE_READ_REQ 0x0UL 897 #define XRRQ_ORRQ_TYPE_ATOMIC_REQ 0x1UL 898 #define XRRQ_ORRQ_RESERVED10_MASK 0x7feUL 899 #define XRRQ_ORRQ_RESERVED10_SFT 1 900 #define XRRQ_ORRQ_NUM_SGES_MASK 0xf800UL 901 #define XRRQ_ORRQ_NUM_SGES_SFT 11 902 __le16 reserved16; 903 __le32 length; 904 __le32 psn; 905 #define XRRQ_ORRQ_PSN_MASK 0xffffffUL 906 #define XRRQ_ORRQ_PSN_SFT 0 907 #define XRRQ_ORRQ_RESERVED8_1_MASK 0xff000000UL 908 #define XRRQ_ORRQ_RESERVED8_1_SFT 24 909 __le32 end_psn; 910 #define XRRQ_ORRQ_END_PSN_MASK 0xffffffUL 911 #define XRRQ_ORRQ_END_PSN_SFT 0 912 #define XRRQ_ORRQ_RESERVED8_2_MASK 0xff000000UL 913 #define XRRQ_ORRQ_RESERVED8_2_SFT 24 914 __le64 first_sge_phy_or_sing_sge_va; 915 __le32 single_sge_l_key; 916 __le32 single_sge_size; 917 }; 918 919 /* Page Buffer List Memory Structures (PBL) */ 920 /* Page Table Entry (PTE) (8 bytes) */ 921 struct ptu_pte { 922 __le32 page_next_to_last_last_valid[2]; 923 #define PTU_PTE_VALID 0x1UL 924 #define PTU_PTE_LAST 0x2UL 925 #define PTU_PTE_NEXT_TO_LAST 0x4UL 926 #define PTU_PTE_PAGE_MASK 0xfffff000UL 927 #define PTU_PTE_PAGE_SFT 12 928 }; 929 930 /* Page Directory Entry (PDE) (8 bytes) */ 931 struct ptu_pde { 932 __le32 page_valid[2]; 933 #define PTU_PDE_VALID 0x1UL 934 #define PTU_PDE_PAGE_MASK 0xfffff000UL 935 #define PTU_PDE_PAGE_SFT 12 936 }; 937 938 /* RoCE Fastpath Host Structures */ 939 /* Command Queue (CMDQ) Interface */ 940 /* Init CMDQ (16 bytes) */ 941 struct cmdq_init { 942 __le64 cmdq_pbl; 943 __le16 cmdq_size_cmdq_lvl; 944 #define CMDQ_INIT_CMDQ_LVL_MASK 0x3UL 945 #define CMDQ_INIT_CMDQ_LVL_SFT 0 946 #define CMDQ_INIT_CMDQ_SIZE_MASK 0xfffcUL 947 #define CMDQ_INIT_CMDQ_SIZE_SFT 2 948 __le16 creq_ring_id; 949 __le32 prod_idx; 950 }; 951 952 /* Update CMDQ producer index (16 bytes) */ 953 struct cmdq_update { 954 __le64 reserved64; 955 __le32 reserved32; 956 __le32 prod_idx; 957 }; 958 959 /* CMDQ common header structure (16 bytes) */ 960 struct cmdq_base { 961 u8 opcode; 962 #define CMDQ_BASE_OPCODE_CREATE_QP 0x1UL 963 #define CMDQ_BASE_OPCODE_DESTROY_QP 0x2UL 964 #define CMDQ_BASE_OPCODE_MODIFY_QP 0x3UL 965 #define CMDQ_BASE_OPCODE_QUERY_QP 0x4UL 966 #define CMDQ_BASE_OPCODE_CREATE_SRQ 0x5UL 967 #define CMDQ_BASE_OPCODE_DESTROY_SRQ 0x6UL 968 #define CMDQ_BASE_OPCODE_QUERY_SRQ 0x8UL 969 #define CMDQ_BASE_OPCODE_CREATE_CQ 0x9UL 970 #define CMDQ_BASE_OPCODE_DESTROY_CQ 0xaUL 971 #define CMDQ_BASE_OPCODE_RESIZE_CQ 0xcUL 972 #define CMDQ_BASE_OPCODE_ALLOCATE_MRW 0xdUL 973 #define CMDQ_BASE_OPCODE_DEALLOCATE_KEY 0xeUL 974 #define CMDQ_BASE_OPCODE_REGISTER_MR 0xfUL 975 #define CMDQ_BASE_OPCODE_DEREGISTER_MR 0x10UL 976 #define CMDQ_BASE_OPCODE_ADD_GID 0x11UL 977 #define CMDQ_BASE_OPCODE_DELETE_GID 0x12UL 978 #define CMDQ_BASE_OPCODE_MODIFY_GID 0x17UL 979 #define CMDQ_BASE_OPCODE_QUERY_GID 0x18UL 980 #define CMDQ_BASE_OPCODE_CREATE_QP1 0x13UL 981 #define CMDQ_BASE_OPCODE_DESTROY_QP1 0x14UL 982 #define CMDQ_BASE_OPCODE_CREATE_AH 0x15UL 983 #define CMDQ_BASE_OPCODE_DESTROY_AH 0x16UL 984 #define CMDQ_BASE_OPCODE_INITIALIZE_FW 0x80UL 985 #define CMDQ_BASE_OPCODE_DEINITIALIZE_FW 0x81UL 986 #define CMDQ_BASE_OPCODE_STOP_FUNC 0x82UL 987 #define CMDQ_BASE_OPCODE_QUERY_FUNC 0x83UL 988 #define CMDQ_BASE_OPCODE_SET_FUNC_RESOURCES 0x84UL 989 #define CMDQ_BASE_OPCODE_READ_CONTEXT 0x85UL 990 #define CMDQ_BASE_OPCODE_VF_BACKCHANNEL_REQUEST 0x86UL 991 #define CMDQ_BASE_OPCODE_READ_VF_MEMORY 0x87UL 992 #define CMDQ_BASE_OPCODE_COMPLETE_VF_REQUEST 0x88UL 993 #define CMDQ_BASE_OPCODE_EXTEND_CONTEXT_ARRRAY 0x89UL 994 #define CMDQ_BASE_OPCODE_MAP_TC_TO_COS 0x8aUL 995 #define CMDQ_BASE_OPCODE_QUERY_VERSION 0x8bUL 996 #define CMDQ_BASE_OPCODE_MODIFY_CC 0x8cUL 997 #define CMDQ_BASE_OPCODE_QUERY_CC 0x8dUL 998 #define CMDQ_BASE_OPCODE_QUERY_ROCE_STATS 0x8eUL 999 u8 cmd_size; 1000 __le16 flags; 1001 __le16 cookie; 1002 u8 resp_size; 1003 u8 reserved8; 1004 __le64 resp_addr; 1005 }; 1006 1007 /* Create QP command (96 bytes) */ 1008 struct cmdq_create_qp { 1009 u8 opcode; 1010 #define CMDQ_CREATE_QP_OPCODE_CREATE_QP 0x1UL 1011 u8 cmd_size; 1012 __le16 flags; 1013 __le16 cookie; 1014 u8 resp_size; 1015 u8 reserved8; 1016 __le64 resp_addr; 1017 __le64 qp_handle; 1018 __le32 qp_flags; 1019 #define CMDQ_CREATE_QP_QP_FLAGS_SRQ_USED 0x1UL 1020 #define CMDQ_CREATE_QP_QP_FLAGS_FORCE_COMPLETION 0x2UL 1021 #define CMDQ_CREATE_QP_QP_FLAGS_RESERVED_LKEY_ENABLE 0x4UL 1022 #define CMDQ_CREATE_QP_QP_FLAGS_FR_PMR_ENABLED 0x8UL 1023 u8 type; 1024 #define CMDQ_CREATE_QP_TYPE_RC 0x2UL 1025 #define CMDQ_CREATE_QP_TYPE_UD 0x4UL 1026 #define CMDQ_CREATE_QP_TYPE_RAW_ETHERTYPE 0x6UL 1027 #define CMDQ_CREATE_QP_TYPE_GSI 0x7UL 1028 u8 sq_pg_size_sq_lvl; 1029 #define CMDQ_CREATE_QP_SQ_LVL_MASK 0xfUL 1030 #define CMDQ_CREATE_QP_SQ_LVL_SFT 0 1031 #define CMDQ_CREATE_QP_SQ_LVL_LVL_0 0x0UL 1032 #define CMDQ_CREATE_QP_SQ_LVL_LVL_1 0x1UL 1033 #define CMDQ_CREATE_QP_SQ_LVL_LVL_2 0x2UL 1034 #define CMDQ_CREATE_QP_SQ_PG_SIZE_MASK 0xf0UL 1035 #define CMDQ_CREATE_QP_SQ_PG_SIZE_SFT 4 1036 #define CMDQ_CREATE_QP_SQ_PG_SIZE_PG_4K (0x0UL << 4) 1037 #define CMDQ_CREATE_QP_SQ_PG_SIZE_PG_8K (0x1UL << 4) 1038 #define CMDQ_CREATE_QP_SQ_PG_SIZE_PG_64K (0x2UL << 4) 1039 #define CMDQ_CREATE_QP_SQ_PG_SIZE_PG_2M (0x3UL << 4) 1040 #define CMDQ_CREATE_QP_SQ_PG_SIZE_PG_8M (0x4UL << 4) 1041 #define CMDQ_CREATE_QP_SQ_PG_SIZE_PG_1G (0x5UL << 4) 1042 u8 rq_pg_size_rq_lvl; 1043 #define CMDQ_CREATE_QP_RQ_LVL_MASK 0xfUL 1044 #define CMDQ_CREATE_QP_RQ_LVL_SFT 0 1045 #define CMDQ_CREATE_QP_RQ_LVL_LVL_0 0x0UL 1046 #define CMDQ_CREATE_QP_RQ_LVL_LVL_1 0x1UL 1047 #define CMDQ_CREATE_QP_RQ_LVL_LVL_2 0x2UL 1048 #define CMDQ_CREATE_QP_RQ_PG_SIZE_MASK 0xf0UL 1049 #define CMDQ_CREATE_QP_RQ_PG_SIZE_SFT 4 1050 #define CMDQ_CREATE_QP_RQ_PG_SIZE_PG_4K (0x0UL << 4) 1051 #define CMDQ_CREATE_QP_RQ_PG_SIZE_PG_8K (0x1UL << 4) 1052 #define CMDQ_CREATE_QP_RQ_PG_SIZE_PG_64K (0x2UL << 4) 1053 #define CMDQ_CREATE_QP_RQ_PG_SIZE_PG_2M (0x3UL << 4) 1054 #define CMDQ_CREATE_QP_RQ_PG_SIZE_PG_8M (0x4UL << 4) 1055 #define CMDQ_CREATE_QP_RQ_PG_SIZE_PG_1G (0x5UL << 4) 1056 u8 unused_0; 1057 __le32 dpi; 1058 __le32 sq_size; 1059 __le32 rq_size; 1060 __le16 sq_fwo_sq_sge; 1061 #define CMDQ_CREATE_QP_SQ_SGE_MASK 0xfUL 1062 #define CMDQ_CREATE_QP_SQ_SGE_SFT 0 1063 #define CMDQ_CREATE_QP_SQ_FWO_MASK 0xfff0UL 1064 #define CMDQ_CREATE_QP_SQ_FWO_SFT 4 1065 __le16 rq_fwo_rq_sge; 1066 #define CMDQ_CREATE_QP_RQ_SGE_MASK 0xfUL 1067 #define CMDQ_CREATE_QP_RQ_SGE_SFT 0 1068 #define CMDQ_CREATE_QP_RQ_FWO_MASK 0xfff0UL 1069 #define CMDQ_CREATE_QP_RQ_FWO_SFT 4 1070 __le32 scq_cid; 1071 __le32 rcq_cid; 1072 __le32 srq_cid; 1073 __le32 pd_id; 1074 __le64 sq_pbl; 1075 __le64 rq_pbl; 1076 __le64 irrq_addr; 1077 __le64 orrq_addr; 1078 }; 1079 1080 /* Destroy QP command (24 bytes) */ 1081 struct cmdq_destroy_qp { 1082 u8 opcode; 1083 #define CMDQ_DESTROY_QP_OPCODE_DESTROY_QP 0x2UL 1084 u8 cmd_size; 1085 __le16 flags; 1086 __le16 cookie; 1087 u8 resp_size; 1088 u8 reserved8; 1089 __le64 resp_addr; 1090 __le32 qp_cid; 1091 __le32 unused_0; 1092 }; 1093 1094 /* Modify QP command (112 bytes) */ 1095 struct cmdq_modify_qp { 1096 u8 opcode; 1097 #define CMDQ_MODIFY_QP_OPCODE_MODIFY_QP 0x3UL 1098 u8 cmd_size; 1099 __le16 flags; 1100 __le16 cookie; 1101 u8 resp_size; 1102 u8 reserved8; 1103 __le64 resp_addr; 1104 __le32 modify_mask; 1105 #define CMDQ_MODIFY_QP_MODIFY_MASK_STATE 0x1UL 1106 #define CMDQ_MODIFY_QP_MODIFY_MASK_EN_SQD_ASYNC_NOTIFY 0x2UL 1107 #define CMDQ_MODIFY_QP_MODIFY_MASK_ACCESS 0x4UL 1108 #define CMDQ_MODIFY_QP_MODIFY_MASK_PKEY 0x8UL 1109 #define CMDQ_MODIFY_QP_MODIFY_MASK_QKEY 0x10UL 1110 #define CMDQ_MODIFY_QP_MODIFY_MASK_DGID 0x20UL 1111 #define CMDQ_MODIFY_QP_MODIFY_MASK_FLOW_LABEL 0x40UL 1112 #define CMDQ_MODIFY_QP_MODIFY_MASK_SGID_INDEX 0x80UL 1113 #define CMDQ_MODIFY_QP_MODIFY_MASK_HOP_LIMIT 0x100UL 1114 #define CMDQ_MODIFY_QP_MODIFY_MASK_TRAFFIC_CLASS 0x200UL 1115 #define CMDQ_MODIFY_QP_MODIFY_MASK_DEST_MAC 0x400UL 1116 #define CMDQ_MODIFY_QP_MODIFY_MASK_PATH_MTU 0x1000UL 1117 #define CMDQ_MODIFY_QP_MODIFY_MASK_TIMEOUT 0x2000UL 1118 #define CMDQ_MODIFY_QP_MODIFY_MASK_RETRY_CNT 0x4000UL 1119 #define CMDQ_MODIFY_QP_MODIFY_MASK_RNR_RETRY 0x8000UL 1120 #define CMDQ_MODIFY_QP_MODIFY_MASK_RQ_PSN 0x10000UL 1121 #define CMDQ_MODIFY_QP_MODIFY_MASK_MAX_RD_ATOMIC 0x20000UL 1122 #define CMDQ_MODIFY_QP_MODIFY_MASK_MIN_RNR_TIMER 0x40000UL 1123 #define CMDQ_MODIFY_QP_MODIFY_MASK_SQ_PSN 0x80000UL 1124 #define CMDQ_MODIFY_QP_MODIFY_MASK_MAX_DEST_RD_ATOMIC 0x100000UL 1125 #define CMDQ_MODIFY_QP_MODIFY_MASK_SQ_SIZE 0x200000UL 1126 #define CMDQ_MODIFY_QP_MODIFY_MASK_RQ_SIZE 0x400000UL 1127 #define CMDQ_MODIFY_QP_MODIFY_MASK_SQ_SGE 0x800000UL 1128 #define CMDQ_MODIFY_QP_MODIFY_MASK_RQ_SGE 0x1000000UL 1129 #define CMDQ_MODIFY_QP_MODIFY_MASK_MAX_INLINE_DATA 0x2000000UL 1130 #define CMDQ_MODIFY_QP_MODIFY_MASK_DEST_QP_ID 0x4000000UL 1131 #define CMDQ_MODIFY_QP_MODIFY_MASK_SRC_MAC 0x8000000UL 1132 #define CMDQ_MODIFY_QP_MODIFY_MASK_VLAN_ID 0x10000000UL 1133 #define CMDQ_MODIFY_QP_MODIFY_MASK_ENABLE_CC 0x20000000UL 1134 #define CMDQ_MODIFY_QP_MODIFY_MASK_TOS_ECN 0x40000000UL 1135 #define CMDQ_MODIFY_QP_MODIFY_MASK_TOS_DSCP 0x80000000UL 1136 __le32 qp_cid; 1137 u8 network_type_en_sqd_async_notify_new_state; 1138 #define CMDQ_MODIFY_QP_NEW_STATE_MASK 0xfUL 1139 #define CMDQ_MODIFY_QP_NEW_STATE_SFT 0 1140 #define CMDQ_MODIFY_QP_NEW_STATE_RESET 0x0UL 1141 #define CMDQ_MODIFY_QP_NEW_STATE_INIT 0x1UL 1142 #define CMDQ_MODIFY_QP_NEW_STATE_RTR 0x2UL 1143 #define CMDQ_MODIFY_QP_NEW_STATE_RTS 0x3UL 1144 #define CMDQ_MODIFY_QP_NEW_STATE_SQD 0x4UL 1145 #define CMDQ_MODIFY_QP_NEW_STATE_SQE 0x5UL 1146 #define CMDQ_MODIFY_QP_NEW_STATE_ERR 0x6UL 1147 #define CMDQ_MODIFY_QP_EN_SQD_ASYNC_NOTIFY 0x10UL 1148 #define CMDQ_MODIFY_QP_NETWORK_TYPE_MASK 0xc0UL 1149 #define CMDQ_MODIFY_QP_NETWORK_TYPE_SFT 6 1150 #define CMDQ_MODIFY_QP_NETWORK_TYPE_ROCEV1 (0x0UL << 6) 1151 #define CMDQ_MODIFY_QP_NETWORK_TYPE_ROCEV2_IPV4 (0x2UL << 6) 1152 #define CMDQ_MODIFY_QP_NETWORK_TYPE_ROCEV2_IPV6 (0x3UL << 6) 1153 u8 access; 1154 #define CMDQ_MODIFY_QP_ACCESS_LOCAL_WRITE 0x1UL 1155 #define CMDQ_MODIFY_QP_ACCESS_REMOTE_WRITE 0x2UL 1156 #define CMDQ_MODIFY_QP_ACCESS_REMOTE_READ 0x4UL 1157 #define CMDQ_MODIFY_QP_ACCESS_REMOTE_ATOMIC 0x8UL 1158 __le16 pkey; 1159 __le32 qkey; 1160 __le32 dgid[4]; 1161 __le32 flow_label; 1162 __le16 sgid_index; 1163 u8 hop_limit; 1164 u8 traffic_class; 1165 __le16 dest_mac[3]; 1166 u8 tos_dscp_tos_ecn; 1167 #define CMDQ_MODIFY_QP_TOS_ECN_MASK 0x3UL 1168 #define CMDQ_MODIFY_QP_TOS_ECN_SFT 0 1169 #define CMDQ_MODIFY_QP_TOS_DSCP_MASK 0xfcUL 1170 #define CMDQ_MODIFY_QP_TOS_DSCP_SFT 2 1171 u8 path_mtu; 1172 #define CMDQ_MODIFY_QP_PATH_MTU_MASK 0xf0UL 1173 #define CMDQ_MODIFY_QP_PATH_MTU_SFT 4 1174 #define CMDQ_MODIFY_QP_PATH_MTU_MTU_256 (0x0UL << 4) 1175 #define CMDQ_MODIFY_QP_PATH_MTU_MTU_512 (0x1UL << 4) 1176 #define CMDQ_MODIFY_QP_PATH_MTU_MTU_1024 (0x2UL << 4) 1177 #define CMDQ_MODIFY_QP_PATH_MTU_MTU_2048 (0x3UL << 4) 1178 #define CMDQ_MODIFY_QP_PATH_MTU_MTU_4096 (0x4UL << 4) 1179 #define CMDQ_MODIFY_QP_PATH_MTU_MTU_8192 (0x5UL << 4) 1180 u8 timeout; 1181 u8 retry_cnt; 1182 u8 rnr_retry; 1183 u8 min_rnr_timer; 1184 __le32 rq_psn; 1185 __le32 sq_psn; 1186 u8 max_rd_atomic; 1187 u8 max_dest_rd_atomic; 1188 __le16 enable_cc; 1189 #define CMDQ_MODIFY_QP_ENABLE_CC 0x1UL 1190 __le32 sq_size; 1191 __le32 rq_size; 1192 __le16 sq_sge; 1193 __le16 rq_sge; 1194 __le32 max_inline_data; 1195 __le32 dest_qp_id; 1196 __le32 unused_3; 1197 __le16 src_mac[3]; 1198 __le16 vlan_pcp_vlan_dei_vlan_id; 1199 #define CMDQ_MODIFY_QP_VLAN_ID_MASK 0xfffUL 1200 #define CMDQ_MODIFY_QP_VLAN_ID_SFT 0 1201 #define CMDQ_MODIFY_QP_VLAN_DEI 0x1000UL 1202 #define CMDQ_MODIFY_QP_VLAN_PCP_MASK 0xe000UL 1203 #define CMDQ_MODIFY_QP_VLAN_PCP_SFT 13 1204 }; 1205 1206 /* Query QP command (24 bytes) */ 1207 struct cmdq_query_qp { 1208 u8 opcode; 1209 #define CMDQ_QUERY_QP_OPCODE_QUERY_QP 0x4UL 1210 u8 cmd_size; 1211 __le16 flags; 1212 __le16 cookie; 1213 u8 resp_size; 1214 u8 reserved8; 1215 __le64 resp_addr; 1216 __le32 qp_cid; 1217 __le32 unused_0; 1218 }; 1219 1220 /* Create SRQ command (48 bytes) */ 1221 struct cmdq_create_srq { 1222 u8 opcode; 1223 #define CMDQ_CREATE_SRQ_OPCODE_CREATE_SRQ 0x5UL 1224 u8 cmd_size; 1225 __le16 flags; 1226 __le16 cookie; 1227 u8 resp_size; 1228 u8 reserved8; 1229 __le64 resp_addr; 1230 __le64 srq_handle; 1231 __le16 pg_size_lvl; 1232 #define CMDQ_CREATE_SRQ_LVL_MASK 0x3UL 1233 #define CMDQ_CREATE_SRQ_LVL_SFT 0 1234 #define CMDQ_CREATE_SRQ_LVL_LVL_0 0x0UL 1235 #define CMDQ_CREATE_SRQ_LVL_LVL_1 0x1UL 1236 #define CMDQ_CREATE_SRQ_LVL_LVL_2 0x2UL 1237 #define CMDQ_CREATE_SRQ_PG_SIZE_MASK 0x1cUL 1238 #define CMDQ_CREATE_SRQ_PG_SIZE_SFT 2 1239 #define CMDQ_CREATE_SRQ_PG_SIZE_PG_4K (0x0UL << 2) 1240 #define CMDQ_CREATE_SRQ_PG_SIZE_PG_8K (0x1UL << 2) 1241 #define CMDQ_CREATE_SRQ_PG_SIZE_PG_64K (0x2UL << 2) 1242 #define CMDQ_CREATE_SRQ_PG_SIZE_PG_2M (0x3UL << 2) 1243 #define CMDQ_CREATE_SRQ_PG_SIZE_PG_8M (0x4UL << 2) 1244 #define CMDQ_CREATE_SRQ_PG_SIZE_PG_1G (0x5UL << 2) 1245 __le16 eventq_id; 1246 #define CMDQ_CREATE_SRQ_EVENTQ_ID_MASK 0xfffUL 1247 #define CMDQ_CREATE_SRQ_EVENTQ_ID_SFT 0 1248 __le16 srq_size; 1249 __le16 srq_fwo; 1250 __le32 dpi; 1251 __le32 pd_id; 1252 __le64 pbl; 1253 }; 1254 1255 /* Destroy SRQ command (24 bytes) */ 1256 struct cmdq_destroy_srq { 1257 u8 opcode; 1258 #define CMDQ_DESTROY_SRQ_OPCODE_DESTROY_SRQ 0x6UL 1259 u8 cmd_size; 1260 __le16 flags; 1261 __le16 cookie; 1262 u8 resp_size; 1263 u8 reserved8; 1264 __le64 resp_addr; 1265 __le32 srq_cid; 1266 __le32 unused_0; 1267 }; 1268 1269 /* Query SRQ command (24 bytes) */ 1270 struct cmdq_query_srq { 1271 u8 opcode; 1272 #define CMDQ_QUERY_SRQ_OPCODE_QUERY_SRQ 0x8UL 1273 u8 cmd_size; 1274 __le16 flags; 1275 __le16 cookie; 1276 u8 resp_size; 1277 u8 reserved8; 1278 __le64 resp_addr; 1279 __le32 srq_cid; 1280 __le32 unused_0; 1281 }; 1282 1283 /* Create CQ command (48 bytes) */ 1284 struct cmdq_create_cq { 1285 u8 opcode; 1286 #define CMDQ_CREATE_CQ_OPCODE_CREATE_CQ 0x9UL 1287 u8 cmd_size; 1288 __le16 flags; 1289 __le16 cookie; 1290 u8 resp_size; 1291 u8 reserved8; 1292 __le64 resp_addr; 1293 __le64 cq_handle; 1294 __le32 pg_size_lvl; 1295 #define CMDQ_CREATE_CQ_LVL_MASK 0x3UL 1296 #define CMDQ_CREATE_CQ_LVL_SFT 0 1297 #define CMDQ_CREATE_CQ_LVL_LVL_0 0x0UL 1298 #define CMDQ_CREATE_CQ_LVL_LVL_1 0x1UL 1299 #define CMDQ_CREATE_CQ_LVL_LVL_2 0x2UL 1300 #define CMDQ_CREATE_CQ_PG_SIZE_MASK 0x1cUL 1301 #define CMDQ_CREATE_CQ_PG_SIZE_SFT 2 1302 #define CMDQ_CREATE_CQ_PG_SIZE_PG_4K (0x0UL << 2) 1303 #define CMDQ_CREATE_CQ_PG_SIZE_PG_8K (0x1UL << 2) 1304 #define CMDQ_CREATE_CQ_PG_SIZE_PG_64K (0x2UL << 2) 1305 #define CMDQ_CREATE_CQ_PG_SIZE_PG_2M (0x3UL << 2) 1306 #define CMDQ_CREATE_CQ_PG_SIZE_PG_8M (0x4UL << 2) 1307 #define CMDQ_CREATE_CQ_PG_SIZE_PG_1G (0x5UL << 2) 1308 __le32 cq_fco_cnq_id; 1309 #define CMDQ_CREATE_CQ_CNQ_ID_MASK 0xfffUL 1310 #define CMDQ_CREATE_CQ_CNQ_ID_SFT 0 1311 #define CMDQ_CREATE_CQ_CQ_FCO_MASK 0xfffff000UL 1312 #define CMDQ_CREATE_CQ_CQ_FCO_SFT 12 1313 __le32 dpi; 1314 __le32 cq_size; 1315 __le64 pbl; 1316 }; 1317 1318 /* Destroy CQ command (24 bytes) */ 1319 struct cmdq_destroy_cq { 1320 u8 opcode; 1321 #define CMDQ_DESTROY_CQ_OPCODE_DESTROY_CQ 0xaUL 1322 u8 cmd_size; 1323 __le16 flags; 1324 __le16 cookie; 1325 u8 resp_size; 1326 u8 reserved8; 1327 __le64 resp_addr; 1328 __le32 cq_cid; 1329 __le32 unused_0; 1330 }; 1331 1332 /* Resize CQ command (40 bytes) */ 1333 struct cmdq_resize_cq { 1334 u8 opcode; 1335 #define CMDQ_RESIZE_CQ_OPCODE_RESIZE_CQ 0xcUL 1336 u8 cmd_size; 1337 __le16 flags; 1338 __le16 cookie; 1339 u8 resp_size; 1340 u8 reserved8; 1341 __le64 resp_addr; 1342 __le32 cq_cid; 1343 __le32 new_cq_size_pg_size_lvl; 1344 #define CMDQ_RESIZE_CQ_LVL_MASK 0x3UL 1345 #define CMDQ_RESIZE_CQ_LVL_SFT 0 1346 #define CMDQ_RESIZE_CQ_LVL_LVL_0 0x0UL 1347 #define CMDQ_RESIZE_CQ_LVL_LVL_1 0x1UL 1348 #define CMDQ_RESIZE_CQ_LVL_LVL_2 0x2UL 1349 #define CMDQ_RESIZE_CQ_PG_SIZE_MASK 0x1cUL 1350 #define CMDQ_RESIZE_CQ_PG_SIZE_SFT 2 1351 #define CMDQ_RESIZE_CQ_PG_SIZE_PG_4K (0x0UL << 2) 1352 #define CMDQ_RESIZE_CQ_PG_SIZE_PG_8K (0x1UL << 2) 1353 #define CMDQ_RESIZE_CQ_PG_SIZE_PG_64K (0x2UL << 2) 1354 #define CMDQ_RESIZE_CQ_PG_SIZE_PG_2M (0x3UL << 2) 1355 #define CMDQ_RESIZE_CQ_PG_SIZE_PG_8M (0x4UL << 2) 1356 #define CMDQ_RESIZE_CQ_PG_SIZE_PG_1G (0x5UL << 2) 1357 #define CMDQ_RESIZE_CQ_NEW_CQ_SIZE_MASK 0x1fffe0UL 1358 #define CMDQ_RESIZE_CQ_NEW_CQ_SIZE_SFT 5 1359 __le64 new_pbl; 1360 __le32 new_cq_fco; 1361 __le32 unused_2; 1362 }; 1363 1364 /* Allocate MRW command (32 bytes) */ 1365 struct cmdq_allocate_mrw { 1366 u8 opcode; 1367 #define CMDQ_ALLOCATE_MRW_OPCODE_ALLOCATE_MRW 0xdUL 1368 u8 cmd_size; 1369 __le16 flags; 1370 __le16 cookie; 1371 u8 resp_size; 1372 u8 reserved8; 1373 __le64 resp_addr; 1374 __le64 mrw_handle; 1375 u8 mrw_flags; 1376 #define CMDQ_ALLOCATE_MRW_MRW_FLAGS_MASK 0xfUL 1377 #define CMDQ_ALLOCATE_MRW_MRW_FLAGS_SFT 0 1378 #define CMDQ_ALLOCATE_MRW_MRW_FLAGS_MR 0x0UL 1379 #define CMDQ_ALLOCATE_MRW_MRW_FLAGS_PMR 0x1UL 1380 #define CMDQ_ALLOCATE_MRW_MRW_FLAGS_MW_TYPE1 0x2UL 1381 #define CMDQ_ALLOCATE_MRW_MRW_FLAGS_MW_TYPE2A 0x3UL 1382 #define CMDQ_ALLOCATE_MRW_MRW_FLAGS_MW_TYPE2B 0x4UL 1383 u8 access; 1384 #define CMDQ_ALLOCATE_MRW_ACCESS_RESERVED_MASK 0x1fUL 1385 #define CMDQ_ALLOCATE_MRW_ACCESS_RESERVED_SFT 0 1386 #define CMDQ_ALLOCATE_MRW_ACCESS_CONSUMER_OWNED_KEY 0x20UL 1387 __le16 unused_1; 1388 __le32 pd_id; 1389 }; 1390 1391 /* De-allocate key command (24 bytes) */ 1392 struct cmdq_deallocate_key { 1393 u8 opcode; 1394 #define CMDQ_DEALLOCATE_KEY_OPCODE_DEALLOCATE_KEY 0xeUL 1395 u8 cmd_size; 1396 __le16 flags; 1397 __le16 cookie; 1398 u8 resp_size; 1399 u8 reserved8; 1400 __le64 resp_addr; 1401 u8 mrw_flags; 1402 #define CMDQ_DEALLOCATE_KEY_MRW_FLAGS_MASK 0xfUL 1403 #define CMDQ_DEALLOCATE_KEY_MRW_FLAGS_SFT 0 1404 #define CMDQ_DEALLOCATE_KEY_MRW_FLAGS_MR 0x0UL 1405 #define CMDQ_DEALLOCATE_KEY_MRW_FLAGS_PMR 0x1UL 1406 #define CMDQ_DEALLOCATE_KEY_MRW_FLAGS_MW_TYPE1 0x2UL 1407 #define CMDQ_DEALLOCATE_KEY_MRW_FLAGS_MW_TYPE2A 0x3UL 1408 #define CMDQ_DEALLOCATE_KEY_MRW_FLAGS_MW_TYPE2B 0x4UL 1409 u8 unused_1[3]; 1410 __le32 key; 1411 }; 1412 1413 /* Register MR command (48 bytes) */ 1414 struct cmdq_register_mr { 1415 u8 opcode; 1416 #define CMDQ_REGISTER_MR_OPCODE_REGISTER_MR 0xfUL 1417 u8 cmd_size; 1418 __le16 flags; 1419 __le16 cookie; 1420 u8 resp_size; 1421 u8 reserved8; 1422 __le64 resp_addr; 1423 u8 log2_pg_size_lvl; 1424 #define CMDQ_REGISTER_MR_LVL_MASK 0x3UL 1425 #define CMDQ_REGISTER_MR_LVL_SFT 0 1426 #define CMDQ_REGISTER_MR_LVL_LVL_0 0x0UL 1427 #define CMDQ_REGISTER_MR_LVL_LVL_1 0x1UL 1428 #define CMDQ_REGISTER_MR_LVL_LVL_2 0x2UL 1429 #define CMDQ_REGISTER_MR_LVL_LAST CMDQ_REGISTER_MR_LVL_LVL_2 1430 #define CMDQ_REGISTER_MR_LOG2_PG_SIZE_MASK 0x7cUL 1431 #define CMDQ_REGISTER_MR_LOG2_PG_SIZE_SFT 2 1432 #define CMDQ_REGISTER_MR_LOG2_PG_SIZE_PG_4K (0xcUL << 2) 1433 #define CMDQ_REGISTER_MR_LOG2_PG_SIZE_PG_8K (0xdUL << 2) 1434 #define CMDQ_REGISTER_MR_LOG2_PG_SIZE_PG_64K (0x10UL << 2) 1435 #define CMDQ_REGISTER_MR_LOG2_PG_SIZE_PG_256K (0x12UL << 2) 1436 #define CMDQ_REGISTER_MR_LOG2_PG_SIZE_PG_1M (0x14UL << 2) 1437 #define CMDQ_REGISTER_MR_LOG2_PG_SIZE_PG_2M (0x15UL << 2) 1438 #define CMDQ_REGISTER_MR_LOG2_PG_SIZE_PG_4M (0x16UL << 2) 1439 #define CMDQ_REGISTER_MR_LOG2_PG_SIZE_PG_1G (0x1eUL << 2) 1440 #define CMDQ_REGISTER_MR_LOG2_PG_SIZE_LAST \ 1441 CMDQ_REGISTER_MR_LOG2_PG_SIZE_PG_1G 1442 #define CMDQ_REGISTER_MR_UNUSED1 0x80UL 1443 u8 access; 1444 #define CMDQ_REGISTER_MR_ACCESS_LOCAL_WRITE 0x1UL 1445 #define CMDQ_REGISTER_MR_ACCESS_REMOTE_READ 0x2UL 1446 #define CMDQ_REGISTER_MR_ACCESS_REMOTE_WRITE 0x4UL 1447 #define CMDQ_REGISTER_MR_ACCESS_REMOTE_ATOMIC 0x8UL 1448 #define CMDQ_REGISTER_MR_ACCESS_MW_BIND 0x10UL 1449 #define CMDQ_REGISTER_MR_ACCESS_ZERO_BASED 0x20UL 1450 __le16 log2_pbl_pg_size; 1451 #define CMDQ_REGISTER_MR_LOG2_PBL_PG_SIZE_MASK 0x1fUL 1452 #define CMDQ_REGISTER_MR_LOG2_PBL_PG_SIZE_SFT 0 1453 #define CMDQ_REGISTER_MR_LOG2_PBL_PG_SIZE_PG_4K 0xcUL 1454 #define CMDQ_REGISTER_MR_LOG2_PBL_PG_SIZE_PG_8K 0xdUL 1455 #define CMDQ_REGISTER_MR_LOG2_PBL_PG_SIZE_PG_64K 0x10UL 1456 #define CMDQ_REGISTER_MR_LOG2_PBL_PG_SIZE_PG_256K 0x12UL 1457 #define CMDQ_REGISTER_MR_LOG2_PBL_PG_SIZE_PG_1M 0x14UL 1458 #define CMDQ_REGISTER_MR_LOG2_PBL_PG_SIZE_PG_2M 0x15UL 1459 #define CMDQ_REGISTER_MR_LOG2_PBL_PG_SIZE_PG_4M 0x16UL 1460 #define CMDQ_REGISTER_MR_LOG2_PBL_PG_SIZE_PG_1G 0x1eUL 1461 #define CMDQ_REGISTER_MR_LOG2_PBL_PG_SIZE_LAST \ 1462 CMDQ_REGISTER_MR_LOG2_PBL_PG_SIZE_PG_1G 1463 #define CMDQ_REGISTER_MR_UNUSED11_MASK 0xffe0UL 1464 #define CMDQ_REGISTER_MR_UNUSED11_SFT 5 1465 __le32 key; 1466 __le64 pbl; 1467 __le64 va; 1468 __le64 mr_size; 1469 }; 1470 1471 /* Deregister MR command (24 bytes) */ 1472 struct cmdq_deregister_mr { 1473 u8 opcode; 1474 #define CMDQ_DEREGISTER_MR_OPCODE_DEREGISTER_MR 0x10UL 1475 u8 cmd_size; 1476 __le16 flags; 1477 __le16 cookie; 1478 u8 resp_size; 1479 u8 reserved8; 1480 __le64 resp_addr; 1481 __le32 lkey; 1482 __le32 unused_0; 1483 }; 1484 1485 /* Add GID command (48 bytes) */ 1486 struct cmdq_add_gid { 1487 u8 opcode; 1488 #define CMDQ_ADD_GID_OPCODE_ADD_GID 0x11UL 1489 u8 cmd_size; 1490 __le16 flags; 1491 __le16 cookie; 1492 u8 resp_size; 1493 u8 reserved8; 1494 __le64 resp_addr; 1495 __be32 gid[4]; 1496 __be16 src_mac[3]; 1497 __le16 vlan; 1498 #define CMDQ_ADD_GID_VLAN_VLAN_ID_MASK 0xfffUL 1499 #define CMDQ_ADD_GID_VLAN_VLAN_ID_SFT 0 1500 #define CMDQ_ADD_GID_VLAN_TPID_MASK 0x7000UL 1501 #define CMDQ_ADD_GID_VLAN_TPID_SFT 12 1502 #define CMDQ_ADD_GID_VLAN_TPID_TPID_88A8 (0x0UL << 12) 1503 #define CMDQ_ADD_GID_VLAN_TPID_TPID_8100 (0x1UL << 12) 1504 #define CMDQ_ADD_GID_VLAN_TPID_TPID_9100 (0x2UL << 12) 1505 #define CMDQ_ADD_GID_VLAN_TPID_TPID_9200 (0x3UL << 12) 1506 #define CMDQ_ADD_GID_VLAN_TPID_TPID_9300 (0x4UL << 12) 1507 #define CMDQ_ADD_GID_VLAN_TPID_TPID_CFG1 (0x5UL << 12) 1508 #define CMDQ_ADD_GID_VLAN_TPID_TPID_CFG2 (0x6UL << 12) 1509 #define CMDQ_ADD_GID_VLAN_TPID_TPID_CFG3 (0x7UL << 12) 1510 #define CMDQ_ADD_GID_VLAN_TPID_LAST CMDQ_ADD_GID_VLAN_TPID_TPID_CFG3 1511 #define CMDQ_ADD_GID_VLAN_VLAN_EN 0x8000UL 1512 __le16 ipid; 1513 __le16 stats_ctx; 1514 #define CMDQ_ADD_GID_STATS_CTX_STATS_CTX_ID_MASK 0x7fffUL 1515 #define CMDQ_ADD_GID_STATS_CTX_STATS_CTX_ID_SFT 0 1516 #define CMDQ_ADD_GID_STATS_CTX_STATS_CTX_VALID 0x8000UL 1517 __le32 unused_0; 1518 }; 1519 1520 /* Delete GID command (24 bytes) */ 1521 struct cmdq_delete_gid { 1522 u8 opcode; 1523 #define CMDQ_DELETE_GID_OPCODE_DELETE_GID 0x12UL 1524 u8 cmd_size; 1525 __le16 flags; 1526 __le16 cookie; 1527 u8 resp_size; 1528 u8 reserved8; 1529 __le64 resp_addr; 1530 __le16 gid_index; 1531 __le16 unused_0; 1532 __le32 unused_1; 1533 }; 1534 1535 /* Modify GID command (48 bytes) */ 1536 struct cmdq_modify_gid { 1537 u8 opcode; 1538 #define CMDQ_MODIFY_GID_OPCODE_MODIFY_GID 0x17UL 1539 u8 cmd_size; 1540 __le16 flags; 1541 __le16 cookie; 1542 u8 resp_size; 1543 u8 reserved8; 1544 __le64 resp_addr; 1545 __be32 gid[4]; 1546 __be16 src_mac[3]; 1547 __le16 vlan; 1548 #define CMDQ_MODIFY_GID_VLAN_VLAN_ID_MASK 0xfffUL 1549 #define CMDQ_MODIFY_GID_VLAN_VLAN_ID_SFT 0 1550 #define CMDQ_MODIFY_GID_VLAN_TPID_MASK 0x7000UL 1551 #define CMDQ_MODIFY_GID_VLAN_TPID_SFT 12 1552 #define CMDQ_MODIFY_GID_VLAN_TPID_TPID_88A8 (0x0UL << 12) 1553 #define CMDQ_MODIFY_GID_VLAN_TPID_TPID_8100 (0x1UL << 12) 1554 #define CMDQ_MODIFY_GID_VLAN_TPID_TPID_9100 (0x2UL << 12) 1555 #define CMDQ_MODIFY_GID_VLAN_TPID_TPID_9200 (0x3UL << 12) 1556 #define CMDQ_MODIFY_GID_VLAN_TPID_TPID_9300 (0x4UL << 12) 1557 #define CMDQ_MODIFY_GID_VLAN_TPID_TPID_CFG1 (0x5UL << 12) 1558 #define CMDQ_MODIFY_GID_VLAN_TPID_TPID_CFG2 (0x6UL << 12) 1559 #define CMDQ_MODIFY_GID_VLAN_TPID_TPID_CFG3 (0x7UL << 12) 1560 #define CMDQ_MODIFY_GID_VLAN_TPID_LAST \ 1561 CMDQ_MODIFY_GID_VLAN_TPID_TPID_CFG3 1562 #define CMDQ_MODIFY_GID_VLAN_VLAN_EN 0x8000UL 1563 __le16 ipid; 1564 __le16 gid_index; 1565 __le16 stats_ctx; 1566 #define CMDQ_MODIFY_GID_STATS_CTX_STATS_CTX_ID_MASK 0x7fffUL 1567 #define CMDQ_MODIFY_GID_STATS_CTX_STATS_CTX_ID_SFT 0 1568 #define CMDQ_MODIFY_GID_STATS_CTX_STATS_CTX_VALID 0x8000UL 1569 __le16 unused_0; 1570 }; 1571 1572 /* Query GID command (24 bytes) */ 1573 struct cmdq_query_gid { 1574 u8 opcode; 1575 #define CMDQ_QUERY_GID_OPCODE_QUERY_GID 0x18UL 1576 u8 cmd_size; 1577 __le16 flags; 1578 __le16 cookie; 1579 u8 resp_size; 1580 u8 reserved8; 1581 __le64 resp_addr; 1582 __le16 gid_index; 1583 __le16 unused_0; 1584 __le32 unused_1; 1585 }; 1586 1587 /* Create QP1 command (80 bytes) */ 1588 struct cmdq_create_qp1 { 1589 u8 opcode; 1590 #define CMDQ_CREATE_QP1_OPCODE_CREATE_QP1 0x13UL 1591 u8 cmd_size; 1592 __le16 flags; 1593 __le16 cookie; 1594 u8 resp_size; 1595 u8 reserved8; 1596 __le64 resp_addr; 1597 __le64 qp_handle; 1598 __le32 qp_flags; 1599 #define CMDQ_CREATE_QP1_QP_FLAGS_SRQ_USED 0x1UL 1600 #define CMDQ_CREATE_QP1_QP_FLAGS_FORCE_COMPLETION 0x2UL 1601 #define CMDQ_CREATE_QP1_QP_FLAGS_RESERVED_LKEY_ENABLE 0x4UL 1602 u8 type; 1603 #define CMDQ_CREATE_QP1_TYPE_GSI 0x1UL 1604 u8 sq_pg_size_sq_lvl; 1605 #define CMDQ_CREATE_QP1_SQ_LVL_MASK 0xfUL 1606 #define CMDQ_CREATE_QP1_SQ_LVL_SFT 0 1607 #define CMDQ_CREATE_QP1_SQ_LVL_LVL_0 0x0UL 1608 #define CMDQ_CREATE_QP1_SQ_LVL_LVL_1 0x1UL 1609 #define CMDQ_CREATE_QP1_SQ_LVL_LVL_2 0x2UL 1610 #define CMDQ_CREATE_QP1_SQ_PG_SIZE_MASK 0xf0UL 1611 #define CMDQ_CREATE_QP1_SQ_PG_SIZE_SFT 4 1612 #define CMDQ_CREATE_QP1_SQ_PG_SIZE_PG_4K (0x0UL << 4) 1613 #define CMDQ_CREATE_QP1_SQ_PG_SIZE_PG_8K (0x1UL << 4) 1614 #define CMDQ_CREATE_QP1_SQ_PG_SIZE_PG_64K (0x2UL << 4) 1615 #define CMDQ_CREATE_QP1_SQ_PG_SIZE_PG_2M (0x3UL << 4) 1616 #define CMDQ_CREATE_QP1_SQ_PG_SIZE_PG_8M (0x4UL << 4) 1617 #define CMDQ_CREATE_QP1_SQ_PG_SIZE_PG_1G (0x5UL << 4) 1618 u8 rq_pg_size_rq_lvl; 1619 #define CMDQ_CREATE_QP1_RQ_LVL_MASK 0xfUL 1620 #define CMDQ_CREATE_QP1_RQ_LVL_SFT 0 1621 #define CMDQ_CREATE_QP1_RQ_LVL_LVL_0 0x0UL 1622 #define CMDQ_CREATE_QP1_RQ_LVL_LVL_1 0x1UL 1623 #define CMDQ_CREATE_QP1_RQ_LVL_LVL_2 0x2UL 1624 #define CMDQ_CREATE_QP1_RQ_PG_SIZE_MASK 0xf0UL 1625 #define CMDQ_CREATE_QP1_RQ_PG_SIZE_SFT 4 1626 #define CMDQ_CREATE_QP1_RQ_PG_SIZE_PG_4K (0x0UL << 4) 1627 #define CMDQ_CREATE_QP1_RQ_PG_SIZE_PG_8K (0x1UL << 4) 1628 #define CMDQ_CREATE_QP1_RQ_PG_SIZE_PG_64K (0x2UL << 4) 1629 #define CMDQ_CREATE_QP1_RQ_PG_SIZE_PG_2M (0x3UL << 4) 1630 #define CMDQ_CREATE_QP1_RQ_PG_SIZE_PG_8M (0x4UL << 4) 1631 #define CMDQ_CREATE_QP1_RQ_PG_SIZE_PG_1G (0x5UL << 4) 1632 u8 unused_0; 1633 __le32 dpi; 1634 __le32 sq_size; 1635 __le32 rq_size; 1636 __le16 sq_fwo_sq_sge; 1637 #define CMDQ_CREATE_QP1_SQ_SGE_MASK 0xfUL 1638 #define CMDQ_CREATE_QP1_SQ_SGE_SFT 0 1639 #define CMDQ_CREATE_QP1_SQ_FWO_MASK 0xfff0UL 1640 #define CMDQ_CREATE_QP1_SQ_FWO_SFT 4 1641 __le16 rq_fwo_rq_sge; 1642 #define CMDQ_CREATE_QP1_RQ_SGE_MASK 0xfUL 1643 #define CMDQ_CREATE_QP1_RQ_SGE_SFT 0 1644 #define CMDQ_CREATE_QP1_RQ_FWO_MASK 0xfff0UL 1645 #define CMDQ_CREATE_QP1_RQ_FWO_SFT 4 1646 __le32 scq_cid; 1647 __le32 rcq_cid; 1648 __le32 srq_cid; 1649 __le32 pd_id; 1650 __le64 sq_pbl; 1651 __le64 rq_pbl; 1652 }; 1653 1654 /* Destroy QP1 command (24 bytes) */ 1655 struct cmdq_destroy_qp1 { 1656 u8 opcode; 1657 #define CMDQ_DESTROY_QP1_OPCODE_DESTROY_QP1 0x14UL 1658 u8 cmd_size; 1659 __le16 flags; 1660 __le16 cookie; 1661 u8 resp_size; 1662 u8 reserved8; 1663 __le64 resp_addr; 1664 __le32 qp1_cid; 1665 __le32 unused_0; 1666 }; 1667 1668 /* Create AH command (64 bytes) */ 1669 struct cmdq_create_ah { 1670 u8 opcode; 1671 #define CMDQ_CREATE_AH_OPCODE_CREATE_AH 0x15UL 1672 u8 cmd_size; 1673 __le16 flags; 1674 __le16 cookie; 1675 u8 resp_size; 1676 u8 reserved8; 1677 __le64 resp_addr; 1678 __le64 ah_handle; 1679 __le32 dgid[4]; 1680 u8 type; 1681 #define CMDQ_CREATE_AH_TYPE_V1 0x0UL 1682 #define CMDQ_CREATE_AH_TYPE_V2IPV4 0x2UL 1683 #define CMDQ_CREATE_AH_TYPE_V2IPV6 0x3UL 1684 u8 hop_limit; 1685 __le16 sgid_index; 1686 __le32 dest_vlan_id_flow_label; 1687 #define CMDQ_CREATE_AH_FLOW_LABEL_MASK 0xfffffUL 1688 #define CMDQ_CREATE_AH_FLOW_LABEL_SFT 0 1689 #define CMDQ_CREATE_AH_DEST_VLAN_ID_MASK 0xfff00000UL 1690 #define CMDQ_CREATE_AH_DEST_VLAN_ID_SFT 20 1691 __le32 pd_id; 1692 __le32 unused_0; 1693 __le16 dest_mac[3]; 1694 u8 traffic_class; 1695 u8 unused_1; 1696 }; 1697 1698 /* Destroy AH command (24 bytes) */ 1699 struct cmdq_destroy_ah { 1700 u8 opcode; 1701 #define CMDQ_DESTROY_AH_OPCODE_DESTROY_AH 0x16UL 1702 u8 cmd_size; 1703 __le16 flags; 1704 __le16 cookie; 1705 u8 resp_size; 1706 u8 reserved8; 1707 __le64 resp_addr; 1708 __le32 ah_cid; 1709 __le32 unused_0; 1710 }; 1711 1712 /* Initialize Firmware command (112 bytes) */ 1713 struct cmdq_initialize_fw { 1714 u8 opcode; 1715 #define CMDQ_INITIALIZE_FW_OPCODE_INITIALIZE_FW 0x80UL 1716 u8 cmd_size; 1717 __le16 flags; 1718 __le16 cookie; 1719 u8 resp_size; 1720 u8 reserved8; 1721 __le64 resp_addr; 1722 u8 qpc_pg_size_qpc_lvl; 1723 #define CMDQ_INITIALIZE_FW_QPC_LVL_MASK 0xfUL 1724 #define CMDQ_INITIALIZE_FW_QPC_LVL_SFT 0 1725 #define CMDQ_INITIALIZE_FW_QPC_LVL_LVL_0 0x0UL 1726 #define CMDQ_INITIALIZE_FW_QPC_LVL_LVL_1 0x1UL 1727 #define CMDQ_INITIALIZE_FW_QPC_LVL_LVL_2 0x2UL 1728 #define CMDQ_INITIALIZE_FW_QPC_PG_SIZE_MASK 0xf0UL 1729 #define CMDQ_INITIALIZE_FW_QPC_PG_SIZE_SFT 4 1730 #define CMDQ_INITIALIZE_FW_QPC_PG_SIZE_PG_4K (0x0UL << 4) 1731 #define CMDQ_INITIALIZE_FW_QPC_PG_SIZE_PG_8K (0x1UL << 4) 1732 #define CMDQ_INITIALIZE_FW_QPC_PG_SIZE_PG_64K (0x2UL << 4) 1733 #define CMDQ_INITIALIZE_FW_QPC_PG_SIZE_PG_2M (0x3UL << 4) 1734 #define CMDQ_INITIALIZE_FW_QPC_PG_SIZE_PG_8M (0x4UL << 4) 1735 #define CMDQ_INITIALIZE_FW_QPC_PG_SIZE_PG_1G (0x5UL << 4) 1736 u8 mrw_pg_size_mrw_lvl; 1737 #define CMDQ_INITIALIZE_FW_MRW_LVL_MASK 0xfUL 1738 #define CMDQ_INITIALIZE_FW_MRW_LVL_SFT 0 1739 #define CMDQ_INITIALIZE_FW_MRW_LVL_LVL_0 0x0UL 1740 #define CMDQ_INITIALIZE_FW_MRW_LVL_LVL_1 0x1UL 1741 #define CMDQ_INITIALIZE_FW_MRW_LVL_LVL_2 0x2UL 1742 #define CMDQ_INITIALIZE_FW_MRW_PG_SIZE_MASK 0xf0UL 1743 #define CMDQ_INITIALIZE_FW_MRW_PG_SIZE_SFT 4 1744 #define CMDQ_INITIALIZE_FW_MRW_PG_SIZE_PG_4K (0x0UL << 4) 1745 #define CMDQ_INITIALIZE_FW_MRW_PG_SIZE_PG_8K (0x1UL << 4) 1746 #define CMDQ_INITIALIZE_FW_MRW_PG_SIZE_PG_64K (0x2UL << 4) 1747 #define CMDQ_INITIALIZE_FW_MRW_PG_SIZE_PG_2M (0x3UL << 4) 1748 #define CMDQ_INITIALIZE_FW_MRW_PG_SIZE_PG_8M (0x4UL << 4) 1749 #define CMDQ_INITIALIZE_FW_MRW_PG_SIZE_PG_1G (0x5UL << 4) 1750 u8 srq_pg_size_srq_lvl; 1751 #define CMDQ_INITIALIZE_FW_SRQ_LVL_MASK 0xfUL 1752 #define CMDQ_INITIALIZE_FW_SRQ_LVL_SFT 0 1753 #define CMDQ_INITIALIZE_FW_SRQ_LVL_LVL_0 0x0UL 1754 #define CMDQ_INITIALIZE_FW_SRQ_LVL_LVL_1 0x1UL 1755 #define CMDQ_INITIALIZE_FW_SRQ_LVL_LVL_2 0x2UL 1756 #define CMDQ_INITIALIZE_FW_SRQ_PG_SIZE_MASK 0xf0UL 1757 #define CMDQ_INITIALIZE_FW_SRQ_PG_SIZE_SFT 4 1758 #define CMDQ_INITIALIZE_FW_SRQ_PG_SIZE_PG_4K (0x0UL << 4) 1759 #define CMDQ_INITIALIZE_FW_SRQ_PG_SIZE_PG_8K (0x1UL << 4) 1760 #define CMDQ_INITIALIZE_FW_SRQ_PG_SIZE_PG_64K (0x2UL << 4) 1761 #define CMDQ_INITIALIZE_FW_SRQ_PG_SIZE_PG_2M (0x3UL << 4) 1762 #define CMDQ_INITIALIZE_FW_SRQ_PG_SIZE_PG_8M (0x4UL << 4) 1763 #define CMDQ_INITIALIZE_FW_SRQ_PG_SIZE_PG_1G (0x5UL << 4) 1764 u8 cq_pg_size_cq_lvl; 1765 #define CMDQ_INITIALIZE_FW_CQ_LVL_MASK 0xfUL 1766 #define CMDQ_INITIALIZE_FW_CQ_LVL_SFT 0 1767 #define CMDQ_INITIALIZE_FW_CQ_LVL_LVL_0 0x0UL 1768 #define CMDQ_INITIALIZE_FW_CQ_LVL_LVL_1 0x1UL 1769 #define CMDQ_INITIALIZE_FW_CQ_LVL_LVL_2 0x2UL 1770 #define CMDQ_INITIALIZE_FW_CQ_PG_SIZE_MASK 0xf0UL 1771 #define CMDQ_INITIALIZE_FW_CQ_PG_SIZE_SFT 4 1772 #define CMDQ_INITIALIZE_FW_CQ_PG_SIZE_PG_4K (0x0UL << 4) 1773 #define CMDQ_INITIALIZE_FW_CQ_PG_SIZE_PG_8K (0x1UL << 4) 1774 #define CMDQ_INITIALIZE_FW_CQ_PG_SIZE_PG_64K (0x2UL << 4) 1775 #define CMDQ_INITIALIZE_FW_CQ_PG_SIZE_PG_2M (0x3UL << 4) 1776 #define CMDQ_INITIALIZE_FW_CQ_PG_SIZE_PG_8M (0x4UL << 4) 1777 #define CMDQ_INITIALIZE_FW_CQ_PG_SIZE_PG_1G (0x5UL << 4) 1778 u8 tqm_pg_size_tqm_lvl; 1779 #define CMDQ_INITIALIZE_FW_TQM_LVL_MASK 0xfUL 1780 #define CMDQ_INITIALIZE_FW_TQM_LVL_SFT 0 1781 #define CMDQ_INITIALIZE_FW_TQM_LVL_LVL_0 0x0UL 1782 #define CMDQ_INITIALIZE_FW_TQM_LVL_LVL_1 0x1UL 1783 #define CMDQ_INITIALIZE_FW_TQM_LVL_LVL_2 0x2UL 1784 #define CMDQ_INITIALIZE_FW_TQM_PG_SIZE_MASK 0xf0UL 1785 #define CMDQ_INITIALIZE_FW_TQM_PG_SIZE_SFT 4 1786 #define CMDQ_INITIALIZE_FW_TQM_PG_SIZE_PG_4K (0x0UL << 4) 1787 #define CMDQ_INITIALIZE_FW_TQM_PG_SIZE_PG_8K (0x1UL << 4) 1788 #define CMDQ_INITIALIZE_FW_TQM_PG_SIZE_PG_64K (0x2UL << 4) 1789 #define CMDQ_INITIALIZE_FW_TQM_PG_SIZE_PG_2M (0x3UL << 4) 1790 #define CMDQ_INITIALIZE_FW_TQM_PG_SIZE_PG_8M (0x4UL << 4) 1791 #define CMDQ_INITIALIZE_FW_TQM_PG_SIZE_PG_1G (0x5UL << 4) 1792 u8 tim_pg_size_tim_lvl; 1793 #define CMDQ_INITIALIZE_FW_TIM_LVL_MASK 0xfUL 1794 #define CMDQ_INITIALIZE_FW_TIM_LVL_SFT 0 1795 #define CMDQ_INITIALIZE_FW_TIM_LVL_LVL_0 0x0UL 1796 #define CMDQ_INITIALIZE_FW_TIM_LVL_LVL_1 0x1UL 1797 #define CMDQ_INITIALIZE_FW_TIM_LVL_LVL_2 0x2UL 1798 #define CMDQ_INITIALIZE_FW_TIM_PG_SIZE_MASK 0xf0UL 1799 #define CMDQ_INITIALIZE_FW_TIM_PG_SIZE_SFT 4 1800 #define CMDQ_INITIALIZE_FW_TIM_PG_SIZE_PG_4K (0x0UL << 4) 1801 #define CMDQ_INITIALIZE_FW_TIM_PG_SIZE_PG_8K (0x1UL << 4) 1802 #define CMDQ_INITIALIZE_FW_TIM_PG_SIZE_PG_64K (0x2UL << 4) 1803 #define CMDQ_INITIALIZE_FW_TIM_PG_SIZE_PG_2M (0x3UL << 4) 1804 #define CMDQ_INITIALIZE_FW_TIM_PG_SIZE_PG_8M (0x4UL << 4) 1805 #define CMDQ_INITIALIZE_FW_TIM_PG_SIZE_PG_1G (0x5UL << 4) 1806 /* This value is (log-base-2-of-DBR-page-size - 12). 1807 * 0 for 4KB. HW supported values are enumerated below. 1808 */ 1809 __le16 log2_dbr_pg_size; 1810 #define CMDQ_INITIALIZE_FW_LOG2_DBR_PG_SIZE_MASK 0xfUL 1811 #define CMDQ_INITIALIZE_FW_LOG2_DBR_PG_SIZE_SFT 0 1812 #define CMDQ_INITIALIZE_FW_LOG2_DBR_PG_SIZE_PG_4K 0x0UL 1813 #define CMDQ_INITIALIZE_FW_LOG2_DBR_PG_SIZE_PG_8K 0x1UL 1814 #define CMDQ_INITIALIZE_FW_LOG2_DBR_PG_SIZE_PG_16K 0x2UL 1815 #define CMDQ_INITIALIZE_FW_LOG2_DBR_PG_SIZE_PG_32K 0x3UL 1816 #define CMDQ_INITIALIZE_FW_LOG2_DBR_PG_SIZE_PG_64K 0x4UL 1817 #define CMDQ_INITIALIZE_FW_LOG2_DBR_PG_SIZE_PG_128K 0x5UL 1818 #define CMDQ_INITIALIZE_FW_LOG2_DBR_PG_SIZE_PG_256K 0x6UL 1819 #define CMDQ_INITIALIZE_FW_LOG2_DBR_PG_SIZE_PG_512K 0x7UL 1820 #define CMDQ_INITIALIZE_FW_LOG2_DBR_PG_SIZE_PG_1M 0x8UL 1821 #define CMDQ_INITIALIZE_FW_LOG2_DBR_PG_SIZE_PG_2M 0x9UL 1822 #define CMDQ_INITIALIZE_FW_LOG2_DBR_PG_SIZE_PG_4M 0xaUL 1823 #define CMDQ_INITIALIZE_FW_LOG2_DBR_PG_SIZE_PG_8M 0xbUL 1824 #define CMDQ_INITIALIZE_FW_LOG2_DBR_PG_SIZE_PG_16M 0xcUL 1825 #define CMDQ_INITIALIZE_FW_LOG2_DBR_PG_SIZE_PG_32M 0xdUL 1826 #define CMDQ_INITIALIZE_FW_LOG2_DBR_PG_SIZE_PG_64M 0xeUL 1827 #define CMDQ_INITIALIZE_FW_LOG2_DBR_PG_SIZE_PG_128M 0xfUL 1828 #define CMDQ_INITIALIZE_FW_LOG2_DBR_PG_SIZE_LAST \ 1829 CMDQ_INITIALIZE_FW_LOG2_DBR_PG_SIZE_PG_128M 1830 __le64 qpc_page_dir; 1831 __le64 mrw_page_dir; 1832 __le64 srq_page_dir; 1833 __le64 cq_page_dir; 1834 __le64 tqm_page_dir; 1835 __le64 tim_page_dir; 1836 __le32 number_of_qp; 1837 __le32 number_of_mrw; 1838 __le32 number_of_srq; 1839 __le32 number_of_cq; 1840 __le32 max_qp_per_vf; 1841 __le32 max_mrw_per_vf; 1842 __le32 max_srq_per_vf; 1843 __le32 max_cq_per_vf; 1844 __le32 max_gid_per_vf; 1845 __le32 stat_ctx_id; 1846 }; 1847 1848 /* De-initialize Firmware command (16 bytes) */ 1849 struct cmdq_deinitialize_fw { 1850 u8 opcode; 1851 #define CMDQ_DEINITIALIZE_FW_OPCODE_DEINITIALIZE_FW 0x81UL 1852 u8 cmd_size; 1853 __le16 flags; 1854 __le16 cookie; 1855 u8 resp_size; 1856 u8 reserved8; 1857 __le64 resp_addr; 1858 }; 1859 1860 /* Stop function command (16 bytes) */ 1861 struct cmdq_stop_func { 1862 u8 opcode; 1863 #define CMDQ_STOP_FUNC_OPCODE_STOP_FUNC 0x82UL 1864 u8 cmd_size; 1865 __le16 flags; 1866 __le16 cookie; 1867 u8 resp_size; 1868 u8 reserved8; 1869 __le64 resp_addr; 1870 }; 1871 1872 /* Query function command (16 bytes) */ 1873 struct cmdq_query_func { 1874 u8 opcode; 1875 #define CMDQ_QUERY_FUNC_OPCODE_QUERY_FUNC 0x83UL 1876 u8 cmd_size; 1877 __le16 flags; 1878 __le16 cookie; 1879 u8 resp_size; 1880 u8 reserved8; 1881 __le64 resp_addr; 1882 }; 1883 1884 /* Set function resources command (16 bytes) */ 1885 struct cmdq_set_func_resources { 1886 u8 opcode; 1887 #define CMDQ_SET_FUNC_RESOURCES_OPCODE_SET_FUNC_RESOURCES 0x84UL 1888 u8 cmd_size; 1889 __le16 flags; 1890 __le16 cookie; 1891 u8 resp_size; 1892 u8 reserved8; 1893 __le64 resp_addr; 1894 __le32 number_of_qp; 1895 __le32 number_of_mrw; 1896 __le32 number_of_srq; 1897 __le32 number_of_cq; 1898 __le32 max_qp_per_vf; 1899 __le32 max_mrw_per_vf; 1900 __le32 max_srq_per_vf; 1901 __le32 max_cq_per_vf; 1902 __le32 max_gid_per_vf; 1903 __le32 stat_ctx_id; 1904 }; 1905 1906 /* Read hardware resource context command (24 bytes) */ 1907 struct cmdq_read_context { 1908 u8 opcode; 1909 #define CMDQ_READ_CONTEXT_OPCODE_READ_CONTEXT 0x85UL 1910 u8 cmd_size; 1911 __le16 flags; 1912 __le16 cookie; 1913 u8 resp_size; 1914 u8 reserved8; 1915 __le64 resp_addr; 1916 __le32 type_xid; 1917 #define CMDQ_READ_CONTEXT_XID_MASK 0xffffffUL 1918 #define CMDQ_READ_CONTEXT_XID_SFT 0 1919 #define CMDQ_READ_CONTEXT_TYPE_MASK 0xff000000UL 1920 #define CMDQ_READ_CONTEXT_TYPE_SFT 24 1921 #define CMDQ_READ_CONTEXT_TYPE_QPC (0x0UL << 24) 1922 #define CMDQ_READ_CONTEXT_TYPE_CQ (0x1UL << 24) 1923 #define CMDQ_READ_CONTEXT_TYPE_MRW (0x2UL << 24) 1924 #define CMDQ_READ_CONTEXT_TYPE_SRQ (0x3UL << 24) 1925 __le32 unused_0; 1926 }; 1927 1928 /* Map TC to COS. Can only be issued from a PF (24 bytes) */ 1929 struct cmdq_map_tc_to_cos { 1930 u8 opcode; 1931 #define CMDQ_MAP_TC_TO_COS_OPCODE_MAP_TC_TO_COS 0x8aUL 1932 u8 cmd_size; 1933 __le16 flags; 1934 __le16 cookie; 1935 u8 resp_size; 1936 u8 reserved8; 1937 __le64 resp_addr; 1938 __le16 cos0; 1939 #define CMDQ_MAP_TC_TO_COS_COS0_NO_CHANGE 0xffffUL 1940 __le16 cos1; 1941 #define CMDQ_MAP_TC_TO_COS_COS1_DISABLE 0x8000UL 1942 #define CMDQ_MAP_TC_TO_COS_COS1_NO_CHANGE 0xffffUL 1943 __le32 unused_0; 1944 }; 1945 1946 /* Query version command (16 bytes) */ 1947 struct cmdq_query_version { 1948 u8 opcode; 1949 #define CMDQ_QUERY_VERSION_OPCODE_QUERY_VERSION 0x8bUL 1950 u8 cmd_size; 1951 __le16 flags; 1952 __le16 cookie; 1953 u8 resp_size; 1954 u8 reserved8; 1955 __le64 resp_addr; 1956 }; 1957 1958 /* Command-Response Event Queue (CREQ) Structures */ 1959 /* Base CREQ Record (16 bytes) */ 1960 struct creq_base { 1961 u8 type; 1962 #define CREQ_BASE_TYPE_MASK 0x3fUL 1963 #define CREQ_BASE_TYPE_SFT 0 1964 #define CREQ_BASE_TYPE_QP_EVENT 0x38UL 1965 #define CREQ_BASE_TYPE_FUNC_EVENT 0x3aUL 1966 #define CREQ_BASE_RESERVED2_MASK 0xc0UL 1967 #define CREQ_BASE_RESERVED2_SFT 6 1968 u8 reserved56[7]; 1969 u8 v; 1970 #define CREQ_BASE_V 0x1UL 1971 #define CREQ_BASE_RESERVED7_MASK 0xfeUL 1972 #define CREQ_BASE_RESERVED7_SFT 1 1973 u8 event; 1974 __le16 reserved48[3]; 1975 }; 1976 1977 /* RoCE Function Async Event Notification (16 bytes) */ 1978 struct creq_func_event { 1979 u8 type; 1980 #define CREQ_FUNC_EVENT_TYPE_MASK 0x3fUL 1981 #define CREQ_FUNC_EVENT_TYPE_SFT 0 1982 #define CREQ_FUNC_EVENT_TYPE_FUNC_EVENT 0x3aUL 1983 #define CREQ_FUNC_EVENT_RESERVED2_MASK 0xc0UL 1984 #define CREQ_FUNC_EVENT_RESERVED2_SFT 6 1985 u8 reserved56[7]; 1986 u8 v; 1987 #define CREQ_FUNC_EVENT_V 0x1UL 1988 #define CREQ_FUNC_EVENT_RESERVED7_MASK 0xfeUL 1989 #define CREQ_FUNC_EVENT_RESERVED7_SFT 1 1990 u8 event; 1991 #define CREQ_FUNC_EVENT_EVENT_TX_WQE_ERROR 0x1UL 1992 #define CREQ_FUNC_EVENT_EVENT_TX_DATA_ERROR 0x2UL 1993 #define CREQ_FUNC_EVENT_EVENT_RX_WQE_ERROR 0x3UL 1994 #define CREQ_FUNC_EVENT_EVENT_RX_DATA_ERROR 0x4UL 1995 #define CREQ_FUNC_EVENT_EVENT_CQ_ERROR 0x5UL 1996 #define CREQ_FUNC_EVENT_EVENT_TQM_ERROR 0x6UL 1997 #define CREQ_FUNC_EVENT_EVENT_CFCQ_ERROR 0x7UL 1998 #define CREQ_FUNC_EVENT_EVENT_CFCS_ERROR 0x8UL 1999 #define CREQ_FUNC_EVENT_EVENT_CFCC_ERROR 0x9UL 2000 #define CREQ_FUNC_EVENT_EVENT_CFCM_ERROR 0xaUL 2001 #define CREQ_FUNC_EVENT_EVENT_TIM_ERROR 0xbUL 2002 #define CREQ_FUNC_EVENT_EVENT_VF_COMM_REQUEST 0x80UL 2003 #define CREQ_FUNC_EVENT_EVENT_RESOURCE_EXHAUSTED 0x81UL 2004 __le16 reserved48[3]; 2005 }; 2006 2007 /* RoCE Slowpath Command Completion (16 bytes) */ 2008 struct creq_qp_event { 2009 u8 type; 2010 #define CREQ_QP_EVENT_TYPE_MASK 0x3fUL 2011 #define CREQ_QP_EVENT_TYPE_SFT 0 2012 #define CREQ_QP_EVENT_TYPE_QP_EVENT 0x38UL 2013 #define CREQ_QP_EVENT_RESERVED2_MASK 0xc0UL 2014 #define CREQ_QP_EVENT_RESERVED2_SFT 6 2015 u8 status; 2016 __le16 cookie; 2017 __le32 reserved32; 2018 u8 v; 2019 #define CREQ_QP_EVENT_V 0x1UL 2020 #define CREQ_QP_EVENT_RESERVED7_MASK 0xfeUL 2021 #define CREQ_QP_EVENT_RESERVED7_SFT 1 2022 u8 event; 2023 #define CREQ_QP_EVENT_EVENT_CREATE_QP 0x1UL 2024 #define CREQ_QP_EVENT_EVENT_DESTROY_QP 0x2UL 2025 #define CREQ_QP_EVENT_EVENT_MODIFY_QP 0x3UL 2026 #define CREQ_QP_EVENT_EVENT_QUERY_QP 0x4UL 2027 #define CREQ_QP_EVENT_EVENT_CREATE_SRQ 0x5UL 2028 #define CREQ_QP_EVENT_EVENT_DESTROY_SRQ 0x6UL 2029 #define CREQ_QP_EVENT_EVENT_QUERY_SRQ 0x8UL 2030 #define CREQ_QP_EVENT_EVENT_CREATE_CQ 0x9UL 2031 #define CREQ_QP_EVENT_EVENT_DESTROY_CQ 0xaUL 2032 #define CREQ_QP_EVENT_EVENT_RESIZE_CQ 0xcUL 2033 #define CREQ_QP_EVENT_EVENT_ALLOCATE_MRW 0xdUL 2034 #define CREQ_QP_EVENT_EVENT_DEALLOCATE_KEY 0xeUL 2035 #define CREQ_QP_EVENT_EVENT_REGISTER_MR 0xfUL 2036 #define CREQ_QP_EVENT_EVENT_DEREGISTER_MR 0x10UL 2037 #define CREQ_QP_EVENT_EVENT_ADD_GID 0x11UL 2038 #define CREQ_QP_EVENT_EVENT_DELETE_GID 0x12UL 2039 #define CREQ_QP_EVENT_EVENT_MODIFY_GID 0x17UL 2040 #define CREQ_QP_EVENT_EVENT_QUERY_GID 0x18UL 2041 #define CREQ_QP_EVENT_EVENT_CREATE_QP1 0x13UL 2042 #define CREQ_QP_EVENT_EVENT_DESTROY_QP1 0x14UL 2043 #define CREQ_QP_EVENT_EVENT_CREATE_AH 0x15UL 2044 #define CREQ_QP_EVENT_EVENT_DESTROY_AH 0x16UL 2045 #define CREQ_QP_EVENT_EVENT_INITIALIZE_FW 0x80UL 2046 #define CREQ_QP_EVENT_EVENT_DEINITIALIZE_FW 0x81UL 2047 #define CREQ_QP_EVENT_EVENT_STOP_FUNC 0x82UL 2048 #define CREQ_QP_EVENT_EVENT_QUERY_FUNC 0x83UL 2049 #define CREQ_QP_EVENT_EVENT_SET_FUNC_RESOURCES 0x84UL 2050 #define CREQ_QP_EVENT_EVENT_MAP_TC_TO_COS 0x8aUL 2051 #define CREQ_QP_EVENT_EVENT_QUERY_VERSION 0x8bUL 2052 #define CREQ_QP_EVENT_EVENT_MODIFY_CC 0x8cUL 2053 #define CREQ_QP_EVENT_EVENT_QUERY_CC 0x8dUL 2054 #define CREQ_QP_EVENT_EVENT_QP_ERROR_NOTIFICATION 0xc0UL 2055 __le16 reserved48[3]; 2056 }; 2057 2058 /* Create QP command response (16 bytes) */ 2059 struct creq_create_qp_resp { 2060 u8 type; 2061 #define CREQ_CREATE_QP_RESP_TYPE_MASK 0x3fUL 2062 #define CREQ_CREATE_QP_RESP_TYPE_SFT 0 2063 #define CREQ_CREATE_QP_RESP_TYPE_QP_EVENT 0x38UL 2064 #define CREQ_CREATE_QP_RESP_RESERVED2_MASK 0xc0UL 2065 #define CREQ_CREATE_QP_RESP_RESERVED2_SFT 6 2066 u8 status; 2067 __le16 cookie; 2068 __le32 xid; 2069 u8 v; 2070 #define CREQ_CREATE_QP_RESP_V 0x1UL 2071 #define CREQ_CREATE_QP_RESP_RESERVED7_MASK 0xfeUL 2072 #define CREQ_CREATE_QP_RESP_RESERVED7_SFT 1 2073 u8 event; 2074 #define CREQ_CREATE_QP_RESP_EVENT_CREATE_QP 0x1UL 2075 __le16 reserved48[3]; 2076 }; 2077 2078 /* Destroy QP command response (16 bytes) */ 2079 struct creq_destroy_qp_resp { 2080 u8 type; 2081 #define CREQ_DESTROY_QP_RESP_TYPE_MASK 0x3fUL 2082 #define CREQ_DESTROY_QP_RESP_TYPE_SFT 0 2083 #define CREQ_DESTROY_QP_RESP_TYPE_QP_EVENT 0x38UL 2084 #define CREQ_DESTROY_QP_RESP_RESERVED2_MASK 0xc0UL 2085 #define CREQ_DESTROY_QP_RESP_RESERVED2_SFT 6 2086 u8 status; 2087 __le16 cookie; 2088 __le32 xid; 2089 u8 v; 2090 #define CREQ_DESTROY_QP_RESP_V 0x1UL 2091 #define CREQ_DESTROY_QP_RESP_RESERVED7_MASK 0xfeUL 2092 #define CREQ_DESTROY_QP_RESP_RESERVED7_SFT 1 2093 u8 event; 2094 #define CREQ_DESTROY_QP_RESP_EVENT_DESTROY_QP 0x2UL 2095 __le16 reserved48[3]; 2096 }; 2097 2098 /* Modify QP command response (16 bytes) */ 2099 struct creq_modify_qp_resp { 2100 u8 type; 2101 #define CREQ_MODIFY_QP_RESP_TYPE_MASK 0x3fUL 2102 #define CREQ_MODIFY_QP_RESP_TYPE_SFT 0 2103 #define CREQ_MODIFY_QP_RESP_TYPE_QP_EVENT 0x38UL 2104 #define CREQ_MODIFY_QP_RESP_RESERVED2_MASK 0xc0UL 2105 #define CREQ_MODIFY_QP_RESP_RESERVED2_SFT 6 2106 u8 status; 2107 __le16 cookie; 2108 __le32 xid; 2109 u8 v; 2110 #define CREQ_MODIFY_QP_RESP_V 0x1UL 2111 #define CREQ_MODIFY_QP_RESP_RESERVED7_MASK 0xfeUL 2112 #define CREQ_MODIFY_QP_RESP_RESERVED7_SFT 1 2113 u8 event; 2114 #define CREQ_MODIFY_QP_RESP_EVENT_MODIFY_QP 0x3UL 2115 __le16 reserved48[3]; 2116 }; 2117 2118 /* cmdq_query_roce_stats (size:128b/16B) */ 2119 struct cmdq_query_roce_stats { 2120 u8 opcode; 2121 #define CMDQ_QUERY_ROCE_STATS_OPCODE_QUERY_ROCE_STATS 0x8eUL 2122 #define CMDQ_QUERY_ROCE_STATS_OPCODE_LAST \ 2123 CMDQ_QUERY_ROCE_STATS_OPCODE_QUERY_ROCE_STATS 2124 u8 cmd_size; 2125 __le16 flags; 2126 __le16 cookie; 2127 u8 resp_size; 2128 u8 reserved8; 2129 __le64 resp_addr; 2130 }; 2131 2132 /* Query QP command response (16 bytes) */ 2133 struct creq_query_qp_resp { 2134 u8 type; 2135 #define CREQ_QUERY_QP_RESP_TYPE_MASK 0x3fUL 2136 #define CREQ_QUERY_QP_RESP_TYPE_SFT 0 2137 #define CREQ_QUERY_QP_RESP_TYPE_QP_EVENT 0x38UL 2138 #define CREQ_QUERY_QP_RESP_RESERVED2_MASK 0xc0UL 2139 #define CREQ_QUERY_QP_RESP_RESERVED2_SFT 6 2140 u8 status; 2141 __le16 cookie; 2142 __le32 size; 2143 u8 v; 2144 #define CREQ_QUERY_QP_RESP_V 0x1UL 2145 #define CREQ_QUERY_QP_RESP_RESERVED7_MASK 0xfeUL 2146 #define CREQ_QUERY_QP_RESP_RESERVED7_SFT 1 2147 u8 event; 2148 #define CREQ_QUERY_QP_RESP_EVENT_QUERY_QP 0x4UL 2149 __le16 reserved48[3]; 2150 }; 2151 2152 /* Query QP command response side buffer structure (104 bytes) */ 2153 struct creq_query_qp_resp_sb { 2154 u8 opcode; 2155 #define CREQ_QUERY_QP_RESP_SB_OPCODE_QUERY_QP 0x4UL 2156 u8 status; 2157 __le16 cookie; 2158 __le16 flags; 2159 u8 resp_size; 2160 u8 reserved8; 2161 __le32 xid; 2162 u8 en_sqd_async_notify_state; 2163 #define CREQ_QUERY_QP_RESP_SB_STATE_MASK 0xfUL 2164 #define CREQ_QUERY_QP_RESP_SB_STATE_SFT 0 2165 #define CREQ_QUERY_QP_RESP_SB_STATE_RESET 0x0UL 2166 #define CREQ_QUERY_QP_RESP_SB_STATE_INIT 0x1UL 2167 #define CREQ_QUERY_QP_RESP_SB_STATE_RTR 0x2UL 2168 #define CREQ_QUERY_QP_RESP_SB_STATE_RTS 0x3UL 2169 #define CREQ_QUERY_QP_RESP_SB_STATE_SQD 0x4UL 2170 #define CREQ_QUERY_QP_RESP_SB_STATE_SQE 0x5UL 2171 #define CREQ_QUERY_QP_RESP_SB_STATE_ERR 0x6UL 2172 #define CREQ_QUERY_QP_RESP_SB_EN_SQD_ASYNC_NOTIFY 0x10UL 2173 u8 access; 2174 #define CREQ_QUERY_QP_RESP_SB_ACCESS_LOCAL_WRITE 0x1UL 2175 #define CREQ_QUERY_QP_RESP_SB_ACCESS_REMOTE_WRITE 0x2UL 2176 #define CREQ_QUERY_QP_RESP_SB_ACCESS_REMOTE_READ 0x4UL 2177 #define CREQ_QUERY_QP_RESP_SB_ACCESS_REMOTE_ATOMIC 0x8UL 2178 __le16 pkey; 2179 __le32 qkey; 2180 __le32 reserved32; 2181 __le32 dgid[4]; 2182 __le32 flow_label; 2183 __le16 sgid_index; 2184 u8 hop_limit; 2185 u8 traffic_class; 2186 __le16 dest_mac[3]; 2187 __le16 path_mtu_dest_vlan_id; 2188 #define CREQ_QUERY_QP_RESP_SB_DEST_VLAN_ID_MASK 0xfffUL 2189 #define CREQ_QUERY_QP_RESP_SB_DEST_VLAN_ID_SFT 0 2190 #define CREQ_QUERY_QP_RESP_SB_PATH_MTU_MASK 0xf000UL 2191 #define CREQ_QUERY_QP_RESP_SB_PATH_MTU_SFT 12 2192 #define CREQ_QUERY_QP_RESP_SB_PATH_MTU_MTU_256 (0x0UL << 12) 2193 #define CREQ_QUERY_QP_RESP_SB_PATH_MTU_MTU_512 (0x1UL << 12) 2194 #define CREQ_QUERY_QP_RESP_SB_PATH_MTU_MTU_1024 (0x2UL << 12) 2195 #define CREQ_QUERY_QP_RESP_SB_PATH_MTU_MTU_2048 (0x3UL << 12) 2196 #define CREQ_QUERY_QP_RESP_SB_PATH_MTU_MTU_4096 (0x4UL << 12) 2197 #define CREQ_QUERY_QP_RESP_SB_PATH_MTU_MTU_8192 (0x5UL << 12) 2198 u8 timeout; 2199 u8 retry_cnt; 2200 u8 rnr_retry; 2201 u8 min_rnr_timer; 2202 __le32 rq_psn; 2203 __le32 sq_psn; 2204 u8 max_rd_atomic; 2205 u8 max_dest_rd_atomic; 2206 u8 tos_dscp_tos_ecn; 2207 #define CREQ_QUERY_QP_RESP_SB_TOS_ECN_MASK 0x3UL 2208 #define CREQ_QUERY_QP_RESP_SB_TOS_ECN_SFT 0 2209 #define CREQ_QUERY_QP_RESP_SB_TOS_DSCP_MASK 0xfcUL 2210 #define CREQ_QUERY_QP_RESP_SB_TOS_DSCP_SFT 2 2211 u8 enable_cc; 2212 #define CREQ_QUERY_QP_RESP_SB_ENABLE_CC 0x1UL 2213 #define CREQ_QUERY_QP_RESP_SB_RESERVED7_MASK 0xfeUL 2214 #define CREQ_QUERY_QP_RESP_SB_RESERVED7_SFT 1 2215 __le32 sq_size; 2216 __le32 rq_size; 2217 __le16 sq_sge; 2218 __le16 rq_sge; 2219 __le32 max_inline_data; 2220 __le32 dest_qp_id; 2221 __le32 unused_1; 2222 __le16 src_mac[3]; 2223 __le16 vlan_pcp_vlan_dei_vlan_id; 2224 #define CREQ_QUERY_QP_RESP_SB_VLAN_ID_MASK 0xfffUL 2225 #define CREQ_QUERY_QP_RESP_SB_VLAN_ID_SFT 0 2226 #define CREQ_QUERY_QP_RESP_SB_VLAN_DEI 0x1000UL 2227 #define CREQ_QUERY_QP_RESP_SB_VLAN_PCP_MASK 0xe000UL 2228 #define CREQ_QUERY_QP_RESP_SB_VLAN_PCP_SFT 13 2229 }; 2230 2231 /* Create SRQ command response (16 bytes) */ 2232 struct creq_create_srq_resp { 2233 u8 type; 2234 #define CREQ_CREATE_SRQ_RESP_TYPE_MASK 0x3fUL 2235 #define CREQ_CREATE_SRQ_RESP_TYPE_SFT 0 2236 #define CREQ_CREATE_SRQ_RESP_TYPE_QP_EVENT 0x38UL 2237 #define CREQ_CREATE_SRQ_RESP_RESERVED2_MASK 0xc0UL 2238 #define CREQ_CREATE_SRQ_RESP_RESERVED2_SFT 6 2239 u8 status; 2240 __le16 cookie; 2241 __le32 xid; 2242 u8 v; 2243 #define CREQ_CREATE_SRQ_RESP_V 0x1UL 2244 #define CREQ_CREATE_SRQ_RESP_RESERVED7_MASK 0xfeUL 2245 #define CREQ_CREATE_SRQ_RESP_RESERVED7_SFT 1 2246 u8 event; 2247 #define CREQ_CREATE_SRQ_RESP_EVENT_CREATE_SRQ 0x5UL 2248 __le16 reserved48[3]; 2249 }; 2250 2251 /* Destroy SRQ command response (16 bytes) */ 2252 struct creq_destroy_srq_resp { 2253 u8 type; 2254 #define CREQ_DESTROY_SRQ_RESP_TYPE_MASK 0x3fUL 2255 #define CREQ_DESTROY_SRQ_RESP_TYPE_SFT 0 2256 #define CREQ_DESTROY_SRQ_RESP_TYPE_QP_EVENT 0x38UL 2257 #define CREQ_DESTROY_SRQ_RESP_RESERVED2_MASK 0xc0UL 2258 #define CREQ_DESTROY_SRQ_RESP_RESERVED2_SFT 6 2259 u8 status; 2260 __le16 cookie; 2261 __le32 xid; 2262 u8 v; 2263 #define CREQ_DESTROY_SRQ_RESP_V 0x1UL 2264 #define CREQ_DESTROY_SRQ_RESP_RESERVED7_MASK 0xfeUL 2265 #define CREQ_DESTROY_SRQ_RESP_RESERVED7_SFT 1 2266 u8 event; 2267 #define CREQ_DESTROY_SRQ_RESP_EVENT_DESTROY_SRQ 0x6UL 2268 __le16 enable_for_arm[3]; 2269 #define CREQ_DESTROY_SRQ_RESP_ENABLE_FOR_ARM_MASK 0x30000UL 2270 #define CREQ_DESTROY_SRQ_RESP_ENABLE_FOR_ARM_SFT 16 2271 #define CREQ_DESTROY_SRQ_RESP_RESERVED46_MASK 0xfffc0000UL 2272 #define CREQ_DESTROY_SRQ_RESP_RESERVED46_SFT 18 2273 }; 2274 2275 /* Query SRQ command response (16 bytes) */ 2276 struct creq_query_srq_resp { 2277 u8 type; 2278 #define CREQ_QUERY_SRQ_RESP_TYPE_MASK 0x3fUL 2279 #define CREQ_QUERY_SRQ_RESP_TYPE_SFT 0 2280 #define CREQ_QUERY_SRQ_RESP_TYPE_QP_EVENT 0x38UL 2281 #define CREQ_QUERY_SRQ_RESP_RESERVED2_MASK 0xc0UL 2282 #define CREQ_QUERY_SRQ_RESP_RESERVED2_SFT 6 2283 u8 status; 2284 __le16 cookie; 2285 __le32 size; 2286 u8 v; 2287 #define CREQ_QUERY_SRQ_RESP_V 0x1UL 2288 #define CREQ_QUERY_SRQ_RESP_RESERVED7_MASK 0xfeUL 2289 #define CREQ_QUERY_SRQ_RESP_RESERVED7_SFT 1 2290 u8 event; 2291 #define CREQ_QUERY_SRQ_RESP_EVENT_QUERY_SRQ 0x8UL 2292 __le16 reserved48[3]; 2293 }; 2294 2295 /* Query SRQ command response side buffer structure (24 bytes) */ 2296 struct creq_query_srq_resp_sb { 2297 u8 opcode; 2298 #define CREQ_QUERY_SRQ_RESP_SB_OPCODE_QUERY_SRQ 0x8UL 2299 u8 status; 2300 __le16 cookie; 2301 __le16 flags; 2302 u8 resp_size; 2303 u8 reserved8; 2304 __le32 xid; 2305 __le16 srq_limit; 2306 __le16 reserved16; 2307 __le32 data[4]; 2308 }; 2309 2310 /* Create CQ command Response (16 bytes) */ 2311 struct creq_create_cq_resp { 2312 u8 type; 2313 #define CREQ_CREATE_CQ_RESP_TYPE_MASK 0x3fUL 2314 #define CREQ_CREATE_CQ_RESP_TYPE_SFT 0 2315 #define CREQ_CREATE_CQ_RESP_TYPE_QP_EVENT 0x38UL 2316 #define CREQ_CREATE_CQ_RESP_RESERVED2_MASK 0xc0UL 2317 #define CREQ_CREATE_CQ_RESP_RESERVED2_SFT 6 2318 u8 status; 2319 __le16 cookie; 2320 __le32 xid; 2321 u8 v; 2322 #define CREQ_CREATE_CQ_RESP_V 0x1UL 2323 #define CREQ_CREATE_CQ_RESP_RESERVED7_MASK 0xfeUL 2324 #define CREQ_CREATE_CQ_RESP_RESERVED7_SFT 1 2325 u8 event; 2326 #define CREQ_CREATE_CQ_RESP_EVENT_CREATE_CQ 0x9UL 2327 __le16 reserved48[3]; 2328 }; 2329 2330 /* Destroy CQ command response (16 bytes) */ 2331 struct creq_destroy_cq_resp { 2332 u8 type; 2333 #define CREQ_DESTROY_CQ_RESP_TYPE_MASK 0x3fUL 2334 #define CREQ_DESTROY_CQ_RESP_TYPE_SFT 0 2335 #define CREQ_DESTROY_CQ_RESP_TYPE_QP_EVENT 0x38UL 2336 #define CREQ_DESTROY_CQ_RESP_RESERVED2_MASK 0xc0UL 2337 #define CREQ_DESTROY_CQ_RESP_RESERVED2_SFT 6 2338 u8 status; 2339 __le16 cookie; 2340 __le32 xid; 2341 u8 v; 2342 #define CREQ_DESTROY_CQ_RESP_V 0x1UL 2343 #define CREQ_DESTROY_CQ_RESP_RESERVED7_MASK 0xfeUL 2344 #define CREQ_DESTROY_CQ_RESP_RESERVED7_SFT 1 2345 u8 event; 2346 #define CREQ_DESTROY_CQ_RESP_EVENT_DESTROY_CQ 0xaUL 2347 __le16 cq_arm_lvl; 2348 #define CREQ_DESTROY_CQ_RESP_CQ_ARM_LVL_MASK 0x3UL 2349 #define CREQ_DESTROY_CQ_RESP_CQ_ARM_LVL_SFT 0 2350 #define CREQ_DESTROY_CQ_RESP_RESERVED14_MASK 0xfffcUL 2351 #define CREQ_DESTROY_CQ_RESP_RESERVED14_SFT 2 2352 __le16 total_cnq_events; 2353 __le16 reserved16; 2354 }; 2355 2356 /* Resize CQ command response (16 bytes) */ 2357 struct creq_resize_cq_resp { 2358 u8 type; 2359 #define CREQ_RESIZE_CQ_RESP_TYPE_MASK 0x3fUL 2360 #define CREQ_RESIZE_CQ_RESP_TYPE_SFT 0 2361 #define CREQ_RESIZE_CQ_RESP_TYPE_QP_EVENT 0x38UL 2362 #define CREQ_RESIZE_CQ_RESP_RESERVED2_MASK 0xc0UL 2363 #define CREQ_RESIZE_CQ_RESP_RESERVED2_SFT 6 2364 u8 status; 2365 __le16 cookie; 2366 __le32 xid; 2367 u8 v; 2368 #define CREQ_RESIZE_CQ_RESP_V 0x1UL 2369 #define CREQ_RESIZE_CQ_RESP_RESERVED7_MASK 0xfeUL 2370 #define CREQ_RESIZE_CQ_RESP_RESERVED7_SFT 1 2371 u8 event; 2372 #define CREQ_RESIZE_CQ_RESP_EVENT_RESIZE_CQ 0xcUL 2373 __le16 reserved48[3]; 2374 }; 2375 2376 /* Allocate MRW command response (16 bytes) */ 2377 struct creq_allocate_mrw_resp { 2378 u8 type; 2379 #define CREQ_ALLOCATE_MRW_RESP_TYPE_MASK 0x3fUL 2380 #define CREQ_ALLOCATE_MRW_RESP_TYPE_SFT 0 2381 #define CREQ_ALLOCATE_MRW_RESP_TYPE_QP_EVENT 0x38UL 2382 #define CREQ_ALLOCATE_MRW_RESP_RESERVED2_MASK 0xc0UL 2383 #define CREQ_ALLOCATE_MRW_RESP_RESERVED2_SFT 6 2384 u8 status; 2385 __le16 cookie; 2386 __le32 xid; 2387 u8 v; 2388 #define CREQ_ALLOCATE_MRW_RESP_V 0x1UL 2389 #define CREQ_ALLOCATE_MRW_RESP_RESERVED7_MASK 0xfeUL 2390 #define CREQ_ALLOCATE_MRW_RESP_RESERVED7_SFT 1 2391 u8 event; 2392 #define CREQ_ALLOCATE_MRW_RESP_EVENT_ALLOCATE_MRW 0xdUL 2393 __le16 reserved48[3]; 2394 }; 2395 2396 /* De-allocate key command response (16 bytes) */ 2397 struct creq_deallocate_key_resp { 2398 u8 type; 2399 #define CREQ_DEALLOCATE_KEY_RESP_TYPE_MASK 0x3fUL 2400 #define CREQ_DEALLOCATE_KEY_RESP_TYPE_SFT 0 2401 #define CREQ_DEALLOCATE_KEY_RESP_TYPE_QP_EVENT 0x38UL 2402 #define CREQ_DEALLOCATE_KEY_RESP_RESERVED2_MASK 0xc0UL 2403 #define CREQ_DEALLOCATE_KEY_RESP_RESERVED2_SFT 6 2404 u8 status; 2405 __le16 cookie; 2406 __le32 xid; 2407 u8 v; 2408 #define CREQ_DEALLOCATE_KEY_RESP_V 0x1UL 2409 #define CREQ_DEALLOCATE_KEY_RESP_RESERVED7_MASK 0xfeUL 2410 #define CREQ_DEALLOCATE_KEY_RESP_RESERVED7_SFT 1 2411 u8 event; 2412 #define CREQ_DEALLOCATE_KEY_RESP_EVENT_DEALLOCATE_KEY 0xeUL 2413 __le16 reserved16; 2414 __le32 bound_window_info; 2415 }; 2416 2417 /* Register MR command response (16 bytes) */ 2418 struct creq_register_mr_resp { 2419 u8 type; 2420 #define CREQ_REGISTER_MR_RESP_TYPE_MASK 0x3fUL 2421 #define CREQ_REGISTER_MR_RESP_TYPE_SFT 0 2422 #define CREQ_REGISTER_MR_RESP_TYPE_QP_EVENT 0x38UL 2423 #define CREQ_REGISTER_MR_RESP_RESERVED2_MASK 0xc0UL 2424 #define CREQ_REGISTER_MR_RESP_RESERVED2_SFT 6 2425 u8 status; 2426 __le16 cookie; 2427 __le32 xid; 2428 u8 v; 2429 #define CREQ_REGISTER_MR_RESP_V 0x1UL 2430 #define CREQ_REGISTER_MR_RESP_RESERVED7_MASK 0xfeUL 2431 #define CREQ_REGISTER_MR_RESP_RESERVED7_SFT 1 2432 u8 event; 2433 #define CREQ_REGISTER_MR_RESP_EVENT_REGISTER_MR 0xfUL 2434 __le16 reserved48[3]; 2435 }; 2436 2437 /* Deregister MR command response (16 bytes) */ 2438 struct creq_deregister_mr_resp { 2439 u8 type; 2440 #define CREQ_DEREGISTER_MR_RESP_TYPE_MASK 0x3fUL 2441 #define CREQ_DEREGISTER_MR_RESP_TYPE_SFT 0 2442 #define CREQ_DEREGISTER_MR_RESP_TYPE_QP_EVENT 0x38UL 2443 #define CREQ_DEREGISTER_MR_RESP_RESERVED2_MASK 0xc0UL 2444 #define CREQ_DEREGISTER_MR_RESP_RESERVED2_SFT 6 2445 u8 status; 2446 __le16 cookie; 2447 __le32 xid; 2448 u8 v; 2449 #define CREQ_DEREGISTER_MR_RESP_V 0x1UL 2450 #define CREQ_DEREGISTER_MR_RESP_RESERVED7_MASK 0xfeUL 2451 #define CREQ_DEREGISTER_MR_RESP_RESERVED7_SFT 1 2452 u8 event; 2453 #define CREQ_DEREGISTER_MR_RESP_EVENT_DEREGISTER_MR 0x10UL 2454 __le16 reserved16; 2455 __le32 bound_windows; 2456 }; 2457 2458 /* Add GID command response (16 bytes) */ 2459 struct creq_add_gid_resp { 2460 u8 type; 2461 #define CREQ_ADD_GID_RESP_TYPE_MASK 0x3fUL 2462 #define CREQ_ADD_GID_RESP_TYPE_SFT 0 2463 #define CREQ_ADD_GID_RESP_TYPE_QP_EVENT 0x38UL 2464 #define CREQ_ADD_GID_RESP_RESERVED2_MASK 0xc0UL 2465 #define CREQ_ADD_GID_RESP_RESERVED2_SFT 6 2466 u8 status; 2467 __le16 cookie; 2468 __le32 xid; 2469 u8 v; 2470 #define CREQ_ADD_GID_RESP_V 0x1UL 2471 #define CREQ_ADD_GID_RESP_RESERVED7_MASK 0xfeUL 2472 #define CREQ_ADD_GID_RESP_RESERVED7_SFT 1 2473 u8 event; 2474 #define CREQ_ADD_GID_RESP_EVENT_ADD_GID 0x11UL 2475 __le16 reserved48[3]; 2476 }; 2477 2478 /* Delete GID command response (16 bytes) */ 2479 struct creq_delete_gid_resp { 2480 u8 type; 2481 #define CREQ_DELETE_GID_RESP_TYPE_MASK 0x3fUL 2482 #define CREQ_DELETE_GID_RESP_TYPE_SFT 0 2483 #define CREQ_DELETE_GID_RESP_TYPE_QP_EVENT 0x38UL 2484 #define CREQ_DELETE_GID_RESP_RESERVED2_MASK 0xc0UL 2485 #define CREQ_DELETE_GID_RESP_RESERVED2_SFT 6 2486 u8 status; 2487 __le16 cookie; 2488 __le32 xid; 2489 u8 v; 2490 #define CREQ_DELETE_GID_RESP_V 0x1UL 2491 #define CREQ_DELETE_GID_RESP_RESERVED7_MASK 0xfeUL 2492 #define CREQ_DELETE_GID_RESP_RESERVED7_SFT 1 2493 u8 event; 2494 #define CREQ_DELETE_GID_RESP_EVENT_DELETE_GID 0x12UL 2495 __le16 reserved48[3]; 2496 }; 2497 2498 /* Modify GID command response (16 bytes) */ 2499 struct creq_modify_gid_resp { 2500 u8 type; 2501 #define CREQ_MODIFY_GID_RESP_TYPE_MASK 0x3fUL 2502 #define CREQ_MODIFY_GID_RESP_TYPE_SFT 0 2503 #define CREQ_MODIFY_GID_RESP_TYPE_QP_EVENT 0x38UL 2504 #define CREQ_MODIFY_GID_RESP_RESERVED2_MASK 0xc0UL 2505 #define CREQ_MODIFY_GID_RESP_RESERVED2_SFT 6 2506 u8 status; 2507 __le16 cookie; 2508 __le32 xid; 2509 u8 v; 2510 #define CREQ_MODIFY_GID_RESP_V 0x1UL 2511 #define CREQ_MODIFY_GID_RESP_RESERVED7_MASK 0xfeUL 2512 #define CREQ_MODIFY_GID_RESP_RESERVED7_SFT 1 2513 u8 event; 2514 #define CREQ_MODIFY_GID_RESP_EVENT_ADD_GID 0x11UL 2515 __le16 reserved48[3]; 2516 }; 2517 2518 /* Query GID command response (16 bytes) */ 2519 struct creq_query_gid_resp { 2520 u8 type; 2521 #define CREQ_QUERY_GID_RESP_TYPE_MASK 0x3fUL 2522 #define CREQ_QUERY_GID_RESP_TYPE_SFT 0 2523 #define CREQ_QUERY_GID_RESP_TYPE_QP_EVENT 0x38UL 2524 #define CREQ_QUERY_GID_RESP_RESERVED2_MASK 0xc0UL 2525 #define CREQ_QUERY_GID_RESP_RESERVED2_SFT 6 2526 u8 status; 2527 __le16 cookie; 2528 __le32 size; 2529 u8 v; 2530 #define CREQ_QUERY_GID_RESP_V 0x1UL 2531 #define CREQ_QUERY_GID_RESP_RESERVED7_MASK 0xfeUL 2532 #define CREQ_QUERY_GID_RESP_RESERVED7_SFT 1 2533 u8 event; 2534 #define CREQ_QUERY_GID_RESP_EVENT_QUERY_GID 0x18UL 2535 __le16 reserved48[3]; 2536 }; 2537 2538 /* Query GID command response side buffer structure (40 bytes) */ 2539 struct creq_query_gid_resp_sb { 2540 u8 opcode; 2541 #define CREQ_QUERY_GID_RESP_SB_OPCODE_QUERY_GID 0x18UL 2542 u8 status; 2543 __le16 cookie; 2544 __le16 flags; 2545 u8 resp_size; 2546 u8 reserved8; 2547 __le32 gid[4]; 2548 __le16 src_mac[3]; 2549 __le16 vlan; 2550 #define CREQ_QUERY_GID_RESP_SB_VLAN_VLAN_ID_MASK 0xfffUL 2551 #define CREQ_QUERY_GID_RESP_SB_VLAN_VLAN_ID_SFT 0 2552 #define CREQ_QUERY_GID_RESP_SB_VLAN_TPID_MASK 0x7000UL 2553 #define CREQ_QUERY_GID_RESP_SB_VLAN_TPID_SFT 12 2554 #define CREQ_QUERY_GID_RESP_SB_VLAN_TPID_TPID_88A8 (0x0UL << 12) 2555 #define CREQ_QUERY_GID_RESP_SB_VLAN_TPID_TPID_8100 (0x1UL << 12) 2556 #define CREQ_QUERY_GID_RESP_SB_VLAN_TPID_TPID_9100 (0x2UL << 12) 2557 #define CREQ_QUERY_GID_RESP_SB_VLAN_TPID_TPID_9200 (0x3UL << 12) 2558 #define CREQ_QUERY_GID_RESP_SB_VLAN_TPID_TPID_9300 (0x4UL << 12) 2559 #define CREQ_QUERY_GID_RESP_SB_VLAN_TPID_TPID_CFG1 (0x5UL << 12) 2560 #define CREQ_QUERY_GID_RESP_SB_VLAN_TPID_TPID_CFG2 (0x6UL << 12) 2561 #define CREQ_QUERY_GID_RESP_SB_VLAN_TPID_TPID_CFG3 (0x7UL << 12) 2562 #define CREQ_QUERY_GID_RESP_SB_VLAN_TPID_LAST \ 2563 CREQ_QUERY_GID_RESP_SB_VLAN_TPID_TPID_CFG3 2564 #define CREQ_QUERY_GID_RESP_SB_VLAN_VLAN_EN 0x8000UL 2565 __le16 ipid; 2566 __le16 gid_index; 2567 __le32 unused_0; 2568 }; 2569 2570 /* Create QP1 command response (16 bytes) */ 2571 struct creq_create_qp1_resp { 2572 u8 type; 2573 #define CREQ_CREATE_QP1_RESP_TYPE_MASK 0x3fUL 2574 #define CREQ_CREATE_QP1_RESP_TYPE_SFT 0 2575 #define CREQ_CREATE_QP1_RESP_TYPE_QP_EVENT 0x38UL 2576 #define CREQ_CREATE_QP1_RESP_RESERVED2_MASK 0xc0UL 2577 #define CREQ_CREATE_QP1_RESP_RESERVED2_SFT 6 2578 u8 status; 2579 __le16 cookie; 2580 __le32 xid; 2581 u8 v; 2582 #define CREQ_CREATE_QP1_RESP_V 0x1UL 2583 #define CREQ_CREATE_QP1_RESP_RESERVED7_MASK 0xfeUL 2584 #define CREQ_CREATE_QP1_RESP_RESERVED7_SFT 1 2585 u8 event; 2586 #define CREQ_CREATE_QP1_RESP_EVENT_CREATE_QP1 0x13UL 2587 __le16 reserved48[3]; 2588 }; 2589 2590 /* Destroy QP1 command response (16 bytes) */ 2591 struct creq_destroy_qp1_resp { 2592 u8 type; 2593 #define CREQ_DESTROY_QP1_RESP_TYPE_MASK 0x3fUL 2594 #define CREQ_DESTROY_QP1_RESP_TYPE_SFT 0 2595 #define CREQ_DESTROY_QP1_RESP_TYPE_QP_EVENT 0x38UL 2596 #define CREQ_DESTROY_QP1_RESP_RESERVED2_MASK 0xc0UL 2597 #define CREQ_DESTROY_QP1_RESP_RESERVED2_SFT 6 2598 u8 status; 2599 __le16 cookie; 2600 __le32 xid; 2601 u8 v; 2602 #define CREQ_DESTROY_QP1_RESP_V 0x1UL 2603 #define CREQ_DESTROY_QP1_RESP_RESERVED7_MASK 0xfeUL 2604 #define CREQ_DESTROY_QP1_RESP_RESERVED7_SFT 1 2605 u8 event; 2606 #define CREQ_DESTROY_QP1_RESP_EVENT_DESTROY_QP1 0x14UL 2607 __le16 reserved48[3]; 2608 }; 2609 2610 /* Create AH command response (16 bytes) */ 2611 struct creq_create_ah_resp { 2612 u8 type; 2613 #define CREQ_CREATE_AH_RESP_TYPE_MASK 0x3fUL 2614 #define CREQ_CREATE_AH_RESP_TYPE_SFT 0 2615 #define CREQ_CREATE_AH_RESP_TYPE_QP_EVENT 0x38UL 2616 #define CREQ_CREATE_AH_RESP_RESERVED2_MASK 0xc0UL 2617 #define CREQ_CREATE_AH_RESP_RESERVED2_SFT 6 2618 u8 status; 2619 __le16 cookie; 2620 __le32 xid; 2621 u8 v; 2622 #define CREQ_CREATE_AH_RESP_V 0x1UL 2623 #define CREQ_CREATE_AH_RESP_RESERVED7_MASK 0xfeUL 2624 #define CREQ_CREATE_AH_RESP_RESERVED7_SFT 1 2625 u8 event; 2626 #define CREQ_CREATE_AH_RESP_EVENT_CREATE_AH 0x15UL 2627 __le16 reserved48[3]; 2628 }; 2629 2630 /* Destroy AH command response (16 bytes) */ 2631 struct creq_destroy_ah_resp { 2632 u8 type; 2633 #define CREQ_DESTROY_AH_RESP_TYPE_MASK 0x3fUL 2634 #define CREQ_DESTROY_AH_RESP_TYPE_SFT 0 2635 #define CREQ_DESTROY_AH_RESP_TYPE_QP_EVENT 0x38UL 2636 #define CREQ_DESTROY_AH_RESP_RESERVED2_MASK 0xc0UL 2637 #define CREQ_DESTROY_AH_RESP_RESERVED2_SFT 6 2638 u8 status; 2639 __le16 cookie; 2640 __le32 xid; 2641 u8 v; 2642 #define CREQ_DESTROY_AH_RESP_V 0x1UL 2643 #define CREQ_DESTROY_AH_RESP_RESERVED7_MASK 0xfeUL 2644 #define CREQ_DESTROY_AH_RESP_RESERVED7_SFT 1 2645 u8 event; 2646 #define CREQ_DESTROY_AH_RESP_EVENT_DESTROY_AH 0x16UL 2647 __le16 reserved48[3]; 2648 }; 2649 2650 /* Initialize Firmware command response (16 bytes) */ 2651 struct creq_initialize_fw_resp { 2652 u8 type; 2653 #define CREQ_INITIALIZE_FW_RESP_TYPE_MASK 0x3fUL 2654 #define CREQ_INITIALIZE_FW_RESP_TYPE_SFT 0 2655 #define CREQ_INITIALIZE_FW_RESP_TYPE_QP_EVENT 0x38UL 2656 #define CREQ_INITIALIZE_FW_RESP_RESERVED2_MASK 0xc0UL 2657 #define CREQ_INITIALIZE_FW_RESP_RESERVED2_SFT 6 2658 u8 status; 2659 __le16 cookie; 2660 __le32 reserved32; 2661 u8 v; 2662 #define CREQ_INITIALIZE_FW_RESP_V 0x1UL 2663 #define CREQ_INITIALIZE_FW_RESP_RESERVED7_MASK 0xfeUL 2664 #define CREQ_INITIALIZE_FW_RESP_RESERVED7_SFT 1 2665 u8 event; 2666 #define CREQ_INITIALIZE_FW_RESP_EVENT_INITIALIZE_FW 0x80UL 2667 __le16 reserved48[3]; 2668 }; 2669 2670 /* De-initialize Firmware command response (16 bytes) */ 2671 struct creq_deinitialize_fw_resp { 2672 u8 type; 2673 #define CREQ_DEINITIALIZE_FW_RESP_TYPE_MASK 0x3fUL 2674 #define CREQ_DEINITIALIZE_FW_RESP_TYPE_SFT 0 2675 #define CREQ_DEINITIALIZE_FW_RESP_TYPE_QP_EVENT 0x38UL 2676 #define CREQ_DEINITIALIZE_FW_RESP_RESERVED2_MASK 0xc0UL 2677 #define CREQ_DEINITIALIZE_FW_RESP_RESERVED2_SFT 6 2678 u8 status; 2679 __le16 cookie; 2680 __le32 reserved32; 2681 u8 v; 2682 #define CREQ_DEINITIALIZE_FW_RESP_V 0x1UL 2683 #define CREQ_DEINITIALIZE_FW_RESP_RESERVED7_MASK 0xfeUL 2684 #define CREQ_DEINITIALIZE_FW_RESP_RESERVED7_SFT 1 2685 u8 event; 2686 #define CREQ_DEINITIALIZE_FW_RESP_EVENT_DEINITIALIZE_FW 0x81UL 2687 __le16 reserved48[3]; 2688 }; 2689 2690 /* Stop function command response (16 bytes) */ 2691 struct creq_stop_func_resp { 2692 u8 type; 2693 #define CREQ_STOP_FUNC_RESP_TYPE_MASK 0x3fUL 2694 #define CREQ_STOP_FUNC_RESP_TYPE_SFT 0 2695 #define CREQ_STOP_FUNC_RESP_TYPE_QP_EVENT 0x38UL 2696 #define CREQ_STOP_FUNC_RESP_RESERVED2_MASK 0xc0UL 2697 #define CREQ_STOP_FUNC_RESP_RESERVED2_SFT 6 2698 u8 status; 2699 __le16 cookie; 2700 __le32 reserved32; 2701 u8 v; 2702 #define CREQ_STOP_FUNC_RESP_V 0x1UL 2703 #define CREQ_STOP_FUNC_RESP_RESERVED7_MASK 0xfeUL 2704 #define CREQ_STOP_FUNC_RESP_RESERVED7_SFT 1 2705 u8 event; 2706 #define CREQ_STOP_FUNC_RESP_EVENT_STOP_FUNC 0x82UL 2707 __le16 reserved48[3]; 2708 }; 2709 2710 /* Query function command response (16 bytes) */ 2711 struct creq_query_func_resp { 2712 u8 type; 2713 #define CREQ_QUERY_FUNC_RESP_TYPE_MASK 0x3fUL 2714 #define CREQ_QUERY_FUNC_RESP_TYPE_SFT 0 2715 #define CREQ_QUERY_FUNC_RESP_TYPE_QP_EVENT 0x38UL 2716 #define CREQ_QUERY_FUNC_RESP_RESERVED2_MASK 0xc0UL 2717 #define CREQ_QUERY_FUNC_RESP_RESERVED2_SFT 6 2718 u8 status; 2719 __le16 cookie; 2720 __le32 size; 2721 u8 v; 2722 #define CREQ_QUERY_FUNC_RESP_V 0x1UL 2723 #define CREQ_QUERY_FUNC_RESP_RESERVED7_MASK 0xfeUL 2724 #define CREQ_QUERY_FUNC_RESP_RESERVED7_SFT 1 2725 u8 event; 2726 #define CREQ_QUERY_FUNC_RESP_EVENT_QUERY_FUNC 0x83UL 2727 __le16 reserved48[3]; 2728 }; 2729 2730 /* Query function command response side buffer structure (88 bytes) */ 2731 struct creq_query_func_resp_sb { 2732 u8 opcode; 2733 #define CREQ_QUERY_FUNC_RESP_SB_OPCODE_QUERY_FUNC 0x83UL 2734 u8 status; 2735 __le16 cookie; 2736 __le16 flags; 2737 u8 resp_size; 2738 u8 reserved8; 2739 __le64 max_mr_size; 2740 __le32 max_qp; 2741 __le16 max_qp_wr; 2742 __le16 dev_cap_flags; 2743 #define CREQ_QUERY_FUNC_RESP_SB_DEV_CAP_FLAGS_RESIZE_QP 0x1UL 2744 __le32 max_cq; 2745 __le32 max_cqe; 2746 __le32 max_pd; 2747 u8 max_sge; 2748 u8 max_srq_sge; 2749 u8 max_qp_rd_atom; 2750 u8 max_qp_init_rd_atom; 2751 __le32 max_mr; 2752 __le32 max_mw; 2753 __le32 max_raw_eth_qp; 2754 __le32 max_ah; 2755 __le32 max_fmr; 2756 __le32 max_srq_wr; 2757 __le32 max_pkeys; 2758 __le32 max_inline_data; 2759 u8 max_map_per_fmr; 2760 u8 l2_db_space_size; 2761 __le16 max_srq; 2762 __le32 max_gid; 2763 __le32 tqm_alloc_reqs[12]; 2764 __le32 max_dpi; 2765 __le32 reserved_32; 2766 }; 2767 2768 /* Set resources command response (16 bytes) */ 2769 struct creq_set_func_resources_resp { 2770 u8 type; 2771 #define CREQ_SET_FUNC_RESOURCES_RESP_TYPE_MASK 0x3fUL 2772 #define CREQ_SET_FUNC_RESOURCES_RESP_TYPE_SFT 0 2773 #define CREQ_SET_FUNC_RESOURCES_RESP_TYPE_QP_EVENT 0x38UL 2774 #define CREQ_SET_FUNC_RESOURCES_RESP_RESERVED2_MASK 0xc0UL 2775 #define CREQ_SET_FUNC_RESOURCES_RESP_RESERVED2_SFT 6 2776 u8 status; 2777 __le16 cookie; 2778 __le32 reserved32; 2779 u8 v; 2780 #define CREQ_SET_FUNC_RESOURCES_RESP_V 0x1UL 2781 #define CREQ_SET_FUNC_RESOURCES_RESP_RESERVED7_MASK 0xfeUL 2782 #define CREQ_SET_FUNC_RESOURCES_RESP_RESERVED7_SFT 1 2783 u8 event; 2784 #define CREQ_SET_FUNC_RESOURCES_RESP_EVENT_SET_FUNC_RESOURCES 0x84UL 2785 __le16 reserved48[3]; 2786 }; 2787 2788 /* Map TC to COS response (16 bytes) */ 2789 struct creq_map_tc_to_cos_resp { 2790 u8 type; 2791 #define CREQ_MAP_TC_TO_COS_RESP_TYPE_MASK 0x3fUL 2792 #define CREQ_MAP_TC_TO_COS_RESP_TYPE_SFT 0 2793 #define CREQ_MAP_TC_TO_COS_RESP_TYPE_QP_EVENT 0x38UL 2794 #define CREQ_MAP_TC_TO_COS_RESP_RESERVED2_MASK 0xc0UL 2795 #define CREQ_MAP_TC_TO_COS_RESP_RESERVED2_SFT 6 2796 u8 status; 2797 __le16 cookie; 2798 __le32 reserved32; 2799 u8 v; 2800 #define CREQ_MAP_TC_TO_COS_RESP_V 0x1UL 2801 #define CREQ_MAP_TC_TO_COS_RESP_RESERVED7_MASK 0xfeUL 2802 #define CREQ_MAP_TC_TO_COS_RESP_RESERVED7_SFT 1 2803 u8 event; 2804 #define CREQ_MAP_TC_TO_COS_RESP_EVENT_MAP_TC_TO_COS 0x8aUL 2805 __le16 reserved48[3]; 2806 }; 2807 2808 /* Query version response (16 bytes) */ 2809 struct creq_query_version_resp { 2810 u8 type; 2811 #define CREQ_QUERY_VERSION_RESP_TYPE_MASK 0x3fUL 2812 #define CREQ_QUERY_VERSION_RESP_TYPE_SFT 0 2813 #define CREQ_QUERY_VERSION_RESP_TYPE_QP_EVENT 0x38UL 2814 #define CREQ_QUERY_VERSION_RESP_RESERVED2_MASK 0xc0UL 2815 #define CREQ_QUERY_VERSION_RESP_RESERVED2_SFT 6 2816 u8 status; 2817 __le16 cookie; 2818 u8 fw_maj; 2819 u8 fw_minor; 2820 u8 fw_bld; 2821 u8 fw_rsvd; 2822 u8 v; 2823 #define CREQ_QUERY_VERSION_RESP_V 0x1UL 2824 #define CREQ_QUERY_VERSION_RESP_RESERVED7_MASK 0xfeUL 2825 #define CREQ_QUERY_VERSION_RESP_RESERVED7_SFT 1 2826 u8 event; 2827 #define CREQ_QUERY_VERSION_RESP_EVENT_QUERY_VERSION 0x8bUL 2828 __le16 reserved16; 2829 u8 intf_maj; 2830 u8 intf_minor; 2831 u8 intf_bld; 2832 u8 intf_rsvd; 2833 }; 2834 2835 /* Modify congestion control command response (16 bytes) */ 2836 struct creq_modify_cc_resp { 2837 u8 type; 2838 #define CREQ_MODIFY_CC_RESP_TYPE_MASK 0x3fUL 2839 #define CREQ_MODIFY_CC_RESP_TYPE_SFT 0 2840 #define CREQ_MODIFY_CC_RESP_TYPE_QP_EVENT 0x38UL 2841 #define CREQ_MODIFY_CC_RESP_RESERVED2_MASK 0xc0UL 2842 #define CREQ_MODIFY_CC_RESP_RESERVED2_SFT 6 2843 u8 status; 2844 __le16 cookie; 2845 __le32 reserved32; 2846 u8 v; 2847 #define CREQ_MODIFY_CC_RESP_V 0x1UL 2848 #define CREQ_MODIFY_CC_RESP_RESERVED7_MASK 0xfeUL 2849 #define CREQ_MODIFY_CC_RESP_RESERVED7_SFT 1 2850 u8 event; 2851 #define CREQ_MODIFY_CC_RESP_EVENT_MODIFY_CC 0x8cUL 2852 __le16 reserved48[3]; 2853 }; 2854 2855 /* Query congestion control command response (16 bytes) */ 2856 struct creq_query_cc_resp { 2857 u8 type; 2858 #define CREQ_QUERY_CC_RESP_TYPE_MASK 0x3fUL 2859 #define CREQ_QUERY_CC_RESP_TYPE_SFT 0 2860 #define CREQ_QUERY_CC_RESP_TYPE_QP_EVENT 0x38UL 2861 #define CREQ_QUERY_CC_RESP_RESERVED2_MASK 0xc0UL 2862 #define CREQ_QUERY_CC_RESP_RESERVED2_SFT 6 2863 u8 status; 2864 __le16 cookie; 2865 __le32 size; 2866 u8 v; 2867 #define CREQ_QUERY_CC_RESP_V 0x1UL 2868 #define CREQ_QUERY_CC_RESP_RESERVED7_MASK 0xfeUL 2869 #define CREQ_QUERY_CC_RESP_RESERVED7_SFT 1 2870 u8 event; 2871 #define CREQ_QUERY_CC_RESP_EVENT_QUERY_CC 0x8dUL 2872 __le16 reserved48[3]; 2873 }; 2874 2875 /* Query congestion control command response side buffer structure (32 bytes) */ 2876 struct creq_query_cc_resp_sb { 2877 u8 opcode; 2878 #define CREQ_QUERY_CC_RESP_SB_OPCODE_QUERY_CC 0x8dUL 2879 u8 status; 2880 __le16 cookie; 2881 __le16 flags; 2882 u8 resp_size; 2883 u8 reserved8; 2884 u8 enable_cc; 2885 #define CREQ_QUERY_CC_RESP_SB_ENABLE_CC 0x1UL 2886 u8 g; 2887 #define CREQ_QUERY_CC_RESP_SB_G_MASK 0x7UL 2888 #define CREQ_QUERY_CC_RESP_SB_G_SFT 0 2889 u8 num_phases_per_state; 2890 __le16 init_cr; 2891 u8 unused_2; 2892 __le16 unused_3; 2893 u8 unused_4; 2894 __le16 init_tr; 2895 u8 tos_dscp_tos_ecn; 2896 #define CREQ_QUERY_CC_RESP_SB_TOS_ECN_MASK 0x3UL 2897 #define CREQ_QUERY_CC_RESP_SB_TOS_ECN_SFT 0 2898 #define CREQ_QUERY_CC_RESP_SB_TOS_DSCP_MASK 0xfcUL 2899 #define CREQ_QUERY_CC_RESP_SB_TOS_DSCP_SFT 2 2900 __le64 reserved64; 2901 __le64 reserved64_1; 2902 }; 2903 2904 /* creq_query_roce_stats_resp (size:128b/16B) */ 2905 struct creq_query_roce_stats_resp { 2906 u8 type; 2907 #define CREQ_QUERY_ROCE_STATS_RESP_TYPE_MASK 0x3fUL 2908 #define CREQ_QUERY_ROCE_STATS_RESP_TYPE_SFT 0 2909 #define CREQ_QUERY_ROCE_STATS_RESP_TYPE_QP_EVENT 0x38UL 2910 #define CREQ_QUERY_ROCE_STATS_RESP_TYPE_LAST \ 2911 CREQ_QUERY_ROCE_STATS_RESP_TYPE_QP_EVENT 2912 u8 status; 2913 __le16 cookie; 2914 __le32 size; 2915 u8 v; 2916 #define CREQ_QUERY_ROCE_STATS_RESP_V 0x1UL 2917 u8 event; 2918 #define CREQ_QUERY_ROCE_STATS_RESP_EVENT_QUERY_ROCE_STATS 0x8eUL 2919 #define CREQ_QUERY_ROCE_STATS_RESP_EVENT_LAST \ 2920 CREQ_QUERY_ROCE_STATS_RESP_EVENT_QUERY_ROCE_STATS 2921 u8 reserved48[6]; 2922 }; 2923 2924 /* creq_query_roce_stats_resp_sb (size:2624b/328B) */ 2925 struct creq_query_roce_stats_resp_sb { 2926 u8 opcode; 2927 #define CREQ_QUERY_ROCE_STATS_RESP_SB_OPCODE_QUERY_ROCE_STATS 0x8eUL 2928 #define CREQ_QUERY_ROCE_STATS_RESP_SB_OPCODE_LAST \ 2929 CREQ_QUERY_ROCE_STATS_RESP_SB_OPCODE_QUERY_ROCE_STATS 2930 u8 status; 2931 __le16 cookie; 2932 __le16 flags; 2933 u8 resp_size; 2934 u8 rsvd; 2935 __le32 num_counters; 2936 __le32 rsvd1; 2937 __le64 to_retransmits; 2938 __le64 seq_err_naks_rcvd; 2939 __le64 max_retry_exceeded; 2940 __le64 rnr_naks_rcvd; 2941 __le64 missing_resp; 2942 __le64 unrecoverable_err; 2943 __le64 bad_resp_err; 2944 __le64 local_qp_op_err; 2945 __le64 local_protection_err; 2946 __le64 mem_mgmt_op_err; 2947 __le64 remote_invalid_req_err; 2948 __le64 remote_access_err; 2949 __le64 remote_op_err; 2950 __le64 dup_req; 2951 __le64 res_exceed_max; 2952 __le64 res_length_mismatch; 2953 __le64 res_exceeds_wqe; 2954 __le64 res_opcode_err; 2955 __le64 res_rx_invalid_rkey; 2956 __le64 res_rx_domain_err; 2957 __le64 res_rx_no_perm; 2958 __le64 res_rx_range_err; 2959 __le64 res_tx_invalid_rkey; 2960 __le64 res_tx_domain_err; 2961 __le64 res_tx_no_perm; 2962 __le64 res_tx_range_err; 2963 __le64 res_irrq_oflow; 2964 __le64 res_unsup_opcode; 2965 __le64 res_unaligned_atomic; 2966 __le64 res_rem_inv_err; 2967 __le64 res_mem_error; 2968 __le64 res_srq_err; 2969 __le64 res_cmp_err; 2970 __le64 res_invalid_dup_rkey; 2971 __le64 res_wqe_format_err; 2972 __le64 res_cq_load_err; 2973 __le64 res_srq_load_err; 2974 __le64 res_tx_pci_err; 2975 __le64 res_rx_pci_err; 2976 __le64 res_oos_drop_count; 2977 __le64 active_qp_count_p0; 2978 __le64 active_qp_count_p1; 2979 __le64 active_qp_count_p2; 2980 __le64 active_qp_count_p3; 2981 }; 2982 2983 /* QP error notification event (16 bytes) */ 2984 struct creq_qp_error_notification { 2985 u8 type; 2986 #define CREQ_QP_ERROR_NOTIFICATION_TYPE_MASK 0x3fUL 2987 #define CREQ_QP_ERROR_NOTIFICATION_TYPE_SFT 0 2988 #define CREQ_QP_ERROR_NOTIFICATION_TYPE_QP_EVENT 0x38UL 2989 #define CREQ_QP_ERROR_NOTIFICATION_RESERVED2_MASK 0xc0UL 2990 #define CREQ_QP_ERROR_NOTIFICATION_RESERVED2_SFT 6 2991 u8 status; 2992 u8 req_slow_path_state; 2993 u8 req_err_state_reason; 2994 __le32 xid; 2995 u8 v; 2996 #define CREQ_QP_ERROR_NOTIFICATION_V 0x1UL 2997 #define CREQ_QP_ERROR_NOTIFICATION_RESERVED7_MASK 0xfeUL 2998 #define CREQ_QP_ERROR_NOTIFICATION_RESERVED7_SFT 1 2999 u8 event; 3000 #define CREQ_QP_ERROR_NOTIFICATION_EVENT_QP_ERROR_NOTIFICATION 0xc0UL 3001 u8 res_slow_path_state; 3002 u8 res_err_state_reason; 3003 __le16 sq_cons_idx; 3004 __le16 rq_cons_idx; 3005 }; 3006 3007 /* RoCE Slowpath HSI Specification 1.6.0 */ 3008 #define ROCE_SP_HSI_VERSION_MAJOR 1 3009 #define ROCE_SP_HSI_VERSION_MINOR 6 3010 #define ROCE_SP_HSI_VERSION_UPDATE 0 3011 3012 #define ROCE_SP_HSI_VERSION_STR "1.6.0" 3013 /* 3014 * Following is the signature for ROCE_SP_HSI message field that indicates not 3015 * applicable (All F's). Need to cast it the size of the field if needed. 3016 */ 3017 #define ROCE_SP_HSI_NA_SIGNATURE ((__le32)(-1)) 3018 #endif /* __BNXT_RE_HSI_H__ */ 3019