11ac5a404SSelvin Xavier /* 21ac5a404SSelvin Xavier * Broadcom NetXtreme-E RoCE driver. 31ac5a404SSelvin Xavier * 41ac5a404SSelvin Xavier * Copyright (c) 2016 - 2017, Broadcom. All rights reserved. The term 51ac5a404SSelvin Xavier * Broadcom refers to Broadcom Limited and/or its subsidiaries. 61ac5a404SSelvin Xavier * 71ac5a404SSelvin Xavier * This software is available to you under a choice of one of two 81ac5a404SSelvin Xavier * licenses. You may choose to be licensed under the terms of the GNU 91ac5a404SSelvin Xavier * General Public License (GPL) Version 2, available from the file 101ac5a404SSelvin Xavier * COPYING in the main directory of this source tree, or the 111ac5a404SSelvin Xavier * BSD license below: 121ac5a404SSelvin Xavier * 131ac5a404SSelvin Xavier * Redistribution and use in source and binary forms, with or without 141ac5a404SSelvin Xavier * modification, are permitted provided that the following conditions 151ac5a404SSelvin Xavier * are met: 161ac5a404SSelvin Xavier * 171ac5a404SSelvin Xavier * 1. Redistributions of source code must retain the above copyright 181ac5a404SSelvin Xavier * notice, this list of conditions and the following disclaimer. 191ac5a404SSelvin Xavier * 2. Redistributions in binary form must reproduce the above copyright 201ac5a404SSelvin Xavier * notice, this list of conditions and the following disclaimer in 211ac5a404SSelvin Xavier * the documentation and/or other materials provided with the 221ac5a404SSelvin Xavier * distribution. 231ac5a404SSelvin Xavier * 241ac5a404SSelvin Xavier * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' 251ac5a404SSelvin Xavier * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, 261ac5a404SSelvin Xavier * THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR 271ac5a404SSelvin Xavier * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS 281ac5a404SSelvin Xavier * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 291ac5a404SSelvin Xavier * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 301ac5a404SSelvin Xavier * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR 311ac5a404SSelvin Xavier * BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, 321ac5a404SSelvin Xavier * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE 331ac5a404SSelvin Xavier * OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN 341ac5a404SSelvin Xavier * IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 351ac5a404SSelvin Xavier * 361ac5a404SSelvin Xavier * Description: RoCE HSI File - Autogenerated 371ac5a404SSelvin Xavier */ 381ac5a404SSelvin Xavier 391ac5a404SSelvin Xavier #ifndef __BNXT_RE_HSI_H__ 401ac5a404SSelvin Xavier #define __BNXT_RE_HSI_H__ 411ac5a404SSelvin Xavier 421ac5a404SSelvin Xavier /* include bnxt_hsi.h from bnxt_en driver */ 431ac5a404SSelvin Xavier #include "bnxt_hsi.h" 441ac5a404SSelvin Xavier 45a9a457f3SSelvin Xavier /* tx_doorbell (size:32b/4B) */ 46a9a457f3SSelvin Xavier struct tx_doorbell { 47a9a457f3SSelvin Xavier __le32 key_idx; 48a9a457f3SSelvin Xavier #define TX_DOORBELL_IDX_MASK 0xffffffUL 49a9a457f3SSelvin Xavier #define TX_DOORBELL_IDX_SFT 0 50a9a457f3SSelvin Xavier #define TX_DOORBELL_KEY_MASK 0xf0000000UL 51a9a457f3SSelvin Xavier #define TX_DOORBELL_KEY_SFT 28 52a9a457f3SSelvin Xavier #define TX_DOORBELL_KEY_TX (0x0UL << 28) 53a9a457f3SSelvin Xavier #define TX_DOORBELL_KEY_LAST TX_DOORBELL_KEY_TX 54a9a457f3SSelvin Xavier }; 55a9a457f3SSelvin Xavier 56a9a457f3SSelvin Xavier /* rx_doorbell (size:32b/4B) */ 57a9a457f3SSelvin Xavier struct rx_doorbell { 58a9a457f3SSelvin Xavier __le32 key_idx; 59a9a457f3SSelvin Xavier #define RX_DOORBELL_IDX_MASK 0xffffffUL 60a9a457f3SSelvin Xavier #define RX_DOORBELL_IDX_SFT 0 61a9a457f3SSelvin Xavier #define RX_DOORBELL_KEY_MASK 0xf0000000UL 62a9a457f3SSelvin Xavier #define RX_DOORBELL_KEY_SFT 28 63a9a457f3SSelvin Xavier #define RX_DOORBELL_KEY_RX (0x1UL << 28) 64a9a457f3SSelvin Xavier #define RX_DOORBELL_KEY_LAST RX_DOORBELL_KEY_RX 65a9a457f3SSelvin Xavier }; 66a9a457f3SSelvin Xavier 67a9a457f3SSelvin Xavier /* cmpl_doorbell (size:32b/4B) */ 681ac5a404SSelvin Xavier struct cmpl_doorbell { 691ac5a404SSelvin Xavier __le32 key_mask_valid_idx; 701ac5a404SSelvin Xavier #define CMPL_DOORBELL_IDX_MASK 0xffffffUL 711ac5a404SSelvin Xavier #define CMPL_DOORBELL_IDX_SFT 0 721ac5a404SSelvin Xavier #define CMPL_DOORBELL_IDX_VALID 0x4000000UL 731ac5a404SSelvin Xavier #define CMPL_DOORBELL_MASK 0x8000000UL 741ac5a404SSelvin Xavier #define CMPL_DOORBELL_KEY_MASK 0xf0000000UL 751ac5a404SSelvin Xavier #define CMPL_DOORBELL_KEY_SFT 28 761ac5a404SSelvin Xavier #define CMPL_DOORBELL_KEY_CMPL (0x2UL << 28) 77a9a457f3SSelvin Xavier #define CMPL_DOORBELL_KEY_LAST CMPL_DOORBELL_KEY_CMPL 781ac5a404SSelvin Xavier }; 791ac5a404SSelvin Xavier 80a9a457f3SSelvin Xavier /* status_doorbell (size:32b/4B) */ 811ac5a404SSelvin Xavier struct status_doorbell { 821ac5a404SSelvin Xavier __le32 key_idx; 831ac5a404SSelvin Xavier #define STATUS_DOORBELL_IDX_MASK 0xffffffUL 841ac5a404SSelvin Xavier #define STATUS_DOORBELL_IDX_SFT 0 851ac5a404SSelvin Xavier #define STATUS_DOORBELL_KEY_MASK 0xf0000000UL 861ac5a404SSelvin Xavier #define STATUS_DOORBELL_KEY_SFT 28 871ac5a404SSelvin Xavier #define STATUS_DOORBELL_KEY_STAT (0x3UL << 28) 88a9a457f3SSelvin Xavier #define STATUS_DOORBELL_KEY_LAST STATUS_DOORBELL_KEY_STAT 891ac5a404SSelvin Xavier }; 901ac5a404SSelvin Xavier 91a9a457f3SSelvin Xavier /* cmdq_init (size:128b/16B) */ 921ac5a404SSelvin Xavier struct cmdq_init { 931ac5a404SSelvin Xavier __le64 cmdq_pbl; 941ac5a404SSelvin Xavier __le16 cmdq_size_cmdq_lvl; 951ac5a404SSelvin Xavier #define CMDQ_INIT_CMDQ_LVL_MASK 0x3UL 961ac5a404SSelvin Xavier #define CMDQ_INIT_CMDQ_LVL_SFT 0 971ac5a404SSelvin Xavier #define CMDQ_INIT_CMDQ_SIZE_MASK 0xfffcUL 981ac5a404SSelvin Xavier #define CMDQ_INIT_CMDQ_SIZE_SFT 2 991ac5a404SSelvin Xavier __le16 creq_ring_id; 1001ac5a404SSelvin Xavier __le32 prod_idx; 1011ac5a404SSelvin Xavier }; 1021ac5a404SSelvin Xavier 103a9a457f3SSelvin Xavier /* cmdq_base (size:128b/16B) */ 1041ac5a404SSelvin Xavier struct cmdq_base { 1051ac5a404SSelvin Xavier u8 opcode; 1061ac5a404SSelvin Xavier #define CMDQ_BASE_OPCODE_CREATE_QP 0x1UL 1071ac5a404SSelvin Xavier #define CMDQ_BASE_OPCODE_DESTROY_QP 0x2UL 1081ac5a404SSelvin Xavier #define CMDQ_BASE_OPCODE_MODIFY_QP 0x3UL 1091ac5a404SSelvin Xavier #define CMDQ_BASE_OPCODE_QUERY_QP 0x4UL 1101ac5a404SSelvin Xavier #define CMDQ_BASE_OPCODE_CREATE_SRQ 0x5UL 1111ac5a404SSelvin Xavier #define CMDQ_BASE_OPCODE_DESTROY_SRQ 0x6UL 1121ac5a404SSelvin Xavier #define CMDQ_BASE_OPCODE_QUERY_SRQ 0x8UL 1131ac5a404SSelvin Xavier #define CMDQ_BASE_OPCODE_CREATE_CQ 0x9UL 1141ac5a404SSelvin Xavier #define CMDQ_BASE_OPCODE_DESTROY_CQ 0xaUL 1151ac5a404SSelvin Xavier #define CMDQ_BASE_OPCODE_RESIZE_CQ 0xcUL 1161ac5a404SSelvin Xavier #define CMDQ_BASE_OPCODE_ALLOCATE_MRW 0xdUL 1171ac5a404SSelvin Xavier #define CMDQ_BASE_OPCODE_DEALLOCATE_KEY 0xeUL 1181ac5a404SSelvin Xavier #define CMDQ_BASE_OPCODE_REGISTER_MR 0xfUL 1191ac5a404SSelvin Xavier #define CMDQ_BASE_OPCODE_DEREGISTER_MR 0x10UL 1201ac5a404SSelvin Xavier #define CMDQ_BASE_OPCODE_ADD_GID 0x11UL 1211ac5a404SSelvin Xavier #define CMDQ_BASE_OPCODE_DELETE_GID 0x12UL 1221ac5a404SSelvin Xavier #define CMDQ_BASE_OPCODE_MODIFY_GID 0x17UL 1231ac5a404SSelvin Xavier #define CMDQ_BASE_OPCODE_QUERY_GID 0x18UL 1241ac5a404SSelvin Xavier #define CMDQ_BASE_OPCODE_CREATE_QP1 0x13UL 1251ac5a404SSelvin Xavier #define CMDQ_BASE_OPCODE_DESTROY_QP1 0x14UL 1261ac5a404SSelvin Xavier #define CMDQ_BASE_OPCODE_CREATE_AH 0x15UL 1271ac5a404SSelvin Xavier #define CMDQ_BASE_OPCODE_DESTROY_AH 0x16UL 1281ac5a404SSelvin Xavier #define CMDQ_BASE_OPCODE_INITIALIZE_FW 0x80UL 1291ac5a404SSelvin Xavier #define CMDQ_BASE_OPCODE_DEINITIALIZE_FW 0x81UL 1301ac5a404SSelvin Xavier #define CMDQ_BASE_OPCODE_STOP_FUNC 0x82UL 1311ac5a404SSelvin Xavier #define CMDQ_BASE_OPCODE_QUERY_FUNC 0x83UL 1321ac5a404SSelvin Xavier #define CMDQ_BASE_OPCODE_SET_FUNC_RESOURCES 0x84UL 1331ac5a404SSelvin Xavier #define CMDQ_BASE_OPCODE_READ_CONTEXT 0x85UL 1341ac5a404SSelvin Xavier #define CMDQ_BASE_OPCODE_VF_BACKCHANNEL_REQUEST 0x86UL 1351ac5a404SSelvin Xavier #define CMDQ_BASE_OPCODE_READ_VF_MEMORY 0x87UL 1361ac5a404SSelvin Xavier #define CMDQ_BASE_OPCODE_COMPLETE_VF_REQUEST 0x88UL 1371ac5a404SSelvin Xavier #define CMDQ_BASE_OPCODE_EXTEND_CONTEXT_ARRRAY 0x89UL 1381ac5a404SSelvin Xavier #define CMDQ_BASE_OPCODE_MAP_TC_TO_COS 0x8aUL 1391ac5a404SSelvin Xavier #define CMDQ_BASE_OPCODE_QUERY_VERSION 0x8bUL 140a9a457f3SSelvin Xavier #define CMDQ_BASE_OPCODE_MODIFY_ROCE_CC 0x8cUL 141a9a457f3SSelvin Xavier #define CMDQ_BASE_OPCODE_QUERY_ROCE_CC 0x8dUL 14289f81008SSelvin Xavier #define CMDQ_BASE_OPCODE_QUERY_ROCE_STATS 0x8eUL 143a9a457f3SSelvin Xavier #define CMDQ_BASE_OPCODE_SET_LINK_AGGR_MODE 0x8fUL 144a9a457f3SSelvin Xavier #define CMDQ_BASE_OPCODE_MODIFY_CQ 0x90UL 145a9a457f3SSelvin Xavier #define CMDQ_BASE_OPCODE_QUERY_QP_EXTEND 0x91UL 1469a381f7eSSelvin Xavier #define CMDQ_BASE_OPCODE_QUERY_ROCE_STATS_EXT 0x92UL 147a9a457f3SSelvin Xavier #define CMDQ_BASE_OPCODE_LAST CMDQ_BASE_OPCODE_QUERY_ROCE_STATS_EXT 1481ac5a404SSelvin Xavier u8 cmd_size; 1491ac5a404SSelvin Xavier __le16 flags; 1501ac5a404SSelvin Xavier __le16 cookie; 1511ac5a404SSelvin Xavier u8 resp_size; 1521ac5a404SSelvin Xavier u8 reserved8; 1531ac5a404SSelvin Xavier __le64 resp_addr; 1541ac5a404SSelvin Xavier }; 1551ac5a404SSelvin Xavier 156a9a457f3SSelvin Xavier /* creq_base (size:128b/16B) */ 157a9a457f3SSelvin Xavier struct creq_base { 158a9a457f3SSelvin Xavier u8 type; 159a9a457f3SSelvin Xavier #define CREQ_BASE_TYPE_MASK 0x3fUL 160a9a457f3SSelvin Xavier #define CREQ_BASE_TYPE_SFT 0 161a9a457f3SSelvin Xavier #define CREQ_BASE_TYPE_QP_EVENT 0x38UL 162a9a457f3SSelvin Xavier #define CREQ_BASE_TYPE_FUNC_EVENT 0x3aUL 163a9a457f3SSelvin Xavier #define CREQ_BASE_TYPE_LAST CREQ_BASE_TYPE_FUNC_EVENT 164a9a457f3SSelvin Xavier u8 reserved56[7]; 165a9a457f3SSelvin Xavier u8 v; 166a9a457f3SSelvin Xavier #define CREQ_BASE_V 0x1UL 167a9a457f3SSelvin Xavier u8 event; 168a9a457f3SSelvin Xavier u8 reserved48[6]; 169a9a457f3SSelvin Xavier }; 170a9a457f3SSelvin Xavier 171a9a457f3SSelvin Xavier /* cmdq_query_version (size:128b/16B) */ 172a9a457f3SSelvin Xavier struct cmdq_query_version { 173a9a457f3SSelvin Xavier u8 opcode; 174a9a457f3SSelvin Xavier #define CMDQ_QUERY_VERSION_OPCODE_QUERY_VERSION 0x8bUL 175a9a457f3SSelvin Xavier #define CMDQ_QUERY_VERSION_OPCODE_LAST CMDQ_QUERY_VERSION_OPCODE_QUERY_VERSION 176a9a457f3SSelvin Xavier u8 cmd_size; 177a9a457f3SSelvin Xavier __le16 flags; 178a9a457f3SSelvin Xavier __le16 cookie; 179a9a457f3SSelvin Xavier u8 resp_size; 180a9a457f3SSelvin Xavier u8 reserved8; 181a9a457f3SSelvin Xavier __le64 resp_addr; 182a9a457f3SSelvin Xavier }; 183a9a457f3SSelvin Xavier 184a9a457f3SSelvin Xavier /* creq_query_version_resp (size:128b/16B) */ 185a9a457f3SSelvin Xavier struct creq_query_version_resp { 186a9a457f3SSelvin Xavier u8 type; 187a9a457f3SSelvin Xavier #define CREQ_QUERY_VERSION_RESP_TYPE_MASK 0x3fUL 188a9a457f3SSelvin Xavier #define CREQ_QUERY_VERSION_RESP_TYPE_SFT 0 189a9a457f3SSelvin Xavier #define CREQ_QUERY_VERSION_RESP_TYPE_QP_EVENT 0x38UL 190a9a457f3SSelvin Xavier #define CREQ_QUERY_VERSION_RESP_TYPE_LAST CREQ_QUERY_VERSION_RESP_TYPE_QP_EVENT 191a9a457f3SSelvin Xavier u8 status; 192a9a457f3SSelvin Xavier __le16 cookie; 193a9a457f3SSelvin Xavier u8 fw_maj; 194a9a457f3SSelvin Xavier u8 fw_minor; 195a9a457f3SSelvin Xavier u8 fw_bld; 196a9a457f3SSelvin Xavier u8 fw_rsvd; 197a9a457f3SSelvin Xavier u8 v; 198a9a457f3SSelvin Xavier #define CREQ_QUERY_VERSION_RESP_V 0x1UL 199a9a457f3SSelvin Xavier u8 event; 200a9a457f3SSelvin Xavier #define CREQ_QUERY_VERSION_RESP_EVENT_QUERY_VERSION 0x8bUL 201a9a457f3SSelvin Xavier #define CREQ_QUERY_VERSION_RESP_EVENT_LAST \ 202a9a457f3SSelvin Xavier CREQ_QUERY_VERSION_RESP_EVENT_QUERY_VERSION 203a9a457f3SSelvin Xavier __le16 reserved16; 204a9a457f3SSelvin Xavier u8 intf_maj; 205a9a457f3SSelvin Xavier u8 intf_minor; 206a9a457f3SSelvin Xavier u8 intf_bld; 207a9a457f3SSelvin Xavier u8 intf_rsvd; 208a9a457f3SSelvin Xavier }; 209a9a457f3SSelvin Xavier 210a9a457f3SSelvin Xavier /* cmdq_initialize_fw (size:896b/112B) */ 211a9a457f3SSelvin Xavier struct cmdq_initialize_fw { 212a9a457f3SSelvin Xavier u8 opcode; 213a9a457f3SSelvin Xavier #define CMDQ_INITIALIZE_FW_OPCODE_INITIALIZE_FW 0x80UL 214a9a457f3SSelvin Xavier #define CMDQ_INITIALIZE_FW_OPCODE_LAST CMDQ_INITIALIZE_FW_OPCODE_INITIALIZE_FW 215a9a457f3SSelvin Xavier u8 cmd_size; 216a9a457f3SSelvin Xavier __le16 flags; 217a9a457f3SSelvin Xavier #define CMDQ_INITIALIZE_FW_FLAGS_MRAV_RESERVATION_SPLIT 0x1UL 218a9a457f3SSelvin Xavier #define CMDQ_INITIALIZE_FW_FLAGS_HW_REQUESTER_RETX_SUPPORTED 0x2UL 219a9a457f3SSelvin Xavier __le16 cookie; 220a9a457f3SSelvin Xavier u8 resp_size; 221a9a457f3SSelvin Xavier u8 reserved8; 222a9a457f3SSelvin Xavier __le64 resp_addr; 223a9a457f3SSelvin Xavier u8 qpc_pg_size_qpc_lvl; 224a9a457f3SSelvin Xavier #define CMDQ_INITIALIZE_FW_QPC_LVL_MASK 0xfUL 225a9a457f3SSelvin Xavier #define CMDQ_INITIALIZE_FW_QPC_LVL_SFT 0 226a9a457f3SSelvin Xavier #define CMDQ_INITIALIZE_FW_QPC_LVL_LVL_0 0x0UL 227a9a457f3SSelvin Xavier #define CMDQ_INITIALIZE_FW_QPC_LVL_LVL_1 0x1UL 228a9a457f3SSelvin Xavier #define CMDQ_INITIALIZE_FW_QPC_LVL_LVL_2 0x2UL 229a9a457f3SSelvin Xavier #define CMDQ_INITIALIZE_FW_QPC_LVL_LAST CMDQ_INITIALIZE_FW_QPC_LVL_LVL_2 230a9a457f3SSelvin Xavier #define CMDQ_INITIALIZE_FW_QPC_PG_SIZE_MASK 0xf0UL 231a9a457f3SSelvin Xavier #define CMDQ_INITIALIZE_FW_QPC_PG_SIZE_SFT 4 232a9a457f3SSelvin Xavier #define CMDQ_INITIALIZE_FW_QPC_PG_SIZE_PG_4K (0x0UL << 4) 233a9a457f3SSelvin Xavier #define CMDQ_INITIALIZE_FW_QPC_PG_SIZE_PG_8K (0x1UL << 4) 234a9a457f3SSelvin Xavier #define CMDQ_INITIALIZE_FW_QPC_PG_SIZE_PG_64K (0x2UL << 4) 235a9a457f3SSelvin Xavier #define CMDQ_INITIALIZE_FW_QPC_PG_SIZE_PG_2M (0x3UL << 4) 236a9a457f3SSelvin Xavier #define CMDQ_INITIALIZE_FW_QPC_PG_SIZE_PG_8M (0x4UL << 4) 237a9a457f3SSelvin Xavier #define CMDQ_INITIALIZE_FW_QPC_PG_SIZE_PG_1G (0x5UL << 4) 238a9a457f3SSelvin Xavier #define CMDQ_INITIALIZE_FW_QPC_PG_SIZE_LAST CMDQ_INITIALIZE_FW_QPC_PG_SIZE_PG_1G 239a9a457f3SSelvin Xavier u8 mrw_pg_size_mrw_lvl; 240a9a457f3SSelvin Xavier #define CMDQ_INITIALIZE_FW_MRW_LVL_MASK 0xfUL 241a9a457f3SSelvin Xavier #define CMDQ_INITIALIZE_FW_MRW_LVL_SFT 0 242a9a457f3SSelvin Xavier #define CMDQ_INITIALIZE_FW_MRW_LVL_LVL_0 0x0UL 243a9a457f3SSelvin Xavier #define CMDQ_INITIALIZE_FW_MRW_LVL_LVL_1 0x1UL 244a9a457f3SSelvin Xavier #define CMDQ_INITIALIZE_FW_MRW_LVL_LVL_2 0x2UL 245a9a457f3SSelvin Xavier #define CMDQ_INITIALIZE_FW_MRW_LVL_LAST CMDQ_INITIALIZE_FW_MRW_LVL_LVL_2 246a9a457f3SSelvin Xavier #define CMDQ_INITIALIZE_FW_MRW_PG_SIZE_MASK 0xf0UL 247a9a457f3SSelvin Xavier #define CMDQ_INITIALIZE_FW_MRW_PG_SIZE_SFT 4 248a9a457f3SSelvin Xavier #define CMDQ_INITIALIZE_FW_MRW_PG_SIZE_PG_4K (0x0UL << 4) 249a9a457f3SSelvin Xavier #define CMDQ_INITIALIZE_FW_MRW_PG_SIZE_PG_8K (0x1UL << 4) 250a9a457f3SSelvin Xavier #define CMDQ_INITIALIZE_FW_MRW_PG_SIZE_PG_64K (0x2UL << 4) 251a9a457f3SSelvin Xavier #define CMDQ_INITIALIZE_FW_MRW_PG_SIZE_PG_2M (0x3UL << 4) 252a9a457f3SSelvin Xavier #define CMDQ_INITIALIZE_FW_MRW_PG_SIZE_PG_8M (0x4UL << 4) 253a9a457f3SSelvin Xavier #define CMDQ_INITIALIZE_FW_MRW_PG_SIZE_PG_1G (0x5UL << 4) 254a9a457f3SSelvin Xavier #define CMDQ_INITIALIZE_FW_MRW_PG_SIZE_LAST CMDQ_INITIALIZE_FW_MRW_PG_SIZE_PG_1G 255a9a457f3SSelvin Xavier u8 srq_pg_size_srq_lvl; 256a9a457f3SSelvin Xavier #define CMDQ_INITIALIZE_FW_SRQ_LVL_MASK 0xfUL 257a9a457f3SSelvin Xavier #define CMDQ_INITIALIZE_FW_SRQ_LVL_SFT 0 258a9a457f3SSelvin Xavier #define CMDQ_INITIALIZE_FW_SRQ_LVL_LVL_0 0x0UL 259a9a457f3SSelvin Xavier #define CMDQ_INITIALIZE_FW_SRQ_LVL_LVL_1 0x1UL 260a9a457f3SSelvin Xavier #define CMDQ_INITIALIZE_FW_SRQ_LVL_LVL_2 0x2UL 261a9a457f3SSelvin Xavier #define CMDQ_INITIALIZE_FW_SRQ_LVL_LAST CMDQ_INITIALIZE_FW_SRQ_LVL_LVL_2 262a9a457f3SSelvin Xavier #define CMDQ_INITIALIZE_FW_SRQ_PG_SIZE_MASK 0xf0UL 263a9a457f3SSelvin Xavier #define CMDQ_INITIALIZE_FW_SRQ_PG_SIZE_SFT 4 264a9a457f3SSelvin Xavier #define CMDQ_INITIALIZE_FW_SRQ_PG_SIZE_PG_4K (0x0UL << 4) 265a9a457f3SSelvin Xavier #define CMDQ_INITIALIZE_FW_SRQ_PG_SIZE_PG_8K (0x1UL << 4) 266a9a457f3SSelvin Xavier #define CMDQ_INITIALIZE_FW_SRQ_PG_SIZE_PG_64K (0x2UL << 4) 267a9a457f3SSelvin Xavier #define CMDQ_INITIALIZE_FW_SRQ_PG_SIZE_PG_2M (0x3UL << 4) 268a9a457f3SSelvin Xavier #define CMDQ_INITIALIZE_FW_SRQ_PG_SIZE_PG_8M (0x4UL << 4) 269a9a457f3SSelvin Xavier #define CMDQ_INITIALIZE_FW_SRQ_PG_SIZE_PG_1G (0x5UL << 4) 270a9a457f3SSelvin Xavier #define CMDQ_INITIALIZE_FW_SRQ_PG_SIZE_LAST CMDQ_INITIALIZE_FW_SRQ_PG_SIZE_PG_1G 271a9a457f3SSelvin Xavier u8 cq_pg_size_cq_lvl; 272a9a457f3SSelvin Xavier #define CMDQ_INITIALIZE_FW_CQ_LVL_MASK 0xfUL 273a9a457f3SSelvin Xavier #define CMDQ_INITIALIZE_FW_CQ_LVL_SFT 0 274a9a457f3SSelvin Xavier #define CMDQ_INITIALIZE_FW_CQ_LVL_LVL_0 0x0UL 275a9a457f3SSelvin Xavier #define CMDQ_INITIALIZE_FW_CQ_LVL_LVL_1 0x1UL 276a9a457f3SSelvin Xavier #define CMDQ_INITIALIZE_FW_CQ_LVL_LVL_2 0x2UL 277a9a457f3SSelvin Xavier #define CMDQ_INITIALIZE_FW_CQ_LVL_LAST CMDQ_INITIALIZE_FW_CQ_LVL_LVL_2 278a9a457f3SSelvin Xavier #define CMDQ_INITIALIZE_FW_CQ_PG_SIZE_MASK 0xf0UL 279a9a457f3SSelvin Xavier #define CMDQ_INITIALIZE_FW_CQ_PG_SIZE_SFT 4 280a9a457f3SSelvin Xavier #define CMDQ_INITIALIZE_FW_CQ_PG_SIZE_PG_4K (0x0UL << 4) 281a9a457f3SSelvin Xavier #define CMDQ_INITIALIZE_FW_CQ_PG_SIZE_PG_8K (0x1UL << 4) 282a9a457f3SSelvin Xavier #define CMDQ_INITIALIZE_FW_CQ_PG_SIZE_PG_64K (0x2UL << 4) 283a9a457f3SSelvin Xavier #define CMDQ_INITIALIZE_FW_CQ_PG_SIZE_PG_2M (0x3UL << 4) 284a9a457f3SSelvin Xavier #define CMDQ_INITIALIZE_FW_CQ_PG_SIZE_PG_8M (0x4UL << 4) 285a9a457f3SSelvin Xavier #define CMDQ_INITIALIZE_FW_CQ_PG_SIZE_PG_1G (0x5UL << 4) 286a9a457f3SSelvin Xavier #define CMDQ_INITIALIZE_FW_CQ_PG_SIZE_LAST CMDQ_INITIALIZE_FW_CQ_PG_SIZE_PG_1G 287a9a457f3SSelvin Xavier u8 tqm_pg_size_tqm_lvl; 288a9a457f3SSelvin Xavier #define CMDQ_INITIALIZE_FW_TQM_LVL_MASK 0xfUL 289a9a457f3SSelvin Xavier #define CMDQ_INITIALIZE_FW_TQM_LVL_SFT 0 290a9a457f3SSelvin Xavier #define CMDQ_INITIALIZE_FW_TQM_LVL_LVL_0 0x0UL 291a9a457f3SSelvin Xavier #define CMDQ_INITIALIZE_FW_TQM_LVL_LVL_1 0x1UL 292a9a457f3SSelvin Xavier #define CMDQ_INITIALIZE_FW_TQM_LVL_LVL_2 0x2UL 293a9a457f3SSelvin Xavier #define CMDQ_INITIALIZE_FW_TQM_LVL_LAST CMDQ_INITIALIZE_FW_TQM_LVL_LVL_2 294a9a457f3SSelvin Xavier #define CMDQ_INITIALIZE_FW_TQM_PG_SIZE_MASK 0xf0UL 295a9a457f3SSelvin Xavier #define CMDQ_INITIALIZE_FW_TQM_PG_SIZE_SFT 4 296a9a457f3SSelvin Xavier #define CMDQ_INITIALIZE_FW_TQM_PG_SIZE_PG_4K (0x0UL << 4) 297a9a457f3SSelvin Xavier #define CMDQ_INITIALIZE_FW_TQM_PG_SIZE_PG_8K (0x1UL << 4) 298a9a457f3SSelvin Xavier #define CMDQ_INITIALIZE_FW_TQM_PG_SIZE_PG_64K (0x2UL << 4) 299a9a457f3SSelvin Xavier #define CMDQ_INITIALIZE_FW_TQM_PG_SIZE_PG_2M (0x3UL << 4) 300a9a457f3SSelvin Xavier #define CMDQ_INITIALIZE_FW_TQM_PG_SIZE_PG_8M (0x4UL << 4) 301a9a457f3SSelvin Xavier #define CMDQ_INITIALIZE_FW_TQM_PG_SIZE_PG_1G (0x5UL << 4) 302a9a457f3SSelvin Xavier #define CMDQ_INITIALIZE_FW_TQM_PG_SIZE_LAST CMDQ_INITIALIZE_FW_TQM_PG_SIZE_PG_1G 303a9a457f3SSelvin Xavier u8 tim_pg_size_tim_lvl; 304a9a457f3SSelvin Xavier #define CMDQ_INITIALIZE_FW_TIM_LVL_MASK 0xfUL 305a9a457f3SSelvin Xavier #define CMDQ_INITIALIZE_FW_TIM_LVL_SFT 0 306a9a457f3SSelvin Xavier #define CMDQ_INITIALIZE_FW_TIM_LVL_LVL_0 0x0UL 307a9a457f3SSelvin Xavier #define CMDQ_INITIALIZE_FW_TIM_LVL_LVL_1 0x1UL 308a9a457f3SSelvin Xavier #define CMDQ_INITIALIZE_FW_TIM_LVL_LVL_2 0x2UL 309a9a457f3SSelvin Xavier #define CMDQ_INITIALIZE_FW_TIM_LVL_LAST CMDQ_INITIALIZE_FW_TIM_LVL_LVL_2 310a9a457f3SSelvin Xavier #define CMDQ_INITIALIZE_FW_TIM_PG_SIZE_MASK 0xf0UL 311a9a457f3SSelvin Xavier #define CMDQ_INITIALIZE_FW_TIM_PG_SIZE_SFT 4 312a9a457f3SSelvin Xavier #define CMDQ_INITIALIZE_FW_TIM_PG_SIZE_PG_4K (0x0UL << 4) 313a9a457f3SSelvin Xavier #define CMDQ_INITIALIZE_FW_TIM_PG_SIZE_PG_8K (0x1UL << 4) 314a9a457f3SSelvin Xavier #define CMDQ_INITIALIZE_FW_TIM_PG_SIZE_PG_64K (0x2UL << 4) 315a9a457f3SSelvin Xavier #define CMDQ_INITIALIZE_FW_TIM_PG_SIZE_PG_2M (0x3UL << 4) 316a9a457f3SSelvin Xavier #define CMDQ_INITIALIZE_FW_TIM_PG_SIZE_PG_8M (0x4UL << 4) 317a9a457f3SSelvin Xavier #define CMDQ_INITIALIZE_FW_TIM_PG_SIZE_PG_1G (0x5UL << 4) 318a9a457f3SSelvin Xavier #define CMDQ_INITIALIZE_FW_TIM_PG_SIZE_LAST CMDQ_INITIALIZE_FW_TIM_PG_SIZE_PG_1G 319a9a457f3SSelvin Xavier __le16 log2_dbr_pg_size; 320a9a457f3SSelvin Xavier #define CMDQ_INITIALIZE_FW_LOG2_DBR_PG_SIZE_MASK 0xfUL 321a9a457f3SSelvin Xavier #define CMDQ_INITIALIZE_FW_LOG2_DBR_PG_SIZE_SFT 0 322a9a457f3SSelvin Xavier #define CMDQ_INITIALIZE_FW_LOG2_DBR_PG_SIZE_PG_4K 0x0UL 323a9a457f3SSelvin Xavier #define CMDQ_INITIALIZE_FW_LOG2_DBR_PG_SIZE_PG_8K 0x1UL 324a9a457f3SSelvin Xavier #define CMDQ_INITIALIZE_FW_LOG2_DBR_PG_SIZE_PG_16K 0x2UL 325a9a457f3SSelvin Xavier #define CMDQ_INITIALIZE_FW_LOG2_DBR_PG_SIZE_PG_32K 0x3UL 326a9a457f3SSelvin Xavier #define CMDQ_INITIALIZE_FW_LOG2_DBR_PG_SIZE_PG_64K 0x4UL 327a9a457f3SSelvin Xavier #define CMDQ_INITIALIZE_FW_LOG2_DBR_PG_SIZE_PG_128K 0x5UL 328a9a457f3SSelvin Xavier #define CMDQ_INITIALIZE_FW_LOG2_DBR_PG_SIZE_PG_256K 0x6UL 329a9a457f3SSelvin Xavier #define CMDQ_INITIALIZE_FW_LOG2_DBR_PG_SIZE_PG_512K 0x7UL 330a9a457f3SSelvin Xavier #define CMDQ_INITIALIZE_FW_LOG2_DBR_PG_SIZE_PG_1M 0x8UL 331a9a457f3SSelvin Xavier #define CMDQ_INITIALIZE_FW_LOG2_DBR_PG_SIZE_PG_2M 0x9UL 332a9a457f3SSelvin Xavier #define CMDQ_INITIALIZE_FW_LOG2_DBR_PG_SIZE_PG_4M 0xaUL 333a9a457f3SSelvin Xavier #define CMDQ_INITIALIZE_FW_LOG2_DBR_PG_SIZE_PG_8M 0xbUL 334a9a457f3SSelvin Xavier #define CMDQ_INITIALIZE_FW_LOG2_DBR_PG_SIZE_PG_16M 0xcUL 335a9a457f3SSelvin Xavier #define CMDQ_INITIALIZE_FW_LOG2_DBR_PG_SIZE_PG_32M 0xdUL 336a9a457f3SSelvin Xavier #define CMDQ_INITIALIZE_FW_LOG2_DBR_PG_SIZE_PG_64M 0xeUL 337a9a457f3SSelvin Xavier #define CMDQ_INITIALIZE_FW_LOG2_DBR_PG_SIZE_PG_128M 0xfUL 338a9a457f3SSelvin Xavier #define CMDQ_INITIALIZE_FW_LOG2_DBR_PG_SIZE_LAST \ 339a9a457f3SSelvin Xavier CMDQ_INITIALIZE_FW_LOG2_DBR_PG_SIZE_PG_128M 340a9a457f3SSelvin Xavier #define CMDQ_INITIALIZE_FW_RSVD_MASK 0xfff0UL 341a9a457f3SSelvin Xavier #define CMDQ_INITIALIZE_FW_RSVD_SFT 4 342a9a457f3SSelvin Xavier __le64 qpc_page_dir; 343a9a457f3SSelvin Xavier __le64 mrw_page_dir; 344a9a457f3SSelvin Xavier __le64 srq_page_dir; 345a9a457f3SSelvin Xavier __le64 cq_page_dir; 346a9a457f3SSelvin Xavier __le64 tqm_page_dir; 347a9a457f3SSelvin Xavier __le64 tim_page_dir; 348a9a457f3SSelvin Xavier __le32 number_of_qp; 349a9a457f3SSelvin Xavier __le32 number_of_mrw; 350a9a457f3SSelvin Xavier __le32 number_of_srq; 351a9a457f3SSelvin Xavier __le32 number_of_cq; 352a9a457f3SSelvin Xavier __le32 max_qp_per_vf; 353a9a457f3SSelvin Xavier __le32 max_mrw_per_vf; 354a9a457f3SSelvin Xavier __le32 max_srq_per_vf; 355a9a457f3SSelvin Xavier __le32 max_cq_per_vf; 356a9a457f3SSelvin Xavier __le32 max_gid_per_vf; 357a9a457f3SSelvin Xavier __le32 stat_ctx_id; 358a9a457f3SSelvin Xavier }; 359a9a457f3SSelvin Xavier 360a9a457f3SSelvin Xavier /* creq_initialize_fw_resp (size:128b/16B) */ 361a9a457f3SSelvin Xavier struct creq_initialize_fw_resp { 362a9a457f3SSelvin Xavier u8 type; 363a9a457f3SSelvin Xavier #define CREQ_INITIALIZE_FW_RESP_TYPE_MASK 0x3fUL 364a9a457f3SSelvin Xavier #define CREQ_INITIALIZE_FW_RESP_TYPE_SFT 0 365a9a457f3SSelvin Xavier #define CREQ_INITIALIZE_FW_RESP_TYPE_QP_EVENT 0x38UL 366a9a457f3SSelvin Xavier #define CREQ_INITIALIZE_FW_RESP_TYPE_LAST CREQ_INITIALIZE_FW_RESP_TYPE_QP_EVENT 367a9a457f3SSelvin Xavier u8 status; 368a9a457f3SSelvin Xavier __le16 cookie; 369a9a457f3SSelvin Xavier __le32 reserved32; 370a9a457f3SSelvin Xavier u8 v; 371a9a457f3SSelvin Xavier #define CREQ_INITIALIZE_FW_RESP_V 0x1UL 372a9a457f3SSelvin Xavier u8 event; 373a9a457f3SSelvin Xavier #define CREQ_INITIALIZE_FW_RESP_EVENT_INITIALIZE_FW 0x80UL 374a9a457f3SSelvin Xavier #define CREQ_INITIALIZE_FW_RESP_EVENT_LAST \ 375a9a457f3SSelvin Xavier CREQ_INITIALIZE_FW_RESP_EVENT_INITIALIZE_FW 376a9a457f3SSelvin Xavier u8 reserved48[6]; 377a9a457f3SSelvin Xavier }; 378a9a457f3SSelvin Xavier 379a9a457f3SSelvin Xavier /* cmdq_deinitialize_fw (size:128b/16B) */ 380a9a457f3SSelvin Xavier struct cmdq_deinitialize_fw { 381a9a457f3SSelvin Xavier u8 opcode; 382a9a457f3SSelvin Xavier #define CMDQ_DEINITIALIZE_FW_OPCODE_DEINITIALIZE_FW 0x81UL 383a9a457f3SSelvin Xavier #define CMDQ_DEINITIALIZE_FW_OPCODE_LAST \ 384a9a457f3SSelvin Xavier CMDQ_DEINITIALIZE_FW_OPCODE_DEINITIALIZE_FW 385a9a457f3SSelvin Xavier u8 cmd_size; 386a9a457f3SSelvin Xavier __le16 flags; 387a9a457f3SSelvin Xavier __le16 cookie; 388a9a457f3SSelvin Xavier u8 resp_size; 389a9a457f3SSelvin Xavier u8 reserved8; 390a9a457f3SSelvin Xavier __le64 resp_addr; 391a9a457f3SSelvin Xavier }; 392a9a457f3SSelvin Xavier 393a9a457f3SSelvin Xavier /* creq_deinitialize_fw_resp (size:128b/16B) */ 394a9a457f3SSelvin Xavier struct creq_deinitialize_fw_resp { 395a9a457f3SSelvin Xavier u8 type; 396a9a457f3SSelvin Xavier #define CREQ_DEINITIALIZE_FW_RESP_TYPE_MASK 0x3fUL 397a9a457f3SSelvin Xavier #define CREQ_DEINITIALIZE_FW_RESP_TYPE_SFT 0 398a9a457f3SSelvin Xavier #define CREQ_DEINITIALIZE_FW_RESP_TYPE_QP_EVENT 0x38UL 399a9a457f3SSelvin Xavier #define CREQ_DEINITIALIZE_FW_RESP_TYPE_LAST CREQ_DEINITIALIZE_FW_RESP_TYPE_QP_EVENT 400a9a457f3SSelvin Xavier u8 status; 401a9a457f3SSelvin Xavier __le16 cookie; 402a9a457f3SSelvin Xavier __le32 reserved32; 403a9a457f3SSelvin Xavier u8 v; 404a9a457f3SSelvin Xavier #define CREQ_DEINITIALIZE_FW_RESP_V 0x1UL 405a9a457f3SSelvin Xavier u8 event; 406a9a457f3SSelvin Xavier #define CREQ_DEINITIALIZE_FW_RESP_EVENT_DEINITIALIZE_FW 0x81UL 407a9a457f3SSelvin Xavier #define CREQ_DEINITIALIZE_FW_RESP_EVENT_LAST \ 408a9a457f3SSelvin Xavier CREQ_DEINITIALIZE_FW_RESP_EVENT_DEINITIALIZE_FW 409a9a457f3SSelvin Xavier u8 reserved48[6]; 410a9a457f3SSelvin Xavier }; 411a9a457f3SSelvin Xavier 412a9a457f3SSelvin Xavier /* cmdq_create_qp (size:768b/96B) */ 4131ac5a404SSelvin Xavier struct cmdq_create_qp { 4141ac5a404SSelvin Xavier u8 opcode; 4151ac5a404SSelvin Xavier #define CMDQ_CREATE_QP_OPCODE_CREATE_QP 0x1UL 416a9a457f3SSelvin Xavier #define CMDQ_CREATE_QP_OPCODE_LAST CMDQ_CREATE_QP_OPCODE_CREATE_QP 4171ac5a404SSelvin Xavier u8 cmd_size; 4181ac5a404SSelvin Xavier __le16 flags; 4191ac5a404SSelvin Xavier __le16 cookie; 4201ac5a404SSelvin Xavier u8 resp_size; 4211ac5a404SSelvin Xavier u8 reserved8; 4221ac5a404SSelvin Xavier __le64 resp_addr; 4231ac5a404SSelvin Xavier __le64 qp_handle; 4241ac5a404SSelvin Xavier __le32 qp_flags; 4251ac5a404SSelvin Xavier #define CMDQ_CREATE_QP_QP_FLAGS_SRQ_USED 0x1UL 4261ac5a404SSelvin Xavier #define CMDQ_CREATE_QP_QP_FLAGS_FORCE_COMPLETION 0x2UL 4271ac5a404SSelvin Xavier #define CMDQ_CREATE_QP_QP_FLAGS_RESERVED_LKEY_ENABLE 0x4UL 4281ac5a404SSelvin Xavier #define CMDQ_CREATE_QP_QP_FLAGS_FR_PMR_ENABLED 0x8UL 42954ace984SDevesh Sharma #define CMDQ_CREATE_QP_QP_FLAGS_VARIABLE_SIZED_WQE_ENABLED 0x10UL 430a9a457f3SSelvin Xavier #define CMDQ_CREATE_QP_QP_FLAGS_OPTIMIZED_TRANSMIT_ENABLED 0x20UL 431a9a457f3SSelvin Xavier #define CMDQ_CREATE_QP_QP_FLAGS_RESPONDER_UD_CQE_WITH_CFA 0x40UL 4329a381f7eSSelvin Xavier #define CMDQ_CREATE_QP_QP_FLAGS_EXT_STATS_ENABLED 0x80UL 4339a381f7eSSelvin Xavier #define CMDQ_CREATE_QP_QP_FLAGS_LAST \ 4349a381f7eSSelvin Xavier CMDQ_CREATE_QP_QP_FLAGS_EXT_STATS_ENABLED 4351ac5a404SSelvin Xavier u8 type; 4361ac5a404SSelvin Xavier #define CMDQ_CREATE_QP_TYPE_RC 0x2UL 4371ac5a404SSelvin Xavier #define CMDQ_CREATE_QP_TYPE_UD 0x4UL 4381ac5a404SSelvin Xavier #define CMDQ_CREATE_QP_TYPE_RAW_ETHERTYPE 0x6UL 439374c5285SDevesh Sharma #define CMDQ_CREATE_QP_TYPE_GSI 0x7UL 440a9a457f3SSelvin Xavier #define CMDQ_CREATE_QP_TYPE_LAST CMDQ_CREATE_QP_TYPE_GSI 4411ac5a404SSelvin Xavier u8 sq_pg_size_sq_lvl; 4421ac5a404SSelvin Xavier #define CMDQ_CREATE_QP_SQ_LVL_MASK 0xfUL 4431ac5a404SSelvin Xavier #define CMDQ_CREATE_QP_SQ_LVL_SFT 0 4441ac5a404SSelvin Xavier #define CMDQ_CREATE_QP_SQ_LVL_LVL_0 0x0UL 4451ac5a404SSelvin Xavier #define CMDQ_CREATE_QP_SQ_LVL_LVL_1 0x1UL 4461ac5a404SSelvin Xavier #define CMDQ_CREATE_QP_SQ_LVL_LVL_2 0x2UL 447a9a457f3SSelvin Xavier #define CMDQ_CREATE_QP_SQ_LVL_LAST CMDQ_CREATE_QP_SQ_LVL_LVL_2 4481ac5a404SSelvin Xavier #define CMDQ_CREATE_QP_SQ_PG_SIZE_MASK 0xf0UL 4491ac5a404SSelvin Xavier #define CMDQ_CREATE_QP_SQ_PG_SIZE_SFT 4 4501ac5a404SSelvin Xavier #define CMDQ_CREATE_QP_SQ_PG_SIZE_PG_4K (0x0UL << 4) 4511ac5a404SSelvin Xavier #define CMDQ_CREATE_QP_SQ_PG_SIZE_PG_8K (0x1UL << 4) 4521ac5a404SSelvin Xavier #define CMDQ_CREATE_QP_SQ_PG_SIZE_PG_64K (0x2UL << 4) 4531ac5a404SSelvin Xavier #define CMDQ_CREATE_QP_SQ_PG_SIZE_PG_2M (0x3UL << 4) 4541ac5a404SSelvin Xavier #define CMDQ_CREATE_QP_SQ_PG_SIZE_PG_8M (0x4UL << 4) 4551ac5a404SSelvin Xavier #define CMDQ_CREATE_QP_SQ_PG_SIZE_PG_1G (0x5UL << 4) 456a9a457f3SSelvin Xavier #define CMDQ_CREATE_QP_SQ_PG_SIZE_LAST CMDQ_CREATE_QP_SQ_PG_SIZE_PG_1G 4571ac5a404SSelvin Xavier u8 rq_pg_size_rq_lvl; 4581ac5a404SSelvin Xavier #define CMDQ_CREATE_QP_RQ_LVL_MASK 0xfUL 4591ac5a404SSelvin Xavier #define CMDQ_CREATE_QP_RQ_LVL_SFT 0 4601ac5a404SSelvin Xavier #define CMDQ_CREATE_QP_RQ_LVL_LVL_0 0x0UL 4611ac5a404SSelvin Xavier #define CMDQ_CREATE_QP_RQ_LVL_LVL_1 0x1UL 4621ac5a404SSelvin Xavier #define CMDQ_CREATE_QP_RQ_LVL_LVL_2 0x2UL 463a9a457f3SSelvin Xavier #define CMDQ_CREATE_QP_RQ_LVL_LAST CMDQ_CREATE_QP_RQ_LVL_LVL_2 4641ac5a404SSelvin Xavier #define CMDQ_CREATE_QP_RQ_PG_SIZE_MASK 0xf0UL 4651ac5a404SSelvin Xavier #define CMDQ_CREATE_QP_RQ_PG_SIZE_SFT 4 4661ac5a404SSelvin Xavier #define CMDQ_CREATE_QP_RQ_PG_SIZE_PG_4K (0x0UL << 4) 4671ac5a404SSelvin Xavier #define CMDQ_CREATE_QP_RQ_PG_SIZE_PG_8K (0x1UL << 4) 4681ac5a404SSelvin Xavier #define CMDQ_CREATE_QP_RQ_PG_SIZE_PG_64K (0x2UL << 4) 4691ac5a404SSelvin Xavier #define CMDQ_CREATE_QP_RQ_PG_SIZE_PG_2M (0x3UL << 4) 4701ac5a404SSelvin Xavier #define CMDQ_CREATE_QP_RQ_PG_SIZE_PG_8M (0x4UL << 4) 4711ac5a404SSelvin Xavier #define CMDQ_CREATE_QP_RQ_PG_SIZE_PG_1G (0x5UL << 4) 472a9a457f3SSelvin Xavier #define CMDQ_CREATE_QP_RQ_PG_SIZE_LAST CMDQ_CREATE_QP_RQ_PG_SIZE_PG_1G 4731ac5a404SSelvin Xavier u8 unused_0; 4741ac5a404SSelvin Xavier __le32 dpi; 4751ac5a404SSelvin Xavier __le32 sq_size; 4761ac5a404SSelvin Xavier __le32 rq_size; 4771ac5a404SSelvin Xavier __le16 sq_fwo_sq_sge; 4781ac5a404SSelvin Xavier #define CMDQ_CREATE_QP_SQ_SGE_MASK 0xfUL 4791ac5a404SSelvin Xavier #define CMDQ_CREATE_QP_SQ_SGE_SFT 0 4801ac5a404SSelvin Xavier #define CMDQ_CREATE_QP_SQ_FWO_MASK 0xfff0UL 4811ac5a404SSelvin Xavier #define CMDQ_CREATE_QP_SQ_FWO_SFT 4 4821ac5a404SSelvin Xavier __le16 rq_fwo_rq_sge; 4831ac5a404SSelvin Xavier #define CMDQ_CREATE_QP_RQ_SGE_MASK 0xfUL 4841ac5a404SSelvin Xavier #define CMDQ_CREATE_QP_RQ_SGE_SFT 0 4851ac5a404SSelvin Xavier #define CMDQ_CREATE_QP_RQ_FWO_MASK 0xfff0UL 4861ac5a404SSelvin Xavier #define CMDQ_CREATE_QP_RQ_FWO_SFT 4 4871ac5a404SSelvin Xavier __le32 scq_cid; 4881ac5a404SSelvin Xavier __le32 rcq_cid; 4891ac5a404SSelvin Xavier __le32 srq_cid; 4901ac5a404SSelvin Xavier __le32 pd_id; 4911ac5a404SSelvin Xavier __le64 sq_pbl; 4921ac5a404SSelvin Xavier __le64 rq_pbl; 4931ac5a404SSelvin Xavier __le64 irrq_addr; 4941ac5a404SSelvin Xavier __le64 orrq_addr; 4951ac5a404SSelvin Xavier }; 4961ac5a404SSelvin Xavier 497a9a457f3SSelvin Xavier /* creq_create_qp_resp (size:128b/16B) */ 498a9a457f3SSelvin Xavier struct creq_create_qp_resp { 499a9a457f3SSelvin Xavier u8 type; 500a9a457f3SSelvin Xavier #define CREQ_CREATE_QP_RESP_TYPE_MASK 0x3fUL 501a9a457f3SSelvin Xavier #define CREQ_CREATE_QP_RESP_TYPE_SFT 0 502a9a457f3SSelvin Xavier #define CREQ_CREATE_QP_RESP_TYPE_QP_EVENT 0x38UL 503a9a457f3SSelvin Xavier #define CREQ_CREATE_QP_RESP_TYPE_LAST CREQ_CREATE_QP_RESP_TYPE_QP_EVENT 504a9a457f3SSelvin Xavier u8 status; 505a9a457f3SSelvin Xavier __le16 cookie; 506a9a457f3SSelvin Xavier __le32 xid; 507a9a457f3SSelvin Xavier u8 v; 508a9a457f3SSelvin Xavier #define CREQ_CREATE_QP_RESP_V 0x1UL 509a9a457f3SSelvin Xavier u8 event; 510a9a457f3SSelvin Xavier #define CREQ_CREATE_QP_RESP_EVENT_CREATE_QP 0x1UL 511a9a457f3SSelvin Xavier #define CREQ_CREATE_QP_RESP_EVENT_LAST CREQ_CREATE_QP_RESP_EVENT_CREATE_QP 512a9a457f3SSelvin Xavier u8 optimized_transmit_enabled; 513a9a457f3SSelvin Xavier u8 reserved48[5]; 514a9a457f3SSelvin Xavier }; 515a9a457f3SSelvin Xavier 516a9a457f3SSelvin Xavier /* cmdq_destroy_qp (size:192b/24B) */ 5171ac5a404SSelvin Xavier struct cmdq_destroy_qp { 5181ac5a404SSelvin Xavier u8 opcode; 5191ac5a404SSelvin Xavier #define CMDQ_DESTROY_QP_OPCODE_DESTROY_QP 0x2UL 520a9a457f3SSelvin Xavier #define CMDQ_DESTROY_QP_OPCODE_LAST CMDQ_DESTROY_QP_OPCODE_DESTROY_QP 5211ac5a404SSelvin Xavier u8 cmd_size; 5221ac5a404SSelvin Xavier __le16 flags; 5231ac5a404SSelvin Xavier __le16 cookie; 5241ac5a404SSelvin Xavier u8 resp_size; 5251ac5a404SSelvin Xavier u8 reserved8; 5261ac5a404SSelvin Xavier __le64 resp_addr; 5271ac5a404SSelvin Xavier __le32 qp_cid; 5281ac5a404SSelvin Xavier __le32 unused_0; 5291ac5a404SSelvin Xavier }; 5301ac5a404SSelvin Xavier 531a9a457f3SSelvin Xavier /* creq_destroy_qp_resp (size:128b/16B) */ 532a9a457f3SSelvin Xavier struct creq_destroy_qp_resp { 533a9a457f3SSelvin Xavier u8 type; 534a9a457f3SSelvin Xavier #define CREQ_DESTROY_QP_RESP_TYPE_MASK 0x3fUL 535a9a457f3SSelvin Xavier #define CREQ_DESTROY_QP_RESP_TYPE_SFT 0 536a9a457f3SSelvin Xavier #define CREQ_DESTROY_QP_RESP_TYPE_QP_EVENT 0x38UL 537a9a457f3SSelvin Xavier #define CREQ_DESTROY_QP_RESP_TYPE_LAST CREQ_DESTROY_QP_RESP_TYPE_QP_EVENT 538a9a457f3SSelvin Xavier u8 status; 539a9a457f3SSelvin Xavier __le16 cookie; 540a9a457f3SSelvin Xavier __le32 xid; 541a9a457f3SSelvin Xavier u8 v; 542a9a457f3SSelvin Xavier #define CREQ_DESTROY_QP_RESP_V 0x1UL 543a9a457f3SSelvin Xavier u8 event; 544a9a457f3SSelvin Xavier #define CREQ_DESTROY_QP_RESP_EVENT_DESTROY_QP 0x2UL 545a9a457f3SSelvin Xavier #define CREQ_DESTROY_QP_RESP_EVENT_LAST CREQ_DESTROY_QP_RESP_EVENT_DESTROY_QP 546a9a457f3SSelvin Xavier u8 reserved48[6]; 547a9a457f3SSelvin Xavier }; 548a9a457f3SSelvin Xavier 549a9a457f3SSelvin Xavier /* cmdq_modify_qp (size:1024b/128B) */ 5501ac5a404SSelvin Xavier struct cmdq_modify_qp { 5511ac5a404SSelvin Xavier u8 opcode; 5521ac5a404SSelvin Xavier #define CMDQ_MODIFY_QP_OPCODE_MODIFY_QP 0x3UL 553a9a457f3SSelvin Xavier #define CMDQ_MODIFY_QP_OPCODE_LAST CMDQ_MODIFY_QP_OPCODE_MODIFY_QP 5541ac5a404SSelvin Xavier u8 cmd_size; 5551ac5a404SSelvin Xavier __le16 flags; 5561ac5a404SSelvin Xavier __le16 cookie; 5571ac5a404SSelvin Xavier u8 resp_size; 5589a54460bSSelvin Xavier u8 qp_type; 5599a54460bSSelvin Xavier #define CMDQ_MODIFY_QP_QP_TYPE_RC 0x2UL 5609a54460bSSelvin Xavier #define CMDQ_MODIFY_QP_QP_TYPE_UD 0x4UL 5619a54460bSSelvin Xavier #define CMDQ_MODIFY_QP_QP_TYPE_RAW_ETHERTYPE 0x6UL 5629a54460bSSelvin Xavier #define CMDQ_MODIFY_QP_QP_TYPE_GSI 0x7UL 5639a54460bSSelvin Xavier #define CMDQ_MODIFY_QP_QP_TYPE_LAST CMDQ_MODIFY_QP_QP_TYPE_GSI 5641ac5a404SSelvin Xavier __le64 resp_addr; 5651ac5a404SSelvin Xavier __le32 modify_mask; 5661ac5a404SSelvin Xavier #define CMDQ_MODIFY_QP_MODIFY_MASK_STATE 0x1UL 5671ac5a404SSelvin Xavier #define CMDQ_MODIFY_QP_MODIFY_MASK_EN_SQD_ASYNC_NOTIFY 0x2UL 5681ac5a404SSelvin Xavier #define CMDQ_MODIFY_QP_MODIFY_MASK_ACCESS 0x4UL 5691ac5a404SSelvin Xavier #define CMDQ_MODIFY_QP_MODIFY_MASK_PKEY 0x8UL 5701ac5a404SSelvin Xavier #define CMDQ_MODIFY_QP_MODIFY_MASK_QKEY 0x10UL 5711ac5a404SSelvin Xavier #define CMDQ_MODIFY_QP_MODIFY_MASK_DGID 0x20UL 5721ac5a404SSelvin Xavier #define CMDQ_MODIFY_QP_MODIFY_MASK_FLOW_LABEL 0x40UL 5731ac5a404SSelvin Xavier #define CMDQ_MODIFY_QP_MODIFY_MASK_SGID_INDEX 0x80UL 5741ac5a404SSelvin Xavier #define CMDQ_MODIFY_QP_MODIFY_MASK_HOP_LIMIT 0x100UL 5751ac5a404SSelvin Xavier #define CMDQ_MODIFY_QP_MODIFY_MASK_TRAFFIC_CLASS 0x200UL 5761ac5a404SSelvin Xavier #define CMDQ_MODIFY_QP_MODIFY_MASK_DEST_MAC 0x400UL 577a9a457f3SSelvin Xavier #define CMDQ_MODIFY_QP_MODIFY_MASK_PINGPONG_PUSH_MODE 0x800UL 5781ac5a404SSelvin Xavier #define CMDQ_MODIFY_QP_MODIFY_MASK_PATH_MTU 0x1000UL 5791ac5a404SSelvin Xavier #define CMDQ_MODIFY_QP_MODIFY_MASK_TIMEOUT 0x2000UL 5801ac5a404SSelvin Xavier #define CMDQ_MODIFY_QP_MODIFY_MASK_RETRY_CNT 0x4000UL 5811ac5a404SSelvin Xavier #define CMDQ_MODIFY_QP_MODIFY_MASK_RNR_RETRY 0x8000UL 5821ac5a404SSelvin Xavier #define CMDQ_MODIFY_QP_MODIFY_MASK_RQ_PSN 0x10000UL 5831ac5a404SSelvin Xavier #define CMDQ_MODIFY_QP_MODIFY_MASK_MAX_RD_ATOMIC 0x20000UL 5841ac5a404SSelvin Xavier #define CMDQ_MODIFY_QP_MODIFY_MASK_MIN_RNR_TIMER 0x40000UL 5851ac5a404SSelvin Xavier #define CMDQ_MODIFY_QP_MODIFY_MASK_SQ_PSN 0x80000UL 5861ac5a404SSelvin Xavier #define CMDQ_MODIFY_QP_MODIFY_MASK_MAX_DEST_RD_ATOMIC 0x100000UL 5871ac5a404SSelvin Xavier #define CMDQ_MODIFY_QP_MODIFY_MASK_SQ_SIZE 0x200000UL 5881ac5a404SSelvin Xavier #define CMDQ_MODIFY_QP_MODIFY_MASK_RQ_SIZE 0x400000UL 5891ac5a404SSelvin Xavier #define CMDQ_MODIFY_QP_MODIFY_MASK_SQ_SGE 0x800000UL 5901ac5a404SSelvin Xavier #define CMDQ_MODIFY_QP_MODIFY_MASK_RQ_SGE 0x1000000UL 5911ac5a404SSelvin Xavier #define CMDQ_MODIFY_QP_MODIFY_MASK_MAX_INLINE_DATA 0x2000000UL 5921ac5a404SSelvin Xavier #define CMDQ_MODIFY_QP_MODIFY_MASK_DEST_QP_ID 0x4000000UL 5931ac5a404SSelvin Xavier #define CMDQ_MODIFY_QP_MODIFY_MASK_SRC_MAC 0x8000000UL 5941ac5a404SSelvin Xavier #define CMDQ_MODIFY_QP_MODIFY_MASK_VLAN_ID 0x10000000UL 5951ac5a404SSelvin Xavier #define CMDQ_MODIFY_QP_MODIFY_MASK_ENABLE_CC 0x20000000UL 5961ac5a404SSelvin Xavier #define CMDQ_MODIFY_QP_MODIFY_MASK_TOS_ECN 0x40000000UL 5971ac5a404SSelvin Xavier #define CMDQ_MODIFY_QP_MODIFY_MASK_TOS_DSCP 0x80000000UL 5981ac5a404SSelvin Xavier __le32 qp_cid; 5991ac5a404SSelvin Xavier u8 network_type_en_sqd_async_notify_new_state; 6001ac5a404SSelvin Xavier #define CMDQ_MODIFY_QP_NEW_STATE_MASK 0xfUL 6011ac5a404SSelvin Xavier #define CMDQ_MODIFY_QP_NEW_STATE_SFT 0 6021ac5a404SSelvin Xavier #define CMDQ_MODIFY_QP_NEW_STATE_RESET 0x0UL 6031ac5a404SSelvin Xavier #define CMDQ_MODIFY_QP_NEW_STATE_INIT 0x1UL 6041ac5a404SSelvin Xavier #define CMDQ_MODIFY_QP_NEW_STATE_RTR 0x2UL 6051ac5a404SSelvin Xavier #define CMDQ_MODIFY_QP_NEW_STATE_RTS 0x3UL 6061ac5a404SSelvin Xavier #define CMDQ_MODIFY_QP_NEW_STATE_SQD 0x4UL 6071ac5a404SSelvin Xavier #define CMDQ_MODIFY_QP_NEW_STATE_SQE 0x5UL 6081ac5a404SSelvin Xavier #define CMDQ_MODIFY_QP_NEW_STATE_ERR 0x6UL 609a9a457f3SSelvin Xavier #define CMDQ_MODIFY_QP_NEW_STATE_LAST CMDQ_MODIFY_QP_NEW_STATE_ERR 6101ac5a404SSelvin Xavier #define CMDQ_MODIFY_QP_EN_SQD_ASYNC_NOTIFY 0x10UL 611a9a457f3SSelvin Xavier #define CMDQ_MODIFY_QP_UNUSED1 0x20UL 6121ac5a404SSelvin Xavier #define CMDQ_MODIFY_QP_NETWORK_TYPE_MASK 0xc0UL 6131ac5a404SSelvin Xavier #define CMDQ_MODIFY_QP_NETWORK_TYPE_SFT 6 6141ac5a404SSelvin Xavier #define CMDQ_MODIFY_QP_NETWORK_TYPE_ROCEV1 (0x0UL << 6) 6151ac5a404SSelvin Xavier #define CMDQ_MODIFY_QP_NETWORK_TYPE_ROCEV2_IPV4 (0x2UL << 6) 6161ac5a404SSelvin Xavier #define CMDQ_MODIFY_QP_NETWORK_TYPE_ROCEV2_IPV6 (0x3UL << 6) 617a9a457f3SSelvin Xavier #define CMDQ_MODIFY_QP_NETWORK_TYPE_LAST CMDQ_MODIFY_QP_NETWORK_TYPE_ROCEV2_IPV6 6181ac5a404SSelvin Xavier u8 access; 6199a54460bSSelvin Xavier #define CMDQ_MODIFY_QP_ACCESS_REMOTE_ATOMIC_REMOTE_READ_REMOTE_WRITE_LOCAL_WRITE_MASK 0xffUL 6209a54460bSSelvin Xavier #define CMDQ_MODIFY_QP_ACCESS_REMOTE_ATOMIC_REMOTE_READ_REMOTE_WRITE_LOCAL_WRITE_SFT 0 6211ac5a404SSelvin Xavier #define CMDQ_MODIFY_QP_ACCESS_LOCAL_WRITE 0x1UL 6221ac5a404SSelvin Xavier #define CMDQ_MODIFY_QP_ACCESS_REMOTE_WRITE 0x2UL 6231ac5a404SSelvin Xavier #define CMDQ_MODIFY_QP_ACCESS_REMOTE_READ 0x4UL 6241ac5a404SSelvin Xavier #define CMDQ_MODIFY_QP_ACCESS_REMOTE_ATOMIC 0x8UL 6251ac5a404SSelvin Xavier __le16 pkey; 6261ac5a404SSelvin Xavier __le32 qkey; 6271ac5a404SSelvin Xavier __le32 dgid[4]; 6281ac5a404SSelvin Xavier __le32 flow_label; 6291ac5a404SSelvin Xavier __le16 sgid_index; 6301ac5a404SSelvin Xavier u8 hop_limit; 6311ac5a404SSelvin Xavier u8 traffic_class; 6321ac5a404SSelvin Xavier __le16 dest_mac[3]; 6331ac5a404SSelvin Xavier u8 tos_dscp_tos_ecn; 6341ac5a404SSelvin Xavier #define CMDQ_MODIFY_QP_TOS_ECN_MASK 0x3UL 6351ac5a404SSelvin Xavier #define CMDQ_MODIFY_QP_TOS_ECN_SFT 0 6361ac5a404SSelvin Xavier #define CMDQ_MODIFY_QP_TOS_DSCP_MASK 0xfcUL 6371ac5a404SSelvin Xavier #define CMDQ_MODIFY_QP_TOS_DSCP_SFT 2 638a9a457f3SSelvin Xavier u8 path_mtu_pingpong_push_enable; 639a9a457f3SSelvin Xavier #define CMDQ_MODIFY_QP_PINGPONG_PUSH_ENABLE 0x1UL 640a9a457f3SSelvin Xavier #define CMDQ_MODIFY_QP_UNUSED3_MASK 0xeUL 641a9a457f3SSelvin Xavier #define CMDQ_MODIFY_QP_UNUSED3_SFT 1 6421ac5a404SSelvin Xavier #define CMDQ_MODIFY_QP_PATH_MTU_MASK 0xf0UL 6431ac5a404SSelvin Xavier #define CMDQ_MODIFY_QP_PATH_MTU_SFT 4 6441ac5a404SSelvin Xavier #define CMDQ_MODIFY_QP_PATH_MTU_MTU_256 (0x0UL << 4) 6451ac5a404SSelvin Xavier #define CMDQ_MODIFY_QP_PATH_MTU_MTU_512 (0x1UL << 4) 6461ac5a404SSelvin Xavier #define CMDQ_MODIFY_QP_PATH_MTU_MTU_1024 (0x2UL << 4) 6471ac5a404SSelvin Xavier #define CMDQ_MODIFY_QP_PATH_MTU_MTU_2048 (0x3UL << 4) 6481ac5a404SSelvin Xavier #define CMDQ_MODIFY_QP_PATH_MTU_MTU_4096 (0x4UL << 4) 6491ac5a404SSelvin Xavier #define CMDQ_MODIFY_QP_PATH_MTU_MTU_8192 (0x5UL << 4) 650a9a457f3SSelvin Xavier #define CMDQ_MODIFY_QP_PATH_MTU_LAST CMDQ_MODIFY_QP_PATH_MTU_MTU_8192 6511ac5a404SSelvin Xavier u8 timeout; 6521ac5a404SSelvin Xavier u8 retry_cnt; 6531ac5a404SSelvin Xavier u8 rnr_retry; 6541ac5a404SSelvin Xavier u8 min_rnr_timer; 6551ac5a404SSelvin Xavier __le32 rq_psn; 6561ac5a404SSelvin Xavier __le32 sq_psn; 6571ac5a404SSelvin Xavier u8 max_rd_atomic; 6581ac5a404SSelvin Xavier u8 max_dest_rd_atomic; 6591ac5a404SSelvin Xavier __le16 enable_cc; 6601ac5a404SSelvin Xavier #define CMDQ_MODIFY_QP_ENABLE_CC 0x1UL 661a9a457f3SSelvin Xavier #define CMDQ_MODIFY_QP_UNUSED15_MASK 0xfffeUL 662a9a457f3SSelvin Xavier #define CMDQ_MODIFY_QP_UNUSED15_SFT 1 6631ac5a404SSelvin Xavier __le32 sq_size; 6641ac5a404SSelvin Xavier __le32 rq_size; 6651ac5a404SSelvin Xavier __le16 sq_sge; 6661ac5a404SSelvin Xavier __le16 rq_sge; 6671ac5a404SSelvin Xavier __le32 max_inline_data; 6681ac5a404SSelvin Xavier __le32 dest_qp_id; 669a9a457f3SSelvin Xavier __le32 pingpong_push_dpi; 6701ac5a404SSelvin Xavier __le16 src_mac[3]; 6711ac5a404SSelvin Xavier __le16 vlan_pcp_vlan_dei_vlan_id; 6721ac5a404SSelvin Xavier #define CMDQ_MODIFY_QP_VLAN_ID_MASK 0xfffUL 6731ac5a404SSelvin Xavier #define CMDQ_MODIFY_QP_VLAN_ID_SFT 0 6741ac5a404SSelvin Xavier #define CMDQ_MODIFY_QP_VLAN_DEI 0x1000UL 6751ac5a404SSelvin Xavier #define CMDQ_MODIFY_QP_VLAN_PCP_MASK 0xe000UL 6761ac5a404SSelvin Xavier #define CMDQ_MODIFY_QP_VLAN_PCP_SFT 13 677a9a457f3SSelvin Xavier __le64 irrq_addr; 678a9a457f3SSelvin Xavier __le64 orrq_addr; 6799a54460bSSelvin Xavier __le32 ext_modify_mask; 6809a54460bSSelvin Xavier #define CMDQ_MODIFY_QP_EXT_MODIFY_MASK_EXT_STATS_CTX 0x1UL 6819a54460bSSelvin Xavier #define CMDQ_MODIFY_QP_EXT_MODIFY_MASK_SCHQ_ID_VALID 0x2UL 6829a54460bSSelvin Xavier __le32 ext_stats_ctx_id; 6839a54460bSSelvin Xavier __le16 schq_id; 6849a54460bSSelvin Xavier __le16 unused_0; 6859a54460bSSelvin Xavier __le32 reserved32; 6861ac5a404SSelvin Xavier }; 6871ac5a404SSelvin Xavier 688a9a457f3SSelvin Xavier /* creq_modify_qp_resp (size:128b/16B) */ 689a9a457f3SSelvin Xavier struct creq_modify_qp_resp { 690a9a457f3SSelvin Xavier u8 type; 691a9a457f3SSelvin Xavier #define CREQ_MODIFY_QP_RESP_TYPE_MASK 0x3fUL 692a9a457f3SSelvin Xavier #define CREQ_MODIFY_QP_RESP_TYPE_SFT 0 693a9a457f3SSelvin Xavier #define CREQ_MODIFY_QP_RESP_TYPE_QP_EVENT 0x38UL 694a9a457f3SSelvin Xavier #define CREQ_MODIFY_QP_RESP_TYPE_LAST CREQ_MODIFY_QP_RESP_TYPE_QP_EVENT 695a9a457f3SSelvin Xavier u8 status; 696a9a457f3SSelvin Xavier __le16 cookie; 697a9a457f3SSelvin Xavier __le32 xid; 698a9a457f3SSelvin Xavier u8 v; 699a9a457f3SSelvin Xavier #define CREQ_MODIFY_QP_RESP_V 0x1UL 700a9a457f3SSelvin Xavier u8 event; 701a9a457f3SSelvin Xavier #define CREQ_MODIFY_QP_RESP_EVENT_MODIFY_QP 0x3UL 702a9a457f3SSelvin Xavier #define CREQ_MODIFY_QP_RESP_EVENT_LAST CREQ_MODIFY_QP_RESP_EVENT_MODIFY_QP 703a9a457f3SSelvin Xavier u8 pingpong_push_state_index_enabled; 704a9a457f3SSelvin Xavier #define CREQ_MODIFY_QP_RESP_PINGPONG_PUSH_ENABLED 0x1UL 705a9a457f3SSelvin Xavier #define CREQ_MODIFY_QP_RESP_PINGPONG_PUSH_INDEX_MASK 0xeUL 706a9a457f3SSelvin Xavier #define CREQ_MODIFY_QP_RESP_PINGPONG_PUSH_INDEX_SFT 1 707a9a457f3SSelvin Xavier #define CREQ_MODIFY_QP_RESP_PINGPONG_PUSH_STATE 0x10UL 708a9a457f3SSelvin Xavier u8 reserved8; 709a9a457f3SSelvin Xavier __le32 lag_src_mac; 710a9a457f3SSelvin Xavier }; 711a9a457f3SSelvin Xavier 712a9a457f3SSelvin Xavier /* cmdq_query_qp (size:192b/24B) */ 7131ac5a404SSelvin Xavier struct cmdq_query_qp { 7141ac5a404SSelvin Xavier u8 opcode; 7151ac5a404SSelvin Xavier #define CMDQ_QUERY_QP_OPCODE_QUERY_QP 0x4UL 716a9a457f3SSelvin Xavier #define CMDQ_QUERY_QP_OPCODE_LAST CMDQ_QUERY_QP_OPCODE_QUERY_QP 7171ac5a404SSelvin Xavier u8 cmd_size; 7181ac5a404SSelvin Xavier __le16 flags; 7191ac5a404SSelvin Xavier __le16 cookie; 7201ac5a404SSelvin Xavier u8 resp_size; 7211ac5a404SSelvin Xavier u8 reserved8; 7221ac5a404SSelvin Xavier __le64 resp_addr; 7231ac5a404SSelvin Xavier __le32 qp_cid; 7241ac5a404SSelvin Xavier __le32 unused_0; 7251ac5a404SSelvin Xavier }; 7261ac5a404SSelvin Xavier 727a9a457f3SSelvin Xavier /* creq_query_qp_resp (size:128b/16B) */ 7281ac5a404SSelvin Xavier struct creq_query_qp_resp { 7291ac5a404SSelvin Xavier u8 type; 7301ac5a404SSelvin Xavier #define CREQ_QUERY_QP_RESP_TYPE_MASK 0x3fUL 7311ac5a404SSelvin Xavier #define CREQ_QUERY_QP_RESP_TYPE_SFT 0 7321ac5a404SSelvin Xavier #define CREQ_QUERY_QP_RESP_TYPE_QP_EVENT 0x38UL 733a9a457f3SSelvin Xavier #define CREQ_QUERY_QP_RESP_TYPE_LAST CREQ_QUERY_QP_RESP_TYPE_QP_EVENT 7341ac5a404SSelvin Xavier u8 status; 7351ac5a404SSelvin Xavier __le16 cookie; 7361ac5a404SSelvin Xavier __le32 size; 7371ac5a404SSelvin Xavier u8 v; 7381ac5a404SSelvin Xavier #define CREQ_QUERY_QP_RESP_V 0x1UL 7391ac5a404SSelvin Xavier u8 event; 7401ac5a404SSelvin Xavier #define CREQ_QUERY_QP_RESP_EVENT_QUERY_QP 0x4UL 741a9a457f3SSelvin Xavier #define CREQ_QUERY_QP_RESP_EVENT_LAST CREQ_QUERY_QP_RESP_EVENT_QUERY_QP 742a9a457f3SSelvin Xavier u8 reserved48[6]; 7431ac5a404SSelvin Xavier }; 7441ac5a404SSelvin Xavier 745a9a457f3SSelvin Xavier /* creq_query_qp_resp_sb (size:832b/104B) */ 7461ac5a404SSelvin Xavier struct creq_query_qp_resp_sb { 7471ac5a404SSelvin Xavier u8 opcode; 7481ac5a404SSelvin Xavier #define CREQ_QUERY_QP_RESP_SB_OPCODE_QUERY_QP 0x4UL 749a9a457f3SSelvin Xavier #define CREQ_QUERY_QP_RESP_SB_OPCODE_LAST CREQ_QUERY_QP_RESP_SB_OPCODE_QUERY_QP 7501ac5a404SSelvin Xavier u8 status; 7511ac5a404SSelvin Xavier __le16 cookie; 7521ac5a404SSelvin Xavier __le16 flags; 7531ac5a404SSelvin Xavier u8 resp_size; 7541ac5a404SSelvin Xavier u8 reserved8; 7551ac5a404SSelvin Xavier __le32 xid; 7561ac5a404SSelvin Xavier u8 en_sqd_async_notify_state; 7571ac5a404SSelvin Xavier #define CREQ_QUERY_QP_RESP_SB_STATE_MASK 0xfUL 7581ac5a404SSelvin Xavier #define CREQ_QUERY_QP_RESP_SB_STATE_SFT 0 7591ac5a404SSelvin Xavier #define CREQ_QUERY_QP_RESP_SB_STATE_RESET 0x0UL 7601ac5a404SSelvin Xavier #define CREQ_QUERY_QP_RESP_SB_STATE_INIT 0x1UL 7611ac5a404SSelvin Xavier #define CREQ_QUERY_QP_RESP_SB_STATE_RTR 0x2UL 7621ac5a404SSelvin Xavier #define CREQ_QUERY_QP_RESP_SB_STATE_RTS 0x3UL 7631ac5a404SSelvin Xavier #define CREQ_QUERY_QP_RESP_SB_STATE_SQD 0x4UL 7641ac5a404SSelvin Xavier #define CREQ_QUERY_QP_RESP_SB_STATE_SQE 0x5UL 7651ac5a404SSelvin Xavier #define CREQ_QUERY_QP_RESP_SB_STATE_ERR 0x6UL 766a9a457f3SSelvin Xavier #define CREQ_QUERY_QP_RESP_SB_STATE_LAST CREQ_QUERY_QP_RESP_SB_STATE_ERR 7671ac5a404SSelvin Xavier #define CREQ_QUERY_QP_RESP_SB_EN_SQD_ASYNC_NOTIFY 0x10UL 768a9a457f3SSelvin Xavier #define CREQ_QUERY_QP_RESP_SB_UNUSED3_MASK 0xe0UL 769a9a457f3SSelvin Xavier #define CREQ_QUERY_QP_RESP_SB_UNUSED3_SFT 5 7701ac5a404SSelvin Xavier u8 access; 771a9a457f3SSelvin Xavier #define \ 772a9a457f3SSelvin Xavier CREQ_QUERY_QP_RESP_SB_ACCESS_REMOTE_ATOMIC_REMOTE_READ_REMOTE_WRITE_LOCAL_WRITE_MASK\ 773a9a457f3SSelvin Xavier 0xffUL 774a9a457f3SSelvin Xavier #define CREQ_QUERY_QP_RESP_SB_ACCESS_REMOTE_ATOMIC_REMOTE_READ_REMOTE_WRITE_LOCAL_WRITE_SFT\ 775a9a457f3SSelvin Xavier 0 7761ac5a404SSelvin Xavier #define CREQ_QUERY_QP_RESP_SB_ACCESS_LOCAL_WRITE 0x1UL 7771ac5a404SSelvin Xavier #define CREQ_QUERY_QP_RESP_SB_ACCESS_REMOTE_WRITE 0x2UL 7781ac5a404SSelvin Xavier #define CREQ_QUERY_QP_RESP_SB_ACCESS_REMOTE_READ 0x4UL 7791ac5a404SSelvin Xavier #define CREQ_QUERY_QP_RESP_SB_ACCESS_REMOTE_ATOMIC 0x8UL 7801ac5a404SSelvin Xavier __le16 pkey; 7811ac5a404SSelvin Xavier __le32 qkey; 7821ac5a404SSelvin Xavier __le32 reserved32; 7831ac5a404SSelvin Xavier __le32 dgid[4]; 7841ac5a404SSelvin Xavier __le32 flow_label; 7851ac5a404SSelvin Xavier __le16 sgid_index; 7861ac5a404SSelvin Xavier u8 hop_limit; 7871ac5a404SSelvin Xavier u8 traffic_class; 7881ac5a404SSelvin Xavier __le16 dest_mac[3]; 7891ac5a404SSelvin Xavier __le16 path_mtu_dest_vlan_id; 7901ac5a404SSelvin Xavier #define CREQ_QUERY_QP_RESP_SB_DEST_VLAN_ID_MASK 0xfffUL 7911ac5a404SSelvin Xavier #define CREQ_QUERY_QP_RESP_SB_DEST_VLAN_ID_SFT 0 7921ac5a404SSelvin Xavier #define CREQ_QUERY_QP_RESP_SB_PATH_MTU_MASK 0xf000UL 7931ac5a404SSelvin Xavier #define CREQ_QUERY_QP_RESP_SB_PATH_MTU_SFT 12 7941ac5a404SSelvin Xavier #define CREQ_QUERY_QP_RESP_SB_PATH_MTU_MTU_256 (0x0UL << 12) 7951ac5a404SSelvin Xavier #define CREQ_QUERY_QP_RESP_SB_PATH_MTU_MTU_512 (0x1UL << 12) 7961ac5a404SSelvin Xavier #define CREQ_QUERY_QP_RESP_SB_PATH_MTU_MTU_1024 (0x2UL << 12) 7971ac5a404SSelvin Xavier #define CREQ_QUERY_QP_RESP_SB_PATH_MTU_MTU_2048 (0x3UL << 12) 7981ac5a404SSelvin Xavier #define CREQ_QUERY_QP_RESP_SB_PATH_MTU_MTU_4096 (0x4UL << 12) 7991ac5a404SSelvin Xavier #define CREQ_QUERY_QP_RESP_SB_PATH_MTU_MTU_8192 (0x5UL << 12) 800a9a457f3SSelvin Xavier #define CREQ_QUERY_QP_RESP_SB_PATH_MTU_LAST CREQ_QUERY_QP_RESP_SB_PATH_MTU_MTU_8192 8011ac5a404SSelvin Xavier u8 timeout; 8021ac5a404SSelvin Xavier u8 retry_cnt; 8031ac5a404SSelvin Xavier u8 rnr_retry; 8041ac5a404SSelvin Xavier u8 min_rnr_timer; 8051ac5a404SSelvin Xavier __le32 rq_psn; 8061ac5a404SSelvin Xavier __le32 sq_psn; 8071ac5a404SSelvin Xavier u8 max_rd_atomic; 8081ac5a404SSelvin Xavier u8 max_dest_rd_atomic; 8091ac5a404SSelvin Xavier u8 tos_dscp_tos_ecn; 8101ac5a404SSelvin Xavier #define CREQ_QUERY_QP_RESP_SB_TOS_ECN_MASK 0x3UL 8111ac5a404SSelvin Xavier #define CREQ_QUERY_QP_RESP_SB_TOS_ECN_SFT 0 8121ac5a404SSelvin Xavier #define CREQ_QUERY_QP_RESP_SB_TOS_DSCP_MASK 0xfcUL 8131ac5a404SSelvin Xavier #define CREQ_QUERY_QP_RESP_SB_TOS_DSCP_SFT 2 8141ac5a404SSelvin Xavier u8 enable_cc; 8151ac5a404SSelvin Xavier #define CREQ_QUERY_QP_RESP_SB_ENABLE_CC 0x1UL 8161ac5a404SSelvin Xavier __le32 sq_size; 8171ac5a404SSelvin Xavier __le32 rq_size; 8181ac5a404SSelvin Xavier __le16 sq_sge; 8191ac5a404SSelvin Xavier __le16 rq_sge; 8201ac5a404SSelvin Xavier __le32 max_inline_data; 8211ac5a404SSelvin Xavier __le32 dest_qp_id; 822a9a457f3SSelvin Xavier __le16 port_id; 823a9a457f3SSelvin Xavier u8 unused_0; 824a9a457f3SSelvin Xavier u8 stat_collection_id; 8251ac5a404SSelvin Xavier __le16 src_mac[3]; 8261ac5a404SSelvin Xavier __le16 vlan_pcp_vlan_dei_vlan_id; 8271ac5a404SSelvin Xavier #define CREQ_QUERY_QP_RESP_SB_VLAN_ID_MASK 0xfffUL 8281ac5a404SSelvin Xavier #define CREQ_QUERY_QP_RESP_SB_VLAN_ID_SFT 0 8291ac5a404SSelvin Xavier #define CREQ_QUERY_QP_RESP_SB_VLAN_DEI 0x1000UL 8301ac5a404SSelvin Xavier #define CREQ_QUERY_QP_RESP_SB_VLAN_PCP_MASK 0xe000UL 8311ac5a404SSelvin Xavier #define CREQ_QUERY_QP_RESP_SB_VLAN_PCP_SFT 13 8321ac5a404SSelvin Xavier }; 8331ac5a404SSelvin Xavier 834a9a457f3SSelvin Xavier /* cmdq_query_qp_extend (size:192b/24B) */ 835a9a457f3SSelvin Xavier struct cmdq_query_qp_extend { 836a9a457f3SSelvin Xavier u8 opcode; 837a9a457f3SSelvin Xavier #define CMDQ_QUERY_QP_EXTEND_OPCODE_QUERY_QP_EXTEND 0x91UL 838a9a457f3SSelvin Xavier #define CMDQ_QUERY_QP_EXTEND_OPCODE_LAST CMDQ_QUERY_QP_EXTEND_OPCODE_QUERY_QP_EXTEND 839a9a457f3SSelvin Xavier u8 cmd_size; 840a9a457f3SSelvin Xavier __le16 flags; 841a9a457f3SSelvin Xavier __le16 cookie; 842a9a457f3SSelvin Xavier u8 resp_size; 843a9a457f3SSelvin Xavier u8 num_qps; 844a9a457f3SSelvin Xavier __le64 resp_addr; 845a9a457f3SSelvin Xavier __le32 function_id; 846a9a457f3SSelvin Xavier #define CMDQ_QUERY_QP_EXTEND_PF_NUM_MASK 0xffUL 847a9a457f3SSelvin Xavier #define CMDQ_QUERY_QP_EXTEND_PF_NUM_SFT 0 848a9a457f3SSelvin Xavier #define CMDQ_QUERY_QP_EXTEND_VF_NUM_MASK 0xffff00UL 849a9a457f3SSelvin Xavier #define CMDQ_QUERY_QP_EXTEND_VF_NUM_SFT 8 850a9a457f3SSelvin Xavier #define CMDQ_QUERY_QP_EXTEND_VF_VALID 0x1000000UL 851a9a457f3SSelvin Xavier __le32 current_index; 852a9a457f3SSelvin Xavier }; 853a9a457f3SSelvin Xavier 854a9a457f3SSelvin Xavier /* creq_query_qp_extend_resp (size:128b/16B) */ 855a9a457f3SSelvin Xavier struct creq_query_qp_extend_resp { 856a9a457f3SSelvin Xavier u8 type; 857a9a457f3SSelvin Xavier #define CREQ_QUERY_QP_EXTEND_RESP_TYPE_MASK 0x3fUL 858a9a457f3SSelvin Xavier #define CREQ_QUERY_QP_EXTEND_RESP_TYPE_SFT 0 859a9a457f3SSelvin Xavier #define CREQ_QUERY_QP_EXTEND_RESP_TYPE_QP_EVENT 0x38UL 860a9a457f3SSelvin Xavier #define CREQ_QUERY_QP_EXTEND_RESP_TYPE_LAST CREQ_QUERY_QP_EXTEND_RESP_TYPE_QP_EVENT 861a9a457f3SSelvin Xavier u8 status; 862a9a457f3SSelvin Xavier __le16 cookie; 863a9a457f3SSelvin Xavier __le32 size; 864a9a457f3SSelvin Xavier u8 v; 865a9a457f3SSelvin Xavier #define CREQ_QUERY_QP_EXTEND_RESP_V 0x1UL 866a9a457f3SSelvin Xavier u8 event; 867a9a457f3SSelvin Xavier #define CREQ_QUERY_QP_EXTEND_RESP_EVENT_QUERY_QP_EXTEND 0x91UL 868a9a457f3SSelvin Xavier #define CREQ_QUERY_QP_EXTEND_RESP_EVENT_LAST CREQ_QUERY_QP_EXTEND_RESP_EVENT_QUERY_QP_EXTEND 869a9a457f3SSelvin Xavier __le16 reserved16; 870a9a457f3SSelvin Xavier __le32 current_index; 871a9a457f3SSelvin Xavier }; 872a9a457f3SSelvin Xavier 873a9a457f3SSelvin Xavier /* creq_query_qp_extend_resp_sb (size:384b/48B) */ 874a9a457f3SSelvin Xavier struct creq_query_qp_extend_resp_sb { 875a9a457f3SSelvin Xavier u8 opcode; 876a9a457f3SSelvin Xavier #define CREQ_QUERY_QP_EXTEND_RESP_SB_OPCODE_QUERY_QP_EXTEND 0x91UL 877a9a457f3SSelvin Xavier #define CREQ_QUERY_QP_EXTEND_RESP_SB_OPCODE_LAST \ 878a9a457f3SSelvin Xavier CREQ_QUERY_QP_EXTEND_RESP_SB_OPCODE_QUERY_QP_EXTEND 879a9a457f3SSelvin Xavier u8 status; 880a9a457f3SSelvin Xavier __le16 cookie; 881a9a457f3SSelvin Xavier __le16 flags; 882a9a457f3SSelvin Xavier u8 resp_size; 883a9a457f3SSelvin Xavier u8 reserved8; 884a9a457f3SSelvin Xavier __le32 xid; 885a9a457f3SSelvin Xavier u8 state; 886a9a457f3SSelvin Xavier #define CREQ_QUERY_QP_EXTEND_RESP_SB_STATE_MASK 0xfUL 887a9a457f3SSelvin Xavier #define CREQ_QUERY_QP_EXTEND_RESP_SB_STATE_SFT 0 888a9a457f3SSelvin Xavier #define CREQ_QUERY_QP_EXTEND_RESP_SB_STATE_RESET 0x0UL 889a9a457f3SSelvin Xavier #define CREQ_QUERY_QP_EXTEND_RESP_SB_STATE_INIT 0x1UL 890a9a457f3SSelvin Xavier #define CREQ_QUERY_QP_EXTEND_RESP_SB_STATE_RTR 0x2UL 891a9a457f3SSelvin Xavier #define CREQ_QUERY_QP_EXTEND_RESP_SB_STATE_RTS 0x3UL 892a9a457f3SSelvin Xavier #define CREQ_QUERY_QP_EXTEND_RESP_SB_STATE_SQD 0x4UL 893a9a457f3SSelvin Xavier #define CREQ_QUERY_QP_EXTEND_RESP_SB_STATE_SQE 0x5UL 894a9a457f3SSelvin Xavier #define CREQ_QUERY_QP_EXTEND_RESP_SB_STATE_ERR 0x6UL 895a9a457f3SSelvin Xavier #define CREQ_QUERY_QP_EXTEND_RESP_SB_STATE_LAST CREQ_QUERY_QP_EXTEND_RESP_SB_STATE_ERR 896a9a457f3SSelvin Xavier #define CREQ_QUERY_QP_EXTEND_RESP_SB_UNUSED4_MASK 0xf0UL 897a9a457f3SSelvin Xavier #define CREQ_QUERY_QP_EXTEND_RESP_SB_UNUSED4_SFT 4 898a9a457f3SSelvin Xavier u8 reserved_8; 899a9a457f3SSelvin Xavier __le16 port_id; 900a9a457f3SSelvin Xavier __le32 qkey; 901a9a457f3SSelvin Xavier __le16 sgid_index; 902a9a457f3SSelvin Xavier u8 network_type; 903a9a457f3SSelvin Xavier #define CREQ_QUERY_QP_EXTEND_RESP_SB_NETWORK_TYPE_ROCEV1 0x0UL 904a9a457f3SSelvin Xavier #define CREQ_QUERY_QP_EXTEND_RESP_SB_NETWORK_TYPE_ROCEV2_IPV4 0x2UL 905a9a457f3SSelvin Xavier #define CREQ_QUERY_QP_EXTEND_RESP_SB_NETWORK_TYPE_ROCEV2_IPV6 0x3UL 906a9a457f3SSelvin Xavier #define CREQ_QUERY_QP_EXTEND_RESP_SB_NETWORK_TYPE_LAST \ 907a9a457f3SSelvin Xavier CREQ_QUERY_QP_EXTEND_RESP_SB_NETWORK_TYPE_ROCEV2_IPV6 908a9a457f3SSelvin Xavier u8 unused_0; 909a9a457f3SSelvin Xavier __le32 dgid[4]; 910a9a457f3SSelvin Xavier __le32 dest_qp_id; 911a9a457f3SSelvin Xavier u8 stat_collection_id; 912a9a457f3SSelvin Xavier u8 reservred_8; 913a9a457f3SSelvin Xavier __le16 reserved_16; 914a9a457f3SSelvin Xavier }; 915a9a457f3SSelvin Xavier 916a9a457f3SSelvin Xavier /* creq_query_qp_extend_resp_sb_tlv (size:512b/64B) */ 917a9a457f3SSelvin Xavier struct creq_query_qp_extend_resp_sb_tlv { 918a9a457f3SSelvin Xavier __le16 cmd_discr; 919a9a457f3SSelvin Xavier u8 reserved_8b; 920a9a457f3SSelvin Xavier u8 tlv_flags; 921a9a457f3SSelvin Xavier #define CREQ_QUERY_QP_EXTEND_RESP_SB_TLV_TLV_FLAGS_MORE 0x1UL 922a9a457f3SSelvin Xavier #define CREQ_QUERY_QP_EXTEND_RESP_SB_TLV_TLV_FLAGS_MORE_LAST 0x0UL 923a9a457f3SSelvin Xavier #define CREQ_QUERY_QP_EXTEND_RESP_SB_TLV_TLV_FLAGS_MORE_NOT_LAST 0x1UL 924a9a457f3SSelvin Xavier #define CREQ_QUERY_QP_EXTEND_RESP_SB_TLV_TLV_FLAGS_REQUIRED 0x2UL 925a9a457f3SSelvin Xavier #define CREQ_QUERY_QP_EXTEND_RESP_SB_TLV_TLV_FLAGS_REQUIRED_NO (0x0UL << 1) 926a9a457f3SSelvin Xavier #define CREQ_QUERY_QP_EXTEND_RESP_SB_TLV_TLV_FLAGS_REQUIRED_YES (0x1UL << 1) 927a9a457f3SSelvin Xavier #define CREQ_QUERY_QP_EXTEND_RESP_SB_TLV_TLV_FLAGS_REQUIRED_LAST \ 928a9a457f3SSelvin Xavier CREQ_QUERY_QP_EXTEND_RESP_SB_TLV_TLV_FLAGS_REQUIRED_YES 929a9a457f3SSelvin Xavier __le16 tlv_type; 930a9a457f3SSelvin Xavier __le16 length; 931a9a457f3SSelvin Xavier u8 total_size; 932a9a457f3SSelvin Xavier u8 reserved56[7]; 933a9a457f3SSelvin Xavier u8 opcode; 934a9a457f3SSelvin Xavier #define CREQ_QUERY_QP_EXTEND_RESP_SB_TLV_OPCODE_QUERY_QP_EXTEND 0x91UL 935a9a457f3SSelvin Xavier #define CREQ_QUERY_QP_EXTEND_RESP_SB_TLV_OPCODE_LAST \ 936a9a457f3SSelvin Xavier CREQ_QUERY_QP_EXTEND_RESP_SB_TLV_OPCODE_QUERY_QP_EXTEND 937a9a457f3SSelvin Xavier u8 status; 938a9a457f3SSelvin Xavier __le16 cookie; 939a9a457f3SSelvin Xavier __le16 flags; 940a9a457f3SSelvin Xavier u8 resp_size; 941a9a457f3SSelvin Xavier u8 reserved8; 942a9a457f3SSelvin Xavier __le32 xid; 943a9a457f3SSelvin Xavier u8 state; 944a9a457f3SSelvin Xavier #define CREQ_QUERY_QP_EXTEND_RESP_SB_TLV_STATE_MASK 0xfUL 945a9a457f3SSelvin Xavier #define CREQ_QUERY_QP_EXTEND_RESP_SB_TLV_STATE_SFT 0 946a9a457f3SSelvin Xavier #define CREQ_QUERY_QP_EXTEND_RESP_SB_TLV_STATE_RESET 0x0UL 947a9a457f3SSelvin Xavier #define CREQ_QUERY_QP_EXTEND_RESP_SB_TLV_STATE_INIT 0x1UL 948a9a457f3SSelvin Xavier #define CREQ_QUERY_QP_EXTEND_RESP_SB_TLV_STATE_RTR 0x2UL 949a9a457f3SSelvin Xavier #define CREQ_QUERY_QP_EXTEND_RESP_SB_TLV_STATE_RTS 0x3UL 950a9a457f3SSelvin Xavier #define CREQ_QUERY_QP_EXTEND_RESP_SB_TLV_STATE_SQD 0x4UL 951a9a457f3SSelvin Xavier #define CREQ_QUERY_QP_EXTEND_RESP_SB_TLV_STATE_SQE 0x5UL 952a9a457f3SSelvin Xavier #define CREQ_QUERY_QP_EXTEND_RESP_SB_TLV_STATE_ERR 0x6UL 953a9a457f3SSelvin Xavier #define CREQ_QUERY_QP_EXTEND_RESP_SB_TLV_STATE_LAST \ 954a9a457f3SSelvin Xavier CREQ_QUERY_QP_EXTEND_RESP_SB_TLV_STATE_ERR 955a9a457f3SSelvin Xavier #define CREQ_QUERY_QP_EXTEND_RESP_SB_TLV_UNUSED4_MASK 0xf0UL 956a9a457f3SSelvin Xavier #define CREQ_QUERY_QP_EXTEND_RESP_SB_TLV_UNUSED4_SFT 4 957a9a457f3SSelvin Xavier u8 reserved_8; 958a9a457f3SSelvin Xavier __le16 port_id; 959a9a457f3SSelvin Xavier __le32 qkey; 960a9a457f3SSelvin Xavier __le16 sgid_index; 961a9a457f3SSelvin Xavier u8 network_type; 962a9a457f3SSelvin Xavier #define CREQ_QUERY_QP_EXTEND_RESP_SB_TLV_NETWORK_TYPE_ROCEV1 0x0UL 963a9a457f3SSelvin Xavier #define CREQ_QUERY_QP_EXTEND_RESP_SB_TLV_NETWORK_TYPE_ROCEV2_IPV4 0x2UL 964a9a457f3SSelvin Xavier #define CREQ_QUERY_QP_EXTEND_RESP_SB_TLV_NETWORK_TYPE_ROCEV2_IPV6 0x3UL 965a9a457f3SSelvin Xavier #define CREQ_QUERY_QP_EXTEND_RESP_SB_TLV_NETWORK_TYPE_LAST \ 966a9a457f3SSelvin Xavier CREQ_QUERY_QP_EXTEND_RESP_SB_TLV_NETWORK_TYPE_ROCEV2_IPV6 967a9a457f3SSelvin Xavier u8 unused_0; 968a9a457f3SSelvin Xavier __le32 dgid[4]; 969a9a457f3SSelvin Xavier __le32 dest_qp_id; 970a9a457f3SSelvin Xavier u8 stat_collection_id; 971a9a457f3SSelvin Xavier u8 reservred_8; 972a9a457f3SSelvin Xavier __le16 reserved_16; 973a9a457f3SSelvin Xavier }; 974a9a457f3SSelvin Xavier 975a9a457f3SSelvin Xavier /* cmdq_create_srq (size:384b/48B) */ 976a9a457f3SSelvin Xavier struct cmdq_create_srq { 977a9a457f3SSelvin Xavier u8 opcode; 978a9a457f3SSelvin Xavier #define CMDQ_CREATE_SRQ_OPCODE_CREATE_SRQ 0x5UL 979a9a457f3SSelvin Xavier #define CMDQ_CREATE_SRQ_OPCODE_LAST CMDQ_CREATE_SRQ_OPCODE_CREATE_SRQ 980a9a457f3SSelvin Xavier u8 cmd_size; 981a9a457f3SSelvin Xavier __le16 flags; 982a9a457f3SSelvin Xavier __le16 cookie; 983a9a457f3SSelvin Xavier u8 resp_size; 984a9a457f3SSelvin Xavier u8 reserved8; 985a9a457f3SSelvin Xavier __le64 resp_addr; 986a9a457f3SSelvin Xavier __le64 srq_handle; 987a9a457f3SSelvin Xavier __le16 pg_size_lvl; 988a9a457f3SSelvin Xavier #define CMDQ_CREATE_SRQ_LVL_MASK 0x3UL 989a9a457f3SSelvin Xavier #define CMDQ_CREATE_SRQ_LVL_SFT 0 990a9a457f3SSelvin Xavier #define CMDQ_CREATE_SRQ_LVL_LVL_0 0x0UL 991a9a457f3SSelvin Xavier #define CMDQ_CREATE_SRQ_LVL_LVL_1 0x1UL 992a9a457f3SSelvin Xavier #define CMDQ_CREATE_SRQ_LVL_LVL_2 0x2UL 993a9a457f3SSelvin Xavier #define CMDQ_CREATE_SRQ_LVL_LAST CMDQ_CREATE_SRQ_LVL_LVL_2 994a9a457f3SSelvin Xavier #define CMDQ_CREATE_SRQ_PG_SIZE_MASK 0x1cUL 995a9a457f3SSelvin Xavier #define CMDQ_CREATE_SRQ_PG_SIZE_SFT 2 996a9a457f3SSelvin Xavier #define CMDQ_CREATE_SRQ_PG_SIZE_PG_4K (0x0UL << 2) 997a9a457f3SSelvin Xavier #define CMDQ_CREATE_SRQ_PG_SIZE_PG_8K (0x1UL << 2) 998a9a457f3SSelvin Xavier #define CMDQ_CREATE_SRQ_PG_SIZE_PG_64K (0x2UL << 2) 999a9a457f3SSelvin Xavier #define CMDQ_CREATE_SRQ_PG_SIZE_PG_2M (0x3UL << 2) 1000a9a457f3SSelvin Xavier #define CMDQ_CREATE_SRQ_PG_SIZE_PG_8M (0x4UL << 2) 1001a9a457f3SSelvin Xavier #define CMDQ_CREATE_SRQ_PG_SIZE_PG_1G (0x5UL << 2) 1002a9a457f3SSelvin Xavier #define CMDQ_CREATE_SRQ_PG_SIZE_LAST CMDQ_CREATE_SRQ_PG_SIZE_PG_1G 1003a9a457f3SSelvin Xavier #define CMDQ_CREATE_SRQ_UNUSED11_MASK 0xffe0UL 1004a9a457f3SSelvin Xavier #define CMDQ_CREATE_SRQ_UNUSED11_SFT 5 1005a9a457f3SSelvin Xavier __le16 eventq_id; 1006a9a457f3SSelvin Xavier #define CMDQ_CREATE_SRQ_EVENTQ_ID_MASK 0xfffUL 1007a9a457f3SSelvin Xavier #define CMDQ_CREATE_SRQ_EVENTQ_ID_SFT 0 1008a9a457f3SSelvin Xavier #define CMDQ_CREATE_SRQ_UNUSED4_MASK 0xf000UL 1009a9a457f3SSelvin Xavier #define CMDQ_CREATE_SRQ_UNUSED4_SFT 12 1010a9a457f3SSelvin Xavier __le16 srq_size; 1011a9a457f3SSelvin Xavier __le16 srq_fwo; 1012a9a457f3SSelvin Xavier __le32 dpi; 1013a9a457f3SSelvin Xavier __le32 pd_id; 1014a9a457f3SSelvin Xavier __le64 pbl; 1015a9a457f3SSelvin Xavier }; 1016a9a457f3SSelvin Xavier 1017a9a457f3SSelvin Xavier /* creq_create_srq_resp (size:128b/16B) */ 10181ac5a404SSelvin Xavier struct creq_create_srq_resp { 10191ac5a404SSelvin Xavier u8 type; 10201ac5a404SSelvin Xavier #define CREQ_CREATE_SRQ_RESP_TYPE_MASK 0x3fUL 10211ac5a404SSelvin Xavier #define CREQ_CREATE_SRQ_RESP_TYPE_SFT 0 10221ac5a404SSelvin Xavier #define CREQ_CREATE_SRQ_RESP_TYPE_QP_EVENT 0x38UL 1023a9a457f3SSelvin Xavier #define CREQ_CREATE_SRQ_RESP_TYPE_LAST CREQ_CREATE_SRQ_RESP_TYPE_QP_EVENT 10241ac5a404SSelvin Xavier u8 status; 10251ac5a404SSelvin Xavier __le16 cookie; 10261ac5a404SSelvin Xavier __le32 xid; 10271ac5a404SSelvin Xavier u8 v; 10281ac5a404SSelvin Xavier #define CREQ_CREATE_SRQ_RESP_V 0x1UL 10291ac5a404SSelvin Xavier u8 event; 10301ac5a404SSelvin Xavier #define CREQ_CREATE_SRQ_RESP_EVENT_CREATE_SRQ 0x5UL 1031a9a457f3SSelvin Xavier #define CREQ_CREATE_SRQ_RESP_EVENT_LAST CREQ_CREATE_SRQ_RESP_EVENT_CREATE_SRQ 1032a9a457f3SSelvin Xavier u8 reserved48[6]; 10331ac5a404SSelvin Xavier }; 10341ac5a404SSelvin Xavier 1035a9a457f3SSelvin Xavier /* cmdq_destroy_srq (size:192b/24B) */ 1036a9a457f3SSelvin Xavier struct cmdq_destroy_srq { 1037a9a457f3SSelvin Xavier u8 opcode; 1038a9a457f3SSelvin Xavier #define CMDQ_DESTROY_SRQ_OPCODE_DESTROY_SRQ 0x6UL 1039a9a457f3SSelvin Xavier #define CMDQ_DESTROY_SRQ_OPCODE_LAST CMDQ_DESTROY_SRQ_OPCODE_DESTROY_SRQ 1040a9a457f3SSelvin Xavier u8 cmd_size; 1041a9a457f3SSelvin Xavier __le16 flags; 1042a9a457f3SSelvin Xavier __le16 cookie; 1043a9a457f3SSelvin Xavier u8 resp_size; 1044a9a457f3SSelvin Xavier u8 reserved8; 1045a9a457f3SSelvin Xavier __le64 resp_addr; 1046a9a457f3SSelvin Xavier __le32 srq_cid; 1047a9a457f3SSelvin Xavier __le32 unused_0; 1048a9a457f3SSelvin Xavier }; 1049a9a457f3SSelvin Xavier 1050a9a457f3SSelvin Xavier /* creq_destroy_srq_resp (size:128b/16B) */ 10511ac5a404SSelvin Xavier struct creq_destroy_srq_resp { 10521ac5a404SSelvin Xavier u8 type; 10531ac5a404SSelvin Xavier #define CREQ_DESTROY_SRQ_RESP_TYPE_MASK 0x3fUL 10541ac5a404SSelvin Xavier #define CREQ_DESTROY_SRQ_RESP_TYPE_SFT 0 10551ac5a404SSelvin Xavier #define CREQ_DESTROY_SRQ_RESP_TYPE_QP_EVENT 0x38UL 1056a9a457f3SSelvin Xavier #define CREQ_DESTROY_SRQ_RESP_TYPE_LAST CREQ_DESTROY_SRQ_RESP_TYPE_QP_EVENT 10571ac5a404SSelvin Xavier u8 status; 10581ac5a404SSelvin Xavier __le16 cookie; 10591ac5a404SSelvin Xavier __le32 xid; 10601ac5a404SSelvin Xavier u8 v; 10611ac5a404SSelvin Xavier #define CREQ_DESTROY_SRQ_RESP_V 0x1UL 10621ac5a404SSelvin Xavier u8 event; 10631ac5a404SSelvin Xavier #define CREQ_DESTROY_SRQ_RESP_EVENT_DESTROY_SRQ 0x6UL 1064a9a457f3SSelvin Xavier #define CREQ_DESTROY_SRQ_RESP_EVENT_LAST CREQ_DESTROY_SRQ_RESP_EVENT_DESTROY_SRQ 10651ac5a404SSelvin Xavier __le16 enable_for_arm[3]; 1066a9a457f3SSelvin Xavier #define CREQ_DESTROY_SRQ_RESP_UNUSED0_MASK 0xffffUL 1067a9a457f3SSelvin Xavier #define CREQ_DESTROY_SRQ_RESP_UNUSED0_SFT 0 10681ac5a404SSelvin Xavier #define CREQ_DESTROY_SRQ_RESP_ENABLE_FOR_ARM_MASK 0x30000UL 10691ac5a404SSelvin Xavier #define CREQ_DESTROY_SRQ_RESP_ENABLE_FOR_ARM_SFT 16 10701ac5a404SSelvin Xavier }; 10711ac5a404SSelvin Xavier 1072a9a457f3SSelvin Xavier /* cmdq_query_srq (size:192b/24B) */ 1073a9a457f3SSelvin Xavier struct cmdq_query_srq { 1074a9a457f3SSelvin Xavier u8 opcode; 1075a9a457f3SSelvin Xavier #define CMDQ_QUERY_SRQ_OPCODE_QUERY_SRQ 0x8UL 1076a9a457f3SSelvin Xavier #define CMDQ_QUERY_SRQ_OPCODE_LAST CMDQ_QUERY_SRQ_OPCODE_QUERY_SRQ 1077a9a457f3SSelvin Xavier u8 cmd_size; 1078a9a457f3SSelvin Xavier __le16 flags; 1079a9a457f3SSelvin Xavier __le16 cookie; 1080a9a457f3SSelvin Xavier u8 resp_size; 1081a9a457f3SSelvin Xavier u8 reserved8; 1082a9a457f3SSelvin Xavier __le64 resp_addr; 1083a9a457f3SSelvin Xavier __le32 srq_cid; 1084a9a457f3SSelvin Xavier __le32 unused_0; 1085a9a457f3SSelvin Xavier }; 1086a9a457f3SSelvin Xavier 1087a9a457f3SSelvin Xavier /* creq_query_srq_resp (size:128b/16B) */ 10881ac5a404SSelvin Xavier struct creq_query_srq_resp { 10891ac5a404SSelvin Xavier u8 type; 10901ac5a404SSelvin Xavier #define CREQ_QUERY_SRQ_RESP_TYPE_MASK 0x3fUL 10911ac5a404SSelvin Xavier #define CREQ_QUERY_SRQ_RESP_TYPE_SFT 0 10921ac5a404SSelvin Xavier #define CREQ_QUERY_SRQ_RESP_TYPE_QP_EVENT 0x38UL 1093a9a457f3SSelvin Xavier #define CREQ_QUERY_SRQ_RESP_TYPE_LAST CREQ_QUERY_SRQ_RESP_TYPE_QP_EVENT 10941ac5a404SSelvin Xavier u8 status; 10951ac5a404SSelvin Xavier __le16 cookie; 10961ac5a404SSelvin Xavier __le32 size; 10971ac5a404SSelvin Xavier u8 v; 10981ac5a404SSelvin Xavier #define CREQ_QUERY_SRQ_RESP_V 0x1UL 10991ac5a404SSelvin Xavier u8 event; 11001ac5a404SSelvin Xavier #define CREQ_QUERY_SRQ_RESP_EVENT_QUERY_SRQ 0x8UL 1101a9a457f3SSelvin Xavier #define CREQ_QUERY_SRQ_RESP_EVENT_LAST CREQ_QUERY_SRQ_RESP_EVENT_QUERY_SRQ 1102a9a457f3SSelvin Xavier u8 reserved48[6]; 11031ac5a404SSelvin Xavier }; 11041ac5a404SSelvin Xavier 1105a9a457f3SSelvin Xavier /* creq_query_srq_resp_sb (size:256b/32B) */ 11061ac5a404SSelvin Xavier struct creq_query_srq_resp_sb { 11071ac5a404SSelvin Xavier u8 opcode; 11081ac5a404SSelvin Xavier #define CREQ_QUERY_SRQ_RESP_SB_OPCODE_QUERY_SRQ 0x8UL 1109a9a457f3SSelvin Xavier #define CREQ_QUERY_SRQ_RESP_SB_OPCODE_LAST CREQ_QUERY_SRQ_RESP_SB_OPCODE_QUERY_SRQ 11101ac5a404SSelvin Xavier u8 status; 11111ac5a404SSelvin Xavier __le16 cookie; 11121ac5a404SSelvin Xavier __le16 flags; 11131ac5a404SSelvin Xavier u8 resp_size; 11141ac5a404SSelvin Xavier u8 reserved8; 11151ac5a404SSelvin Xavier __le32 xid; 11161ac5a404SSelvin Xavier __le16 srq_limit; 11171ac5a404SSelvin Xavier __le16 reserved16; 11181ac5a404SSelvin Xavier __le32 data[4]; 11191ac5a404SSelvin Xavier }; 11201ac5a404SSelvin Xavier 1121a9a457f3SSelvin Xavier /* cmdq_create_cq (size:384b/48B) */ 1122a9a457f3SSelvin Xavier struct cmdq_create_cq { 1123a9a457f3SSelvin Xavier u8 opcode; 1124a9a457f3SSelvin Xavier #define CMDQ_CREATE_CQ_OPCODE_CREATE_CQ 0x9UL 1125a9a457f3SSelvin Xavier #define CMDQ_CREATE_CQ_OPCODE_LAST CMDQ_CREATE_CQ_OPCODE_CREATE_CQ 1126a9a457f3SSelvin Xavier u8 cmd_size; 1127a9a457f3SSelvin Xavier __le16 flags; 1128a9a457f3SSelvin Xavier #define CMDQ_CREATE_CQ_FLAGS_DISABLE_CQ_OVERFLOW_DETECTION 0x1UL 1129a9a457f3SSelvin Xavier __le16 cookie; 1130a9a457f3SSelvin Xavier u8 resp_size; 1131a9a457f3SSelvin Xavier u8 reserved8; 1132a9a457f3SSelvin Xavier __le64 resp_addr; 1133a9a457f3SSelvin Xavier __le64 cq_handle; 1134a9a457f3SSelvin Xavier __le32 pg_size_lvl; 1135a9a457f3SSelvin Xavier #define CMDQ_CREATE_CQ_LVL_MASK 0x3UL 1136a9a457f3SSelvin Xavier #define CMDQ_CREATE_CQ_LVL_SFT 0 1137a9a457f3SSelvin Xavier #define CMDQ_CREATE_CQ_LVL_LVL_0 0x0UL 1138a9a457f3SSelvin Xavier #define CMDQ_CREATE_CQ_LVL_LVL_1 0x1UL 1139a9a457f3SSelvin Xavier #define CMDQ_CREATE_CQ_LVL_LVL_2 0x2UL 1140a9a457f3SSelvin Xavier #define CMDQ_CREATE_CQ_LVL_LAST CMDQ_CREATE_CQ_LVL_LVL_2 1141a9a457f3SSelvin Xavier #define CMDQ_CREATE_CQ_PG_SIZE_MASK 0x1cUL 1142a9a457f3SSelvin Xavier #define CMDQ_CREATE_CQ_PG_SIZE_SFT 2 1143a9a457f3SSelvin Xavier #define CMDQ_CREATE_CQ_PG_SIZE_PG_4K (0x0UL << 2) 1144a9a457f3SSelvin Xavier #define CMDQ_CREATE_CQ_PG_SIZE_PG_8K (0x1UL << 2) 1145a9a457f3SSelvin Xavier #define CMDQ_CREATE_CQ_PG_SIZE_PG_64K (0x2UL << 2) 1146a9a457f3SSelvin Xavier #define CMDQ_CREATE_CQ_PG_SIZE_PG_2M (0x3UL << 2) 1147a9a457f3SSelvin Xavier #define CMDQ_CREATE_CQ_PG_SIZE_PG_8M (0x4UL << 2) 1148a9a457f3SSelvin Xavier #define CMDQ_CREATE_CQ_PG_SIZE_PG_1G (0x5UL << 2) 1149a9a457f3SSelvin Xavier #define CMDQ_CREATE_CQ_PG_SIZE_LAST CMDQ_CREATE_CQ_PG_SIZE_PG_1G 1150a9a457f3SSelvin Xavier #define CMDQ_CREATE_CQ_UNUSED27_MASK 0xffffffe0UL 1151a9a457f3SSelvin Xavier #define CMDQ_CREATE_CQ_UNUSED27_SFT 5 1152a9a457f3SSelvin Xavier __le32 cq_fco_cnq_id; 1153a9a457f3SSelvin Xavier #define CMDQ_CREATE_CQ_CNQ_ID_MASK 0xfffUL 1154a9a457f3SSelvin Xavier #define CMDQ_CREATE_CQ_CNQ_ID_SFT 0 1155a9a457f3SSelvin Xavier #define CMDQ_CREATE_CQ_CQ_FCO_MASK 0xfffff000UL 1156a9a457f3SSelvin Xavier #define CMDQ_CREATE_CQ_CQ_FCO_SFT 12 1157a9a457f3SSelvin Xavier __le32 dpi; 1158a9a457f3SSelvin Xavier __le32 cq_size; 1159a9a457f3SSelvin Xavier __le64 pbl; 1160a9a457f3SSelvin Xavier }; 1161a9a457f3SSelvin Xavier 1162a9a457f3SSelvin Xavier /* creq_create_cq_resp (size:128b/16B) */ 11631ac5a404SSelvin Xavier struct creq_create_cq_resp { 11641ac5a404SSelvin Xavier u8 type; 11651ac5a404SSelvin Xavier #define CREQ_CREATE_CQ_RESP_TYPE_MASK 0x3fUL 11661ac5a404SSelvin Xavier #define CREQ_CREATE_CQ_RESP_TYPE_SFT 0 11671ac5a404SSelvin Xavier #define CREQ_CREATE_CQ_RESP_TYPE_QP_EVENT 0x38UL 1168a9a457f3SSelvin Xavier #define CREQ_CREATE_CQ_RESP_TYPE_LAST CREQ_CREATE_CQ_RESP_TYPE_QP_EVENT 11691ac5a404SSelvin Xavier u8 status; 11701ac5a404SSelvin Xavier __le16 cookie; 11711ac5a404SSelvin Xavier __le32 xid; 11721ac5a404SSelvin Xavier u8 v; 11731ac5a404SSelvin Xavier #define CREQ_CREATE_CQ_RESP_V 0x1UL 11741ac5a404SSelvin Xavier u8 event; 11751ac5a404SSelvin Xavier #define CREQ_CREATE_CQ_RESP_EVENT_CREATE_CQ 0x9UL 1176a9a457f3SSelvin Xavier #define CREQ_CREATE_CQ_RESP_EVENT_LAST CREQ_CREATE_CQ_RESP_EVENT_CREATE_CQ 1177a9a457f3SSelvin Xavier u8 reserved48[6]; 11781ac5a404SSelvin Xavier }; 11791ac5a404SSelvin Xavier 1180a9a457f3SSelvin Xavier /* cmdq_destroy_cq (size:192b/24B) */ 1181a9a457f3SSelvin Xavier struct cmdq_destroy_cq { 1182a9a457f3SSelvin Xavier u8 opcode; 1183a9a457f3SSelvin Xavier #define CMDQ_DESTROY_CQ_OPCODE_DESTROY_CQ 0xaUL 1184a9a457f3SSelvin Xavier #define CMDQ_DESTROY_CQ_OPCODE_LAST CMDQ_DESTROY_CQ_OPCODE_DESTROY_CQ 1185a9a457f3SSelvin Xavier u8 cmd_size; 1186a9a457f3SSelvin Xavier __le16 flags; 1187a9a457f3SSelvin Xavier __le16 cookie; 1188a9a457f3SSelvin Xavier u8 resp_size; 1189a9a457f3SSelvin Xavier u8 reserved8; 1190a9a457f3SSelvin Xavier __le64 resp_addr; 1191a9a457f3SSelvin Xavier __le32 cq_cid; 1192a9a457f3SSelvin Xavier __le32 unused_0; 1193a9a457f3SSelvin Xavier }; 1194a9a457f3SSelvin Xavier 1195a9a457f3SSelvin Xavier /* creq_destroy_cq_resp (size:128b/16B) */ 11961ac5a404SSelvin Xavier struct creq_destroy_cq_resp { 11971ac5a404SSelvin Xavier u8 type; 11981ac5a404SSelvin Xavier #define CREQ_DESTROY_CQ_RESP_TYPE_MASK 0x3fUL 11991ac5a404SSelvin Xavier #define CREQ_DESTROY_CQ_RESP_TYPE_SFT 0 12001ac5a404SSelvin Xavier #define CREQ_DESTROY_CQ_RESP_TYPE_QP_EVENT 0x38UL 1201a9a457f3SSelvin Xavier #define CREQ_DESTROY_CQ_RESP_TYPE_LAST CREQ_DESTROY_CQ_RESP_TYPE_QP_EVENT 12021ac5a404SSelvin Xavier u8 status; 12031ac5a404SSelvin Xavier __le16 cookie; 12041ac5a404SSelvin Xavier __le32 xid; 12051ac5a404SSelvin Xavier u8 v; 12061ac5a404SSelvin Xavier #define CREQ_DESTROY_CQ_RESP_V 0x1UL 12071ac5a404SSelvin Xavier u8 event; 12081ac5a404SSelvin Xavier #define CREQ_DESTROY_CQ_RESP_EVENT_DESTROY_CQ 0xaUL 1209a9a457f3SSelvin Xavier #define CREQ_DESTROY_CQ_RESP_EVENT_LAST CREQ_DESTROY_CQ_RESP_EVENT_DESTROY_CQ 12101ac5a404SSelvin Xavier __le16 cq_arm_lvl; 12111ac5a404SSelvin Xavier #define CREQ_DESTROY_CQ_RESP_CQ_ARM_LVL_MASK 0x3UL 12121ac5a404SSelvin Xavier #define CREQ_DESTROY_CQ_RESP_CQ_ARM_LVL_SFT 0 12131ac5a404SSelvin Xavier __le16 total_cnq_events; 12141ac5a404SSelvin Xavier __le16 reserved16; 12151ac5a404SSelvin Xavier }; 12161ac5a404SSelvin Xavier 1217a9a457f3SSelvin Xavier /* cmdq_resize_cq (size:320b/40B) */ 1218a9a457f3SSelvin Xavier struct cmdq_resize_cq { 1219a9a457f3SSelvin Xavier u8 opcode; 1220a9a457f3SSelvin Xavier #define CMDQ_RESIZE_CQ_OPCODE_RESIZE_CQ 0xcUL 1221a9a457f3SSelvin Xavier #define CMDQ_RESIZE_CQ_OPCODE_LAST CMDQ_RESIZE_CQ_OPCODE_RESIZE_CQ 1222a9a457f3SSelvin Xavier u8 cmd_size; 1223a9a457f3SSelvin Xavier __le16 flags; 1224a9a457f3SSelvin Xavier __le16 cookie; 1225a9a457f3SSelvin Xavier u8 resp_size; 1226a9a457f3SSelvin Xavier u8 reserved8; 1227a9a457f3SSelvin Xavier __le64 resp_addr; 1228a9a457f3SSelvin Xavier __le32 cq_cid; 1229a9a457f3SSelvin Xavier __le32 new_cq_size_pg_size_lvl; 1230a9a457f3SSelvin Xavier #define CMDQ_RESIZE_CQ_LVL_MASK 0x3UL 1231a9a457f3SSelvin Xavier #define CMDQ_RESIZE_CQ_LVL_SFT 0 1232a9a457f3SSelvin Xavier #define CMDQ_RESIZE_CQ_LVL_LVL_0 0x0UL 1233a9a457f3SSelvin Xavier #define CMDQ_RESIZE_CQ_LVL_LVL_1 0x1UL 1234a9a457f3SSelvin Xavier #define CMDQ_RESIZE_CQ_LVL_LVL_2 0x2UL 1235a9a457f3SSelvin Xavier #define CMDQ_RESIZE_CQ_LVL_LAST CMDQ_RESIZE_CQ_LVL_LVL_2 1236a9a457f3SSelvin Xavier #define CMDQ_RESIZE_CQ_PG_SIZE_MASK 0x1cUL 1237a9a457f3SSelvin Xavier #define CMDQ_RESIZE_CQ_PG_SIZE_SFT 2 1238a9a457f3SSelvin Xavier #define CMDQ_RESIZE_CQ_PG_SIZE_PG_4K (0x0UL << 2) 1239a9a457f3SSelvin Xavier #define CMDQ_RESIZE_CQ_PG_SIZE_PG_8K (0x1UL << 2) 1240a9a457f3SSelvin Xavier #define CMDQ_RESIZE_CQ_PG_SIZE_PG_64K (0x2UL << 2) 1241a9a457f3SSelvin Xavier #define CMDQ_RESIZE_CQ_PG_SIZE_PG_2M (0x3UL << 2) 1242a9a457f3SSelvin Xavier #define CMDQ_RESIZE_CQ_PG_SIZE_PG_8M (0x4UL << 2) 1243a9a457f3SSelvin Xavier #define CMDQ_RESIZE_CQ_PG_SIZE_PG_1G (0x5UL << 2) 1244a9a457f3SSelvin Xavier #define CMDQ_RESIZE_CQ_PG_SIZE_LAST CMDQ_RESIZE_CQ_PG_SIZE_PG_1G 1245a9a457f3SSelvin Xavier #define CMDQ_RESIZE_CQ_NEW_CQ_SIZE_MASK 0x1fffffe0UL 1246a9a457f3SSelvin Xavier #define CMDQ_RESIZE_CQ_NEW_CQ_SIZE_SFT 5 1247a9a457f3SSelvin Xavier __le64 new_pbl; 1248a9a457f3SSelvin Xavier __le32 new_cq_fco; 1249a9a457f3SSelvin Xavier __le32 unused_0; 1250a9a457f3SSelvin Xavier }; 1251a9a457f3SSelvin Xavier 1252a9a457f3SSelvin Xavier /* creq_resize_cq_resp (size:128b/16B) */ 12531ac5a404SSelvin Xavier struct creq_resize_cq_resp { 12541ac5a404SSelvin Xavier u8 type; 12551ac5a404SSelvin Xavier #define CREQ_RESIZE_CQ_RESP_TYPE_MASK 0x3fUL 12561ac5a404SSelvin Xavier #define CREQ_RESIZE_CQ_RESP_TYPE_SFT 0 12571ac5a404SSelvin Xavier #define CREQ_RESIZE_CQ_RESP_TYPE_QP_EVENT 0x38UL 1258a9a457f3SSelvin Xavier #define CREQ_RESIZE_CQ_RESP_TYPE_LAST CREQ_RESIZE_CQ_RESP_TYPE_QP_EVENT 12591ac5a404SSelvin Xavier u8 status; 12601ac5a404SSelvin Xavier __le16 cookie; 12611ac5a404SSelvin Xavier __le32 xid; 12621ac5a404SSelvin Xavier u8 v; 12631ac5a404SSelvin Xavier #define CREQ_RESIZE_CQ_RESP_V 0x1UL 12641ac5a404SSelvin Xavier u8 event; 12651ac5a404SSelvin Xavier #define CREQ_RESIZE_CQ_RESP_EVENT_RESIZE_CQ 0xcUL 1266a9a457f3SSelvin Xavier #define CREQ_RESIZE_CQ_RESP_EVENT_LAST CREQ_RESIZE_CQ_RESP_EVENT_RESIZE_CQ 1267a9a457f3SSelvin Xavier u8 reserved48[6]; 12681ac5a404SSelvin Xavier }; 12691ac5a404SSelvin Xavier 1270a9a457f3SSelvin Xavier /* cmdq_allocate_mrw (size:256b/32B) */ 1271a9a457f3SSelvin Xavier struct cmdq_allocate_mrw { 1272a9a457f3SSelvin Xavier u8 opcode; 1273a9a457f3SSelvin Xavier #define CMDQ_ALLOCATE_MRW_OPCODE_ALLOCATE_MRW 0xdUL 1274a9a457f3SSelvin Xavier #define CMDQ_ALLOCATE_MRW_OPCODE_LAST CMDQ_ALLOCATE_MRW_OPCODE_ALLOCATE_MRW 1275a9a457f3SSelvin Xavier u8 cmd_size; 1276a9a457f3SSelvin Xavier __le16 flags; 1277a9a457f3SSelvin Xavier __le16 cookie; 1278a9a457f3SSelvin Xavier u8 resp_size; 1279a9a457f3SSelvin Xavier u8 reserved8; 1280a9a457f3SSelvin Xavier __le64 resp_addr; 1281a9a457f3SSelvin Xavier __le64 mrw_handle; 1282a9a457f3SSelvin Xavier u8 mrw_flags; 1283a9a457f3SSelvin Xavier #define CMDQ_ALLOCATE_MRW_MRW_FLAGS_MASK 0xfUL 1284a9a457f3SSelvin Xavier #define CMDQ_ALLOCATE_MRW_MRW_FLAGS_SFT 0 1285a9a457f3SSelvin Xavier #define CMDQ_ALLOCATE_MRW_MRW_FLAGS_MR 0x0UL 1286a9a457f3SSelvin Xavier #define CMDQ_ALLOCATE_MRW_MRW_FLAGS_PMR 0x1UL 1287a9a457f3SSelvin Xavier #define CMDQ_ALLOCATE_MRW_MRW_FLAGS_MW_TYPE1 0x2UL 1288a9a457f3SSelvin Xavier #define CMDQ_ALLOCATE_MRW_MRW_FLAGS_MW_TYPE2A 0x3UL 1289a9a457f3SSelvin Xavier #define CMDQ_ALLOCATE_MRW_MRW_FLAGS_MW_TYPE2B 0x4UL 1290a9a457f3SSelvin Xavier #define CMDQ_ALLOCATE_MRW_MRW_FLAGS_LAST CMDQ_ALLOCATE_MRW_MRW_FLAGS_MW_TYPE2B 1291a9a457f3SSelvin Xavier #define CMDQ_ALLOCATE_MRW_UNUSED4_MASK 0xf0UL 1292a9a457f3SSelvin Xavier #define CMDQ_ALLOCATE_MRW_UNUSED4_SFT 4 1293a9a457f3SSelvin Xavier u8 access; 1294a9a457f3SSelvin Xavier #define CMDQ_ALLOCATE_MRW_ACCESS_CONSUMER_OWNED_KEY 0x20UL 1295a9a457f3SSelvin Xavier __le16 unused16; 1296a9a457f3SSelvin Xavier __le32 pd_id; 1297a9a457f3SSelvin Xavier }; 1298a9a457f3SSelvin Xavier 1299a9a457f3SSelvin Xavier /* creq_allocate_mrw_resp (size:128b/16B) */ 13001ac5a404SSelvin Xavier struct creq_allocate_mrw_resp { 13011ac5a404SSelvin Xavier u8 type; 13021ac5a404SSelvin Xavier #define CREQ_ALLOCATE_MRW_RESP_TYPE_MASK 0x3fUL 13031ac5a404SSelvin Xavier #define CREQ_ALLOCATE_MRW_RESP_TYPE_SFT 0 13041ac5a404SSelvin Xavier #define CREQ_ALLOCATE_MRW_RESP_TYPE_QP_EVENT 0x38UL 1305a9a457f3SSelvin Xavier #define CREQ_ALLOCATE_MRW_RESP_TYPE_LAST CREQ_ALLOCATE_MRW_RESP_TYPE_QP_EVENT 13061ac5a404SSelvin Xavier u8 status; 13071ac5a404SSelvin Xavier __le16 cookie; 13081ac5a404SSelvin Xavier __le32 xid; 13091ac5a404SSelvin Xavier u8 v; 13101ac5a404SSelvin Xavier #define CREQ_ALLOCATE_MRW_RESP_V 0x1UL 13111ac5a404SSelvin Xavier u8 event; 13121ac5a404SSelvin Xavier #define CREQ_ALLOCATE_MRW_RESP_EVENT_ALLOCATE_MRW 0xdUL 1313a9a457f3SSelvin Xavier #define CREQ_ALLOCATE_MRW_RESP_EVENT_LAST CREQ_ALLOCATE_MRW_RESP_EVENT_ALLOCATE_MRW 1314a9a457f3SSelvin Xavier u8 reserved48[6]; 13151ac5a404SSelvin Xavier }; 13161ac5a404SSelvin Xavier 1317a9a457f3SSelvin Xavier /* cmdq_deallocate_key (size:192b/24B) */ 1318a9a457f3SSelvin Xavier struct cmdq_deallocate_key { 1319a9a457f3SSelvin Xavier u8 opcode; 1320a9a457f3SSelvin Xavier #define CMDQ_DEALLOCATE_KEY_OPCODE_DEALLOCATE_KEY 0xeUL 1321a9a457f3SSelvin Xavier #define CMDQ_DEALLOCATE_KEY_OPCODE_LAST CMDQ_DEALLOCATE_KEY_OPCODE_DEALLOCATE_KEY 1322a9a457f3SSelvin Xavier u8 cmd_size; 1323a9a457f3SSelvin Xavier __le16 flags; 1324a9a457f3SSelvin Xavier __le16 cookie; 1325a9a457f3SSelvin Xavier u8 resp_size; 1326a9a457f3SSelvin Xavier u8 reserved8; 1327a9a457f3SSelvin Xavier __le64 resp_addr; 1328a9a457f3SSelvin Xavier u8 mrw_flags; 1329a9a457f3SSelvin Xavier #define CMDQ_DEALLOCATE_KEY_MRW_FLAGS_MASK 0xfUL 1330a9a457f3SSelvin Xavier #define CMDQ_DEALLOCATE_KEY_MRW_FLAGS_SFT 0 1331a9a457f3SSelvin Xavier #define CMDQ_DEALLOCATE_KEY_MRW_FLAGS_MR 0x0UL 1332a9a457f3SSelvin Xavier #define CMDQ_DEALLOCATE_KEY_MRW_FLAGS_PMR 0x1UL 1333a9a457f3SSelvin Xavier #define CMDQ_DEALLOCATE_KEY_MRW_FLAGS_MW_TYPE1 0x2UL 1334a9a457f3SSelvin Xavier #define CMDQ_DEALLOCATE_KEY_MRW_FLAGS_MW_TYPE2A 0x3UL 1335a9a457f3SSelvin Xavier #define CMDQ_DEALLOCATE_KEY_MRW_FLAGS_MW_TYPE2B 0x4UL 1336a9a457f3SSelvin Xavier #define CMDQ_DEALLOCATE_KEY_MRW_FLAGS_LAST CMDQ_DEALLOCATE_KEY_MRW_FLAGS_MW_TYPE2B 1337a9a457f3SSelvin Xavier #define CMDQ_DEALLOCATE_KEY_UNUSED4_MASK 0xf0UL 1338a9a457f3SSelvin Xavier #define CMDQ_DEALLOCATE_KEY_UNUSED4_SFT 4 1339a9a457f3SSelvin Xavier u8 unused24[3]; 1340a9a457f3SSelvin Xavier __le32 key; 1341a9a457f3SSelvin Xavier }; 1342a9a457f3SSelvin Xavier 1343a9a457f3SSelvin Xavier /* creq_deallocate_key_resp (size:128b/16B) */ 13441ac5a404SSelvin Xavier struct creq_deallocate_key_resp { 13451ac5a404SSelvin Xavier u8 type; 13461ac5a404SSelvin Xavier #define CREQ_DEALLOCATE_KEY_RESP_TYPE_MASK 0x3fUL 13471ac5a404SSelvin Xavier #define CREQ_DEALLOCATE_KEY_RESP_TYPE_SFT 0 13481ac5a404SSelvin Xavier #define CREQ_DEALLOCATE_KEY_RESP_TYPE_QP_EVENT 0x38UL 1349a9a457f3SSelvin Xavier #define CREQ_DEALLOCATE_KEY_RESP_TYPE_LAST CREQ_DEALLOCATE_KEY_RESP_TYPE_QP_EVENT 13501ac5a404SSelvin Xavier u8 status; 13511ac5a404SSelvin Xavier __le16 cookie; 13521ac5a404SSelvin Xavier __le32 xid; 13531ac5a404SSelvin Xavier u8 v; 13541ac5a404SSelvin Xavier #define CREQ_DEALLOCATE_KEY_RESP_V 0x1UL 13551ac5a404SSelvin Xavier u8 event; 13561ac5a404SSelvin Xavier #define CREQ_DEALLOCATE_KEY_RESP_EVENT_DEALLOCATE_KEY 0xeUL 1357a9a457f3SSelvin Xavier #define CREQ_DEALLOCATE_KEY_RESP_EVENT_LAST CREQ_DEALLOCATE_KEY_RESP_EVENT_DEALLOCATE_KEY 13581ac5a404SSelvin Xavier __le16 reserved16; 13591ac5a404SSelvin Xavier __le32 bound_window_info; 13601ac5a404SSelvin Xavier }; 13611ac5a404SSelvin Xavier 1362a9a457f3SSelvin Xavier /* cmdq_register_mr (size:384b/48B) */ 1363a9a457f3SSelvin Xavier struct cmdq_register_mr { 1364a9a457f3SSelvin Xavier u8 opcode; 1365a9a457f3SSelvin Xavier #define CMDQ_REGISTER_MR_OPCODE_REGISTER_MR 0xfUL 1366a9a457f3SSelvin Xavier #define CMDQ_REGISTER_MR_OPCODE_LAST CMDQ_REGISTER_MR_OPCODE_REGISTER_MR 1367a9a457f3SSelvin Xavier u8 cmd_size; 1368a9a457f3SSelvin Xavier __le16 flags; 1369a9a457f3SSelvin Xavier #define CMDQ_REGISTER_MR_FLAGS_ALLOC_MR 0x1UL 1370a9a457f3SSelvin Xavier __le16 cookie; 1371a9a457f3SSelvin Xavier u8 resp_size; 1372a9a457f3SSelvin Xavier u8 reserved8; 1373a9a457f3SSelvin Xavier __le64 resp_addr; 1374a9a457f3SSelvin Xavier u8 log2_pg_size_lvl; 1375a9a457f3SSelvin Xavier #define CMDQ_REGISTER_MR_LVL_MASK 0x3UL 1376a9a457f3SSelvin Xavier #define CMDQ_REGISTER_MR_LVL_SFT 0 1377a9a457f3SSelvin Xavier #define CMDQ_REGISTER_MR_LVL_LVL_0 0x0UL 1378a9a457f3SSelvin Xavier #define CMDQ_REGISTER_MR_LVL_LVL_1 0x1UL 1379a9a457f3SSelvin Xavier #define CMDQ_REGISTER_MR_LVL_LVL_2 0x2UL 1380a9a457f3SSelvin Xavier #define CMDQ_REGISTER_MR_LVL_LAST CMDQ_REGISTER_MR_LVL_LVL_2 1381a9a457f3SSelvin Xavier #define CMDQ_REGISTER_MR_LOG2_PG_SIZE_MASK 0x7cUL 1382a9a457f3SSelvin Xavier #define CMDQ_REGISTER_MR_LOG2_PG_SIZE_SFT 2 1383a9a457f3SSelvin Xavier #define CMDQ_REGISTER_MR_LOG2_PG_SIZE_PG_4K (0xcUL << 2) 1384a9a457f3SSelvin Xavier #define CMDQ_REGISTER_MR_LOG2_PG_SIZE_PG_8K (0xdUL << 2) 1385a9a457f3SSelvin Xavier #define CMDQ_REGISTER_MR_LOG2_PG_SIZE_PG_64K (0x10UL << 2) 1386a9a457f3SSelvin Xavier #define CMDQ_REGISTER_MR_LOG2_PG_SIZE_PG_256K (0x12UL << 2) 1387a9a457f3SSelvin Xavier #define CMDQ_REGISTER_MR_LOG2_PG_SIZE_PG_1M (0x14UL << 2) 1388a9a457f3SSelvin Xavier #define CMDQ_REGISTER_MR_LOG2_PG_SIZE_PG_2M (0x15UL << 2) 1389a9a457f3SSelvin Xavier #define CMDQ_REGISTER_MR_LOG2_PG_SIZE_PG_4M (0x16UL << 2) 1390a9a457f3SSelvin Xavier #define CMDQ_REGISTER_MR_LOG2_PG_SIZE_PG_1G (0x1eUL << 2) 1391a9a457f3SSelvin Xavier #define CMDQ_REGISTER_MR_LOG2_PG_SIZE_LAST CMDQ_REGISTER_MR_LOG2_PG_SIZE_PG_1G 1392a9a457f3SSelvin Xavier #define CMDQ_REGISTER_MR_UNUSED1 0x80UL 1393a9a457f3SSelvin Xavier u8 access; 1394a9a457f3SSelvin Xavier #define CMDQ_REGISTER_MR_ACCESS_LOCAL_WRITE 0x1UL 1395a9a457f3SSelvin Xavier #define CMDQ_REGISTER_MR_ACCESS_REMOTE_READ 0x2UL 1396a9a457f3SSelvin Xavier #define CMDQ_REGISTER_MR_ACCESS_REMOTE_WRITE 0x4UL 1397a9a457f3SSelvin Xavier #define CMDQ_REGISTER_MR_ACCESS_REMOTE_ATOMIC 0x8UL 1398a9a457f3SSelvin Xavier #define CMDQ_REGISTER_MR_ACCESS_MW_BIND 0x10UL 1399a9a457f3SSelvin Xavier #define CMDQ_REGISTER_MR_ACCESS_ZERO_BASED 0x20UL 1400a9a457f3SSelvin Xavier __le16 log2_pbl_pg_size; 1401a9a457f3SSelvin Xavier #define CMDQ_REGISTER_MR_LOG2_PBL_PG_SIZE_MASK 0x1fUL 1402a9a457f3SSelvin Xavier #define CMDQ_REGISTER_MR_LOG2_PBL_PG_SIZE_SFT 0 1403a9a457f3SSelvin Xavier #define CMDQ_REGISTER_MR_LOG2_PBL_PG_SIZE_PG_4K 0xcUL 1404a9a457f3SSelvin Xavier #define CMDQ_REGISTER_MR_LOG2_PBL_PG_SIZE_PG_8K 0xdUL 1405a9a457f3SSelvin Xavier #define CMDQ_REGISTER_MR_LOG2_PBL_PG_SIZE_PG_64K 0x10UL 1406a9a457f3SSelvin Xavier #define CMDQ_REGISTER_MR_LOG2_PBL_PG_SIZE_PG_256K 0x12UL 1407a9a457f3SSelvin Xavier #define CMDQ_REGISTER_MR_LOG2_PBL_PG_SIZE_PG_1M 0x14UL 1408a9a457f3SSelvin Xavier #define CMDQ_REGISTER_MR_LOG2_PBL_PG_SIZE_PG_2M 0x15UL 1409a9a457f3SSelvin Xavier #define CMDQ_REGISTER_MR_LOG2_PBL_PG_SIZE_PG_4M 0x16UL 1410a9a457f3SSelvin Xavier #define CMDQ_REGISTER_MR_LOG2_PBL_PG_SIZE_PG_1G 0x1eUL 1411a9a457f3SSelvin Xavier #define CMDQ_REGISTER_MR_LOG2_PBL_PG_SIZE_LAST CMDQ_REGISTER_MR_LOG2_PBL_PG_SIZE_PG_1G 1412a9a457f3SSelvin Xavier #define CMDQ_REGISTER_MR_UNUSED11_MASK 0xffe0UL 1413a9a457f3SSelvin Xavier #define CMDQ_REGISTER_MR_UNUSED11_SFT 5 1414a9a457f3SSelvin Xavier __le32 key; 1415a9a457f3SSelvin Xavier __le64 pbl; 1416a9a457f3SSelvin Xavier __le64 va; 1417a9a457f3SSelvin Xavier __le64 mr_size; 1418a9a457f3SSelvin Xavier }; 1419a9a457f3SSelvin Xavier 1420a9a457f3SSelvin Xavier /* creq_register_mr_resp (size:128b/16B) */ 14211ac5a404SSelvin Xavier struct creq_register_mr_resp { 14221ac5a404SSelvin Xavier u8 type; 14231ac5a404SSelvin Xavier #define CREQ_REGISTER_MR_RESP_TYPE_MASK 0x3fUL 14241ac5a404SSelvin Xavier #define CREQ_REGISTER_MR_RESP_TYPE_SFT 0 14251ac5a404SSelvin Xavier #define CREQ_REGISTER_MR_RESP_TYPE_QP_EVENT 0x38UL 1426a9a457f3SSelvin Xavier #define CREQ_REGISTER_MR_RESP_TYPE_LAST CREQ_REGISTER_MR_RESP_TYPE_QP_EVENT 14271ac5a404SSelvin Xavier u8 status; 14281ac5a404SSelvin Xavier __le16 cookie; 14291ac5a404SSelvin Xavier __le32 xid; 14301ac5a404SSelvin Xavier u8 v; 14311ac5a404SSelvin Xavier #define CREQ_REGISTER_MR_RESP_V 0x1UL 14321ac5a404SSelvin Xavier u8 event; 14331ac5a404SSelvin Xavier #define CREQ_REGISTER_MR_RESP_EVENT_REGISTER_MR 0xfUL 1434a9a457f3SSelvin Xavier #define CREQ_REGISTER_MR_RESP_EVENT_LAST CREQ_REGISTER_MR_RESP_EVENT_REGISTER_MR 1435a9a457f3SSelvin Xavier u8 reserved48[6]; 14361ac5a404SSelvin Xavier }; 14371ac5a404SSelvin Xavier 1438a9a457f3SSelvin Xavier /* cmdq_deregister_mr (size:192b/24B) */ 1439a9a457f3SSelvin Xavier struct cmdq_deregister_mr { 1440a9a457f3SSelvin Xavier u8 opcode; 1441a9a457f3SSelvin Xavier #define CMDQ_DEREGISTER_MR_OPCODE_DEREGISTER_MR 0x10UL 1442a9a457f3SSelvin Xavier #define CMDQ_DEREGISTER_MR_OPCODE_LAST CMDQ_DEREGISTER_MR_OPCODE_DEREGISTER_MR 1443a9a457f3SSelvin Xavier u8 cmd_size; 1444a9a457f3SSelvin Xavier __le16 flags; 1445a9a457f3SSelvin Xavier __le16 cookie; 1446a9a457f3SSelvin Xavier u8 resp_size; 1447a9a457f3SSelvin Xavier u8 reserved8; 1448a9a457f3SSelvin Xavier __le64 resp_addr; 1449a9a457f3SSelvin Xavier __le32 lkey; 1450a9a457f3SSelvin Xavier __le32 unused_0; 1451a9a457f3SSelvin Xavier }; 1452a9a457f3SSelvin Xavier 1453a9a457f3SSelvin Xavier /* creq_deregister_mr_resp (size:128b/16B) */ 14541ac5a404SSelvin Xavier struct creq_deregister_mr_resp { 14551ac5a404SSelvin Xavier u8 type; 14561ac5a404SSelvin Xavier #define CREQ_DEREGISTER_MR_RESP_TYPE_MASK 0x3fUL 14571ac5a404SSelvin Xavier #define CREQ_DEREGISTER_MR_RESP_TYPE_SFT 0 14581ac5a404SSelvin Xavier #define CREQ_DEREGISTER_MR_RESP_TYPE_QP_EVENT 0x38UL 1459a9a457f3SSelvin Xavier #define CREQ_DEREGISTER_MR_RESP_TYPE_LAST CREQ_DEREGISTER_MR_RESP_TYPE_QP_EVENT 14601ac5a404SSelvin Xavier u8 status; 14611ac5a404SSelvin Xavier __le16 cookie; 14621ac5a404SSelvin Xavier __le32 xid; 14631ac5a404SSelvin Xavier u8 v; 14641ac5a404SSelvin Xavier #define CREQ_DEREGISTER_MR_RESP_V 0x1UL 14651ac5a404SSelvin Xavier u8 event; 14661ac5a404SSelvin Xavier #define CREQ_DEREGISTER_MR_RESP_EVENT_DEREGISTER_MR 0x10UL 1467a9a457f3SSelvin Xavier #define CREQ_DEREGISTER_MR_RESP_EVENT_LAST CREQ_DEREGISTER_MR_RESP_EVENT_DEREGISTER_MR 14681ac5a404SSelvin Xavier __le16 reserved16; 14691ac5a404SSelvin Xavier __le32 bound_windows; 14701ac5a404SSelvin Xavier }; 14711ac5a404SSelvin Xavier 1472a9a457f3SSelvin Xavier /* cmdq_add_gid (size:384b/48B) */ 1473a9a457f3SSelvin Xavier struct cmdq_add_gid { 1474a9a457f3SSelvin Xavier u8 opcode; 1475a9a457f3SSelvin Xavier #define CMDQ_ADD_GID_OPCODE_ADD_GID 0x11UL 1476a9a457f3SSelvin Xavier #define CMDQ_ADD_GID_OPCODE_LAST CMDQ_ADD_GID_OPCODE_ADD_GID 1477a9a457f3SSelvin Xavier u8 cmd_size; 1478a9a457f3SSelvin Xavier __le16 flags; 1479a9a457f3SSelvin Xavier __le16 cookie; 1480a9a457f3SSelvin Xavier u8 resp_size; 1481a9a457f3SSelvin Xavier u8 reserved8; 1482a9a457f3SSelvin Xavier __le64 resp_addr; 1483a9a457f3SSelvin Xavier __be32 gid[4]; 1484a9a457f3SSelvin Xavier __be16 src_mac[3]; 1485a9a457f3SSelvin Xavier __le16 vlan; 1486a9a457f3SSelvin Xavier #define CMDQ_ADD_GID_VLAN_VLAN_EN_TPID_VLAN_ID_MASK 0xffffUL 1487a9a457f3SSelvin Xavier #define CMDQ_ADD_GID_VLAN_VLAN_EN_TPID_VLAN_ID_SFT 0 1488a9a457f3SSelvin Xavier #define CMDQ_ADD_GID_VLAN_VLAN_ID_MASK 0xfffUL 1489a9a457f3SSelvin Xavier #define CMDQ_ADD_GID_VLAN_VLAN_ID_SFT 0 1490a9a457f3SSelvin Xavier #define CMDQ_ADD_GID_VLAN_TPID_MASK 0x7000UL 1491a9a457f3SSelvin Xavier #define CMDQ_ADD_GID_VLAN_TPID_SFT 12 1492a9a457f3SSelvin Xavier #define CMDQ_ADD_GID_VLAN_TPID_TPID_88A8 (0x0UL << 12) 1493a9a457f3SSelvin Xavier #define CMDQ_ADD_GID_VLAN_TPID_TPID_8100 (0x1UL << 12) 1494a9a457f3SSelvin Xavier #define CMDQ_ADD_GID_VLAN_TPID_TPID_9100 (0x2UL << 12) 1495a9a457f3SSelvin Xavier #define CMDQ_ADD_GID_VLAN_TPID_TPID_9200 (0x3UL << 12) 1496a9a457f3SSelvin Xavier #define CMDQ_ADD_GID_VLAN_TPID_TPID_9300 (0x4UL << 12) 1497a9a457f3SSelvin Xavier #define CMDQ_ADD_GID_VLAN_TPID_TPID_CFG1 (0x5UL << 12) 1498a9a457f3SSelvin Xavier #define CMDQ_ADD_GID_VLAN_TPID_TPID_CFG2 (0x6UL << 12) 1499a9a457f3SSelvin Xavier #define CMDQ_ADD_GID_VLAN_TPID_TPID_CFG3 (0x7UL << 12) 1500a9a457f3SSelvin Xavier #define CMDQ_ADD_GID_VLAN_TPID_LAST CMDQ_ADD_GID_VLAN_TPID_TPID_CFG3 1501a9a457f3SSelvin Xavier #define CMDQ_ADD_GID_VLAN_VLAN_EN 0x8000UL 1502a9a457f3SSelvin Xavier __le16 ipid; 1503a9a457f3SSelvin Xavier __le16 stats_ctx; 1504a9a457f3SSelvin Xavier #define CMDQ_ADD_GID_STATS_CTX_STATS_CTX_VALID_STATS_CTX_ID_MASK 0xffffUL 1505a9a457f3SSelvin Xavier #define CMDQ_ADD_GID_STATS_CTX_STATS_CTX_VALID_STATS_CTX_ID_SFT 0 1506a9a457f3SSelvin Xavier #define CMDQ_ADD_GID_STATS_CTX_STATS_CTX_ID_MASK 0x7fffUL 1507a9a457f3SSelvin Xavier #define CMDQ_ADD_GID_STATS_CTX_STATS_CTX_ID_SFT 0 1508a9a457f3SSelvin Xavier #define CMDQ_ADD_GID_STATS_CTX_STATS_CTX_VALID 0x8000UL 1509a9a457f3SSelvin Xavier __le32 unused_0; 1510a9a457f3SSelvin Xavier }; 1511a9a457f3SSelvin Xavier 1512a9a457f3SSelvin Xavier /* creq_add_gid_resp (size:128b/16B) */ 15131ac5a404SSelvin Xavier struct creq_add_gid_resp { 15141ac5a404SSelvin Xavier u8 type; 15151ac5a404SSelvin Xavier #define CREQ_ADD_GID_RESP_TYPE_MASK 0x3fUL 15161ac5a404SSelvin Xavier #define CREQ_ADD_GID_RESP_TYPE_SFT 0 15171ac5a404SSelvin Xavier #define CREQ_ADD_GID_RESP_TYPE_QP_EVENT 0x38UL 1518a9a457f3SSelvin Xavier #define CREQ_ADD_GID_RESP_TYPE_LAST CREQ_ADD_GID_RESP_TYPE_QP_EVENT 15191ac5a404SSelvin Xavier u8 status; 15201ac5a404SSelvin Xavier __le16 cookie; 15211ac5a404SSelvin Xavier __le32 xid; 15221ac5a404SSelvin Xavier u8 v; 15231ac5a404SSelvin Xavier #define CREQ_ADD_GID_RESP_V 0x1UL 15241ac5a404SSelvin Xavier u8 event; 15251ac5a404SSelvin Xavier #define CREQ_ADD_GID_RESP_EVENT_ADD_GID 0x11UL 1526a9a457f3SSelvin Xavier #define CREQ_ADD_GID_RESP_EVENT_LAST CREQ_ADD_GID_RESP_EVENT_ADD_GID 1527a9a457f3SSelvin Xavier u8 reserved48[6]; 15281ac5a404SSelvin Xavier }; 15291ac5a404SSelvin Xavier 1530a9a457f3SSelvin Xavier /* cmdq_delete_gid (size:192b/24B) */ 1531a9a457f3SSelvin Xavier struct cmdq_delete_gid { 1532a9a457f3SSelvin Xavier u8 opcode; 1533a9a457f3SSelvin Xavier #define CMDQ_DELETE_GID_OPCODE_DELETE_GID 0x12UL 1534a9a457f3SSelvin Xavier #define CMDQ_DELETE_GID_OPCODE_LAST CMDQ_DELETE_GID_OPCODE_DELETE_GID 1535a9a457f3SSelvin Xavier u8 cmd_size; 1536a9a457f3SSelvin Xavier __le16 flags; 1537a9a457f3SSelvin Xavier __le16 cookie; 1538a9a457f3SSelvin Xavier u8 resp_size; 1539a9a457f3SSelvin Xavier u8 reserved8; 1540a9a457f3SSelvin Xavier __le64 resp_addr; 1541a9a457f3SSelvin Xavier __le16 gid_index; 1542a9a457f3SSelvin Xavier u8 unused_0[6]; 1543a9a457f3SSelvin Xavier }; 1544a9a457f3SSelvin Xavier 1545a9a457f3SSelvin Xavier /* creq_delete_gid_resp (size:128b/16B) */ 15461ac5a404SSelvin Xavier struct creq_delete_gid_resp { 15471ac5a404SSelvin Xavier u8 type; 15481ac5a404SSelvin Xavier #define CREQ_DELETE_GID_RESP_TYPE_MASK 0x3fUL 15491ac5a404SSelvin Xavier #define CREQ_DELETE_GID_RESP_TYPE_SFT 0 15501ac5a404SSelvin Xavier #define CREQ_DELETE_GID_RESP_TYPE_QP_EVENT 0x38UL 1551a9a457f3SSelvin Xavier #define CREQ_DELETE_GID_RESP_TYPE_LAST CREQ_DELETE_GID_RESP_TYPE_QP_EVENT 15521ac5a404SSelvin Xavier u8 status; 15531ac5a404SSelvin Xavier __le16 cookie; 15541ac5a404SSelvin Xavier __le32 xid; 15551ac5a404SSelvin Xavier u8 v; 15561ac5a404SSelvin Xavier #define CREQ_DELETE_GID_RESP_V 0x1UL 15571ac5a404SSelvin Xavier u8 event; 15581ac5a404SSelvin Xavier #define CREQ_DELETE_GID_RESP_EVENT_DELETE_GID 0x12UL 1559a9a457f3SSelvin Xavier #define CREQ_DELETE_GID_RESP_EVENT_LAST CREQ_DELETE_GID_RESP_EVENT_DELETE_GID 1560a9a457f3SSelvin Xavier u8 reserved48[6]; 15611ac5a404SSelvin Xavier }; 15621ac5a404SSelvin Xavier 1563a9a457f3SSelvin Xavier /* cmdq_modify_gid (size:384b/48B) */ 1564a9a457f3SSelvin Xavier struct cmdq_modify_gid { 1565a9a457f3SSelvin Xavier u8 opcode; 1566a9a457f3SSelvin Xavier #define CMDQ_MODIFY_GID_OPCODE_MODIFY_GID 0x17UL 1567a9a457f3SSelvin Xavier #define CMDQ_MODIFY_GID_OPCODE_LAST CMDQ_MODIFY_GID_OPCODE_MODIFY_GID 1568a9a457f3SSelvin Xavier u8 cmd_size; 1569a9a457f3SSelvin Xavier __le16 flags; 1570a9a457f3SSelvin Xavier __le16 cookie; 1571a9a457f3SSelvin Xavier u8 resp_size; 1572a9a457f3SSelvin Xavier u8 reserved8; 1573a9a457f3SSelvin Xavier __le64 resp_addr; 1574a9a457f3SSelvin Xavier __be32 gid[4]; 1575a9a457f3SSelvin Xavier __be16 src_mac[3]; 1576a9a457f3SSelvin Xavier __le16 vlan; 1577a9a457f3SSelvin Xavier #define CMDQ_MODIFY_GID_VLAN_VLAN_ID_MASK 0xfffUL 1578a9a457f3SSelvin Xavier #define CMDQ_MODIFY_GID_VLAN_VLAN_ID_SFT 0 1579a9a457f3SSelvin Xavier #define CMDQ_MODIFY_GID_VLAN_TPID_MASK 0x7000UL 1580a9a457f3SSelvin Xavier #define CMDQ_MODIFY_GID_VLAN_TPID_SFT 12 1581a9a457f3SSelvin Xavier #define CMDQ_MODIFY_GID_VLAN_TPID_TPID_88A8 (0x0UL << 12) 1582a9a457f3SSelvin Xavier #define CMDQ_MODIFY_GID_VLAN_TPID_TPID_8100 (0x1UL << 12) 1583a9a457f3SSelvin Xavier #define CMDQ_MODIFY_GID_VLAN_TPID_TPID_9100 (0x2UL << 12) 1584a9a457f3SSelvin Xavier #define CMDQ_MODIFY_GID_VLAN_TPID_TPID_9200 (0x3UL << 12) 1585a9a457f3SSelvin Xavier #define CMDQ_MODIFY_GID_VLAN_TPID_TPID_9300 (0x4UL << 12) 1586a9a457f3SSelvin Xavier #define CMDQ_MODIFY_GID_VLAN_TPID_TPID_CFG1 (0x5UL << 12) 1587a9a457f3SSelvin Xavier #define CMDQ_MODIFY_GID_VLAN_TPID_TPID_CFG2 (0x6UL << 12) 1588a9a457f3SSelvin Xavier #define CMDQ_MODIFY_GID_VLAN_TPID_TPID_CFG3 (0x7UL << 12) 1589a9a457f3SSelvin Xavier #define CMDQ_MODIFY_GID_VLAN_TPID_LAST CMDQ_MODIFY_GID_VLAN_TPID_TPID_CFG3 1590a9a457f3SSelvin Xavier #define CMDQ_MODIFY_GID_VLAN_VLAN_EN 0x8000UL 1591a9a457f3SSelvin Xavier __le16 ipid; 1592a9a457f3SSelvin Xavier __le16 gid_index; 1593a9a457f3SSelvin Xavier __le16 stats_ctx; 1594a9a457f3SSelvin Xavier #define CMDQ_MODIFY_GID_STATS_CTX_STATS_CTX_ID_MASK 0x7fffUL 1595a9a457f3SSelvin Xavier #define CMDQ_MODIFY_GID_STATS_CTX_STATS_CTX_ID_SFT 0 1596a9a457f3SSelvin Xavier #define CMDQ_MODIFY_GID_STATS_CTX_STATS_CTX_VALID 0x8000UL 1597a9a457f3SSelvin Xavier __le16 unused_0; 1598a9a457f3SSelvin Xavier }; 1599a9a457f3SSelvin Xavier 1600a9a457f3SSelvin Xavier /* creq_modify_gid_resp (size:128b/16B) */ 16011ac5a404SSelvin Xavier struct creq_modify_gid_resp { 16021ac5a404SSelvin Xavier u8 type; 16031ac5a404SSelvin Xavier #define CREQ_MODIFY_GID_RESP_TYPE_MASK 0x3fUL 16041ac5a404SSelvin Xavier #define CREQ_MODIFY_GID_RESP_TYPE_SFT 0 16051ac5a404SSelvin Xavier #define CREQ_MODIFY_GID_RESP_TYPE_QP_EVENT 0x38UL 1606a9a457f3SSelvin Xavier #define CREQ_MODIFY_GID_RESP_TYPE_LAST CREQ_MODIFY_GID_RESP_TYPE_QP_EVENT 16071ac5a404SSelvin Xavier u8 status; 16081ac5a404SSelvin Xavier __le16 cookie; 16091ac5a404SSelvin Xavier __le32 xid; 16101ac5a404SSelvin Xavier u8 v; 16111ac5a404SSelvin Xavier #define CREQ_MODIFY_GID_RESP_V 0x1UL 16121ac5a404SSelvin Xavier u8 event; 16131ac5a404SSelvin Xavier #define CREQ_MODIFY_GID_RESP_EVENT_ADD_GID 0x11UL 1614a9a457f3SSelvin Xavier #define CREQ_MODIFY_GID_RESP_EVENT_LAST CREQ_MODIFY_GID_RESP_EVENT_ADD_GID 1615a9a457f3SSelvin Xavier u8 reserved48[6]; 16161ac5a404SSelvin Xavier }; 16171ac5a404SSelvin Xavier 1618a9a457f3SSelvin Xavier /* cmdq_query_gid (size:192b/24B) */ 1619a9a457f3SSelvin Xavier struct cmdq_query_gid { 1620a9a457f3SSelvin Xavier u8 opcode; 1621a9a457f3SSelvin Xavier #define CMDQ_QUERY_GID_OPCODE_QUERY_GID 0x18UL 1622a9a457f3SSelvin Xavier #define CMDQ_QUERY_GID_OPCODE_LAST CMDQ_QUERY_GID_OPCODE_QUERY_GID 1623a9a457f3SSelvin Xavier u8 cmd_size; 1624a9a457f3SSelvin Xavier __le16 flags; 1625a9a457f3SSelvin Xavier __le16 cookie; 1626a9a457f3SSelvin Xavier u8 resp_size; 1627a9a457f3SSelvin Xavier u8 reserved8; 1628a9a457f3SSelvin Xavier __le64 resp_addr; 1629a9a457f3SSelvin Xavier __le16 gid_index; 1630a9a457f3SSelvin Xavier u8 unused16[6]; 1631a9a457f3SSelvin Xavier }; 1632a9a457f3SSelvin Xavier 1633a9a457f3SSelvin Xavier /* creq_query_gid_resp (size:128b/16B) */ 16341ac5a404SSelvin Xavier struct creq_query_gid_resp { 16351ac5a404SSelvin Xavier u8 type; 16361ac5a404SSelvin Xavier #define CREQ_QUERY_GID_RESP_TYPE_MASK 0x3fUL 16371ac5a404SSelvin Xavier #define CREQ_QUERY_GID_RESP_TYPE_SFT 0 16381ac5a404SSelvin Xavier #define CREQ_QUERY_GID_RESP_TYPE_QP_EVENT 0x38UL 1639a9a457f3SSelvin Xavier #define CREQ_QUERY_GID_RESP_TYPE_LAST CREQ_QUERY_GID_RESP_TYPE_QP_EVENT 16401ac5a404SSelvin Xavier u8 status; 16411ac5a404SSelvin Xavier __le16 cookie; 16421ac5a404SSelvin Xavier __le32 size; 16431ac5a404SSelvin Xavier u8 v; 16441ac5a404SSelvin Xavier #define CREQ_QUERY_GID_RESP_V 0x1UL 16451ac5a404SSelvin Xavier u8 event; 16461ac5a404SSelvin Xavier #define CREQ_QUERY_GID_RESP_EVENT_QUERY_GID 0x18UL 1647a9a457f3SSelvin Xavier #define CREQ_QUERY_GID_RESP_EVENT_LAST CREQ_QUERY_GID_RESP_EVENT_QUERY_GID 1648a9a457f3SSelvin Xavier u8 reserved48[6]; 16491ac5a404SSelvin Xavier }; 16501ac5a404SSelvin Xavier 1651a9a457f3SSelvin Xavier /* creq_query_gid_resp_sb (size:320b/40B) */ 16521ac5a404SSelvin Xavier struct creq_query_gid_resp_sb { 16531ac5a404SSelvin Xavier u8 opcode; 16541ac5a404SSelvin Xavier #define CREQ_QUERY_GID_RESP_SB_OPCODE_QUERY_GID 0x18UL 1655a9a457f3SSelvin Xavier #define CREQ_QUERY_GID_RESP_SB_OPCODE_LAST CREQ_QUERY_GID_RESP_SB_OPCODE_QUERY_GID 16561ac5a404SSelvin Xavier u8 status; 16571ac5a404SSelvin Xavier __le16 cookie; 16581ac5a404SSelvin Xavier __le16 flags; 16591ac5a404SSelvin Xavier u8 resp_size; 16601ac5a404SSelvin Xavier u8 reserved8; 16611ac5a404SSelvin Xavier __le32 gid[4]; 16621ac5a404SSelvin Xavier __le16 src_mac[3]; 16631ac5a404SSelvin Xavier __le16 vlan; 1664a9a457f3SSelvin Xavier #define CREQ_QUERY_GID_RESP_SB_VLAN_VLAN_EN_TPID_VLAN_ID_MASK 0xffffUL 1665a9a457f3SSelvin Xavier #define CREQ_QUERY_GID_RESP_SB_VLAN_VLAN_EN_TPID_VLAN_ID_SFT 0 16661ac5a404SSelvin Xavier #define CREQ_QUERY_GID_RESP_SB_VLAN_VLAN_ID_MASK 0xfffUL 16671ac5a404SSelvin Xavier #define CREQ_QUERY_GID_RESP_SB_VLAN_VLAN_ID_SFT 0 16681ac5a404SSelvin Xavier #define CREQ_QUERY_GID_RESP_SB_VLAN_TPID_MASK 0x7000UL 16691ac5a404SSelvin Xavier #define CREQ_QUERY_GID_RESP_SB_VLAN_TPID_SFT 12 16701ac5a404SSelvin Xavier #define CREQ_QUERY_GID_RESP_SB_VLAN_TPID_TPID_88A8 (0x0UL << 12) 16711ac5a404SSelvin Xavier #define CREQ_QUERY_GID_RESP_SB_VLAN_TPID_TPID_8100 (0x1UL << 12) 16721ac5a404SSelvin Xavier #define CREQ_QUERY_GID_RESP_SB_VLAN_TPID_TPID_9100 (0x2UL << 12) 16731ac5a404SSelvin Xavier #define CREQ_QUERY_GID_RESP_SB_VLAN_TPID_TPID_9200 (0x3UL << 12) 16741ac5a404SSelvin Xavier #define CREQ_QUERY_GID_RESP_SB_VLAN_TPID_TPID_9300 (0x4UL << 12) 16751ac5a404SSelvin Xavier #define CREQ_QUERY_GID_RESP_SB_VLAN_TPID_TPID_CFG1 (0x5UL << 12) 16761ac5a404SSelvin Xavier #define CREQ_QUERY_GID_RESP_SB_VLAN_TPID_TPID_CFG2 (0x6UL << 12) 16771ac5a404SSelvin Xavier #define CREQ_QUERY_GID_RESP_SB_VLAN_TPID_TPID_CFG3 (0x7UL << 12) 1678a9a457f3SSelvin Xavier #define CREQ_QUERY_GID_RESP_SB_VLAN_TPID_LAST CREQ_QUERY_GID_RESP_SB_VLAN_TPID_TPID_CFG3 16791ac5a404SSelvin Xavier #define CREQ_QUERY_GID_RESP_SB_VLAN_VLAN_EN 0x8000UL 16801ac5a404SSelvin Xavier __le16 ipid; 16811ac5a404SSelvin Xavier __le16 gid_index; 16821ac5a404SSelvin Xavier __le32 unused_0; 16831ac5a404SSelvin Xavier }; 16841ac5a404SSelvin Xavier 1685a9a457f3SSelvin Xavier /* cmdq_create_qp1 (size:640b/80B) */ 1686a9a457f3SSelvin Xavier struct cmdq_create_qp1 { 1687a9a457f3SSelvin Xavier u8 opcode; 1688a9a457f3SSelvin Xavier #define CMDQ_CREATE_QP1_OPCODE_CREATE_QP1 0x13UL 1689a9a457f3SSelvin Xavier #define CMDQ_CREATE_QP1_OPCODE_LAST CMDQ_CREATE_QP1_OPCODE_CREATE_QP1 1690a9a457f3SSelvin Xavier u8 cmd_size; 1691a9a457f3SSelvin Xavier __le16 flags; 1692a9a457f3SSelvin Xavier __le16 cookie; 1693a9a457f3SSelvin Xavier u8 resp_size; 1694a9a457f3SSelvin Xavier u8 reserved8; 1695a9a457f3SSelvin Xavier __le64 resp_addr; 1696a9a457f3SSelvin Xavier __le64 qp_handle; 1697a9a457f3SSelvin Xavier __le32 qp_flags; 1698a9a457f3SSelvin Xavier #define CMDQ_CREATE_QP1_QP_FLAGS_SRQ_USED 0x1UL 1699a9a457f3SSelvin Xavier #define CMDQ_CREATE_QP1_QP_FLAGS_FORCE_COMPLETION 0x2UL 1700a9a457f3SSelvin Xavier #define CMDQ_CREATE_QP1_QP_FLAGS_RESERVED_LKEY_ENABLE 0x4UL 1701a9a457f3SSelvin Xavier #define CMDQ_CREATE_QP1_QP_FLAGS_LAST CMDQ_CREATE_QP1_QP_FLAGS_RESERVED_LKEY_ENABLE 1702a9a457f3SSelvin Xavier u8 type; 1703a9a457f3SSelvin Xavier #define CMDQ_CREATE_QP1_TYPE_GSI 0x1UL 1704a9a457f3SSelvin Xavier #define CMDQ_CREATE_QP1_TYPE_LAST CMDQ_CREATE_QP1_TYPE_GSI 1705a9a457f3SSelvin Xavier u8 sq_pg_size_sq_lvl; 1706a9a457f3SSelvin Xavier #define CMDQ_CREATE_QP1_SQ_LVL_MASK 0xfUL 1707a9a457f3SSelvin Xavier #define CMDQ_CREATE_QP1_SQ_LVL_SFT 0 1708a9a457f3SSelvin Xavier #define CMDQ_CREATE_QP1_SQ_LVL_LVL_0 0x0UL 1709a9a457f3SSelvin Xavier #define CMDQ_CREATE_QP1_SQ_LVL_LVL_1 0x1UL 1710a9a457f3SSelvin Xavier #define CMDQ_CREATE_QP1_SQ_LVL_LVL_2 0x2UL 1711a9a457f3SSelvin Xavier #define CMDQ_CREATE_QP1_SQ_LVL_LAST CMDQ_CREATE_QP1_SQ_LVL_LVL_2 1712a9a457f3SSelvin Xavier #define CMDQ_CREATE_QP1_SQ_PG_SIZE_MASK 0xf0UL 1713a9a457f3SSelvin Xavier #define CMDQ_CREATE_QP1_SQ_PG_SIZE_SFT 4 1714a9a457f3SSelvin Xavier #define CMDQ_CREATE_QP1_SQ_PG_SIZE_PG_4K (0x0UL << 4) 1715a9a457f3SSelvin Xavier #define CMDQ_CREATE_QP1_SQ_PG_SIZE_PG_8K (0x1UL << 4) 1716a9a457f3SSelvin Xavier #define CMDQ_CREATE_QP1_SQ_PG_SIZE_PG_64K (0x2UL << 4) 1717a9a457f3SSelvin Xavier #define CMDQ_CREATE_QP1_SQ_PG_SIZE_PG_2M (0x3UL << 4) 1718a9a457f3SSelvin Xavier #define CMDQ_CREATE_QP1_SQ_PG_SIZE_PG_8M (0x4UL << 4) 1719a9a457f3SSelvin Xavier #define CMDQ_CREATE_QP1_SQ_PG_SIZE_PG_1G (0x5UL << 4) 1720a9a457f3SSelvin Xavier #define CMDQ_CREATE_QP1_SQ_PG_SIZE_LAST CMDQ_CREATE_QP1_SQ_PG_SIZE_PG_1G 1721a9a457f3SSelvin Xavier u8 rq_pg_size_rq_lvl; 1722a9a457f3SSelvin Xavier #define CMDQ_CREATE_QP1_RQ_LVL_MASK 0xfUL 1723a9a457f3SSelvin Xavier #define CMDQ_CREATE_QP1_RQ_LVL_SFT 0 1724a9a457f3SSelvin Xavier #define CMDQ_CREATE_QP1_RQ_LVL_LVL_0 0x0UL 1725a9a457f3SSelvin Xavier #define CMDQ_CREATE_QP1_RQ_LVL_LVL_1 0x1UL 1726a9a457f3SSelvin Xavier #define CMDQ_CREATE_QP1_RQ_LVL_LVL_2 0x2UL 1727a9a457f3SSelvin Xavier #define CMDQ_CREATE_QP1_RQ_LVL_LAST CMDQ_CREATE_QP1_RQ_LVL_LVL_2 1728a9a457f3SSelvin Xavier #define CMDQ_CREATE_QP1_RQ_PG_SIZE_MASK 0xf0UL 1729a9a457f3SSelvin Xavier #define CMDQ_CREATE_QP1_RQ_PG_SIZE_SFT 4 1730a9a457f3SSelvin Xavier #define CMDQ_CREATE_QP1_RQ_PG_SIZE_PG_4K (0x0UL << 4) 1731a9a457f3SSelvin Xavier #define CMDQ_CREATE_QP1_RQ_PG_SIZE_PG_8K (0x1UL << 4) 1732a9a457f3SSelvin Xavier #define CMDQ_CREATE_QP1_RQ_PG_SIZE_PG_64K (0x2UL << 4) 1733a9a457f3SSelvin Xavier #define CMDQ_CREATE_QP1_RQ_PG_SIZE_PG_2M (0x3UL << 4) 1734a9a457f3SSelvin Xavier #define CMDQ_CREATE_QP1_RQ_PG_SIZE_PG_8M (0x4UL << 4) 1735a9a457f3SSelvin Xavier #define CMDQ_CREATE_QP1_RQ_PG_SIZE_PG_1G (0x5UL << 4) 1736a9a457f3SSelvin Xavier #define CMDQ_CREATE_QP1_RQ_PG_SIZE_LAST CMDQ_CREATE_QP1_RQ_PG_SIZE_PG_1G 1737a9a457f3SSelvin Xavier u8 unused_0; 1738a9a457f3SSelvin Xavier __le32 dpi; 1739a9a457f3SSelvin Xavier __le32 sq_size; 1740a9a457f3SSelvin Xavier __le32 rq_size; 1741a9a457f3SSelvin Xavier __le16 sq_fwo_sq_sge; 1742a9a457f3SSelvin Xavier #define CMDQ_CREATE_QP1_SQ_SGE_MASK 0xfUL 1743a9a457f3SSelvin Xavier #define CMDQ_CREATE_QP1_SQ_SGE_SFT 0 1744a9a457f3SSelvin Xavier #define CMDQ_CREATE_QP1_SQ_FWO_MASK 0xfff0UL 1745a9a457f3SSelvin Xavier #define CMDQ_CREATE_QP1_SQ_FWO_SFT 4 1746a9a457f3SSelvin Xavier __le16 rq_fwo_rq_sge; 1747a9a457f3SSelvin Xavier #define CMDQ_CREATE_QP1_RQ_SGE_MASK 0xfUL 1748a9a457f3SSelvin Xavier #define CMDQ_CREATE_QP1_RQ_SGE_SFT 0 1749a9a457f3SSelvin Xavier #define CMDQ_CREATE_QP1_RQ_FWO_MASK 0xfff0UL 1750a9a457f3SSelvin Xavier #define CMDQ_CREATE_QP1_RQ_FWO_SFT 4 1751a9a457f3SSelvin Xavier __le32 scq_cid; 1752a9a457f3SSelvin Xavier __le32 rcq_cid; 1753a9a457f3SSelvin Xavier __le32 srq_cid; 1754a9a457f3SSelvin Xavier __le32 pd_id; 1755a9a457f3SSelvin Xavier __le64 sq_pbl; 1756a9a457f3SSelvin Xavier __le64 rq_pbl; 1757a9a457f3SSelvin Xavier }; 1758a9a457f3SSelvin Xavier 1759a9a457f3SSelvin Xavier /* creq_create_qp1_resp (size:128b/16B) */ 17601ac5a404SSelvin Xavier struct creq_create_qp1_resp { 17611ac5a404SSelvin Xavier u8 type; 17621ac5a404SSelvin Xavier #define CREQ_CREATE_QP1_RESP_TYPE_MASK 0x3fUL 17631ac5a404SSelvin Xavier #define CREQ_CREATE_QP1_RESP_TYPE_SFT 0 17641ac5a404SSelvin Xavier #define CREQ_CREATE_QP1_RESP_TYPE_QP_EVENT 0x38UL 1765a9a457f3SSelvin Xavier #define CREQ_CREATE_QP1_RESP_TYPE_LAST CREQ_CREATE_QP1_RESP_TYPE_QP_EVENT 17661ac5a404SSelvin Xavier u8 status; 17671ac5a404SSelvin Xavier __le16 cookie; 17681ac5a404SSelvin Xavier __le32 xid; 17691ac5a404SSelvin Xavier u8 v; 17701ac5a404SSelvin Xavier #define CREQ_CREATE_QP1_RESP_V 0x1UL 17711ac5a404SSelvin Xavier u8 event; 17721ac5a404SSelvin Xavier #define CREQ_CREATE_QP1_RESP_EVENT_CREATE_QP1 0x13UL 1773a9a457f3SSelvin Xavier #define CREQ_CREATE_QP1_RESP_EVENT_LAST CREQ_CREATE_QP1_RESP_EVENT_CREATE_QP1 1774a9a457f3SSelvin Xavier u8 reserved48[6]; 17751ac5a404SSelvin Xavier }; 17761ac5a404SSelvin Xavier 1777a9a457f3SSelvin Xavier /* cmdq_destroy_qp1 (size:192b/24B) */ 1778a9a457f3SSelvin Xavier struct cmdq_destroy_qp1 { 1779a9a457f3SSelvin Xavier u8 opcode; 1780a9a457f3SSelvin Xavier #define CMDQ_DESTROY_QP1_OPCODE_DESTROY_QP1 0x14UL 1781a9a457f3SSelvin Xavier #define CMDQ_DESTROY_QP1_OPCODE_LAST CMDQ_DESTROY_QP1_OPCODE_DESTROY_QP1 1782a9a457f3SSelvin Xavier u8 cmd_size; 1783a9a457f3SSelvin Xavier __le16 flags; 1784a9a457f3SSelvin Xavier __le16 cookie; 1785a9a457f3SSelvin Xavier u8 resp_size; 1786a9a457f3SSelvin Xavier u8 reserved8; 1787a9a457f3SSelvin Xavier __le64 resp_addr; 1788a9a457f3SSelvin Xavier __le32 qp1_cid; 1789a9a457f3SSelvin Xavier __le32 unused_0; 1790a9a457f3SSelvin Xavier }; 1791a9a457f3SSelvin Xavier 1792a9a457f3SSelvin Xavier /* creq_destroy_qp1_resp (size:128b/16B) */ 17931ac5a404SSelvin Xavier struct creq_destroy_qp1_resp { 17941ac5a404SSelvin Xavier u8 type; 17951ac5a404SSelvin Xavier #define CREQ_DESTROY_QP1_RESP_TYPE_MASK 0x3fUL 17961ac5a404SSelvin Xavier #define CREQ_DESTROY_QP1_RESP_TYPE_SFT 0 17971ac5a404SSelvin Xavier #define CREQ_DESTROY_QP1_RESP_TYPE_QP_EVENT 0x38UL 1798a9a457f3SSelvin Xavier #define CREQ_DESTROY_QP1_RESP_TYPE_LAST CREQ_DESTROY_QP1_RESP_TYPE_QP_EVENT 17991ac5a404SSelvin Xavier u8 status; 18001ac5a404SSelvin Xavier __le16 cookie; 18011ac5a404SSelvin Xavier __le32 xid; 18021ac5a404SSelvin Xavier u8 v; 18031ac5a404SSelvin Xavier #define CREQ_DESTROY_QP1_RESP_V 0x1UL 18041ac5a404SSelvin Xavier u8 event; 18051ac5a404SSelvin Xavier #define CREQ_DESTROY_QP1_RESP_EVENT_DESTROY_QP1 0x14UL 1806a9a457f3SSelvin Xavier #define CREQ_DESTROY_QP1_RESP_EVENT_LAST CREQ_DESTROY_QP1_RESP_EVENT_DESTROY_QP1 1807a9a457f3SSelvin Xavier u8 reserved48[6]; 18081ac5a404SSelvin Xavier }; 18091ac5a404SSelvin Xavier 1810a9a457f3SSelvin Xavier /* cmdq_create_ah (size:512b/64B) */ 1811a9a457f3SSelvin Xavier struct cmdq_create_ah { 1812a9a457f3SSelvin Xavier u8 opcode; 1813a9a457f3SSelvin Xavier #define CMDQ_CREATE_AH_OPCODE_CREATE_AH 0x15UL 1814a9a457f3SSelvin Xavier #define CMDQ_CREATE_AH_OPCODE_LAST CMDQ_CREATE_AH_OPCODE_CREATE_AH 1815a9a457f3SSelvin Xavier u8 cmd_size; 1816a9a457f3SSelvin Xavier __le16 flags; 1817a9a457f3SSelvin Xavier __le16 cookie; 1818a9a457f3SSelvin Xavier u8 resp_size; 1819a9a457f3SSelvin Xavier u8 reserved8; 1820a9a457f3SSelvin Xavier __le64 resp_addr; 1821a9a457f3SSelvin Xavier __le64 ah_handle; 1822a9a457f3SSelvin Xavier __le32 dgid[4]; 1823a9a457f3SSelvin Xavier u8 type; 1824a9a457f3SSelvin Xavier #define CMDQ_CREATE_AH_TYPE_V1 0x0UL 1825a9a457f3SSelvin Xavier #define CMDQ_CREATE_AH_TYPE_V2IPV4 0x2UL 1826a9a457f3SSelvin Xavier #define CMDQ_CREATE_AH_TYPE_V2IPV6 0x3UL 1827a9a457f3SSelvin Xavier #define CMDQ_CREATE_AH_TYPE_LAST CMDQ_CREATE_AH_TYPE_V2IPV6 1828a9a457f3SSelvin Xavier u8 hop_limit; 1829a9a457f3SSelvin Xavier __le16 sgid_index; 1830a9a457f3SSelvin Xavier __le32 dest_vlan_id_flow_label; 1831a9a457f3SSelvin Xavier #define CMDQ_CREATE_AH_FLOW_LABEL_MASK 0xfffffUL 1832a9a457f3SSelvin Xavier #define CMDQ_CREATE_AH_FLOW_LABEL_SFT 0 1833a9a457f3SSelvin Xavier #define CMDQ_CREATE_AH_DEST_VLAN_ID_MASK 0xfff00000UL 1834a9a457f3SSelvin Xavier #define CMDQ_CREATE_AH_DEST_VLAN_ID_SFT 20 1835a9a457f3SSelvin Xavier __le32 pd_id; 1836a9a457f3SSelvin Xavier __le32 unused_0; 1837a9a457f3SSelvin Xavier __le16 dest_mac[3]; 1838a9a457f3SSelvin Xavier u8 traffic_class; 1839a9a457f3SSelvin Xavier u8 enable_cc; 1840a9a457f3SSelvin Xavier #define CMDQ_CREATE_AH_ENABLE_CC 0x1UL 1841a9a457f3SSelvin Xavier }; 1842a9a457f3SSelvin Xavier 1843a9a457f3SSelvin Xavier /* creq_create_ah_resp (size:128b/16B) */ 18441ac5a404SSelvin Xavier struct creq_create_ah_resp { 18451ac5a404SSelvin Xavier u8 type; 18461ac5a404SSelvin Xavier #define CREQ_CREATE_AH_RESP_TYPE_MASK 0x3fUL 18471ac5a404SSelvin Xavier #define CREQ_CREATE_AH_RESP_TYPE_SFT 0 18481ac5a404SSelvin Xavier #define CREQ_CREATE_AH_RESP_TYPE_QP_EVENT 0x38UL 1849a9a457f3SSelvin Xavier #define CREQ_CREATE_AH_RESP_TYPE_LAST CREQ_CREATE_AH_RESP_TYPE_QP_EVENT 18501ac5a404SSelvin Xavier u8 status; 18511ac5a404SSelvin Xavier __le16 cookie; 18521ac5a404SSelvin Xavier __le32 xid; 18531ac5a404SSelvin Xavier u8 v; 18541ac5a404SSelvin Xavier #define CREQ_CREATE_AH_RESP_V 0x1UL 18551ac5a404SSelvin Xavier u8 event; 18561ac5a404SSelvin Xavier #define CREQ_CREATE_AH_RESP_EVENT_CREATE_AH 0x15UL 1857a9a457f3SSelvin Xavier #define CREQ_CREATE_AH_RESP_EVENT_LAST CREQ_CREATE_AH_RESP_EVENT_CREATE_AH 1858a9a457f3SSelvin Xavier u8 reserved48[6]; 18591ac5a404SSelvin Xavier }; 18601ac5a404SSelvin Xavier 1861a9a457f3SSelvin Xavier /* cmdq_destroy_ah (size:192b/24B) */ 1862a9a457f3SSelvin Xavier struct cmdq_destroy_ah { 1863a9a457f3SSelvin Xavier u8 opcode; 1864a9a457f3SSelvin Xavier #define CMDQ_DESTROY_AH_OPCODE_DESTROY_AH 0x16UL 1865a9a457f3SSelvin Xavier #define CMDQ_DESTROY_AH_OPCODE_LAST CMDQ_DESTROY_AH_OPCODE_DESTROY_AH 1866a9a457f3SSelvin Xavier u8 cmd_size; 1867a9a457f3SSelvin Xavier __le16 flags; 1868a9a457f3SSelvin Xavier __le16 cookie; 1869a9a457f3SSelvin Xavier u8 resp_size; 1870a9a457f3SSelvin Xavier u8 reserved8; 1871a9a457f3SSelvin Xavier __le64 resp_addr; 1872a9a457f3SSelvin Xavier __le32 ah_cid; 1873a9a457f3SSelvin Xavier __le32 unused_0; 1874a9a457f3SSelvin Xavier }; 1875a9a457f3SSelvin Xavier 1876a9a457f3SSelvin Xavier /* creq_destroy_ah_resp (size:128b/16B) */ 18771ac5a404SSelvin Xavier struct creq_destroy_ah_resp { 18781ac5a404SSelvin Xavier u8 type; 18791ac5a404SSelvin Xavier #define CREQ_DESTROY_AH_RESP_TYPE_MASK 0x3fUL 18801ac5a404SSelvin Xavier #define CREQ_DESTROY_AH_RESP_TYPE_SFT 0 18811ac5a404SSelvin Xavier #define CREQ_DESTROY_AH_RESP_TYPE_QP_EVENT 0x38UL 1882a9a457f3SSelvin Xavier #define CREQ_DESTROY_AH_RESP_TYPE_LAST CREQ_DESTROY_AH_RESP_TYPE_QP_EVENT 18831ac5a404SSelvin Xavier u8 status; 18841ac5a404SSelvin Xavier __le16 cookie; 18851ac5a404SSelvin Xavier __le32 xid; 18861ac5a404SSelvin Xavier u8 v; 18871ac5a404SSelvin Xavier #define CREQ_DESTROY_AH_RESP_V 0x1UL 18881ac5a404SSelvin Xavier u8 event; 18891ac5a404SSelvin Xavier #define CREQ_DESTROY_AH_RESP_EVENT_DESTROY_AH 0x16UL 1890a9a457f3SSelvin Xavier #define CREQ_DESTROY_AH_RESP_EVENT_LAST CREQ_DESTROY_AH_RESP_EVENT_DESTROY_AH 1891a9a457f3SSelvin Xavier u8 reserved48[6]; 18921ac5a404SSelvin Xavier }; 18931ac5a404SSelvin Xavier 1894a9a457f3SSelvin Xavier /* cmdq_query_roce_stats (size:192b/24B) */ 1895a9a457f3SSelvin Xavier struct cmdq_query_roce_stats { 18961ac5a404SSelvin Xavier u8 opcode; 1897a9a457f3SSelvin Xavier #define CMDQ_QUERY_ROCE_STATS_OPCODE_QUERY_ROCE_STATS 0x8eUL 1898a9a457f3SSelvin Xavier #define CMDQ_QUERY_ROCE_STATS_OPCODE_LAST CMDQ_QUERY_ROCE_STATS_OPCODE_QUERY_ROCE_STATS 1899a9a457f3SSelvin Xavier u8 cmd_size; 19001ac5a404SSelvin Xavier __le16 flags; 1901a9a457f3SSelvin Xavier #define CMDQ_QUERY_ROCE_STATS_FLAGS_COLLECTION_ID 0x1UL 1902a9a457f3SSelvin Xavier #define CMDQ_QUERY_ROCE_STATS_FLAGS_FUNCTION_ID 0x2UL 1903a9a457f3SSelvin Xavier __le16 cookie; 19041ac5a404SSelvin Xavier u8 resp_size; 1905a9a457f3SSelvin Xavier u8 collection_id; 1906a9a457f3SSelvin Xavier __le64 resp_addr; 1907a9a457f3SSelvin Xavier __le32 function_id; 1908a9a457f3SSelvin Xavier #define CMDQ_QUERY_ROCE_STATS_PF_NUM_MASK 0xffUL 1909a9a457f3SSelvin Xavier #define CMDQ_QUERY_ROCE_STATS_PF_NUM_SFT 0 1910a9a457f3SSelvin Xavier #define CMDQ_QUERY_ROCE_STATS_VF_NUM_MASK 0xffff00UL 1911a9a457f3SSelvin Xavier #define CMDQ_QUERY_ROCE_STATS_VF_NUM_SFT 8 1912a9a457f3SSelvin Xavier #define CMDQ_QUERY_ROCE_STATS_VF_VALID 0x1000000UL 19131ac5a404SSelvin Xavier __le32 reserved32; 19141ac5a404SSelvin Xavier }; 19151ac5a404SSelvin Xavier 191689f81008SSelvin Xavier /* creq_query_roce_stats_resp (size:128b/16B) */ 191789f81008SSelvin Xavier struct creq_query_roce_stats_resp { 191889f81008SSelvin Xavier u8 type; 191989f81008SSelvin Xavier #define CREQ_QUERY_ROCE_STATS_RESP_TYPE_MASK 0x3fUL 192089f81008SSelvin Xavier #define CREQ_QUERY_ROCE_STATS_RESP_TYPE_SFT 0 192189f81008SSelvin Xavier #define CREQ_QUERY_ROCE_STATS_RESP_TYPE_QP_EVENT 0x38UL 1922a9a457f3SSelvin Xavier #define CREQ_QUERY_ROCE_STATS_RESP_TYPE_LAST CREQ_QUERY_ROCE_STATS_RESP_TYPE_QP_EVENT 192389f81008SSelvin Xavier u8 status; 192489f81008SSelvin Xavier __le16 cookie; 192589f81008SSelvin Xavier __le32 size; 192689f81008SSelvin Xavier u8 v; 192789f81008SSelvin Xavier #define CREQ_QUERY_ROCE_STATS_RESP_V 0x1UL 192889f81008SSelvin Xavier u8 event; 192989f81008SSelvin Xavier #define CREQ_QUERY_ROCE_STATS_RESP_EVENT_QUERY_ROCE_STATS 0x8eUL 193089f81008SSelvin Xavier #define CREQ_QUERY_ROCE_STATS_RESP_EVENT_LAST \ 193189f81008SSelvin Xavier CREQ_QUERY_ROCE_STATS_RESP_EVENT_QUERY_ROCE_STATS 193289f81008SSelvin Xavier u8 reserved48[6]; 193389f81008SSelvin Xavier }; 193489f81008SSelvin Xavier 1935a9a457f3SSelvin Xavier /* creq_query_roce_stats_resp_sb (size:2944b/368B) */ 193689f81008SSelvin Xavier struct creq_query_roce_stats_resp_sb { 193789f81008SSelvin Xavier u8 opcode; 193889f81008SSelvin Xavier #define CREQ_QUERY_ROCE_STATS_RESP_SB_OPCODE_QUERY_ROCE_STATS 0x8eUL 193989f81008SSelvin Xavier #define CREQ_QUERY_ROCE_STATS_RESP_SB_OPCODE_LAST \ 194089f81008SSelvin Xavier CREQ_QUERY_ROCE_STATS_RESP_SB_OPCODE_QUERY_ROCE_STATS 194189f81008SSelvin Xavier u8 status; 194289f81008SSelvin Xavier __le16 cookie; 194389f81008SSelvin Xavier __le16 flags; 194489f81008SSelvin Xavier u8 resp_size; 194589f81008SSelvin Xavier u8 rsvd; 194689f81008SSelvin Xavier __le32 num_counters; 194789f81008SSelvin Xavier __le32 rsvd1; 194889f81008SSelvin Xavier __le64 to_retransmits; 194989f81008SSelvin Xavier __le64 seq_err_naks_rcvd; 195089f81008SSelvin Xavier __le64 max_retry_exceeded; 195189f81008SSelvin Xavier __le64 rnr_naks_rcvd; 195289f81008SSelvin Xavier __le64 missing_resp; 195389f81008SSelvin Xavier __le64 unrecoverable_err; 195489f81008SSelvin Xavier __le64 bad_resp_err; 195589f81008SSelvin Xavier __le64 local_qp_op_err; 195689f81008SSelvin Xavier __le64 local_protection_err; 195789f81008SSelvin Xavier __le64 mem_mgmt_op_err; 195889f81008SSelvin Xavier __le64 remote_invalid_req_err; 195989f81008SSelvin Xavier __le64 remote_access_err; 196089f81008SSelvin Xavier __le64 remote_op_err; 196189f81008SSelvin Xavier __le64 dup_req; 196289f81008SSelvin Xavier __le64 res_exceed_max; 196389f81008SSelvin Xavier __le64 res_length_mismatch; 196489f81008SSelvin Xavier __le64 res_exceeds_wqe; 196589f81008SSelvin Xavier __le64 res_opcode_err; 196689f81008SSelvin Xavier __le64 res_rx_invalid_rkey; 196789f81008SSelvin Xavier __le64 res_rx_domain_err; 196889f81008SSelvin Xavier __le64 res_rx_no_perm; 196989f81008SSelvin Xavier __le64 res_rx_range_err; 197089f81008SSelvin Xavier __le64 res_tx_invalid_rkey; 197189f81008SSelvin Xavier __le64 res_tx_domain_err; 197289f81008SSelvin Xavier __le64 res_tx_no_perm; 197389f81008SSelvin Xavier __le64 res_tx_range_err; 197489f81008SSelvin Xavier __le64 res_irrq_oflow; 197589f81008SSelvin Xavier __le64 res_unsup_opcode; 197689f81008SSelvin Xavier __le64 res_unaligned_atomic; 197789f81008SSelvin Xavier __le64 res_rem_inv_err; 197889f81008SSelvin Xavier __le64 res_mem_error; 197989f81008SSelvin Xavier __le64 res_srq_err; 198089f81008SSelvin Xavier __le64 res_cmp_err; 198189f81008SSelvin Xavier __le64 res_invalid_dup_rkey; 198289f81008SSelvin Xavier __le64 res_wqe_format_err; 198389f81008SSelvin Xavier __le64 res_cq_load_err; 198489f81008SSelvin Xavier __le64 res_srq_load_err; 198589f81008SSelvin Xavier __le64 res_tx_pci_err; 198689f81008SSelvin Xavier __le64 res_rx_pci_err; 1987316dd282SSelvin Xavier __le64 res_oos_drop_count; 1988316dd282SSelvin Xavier __le64 active_qp_count_p0; 1989316dd282SSelvin Xavier __le64 active_qp_count_p1; 1990316dd282SSelvin Xavier __le64 active_qp_count_p2; 1991316dd282SSelvin Xavier __le64 active_qp_count_p3; 199289f81008SSelvin Xavier }; 199389f81008SSelvin Xavier 19949a381f7eSSelvin Xavier /* cmdq_query_roce_stats_ext (size:192b/24B) */ 19959a381f7eSSelvin Xavier struct cmdq_query_roce_stats_ext { 19969a381f7eSSelvin Xavier u8 opcode; 19979a381f7eSSelvin Xavier #define CMDQ_QUERY_ROCE_STATS_EXT_OPCODE_QUERY_ROCE_STATS 0x92UL 19989a381f7eSSelvin Xavier #define CMDQ_QUERY_ROCE_STATS_EXT_OPCODE_LAST \ 19999a381f7eSSelvin Xavier CMDQ_QUERY_ROCE_STATS_EXT_OPCODE_QUERY_ROCE_STATS 20009a381f7eSSelvin Xavier u8 cmd_size; 20019a381f7eSSelvin Xavier __le16 flags; 20029a381f7eSSelvin Xavier #define CMDQ_QUERY_ROCE_STATS_EXT_FLAGS_COLLECTION_ID 0x1UL 20039a381f7eSSelvin Xavier #define CMDQ_QUERY_ROCE_STATS_EXT_FLAGS_FUNCTION_ID 0x2UL 20049a381f7eSSelvin Xavier __le16 cookie; 20059a381f7eSSelvin Xavier u8 resp_size; 20069a381f7eSSelvin Xavier u8 collection_id; 20079a381f7eSSelvin Xavier __le64 resp_addr; 20089a381f7eSSelvin Xavier __le32 function_id; 20099a381f7eSSelvin Xavier #define CMDQ_QUERY_ROCE_STATS_EXT_PF_NUM_MASK 0xffUL 20109a381f7eSSelvin Xavier #define CMDQ_QUERY_ROCE_STATS_EXT_PF_NUM_SFT 0 20119a381f7eSSelvin Xavier #define CMDQ_QUERY_ROCE_STATS_EXT_VF_NUM_MASK 0xffff00UL 20129a381f7eSSelvin Xavier #define CMDQ_QUERY_ROCE_STATS_EXT_VF_NUM_SFT 8 20139a381f7eSSelvin Xavier #define CMDQ_QUERY_ROCE_STATS_EXT_VF_VALID 0x1000000UL 20149a381f7eSSelvin Xavier __le32 reserved32; 20159a381f7eSSelvin Xavier }; 20169a381f7eSSelvin Xavier 20179a381f7eSSelvin Xavier /* creq_query_roce_stats_ext_resp (size:128b/16B) */ 20189a381f7eSSelvin Xavier struct creq_query_roce_stats_ext_resp { 20199a381f7eSSelvin Xavier u8 type; 20209a381f7eSSelvin Xavier #define CREQ_QUERY_ROCE_STATS_EXT_RESP_TYPE_MASK 0x3fUL 20219a381f7eSSelvin Xavier #define CREQ_QUERY_ROCE_STATS_EXT_RESP_TYPE_SFT 0 20229a381f7eSSelvin Xavier #define CREQ_QUERY_ROCE_STATS_EXT_RESP_TYPE_QP_EVENT 0x38UL 20239a381f7eSSelvin Xavier #define CREQ_QUERY_ROCE_STATS_EXT_RESP_TYPE_LAST \ 20249a381f7eSSelvin Xavier CREQ_QUERY_ROCE_STATS_EXT_RESP_TYPE_QP_EVENT 20259a381f7eSSelvin Xavier u8 status; 20269a381f7eSSelvin Xavier __le16 cookie; 20279a381f7eSSelvin Xavier __le32 size; 20289a381f7eSSelvin Xavier u8 v; 20299a381f7eSSelvin Xavier #define CREQ_QUERY_ROCE_STATS_EXT_RESP_V 0x1UL 20309a381f7eSSelvin Xavier u8 event; 20319a381f7eSSelvin Xavier #define CREQ_QUERY_ROCE_STATS_EXT_RESP_EVENT_QUERY_ROCE_STATS_EXT 0x92UL 20329a381f7eSSelvin Xavier #define CREQ_QUERY_ROCE_STATS_EXT_RESP_EVENT_LAST \ 20339a381f7eSSelvin Xavier CREQ_QUERY_ROCE_STATS_EXT_RESP_EVENT_QUERY_ROCE_STATS_EXT 20349a381f7eSSelvin Xavier u8 reserved48[6]; 20359a381f7eSSelvin Xavier }; 20369a381f7eSSelvin Xavier 2037a9a457f3SSelvin Xavier /* creq_query_roce_stats_ext_resp_sb (size:1856b/232B) */ 20389a381f7eSSelvin Xavier struct creq_query_roce_stats_ext_resp_sb { 20399a381f7eSSelvin Xavier u8 opcode; 20409a381f7eSSelvin Xavier #define CREQ_QUERY_ROCE_STATS_EXT_RESP_SB_OPCODE_QUERY_ROCE_STATS_EXT 0x92UL 20419a381f7eSSelvin Xavier #define CREQ_QUERY_ROCE_STATS_EXT_RESP_SB_OPCODE_LAST \ 20429a381f7eSSelvin Xavier CREQ_QUERY_ROCE_STATS_EXT_RESP_SB_OPCODE_QUERY_ROCE_STATS_EXT 20439a381f7eSSelvin Xavier u8 status; 20449a381f7eSSelvin Xavier __le16 cookie; 20459a381f7eSSelvin Xavier __le16 flags; 20469a381f7eSSelvin Xavier u8 resp_size; 20479a381f7eSSelvin Xavier u8 rsvd; 20489a381f7eSSelvin Xavier __le64 tx_atomic_req_pkts; 20499a381f7eSSelvin Xavier __le64 tx_read_req_pkts; 20509a381f7eSSelvin Xavier __le64 tx_read_res_pkts; 20519a381f7eSSelvin Xavier __le64 tx_write_req_pkts; 20529a381f7eSSelvin Xavier __le64 tx_send_req_pkts; 20539a381f7eSSelvin Xavier __le64 tx_roce_pkts; 20549a381f7eSSelvin Xavier __le64 tx_roce_bytes; 20559a381f7eSSelvin Xavier __le64 rx_atomic_req_pkts; 20569a381f7eSSelvin Xavier __le64 rx_read_req_pkts; 20579a381f7eSSelvin Xavier __le64 rx_read_res_pkts; 20589a381f7eSSelvin Xavier __le64 rx_write_req_pkts; 20599a381f7eSSelvin Xavier __le64 rx_send_req_pkts; 20609a381f7eSSelvin Xavier __le64 rx_roce_pkts; 20619a381f7eSSelvin Xavier __le64 rx_roce_bytes; 20629a381f7eSSelvin Xavier __le64 rx_roce_good_pkts; 20639a381f7eSSelvin Xavier __le64 rx_roce_good_bytes; 20649a381f7eSSelvin Xavier __le64 rx_out_of_buffer_pkts; 20659a381f7eSSelvin Xavier __le64 rx_out_of_sequence_pkts; 20669a381f7eSSelvin Xavier __le64 tx_cnp_pkts; 20679a381f7eSSelvin Xavier __le64 rx_cnp_pkts; 20689a381f7eSSelvin Xavier __le64 rx_ecn_marked_pkts; 20699a381f7eSSelvin Xavier __le64 tx_cnp_bytes; 20709a381f7eSSelvin Xavier __le64 rx_cnp_bytes; 2071a9a457f3SSelvin Xavier __le64 seq_err_naks_rcvd; 2072a9a457f3SSelvin Xavier __le64 rnr_naks_rcvd; 2073a9a457f3SSelvin Xavier __le64 missing_resp; 2074a9a457f3SSelvin Xavier __le64 to_retransmit; 2075a9a457f3SSelvin Xavier __le64 dup_req; 20769a381f7eSSelvin Xavier }; 20779a381f7eSSelvin Xavier 2078a9a457f3SSelvin Xavier /* cmdq_query_func (size:128b/16B) */ 2079a9a457f3SSelvin Xavier struct cmdq_query_func { 2080a9a457f3SSelvin Xavier u8 opcode; 2081a9a457f3SSelvin Xavier #define CMDQ_QUERY_FUNC_OPCODE_QUERY_FUNC 0x83UL 2082a9a457f3SSelvin Xavier #define CMDQ_QUERY_FUNC_OPCODE_LAST CMDQ_QUERY_FUNC_OPCODE_QUERY_FUNC 2083a9a457f3SSelvin Xavier u8 cmd_size; 2084a9a457f3SSelvin Xavier __le16 flags; 2085a9a457f3SSelvin Xavier __le16 cookie; 2086a9a457f3SSelvin Xavier u8 resp_size; 2087a9a457f3SSelvin Xavier u8 reserved8; 2088a9a457f3SSelvin Xavier __le64 resp_addr; 2089a9a457f3SSelvin Xavier }; 2090a9a457f3SSelvin Xavier 2091a9a457f3SSelvin Xavier /* creq_query_func_resp (size:128b/16B) */ 2092a9a457f3SSelvin Xavier struct creq_query_func_resp { 2093a9a457f3SSelvin Xavier u8 type; 2094a9a457f3SSelvin Xavier #define CREQ_QUERY_FUNC_RESP_TYPE_MASK 0x3fUL 2095a9a457f3SSelvin Xavier #define CREQ_QUERY_FUNC_RESP_TYPE_SFT 0 2096a9a457f3SSelvin Xavier #define CREQ_QUERY_FUNC_RESP_TYPE_QP_EVENT 0x38UL 2097a9a457f3SSelvin Xavier #define CREQ_QUERY_FUNC_RESP_TYPE_LAST CREQ_QUERY_FUNC_RESP_TYPE_QP_EVENT 2098a9a457f3SSelvin Xavier u8 status; 2099a9a457f3SSelvin Xavier __le16 cookie; 2100a9a457f3SSelvin Xavier __le32 size; 2101a9a457f3SSelvin Xavier u8 v; 2102a9a457f3SSelvin Xavier #define CREQ_QUERY_FUNC_RESP_V 0x1UL 2103a9a457f3SSelvin Xavier u8 event; 2104a9a457f3SSelvin Xavier #define CREQ_QUERY_FUNC_RESP_EVENT_QUERY_FUNC 0x83UL 2105a9a457f3SSelvin Xavier #define CREQ_QUERY_FUNC_RESP_EVENT_LAST CREQ_QUERY_FUNC_RESP_EVENT_QUERY_FUNC 2106a9a457f3SSelvin Xavier u8 reserved48[6]; 2107a9a457f3SSelvin Xavier }; 2108a9a457f3SSelvin Xavier 2109a9a457f3SSelvin Xavier /* creq_query_func_resp_sb (size:1088b/136B) */ 2110a9a457f3SSelvin Xavier struct creq_query_func_resp_sb { 2111a9a457f3SSelvin Xavier u8 opcode; 2112a9a457f3SSelvin Xavier #define CREQ_QUERY_FUNC_RESP_SB_OPCODE_QUERY_FUNC 0x83UL 2113a9a457f3SSelvin Xavier #define CREQ_QUERY_FUNC_RESP_SB_OPCODE_LAST CREQ_QUERY_FUNC_RESP_SB_OPCODE_QUERY_FUNC 2114a9a457f3SSelvin Xavier u8 status; 2115a9a457f3SSelvin Xavier __le16 cookie; 2116a9a457f3SSelvin Xavier __le16 flags; 2117a9a457f3SSelvin Xavier u8 resp_size; 2118a9a457f3SSelvin Xavier u8 reserved8; 2119a9a457f3SSelvin Xavier __le64 max_mr_size; 2120a9a457f3SSelvin Xavier __le32 max_qp; 2121a9a457f3SSelvin Xavier __le16 max_qp_wr; 2122a9a457f3SSelvin Xavier __le16 dev_cap_flags; 2123a9a457f3SSelvin Xavier #define CREQ_QUERY_FUNC_RESP_SB_RESIZE_QP 0x1UL 2124a9a457f3SSelvin Xavier #define CREQ_QUERY_FUNC_RESP_SB_CC_GENERATION_MASK 0xeUL 2125a9a457f3SSelvin Xavier #define CREQ_QUERY_FUNC_RESP_SB_CC_GENERATION_SFT 1 2126a9a457f3SSelvin Xavier #define CREQ_QUERY_FUNC_RESP_SB_CC_GENERATION_CC_GEN0 (0x0UL << 1) 2127a9a457f3SSelvin Xavier #define CREQ_QUERY_FUNC_RESP_SB_CC_GENERATION_CC_GEN1 (0x1UL << 1) 2128a9a457f3SSelvin Xavier #define CREQ_QUERY_FUNC_RESP_SB_CC_GENERATION_CC_GEN1_EXT (0x2UL << 1) 2129a9a457f3SSelvin Xavier #define CREQ_QUERY_FUNC_RESP_SB_CC_GENERATION_LAST \ 2130a9a457f3SSelvin Xavier CREQ_QUERY_FUNC_RESP_SB_CC_GENERATION_CC_GEN1_EXT 2131a9a457f3SSelvin Xavier #define CREQ_QUERY_FUNC_RESP_SB_EXT_STATS 0x10UL 2132a9a457f3SSelvin Xavier #define CREQ_QUERY_FUNC_RESP_SB_MR_REGISTER_ALLOC 0x20UL 2133a9a457f3SSelvin Xavier #define CREQ_QUERY_FUNC_RESP_SB_OPTIMIZED_TRANSMIT_ENABLED 0x40UL 2134a9a457f3SSelvin Xavier #define CREQ_QUERY_FUNC_RESP_SB_CQE_V2 0x80UL 2135a9a457f3SSelvin Xavier #define CREQ_QUERY_FUNC_RESP_SB_PINGPONG_PUSH_MODE 0x100UL 2136a9a457f3SSelvin Xavier #define CREQ_QUERY_FUNC_RESP_SB_HW_REQUESTER_RETX_ENABLED 0x200UL 2137a9a457f3SSelvin Xavier #define CREQ_QUERY_FUNC_RESP_SB_HW_RESPONDER_RETX_ENABLED 0x400UL 2138a9a457f3SSelvin Xavier __le32 max_cq; 2139a9a457f3SSelvin Xavier __le32 max_cqe; 2140a9a457f3SSelvin Xavier __le32 max_pd; 2141a9a457f3SSelvin Xavier u8 max_sge; 2142a9a457f3SSelvin Xavier u8 max_srq_sge; 2143a9a457f3SSelvin Xavier u8 max_qp_rd_atom; 2144a9a457f3SSelvin Xavier u8 max_qp_init_rd_atom; 2145a9a457f3SSelvin Xavier __le32 max_mr; 2146a9a457f3SSelvin Xavier __le32 max_mw; 2147a9a457f3SSelvin Xavier __le32 max_raw_eth_qp; 2148a9a457f3SSelvin Xavier __le32 max_ah; 2149a9a457f3SSelvin Xavier __le32 max_fmr; 2150a9a457f3SSelvin Xavier __le32 max_srq_wr; 2151a9a457f3SSelvin Xavier __le32 max_pkeys; 2152a9a457f3SSelvin Xavier __le32 max_inline_data; 2153a9a457f3SSelvin Xavier u8 max_map_per_fmr; 2154a9a457f3SSelvin Xavier u8 l2_db_space_size; 2155a9a457f3SSelvin Xavier __le16 max_srq; 2156a9a457f3SSelvin Xavier __le32 max_gid; 2157a9a457f3SSelvin Xavier __le32 tqm_alloc_reqs[12]; 2158a9a457f3SSelvin Xavier __le32 max_dpi; 2159a9a457f3SSelvin Xavier u8 max_sge_var_wqe; 2160a9a457f3SSelvin Xavier u8 reserved_8; 2161a9a457f3SSelvin Xavier __le16 max_inline_data_var_wqe; 2162a9a457f3SSelvin Xavier }; 2163a9a457f3SSelvin Xavier 2164a9a457f3SSelvin Xavier /* cmdq_set_func_resources (size:448b/56B) */ 2165a9a457f3SSelvin Xavier struct cmdq_set_func_resources { 2166a9a457f3SSelvin Xavier u8 opcode; 2167a9a457f3SSelvin Xavier #define CMDQ_SET_FUNC_RESOURCES_OPCODE_SET_FUNC_RESOURCES 0x84UL 2168a9a457f3SSelvin Xavier #define CMDQ_SET_FUNC_RESOURCES_OPCODE_LAST\ 2169a9a457f3SSelvin Xavier CMDQ_SET_FUNC_RESOURCES_OPCODE_SET_FUNC_RESOURCES 2170a9a457f3SSelvin Xavier u8 cmd_size; 2171a9a457f3SSelvin Xavier __le16 flags; 2172a9a457f3SSelvin Xavier #define CMDQ_SET_FUNC_RESOURCES_FLAGS_MRAV_RESERVATION_SPLIT 0x1UL 2173a9a457f3SSelvin Xavier __le16 cookie; 2174a9a457f3SSelvin Xavier u8 resp_size; 2175a9a457f3SSelvin Xavier u8 reserved8; 2176a9a457f3SSelvin Xavier __le64 resp_addr; 2177a9a457f3SSelvin Xavier __le32 number_of_qp; 2178a9a457f3SSelvin Xavier __le32 number_of_mrw; 2179a9a457f3SSelvin Xavier __le32 number_of_srq; 2180a9a457f3SSelvin Xavier __le32 number_of_cq; 2181a9a457f3SSelvin Xavier __le32 max_qp_per_vf; 2182a9a457f3SSelvin Xavier __le32 max_mrw_per_vf; 2183a9a457f3SSelvin Xavier __le32 max_srq_per_vf; 2184a9a457f3SSelvin Xavier __le32 max_cq_per_vf; 2185a9a457f3SSelvin Xavier __le32 max_gid_per_vf; 2186a9a457f3SSelvin Xavier __le32 stat_ctx_id; 2187a9a457f3SSelvin Xavier }; 2188a9a457f3SSelvin Xavier 2189a9a457f3SSelvin Xavier /* creq_set_func_resources_resp (size:128b/16B) */ 2190a9a457f3SSelvin Xavier struct creq_set_func_resources_resp { 2191a9a457f3SSelvin Xavier u8 type; 2192a9a457f3SSelvin Xavier #define CREQ_SET_FUNC_RESOURCES_RESP_TYPE_MASK 0x3fUL 2193a9a457f3SSelvin Xavier #define CREQ_SET_FUNC_RESOURCES_RESP_TYPE_SFT 0 2194a9a457f3SSelvin Xavier #define CREQ_SET_FUNC_RESOURCES_RESP_TYPE_QP_EVENT 0x38UL 2195a9a457f3SSelvin Xavier #define CREQ_SET_FUNC_RESOURCES_RESP_TYPE_LAST CREQ_SET_FUNC_RESOURCES_RESP_TYPE_QP_EVENT 2196a9a457f3SSelvin Xavier u8 status; 2197a9a457f3SSelvin Xavier __le16 cookie; 2198a9a457f3SSelvin Xavier __le32 reserved32; 2199a9a457f3SSelvin Xavier u8 v; 2200a9a457f3SSelvin Xavier #define CREQ_SET_FUNC_RESOURCES_RESP_V 0x1UL 2201a9a457f3SSelvin Xavier u8 event; 2202a9a457f3SSelvin Xavier #define CREQ_SET_FUNC_RESOURCES_RESP_EVENT_SET_FUNC_RESOURCES 0x84UL 2203a9a457f3SSelvin Xavier #define CREQ_SET_FUNC_RESOURCES_RESP_EVENT_LAST \ 2204a9a457f3SSelvin Xavier CREQ_SET_FUNC_RESOURCES_RESP_EVENT_SET_FUNC_RESOURCES 2205a9a457f3SSelvin Xavier u8 reserved48[6]; 2206a9a457f3SSelvin Xavier }; 2207a9a457f3SSelvin Xavier 2208a9a457f3SSelvin Xavier /* cmdq_map_tc_to_cos (size:192b/24B) */ 2209a9a457f3SSelvin Xavier struct cmdq_map_tc_to_cos { 2210a9a457f3SSelvin Xavier u8 opcode; 2211a9a457f3SSelvin Xavier #define CMDQ_MAP_TC_TO_COS_OPCODE_MAP_TC_TO_COS 0x8aUL 2212a9a457f3SSelvin Xavier #define CMDQ_MAP_TC_TO_COS_OPCODE_LAST CMDQ_MAP_TC_TO_COS_OPCODE_MAP_TC_TO_COS 2213a9a457f3SSelvin Xavier u8 cmd_size; 2214a9a457f3SSelvin Xavier __le16 flags; 2215a9a457f3SSelvin Xavier __le16 cookie; 2216a9a457f3SSelvin Xavier u8 resp_size; 2217a9a457f3SSelvin Xavier u8 reserved8; 2218a9a457f3SSelvin Xavier __le64 resp_addr; 2219a9a457f3SSelvin Xavier __le16 cos0; 2220a9a457f3SSelvin Xavier #define CMDQ_MAP_TC_TO_COS_COS0_NO_CHANGE 0xffffUL 2221a9a457f3SSelvin Xavier #define CMDQ_MAP_TC_TO_COS_COS0_LAST CMDQ_MAP_TC_TO_COS_COS0_NO_CHANGE 2222a9a457f3SSelvin Xavier __le16 cos1; 2223a9a457f3SSelvin Xavier #define CMDQ_MAP_TC_TO_COS_COS1_DISABLE 0x8000UL 2224a9a457f3SSelvin Xavier #define CMDQ_MAP_TC_TO_COS_COS1_NO_CHANGE 0xffffUL 2225a9a457f3SSelvin Xavier #define CMDQ_MAP_TC_TO_COS_COS1_LAST CMDQ_MAP_TC_TO_COS_COS1_NO_CHANGE 2226a9a457f3SSelvin Xavier __le32 unused_0; 2227a9a457f3SSelvin Xavier }; 2228a9a457f3SSelvin Xavier 2229a9a457f3SSelvin Xavier /* creq_map_tc_to_cos_resp (size:128b/16B) */ 2230a9a457f3SSelvin Xavier struct creq_map_tc_to_cos_resp { 2231a9a457f3SSelvin Xavier u8 type; 2232a9a457f3SSelvin Xavier #define CREQ_MAP_TC_TO_COS_RESP_TYPE_MASK 0x3fUL 2233a9a457f3SSelvin Xavier #define CREQ_MAP_TC_TO_COS_RESP_TYPE_SFT 0 2234a9a457f3SSelvin Xavier #define CREQ_MAP_TC_TO_COS_RESP_TYPE_QP_EVENT 0x38UL 2235a9a457f3SSelvin Xavier #define CREQ_MAP_TC_TO_COS_RESP_TYPE_LAST CREQ_MAP_TC_TO_COS_RESP_TYPE_QP_EVENT 2236a9a457f3SSelvin Xavier u8 status; 2237a9a457f3SSelvin Xavier __le16 cookie; 2238a9a457f3SSelvin Xavier __le32 reserved32; 2239a9a457f3SSelvin Xavier u8 v; 2240a9a457f3SSelvin Xavier #define CREQ_MAP_TC_TO_COS_RESP_V 0x1UL 2241a9a457f3SSelvin Xavier u8 event; 2242a9a457f3SSelvin Xavier #define CREQ_MAP_TC_TO_COS_RESP_EVENT_MAP_TC_TO_COS 0x8aUL 2243a9a457f3SSelvin Xavier #define CREQ_MAP_TC_TO_COS_RESP_EVENT_LAST CREQ_MAP_TC_TO_COS_RESP_EVENT_MAP_TC_TO_COS 2244a9a457f3SSelvin Xavier u8 reserved48[6]; 2245a9a457f3SSelvin Xavier }; 2246a9a457f3SSelvin Xavier 2247a9a457f3SSelvin Xavier /* cmdq_query_roce_cc (size:128b/16B) */ 2248a9a457f3SSelvin Xavier struct cmdq_query_roce_cc { 2249a9a457f3SSelvin Xavier u8 opcode; 2250a9a457f3SSelvin Xavier #define CMDQ_QUERY_ROCE_CC_OPCODE_QUERY_ROCE_CC 0x8dUL 2251a9a457f3SSelvin Xavier #define CMDQ_QUERY_ROCE_CC_OPCODE_LAST CMDQ_QUERY_ROCE_CC_OPCODE_QUERY_ROCE_CC 2252a9a457f3SSelvin Xavier u8 cmd_size; 2253a9a457f3SSelvin Xavier __le16 flags; 2254a9a457f3SSelvin Xavier __le16 cookie; 2255a9a457f3SSelvin Xavier u8 resp_size; 2256a9a457f3SSelvin Xavier u8 reserved8; 2257a9a457f3SSelvin Xavier __le64 resp_addr; 2258a9a457f3SSelvin Xavier }; 2259a9a457f3SSelvin Xavier 2260a9a457f3SSelvin Xavier /* creq_query_roce_cc_resp (size:128b/16B) */ 2261a9a457f3SSelvin Xavier struct creq_query_roce_cc_resp { 2262a9a457f3SSelvin Xavier u8 type; 2263a9a457f3SSelvin Xavier #define CREQ_QUERY_ROCE_CC_RESP_TYPE_MASK 0x3fUL 2264a9a457f3SSelvin Xavier #define CREQ_QUERY_ROCE_CC_RESP_TYPE_SFT 0 2265a9a457f3SSelvin Xavier #define CREQ_QUERY_ROCE_CC_RESP_TYPE_QP_EVENT 0x38UL 2266a9a457f3SSelvin Xavier #define CREQ_QUERY_ROCE_CC_RESP_TYPE_LAST CREQ_QUERY_ROCE_CC_RESP_TYPE_QP_EVENT 2267a9a457f3SSelvin Xavier u8 status; 2268a9a457f3SSelvin Xavier __le16 cookie; 2269a9a457f3SSelvin Xavier __le32 size; 2270a9a457f3SSelvin Xavier u8 v; 2271a9a457f3SSelvin Xavier #define CREQ_QUERY_ROCE_CC_RESP_V 0x1UL 2272a9a457f3SSelvin Xavier u8 event; 2273a9a457f3SSelvin Xavier #define CREQ_QUERY_ROCE_CC_RESP_EVENT_QUERY_ROCE_CC 0x8dUL 2274a9a457f3SSelvin Xavier #define CREQ_QUERY_ROCE_CC_RESP_EVENT_LAST CREQ_QUERY_ROCE_CC_RESP_EVENT_QUERY_ROCE_CC 2275a9a457f3SSelvin Xavier u8 reserved48[6]; 2276a9a457f3SSelvin Xavier }; 2277a9a457f3SSelvin Xavier 2278a9a457f3SSelvin Xavier /* creq_query_roce_cc_resp_sb (size:256b/32B) */ 2279a9a457f3SSelvin Xavier struct creq_query_roce_cc_resp_sb { 2280a9a457f3SSelvin Xavier u8 opcode; 2281a9a457f3SSelvin Xavier #define CREQ_QUERY_ROCE_CC_RESP_SB_OPCODE_QUERY_ROCE_CC 0x8dUL 2282a9a457f3SSelvin Xavier #define CREQ_QUERY_ROCE_CC_RESP_SB_OPCODE_LAST \ 2283a9a457f3SSelvin Xavier CREQ_QUERY_ROCE_CC_RESP_SB_OPCODE_QUERY_ROCE_CC 2284a9a457f3SSelvin Xavier u8 status; 2285a9a457f3SSelvin Xavier __le16 cookie; 2286a9a457f3SSelvin Xavier __le16 flags; 2287a9a457f3SSelvin Xavier u8 resp_size; 2288a9a457f3SSelvin Xavier u8 reserved8; 2289a9a457f3SSelvin Xavier u8 enable_cc; 2290a9a457f3SSelvin Xavier #define CREQ_QUERY_ROCE_CC_RESP_SB_ENABLE_CC 0x1UL 2291a9a457f3SSelvin Xavier #define CREQ_QUERY_ROCE_CC_RESP_SB_UNUSED7_MASK 0xfeUL 2292a9a457f3SSelvin Xavier #define CREQ_QUERY_ROCE_CC_RESP_SB_UNUSED7_SFT 1 2293a9a457f3SSelvin Xavier u8 tos_dscp_tos_ecn; 2294a9a457f3SSelvin Xavier #define CREQ_QUERY_ROCE_CC_RESP_SB_TOS_ECN_MASK 0x3UL 2295a9a457f3SSelvin Xavier #define CREQ_QUERY_ROCE_CC_RESP_SB_TOS_ECN_SFT 0 2296a9a457f3SSelvin Xavier #define CREQ_QUERY_ROCE_CC_RESP_SB_TOS_DSCP_MASK 0xfcUL 2297a9a457f3SSelvin Xavier #define CREQ_QUERY_ROCE_CC_RESP_SB_TOS_DSCP_SFT 2 2298a9a457f3SSelvin Xavier u8 g; 2299a9a457f3SSelvin Xavier u8 num_phases_per_state; 2300a9a457f3SSelvin Xavier __le16 init_cr; 2301a9a457f3SSelvin Xavier __le16 init_tr; 2302a9a457f3SSelvin Xavier u8 alt_vlan_pcp; 2303a9a457f3SSelvin Xavier #define CREQ_QUERY_ROCE_CC_RESP_SB_ALT_VLAN_PCP_MASK 0x7UL 2304a9a457f3SSelvin Xavier #define CREQ_QUERY_ROCE_CC_RESP_SB_ALT_VLAN_PCP_SFT 0 2305a9a457f3SSelvin Xavier #define CREQ_QUERY_ROCE_CC_RESP_SB_RSVD1_MASK 0xf8UL 2306a9a457f3SSelvin Xavier #define CREQ_QUERY_ROCE_CC_RESP_SB_RSVD1_SFT 3 2307a9a457f3SSelvin Xavier u8 alt_tos_dscp; 2308a9a457f3SSelvin Xavier #define CREQ_QUERY_ROCE_CC_RESP_SB_ALT_TOS_DSCP_MASK 0x3fUL 2309a9a457f3SSelvin Xavier #define CREQ_QUERY_ROCE_CC_RESP_SB_ALT_TOS_DSCP_SFT 0 2310a9a457f3SSelvin Xavier #define CREQ_QUERY_ROCE_CC_RESP_SB_RSVD4_MASK 0xc0UL 2311a9a457f3SSelvin Xavier #define CREQ_QUERY_ROCE_CC_RESP_SB_RSVD4_SFT 6 2312a9a457f3SSelvin Xavier u8 cc_mode; 2313a9a457f3SSelvin Xavier #define CREQ_QUERY_ROCE_CC_RESP_SB_CC_MODE_DCTCP 0x0UL 2314a9a457f3SSelvin Xavier #define CREQ_QUERY_ROCE_CC_RESP_SB_CC_MODE_PROBABILISTIC 0x1UL 2315a9a457f3SSelvin Xavier #define CREQ_QUERY_ROCE_CC_RESP_SB_CC_MODE_LAST \ 2316a9a457f3SSelvin Xavier CREQ_QUERY_ROCE_CC_RESP_SB_CC_MODE_PROBABILISTIC 2317a9a457f3SSelvin Xavier u8 tx_queue; 2318a9a457f3SSelvin Xavier __le16 rtt; 2319a9a457f3SSelvin Xavier #define CREQ_QUERY_ROCE_CC_RESP_SB_RTT_MASK 0x3fffUL 2320a9a457f3SSelvin Xavier #define CREQ_QUERY_ROCE_CC_RESP_SB_RTT_SFT 0 2321a9a457f3SSelvin Xavier #define CREQ_QUERY_ROCE_CC_RESP_SB_RSVD5_MASK 0xc000UL 2322a9a457f3SSelvin Xavier #define CREQ_QUERY_ROCE_CC_RESP_SB_RSVD5_SFT 14 2323a9a457f3SSelvin Xavier __le16 tcp_cp; 2324a9a457f3SSelvin Xavier #define CREQ_QUERY_ROCE_CC_RESP_SB_TCP_CP_MASK 0x3ffUL 2325a9a457f3SSelvin Xavier #define CREQ_QUERY_ROCE_CC_RESP_SB_TCP_CP_SFT 0 2326a9a457f3SSelvin Xavier #define CREQ_QUERY_ROCE_CC_RESP_SB_RSVD6_MASK 0xfc00UL 2327a9a457f3SSelvin Xavier #define CREQ_QUERY_ROCE_CC_RESP_SB_RSVD6_SFT 10 2328a9a457f3SSelvin Xavier __le16 inactivity_th; 2329a9a457f3SSelvin Xavier u8 pkts_per_phase; 2330a9a457f3SSelvin Xavier u8 time_per_phase; 2331a9a457f3SSelvin Xavier __le32 reserved32; 2332a9a457f3SSelvin Xavier }; 2333a9a457f3SSelvin Xavier 2334a9a457f3SSelvin Xavier /* creq_query_roce_cc_resp_sb_tlv (size:384b/48B) */ 2335a9a457f3SSelvin Xavier struct creq_query_roce_cc_resp_sb_tlv { 2336a9a457f3SSelvin Xavier __le16 cmd_discr; 2337a9a457f3SSelvin Xavier u8 reserved_8b; 2338a9a457f3SSelvin Xavier u8 tlv_flags; 2339a9a457f3SSelvin Xavier #define CREQ_QUERY_ROCE_CC_RESP_SB_TLV_TLV_FLAGS_MORE 0x1UL 2340a9a457f3SSelvin Xavier #define CREQ_QUERY_ROCE_CC_RESP_SB_TLV_TLV_FLAGS_MORE_LAST 0x0UL 2341a9a457f3SSelvin Xavier #define CREQ_QUERY_ROCE_CC_RESP_SB_TLV_TLV_FLAGS_MORE_NOT_LAST 0x1UL 2342a9a457f3SSelvin Xavier #define CREQ_QUERY_ROCE_CC_RESP_SB_TLV_TLV_FLAGS_REQUIRED 0x2UL 2343a9a457f3SSelvin Xavier #define CREQ_QUERY_ROCE_CC_RESP_SB_TLV_TLV_FLAGS_REQUIRED_NO (0x0UL << 1) 2344a9a457f3SSelvin Xavier #define CREQ_QUERY_ROCE_CC_RESP_SB_TLV_TLV_FLAGS_REQUIRED_YES (0x1UL << 1) 2345a9a457f3SSelvin Xavier #define CREQ_QUERY_ROCE_CC_RESP_SB_TLV_TLV_FLAGS_REQUIRED_LAST \ 2346a9a457f3SSelvin Xavier CREQ_QUERY_ROCE_CC_RESP_SB_TLV_TLV_FLAGS_REQUIRED_YES 2347a9a457f3SSelvin Xavier __le16 tlv_type; 2348a9a457f3SSelvin Xavier __le16 length; 2349a9a457f3SSelvin Xavier u8 total_size; 2350a9a457f3SSelvin Xavier u8 reserved56[7]; 2351a9a457f3SSelvin Xavier u8 opcode; 2352a9a457f3SSelvin Xavier #define CREQ_QUERY_ROCE_CC_RESP_SB_TLV_OPCODE_QUERY_ROCE_CC 0x8dUL 2353a9a457f3SSelvin Xavier #define CREQ_QUERY_ROCE_CC_RESP_SB_TLV_OPCODE_LAST \ 2354a9a457f3SSelvin Xavier CREQ_QUERY_ROCE_CC_RESP_SB_TLV_OPCODE_QUERY_ROCE_CC 2355a9a457f3SSelvin Xavier u8 status; 2356a9a457f3SSelvin Xavier __le16 cookie; 2357a9a457f3SSelvin Xavier __le16 flags; 2358a9a457f3SSelvin Xavier u8 resp_size; 2359a9a457f3SSelvin Xavier u8 reserved8; 2360a9a457f3SSelvin Xavier u8 enable_cc; 2361a9a457f3SSelvin Xavier #define CREQ_QUERY_ROCE_CC_RESP_SB_TLV_ENABLE_CC 0x1UL 2362a9a457f3SSelvin Xavier #define CREQ_QUERY_ROCE_CC_RESP_SB_TLV_UNUSED7_MASK 0xfeUL 2363a9a457f3SSelvin Xavier #define CREQ_QUERY_ROCE_CC_RESP_SB_TLV_UNUSED7_SFT 1 2364a9a457f3SSelvin Xavier u8 tos_dscp_tos_ecn; 2365a9a457f3SSelvin Xavier #define CREQ_QUERY_ROCE_CC_RESP_SB_TLV_TOS_ECN_MASK 0x3UL 2366a9a457f3SSelvin Xavier #define CREQ_QUERY_ROCE_CC_RESP_SB_TLV_TOS_ECN_SFT 0 2367a9a457f3SSelvin Xavier #define CREQ_QUERY_ROCE_CC_RESP_SB_TLV_TOS_DSCP_MASK 0xfcUL 2368a9a457f3SSelvin Xavier #define CREQ_QUERY_ROCE_CC_RESP_SB_TLV_TOS_DSCP_SFT 2 2369a9a457f3SSelvin Xavier u8 g; 2370a9a457f3SSelvin Xavier u8 num_phases_per_state; 2371a9a457f3SSelvin Xavier __le16 init_cr; 2372a9a457f3SSelvin Xavier __le16 init_tr; 2373a9a457f3SSelvin Xavier u8 alt_vlan_pcp; 2374a9a457f3SSelvin Xavier #define CREQ_QUERY_ROCE_CC_RESP_SB_TLV_ALT_VLAN_PCP_MASK 0x7UL 2375a9a457f3SSelvin Xavier #define CREQ_QUERY_ROCE_CC_RESP_SB_TLV_ALT_VLAN_PCP_SFT 0 2376a9a457f3SSelvin Xavier #define CREQ_QUERY_ROCE_CC_RESP_SB_TLV_RSVD1_MASK 0xf8UL 2377a9a457f3SSelvin Xavier #define CREQ_QUERY_ROCE_CC_RESP_SB_TLV_RSVD1_SFT 3 2378a9a457f3SSelvin Xavier u8 alt_tos_dscp; 2379a9a457f3SSelvin Xavier #define CREQ_QUERY_ROCE_CC_RESP_SB_TLV_ALT_TOS_DSCP_MASK 0x3fUL 2380a9a457f3SSelvin Xavier #define CREQ_QUERY_ROCE_CC_RESP_SB_TLV_ALT_TOS_DSCP_SFT 0 2381a9a457f3SSelvin Xavier #define CREQ_QUERY_ROCE_CC_RESP_SB_TLV_RSVD4_MASK 0xc0UL 2382a9a457f3SSelvin Xavier #define CREQ_QUERY_ROCE_CC_RESP_SB_TLV_RSVD4_SFT 6 2383a9a457f3SSelvin Xavier u8 cc_mode; 2384a9a457f3SSelvin Xavier #define CREQ_QUERY_ROCE_CC_RESP_SB_TLV_CC_MODE_DCTCP 0x0UL 2385a9a457f3SSelvin Xavier #define CREQ_QUERY_ROCE_CC_RESP_SB_TLV_CC_MODE_PROBABILISTIC 0x1UL 2386a9a457f3SSelvin Xavier #define CREQ_QUERY_ROCE_CC_RESP_SB_TLV_CC_MODE_LAST\ 2387a9a457f3SSelvin Xavier CREQ_QUERY_ROCE_CC_RESP_SB_TLV_CC_MODE_PROBABILISTIC 2388a9a457f3SSelvin Xavier u8 tx_queue; 2389a9a457f3SSelvin Xavier __le16 rtt; 2390a9a457f3SSelvin Xavier #define CREQ_QUERY_ROCE_CC_RESP_SB_TLV_RTT_MASK 0x3fffUL 2391a9a457f3SSelvin Xavier #define CREQ_QUERY_ROCE_CC_RESP_SB_TLV_RTT_SFT 0 2392a9a457f3SSelvin Xavier #define CREQ_QUERY_ROCE_CC_RESP_SB_TLV_RSVD5_MASK 0xc000UL 2393a9a457f3SSelvin Xavier #define CREQ_QUERY_ROCE_CC_RESP_SB_TLV_RSVD5_SFT 14 2394a9a457f3SSelvin Xavier __le16 tcp_cp; 2395a9a457f3SSelvin Xavier #define CREQ_QUERY_ROCE_CC_RESP_SB_TLV_TCP_CP_MASK 0x3ffUL 2396a9a457f3SSelvin Xavier #define CREQ_QUERY_ROCE_CC_RESP_SB_TLV_TCP_CP_SFT 0 2397a9a457f3SSelvin Xavier #define CREQ_QUERY_ROCE_CC_RESP_SB_TLV_RSVD6_MASK 0xfc00UL 2398a9a457f3SSelvin Xavier #define CREQ_QUERY_ROCE_CC_RESP_SB_TLV_RSVD6_SFT 10 2399a9a457f3SSelvin Xavier __le16 inactivity_th; 2400a9a457f3SSelvin Xavier u8 pkts_per_phase; 2401a9a457f3SSelvin Xavier u8 time_per_phase; 2402a9a457f3SSelvin Xavier __le32 reserved32; 2403a9a457f3SSelvin Xavier }; 2404a9a457f3SSelvin Xavier 2405a9a457f3SSelvin Xavier /* creq_query_roce_cc_gen1_resp_sb_tlv (size:704b/88B) */ 2406a9a457f3SSelvin Xavier struct creq_query_roce_cc_gen1_resp_sb_tlv { 2407a9a457f3SSelvin Xavier __le16 cmd_discr; 2408a9a457f3SSelvin Xavier u8 reserved_8b; 2409a9a457f3SSelvin Xavier u8 tlv_flags; 2410a9a457f3SSelvin Xavier #define CREQ_QUERY_ROCE_CC_GEN1_RESP_SB_TLV_TLV_FLAGS_MORE 0x1UL 2411a9a457f3SSelvin Xavier #define CREQ_QUERY_ROCE_CC_GEN1_RESP_SB_TLV_TLV_FLAGS_MORE_LAST 0x0UL 2412a9a457f3SSelvin Xavier #define CREQ_QUERY_ROCE_CC_GEN1_RESP_SB_TLV_TLV_FLAGS_MORE_NOT_LAST 0x1UL 2413a9a457f3SSelvin Xavier #define CREQ_QUERY_ROCE_CC_GEN1_RESP_SB_TLV_TLV_FLAGS_REQUIRED 0x2UL 2414a9a457f3SSelvin Xavier #define CREQ_QUERY_ROCE_CC_GEN1_RESP_SB_TLV_TLV_FLAGS_REQUIRED_NO (0x0UL << 1) 2415a9a457f3SSelvin Xavier #define CREQ_QUERY_ROCE_CC_GEN1_RESP_SB_TLV_TLV_FLAGS_REQUIRED_YES (0x1UL << 1) 2416a9a457f3SSelvin Xavier #define CREQ_QUERY_ROCE_CC_GEN1_RESP_SB_TLV_TLV_FLAGS_REQUIRED_LAST \ 2417a9a457f3SSelvin Xavier CREQ_QUERY_ROCE_CC_GEN1_RESP_SB_TLV_TLV_FLAGS_REQUIRED_YES 2418a9a457f3SSelvin Xavier __le16 tlv_type; 2419a9a457f3SSelvin Xavier __le16 length; 2420a9a457f3SSelvin Xavier __le64 reserved64; 2421a9a457f3SSelvin Xavier __le16 inactivity_th_hi; 2422a9a457f3SSelvin Xavier __le16 min_time_between_cnps; 2423a9a457f3SSelvin Xavier __le16 init_cp; 2424a9a457f3SSelvin Xavier u8 tr_update_mode; 2425a9a457f3SSelvin Xavier u8 tr_update_cycles; 2426a9a457f3SSelvin Xavier u8 fr_num_rtts; 2427a9a457f3SSelvin Xavier u8 ai_rate_increase; 2428a9a457f3SSelvin Xavier __le16 reduction_relax_rtts_th; 2429a9a457f3SSelvin Xavier __le16 additional_relax_cr_th; 2430a9a457f3SSelvin Xavier __le16 cr_min_th; 2431a9a457f3SSelvin Xavier u8 bw_avg_weight; 2432a9a457f3SSelvin Xavier u8 actual_cr_factor; 2433a9a457f3SSelvin Xavier __le16 max_cp_cr_th; 2434a9a457f3SSelvin Xavier u8 cp_bias_en; 2435a9a457f3SSelvin Xavier u8 cp_bias; 2436a9a457f3SSelvin Xavier u8 cnp_ecn; 2437a9a457f3SSelvin Xavier #define CREQ_QUERY_ROCE_CC_GEN1_RESP_SB_TLV_CNP_ECN_NOT_ECT 0x0UL 2438a9a457f3SSelvin Xavier #define CREQ_QUERY_ROCE_CC_GEN1_RESP_SB_TLV_CNP_ECN_ECT_1 0x1UL 2439a9a457f3SSelvin Xavier #define CREQ_QUERY_ROCE_CC_GEN1_RESP_SB_TLV_CNP_ECN_ECT_0 0x2UL 2440a9a457f3SSelvin Xavier #define CREQ_QUERY_ROCE_CC_GEN1_RESP_SB_TLV_CNP_ECN_LAST \ 2441a9a457f3SSelvin Xavier CREQ_QUERY_ROCE_CC_GEN1_RESP_SB_TLV_CNP_ECN_ECT_0 2442a9a457f3SSelvin Xavier u8 rtt_jitter_en; 2443a9a457f3SSelvin Xavier __le16 link_bytes_per_usec; 2444a9a457f3SSelvin Xavier __le16 reset_cc_cr_th; 2445a9a457f3SSelvin Xavier u8 cr_width; 2446a9a457f3SSelvin Xavier u8 quota_period_min; 2447a9a457f3SSelvin Xavier u8 quota_period_max; 2448a9a457f3SSelvin Xavier u8 quota_period_abs_max; 2449a9a457f3SSelvin Xavier __le16 tr_lower_bound; 2450a9a457f3SSelvin Xavier u8 cr_prob_factor; 2451a9a457f3SSelvin Xavier u8 tr_prob_factor; 2452a9a457f3SSelvin Xavier __le16 fairness_cr_th; 2453a9a457f3SSelvin Xavier u8 red_div; 2454a9a457f3SSelvin Xavier u8 cnp_ratio_th; 2455a9a457f3SSelvin Xavier __le16 exp_ai_rtts; 2456a9a457f3SSelvin Xavier u8 exp_ai_cr_cp_ratio; 2457a9a457f3SSelvin Xavier u8 use_rate_table; 2458a9a457f3SSelvin Xavier __le16 cp_exp_update_th; 2459a9a457f3SSelvin Xavier __le16 high_exp_ai_rtts_th1; 2460a9a457f3SSelvin Xavier __le16 high_exp_ai_rtts_th2; 2461a9a457f3SSelvin Xavier __le16 actual_cr_cong_free_rtts_th; 2462a9a457f3SSelvin Xavier __le16 severe_cong_cr_th1; 2463a9a457f3SSelvin Xavier __le16 severe_cong_cr_th2; 2464a9a457f3SSelvin Xavier __le32 link64B_per_rtt; 2465a9a457f3SSelvin Xavier u8 cc_ack_bytes; 2466a9a457f3SSelvin Xavier u8 reduce_init_en; 2467a9a457f3SSelvin Xavier __le16 reduce_init_cong_free_rtts_th; 2468a9a457f3SSelvin Xavier u8 random_no_red_en; 2469a9a457f3SSelvin Xavier u8 actual_cr_shift_correction_en; 2470a9a457f3SSelvin Xavier u8 quota_period_adjust_en; 2471a9a457f3SSelvin Xavier u8 reserved[5]; 2472a9a457f3SSelvin Xavier }; 2473a9a457f3SSelvin Xavier 2474a9a457f3SSelvin Xavier /* cmdq_modify_roce_cc (size:448b/56B) */ 2475a9a457f3SSelvin Xavier struct cmdq_modify_roce_cc { 2476a9a457f3SSelvin Xavier u8 opcode; 2477a9a457f3SSelvin Xavier #define CMDQ_MODIFY_ROCE_CC_OPCODE_MODIFY_ROCE_CC 0x8cUL 2478a9a457f3SSelvin Xavier #define CMDQ_MODIFY_ROCE_CC_OPCODE_LAST CMDQ_MODIFY_ROCE_CC_OPCODE_MODIFY_ROCE_CC 2479a9a457f3SSelvin Xavier u8 cmd_size; 2480a9a457f3SSelvin Xavier __le16 flags; 2481a9a457f3SSelvin Xavier __le16 cookie; 2482a9a457f3SSelvin Xavier u8 resp_size; 2483a9a457f3SSelvin Xavier u8 reserved8; 2484a9a457f3SSelvin Xavier __le64 resp_addr; 2485a9a457f3SSelvin Xavier __le32 modify_mask; 2486a9a457f3SSelvin Xavier #define CMDQ_MODIFY_ROCE_CC_MODIFY_MASK_ENABLE_CC 0x1UL 2487a9a457f3SSelvin Xavier #define CMDQ_MODIFY_ROCE_CC_MODIFY_MASK_G 0x2UL 2488a9a457f3SSelvin Xavier #define CMDQ_MODIFY_ROCE_CC_MODIFY_MASK_NUMPHASEPERSTATE 0x4UL 2489a9a457f3SSelvin Xavier #define CMDQ_MODIFY_ROCE_CC_MODIFY_MASK_INIT_CR 0x8UL 2490a9a457f3SSelvin Xavier #define CMDQ_MODIFY_ROCE_CC_MODIFY_MASK_INIT_TR 0x10UL 2491a9a457f3SSelvin Xavier #define CMDQ_MODIFY_ROCE_CC_MODIFY_MASK_TOS_ECN 0x20UL 2492a9a457f3SSelvin Xavier #define CMDQ_MODIFY_ROCE_CC_MODIFY_MASK_TOS_DSCP 0x40UL 2493a9a457f3SSelvin Xavier #define CMDQ_MODIFY_ROCE_CC_MODIFY_MASK_ALT_VLAN_PCP 0x80UL 2494a9a457f3SSelvin Xavier #define CMDQ_MODIFY_ROCE_CC_MODIFY_MASK_ALT_TOS_DSCP 0x100UL 2495a9a457f3SSelvin Xavier #define CMDQ_MODIFY_ROCE_CC_MODIFY_MASK_RTT 0x200UL 2496a9a457f3SSelvin Xavier #define CMDQ_MODIFY_ROCE_CC_MODIFY_MASK_CC_MODE 0x400UL 2497a9a457f3SSelvin Xavier #define CMDQ_MODIFY_ROCE_CC_MODIFY_MASK_TCP_CP 0x800UL 2498a9a457f3SSelvin Xavier #define CMDQ_MODIFY_ROCE_CC_MODIFY_MASK_TX_QUEUE 0x1000UL 2499a9a457f3SSelvin Xavier #define CMDQ_MODIFY_ROCE_CC_MODIFY_MASK_INACTIVITY_CP 0x2000UL 2500a9a457f3SSelvin Xavier #define CMDQ_MODIFY_ROCE_CC_MODIFY_MASK_TIME_PER_PHASE 0x4000UL 2501a9a457f3SSelvin Xavier #define CMDQ_MODIFY_ROCE_CC_MODIFY_MASK_PKTS_PER_PHASE 0x8000UL 2502a9a457f3SSelvin Xavier u8 enable_cc; 2503a9a457f3SSelvin Xavier #define CMDQ_MODIFY_ROCE_CC_ENABLE_CC 0x1UL 2504a9a457f3SSelvin Xavier #define CMDQ_MODIFY_ROCE_CC_RSVD1_MASK 0xfeUL 2505a9a457f3SSelvin Xavier #define CMDQ_MODIFY_ROCE_CC_RSVD1_SFT 1 2506a9a457f3SSelvin Xavier u8 g; 2507a9a457f3SSelvin Xavier u8 num_phases_per_state; 2508a9a457f3SSelvin Xavier u8 pkts_per_phase; 2509a9a457f3SSelvin Xavier __le16 init_cr; 2510a9a457f3SSelvin Xavier __le16 init_tr; 2511a9a457f3SSelvin Xavier u8 tos_dscp_tos_ecn; 2512a9a457f3SSelvin Xavier #define CMDQ_MODIFY_ROCE_CC_TOS_ECN_MASK 0x3UL 2513a9a457f3SSelvin Xavier #define CMDQ_MODIFY_ROCE_CC_TOS_ECN_SFT 0 2514a9a457f3SSelvin Xavier #define CMDQ_MODIFY_ROCE_CC_TOS_DSCP_MASK 0xfcUL 2515a9a457f3SSelvin Xavier #define CMDQ_MODIFY_ROCE_CC_TOS_DSCP_SFT 2 2516a9a457f3SSelvin Xavier u8 alt_vlan_pcp; 2517a9a457f3SSelvin Xavier #define CMDQ_MODIFY_ROCE_CC_ALT_VLAN_PCP_MASK 0x7UL 2518a9a457f3SSelvin Xavier #define CMDQ_MODIFY_ROCE_CC_ALT_VLAN_PCP_SFT 0 2519a9a457f3SSelvin Xavier #define CMDQ_MODIFY_ROCE_CC_RSVD3_MASK 0xf8UL 2520a9a457f3SSelvin Xavier #define CMDQ_MODIFY_ROCE_CC_RSVD3_SFT 3 2521a9a457f3SSelvin Xavier __le16 alt_tos_dscp; 2522a9a457f3SSelvin Xavier #define CMDQ_MODIFY_ROCE_CC_ALT_TOS_DSCP_MASK 0x3fUL 2523a9a457f3SSelvin Xavier #define CMDQ_MODIFY_ROCE_CC_ALT_TOS_DSCP_SFT 0 2524a9a457f3SSelvin Xavier #define CMDQ_MODIFY_ROCE_CC_RSVD4_MASK 0xffc0UL 2525a9a457f3SSelvin Xavier #define CMDQ_MODIFY_ROCE_CC_RSVD4_SFT 6 2526a9a457f3SSelvin Xavier __le16 rtt; 2527a9a457f3SSelvin Xavier #define CMDQ_MODIFY_ROCE_CC_RTT_MASK 0x3fffUL 2528a9a457f3SSelvin Xavier #define CMDQ_MODIFY_ROCE_CC_RTT_SFT 0 2529a9a457f3SSelvin Xavier #define CMDQ_MODIFY_ROCE_CC_RSVD5_MASK 0xc000UL 2530a9a457f3SSelvin Xavier #define CMDQ_MODIFY_ROCE_CC_RSVD5_SFT 14 2531a9a457f3SSelvin Xavier __le16 tcp_cp; 2532a9a457f3SSelvin Xavier #define CMDQ_MODIFY_ROCE_CC_TCP_CP_MASK 0x3ffUL 2533a9a457f3SSelvin Xavier #define CMDQ_MODIFY_ROCE_CC_TCP_CP_SFT 0 2534a9a457f3SSelvin Xavier #define CMDQ_MODIFY_ROCE_CC_RSVD6_MASK 0xfc00UL 2535a9a457f3SSelvin Xavier #define CMDQ_MODIFY_ROCE_CC_RSVD6_SFT 10 2536a9a457f3SSelvin Xavier u8 cc_mode; 2537a9a457f3SSelvin Xavier #define CMDQ_MODIFY_ROCE_CC_CC_MODE_DCTCP_CC_MODE 0x0UL 2538a9a457f3SSelvin Xavier #define CMDQ_MODIFY_ROCE_CC_CC_MODE_PROBABILISTIC_CC_MODE 0x1UL 2539a9a457f3SSelvin Xavier #define CMDQ_MODIFY_ROCE_CC_CC_MODE_LAST CMDQ_MODIFY_ROCE_CC_CC_MODE_PROBABILISTIC_CC_MODE 2540a9a457f3SSelvin Xavier u8 tx_queue; 2541a9a457f3SSelvin Xavier __le16 inactivity_th; 2542a9a457f3SSelvin Xavier u8 time_per_phase; 2543a9a457f3SSelvin Xavier u8 reserved8_1; 2544a9a457f3SSelvin Xavier __le16 reserved16; 2545a9a457f3SSelvin Xavier __le32 reserved32; 2546a9a457f3SSelvin Xavier __le64 reserved64; 2547a9a457f3SSelvin Xavier }; 2548a9a457f3SSelvin Xavier 2549a9a457f3SSelvin Xavier /* cmdq_modify_roce_cc_tlv (size:640b/80B) */ 2550a9a457f3SSelvin Xavier struct cmdq_modify_roce_cc_tlv { 2551a9a457f3SSelvin Xavier __le16 cmd_discr; 2552a9a457f3SSelvin Xavier u8 reserved_8b; 2553a9a457f3SSelvin Xavier u8 tlv_flags; 2554a9a457f3SSelvin Xavier #define CMDQ_MODIFY_ROCE_CC_TLV_TLV_FLAGS_MORE 0x1UL 2555a9a457f3SSelvin Xavier #define CMDQ_MODIFY_ROCE_CC_TLV_TLV_FLAGS_MORE_LAST 0x0UL 2556a9a457f3SSelvin Xavier #define CMDQ_MODIFY_ROCE_CC_TLV_TLV_FLAGS_MORE_NOT_LAST 0x1UL 2557a9a457f3SSelvin Xavier #define CMDQ_MODIFY_ROCE_CC_TLV_TLV_FLAGS_REQUIRED 0x2UL 2558a9a457f3SSelvin Xavier #define CMDQ_MODIFY_ROCE_CC_TLV_TLV_FLAGS_REQUIRED_NO (0x0UL << 1) 2559a9a457f3SSelvin Xavier #define CMDQ_MODIFY_ROCE_CC_TLV_TLV_FLAGS_REQUIRED_YES (0x1UL << 1) 2560a9a457f3SSelvin Xavier #define CMDQ_MODIFY_ROCE_CC_TLV_TLV_FLAGS_REQUIRED_LAST \ 2561a9a457f3SSelvin Xavier CMDQ_MODIFY_ROCE_CC_TLV_TLV_FLAGS_REQUIRED_YES 2562a9a457f3SSelvin Xavier __le16 tlv_type; 2563a9a457f3SSelvin Xavier __le16 length; 2564a9a457f3SSelvin Xavier u8 total_size; 2565a9a457f3SSelvin Xavier u8 reserved56[7]; 2566a9a457f3SSelvin Xavier u8 opcode; 2567a9a457f3SSelvin Xavier #define CMDQ_MODIFY_ROCE_CC_TLV_OPCODE_MODIFY_ROCE_CC 0x8cUL 2568a9a457f3SSelvin Xavier #define CMDQ_MODIFY_ROCE_CC_TLV_OPCODE_LAST CMDQ_MODIFY_ROCE_CC_TLV_OPCODE_MODIFY_ROCE_CC 2569a9a457f3SSelvin Xavier u8 cmd_size; 2570a9a457f3SSelvin Xavier __le16 flags; 2571a9a457f3SSelvin Xavier __le16 cookie; 2572a9a457f3SSelvin Xavier u8 resp_size; 2573a9a457f3SSelvin Xavier u8 reserved8; 2574a9a457f3SSelvin Xavier __le64 resp_addr; 2575a9a457f3SSelvin Xavier __le32 modify_mask; 2576a9a457f3SSelvin Xavier #define CMDQ_MODIFY_ROCE_CC_TLV_MODIFY_MASK_ENABLE_CC 0x1UL 2577a9a457f3SSelvin Xavier #define CMDQ_MODIFY_ROCE_CC_TLV_MODIFY_MASK_G 0x2UL 2578a9a457f3SSelvin Xavier #define CMDQ_MODIFY_ROCE_CC_TLV_MODIFY_MASK_NUMPHASEPERSTATE 0x4UL 2579a9a457f3SSelvin Xavier #define CMDQ_MODIFY_ROCE_CC_TLV_MODIFY_MASK_INIT_CR 0x8UL 2580a9a457f3SSelvin Xavier #define CMDQ_MODIFY_ROCE_CC_TLV_MODIFY_MASK_INIT_TR 0x10UL 2581a9a457f3SSelvin Xavier #define CMDQ_MODIFY_ROCE_CC_TLV_MODIFY_MASK_TOS_ECN 0x20UL 2582a9a457f3SSelvin Xavier #define CMDQ_MODIFY_ROCE_CC_TLV_MODIFY_MASK_TOS_DSCP 0x40UL 2583a9a457f3SSelvin Xavier #define CMDQ_MODIFY_ROCE_CC_TLV_MODIFY_MASK_ALT_VLAN_PCP 0x80UL 2584a9a457f3SSelvin Xavier #define CMDQ_MODIFY_ROCE_CC_TLV_MODIFY_MASK_ALT_TOS_DSCP 0x100UL 2585a9a457f3SSelvin Xavier #define CMDQ_MODIFY_ROCE_CC_TLV_MODIFY_MASK_RTT 0x200UL 2586a9a457f3SSelvin Xavier #define CMDQ_MODIFY_ROCE_CC_TLV_MODIFY_MASK_CC_MODE 0x400UL 2587a9a457f3SSelvin Xavier #define CMDQ_MODIFY_ROCE_CC_TLV_MODIFY_MASK_TCP_CP 0x800UL 2588a9a457f3SSelvin Xavier #define CMDQ_MODIFY_ROCE_CC_TLV_MODIFY_MASK_TX_QUEUE 0x1000UL 2589a9a457f3SSelvin Xavier #define CMDQ_MODIFY_ROCE_CC_TLV_MODIFY_MASK_INACTIVITY_CP 0x2000UL 2590a9a457f3SSelvin Xavier #define CMDQ_MODIFY_ROCE_CC_TLV_MODIFY_MASK_TIME_PER_PHASE 0x4000UL 2591a9a457f3SSelvin Xavier #define CMDQ_MODIFY_ROCE_CC_TLV_MODIFY_MASK_PKTS_PER_PHASE 0x8000UL 2592a9a457f3SSelvin Xavier u8 enable_cc; 2593a9a457f3SSelvin Xavier #define CMDQ_MODIFY_ROCE_CC_TLV_ENABLE_CC 0x1UL 2594a9a457f3SSelvin Xavier #define CMDQ_MODIFY_ROCE_CC_TLV_RSVD1_MASK 0xfeUL 2595a9a457f3SSelvin Xavier #define CMDQ_MODIFY_ROCE_CC_TLV_RSVD1_SFT 1 2596a9a457f3SSelvin Xavier u8 g; 2597a9a457f3SSelvin Xavier u8 num_phases_per_state; 2598a9a457f3SSelvin Xavier u8 pkts_per_phase; 2599a9a457f3SSelvin Xavier __le16 init_cr; 2600a9a457f3SSelvin Xavier __le16 init_tr; 2601a9a457f3SSelvin Xavier u8 tos_dscp_tos_ecn; 2602a9a457f3SSelvin Xavier #define CMDQ_MODIFY_ROCE_CC_TLV_TOS_ECN_MASK 0x3UL 2603a9a457f3SSelvin Xavier #define CMDQ_MODIFY_ROCE_CC_TLV_TOS_ECN_SFT 0 2604a9a457f3SSelvin Xavier #define CMDQ_MODIFY_ROCE_CC_TLV_TOS_DSCP_MASK 0xfcUL 2605a9a457f3SSelvin Xavier #define CMDQ_MODIFY_ROCE_CC_TLV_TOS_DSCP_SFT 2 2606a9a457f3SSelvin Xavier u8 alt_vlan_pcp; 2607a9a457f3SSelvin Xavier #define CMDQ_MODIFY_ROCE_CC_TLV_ALT_VLAN_PCP_MASK 0x7UL 2608a9a457f3SSelvin Xavier #define CMDQ_MODIFY_ROCE_CC_TLV_ALT_VLAN_PCP_SFT 0 2609a9a457f3SSelvin Xavier #define CMDQ_MODIFY_ROCE_CC_TLV_RSVD3_MASK 0xf8UL 2610a9a457f3SSelvin Xavier #define CMDQ_MODIFY_ROCE_CC_TLV_RSVD3_SFT 3 2611a9a457f3SSelvin Xavier __le16 alt_tos_dscp; 2612a9a457f3SSelvin Xavier #define CMDQ_MODIFY_ROCE_CC_TLV_ALT_TOS_DSCP_MASK 0x3fUL 2613a9a457f3SSelvin Xavier #define CMDQ_MODIFY_ROCE_CC_TLV_ALT_TOS_DSCP_SFT 0 2614a9a457f3SSelvin Xavier #define CMDQ_MODIFY_ROCE_CC_TLV_RSVD4_MASK 0xffc0UL 2615a9a457f3SSelvin Xavier #define CMDQ_MODIFY_ROCE_CC_TLV_RSVD4_SFT 6 2616a9a457f3SSelvin Xavier __le16 rtt; 2617a9a457f3SSelvin Xavier #define CMDQ_MODIFY_ROCE_CC_TLV_RTT_MASK 0x3fffUL 2618a9a457f3SSelvin Xavier #define CMDQ_MODIFY_ROCE_CC_TLV_RTT_SFT 0 2619a9a457f3SSelvin Xavier #define CMDQ_MODIFY_ROCE_CC_TLV_RSVD5_MASK 0xc000UL 2620a9a457f3SSelvin Xavier #define CMDQ_MODIFY_ROCE_CC_TLV_RSVD5_SFT 14 2621a9a457f3SSelvin Xavier __le16 tcp_cp; 2622a9a457f3SSelvin Xavier #define CMDQ_MODIFY_ROCE_CC_TLV_TCP_CP_MASK 0x3ffUL 2623a9a457f3SSelvin Xavier #define CMDQ_MODIFY_ROCE_CC_TLV_TCP_CP_SFT 0 2624a9a457f3SSelvin Xavier #define CMDQ_MODIFY_ROCE_CC_TLV_RSVD6_MASK 0xfc00UL 2625a9a457f3SSelvin Xavier #define CMDQ_MODIFY_ROCE_CC_TLV_RSVD6_SFT 10 2626a9a457f3SSelvin Xavier u8 cc_mode; 2627a9a457f3SSelvin Xavier #define CMDQ_MODIFY_ROCE_CC_TLV_CC_MODE_DCTCP_CC_MODE 0x0UL 2628a9a457f3SSelvin Xavier #define CMDQ_MODIFY_ROCE_CC_TLV_CC_MODE_PROBABILISTIC_CC_MODE 0x1UL 2629a9a457f3SSelvin Xavier #define CMDQ_MODIFY_ROCE_CC_TLV_CC_MODE_LAST\ 2630a9a457f3SSelvin Xavier CMDQ_MODIFY_ROCE_CC_TLV_CC_MODE_PROBABILISTIC_CC_MODE 2631a9a457f3SSelvin Xavier u8 tx_queue; 2632a9a457f3SSelvin Xavier __le16 inactivity_th; 2633a9a457f3SSelvin Xavier u8 time_per_phase; 2634a9a457f3SSelvin Xavier u8 reserved8_1; 2635a9a457f3SSelvin Xavier __le16 reserved16; 2636a9a457f3SSelvin Xavier __le32 reserved32; 2637a9a457f3SSelvin Xavier __le64 reserved64; 2638a9a457f3SSelvin Xavier __le64 reservedtlvpad; 2639a9a457f3SSelvin Xavier }; 2640a9a457f3SSelvin Xavier 2641a9a457f3SSelvin Xavier /* cmdq_modify_roce_cc_gen1_tlv (size:768b/96B) */ 2642a9a457f3SSelvin Xavier struct cmdq_modify_roce_cc_gen1_tlv { 2643a9a457f3SSelvin Xavier __le16 cmd_discr; 2644a9a457f3SSelvin Xavier u8 reserved_8b; 2645a9a457f3SSelvin Xavier u8 tlv_flags; 2646a9a457f3SSelvin Xavier #define CMDQ_MODIFY_ROCE_CC_GEN1_TLV_TLV_FLAGS_MORE 0x1UL 2647a9a457f3SSelvin Xavier #define CMDQ_MODIFY_ROCE_CC_GEN1_TLV_TLV_FLAGS_MORE_LAST 0x0UL 2648a9a457f3SSelvin Xavier #define CMDQ_MODIFY_ROCE_CC_GEN1_TLV_TLV_FLAGS_MORE_NOT_LAST 0x1UL 2649a9a457f3SSelvin Xavier #define CMDQ_MODIFY_ROCE_CC_GEN1_TLV_TLV_FLAGS_REQUIRED 0x2UL 2650a9a457f3SSelvin Xavier #define CMDQ_MODIFY_ROCE_CC_GEN1_TLV_TLV_FLAGS_REQUIRED_NO (0x0UL << 1) 2651a9a457f3SSelvin Xavier #define CMDQ_MODIFY_ROCE_CC_GEN1_TLV_TLV_FLAGS_REQUIRED_YES (0x1UL << 1) 2652a9a457f3SSelvin Xavier #define CMDQ_MODIFY_ROCE_CC_GEN1_TLV_TLV_FLAGS_REQUIRED_LAST\ 2653a9a457f3SSelvin Xavier CMDQ_MODIFY_ROCE_CC_GEN1_TLV_TLV_FLAGS_REQUIRED_YES 2654a9a457f3SSelvin Xavier __le16 tlv_type; 2655a9a457f3SSelvin Xavier __le16 length; 2656a9a457f3SSelvin Xavier __le64 reserved64; 2657a9a457f3SSelvin Xavier __le64 modify_mask; 2658a9a457f3SSelvin Xavier #define CMDQ_MODIFY_ROCE_CC_GEN1_TLV_MODIFY_MASK_MIN_TIME_BETWEEN_CNPS 0x1UL 2659a9a457f3SSelvin Xavier #define CMDQ_MODIFY_ROCE_CC_GEN1_TLV_MODIFY_MASK_INIT_CP 0x2UL 2660a9a457f3SSelvin Xavier #define CMDQ_MODIFY_ROCE_CC_GEN1_TLV_MODIFY_MASK_TR_UPDATE_MODE 0x4UL 2661a9a457f3SSelvin Xavier #define CMDQ_MODIFY_ROCE_CC_GEN1_TLV_MODIFY_MASK_TR_UPDATE_CYCLES 0x8UL 2662a9a457f3SSelvin Xavier #define CMDQ_MODIFY_ROCE_CC_GEN1_TLV_MODIFY_MASK_FR_NUM_RTTS 0x10UL 2663a9a457f3SSelvin Xavier #define CMDQ_MODIFY_ROCE_CC_GEN1_TLV_MODIFY_MASK_AI_RATE_INCREASE 0x20UL 2664a9a457f3SSelvin Xavier #define CMDQ_MODIFY_ROCE_CC_GEN1_TLV_MODIFY_MASK_REDUCTION_RELAX_RTTS_TH 0x40UL 2665a9a457f3SSelvin Xavier #define CMDQ_MODIFY_ROCE_CC_GEN1_TLV_MODIFY_MASK_ADDITIONAL_RELAX_CR_TH 0x80UL 2666a9a457f3SSelvin Xavier #define CMDQ_MODIFY_ROCE_CC_GEN1_TLV_MODIFY_MASK_CR_MIN_TH 0x100UL 2667a9a457f3SSelvin Xavier #define CMDQ_MODIFY_ROCE_CC_GEN1_TLV_MODIFY_MASK_BW_AVG_WEIGHT 0x200UL 2668a9a457f3SSelvin Xavier #define CMDQ_MODIFY_ROCE_CC_GEN1_TLV_MODIFY_MASK_ACTUAL_CR_FACTOR 0x400UL 2669a9a457f3SSelvin Xavier #define CMDQ_MODIFY_ROCE_CC_GEN1_TLV_MODIFY_MASK_MAX_CP_CR_TH 0x800UL 2670a9a457f3SSelvin Xavier #define CMDQ_MODIFY_ROCE_CC_GEN1_TLV_MODIFY_MASK_CP_BIAS_EN 0x1000UL 2671a9a457f3SSelvin Xavier #define CMDQ_MODIFY_ROCE_CC_GEN1_TLV_MODIFY_MASK_CP_BIAS 0x2000UL 2672a9a457f3SSelvin Xavier #define CMDQ_MODIFY_ROCE_CC_GEN1_TLV_MODIFY_MASK_CNP_ECN 0x4000UL 2673a9a457f3SSelvin Xavier #define CMDQ_MODIFY_ROCE_CC_GEN1_TLV_MODIFY_MASK_RTT_JITTER_EN 0x8000UL 2674a9a457f3SSelvin Xavier #define CMDQ_MODIFY_ROCE_CC_GEN1_TLV_MODIFY_MASK_LINK_BYTES_PER_USEC 0x10000UL 2675a9a457f3SSelvin Xavier #define CMDQ_MODIFY_ROCE_CC_GEN1_TLV_MODIFY_MASK_RESET_CC_CR_TH 0x20000UL 2676a9a457f3SSelvin Xavier #define CMDQ_MODIFY_ROCE_CC_GEN1_TLV_MODIFY_MASK_CR_WIDTH 0x40000UL 2677a9a457f3SSelvin Xavier #define CMDQ_MODIFY_ROCE_CC_GEN1_TLV_MODIFY_MASK_QUOTA_PERIOD_MIN 0x80000UL 2678a9a457f3SSelvin Xavier #define CMDQ_MODIFY_ROCE_CC_GEN1_TLV_MODIFY_MASK_QUOTA_PERIOD_MAX 0x100000UL 2679a9a457f3SSelvin Xavier #define CMDQ_MODIFY_ROCE_CC_GEN1_TLV_MODIFY_MASK_QUOTA_PERIOD_ABS_MAX 0x200000UL 2680a9a457f3SSelvin Xavier #define CMDQ_MODIFY_ROCE_CC_GEN1_TLV_MODIFY_MASK_TR_LOWER_BOUND 0x400000UL 2681a9a457f3SSelvin Xavier #define CMDQ_MODIFY_ROCE_CC_GEN1_TLV_MODIFY_MASK_CR_PROB_FACTOR 0x800000UL 2682a9a457f3SSelvin Xavier #define CMDQ_MODIFY_ROCE_CC_GEN1_TLV_MODIFY_MASK_TR_PROB_FACTOR 0x1000000UL 2683a9a457f3SSelvin Xavier #define CMDQ_MODIFY_ROCE_CC_GEN1_TLV_MODIFY_MASK_FAIRNESS_CR_TH 0x2000000UL 2684a9a457f3SSelvin Xavier #define CMDQ_MODIFY_ROCE_CC_GEN1_TLV_MODIFY_MASK_RED_DIV 0x4000000UL 2685a9a457f3SSelvin Xavier #define CMDQ_MODIFY_ROCE_CC_GEN1_TLV_MODIFY_MASK_CNP_RATIO_TH 0x8000000UL 2686a9a457f3SSelvin Xavier #define CMDQ_MODIFY_ROCE_CC_GEN1_TLV_MODIFY_MASK_EXP_AI_RTTS 0x10000000UL 2687a9a457f3SSelvin Xavier #define CMDQ_MODIFY_ROCE_CC_GEN1_TLV_MODIFY_MASK_EXP_AI_CR_CP_RATIO 0x20000000UL 2688a9a457f3SSelvin Xavier #define CMDQ_MODIFY_ROCE_CC_GEN1_TLV_MODIFY_MASK_CP_EXP_UPDATE_TH 0x40000000UL 2689a9a457f3SSelvin Xavier #define CMDQ_MODIFY_ROCE_CC_GEN1_TLV_MODIFY_MASK_HIGH_EXP_AI_RTTS_TH1 0x80000000UL 2690a9a457f3SSelvin Xavier #define CMDQ_MODIFY_ROCE_CC_GEN1_TLV_MODIFY_MASK_HIGH_EXP_AI_RTTS_TH2 0x100000000ULL 2691a9a457f3SSelvin Xavier #define CMDQ_MODIFY_ROCE_CC_GEN1_TLV_MODIFY_MASK_USE_RATE_TABLE 0x200000000ULL 2692a9a457f3SSelvin Xavier #define CMDQ_MODIFY_ROCE_CC_GEN1_TLV_MODIFY_MASK_LINK64B_PER_RTT 0x400000000ULL 2693a9a457f3SSelvin Xavier #define CMDQ_MODIFY_ROCE_CC_GEN1_TLV_MODIFY_MASK_ACTUAL_CR_CONG_FREE_RTTS_TH 0x800000000ULL 2694a9a457f3SSelvin Xavier #define CMDQ_MODIFY_ROCE_CC_GEN1_TLV_MODIFY_MASK_SEVERE_CONG_CR_TH1 0x1000000000ULL 2695a9a457f3SSelvin Xavier #define CMDQ_MODIFY_ROCE_CC_GEN1_TLV_MODIFY_MASK_SEVERE_CONG_CR_TH2 0x2000000000ULL 2696a9a457f3SSelvin Xavier #define CMDQ_MODIFY_ROCE_CC_GEN1_TLV_MODIFY_MASK_CC_ACK_BYTES 0x4000000000ULL 2697a9a457f3SSelvin Xavier #define CMDQ_MODIFY_ROCE_CC_GEN1_TLV_MODIFY_MASK_REDUCE_INIT_EN 0x8000000000ULL 2698a9a457f3SSelvin Xavier #define CMDQ_MODIFY_ROCE_CC_GEN1_TLV_MODIFY_MASK_REDUCE_INIT_CONG_FREE_RTTS_TH \ 2699a9a457f3SSelvin Xavier 0x10000000000ULL 2700a9a457f3SSelvin Xavier #define CMDQ_MODIFY_ROCE_CC_GEN1_TLV_MODIFY_MASK_RANDOM_NO_RED_EN 0x20000000000ULL 2701a9a457f3SSelvin Xavier #define CMDQ_MODIFY_ROCE_CC_GEN1_TLV_MODIFY_MASK_ACTUAL_CR_SHIFT_CORRECTION_EN \ 2702a9a457f3SSelvin Xavier 0x40000000000ULL 2703a9a457f3SSelvin Xavier #define CMDQ_MODIFY_ROCE_CC_GEN1_TLV_MODIFY_MASK_QUOTA_PERIOD_ADJUST_EN 0x80000000000ULL 2704a9a457f3SSelvin Xavier __le16 inactivity_th_hi; 2705a9a457f3SSelvin Xavier __le16 min_time_between_cnps; 2706a9a457f3SSelvin Xavier __le16 init_cp; 2707a9a457f3SSelvin Xavier u8 tr_update_mode; 2708a9a457f3SSelvin Xavier u8 tr_update_cycles; 2709a9a457f3SSelvin Xavier u8 fr_num_rtts; 2710a9a457f3SSelvin Xavier u8 ai_rate_increase; 2711a9a457f3SSelvin Xavier __le16 reduction_relax_rtts_th; 2712a9a457f3SSelvin Xavier __le16 additional_relax_cr_th; 2713a9a457f3SSelvin Xavier __le16 cr_min_th; 2714a9a457f3SSelvin Xavier u8 bw_avg_weight; 2715a9a457f3SSelvin Xavier u8 actual_cr_factor; 2716a9a457f3SSelvin Xavier __le16 max_cp_cr_th; 2717a9a457f3SSelvin Xavier u8 cp_bias_en; 2718a9a457f3SSelvin Xavier u8 cp_bias; 2719a9a457f3SSelvin Xavier u8 cnp_ecn; 2720a9a457f3SSelvin Xavier #define CMDQ_MODIFY_ROCE_CC_GEN1_TLV_CNP_ECN_NOT_ECT 0x0UL 2721a9a457f3SSelvin Xavier #define CMDQ_MODIFY_ROCE_CC_GEN1_TLV_CNP_ECN_ECT_1 0x1UL 2722a9a457f3SSelvin Xavier #define CMDQ_MODIFY_ROCE_CC_GEN1_TLV_CNP_ECN_ECT_0 0x2UL 2723a9a457f3SSelvin Xavier #define CMDQ_MODIFY_ROCE_CC_GEN1_TLV_CNP_ECN_LAST CMDQ_MODIFY_ROCE_CC_GEN1_TLV_CNP_ECN_ECT_0 2724a9a457f3SSelvin Xavier u8 rtt_jitter_en; 2725a9a457f3SSelvin Xavier __le16 link_bytes_per_usec; 2726a9a457f3SSelvin Xavier __le16 reset_cc_cr_th; 2727a9a457f3SSelvin Xavier u8 cr_width; 2728a9a457f3SSelvin Xavier u8 quota_period_min; 2729a9a457f3SSelvin Xavier u8 quota_period_max; 2730a9a457f3SSelvin Xavier u8 quota_period_abs_max; 2731a9a457f3SSelvin Xavier __le16 tr_lower_bound; 2732a9a457f3SSelvin Xavier u8 cr_prob_factor; 2733a9a457f3SSelvin Xavier u8 tr_prob_factor; 2734a9a457f3SSelvin Xavier __le16 fairness_cr_th; 2735a9a457f3SSelvin Xavier u8 red_div; 2736a9a457f3SSelvin Xavier u8 cnp_ratio_th; 2737a9a457f3SSelvin Xavier __le16 exp_ai_rtts; 2738a9a457f3SSelvin Xavier u8 exp_ai_cr_cp_ratio; 2739a9a457f3SSelvin Xavier u8 use_rate_table; 2740a9a457f3SSelvin Xavier __le16 cp_exp_update_th; 2741a9a457f3SSelvin Xavier __le16 high_exp_ai_rtts_th1; 2742a9a457f3SSelvin Xavier __le16 high_exp_ai_rtts_th2; 2743a9a457f3SSelvin Xavier __le16 actual_cr_cong_free_rtts_th; 2744a9a457f3SSelvin Xavier __le16 severe_cong_cr_th1; 2745a9a457f3SSelvin Xavier __le16 severe_cong_cr_th2; 2746a9a457f3SSelvin Xavier __le32 link64B_per_rtt; 2747a9a457f3SSelvin Xavier u8 cc_ack_bytes; 2748a9a457f3SSelvin Xavier u8 reduce_init_en; 2749a9a457f3SSelvin Xavier __le16 reduce_init_cong_free_rtts_th; 2750a9a457f3SSelvin Xavier u8 random_no_red_en; 2751a9a457f3SSelvin Xavier u8 actual_cr_shift_correction_en; 2752a9a457f3SSelvin Xavier u8 quota_period_adjust_en; 2753a9a457f3SSelvin Xavier u8 reserved[5]; 2754a9a457f3SSelvin Xavier }; 2755a9a457f3SSelvin Xavier 2756a9a457f3SSelvin Xavier /* creq_modify_roce_cc_resp (size:128b/16B) */ 2757a9a457f3SSelvin Xavier struct creq_modify_roce_cc_resp { 2758a9a457f3SSelvin Xavier u8 type; 2759a9a457f3SSelvin Xavier #define CREQ_MODIFY_ROCE_CC_RESP_TYPE_MASK 0x3fUL 2760a9a457f3SSelvin Xavier #define CREQ_MODIFY_ROCE_CC_RESP_TYPE_SFT 0 2761a9a457f3SSelvin Xavier #define CREQ_MODIFY_ROCE_CC_RESP_TYPE_QP_EVENT 0x38UL 2762a9a457f3SSelvin Xavier #define CREQ_MODIFY_ROCE_CC_RESP_TYPE_LAST CREQ_MODIFY_ROCE_CC_RESP_TYPE_QP_EVENT 2763a9a457f3SSelvin Xavier u8 status; 2764a9a457f3SSelvin Xavier __le16 cookie; 2765a9a457f3SSelvin Xavier __le32 reserved32; 2766a9a457f3SSelvin Xavier u8 v; 2767a9a457f3SSelvin Xavier #define CREQ_MODIFY_ROCE_CC_RESP_V 0x1UL 2768a9a457f3SSelvin Xavier u8 event; 2769a9a457f3SSelvin Xavier #define CREQ_MODIFY_ROCE_CC_RESP_EVENT_MODIFY_ROCE_CC 0x8cUL 2770a9a457f3SSelvin Xavier #define CREQ_MODIFY_ROCE_CC_RESP_EVENT_LAST CREQ_MODIFY_ROCE_CC_RESP_EVENT_MODIFY_ROCE_CC 2771a9a457f3SSelvin Xavier u8 reserved48[6]; 2772a9a457f3SSelvin Xavier }; 2773a9a457f3SSelvin Xavier 2774a9a457f3SSelvin Xavier /* cmdq_set_link_aggr_mode_cc (size:320b/40B) */ 2775a9a457f3SSelvin Xavier struct cmdq_set_link_aggr_mode_cc { 2776a9a457f3SSelvin Xavier u8 opcode; 2777a9a457f3SSelvin Xavier #define CMDQ_SET_LINK_AGGR_MODE_OPCODE_SET_LINK_AGGR_MODE 0x8fUL 2778a9a457f3SSelvin Xavier #define CMDQ_SET_LINK_AGGR_MODE_OPCODE_LAST \ 2779a9a457f3SSelvin Xavier CMDQ_SET_LINK_AGGR_MODE_OPCODE_SET_LINK_AGGR_MODE 2780a9a457f3SSelvin Xavier u8 cmd_size; 2781a9a457f3SSelvin Xavier __le16 flags; 2782a9a457f3SSelvin Xavier __le16 cookie; 2783a9a457f3SSelvin Xavier u8 resp_size; 2784a9a457f3SSelvin Xavier u8 reserved8; 2785a9a457f3SSelvin Xavier __le64 resp_addr; 2786a9a457f3SSelvin Xavier __le32 modify_mask; 2787a9a457f3SSelvin Xavier #define CMDQ_SET_LINK_AGGR_MODE_MODIFY_MASK_AGGR_EN 0x1UL 2788a9a457f3SSelvin Xavier #define CMDQ_SET_LINK_AGGR_MODE_MODIFY_MASK_ACTIVE_PORT_MAP 0x2UL 2789a9a457f3SSelvin Xavier #define CMDQ_SET_LINK_AGGR_MODE_MODIFY_MASK_MEMBER_PORT_MAP 0x4UL 2790a9a457f3SSelvin Xavier #define CMDQ_SET_LINK_AGGR_MODE_MODIFY_MASK_AGGR_MODE 0x8UL 2791a9a457f3SSelvin Xavier #define CMDQ_SET_LINK_AGGR_MODE_MODIFY_MASK_STAT_CTX_ID 0x10UL 2792a9a457f3SSelvin Xavier u8 aggr_enable; 2793a9a457f3SSelvin Xavier #define CMDQ_SET_LINK_AGGR_MODE_AGGR_ENABLE 0x1UL 2794a9a457f3SSelvin Xavier #define CMDQ_SET_LINK_AGGR_MODE_RSVD1_MASK 0xfeUL 2795a9a457f3SSelvin Xavier #define CMDQ_SET_LINK_AGGR_MODE_RSVD1_SFT 1 2796a9a457f3SSelvin Xavier u8 active_port_map; 2797a9a457f3SSelvin Xavier #define CMDQ_SET_LINK_AGGR_MODE_ACTIVE_PORT_MAP_MASK 0xfUL 2798a9a457f3SSelvin Xavier #define CMDQ_SET_LINK_AGGR_MODE_ACTIVE_PORT_MAP_SFT 0 2799a9a457f3SSelvin Xavier #define CMDQ_SET_LINK_AGGR_MODE_RSVD2_MASK 0xf0UL 2800a9a457f3SSelvin Xavier #define CMDQ_SET_LINK_AGGR_MODE_RSVD2_SFT 4 2801a9a457f3SSelvin Xavier u8 member_port_map; 2802a9a457f3SSelvin Xavier u8 link_aggr_mode; 2803a9a457f3SSelvin Xavier #define CMDQ_SET_LINK_AGGR_MODE_AGGR_MODE_ACTIVE_ACTIVE 0x1UL 2804a9a457f3SSelvin Xavier #define CMDQ_SET_LINK_AGGR_MODE_AGGR_MODE_ACTIVE_BACKUP 0x2UL 2805a9a457f3SSelvin Xavier #define CMDQ_SET_LINK_AGGR_MODE_AGGR_MODE_BALANCE_XOR 0x3UL 2806a9a457f3SSelvin Xavier #define CMDQ_SET_LINK_AGGR_MODE_AGGR_MODE_802_3_AD 0x4UL 2807a9a457f3SSelvin Xavier #define CMDQ_SET_LINK_AGGR_MODE_AGGR_MODE_LAST CMDQ_SET_LINK_AGGR_MODE_AGGR_MODE_802_3_AD 2808a9a457f3SSelvin Xavier __le16 stat_ctx_id[4]; 2809a9a457f3SSelvin Xavier __le64 rsvd1; 2810a9a457f3SSelvin Xavier }; 2811a9a457f3SSelvin Xavier 2812a9a457f3SSelvin Xavier /* creq_set_link_aggr_mode_resources_resp (size:128b/16B) */ 2813a9a457f3SSelvin Xavier struct creq_set_link_aggr_mode_resources_resp { 2814a9a457f3SSelvin Xavier u8 type; 2815a9a457f3SSelvin Xavier #define CREQ_SET_LINK_AGGR_MODE_RESP_TYPE_MASK 0x3fUL 2816a9a457f3SSelvin Xavier #define CREQ_SET_LINK_AGGR_MODE_RESP_TYPE_SFT 0 2817a9a457f3SSelvin Xavier #define CREQ_SET_LINK_AGGR_MODE_RESP_TYPE_QP_EVENT 0x38UL 2818a9a457f3SSelvin Xavier #define CREQ_SET_LINK_AGGR_MODE_RESP_TYPE_LAST CREQ_SET_LINK_AGGR_MODE_RESP_TYPE_QP_EVENT 2819a9a457f3SSelvin Xavier u8 status; 2820a9a457f3SSelvin Xavier __le16 cookie; 2821a9a457f3SSelvin Xavier __le32 reserved32; 2822a9a457f3SSelvin Xavier u8 v; 2823a9a457f3SSelvin Xavier #define CREQ_SET_LINK_AGGR_MODE_RESP_V 0x1UL 2824a9a457f3SSelvin Xavier u8 event; 2825a9a457f3SSelvin Xavier #define CREQ_SET_LINK_AGGR_MODE_RESP_EVENT_SET_LINK_AGGR_MODE 0x8fUL 2826a9a457f3SSelvin Xavier #define CREQ_SET_LINK_AGGR_MODE_RESP_EVENT_LAST\ 2827a9a457f3SSelvin Xavier CREQ_SET_LINK_AGGR_MODE_RESP_EVENT_SET_LINK_AGGR_MODE 2828a9a457f3SSelvin Xavier u8 reserved48[6]; 2829a9a457f3SSelvin Xavier }; 2830a9a457f3SSelvin Xavier 2831a9a457f3SSelvin Xavier /* creq_func_event (size:128b/16B) */ 2832a9a457f3SSelvin Xavier struct creq_func_event { 2833a9a457f3SSelvin Xavier u8 type; 2834a9a457f3SSelvin Xavier #define CREQ_FUNC_EVENT_TYPE_MASK 0x3fUL 2835a9a457f3SSelvin Xavier #define CREQ_FUNC_EVENT_TYPE_SFT 0 2836a9a457f3SSelvin Xavier #define CREQ_FUNC_EVENT_TYPE_FUNC_EVENT 0x3aUL 2837a9a457f3SSelvin Xavier #define CREQ_FUNC_EVENT_TYPE_LAST CREQ_FUNC_EVENT_TYPE_FUNC_EVENT 2838a9a457f3SSelvin Xavier u8 reserved56[7]; 2839a9a457f3SSelvin Xavier u8 v; 2840a9a457f3SSelvin Xavier #define CREQ_FUNC_EVENT_V 0x1UL 2841a9a457f3SSelvin Xavier u8 event; 2842a9a457f3SSelvin Xavier #define CREQ_FUNC_EVENT_EVENT_TX_WQE_ERROR 0x1UL 2843a9a457f3SSelvin Xavier #define CREQ_FUNC_EVENT_EVENT_TX_DATA_ERROR 0x2UL 2844a9a457f3SSelvin Xavier #define CREQ_FUNC_EVENT_EVENT_RX_WQE_ERROR 0x3UL 2845a9a457f3SSelvin Xavier #define CREQ_FUNC_EVENT_EVENT_RX_DATA_ERROR 0x4UL 2846a9a457f3SSelvin Xavier #define CREQ_FUNC_EVENT_EVENT_CQ_ERROR 0x5UL 2847a9a457f3SSelvin Xavier #define CREQ_FUNC_EVENT_EVENT_TQM_ERROR 0x6UL 2848a9a457f3SSelvin Xavier #define CREQ_FUNC_EVENT_EVENT_CFCQ_ERROR 0x7UL 2849a9a457f3SSelvin Xavier #define CREQ_FUNC_EVENT_EVENT_CFCS_ERROR 0x8UL 2850a9a457f3SSelvin Xavier #define CREQ_FUNC_EVENT_EVENT_CFCC_ERROR 0x9UL 2851a9a457f3SSelvin Xavier #define CREQ_FUNC_EVENT_EVENT_CFCM_ERROR 0xaUL 2852a9a457f3SSelvin Xavier #define CREQ_FUNC_EVENT_EVENT_TIM_ERROR 0xbUL 2853a9a457f3SSelvin Xavier #define CREQ_FUNC_EVENT_EVENT_VF_COMM_REQUEST 0x80UL 2854a9a457f3SSelvin Xavier #define CREQ_FUNC_EVENT_EVENT_RESOURCE_EXHAUSTED 0x81UL 2855a9a457f3SSelvin Xavier #define CREQ_FUNC_EVENT_EVENT_LAST CREQ_FUNC_EVENT_EVENT_RESOURCE_EXHAUSTED 2856a9a457f3SSelvin Xavier u8 reserved48[6]; 2857a9a457f3SSelvin Xavier }; 2858a9a457f3SSelvin Xavier 2859a9a457f3SSelvin Xavier /* creq_qp_event (size:128b/16B) */ 2860a9a457f3SSelvin Xavier struct creq_qp_event { 2861a9a457f3SSelvin Xavier u8 type; 2862a9a457f3SSelvin Xavier #define CREQ_QP_EVENT_TYPE_MASK 0x3fUL 2863a9a457f3SSelvin Xavier #define CREQ_QP_EVENT_TYPE_SFT 0 2864a9a457f3SSelvin Xavier #define CREQ_QP_EVENT_TYPE_QP_EVENT 0x38UL 2865a9a457f3SSelvin Xavier #define CREQ_QP_EVENT_TYPE_LAST CREQ_QP_EVENT_TYPE_QP_EVENT 2866a9a457f3SSelvin Xavier u8 status; 2867a9a457f3SSelvin Xavier #define CREQ_QP_EVENT_STATUS_SUCCESS 0x0UL 2868a9a457f3SSelvin Xavier #define CREQ_QP_EVENT_STATUS_FAIL 0x1UL 2869a9a457f3SSelvin Xavier #define CREQ_QP_EVENT_STATUS_RESOURCES 0x2UL 2870a9a457f3SSelvin Xavier #define CREQ_QP_EVENT_STATUS_INVALID_CMD 0x3UL 2871a9a457f3SSelvin Xavier #define CREQ_QP_EVENT_STATUS_NOT_IMPLEMENTED 0x4UL 2872a9a457f3SSelvin Xavier #define CREQ_QP_EVENT_STATUS_INVALID_PARAMETER 0x5UL 2873a9a457f3SSelvin Xavier #define CREQ_QP_EVENT_STATUS_HARDWARE_ERROR 0x6UL 2874a9a457f3SSelvin Xavier #define CREQ_QP_EVENT_STATUS_INTERNAL_ERROR 0x7UL 2875a9a457f3SSelvin Xavier #define CREQ_QP_EVENT_STATUS_LAST CREQ_QP_EVENT_STATUS_INTERNAL_ERROR 2876a9a457f3SSelvin Xavier __le16 cookie; 2877a9a457f3SSelvin Xavier __le32 reserved32; 2878a9a457f3SSelvin Xavier u8 v; 2879a9a457f3SSelvin Xavier #define CREQ_QP_EVENT_V 0x1UL 2880a9a457f3SSelvin Xavier u8 event; 2881a9a457f3SSelvin Xavier #define CREQ_QP_EVENT_EVENT_CREATE_QP 0x1UL 2882a9a457f3SSelvin Xavier #define CREQ_QP_EVENT_EVENT_DESTROY_QP 0x2UL 2883a9a457f3SSelvin Xavier #define CREQ_QP_EVENT_EVENT_MODIFY_QP 0x3UL 2884a9a457f3SSelvin Xavier #define CREQ_QP_EVENT_EVENT_QUERY_QP 0x4UL 2885a9a457f3SSelvin Xavier #define CREQ_QP_EVENT_EVENT_CREATE_SRQ 0x5UL 2886a9a457f3SSelvin Xavier #define CREQ_QP_EVENT_EVENT_DESTROY_SRQ 0x6UL 2887a9a457f3SSelvin Xavier #define CREQ_QP_EVENT_EVENT_QUERY_SRQ 0x8UL 2888a9a457f3SSelvin Xavier #define CREQ_QP_EVENT_EVENT_CREATE_CQ 0x9UL 2889a9a457f3SSelvin Xavier #define CREQ_QP_EVENT_EVENT_DESTROY_CQ 0xaUL 2890a9a457f3SSelvin Xavier #define CREQ_QP_EVENT_EVENT_RESIZE_CQ 0xcUL 2891a9a457f3SSelvin Xavier #define CREQ_QP_EVENT_EVENT_ALLOCATE_MRW 0xdUL 2892a9a457f3SSelvin Xavier #define CREQ_QP_EVENT_EVENT_DEALLOCATE_KEY 0xeUL 2893a9a457f3SSelvin Xavier #define CREQ_QP_EVENT_EVENT_REGISTER_MR 0xfUL 2894a9a457f3SSelvin Xavier #define CREQ_QP_EVENT_EVENT_DEREGISTER_MR 0x10UL 2895a9a457f3SSelvin Xavier #define CREQ_QP_EVENT_EVENT_ADD_GID 0x11UL 2896a9a457f3SSelvin Xavier #define CREQ_QP_EVENT_EVENT_DELETE_GID 0x12UL 2897a9a457f3SSelvin Xavier #define CREQ_QP_EVENT_EVENT_MODIFY_GID 0x17UL 2898a9a457f3SSelvin Xavier #define CREQ_QP_EVENT_EVENT_QUERY_GID 0x18UL 2899a9a457f3SSelvin Xavier #define CREQ_QP_EVENT_EVENT_CREATE_QP1 0x13UL 2900a9a457f3SSelvin Xavier #define CREQ_QP_EVENT_EVENT_DESTROY_QP1 0x14UL 2901a9a457f3SSelvin Xavier #define CREQ_QP_EVENT_EVENT_CREATE_AH 0x15UL 2902a9a457f3SSelvin Xavier #define CREQ_QP_EVENT_EVENT_DESTROY_AH 0x16UL 2903a9a457f3SSelvin Xavier #define CREQ_QP_EVENT_EVENT_INITIALIZE_FW 0x80UL 2904a9a457f3SSelvin Xavier #define CREQ_QP_EVENT_EVENT_DEINITIALIZE_FW 0x81UL 2905a9a457f3SSelvin Xavier #define CREQ_QP_EVENT_EVENT_STOP_FUNC 0x82UL 2906a9a457f3SSelvin Xavier #define CREQ_QP_EVENT_EVENT_QUERY_FUNC 0x83UL 2907a9a457f3SSelvin Xavier #define CREQ_QP_EVENT_EVENT_SET_FUNC_RESOURCES 0x84UL 2908a9a457f3SSelvin Xavier #define CREQ_QP_EVENT_EVENT_READ_CONTEXT 0x85UL 2909a9a457f3SSelvin Xavier #define CREQ_QP_EVENT_EVENT_MAP_TC_TO_COS 0x8aUL 2910a9a457f3SSelvin Xavier #define CREQ_QP_EVENT_EVENT_QUERY_VERSION 0x8bUL 2911a9a457f3SSelvin Xavier #define CREQ_QP_EVENT_EVENT_MODIFY_CC 0x8cUL 2912a9a457f3SSelvin Xavier #define CREQ_QP_EVENT_EVENT_QUERY_CC 0x8dUL 2913a9a457f3SSelvin Xavier #define CREQ_QP_EVENT_EVENT_QUERY_ROCE_STATS 0x8eUL 2914a9a457f3SSelvin Xavier #define CREQ_QP_EVENT_EVENT_SET_LINK_AGGR_MODE 0x8fUL 2915a9a457f3SSelvin Xavier #define CREQ_QP_EVENT_EVENT_QUERY_QP_EXTEND 0x91UL 2916a9a457f3SSelvin Xavier #define CREQ_QP_EVENT_EVENT_QP_ERROR_NOTIFICATION 0xc0UL 2917a9a457f3SSelvin Xavier #define CREQ_QP_EVENT_EVENT_CQ_ERROR_NOTIFICATION 0xc1UL 2918a9a457f3SSelvin Xavier #define CREQ_QP_EVENT_EVENT_LAST CREQ_QP_EVENT_EVENT_CQ_ERROR_NOTIFICATION 2919a9a457f3SSelvin Xavier u8 reserved48[6]; 2920a9a457f3SSelvin Xavier }; 2921a9a457f3SSelvin Xavier 2922a9a457f3SSelvin Xavier /* creq_qp_error_notification (size:128b/16B) */ 29231ac5a404SSelvin Xavier struct creq_qp_error_notification { 29241ac5a404SSelvin Xavier u8 type; 29251ac5a404SSelvin Xavier #define CREQ_QP_ERROR_NOTIFICATION_TYPE_MASK 0x3fUL 29261ac5a404SSelvin Xavier #define CREQ_QP_ERROR_NOTIFICATION_TYPE_SFT 0 29271ac5a404SSelvin Xavier #define CREQ_QP_ERROR_NOTIFICATION_TYPE_QP_EVENT 0x38UL 2928a9a457f3SSelvin Xavier #define CREQ_QP_ERROR_NOTIFICATION_TYPE_LAST CREQ_QP_ERROR_NOTIFICATION_TYPE_QP_EVENT 29291ac5a404SSelvin Xavier u8 status; 29301ac5a404SSelvin Xavier u8 req_slow_path_state; 29311ac5a404SSelvin Xavier u8 req_err_state_reason; 29321ac5a404SSelvin Xavier __le32 xid; 29331ac5a404SSelvin Xavier u8 v; 29341ac5a404SSelvin Xavier #define CREQ_QP_ERROR_NOTIFICATION_V 0x1UL 29351ac5a404SSelvin Xavier u8 event; 29361ac5a404SSelvin Xavier #define CREQ_QP_ERROR_NOTIFICATION_EVENT_QP_ERROR_NOTIFICATION 0xc0UL 2937a9a457f3SSelvin Xavier #define CREQ_QP_ERROR_NOTIFICATION_EVENT_LAST \ 2938a9a457f3SSelvin Xavier CREQ_QP_ERROR_NOTIFICATION_EVENT_QP_ERROR_NOTIFICATION 29391ac5a404SSelvin Xavier u8 res_slow_path_state; 29401ac5a404SSelvin Xavier u8 res_err_state_reason; 29411ac5a404SSelvin Xavier __le16 sq_cons_idx; 29421ac5a404SSelvin Xavier __le16 rq_cons_idx; 29431ac5a404SSelvin Xavier }; 29441ac5a404SSelvin Xavier 2945a9a457f3SSelvin Xavier /* creq_cq_error_notification (size:128b/16B) */ 2946a9a457f3SSelvin Xavier struct creq_cq_error_notification { 2947a9a457f3SSelvin Xavier u8 type; 2948a9a457f3SSelvin Xavier #define CREQ_CQ_ERROR_NOTIFICATION_TYPE_MASK 0x3fUL 2949a9a457f3SSelvin Xavier #define CREQ_CQ_ERROR_NOTIFICATION_TYPE_SFT 0 2950a9a457f3SSelvin Xavier #define CREQ_CQ_ERROR_NOTIFICATION_TYPE_CQ_EVENT 0x38UL 2951a9a457f3SSelvin Xavier #define CREQ_CQ_ERROR_NOTIFICATION_TYPE_LAST CREQ_CQ_ERROR_NOTIFICATION_TYPE_CQ_EVENT 2952a9a457f3SSelvin Xavier u8 status; 2953a9a457f3SSelvin Xavier u8 cq_err_reason; 2954a9a457f3SSelvin Xavier #define CREQ_CQ_ERROR_NOTIFICATION_CQ_ERR_REASON_REQ_CQ_INVALID_ERROR 0x1UL 2955a9a457f3SSelvin Xavier #define CREQ_CQ_ERROR_NOTIFICATION_CQ_ERR_REASON_REQ_CQ_OVERFLOW_ERROR 0x2UL 2956a9a457f3SSelvin Xavier #define CREQ_CQ_ERROR_NOTIFICATION_CQ_ERR_REASON_REQ_CQ_LOAD_ERROR 0x3UL 2957a9a457f3SSelvin Xavier #define CREQ_CQ_ERROR_NOTIFICATION_CQ_ERR_REASON_RES_CQ_INVALID_ERROR 0x4UL 2958a9a457f3SSelvin Xavier #define CREQ_CQ_ERROR_NOTIFICATION_CQ_ERR_REASON_RES_CQ_OVERFLOW_ERROR 0x5UL 2959a9a457f3SSelvin Xavier #define CREQ_CQ_ERROR_NOTIFICATION_CQ_ERR_REASON_RES_CQ_LOAD_ERROR 0x6UL 2960a9a457f3SSelvin Xavier #define CREQ_CQ_ERROR_NOTIFICATION_CQ_ERR_REASON_LAST \ 2961a9a457f3SSelvin Xavier CREQ_CQ_ERROR_NOTIFICATION_CQ_ERR_REASON_RES_CQ_LOAD_ERROR 2962a9a457f3SSelvin Xavier u8 reserved8; 2963a9a457f3SSelvin Xavier __le32 xid; 2964a9a457f3SSelvin Xavier u8 v; 2965a9a457f3SSelvin Xavier #define CREQ_CQ_ERROR_NOTIFICATION_V 0x1UL 2966a9a457f3SSelvin Xavier u8 event; 2967a9a457f3SSelvin Xavier #define CREQ_CQ_ERROR_NOTIFICATION_EVENT_CQ_ERROR_NOTIFICATION 0xc1UL 2968a9a457f3SSelvin Xavier #define CREQ_CQ_ERROR_NOTIFICATION_EVENT_LAST \ 2969a9a457f3SSelvin Xavier CREQ_CQ_ERROR_NOTIFICATION_EVENT_CQ_ERROR_NOTIFICATION 2970a9a457f3SSelvin Xavier u8 reserved48[6]; 2971a9a457f3SSelvin Xavier }; 29721ac5a404SSelvin Xavier 2973a9a457f3SSelvin Xavier /* sq_base (size:64b/8B) */ 2974a9a457f3SSelvin Xavier struct sq_base { 2975a9a457f3SSelvin Xavier u8 wqe_type; 2976a9a457f3SSelvin Xavier #define SQ_BASE_WQE_TYPE_SEND 0x0UL 2977a9a457f3SSelvin Xavier #define SQ_BASE_WQE_TYPE_SEND_W_IMMEAD 0x1UL 2978a9a457f3SSelvin Xavier #define SQ_BASE_WQE_TYPE_SEND_W_INVALID 0x2UL 2979a9a457f3SSelvin Xavier #define SQ_BASE_WQE_TYPE_WRITE_WQE 0x4UL 2980a9a457f3SSelvin Xavier #define SQ_BASE_WQE_TYPE_WRITE_W_IMMEAD 0x5UL 2981a9a457f3SSelvin Xavier #define SQ_BASE_WQE_TYPE_READ_WQE 0x6UL 2982a9a457f3SSelvin Xavier #define SQ_BASE_WQE_TYPE_ATOMIC_CS 0x8UL 2983a9a457f3SSelvin Xavier #define SQ_BASE_WQE_TYPE_ATOMIC_FA 0xbUL 2984a9a457f3SSelvin Xavier #define SQ_BASE_WQE_TYPE_LOCAL_INVALID 0xcUL 2985a9a457f3SSelvin Xavier #define SQ_BASE_WQE_TYPE_FR_PMR 0xdUL 2986a9a457f3SSelvin Xavier #define SQ_BASE_WQE_TYPE_BIND 0xeUL 2987a9a457f3SSelvin Xavier #define SQ_BASE_WQE_TYPE_FR_PPMR 0xfUL 2988a9a457f3SSelvin Xavier #define SQ_BASE_WQE_TYPE_LAST SQ_BASE_WQE_TYPE_FR_PPMR 2989a9a457f3SSelvin Xavier u8 unused_0[7]; 2990a9a457f3SSelvin Xavier }; 2991a9a457f3SSelvin Xavier 2992a9a457f3SSelvin Xavier /* sq_sge (size:128b/16B) */ 2993a9a457f3SSelvin Xavier struct sq_sge { 2994a9a457f3SSelvin Xavier __le64 va_or_pa; 2995a9a457f3SSelvin Xavier __le32 l_key; 2996a9a457f3SSelvin Xavier __le32 size; 2997a9a457f3SSelvin Xavier }; 2998a9a457f3SSelvin Xavier 2999a9a457f3SSelvin Xavier /* sq_psn_search (size:64b/8B) */ 3000a9a457f3SSelvin Xavier struct sq_psn_search { 3001a9a457f3SSelvin Xavier __le32 opcode_start_psn; 3002a9a457f3SSelvin Xavier #define SQ_PSN_SEARCH_START_PSN_MASK 0xffffffUL 3003a9a457f3SSelvin Xavier #define SQ_PSN_SEARCH_START_PSN_SFT 0 3004a9a457f3SSelvin Xavier #define SQ_PSN_SEARCH_OPCODE_MASK 0xff000000UL 3005a9a457f3SSelvin Xavier #define SQ_PSN_SEARCH_OPCODE_SFT 24 3006a9a457f3SSelvin Xavier __le32 flags_next_psn; 3007a9a457f3SSelvin Xavier #define SQ_PSN_SEARCH_NEXT_PSN_MASK 0xffffffUL 3008a9a457f3SSelvin Xavier #define SQ_PSN_SEARCH_NEXT_PSN_SFT 0 3009a9a457f3SSelvin Xavier #define SQ_PSN_SEARCH_FLAGS_MASK 0xff000000UL 3010a9a457f3SSelvin Xavier #define SQ_PSN_SEARCH_FLAGS_SFT 24 3011a9a457f3SSelvin Xavier }; 3012a9a457f3SSelvin Xavier 3013a9a457f3SSelvin Xavier /* sq_psn_search_ext (size:128b/16B) */ 3014a9a457f3SSelvin Xavier struct sq_psn_search_ext { 3015a9a457f3SSelvin Xavier __le32 opcode_start_psn; 3016a9a457f3SSelvin Xavier #define SQ_PSN_SEARCH_EXT_START_PSN_MASK 0xffffffUL 3017a9a457f3SSelvin Xavier #define SQ_PSN_SEARCH_EXT_START_PSN_SFT 0 3018a9a457f3SSelvin Xavier #define SQ_PSN_SEARCH_EXT_OPCODE_MASK 0xff000000UL 3019a9a457f3SSelvin Xavier #define SQ_PSN_SEARCH_EXT_OPCODE_SFT 24 3020a9a457f3SSelvin Xavier __le32 flags_next_psn; 3021a9a457f3SSelvin Xavier #define SQ_PSN_SEARCH_EXT_NEXT_PSN_MASK 0xffffffUL 3022a9a457f3SSelvin Xavier #define SQ_PSN_SEARCH_EXT_NEXT_PSN_SFT 0 3023a9a457f3SSelvin Xavier #define SQ_PSN_SEARCH_EXT_FLAGS_MASK 0xff000000UL 3024a9a457f3SSelvin Xavier #define SQ_PSN_SEARCH_EXT_FLAGS_SFT 24 3025a9a457f3SSelvin Xavier __le16 start_slot_idx; 3026a9a457f3SSelvin Xavier __le16 reserved16; 3027a9a457f3SSelvin Xavier __le32 reserved32; 3028a9a457f3SSelvin Xavier }; 3029a9a457f3SSelvin Xavier 30309a54460bSSelvin Xavier /* sq_msn_search (size:64b/8B) */ 30319a54460bSSelvin Xavier struct sq_msn_search { 30329a54460bSSelvin Xavier __le64 start_idx_next_psn_start_psn; 30339a54460bSSelvin Xavier #define SQ_MSN_SEARCH_START_PSN_MASK 0xffffffUL 30349a54460bSSelvin Xavier #define SQ_MSN_SEARCH_START_PSN_SFT 0 30359a54460bSSelvin Xavier #define SQ_MSN_SEARCH_NEXT_PSN_MASK 0xffffff000000ULL 30369a54460bSSelvin Xavier #define SQ_MSN_SEARCH_NEXT_PSN_SFT 24 30379a54460bSSelvin Xavier #define SQ_MSN_SEARCH_START_IDX_MASK 0xffff000000000000ULL 30389a54460bSSelvin Xavier #define SQ_MSN_SEARCH_START_IDX_SFT 48 30399a54460bSSelvin Xavier }; 30409a54460bSSelvin Xavier 3041a9a457f3SSelvin Xavier /* sq_send (size:1024b/128B) */ 3042a9a457f3SSelvin Xavier struct sq_send { 3043a9a457f3SSelvin Xavier u8 wqe_type; 3044a9a457f3SSelvin Xavier #define SQ_SEND_WQE_TYPE_SEND 0x0UL 3045a9a457f3SSelvin Xavier #define SQ_SEND_WQE_TYPE_SEND_W_IMMEAD 0x1UL 3046a9a457f3SSelvin Xavier #define SQ_SEND_WQE_TYPE_SEND_W_INVALID 0x2UL 3047a9a457f3SSelvin Xavier #define SQ_SEND_WQE_TYPE_LAST SQ_SEND_WQE_TYPE_SEND_W_INVALID 3048a9a457f3SSelvin Xavier u8 flags; 3049a9a457f3SSelvin Xavier #define SQ_SEND_FLAGS_INLINE_SE_UC_FENCE_RD_OR_ATOMIC_FENCE_SIGNAL_COMP_MASK 0xffUL 3050a9a457f3SSelvin Xavier #define SQ_SEND_FLAGS_INLINE_SE_UC_FENCE_RD_OR_ATOMIC_FENCE_SIGNAL_COMP_SFT 0 3051a9a457f3SSelvin Xavier #define SQ_SEND_FLAGS_SIGNAL_COMP 0x1UL 3052a9a457f3SSelvin Xavier #define SQ_SEND_FLAGS_RD_OR_ATOMIC_FENCE 0x2UL 3053a9a457f3SSelvin Xavier #define SQ_SEND_FLAGS_UC_FENCE 0x4UL 3054a9a457f3SSelvin Xavier #define SQ_SEND_FLAGS_SE 0x8UL 3055a9a457f3SSelvin Xavier #define SQ_SEND_FLAGS_INLINE 0x10UL 3056a9a457f3SSelvin Xavier #define SQ_SEND_FLAGS_WQE_TS_EN 0x20UL 3057a9a457f3SSelvin Xavier #define SQ_SEND_FLAGS_DEBUG_TRACE 0x40UL 3058a9a457f3SSelvin Xavier u8 wqe_size; 3059a9a457f3SSelvin Xavier u8 reserved8_1; 3060a9a457f3SSelvin Xavier __le32 inv_key_or_imm_data; 3061a9a457f3SSelvin Xavier __le32 length; 3062a9a457f3SSelvin Xavier __le32 q_key; 3063a9a457f3SSelvin Xavier __le32 dst_qp; 3064a9a457f3SSelvin Xavier #define SQ_SEND_DST_QP_MASK 0xffffffUL 3065a9a457f3SSelvin Xavier #define SQ_SEND_DST_QP_SFT 0 3066a9a457f3SSelvin Xavier __le32 avid; 3067a9a457f3SSelvin Xavier #define SQ_SEND_AVID_MASK 0xfffffUL 3068a9a457f3SSelvin Xavier #define SQ_SEND_AVID_SFT 0 3069a9a457f3SSelvin Xavier __le32 reserved32; 3070a9a457f3SSelvin Xavier __le32 timestamp; 3071a9a457f3SSelvin Xavier #define SQ_SEND_TIMESTAMP_MASK 0xffffffUL 3072a9a457f3SSelvin Xavier #define SQ_SEND_TIMESTAMP_SFT 0 3073a9a457f3SSelvin Xavier __le32 data[24]; 3074a9a457f3SSelvin Xavier }; 3075a9a457f3SSelvin Xavier 3076a9a457f3SSelvin Xavier /* sq_send_hdr (size:256b/32B) */ 3077a9a457f3SSelvin Xavier struct sq_send_hdr { 3078a9a457f3SSelvin Xavier u8 wqe_type; 3079a9a457f3SSelvin Xavier #define SQ_SEND_HDR_WQE_TYPE_SEND 0x0UL 3080a9a457f3SSelvin Xavier #define SQ_SEND_HDR_WQE_TYPE_SEND_W_IMMEAD 0x1UL 3081a9a457f3SSelvin Xavier #define SQ_SEND_HDR_WQE_TYPE_SEND_W_INVALID 0x2UL 3082a9a457f3SSelvin Xavier #define SQ_SEND_HDR_WQE_TYPE_LAST SQ_SEND_HDR_WQE_TYPE_SEND_W_INVALID 3083a9a457f3SSelvin Xavier u8 flags; 3084a9a457f3SSelvin Xavier #define SQ_SEND_HDR_FLAGS_INLINE_SE_UC_FENCE_RD_OR_ATOMIC_FENCE_SIGNAL_COMP_MASK 0xffUL 3085a9a457f3SSelvin Xavier #define SQ_SEND_HDR_FLAGS_INLINE_SE_UC_FENCE_RD_OR_ATOMIC_FENCE_SIGNAL_COMP_SFT 0 3086a9a457f3SSelvin Xavier #define SQ_SEND_HDR_FLAGS_SIGNAL_COMP 0x1UL 3087a9a457f3SSelvin Xavier #define SQ_SEND_HDR_FLAGS_RD_OR_ATOMIC_FENCE 0x2UL 3088a9a457f3SSelvin Xavier #define SQ_SEND_HDR_FLAGS_UC_FENCE 0x4UL 3089a9a457f3SSelvin Xavier #define SQ_SEND_HDR_FLAGS_SE 0x8UL 3090a9a457f3SSelvin Xavier #define SQ_SEND_HDR_FLAGS_INLINE 0x10UL 3091a9a457f3SSelvin Xavier #define SQ_SEND_HDR_FLAGS_WQE_TS_EN 0x20UL 3092a9a457f3SSelvin Xavier #define SQ_SEND_HDR_FLAGS_DEBUG_TRACE 0x40UL 3093a9a457f3SSelvin Xavier u8 wqe_size; 3094a9a457f3SSelvin Xavier u8 reserved8_1; 3095a9a457f3SSelvin Xavier __le32 inv_key_or_imm_data; 3096a9a457f3SSelvin Xavier __le32 length; 3097a9a457f3SSelvin Xavier __le32 q_key; 3098a9a457f3SSelvin Xavier __le32 dst_qp; 3099a9a457f3SSelvin Xavier #define SQ_SEND_HDR_DST_QP_MASK 0xffffffUL 3100a9a457f3SSelvin Xavier #define SQ_SEND_HDR_DST_QP_SFT 0 3101a9a457f3SSelvin Xavier __le32 avid; 3102a9a457f3SSelvin Xavier #define SQ_SEND_HDR_AVID_MASK 0xfffffUL 3103a9a457f3SSelvin Xavier #define SQ_SEND_HDR_AVID_SFT 0 3104a9a457f3SSelvin Xavier __le32 reserved32; 3105a9a457f3SSelvin Xavier __le32 timestamp; 3106a9a457f3SSelvin Xavier #define SQ_SEND_HDR_TIMESTAMP_MASK 0xffffffUL 3107a9a457f3SSelvin Xavier #define SQ_SEND_HDR_TIMESTAMP_SFT 0 3108a9a457f3SSelvin Xavier }; 3109a9a457f3SSelvin Xavier 3110a9a457f3SSelvin Xavier /* sq_send_raweth_qp1 (size:1024b/128B) */ 3111a9a457f3SSelvin Xavier struct sq_send_raweth_qp1 { 3112a9a457f3SSelvin Xavier u8 wqe_type; 3113a9a457f3SSelvin Xavier #define SQ_SEND_RAWETH_QP1_WQE_TYPE_SEND 0x0UL 3114a9a457f3SSelvin Xavier #define SQ_SEND_RAWETH_QP1_WQE_TYPE_LAST SQ_SEND_RAWETH_QP1_WQE_TYPE_SEND 3115a9a457f3SSelvin Xavier u8 flags; 3116a9a457f3SSelvin Xavier #define SQ_SEND_RAWETH_QP1_FLAGS_INLINE_SE_UC_FENCE_RD_OR_ATOMIC_FENCE_SIGNAL_COMP_MASK \ 3117a9a457f3SSelvin Xavier 0xffUL 3118a9a457f3SSelvin Xavier #define SQ_SEND_RAWETH_QP1_FLAGS_INLINE_SE_UC_FENCE_RD_OR_ATOMIC_FENCE_SIGNAL_COMP_SFT \ 3119a9a457f3SSelvin Xavier 0 3120a9a457f3SSelvin Xavier #define SQ_SEND_RAWETH_QP1_FLAGS_SIGNAL_COMP 0x1UL 3121a9a457f3SSelvin Xavier #define SQ_SEND_RAWETH_QP1_FLAGS_RD_OR_ATOMIC_FENCE 0x2UL 3122a9a457f3SSelvin Xavier #define SQ_SEND_RAWETH_QP1_FLAGS_UC_FENCE 0x4UL 3123a9a457f3SSelvin Xavier #define SQ_SEND_RAWETH_QP1_FLAGS_SE 0x8UL 3124a9a457f3SSelvin Xavier #define SQ_SEND_RAWETH_QP1_FLAGS_INLINE 0x10UL 3125a9a457f3SSelvin Xavier #define SQ_SEND_RAWETH_QP1_FLAGS_WQE_TS_EN 0x20UL 3126a9a457f3SSelvin Xavier #define SQ_SEND_RAWETH_QP1_FLAGS_DEBUG_TRACE 0x40UL 3127a9a457f3SSelvin Xavier u8 wqe_size; 3128a9a457f3SSelvin Xavier u8 reserved8; 3129a9a457f3SSelvin Xavier __le16 lflags; 3130a9a457f3SSelvin Xavier #define SQ_SEND_RAWETH_QP1_LFLAGS_TCP_UDP_CHKSUM 0x1UL 3131a9a457f3SSelvin Xavier #define SQ_SEND_RAWETH_QP1_LFLAGS_IP_CHKSUM 0x2UL 3132a9a457f3SSelvin Xavier #define SQ_SEND_RAWETH_QP1_LFLAGS_NOCRC 0x4UL 3133a9a457f3SSelvin Xavier #define SQ_SEND_RAWETH_QP1_LFLAGS_STAMP 0x8UL 3134a9a457f3SSelvin Xavier #define SQ_SEND_RAWETH_QP1_LFLAGS_T_IP_CHKSUM 0x10UL 3135a9a457f3SSelvin Xavier #define SQ_SEND_RAWETH_QP1_LFLAGS_ROCE_CRC 0x100UL 3136a9a457f3SSelvin Xavier #define SQ_SEND_RAWETH_QP1_LFLAGS_FCOE_CRC 0x200UL 3137a9a457f3SSelvin Xavier __le16 cfa_action; 3138a9a457f3SSelvin Xavier __le32 length; 3139a9a457f3SSelvin Xavier __le32 reserved32_1; 3140a9a457f3SSelvin Xavier __le32 cfa_meta; 3141a9a457f3SSelvin Xavier #define SQ_SEND_RAWETH_QP1_CFA_META_VLAN_VID_MASK 0xfffUL 3142a9a457f3SSelvin Xavier #define SQ_SEND_RAWETH_QP1_CFA_META_VLAN_VID_SFT 0 3143a9a457f3SSelvin Xavier #define SQ_SEND_RAWETH_QP1_CFA_META_VLAN_DE 0x1000UL 3144a9a457f3SSelvin Xavier #define SQ_SEND_RAWETH_QP1_CFA_META_VLAN_PRI_MASK 0xe000UL 3145a9a457f3SSelvin Xavier #define SQ_SEND_RAWETH_QP1_CFA_META_VLAN_PRI_SFT 13 3146a9a457f3SSelvin Xavier #define SQ_SEND_RAWETH_QP1_CFA_META_VLAN_TPID_MASK 0x70000UL 3147a9a457f3SSelvin Xavier #define SQ_SEND_RAWETH_QP1_CFA_META_VLAN_TPID_SFT 16 3148a9a457f3SSelvin Xavier #define SQ_SEND_RAWETH_QP1_CFA_META_VLAN_TPID_TPID88A8 (0x0UL << 16) 3149a9a457f3SSelvin Xavier #define SQ_SEND_RAWETH_QP1_CFA_META_VLAN_TPID_TPID8100 (0x1UL << 16) 3150a9a457f3SSelvin Xavier #define SQ_SEND_RAWETH_QP1_CFA_META_VLAN_TPID_TPID9100 (0x2UL << 16) 3151a9a457f3SSelvin Xavier #define SQ_SEND_RAWETH_QP1_CFA_META_VLAN_TPID_TPID9200 (0x3UL << 16) 3152a9a457f3SSelvin Xavier #define SQ_SEND_RAWETH_QP1_CFA_META_VLAN_TPID_TPID9300 (0x4UL << 16) 3153a9a457f3SSelvin Xavier #define SQ_SEND_RAWETH_QP1_CFA_META_VLAN_TPID_TPIDCFG (0x5UL << 16) 3154a9a457f3SSelvin Xavier #define SQ_SEND_RAWETH_QP1_CFA_META_VLAN_TPID_LAST\ 3155a9a457f3SSelvin Xavier SQ_SEND_RAWETH_QP1_CFA_META_VLAN_TPID_TPIDCFG 3156a9a457f3SSelvin Xavier #define SQ_SEND_RAWETH_QP1_CFA_META_VLAN_RESERVED_MASK 0xff80000UL 3157a9a457f3SSelvin Xavier #define SQ_SEND_RAWETH_QP1_CFA_META_VLAN_RESERVED_SFT 19 3158a9a457f3SSelvin Xavier #define SQ_SEND_RAWETH_QP1_CFA_META_KEY_MASK 0xf0000000UL 3159a9a457f3SSelvin Xavier #define SQ_SEND_RAWETH_QP1_CFA_META_KEY_SFT 28 3160a9a457f3SSelvin Xavier #define SQ_SEND_RAWETH_QP1_CFA_META_KEY_NONE (0x0UL << 28) 3161a9a457f3SSelvin Xavier #define SQ_SEND_RAWETH_QP1_CFA_META_KEY_VLAN_TAG (0x1UL << 28) 3162a9a457f3SSelvin Xavier #define SQ_SEND_RAWETH_QP1_CFA_META_KEY_LAST SQ_SEND_RAWETH_QP1_CFA_META_KEY_VLAN_TAG 3163a9a457f3SSelvin Xavier __le32 reserved32_2; 3164a9a457f3SSelvin Xavier __le32 reserved32_3; 3165a9a457f3SSelvin Xavier __le32 timestamp; 3166a9a457f3SSelvin Xavier #define SQ_SEND_RAWETH_QP1_TIMESTAMP_MASK 0xffffffUL 3167a9a457f3SSelvin Xavier #define SQ_SEND_RAWETH_QP1_TIMESTAMP_SFT 0 3168a9a457f3SSelvin Xavier __le32 data[24]; 3169a9a457f3SSelvin Xavier }; 3170a9a457f3SSelvin Xavier 3171a9a457f3SSelvin Xavier /* sq_send_raweth_qp1_hdr (size:256b/32B) */ 3172a9a457f3SSelvin Xavier struct sq_send_raweth_qp1_hdr { 3173a9a457f3SSelvin Xavier u8 wqe_type; 3174a9a457f3SSelvin Xavier #define SQ_SEND_RAWETH_QP1_HDR_WQE_TYPE_SEND 0x0UL 3175a9a457f3SSelvin Xavier #define SQ_SEND_RAWETH_QP1_HDR_WQE_TYPE_LAST SQ_SEND_RAWETH_QP1_HDR_WQE_TYPE_SEND 3176a9a457f3SSelvin Xavier u8 flags; 3177a9a457f3SSelvin Xavier #define \ 3178a9a457f3SSelvin Xavier SQ_SEND_RAWETH_QP1_HDR_FLAGS_INLINE_SE_UC_FENCE_RD_OR_ATOMIC_FENCE_SIGNAL_COMP_MASK 0xffUL 3179a9a457f3SSelvin Xavier #define SQ_SEND_RAWETH_QP1_HDR_FLAGS_INLINE_SE_UC_FENCE_RD_OR_ATOMIC_FENCE_SIGNAL_COMP_SFT\ 3180a9a457f3SSelvin Xavier 0 3181a9a457f3SSelvin Xavier #define SQ_SEND_RAWETH_QP1_HDR_FLAGS_SIGNAL_COMP 0x1UL 3182a9a457f3SSelvin Xavier #define SQ_SEND_RAWETH_QP1_HDR_FLAGS_RD_OR_ATOMIC_FENCE 0x2UL 3183a9a457f3SSelvin Xavier #define SQ_SEND_RAWETH_QP1_HDR_FLAGS_UC_FENCE 0x4UL 3184a9a457f3SSelvin Xavier #define SQ_SEND_RAWETH_QP1_HDR_FLAGS_SE 0x8UL 3185a9a457f3SSelvin Xavier #define SQ_SEND_RAWETH_QP1_HDR_FLAGS_INLINE 0x10UL 3186a9a457f3SSelvin Xavier #define SQ_SEND_RAWETH_QP1_HDR_FLAGS_WQE_TS_EN 0x20UL 3187a9a457f3SSelvin Xavier #define SQ_SEND_RAWETH_QP1_HDR_FLAGS_DEBUG_TRACE 0x40UL 3188a9a457f3SSelvin Xavier u8 wqe_size; 3189a9a457f3SSelvin Xavier u8 reserved8; 3190a9a457f3SSelvin Xavier __le16 lflags; 3191a9a457f3SSelvin Xavier #define SQ_SEND_RAWETH_QP1_HDR_LFLAGS_TCP_UDP_CHKSUM 0x1UL 3192a9a457f3SSelvin Xavier #define SQ_SEND_RAWETH_QP1_HDR_LFLAGS_IP_CHKSUM 0x2UL 3193a9a457f3SSelvin Xavier #define SQ_SEND_RAWETH_QP1_HDR_LFLAGS_NOCRC 0x4UL 3194a9a457f3SSelvin Xavier #define SQ_SEND_RAWETH_QP1_HDR_LFLAGS_STAMP 0x8UL 3195a9a457f3SSelvin Xavier #define SQ_SEND_RAWETH_QP1_HDR_LFLAGS_T_IP_CHKSUM 0x10UL 3196a9a457f3SSelvin Xavier #define SQ_SEND_RAWETH_QP1_HDR_LFLAGS_ROCE_CRC 0x100UL 3197a9a457f3SSelvin Xavier #define SQ_SEND_RAWETH_QP1_HDR_LFLAGS_FCOE_CRC 0x200UL 3198a9a457f3SSelvin Xavier __le16 cfa_action; 3199a9a457f3SSelvin Xavier __le32 length; 3200a9a457f3SSelvin Xavier __le32 reserved32_1; 3201a9a457f3SSelvin Xavier __le32 cfa_meta; 3202a9a457f3SSelvin Xavier #define SQ_SEND_RAWETH_QP1_HDR_CFA_META_VLAN_VID_MASK 0xfffUL 3203a9a457f3SSelvin Xavier #define SQ_SEND_RAWETH_QP1_HDR_CFA_META_VLAN_VID_SFT 0 3204a9a457f3SSelvin Xavier #define SQ_SEND_RAWETH_QP1_HDR_CFA_META_VLAN_DE 0x1000UL 3205a9a457f3SSelvin Xavier #define SQ_SEND_RAWETH_QP1_HDR_CFA_META_VLAN_PRI_MASK 0xe000UL 3206a9a457f3SSelvin Xavier #define SQ_SEND_RAWETH_QP1_HDR_CFA_META_VLAN_PRI_SFT 13 3207a9a457f3SSelvin Xavier #define SQ_SEND_RAWETH_QP1_HDR_CFA_META_VLAN_TPID_MASK 0x70000UL 3208a9a457f3SSelvin Xavier #define SQ_SEND_RAWETH_QP1_HDR_CFA_META_VLAN_TPID_SFT 16 3209a9a457f3SSelvin Xavier #define SQ_SEND_RAWETH_QP1_HDR_CFA_META_VLAN_TPID_TPID88A8 (0x0UL << 16) 3210a9a457f3SSelvin Xavier #define SQ_SEND_RAWETH_QP1_HDR_CFA_META_VLAN_TPID_TPID8100 (0x1UL << 16) 3211a9a457f3SSelvin Xavier #define SQ_SEND_RAWETH_QP1_HDR_CFA_META_VLAN_TPID_TPID9100 (0x2UL << 16) 3212a9a457f3SSelvin Xavier #define SQ_SEND_RAWETH_QP1_HDR_CFA_META_VLAN_TPID_TPID9200 (0x3UL << 16) 3213a9a457f3SSelvin Xavier #define SQ_SEND_RAWETH_QP1_HDR_CFA_META_VLAN_TPID_TPID9300 (0x4UL << 16) 3214a9a457f3SSelvin Xavier #define SQ_SEND_RAWETH_QP1_HDR_CFA_META_VLAN_TPID_TPIDCFG (0x5UL << 16) 3215a9a457f3SSelvin Xavier #define SQ_SEND_RAWETH_QP1_HDR_CFA_META_VLAN_TPID_LAST\ 3216a9a457f3SSelvin Xavier SQ_SEND_RAWETH_QP1_HDR_CFA_META_VLAN_TPID_TPIDCFG 3217a9a457f3SSelvin Xavier #define SQ_SEND_RAWETH_QP1_HDR_CFA_META_VLAN_RESERVED_MASK 0xff80000UL 3218a9a457f3SSelvin Xavier #define SQ_SEND_RAWETH_QP1_HDR_CFA_META_VLAN_RESERVED_SFT 19 3219a9a457f3SSelvin Xavier #define SQ_SEND_RAWETH_QP1_HDR_CFA_META_KEY_MASK 0xf0000000UL 3220a9a457f3SSelvin Xavier #define SQ_SEND_RAWETH_QP1_HDR_CFA_META_KEY_SFT 28 3221a9a457f3SSelvin Xavier #define SQ_SEND_RAWETH_QP1_HDR_CFA_META_KEY_NONE (0x0UL << 28) 3222a9a457f3SSelvin Xavier #define SQ_SEND_RAWETH_QP1_HDR_CFA_META_KEY_VLAN_TAG (0x1UL << 28) 3223a9a457f3SSelvin Xavier #define SQ_SEND_RAWETH_QP1_HDR_CFA_META_KEY_LAST\ 3224a9a457f3SSelvin Xavier SQ_SEND_RAWETH_QP1_HDR_CFA_META_KEY_VLAN_TAG 3225a9a457f3SSelvin Xavier __le32 reserved32_2; 3226a9a457f3SSelvin Xavier __le32 reserved32_3; 3227a9a457f3SSelvin Xavier __le32 timestamp; 3228a9a457f3SSelvin Xavier #define SQ_SEND_RAWETH_QP1_HDR_TIMESTAMP_MASK 0xffffffUL 3229a9a457f3SSelvin Xavier #define SQ_SEND_RAWETH_QP1_HDR_TIMESTAMP_SFT 0 3230a9a457f3SSelvin Xavier }; 3231a9a457f3SSelvin Xavier 3232a9a457f3SSelvin Xavier /* sq_rdma (size:1024b/128B) */ 3233a9a457f3SSelvin Xavier struct sq_rdma { 3234a9a457f3SSelvin Xavier u8 wqe_type; 3235a9a457f3SSelvin Xavier #define SQ_RDMA_WQE_TYPE_WRITE_WQE 0x4UL 3236a9a457f3SSelvin Xavier #define SQ_RDMA_WQE_TYPE_WRITE_W_IMMEAD 0x5UL 3237a9a457f3SSelvin Xavier #define SQ_RDMA_WQE_TYPE_READ_WQE 0x6UL 3238a9a457f3SSelvin Xavier #define SQ_RDMA_WQE_TYPE_LAST SQ_RDMA_WQE_TYPE_READ_WQE 3239a9a457f3SSelvin Xavier u8 flags; 3240a9a457f3SSelvin Xavier #define SQ_RDMA_FLAGS_INLINE_SE_UC_FENCE_RD_OR_ATOMIC_FENCE_SIGNAL_COMP_MASK 0xffUL 3241a9a457f3SSelvin Xavier #define SQ_RDMA_FLAGS_INLINE_SE_UC_FENCE_RD_OR_ATOMIC_FENCE_SIGNAL_COMP_SFT 0 3242a9a457f3SSelvin Xavier #define SQ_RDMA_FLAGS_SIGNAL_COMP 0x1UL 3243a9a457f3SSelvin Xavier #define SQ_RDMA_FLAGS_RD_OR_ATOMIC_FENCE 0x2UL 3244a9a457f3SSelvin Xavier #define SQ_RDMA_FLAGS_UC_FENCE 0x4UL 3245a9a457f3SSelvin Xavier #define SQ_RDMA_FLAGS_SE 0x8UL 3246a9a457f3SSelvin Xavier #define SQ_RDMA_FLAGS_INLINE 0x10UL 3247a9a457f3SSelvin Xavier #define SQ_RDMA_FLAGS_WQE_TS_EN 0x20UL 3248a9a457f3SSelvin Xavier #define SQ_RDMA_FLAGS_DEBUG_TRACE 0x40UL 3249a9a457f3SSelvin Xavier u8 wqe_size; 3250a9a457f3SSelvin Xavier u8 reserved8; 3251a9a457f3SSelvin Xavier __le32 imm_data; 3252a9a457f3SSelvin Xavier __le32 length; 3253a9a457f3SSelvin Xavier __le32 reserved32_1; 3254a9a457f3SSelvin Xavier __le64 remote_va; 3255a9a457f3SSelvin Xavier __le32 remote_key; 3256a9a457f3SSelvin Xavier __le32 timestamp; 3257a9a457f3SSelvin Xavier #define SQ_RDMA_TIMESTAMP_MASK 0xffffffUL 3258a9a457f3SSelvin Xavier #define SQ_RDMA_TIMESTAMP_SFT 0 3259a9a457f3SSelvin Xavier __le32 data[24]; 3260a9a457f3SSelvin Xavier }; 3261a9a457f3SSelvin Xavier 3262a9a457f3SSelvin Xavier /* sq_rdma_hdr (size:256b/32B) */ 3263a9a457f3SSelvin Xavier struct sq_rdma_hdr { 3264a9a457f3SSelvin Xavier u8 wqe_type; 3265a9a457f3SSelvin Xavier #define SQ_RDMA_HDR_WQE_TYPE_WRITE_WQE 0x4UL 3266a9a457f3SSelvin Xavier #define SQ_RDMA_HDR_WQE_TYPE_WRITE_W_IMMEAD 0x5UL 3267a9a457f3SSelvin Xavier #define SQ_RDMA_HDR_WQE_TYPE_READ_WQE 0x6UL 3268a9a457f3SSelvin Xavier #define SQ_RDMA_HDR_WQE_TYPE_LAST SQ_RDMA_HDR_WQE_TYPE_READ_WQE 3269a9a457f3SSelvin Xavier u8 flags; 3270a9a457f3SSelvin Xavier #define SQ_RDMA_HDR_FLAGS_INLINE_SE_UC_FENCE_RD_OR_ATOMIC_FENCE_SIGNAL_COMP_MASK 0xffUL 3271a9a457f3SSelvin Xavier #define SQ_RDMA_HDR_FLAGS_INLINE_SE_UC_FENCE_RD_OR_ATOMIC_FENCE_SIGNAL_COMP_SFT 0 3272a9a457f3SSelvin Xavier #define SQ_RDMA_HDR_FLAGS_SIGNAL_COMP 0x1UL 3273a9a457f3SSelvin Xavier #define SQ_RDMA_HDR_FLAGS_RD_OR_ATOMIC_FENCE 0x2UL 3274a9a457f3SSelvin Xavier #define SQ_RDMA_HDR_FLAGS_UC_FENCE 0x4UL 3275a9a457f3SSelvin Xavier #define SQ_RDMA_HDR_FLAGS_SE 0x8UL 3276a9a457f3SSelvin Xavier #define SQ_RDMA_HDR_FLAGS_INLINE 0x10UL 3277a9a457f3SSelvin Xavier #define SQ_RDMA_HDR_FLAGS_WQE_TS_EN 0x20UL 3278a9a457f3SSelvin Xavier #define SQ_RDMA_HDR_FLAGS_DEBUG_TRACE 0x40UL 3279a9a457f3SSelvin Xavier u8 wqe_size; 3280a9a457f3SSelvin Xavier u8 reserved8; 3281a9a457f3SSelvin Xavier __le32 imm_data; 3282a9a457f3SSelvin Xavier __le32 length; 3283a9a457f3SSelvin Xavier __le32 reserved32_1; 3284a9a457f3SSelvin Xavier __le64 remote_va; 3285a9a457f3SSelvin Xavier __le32 remote_key; 3286a9a457f3SSelvin Xavier __le32 timestamp; 3287a9a457f3SSelvin Xavier #define SQ_RDMA_HDR_TIMESTAMP_MASK 0xffffffUL 3288a9a457f3SSelvin Xavier #define SQ_RDMA_HDR_TIMESTAMP_SFT 0 3289a9a457f3SSelvin Xavier }; 3290a9a457f3SSelvin Xavier 3291a9a457f3SSelvin Xavier /* sq_atomic (size:1024b/128B) */ 3292a9a457f3SSelvin Xavier struct sq_atomic { 3293a9a457f3SSelvin Xavier u8 wqe_type; 3294a9a457f3SSelvin Xavier #define SQ_ATOMIC_WQE_TYPE_ATOMIC_CS 0x8UL 3295a9a457f3SSelvin Xavier #define SQ_ATOMIC_WQE_TYPE_ATOMIC_FA 0xbUL 3296a9a457f3SSelvin Xavier #define SQ_ATOMIC_WQE_TYPE_LAST SQ_ATOMIC_WQE_TYPE_ATOMIC_FA 3297a9a457f3SSelvin Xavier u8 flags; 3298a9a457f3SSelvin Xavier #define SQ_ATOMIC_FLAGS_INLINE_SE_UC_FENCE_RD_OR_ATOMIC_FENCE_SIGNAL_COMP_MASK 0xffUL 3299a9a457f3SSelvin Xavier #define SQ_ATOMIC_FLAGS_INLINE_SE_UC_FENCE_RD_OR_ATOMIC_FENCE_SIGNAL_COMP_SFT 0 3300a9a457f3SSelvin Xavier #define SQ_ATOMIC_FLAGS_SIGNAL_COMP 0x1UL 3301a9a457f3SSelvin Xavier #define SQ_ATOMIC_FLAGS_RD_OR_ATOMIC_FENCE 0x2UL 3302a9a457f3SSelvin Xavier #define SQ_ATOMIC_FLAGS_UC_FENCE 0x4UL 3303a9a457f3SSelvin Xavier #define SQ_ATOMIC_FLAGS_SE 0x8UL 3304a9a457f3SSelvin Xavier #define SQ_ATOMIC_FLAGS_INLINE 0x10UL 3305a9a457f3SSelvin Xavier #define SQ_ATOMIC_FLAGS_WQE_TS_EN 0x20UL 3306a9a457f3SSelvin Xavier #define SQ_ATOMIC_FLAGS_DEBUG_TRACE 0x40UL 3307a9a457f3SSelvin Xavier __le16 reserved16; 3308a9a457f3SSelvin Xavier __le32 remote_key; 3309a9a457f3SSelvin Xavier __le64 remote_va; 3310a9a457f3SSelvin Xavier __le64 swap_data; 3311a9a457f3SSelvin Xavier __le64 cmp_data; 3312a9a457f3SSelvin Xavier __le32 data[24]; 3313a9a457f3SSelvin Xavier }; 3314a9a457f3SSelvin Xavier 3315a9a457f3SSelvin Xavier /* sq_atomic_hdr (size:256b/32B) */ 3316a9a457f3SSelvin Xavier struct sq_atomic_hdr { 3317a9a457f3SSelvin Xavier u8 wqe_type; 3318a9a457f3SSelvin Xavier #define SQ_ATOMIC_HDR_WQE_TYPE_ATOMIC_CS 0x8UL 3319a9a457f3SSelvin Xavier #define SQ_ATOMIC_HDR_WQE_TYPE_ATOMIC_FA 0xbUL 3320a9a457f3SSelvin Xavier #define SQ_ATOMIC_HDR_WQE_TYPE_LAST SQ_ATOMIC_HDR_WQE_TYPE_ATOMIC_FA 3321a9a457f3SSelvin Xavier u8 flags; 3322a9a457f3SSelvin Xavier #define SQ_ATOMIC_HDR_FLAGS_INLINE_SE_UC_FENCE_RD_OR_ATOMIC_FENCE_SIGNAL_COMP_MASK 0xffUL 3323a9a457f3SSelvin Xavier #define SQ_ATOMIC_HDR_FLAGS_INLINE_SE_UC_FENCE_RD_OR_ATOMIC_FENCE_SIGNAL_COMP_SFT 0 3324a9a457f3SSelvin Xavier #define SQ_ATOMIC_HDR_FLAGS_SIGNAL_COMP 0x1UL 3325a9a457f3SSelvin Xavier #define SQ_ATOMIC_HDR_FLAGS_RD_OR_ATOMIC_FENCE 0x2UL 3326a9a457f3SSelvin Xavier #define SQ_ATOMIC_HDR_FLAGS_UC_FENCE 0x4UL 3327a9a457f3SSelvin Xavier #define SQ_ATOMIC_HDR_FLAGS_SE 0x8UL 3328a9a457f3SSelvin Xavier #define SQ_ATOMIC_HDR_FLAGS_INLINE 0x10UL 3329a9a457f3SSelvin Xavier #define SQ_ATOMIC_HDR_FLAGS_WQE_TS_EN 0x20UL 3330a9a457f3SSelvin Xavier #define SQ_ATOMIC_HDR_FLAGS_DEBUG_TRACE 0x40UL 3331a9a457f3SSelvin Xavier __le16 reserved16; 3332a9a457f3SSelvin Xavier __le32 remote_key; 3333a9a457f3SSelvin Xavier __le64 remote_va; 3334a9a457f3SSelvin Xavier __le64 swap_data; 3335a9a457f3SSelvin Xavier __le64 cmp_data; 3336a9a457f3SSelvin Xavier }; 3337a9a457f3SSelvin Xavier 3338a9a457f3SSelvin Xavier /* sq_localinvalidate (size:1024b/128B) */ 3339a9a457f3SSelvin Xavier struct sq_localinvalidate { 3340a9a457f3SSelvin Xavier u8 wqe_type; 3341a9a457f3SSelvin Xavier #define SQ_LOCALINVALIDATE_WQE_TYPE_LOCAL_INVALID 0xcUL 3342a9a457f3SSelvin Xavier #define SQ_LOCALINVALIDATE_WQE_TYPE_LAST SQ_LOCALINVALIDATE_WQE_TYPE_LOCAL_INVALID 3343a9a457f3SSelvin Xavier u8 flags; 3344a9a457f3SSelvin Xavier #define SQ_LOCALINVALIDATE_FLAGS_INLINE_SE_UC_FENCE_RD_OR_ATOMIC_FENCE_SIGNAL_COMP_MASK\ 3345a9a457f3SSelvin Xavier 0xffUL 3346a9a457f3SSelvin Xavier #define SQ_LOCALINVALIDATE_FLAGS_INLINE_SE_UC_FENCE_RD_OR_ATOMIC_FENCE_SIGNAL_COMP_SFT\ 3347a9a457f3SSelvin Xavier 0 3348a9a457f3SSelvin Xavier #define SQ_LOCALINVALIDATE_FLAGS_SIGNAL_COMP 0x1UL 3349a9a457f3SSelvin Xavier #define SQ_LOCALINVALIDATE_FLAGS_RD_OR_ATOMIC_FENCE 0x2UL 3350a9a457f3SSelvin Xavier #define SQ_LOCALINVALIDATE_FLAGS_UC_FENCE 0x4UL 3351a9a457f3SSelvin Xavier #define SQ_LOCALINVALIDATE_FLAGS_SE 0x8UL 3352a9a457f3SSelvin Xavier #define SQ_LOCALINVALIDATE_FLAGS_INLINE 0x10UL 3353a9a457f3SSelvin Xavier #define SQ_LOCALINVALIDATE_FLAGS_WQE_TS_EN 0x20UL 3354a9a457f3SSelvin Xavier #define SQ_LOCALINVALIDATE_FLAGS_DEBUG_TRACE 0x40UL 3355a9a457f3SSelvin Xavier __le16 reserved16; 3356a9a457f3SSelvin Xavier __le32 inv_l_key; 3357a9a457f3SSelvin Xavier __le64 reserved64; 3358a9a457f3SSelvin Xavier u8 reserved128[16]; 3359a9a457f3SSelvin Xavier __le32 data[24]; 3360a9a457f3SSelvin Xavier }; 3361a9a457f3SSelvin Xavier 3362a9a457f3SSelvin Xavier /* sq_localinvalidate_hdr (size:256b/32B) */ 3363a9a457f3SSelvin Xavier struct sq_localinvalidate_hdr { 3364a9a457f3SSelvin Xavier u8 wqe_type; 3365a9a457f3SSelvin Xavier #define SQ_LOCALINVALIDATE_HDR_WQE_TYPE_LOCAL_INVALID 0xcUL 3366a9a457f3SSelvin Xavier #define SQ_LOCALINVALIDATE_HDR_WQE_TYPE_LAST SQ_LOCALINVALIDATE_HDR_WQE_TYPE_LOCAL_INVALID 3367a9a457f3SSelvin Xavier u8 flags; 3368a9a457f3SSelvin Xavier #define \ 3369a9a457f3SSelvin Xavier SQ_LOCALINVALIDATE_HDR_FLAGS_INLINE_SE_UC_FENCE_RD_OR_ATOMIC_FENCE_SIGNAL_COMP_MASK 0xffUL 3370a9a457f3SSelvin Xavier #define SQ_LOCALINVALIDATE_HDR_FLAGS_INLINE_SE_UC_FENCE_RD_OR_ATOMIC_FENCE_SIGNAL_COMP_SFT\ 3371a9a457f3SSelvin Xavier 0 3372a9a457f3SSelvin Xavier #define SQ_LOCALINVALIDATE_HDR_FLAGS_SIGNAL_COMP 0x1UL 3373a9a457f3SSelvin Xavier #define SQ_LOCALINVALIDATE_HDR_FLAGS_RD_OR_ATOMIC_FENCE 0x2UL 3374a9a457f3SSelvin Xavier #define SQ_LOCALINVALIDATE_HDR_FLAGS_UC_FENCE 0x4UL 3375a9a457f3SSelvin Xavier #define SQ_LOCALINVALIDATE_HDR_FLAGS_SE 0x8UL 3376a9a457f3SSelvin Xavier #define SQ_LOCALINVALIDATE_HDR_FLAGS_INLINE 0x10UL 3377a9a457f3SSelvin Xavier #define SQ_LOCALINVALIDATE_HDR_FLAGS_WQE_TS_EN 0x20UL 3378a9a457f3SSelvin Xavier #define SQ_LOCALINVALIDATE_HDR_FLAGS_DEBUG_TRACE 0x40UL 3379a9a457f3SSelvin Xavier __le16 reserved16; 3380a9a457f3SSelvin Xavier __le32 inv_l_key; 3381a9a457f3SSelvin Xavier __le64 reserved64; 3382a9a457f3SSelvin Xavier u8 reserved128[16]; 3383a9a457f3SSelvin Xavier }; 3384a9a457f3SSelvin Xavier 3385a9a457f3SSelvin Xavier /* sq_fr_pmr (size:1024b/128B) */ 3386a9a457f3SSelvin Xavier struct sq_fr_pmr { 3387a9a457f3SSelvin Xavier u8 wqe_type; 3388a9a457f3SSelvin Xavier #define SQ_FR_PMR_WQE_TYPE_FR_PMR 0xdUL 3389a9a457f3SSelvin Xavier #define SQ_FR_PMR_WQE_TYPE_LAST SQ_FR_PMR_WQE_TYPE_FR_PMR 3390a9a457f3SSelvin Xavier u8 flags; 3391a9a457f3SSelvin Xavier #define SQ_FR_PMR_FLAGS_SIGNAL_COMP 0x1UL 3392a9a457f3SSelvin Xavier #define SQ_FR_PMR_FLAGS_RD_OR_ATOMIC_FENCE 0x2UL 3393a9a457f3SSelvin Xavier #define SQ_FR_PMR_FLAGS_UC_FENCE 0x4UL 3394a9a457f3SSelvin Xavier #define SQ_FR_PMR_FLAGS_SE 0x8UL 3395a9a457f3SSelvin Xavier #define SQ_FR_PMR_FLAGS_INLINE 0x10UL 3396a9a457f3SSelvin Xavier #define SQ_FR_PMR_FLAGS_WQE_TS_EN 0x20UL 3397a9a457f3SSelvin Xavier #define SQ_FR_PMR_FLAGS_DEBUG_TRACE 0x40UL 3398a9a457f3SSelvin Xavier u8 access_cntl; 3399a9a457f3SSelvin Xavier #define SQ_FR_PMR_ACCESS_CNTL_LOCAL_WRITE 0x1UL 3400a9a457f3SSelvin Xavier #define SQ_FR_PMR_ACCESS_CNTL_REMOTE_READ 0x2UL 3401a9a457f3SSelvin Xavier #define SQ_FR_PMR_ACCESS_CNTL_REMOTE_WRITE 0x4UL 3402a9a457f3SSelvin Xavier #define SQ_FR_PMR_ACCESS_CNTL_REMOTE_ATOMIC 0x8UL 3403a9a457f3SSelvin Xavier #define SQ_FR_PMR_ACCESS_CNTL_WINDOW_BIND 0x10UL 3404a9a457f3SSelvin Xavier u8 zero_based_page_size_log; 3405a9a457f3SSelvin Xavier #define SQ_FR_PMR_PAGE_SIZE_LOG_MASK 0x1fUL 3406a9a457f3SSelvin Xavier #define SQ_FR_PMR_PAGE_SIZE_LOG_SFT 0 3407a9a457f3SSelvin Xavier #define SQ_FR_PMR_PAGE_SIZE_LOG_PGSZ_4K 0x0UL 3408a9a457f3SSelvin Xavier #define SQ_FR_PMR_PAGE_SIZE_LOG_PGSZ_8K 0x1UL 3409a9a457f3SSelvin Xavier #define SQ_FR_PMR_PAGE_SIZE_LOG_PGSZ_16K 0x2UL 3410a9a457f3SSelvin Xavier #define SQ_FR_PMR_PAGE_SIZE_LOG_PGSZ_32K 0x3UL 3411a9a457f3SSelvin Xavier #define SQ_FR_PMR_PAGE_SIZE_LOG_PGSZ_64K 0x4UL 3412a9a457f3SSelvin Xavier #define SQ_FR_PMR_PAGE_SIZE_LOG_PGSZ_128K 0x5UL 3413a9a457f3SSelvin Xavier #define SQ_FR_PMR_PAGE_SIZE_LOG_PGSZ_256K 0x6UL 3414a9a457f3SSelvin Xavier #define SQ_FR_PMR_PAGE_SIZE_LOG_PGSZ_512K 0x7UL 3415a9a457f3SSelvin Xavier #define SQ_FR_PMR_PAGE_SIZE_LOG_PGSZ_1M 0x8UL 3416a9a457f3SSelvin Xavier #define SQ_FR_PMR_PAGE_SIZE_LOG_PGSZ_2M 0x9UL 3417a9a457f3SSelvin Xavier #define SQ_FR_PMR_PAGE_SIZE_LOG_PGSZ_4M 0xaUL 3418a9a457f3SSelvin Xavier #define SQ_FR_PMR_PAGE_SIZE_LOG_PGSZ_8M 0xbUL 3419a9a457f3SSelvin Xavier #define SQ_FR_PMR_PAGE_SIZE_LOG_PGSZ_16M 0xcUL 3420a9a457f3SSelvin Xavier #define SQ_FR_PMR_PAGE_SIZE_LOG_PGSZ_32M 0xdUL 3421a9a457f3SSelvin Xavier #define SQ_FR_PMR_PAGE_SIZE_LOG_PGSZ_64M 0xeUL 3422a9a457f3SSelvin Xavier #define SQ_FR_PMR_PAGE_SIZE_LOG_PGSZ_128M 0xfUL 3423a9a457f3SSelvin Xavier #define SQ_FR_PMR_PAGE_SIZE_LOG_PGSZ_256M 0x10UL 3424a9a457f3SSelvin Xavier #define SQ_FR_PMR_PAGE_SIZE_LOG_PGSZ_512M 0x11UL 3425a9a457f3SSelvin Xavier #define SQ_FR_PMR_PAGE_SIZE_LOG_PGSZ_1G 0x12UL 3426a9a457f3SSelvin Xavier #define SQ_FR_PMR_PAGE_SIZE_LOG_PGSZ_2G 0x13UL 3427a9a457f3SSelvin Xavier #define SQ_FR_PMR_PAGE_SIZE_LOG_PGSZ_4G 0x14UL 3428a9a457f3SSelvin Xavier #define SQ_FR_PMR_PAGE_SIZE_LOG_PGSZ_8G 0x15UL 3429a9a457f3SSelvin Xavier #define SQ_FR_PMR_PAGE_SIZE_LOG_PGSZ_16G 0x16UL 3430a9a457f3SSelvin Xavier #define SQ_FR_PMR_PAGE_SIZE_LOG_PGSZ_32G 0x17UL 3431a9a457f3SSelvin Xavier #define SQ_FR_PMR_PAGE_SIZE_LOG_PGSZ_64G 0x18UL 3432a9a457f3SSelvin Xavier #define SQ_FR_PMR_PAGE_SIZE_LOG_PGSZ_128G 0x19UL 3433a9a457f3SSelvin Xavier #define SQ_FR_PMR_PAGE_SIZE_LOG_PGSZ_256G 0x1aUL 3434a9a457f3SSelvin Xavier #define SQ_FR_PMR_PAGE_SIZE_LOG_PGSZ_512G 0x1bUL 3435a9a457f3SSelvin Xavier #define SQ_FR_PMR_PAGE_SIZE_LOG_PGSZ_1T 0x1cUL 3436a9a457f3SSelvin Xavier #define SQ_FR_PMR_PAGE_SIZE_LOG_PGSZ_2T 0x1dUL 3437a9a457f3SSelvin Xavier #define SQ_FR_PMR_PAGE_SIZE_LOG_PGSZ_4T 0x1eUL 3438a9a457f3SSelvin Xavier #define SQ_FR_PMR_PAGE_SIZE_LOG_PGSZ_8T 0x1fUL 3439a9a457f3SSelvin Xavier #define SQ_FR_PMR_PAGE_SIZE_LOG_LAST SQ_FR_PMR_PAGE_SIZE_LOG_PGSZ_8T 3440a9a457f3SSelvin Xavier #define SQ_FR_PMR_ZERO_BASED 0x20UL 3441a9a457f3SSelvin Xavier __le32 l_key; 3442a9a457f3SSelvin Xavier u8 length[5]; 3443a9a457f3SSelvin Xavier u8 reserved8_1; 3444a9a457f3SSelvin Xavier u8 reserved8_2; 3445a9a457f3SSelvin Xavier u8 numlevels_pbl_page_size_log; 3446a9a457f3SSelvin Xavier #define SQ_FR_PMR_PBL_PAGE_SIZE_LOG_MASK 0x1fUL 3447a9a457f3SSelvin Xavier #define SQ_FR_PMR_PBL_PAGE_SIZE_LOG_SFT 0 3448a9a457f3SSelvin Xavier #define SQ_FR_PMR_PBL_PAGE_SIZE_LOG_PGSZ_4K 0x0UL 3449a9a457f3SSelvin Xavier #define SQ_FR_PMR_PBL_PAGE_SIZE_LOG_PGSZ_8K 0x1UL 3450a9a457f3SSelvin Xavier #define SQ_FR_PMR_PBL_PAGE_SIZE_LOG_PGSZ_16K 0x2UL 3451a9a457f3SSelvin Xavier #define SQ_FR_PMR_PBL_PAGE_SIZE_LOG_PGSZ_32K 0x3UL 3452a9a457f3SSelvin Xavier #define SQ_FR_PMR_PBL_PAGE_SIZE_LOG_PGSZ_64K 0x4UL 3453a9a457f3SSelvin Xavier #define SQ_FR_PMR_PBL_PAGE_SIZE_LOG_PGSZ_128K 0x5UL 3454a9a457f3SSelvin Xavier #define SQ_FR_PMR_PBL_PAGE_SIZE_LOG_PGSZ_256K 0x6UL 3455a9a457f3SSelvin Xavier #define SQ_FR_PMR_PBL_PAGE_SIZE_LOG_PGSZ_512K 0x7UL 3456a9a457f3SSelvin Xavier #define SQ_FR_PMR_PBL_PAGE_SIZE_LOG_PGSZ_1M 0x8UL 3457a9a457f3SSelvin Xavier #define SQ_FR_PMR_PBL_PAGE_SIZE_LOG_PGSZ_2M 0x9UL 3458a9a457f3SSelvin Xavier #define SQ_FR_PMR_PBL_PAGE_SIZE_LOG_PGSZ_4M 0xaUL 3459a9a457f3SSelvin Xavier #define SQ_FR_PMR_PBL_PAGE_SIZE_LOG_PGSZ_8M 0xbUL 3460a9a457f3SSelvin Xavier #define SQ_FR_PMR_PBL_PAGE_SIZE_LOG_PGSZ_16M 0xcUL 3461a9a457f3SSelvin Xavier #define SQ_FR_PMR_PBL_PAGE_SIZE_LOG_PGSZ_32M 0xdUL 3462a9a457f3SSelvin Xavier #define SQ_FR_PMR_PBL_PAGE_SIZE_LOG_PGSZ_64M 0xeUL 3463a9a457f3SSelvin Xavier #define SQ_FR_PMR_PBL_PAGE_SIZE_LOG_PGSZ_128M 0xfUL 3464a9a457f3SSelvin Xavier #define SQ_FR_PMR_PBL_PAGE_SIZE_LOG_PGSZ_256M 0x10UL 3465a9a457f3SSelvin Xavier #define SQ_FR_PMR_PBL_PAGE_SIZE_LOG_PGSZ_512M 0x11UL 3466a9a457f3SSelvin Xavier #define SQ_FR_PMR_PBL_PAGE_SIZE_LOG_PGSZ_1G 0x12UL 3467a9a457f3SSelvin Xavier #define SQ_FR_PMR_PBL_PAGE_SIZE_LOG_PGSZ_2G 0x13UL 3468a9a457f3SSelvin Xavier #define SQ_FR_PMR_PBL_PAGE_SIZE_LOG_PGSZ_4G 0x14UL 3469a9a457f3SSelvin Xavier #define SQ_FR_PMR_PBL_PAGE_SIZE_LOG_PGSZ_8G 0x15UL 3470a9a457f3SSelvin Xavier #define SQ_FR_PMR_PBL_PAGE_SIZE_LOG_PGSZ_16G 0x16UL 3471a9a457f3SSelvin Xavier #define SQ_FR_PMR_PBL_PAGE_SIZE_LOG_PGSZ_32G 0x17UL 3472a9a457f3SSelvin Xavier #define SQ_FR_PMR_PBL_PAGE_SIZE_LOG_PGSZ_64G 0x18UL 3473a9a457f3SSelvin Xavier #define SQ_FR_PMR_PBL_PAGE_SIZE_LOG_PGSZ_128G 0x19UL 3474a9a457f3SSelvin Xavier #define SQ_FR_PMR_PBL_PAGE_SIZE_LOG_PGSZ_256G 0x1aUL 3475a9a457f3SSelvin Xavier #define SQ_FR_PMR_PBL_PAGE_SIZE_LOG_PGSZ_512G 0x1bUL 3476a9a457f3SSelvin Xavier #define SQ_FR_PMR_PBL_PAGE_SIZE_LOG_PGSZ_1T 0x1cUL 3477a9a457f3SSelvin Xavier #define SQ_FR_PMR_PBL_PAGE_SIZE_LOG_PGSZ_2T 0x1dUL 3478a9a457f3SSelvin Xavier #define SQ_FR_PMR_PBL_PAGE_SIZE_LOG_PGSZ_4T 0x1eUL 3479a9a457f3SSelvin Xavier #define SQ_FR_PMR_PBL_PAGE_SIZE_LOG_PGSZ_8T 0x1fUL 3480a9a457f3SSelvin Xavier #define SQ_FR_PMR_PBL_PAGE_SIZE_LOG_LAST SQ_FR_PMR_PBL_PAGE_SIZE_LOG_PGSZ_8T 3481a9a457f3SSelvin Xavier #define SQ_FR_PMR_NUMLEVELS_MASK 0xc0UL 3482a9a457f3SSelvin Xavier #define SQ_FR_PMR_NUMLEVELS_SFT 6 3483a9a457f3SSelvin Xavier #define SQ_FR_PMR_NUMLEVELS_PHYSICAL (0x0UL << 6) 3484a9a457f3SSelvin Xavier #define SQ_FR_PMR_NUMLEVELS_LAYER1 (0x1UL << 6) 3485a9a457f3SSelvin Xavier #define SQ_FR_PMR_NUMLEVELS_LAYER2 (0x2UL << 6) 3486a9a457f3SSelvin Xavier #define SQ_FR_PMR_NUMLEVELS_LAST SQ_FR_PMR_NUMLEVELS_LAYER2 3487a9a457f3SSelvin Xavier __le64 pblptr; 3488a9a457f3SSelvin Xavier __le64 va; 3489a9a457f3SSelvin Xavier __le32 data[24]; 3490a9a457f3SSelvin Xavier }; 3491a9a457f3SSelvin Xavier 3492a9a457f3SSelvin Xavier /* sq_fr_pmr_hdr (size:256b/32B) */ 3493a9a457f3SSelvin Xavier struct sq_fr_pmr_hdr { 3494a9a457f3SSelvin Xavier u8 wqe_type; 3495a9a457f3SSelvin Xavier #define SQ_FR_PMR_HDR_WQE_TYPE_FR_PMR 0xdUL 3496a9a457f3SSelvin Xavier #define SQ_FR_PMR_HDR_WQE_TYPE_LAST SQ_FR_PMR_HDR_WQE_TYPE_FR_PMR 3497a9a457f3SSelvin Xavier u8 flags; 3498a9a457f3SSelvin Xavier #define SQ_FR_PMR_HDR_FLAGS_SIGNAL_COMP 0x1UL 3499a9a457f3SSelvin Xavier #define SQ_FR_PMR_HDR_FLAGS_RD_OR_ATOMIC_FENCE 0x2UL 3500a9a457f3SSelvin Xavier #define SQ_FR_PMR_HDR_FLAGS_UC_FENCE 0x4UL 3501a9a457f3SSelvin Xavier #define SQ_FR_PMR_HDR_FLAGS_SE 0x8UL 3502a9a457f3SSelvin Xavier #define SQ_FR_PMR_HDR_FLAGS_INLINE 0x10UL 3503a9a457f3SSelvin Xavier #define SQ_FR_PMR_HDR_FLAGS_WQE_TS_EN 0x20UL 3504a9a457f3SSelvin Xavier #define SQ_FR_PMR_HDR_FLAGS_DEBUG_TRACE 0x40UL 3505a9a457f3SSelvin Xavier u8 access_cntl; 3506a9a457f3SSelvin Xavier #define SQ_FR_PMR_HDR_ACCESS_CNTL_LOCAL_WRITE 0x1UL 3507a9a457f3SSelvin Xavier #define SQ_FR_PMR_HDR_ACCESS_CNTL_REMOTE_READ 0x2UL 3508a9a457f3SSelvin Xavier #define SQ_FR_PMR_HDR_ACCESS_CNTL_REMOTE_WRITE 0x4UL 3509a9a457f3SSelvin Xavier #define SQ_FR_PMR_HDR_ACCESS_CNTL_REMOTE_ATOMIC 0x8UL 3510a9a457f3SSelvin Xavier #define SQ_FR_PMR_HDR_ACCESS_CNTL_WINDOW_BIND 0x10UL 3511a9a457f3SSelvin Xavier u8 zero_based_page_size_log; 3512a9a457f3SSelvin Xavier #define SQ_FR_PMR_HDR_PAGE_SIZE_LOG_MASK 0x1fUL 3513a9a457f3SSelvin Xavier #define SQ_FR_PMR_HDR_PAGE_SIZE_LOG_SFT 0 3514a9a457f3SSelvin Xavier #define SQ_FR_PMR_HDR_PAGE_SIZE_LOG_PGSZ_4K 0x0UL 3515a9a457f3SSelvin Xavier #define SQ_FR_PMR_HDR_PAGE_SIZE_LOG_PGSZ_8K 0x1UL 3516a9a457f3SSelvin Xavier #define SQ_FR_PMR_HDR_PAGE_SIZE_LOG_PGSZ_16K 0x2UL 3517a9a457f3SSelvin Xavier #define SQ_FR_PMR_HDR_PAGE_SIZE_LOG_PGSZ_32K 0x3UL 3518a9a457f3SSelvin Xavier #define SQ_FR_PMR_HDR_PAGE_SIZE_LOG_PGSZ_64K 0x4UL 3519a9a457f3SSelvin Xavier #define SQ_FR_PMR_HDR_PAGE_SIZE_LOG_PGSZ_128K 0x5UL 3520a9a457f3SSelvin Xavier #define SQ_FR_PMR_HDR_PAGE_SIZE_LOG_PGSZ_256K 0x6UL 3521a9a457f3SSelvin Xavier #define SQ_FR_PMR_HDR_PAGE_SIZE_LOG_PGSZ_512K 0x7UL 3522a9a457f3SSelvin Xavier #define SQ_FR_PMR_HDR_PAGE_SIZE_LOG_PGSZ_1M 0x8UL 3523a9a457f3SSelvin Xavier #define SQ_FR_PMR_HDR_PAGE_SIZE_LOG_PGSZ_2M 0x9UL 3524a9a457f3SSelvin Xavier #define SQ_FR_PMR_HDR_PAGE_SIZE_LOG_PGSZ_4M 0xaUL 3525a9a457f3SSelvin Xavier #define SQ_FR_PMR_HDR_PAGE_SIZE_LOG_PGSZ_8M 0xbUL 3526a9a457f3SSelvin Xavier #define SQ_FR_PMR_HDR_PAGE_SIZE_LOG_PGSZ_16M 0xcUL 3527a9a457f3SSelvin Xavier #define SQ_FR_PMR_HDR_PAGE_SIZE_LOG_PGSZ_32M 0xdUL 3528a9a457f3SSelvin Xavier #define SQ_FR_PMR_HDR_PAGE_SIZE_LOG_PGSZ_64M 0xeUL 3529a9a457f3SSelvin Xavier #define SQ_FR_PMR_HDR_PAGE_SIZE_LOG_PGSZ_128M 0xfUL 3530a9a457f3SSelvin Xavier #define SQ_FR_PMR_HDR_PAGE_SIZE_LOG_PGSZ_256M 0x10UL 3531a9a457f3SSelvin Xavier #define SQ_FR_PMR_HDR_PAGE_SIZE_LOG_PGSZ_512M 0x11UL 3532a9a457f3SSelvin Xavier #define SQ_FR_PMR_HDR_PAGE_SIZE_LOG_PGSZ_1G 0x12UL 3533a9a457f3SSelvin Xavier #define SQ_FR_PMR_HDR_PAGE_SIZE_LOG_PGSZ_2G 0x13UL 3534a9a457f3SSelvin Xavier #define SQ_FR_PMR_HDR_PAGE_SIZE_LOG_PGSZ_4G 0x14UL 3535a9a457f3SSelvin Xavier #define SQ_FR_PMR_HDR_PAGE_SIZE_LOG_PGSZ_8G 0x15UL 3536a9a457f3SSelvin Xavier #define SQ_FR_PMR_HDR_PAGE_SIZE_LOG_PGSZ_16G 0x16UL 3537a9a457f3SSelvin Xavier #define SQ_FR_PMR_HDR_PAGE_SIZE_LOG_PGSZ_32G 0x17UL 3538a9a457f3SSelvin Xavier #define SQ_FR_PMR_HDR_PAGE_SIZE_LOG_PGSZ_64G 0x18UL 3539a9a457f3SSelvin Xavier #define SQ_FR_PMR_HDR_PAGE_SIZE_LOG_PGSZ_128G 0x19UL 3540a9a457f3SSelvin Xavier #define SQ_FR_PMR_HDR_PAGE_SIZE_LOG_PGSZ_256G 0x1aUL 3541a9a457f3SSelvin Xavier #define SQ_FR_PMR_HDR_PAGE_SIZE_LOG_PGSZ_512G 0x1bUL 3542a9a457f3SSelvin Xavier #define SQ_FR_PMR_HDR_PAGE_SIZE_LOG_PGSZ_1T 0x1cUL 3543a9a457f3SSelvin Xavier #define SQ_FR_PMR_HDR_PAGE_SIZE_LOG_PGSZ_2T 0x1dUL 3544a9a457f3SSelvin Xavier #define SQ_FR_PMR_HDR_PAGE_SIZE_LOG_PGSZ_4T 0x1eUL 3545a9a457f3SSelvin Xavier #define SQ_FR_PMR_HDR_PAGE_SIZE_LOG_PGSZ_8T 0x1fUL 3546a9a457f3SSelvin Xavier #define SQ_FR_PMR_HDR_PAGE_SIZE_LOG_LAST SQ_FR_PMR_HDR_PAGE_SIZE_LOG_PGSZ_8T 3547a9a457f3SSelvin Xavier #define SQ_FR_PMR_HDR_ZERO_BASED 0x20UL 3548a9a457f3SSelvin Xavier __le32 l_key; 3549a9a457f3SSelvin Xavier u8 length[5]; 3550a9a457f3SSelvin Xavier u8 reserved8_1; 3551a9a457f3SSelvin Xavier u8 reserved8_2; 3552a9a457f3SSelvin Xavier u8 numlevels_pbl_page_size_log; 3553a9a457f3SSelvin Xavier #define SQ_FR_PMR_HDR_PBL_PAGE_SIZE_LOG_MASK 0x1fUL 3554a9a457f3SSelvin Xavier #define SQ_FR_PMR_HDR_PBL_PAGE_SIZE_LOG_SFT 0 3555a9a457f3SSelvin Xavier #define SQ_FR_PMR_HDR_PBL_PAGE_SIZE_LOG_PGSZ_4K 0x0UL 3556a9a457f3SSelvin Xavier #define SQ_FR_PMR_HDR_PBL_PAGE_SIZE_LOG_PGSZ_8K 0x1UL 3557a9a457f3SSelvin Xavier #define SQ_FR_PMR_HDR_PBL_PAGE_SIZE_LOG_PGSZ_16K 0x2UL 3558a9a457f3SSelvin Xavier #define SQ_FR_PMR_HDR_PBL_PAGE_SIZE_LOG_PGSZ_32K 0x3UL 3559a9a457f3SSelvin Xavier #define SQ_FR_PMR_HDR_PBL_PAGE_SIZE_LOG_PGSZ_64K 0x4UL 3560a9a457f3SSelvin Xavier #define SQ_FR_PMR_HDR_PBL_PAGE_SIZE_LOG_PGSZ_128K 0x5UL 3561a9a457f3SSelvin Xavier #define SQ_FR_PMR_HDR_PBL_PAGE_SIZE_LOG_PGSZ_256K 0x6UL 3562a9a457f3SSelvin Xavier #define SQ_FR_PMR_HDR_PBL_PAGE_SIZE_LOG_PGSZ_512K 0x7UL 3563a9a457f3SSelvin Xavier #define SQ_FR_PMR_HDR_PBL_PAGE_SIZE_LOG_PGSZ_1M 0x8UL 3564a9a457f3SSelvin Xavier #define SQ_FR_PMR_HDR_PBL_PAGE_SIZE_LOG_PGSZ_2M 0x9UL 3565a9a457f3SSelvin Xavier #define SQ_FR_PMR_HDR_PBL_PAGE_SIZE_LOG_PGSZ_4M 0xaUL 3566a9a457f3SSelvin Xavier #define SQ_FR_PMR_HDR_PBL_PAGE_SIZE_LOG_PGSZ_8M 0xbUL 3567a9a457f3SSelvin Xavier #define SQ_FR_PMR_HDR_PBL_PAGE_SIZE_LOG_PGSZ_16M 0xcUL 3568a9a457f3SSelvin Xavier #define SQ_FR_PMR_HDR_PBL_PAGE_SIZE_LOG_PGSZ_32M 0xdUL 3569a9a457f3SSelvin Xavier #define SQ_FR_PMR_HDR_PBL_PAGE_SIZE_LOG_PGSZ_64M 0xeUL 3570a9a457f3SSelvin Xavier #define SQ_FR_PMR_HDR_PBL_PAGE_SIZE_LOG_PGSZ_128M 0xfUL 3571a9a457f3SSelvin Xavier #define SQ_FR_PMR_HDR_PBL_PAGE_SIZE_LOG_PGSZ_256M 0x10UL 3572a9a457f3SSelvin Xavier #define SQ_FR_PMR_HDR_PBL_PAGE_SIZE_LOG_PGSZ_512M 0x11UL 3573a9a457f3SSelvin Xavier #define SQ_FR_PMR_HDR_PBL_PAGE_SIZE_LOG_PGSZ_1G 0x12UL 3574a9a457f3SSelvin Xavier #define SQ_FR_PMR_HDR_PBL_PAGE_SIZE_LOG_PGSZ_2G 0x13UL 3575a9a457f3SSelvin Xavier #define SQ_FR_PMR_HDR_PBL_PAGE_SIZE_LOG_PGSZ_4G 0x14UL 3576a9a457f3SSelvin Xavier #define SQ_FR_PMR_HDR_PBL_PAGE_SIZE_LOG_PGSZ_8G 0x15UL 3577a9a457f3SSelvin Xavier #define SQ_FR_PMR_HDR_PBL_PAGE_SIZE_LOG_PGSZ_16G 0x16UL 3578a9a457f3SSelvin Xavier #define SQ_FR_PMR_HDR_PBL_PAGE_SIZE_LOG_PGSZ_32G 0x17UL 3579a9a457f3SSelvin Xavier #define SQ_FR_PMR_HDR_PBL_PAGE_SIZE_LOG_PGSZ_64G 0x18UL 3580a9a457f3SSelvin Xavier #define SQ_FR_PMR_HDR_PBL_PAGE_SIZE_LOG_PGSZ_128G 0x19UL 3581a9a457f3SSelvin Xavier #define SQ_FR_PMR_HDR_PBL_PAGE_SIZE_LOG_PGSZ_256G 0x1aUL 3582a9a457f3SSelvin Xavier #define SQ_FR_PMR_HDR_PBL_PAGE_SIZE_LOG_PGSZ_512G 0x1bUL 3583a9a457f3SSelvin Xavier #define SQ_FR_PMR_HDR_PBL_PAGE_SIZE_LOG_PGSZ_1T 0x1cUL 3584a9a457f3SSelvin Xavier #define SQ_FR_PMR_HDR_PBL_PAGE_SIZE_LOG_PGSZ_2T 0x1dUL 3585a9a457f3SSelvin Xavier #define SQ_FR_PMR_HDR_PBL_PAGE_SIZE_LOG_PGSZ_4T 0x1eUL 3586a9a457f3SSelvin Xavier #define SQ_FR_PMR_HDR_PBL_PAGE_SIZE_LOG_PGSZ_8T 0x1fUL 3587a9a457f3SSelvin Xavier #define SQ_FR_PMR_HDR_PBL_PAGE_SIZE_LOG_LAST SQ_FR_PMR_HDR_PBL_PAGE_SIZE_LOG_PGSZ_8T 3588a9a457f3SSelvin Xavier #define SQ_FR_PMR_HDR_NUMLEVELS_MASK 0xc0UL 3589a9a457f3SSelvin Xavier #define SQ_FR_PMR_HDR_NUMLEVELS_SFT 6 3590a9a457f3SSelvin Xavier #define SQ_FR_PMR_HDR_NUMLEVELS_PHYSICAL (0x0UL << 6) 3591a9a457f3SSelvin Xavier #define SQ_FR_PMR_HDR_NUMLEVELS_LAYER1 (0x1UL << 6) 3592a9a457f3SSelvin Xavier #define SQ_FR_PMR_HDR_NUMLEVELS_LAYER2 (0x2UL << 6) 3593a9a457f3SSelvin Xavier #define SQ_FR_PMR_HDR_NUMLEVELS_LAST SQ_FR_PMR_HDR_NUMLEVELS_LAYER2 3594a9a457f3SSelvin Xavier __le64 pblptr; 3595a9a457f3SSelvin Xavier __le64 va; 3596a9a457f3SSelvin Xavier }; 3597a9a457f3SSelvin Xavier 3598a9a457f3SSelvin Xavier /* sq_bind (size:1024b/128B) */ 3599a9a457f3SSelvin Xavier struct sq_bind { 3600a9a457f3SSelvin Xavier u8 wqe_type; 3601a9a457f3SSelvin Xavier #define SQ_BIND_WQE_TYPE_BIND 0xeUL 3602a9a457f3SSelvin Xavier #define SQ_BIND_WQE_TYPE_LAST SQ_BIND_WQE_TYPE_BIND 3603a9a457f3SSelvin Xavier u8 flags; 3604a9a457f3SSelvin Xavier #define SQ_BIND_FLAGS_INLINE_SE_UC_FENCE_RD_OR_ATOMIC_FENCE_SIGNAL_COMP_MASK 0xffUL 3605a9a457f3SSelvin Xavier #define SQ_BIND_FLAGS_INLINE_SE_UC_FENCE_RD_OR_ATOMIC_FENCE_SIGNAL_COMP_SFT 0 3606a9a457f3SSelvin Xavier #define SQ_BIND_FLAGS_SIGNAL_COMP 0x1UL 3607a9a457f3SSelvin Xavier #define SQ_BIND_FLAGS_RD_OR_ATOMIC_FENCE 0x2UL 3608a9a457f3SSelvin Xavier #define SQ_BIND_FLAGS_UC_FENCE 0x4UL 3609a9a457f3SSelvin Xavier #define SQ_BIND_FLAGS_SE 0x8UL 3610a9a457f3SSelvin Xavier #define SQ_BIND_FLAGS_INLINE 0x10UL 3611a9a457f3SSelvin Xavier #define SQ_BIND_FLAGS_WQE_TS_EN 0x20UL 3612a9a457f3SSelvin Xavier #define SQ_BIND_FLAGS_DEBUG_TRACE 0x40UL 3613a9a457f3SSelvin Xavier u8 access_cntl; 3614a9a457f3SSelvin Xavier #define \ 3615a9a457f3SSelvin Xavier SQ_BIND_ACCESS_CNTL_WINDOW_BIND_REMOTE_ATOMIC_REMOTE_WRITE_REMOTE_READ_LOCAL_WRITE_MASK\ 3616a9a457f3SSelvin Xavier 0xffUL 3617a9a457f3SSelvin Xavier #define \ 3618a9a457f3SSelvin Xavier SQ_BIND_ACCESS_CNTL_WINDOW_BIND_REMOTE_ATOMIC_REMOTE_WRITE_REMOTE_READ_LOCAL_WRITE_SFT 0 3619a9a457f3SSelvin Xavier #define SQ_BIND_ACCESS_CNTL_LOCAL_WRITE 0x1UL 3620a9a457f3SSelvin Xavier #define SQ_BIND_ACCESS_CNTL_REMOTE_READ 0x2UL 3621a9a457f3SSelvin Xavier #define SQ_BIND_ACCESS_CNTL_REMOTE_WRITE 0x4UL 3622a9a457f3SSelvin Xavier #define SQ_BIND_ACCESS_CNTL_REMOTE_ATOMIC 0x8UL 3623a9a457f3SSelvin Xavier #define SQ_BIND_ACCESS_CNTL_WINDOW_BIND 0x10UL 3624a9a457f3SSelvin Xavier u8 reserved8_1; 3625a9a457f3SSelvin Xavier u8 mw_type_zero_based; 3626a9a457f3SSelvin Xavier #define SQ_BIND_ZERO_BASED 0x1UL 3627a9a457f3SSelvin Xavier #define SQ_BIND_MW_TYPE 0x2UL 3628a9a457f3SSelvin Xavier #define SQ_BIND_MW_TYPE_TYPE1 (0x0UL << 1) 3629a9a457f3SSelvin Xavier #define SQ_BIND_MW_TYPE_TYPE2 (0x1UL << 1) 3630a9a457f3SSelvin Xavier #define SQ_BIND_MW_TYPE_LAST SQ_BIND_MW_TYPE_TYPE2 3631a9a457f3SSelvin Xavier u8 reserved8_2; 3632a9a457f3SSelvin Xavier __le16 reserved16; 3633a9a457f3SSelvin Xavier __le32 parent_l_key; 3634a9a457f3SSelvin Xavier __le32 l_key; 3635a9a457f3SSelvin Xavier __le64 va; 3636a9a457f3SSelvin Xavier u8 length[5]; 3637a9a457f3SSelvin Xavier u8 reserved24[3]; 3638a9a457f3SSelvin Xavier __le32 data[24]; 3639a9a457f3SSelvin Xavier }; 3640a9a457f3SSelvin Xavier 3641a9a457f3SSelvin Xavier /* sq_bind_hdr (size:256b/32B) */ 3642a9a457f3SSelvin Xavier struct sq_bind_hdr { 3643a9a457f3SSelvin Xavier u8 wqe_type; 3644a9a457f3SSelvin Xavier #define SQ_BIND_HDR_WQE_TYPE_BIND 0xeUL 3645a9a457f3SSelvin Xavier #define SQ_BIND_HDR_WQE_TYPE_LAST SQ_BIND_HDR_WQE_TYPE_BIND 3646a9a457f3SSelvin Xavier u8 flags; 3647a9a457f3SSelvin Xavier #define SQ_BIND_HDR_FLAGS_INLINE_SE_UC_FENCE_RD_OR_ATOMIC_FENCE_SIGNAL_COMP_MASK 0xffUL 3648a9a457f3SSelvin Xavier #define SQ_BIND_HDR_FLAGS_INLINE_SE_UC_FENCE_RD_OR_ATOMIC_FENCE_SIGNAL_COMP_SFT 0 3649a9a457f3SSelvin Xavier #define SQ_BIND_HDR_FLAGS_SIGNAL_COMP 0x1UL 3650a9a457f3SSelvin Xavier #define SQ_BIND_HDR_FLAGS_RD_OR_ATOMIC_FENCE 0x2UL 3651a9a457f3SSelvin Xavier #define SQ_BIND_HDR_FLAGS_UC_FENCE 0x4UL 3652a9a457f3SSelvin Xavier #define SQ_BIND_HDR_FLAGS_SE 0x8UL 3653a9a457f3SSelvin Xavier #define SQ_BIND_HDR_FLAGS_INLINE 0x10UL 3654a9a457f3SSelvin Xavier #define SQ_BIND_HDR_FLAGS_WQE_TS_EN 0x20UL 3655a9a457f3SSelvin Xavier #define SQ_BIND_HDR_FLAGS_DEBUG_TRACE 0x40UL 3656a9a457f3SSelvin Xavier u8 access_cntl; 3657a9a457f3SSelvin Xavier #define \ 3658a9a457f3SSelvin Xavier SQ_BIND_HDR_ACCESS_CNTL_WINDOW_BIND_REMOTE_ATOMIC_REMOTE_WRITE_REMOTE_READ_LOCAL_WRITE_MASK\ 3659a9a457f3SSelvin Xavier 0xffUL 3660a9a457f3SSelvin Xavier #define \ 3661a9a457f3SSelvin Xavier SQ_BIND_HDR_ACCESS_CNTL_WINDOW_BIND_REMOTE_ATOMIC_REMOTE_WRITE_REMOTE_READ_LOCAL_WRITE_SFT \ 3662a9a457f3SSelvin Xavier 0 3663a9a457f3SSelvin Xavier #define SQ_BIND_HDR_ACCESS_CNTL_LOCAL_WRITE 0x1UL 3664a9a457f3SSelvin Xavier #define SQ_BIND_HDR_ACCESS_CNTL_REMOTE_READ 0x2UL 3665a9a457f3SSelvin Xavier #define SQ_BIND_HDR_ACCESS_CNTL_REMOTE_WRITE 0x4UL 3666a9a457f3SSelvin Xavier #define SQ_BIND_HDR_ACCESS_CNTL_REMOTE_ATOMIC 0x8UL 3667a9a457f3SSelvin Xavier #define SQ_BIND_HDR_ACCESS_CNTL_WINDOW_BIND 0x10UL 3668a9a457f3SSelvin Xavier u8 reserved8_1; 3669a9a457f3SSelvin Xavier u8 mw_type_zero_based; 3670a9a457f3SSelvin Xavier #define SQ_BIND_HDR_ZERO_BASED 0x1UL 3671a9a457f3SSelvin Xavier #define SQ_BIND_HDR_MW_TYPE 0x2UL 3672a9a457f3SSelvin Xavier #define SQ_BIND_HDR_MW_TYPE_TYPE1 (0x0UL << 1) 3673a9a457f3SSelvin Xavier #define SQ_BIND_HDR_MW_TYPE_TYPE2 (0x1UL << 1) 3674a9a457f3SSelvin Xavier #define SQ_BIND_HDR_MW_TYPE_LAST SQ_BIND_HDR_MW_TYPE_TYPE2 3675a9a457f3SSelvin Xavier u8 reserved8_2; 3676a9a457f3SSelvin Xavier __le16 reserved16; 3677a9a457f3SSelvin Xavier __le32 parent_l_key; 3678a9a457f3SSelvin Xavier __le32 l_key; 3679a9a457f3SSelvin Xavier __le64 va; 3680a9a457f3SSelvin Xavier u8 length[5]; 3681a9a457f3SSelvin Xavier u8 reserved24[3]; 3682a9a457f3SSelvin Xavier }; 3683a9a457f3SSelvin Xavier 3684a9a457f3SSelvin Xavier /* rq_wqe (size:1024b/128B) */ 3685a9a457f3SSelvin Xavier struct rq_wqe { 3686a9a457f3SSelvin Xavier u8 wqe_type; 3687a9a457f3SSelvin Xavier #define RQ_WQE_WQE_TYPE_RCV 0x80UL 3688a9a457f3SSelvin Xavier #define RQ_WQE_WQE_TYPE_LAST RQ_WQE_WQE_TYPE_RCV 3689a9a457f3SSelvin Xavier u8 flags; 3690a9a457f3SSelvin Xavier u8 wqe_size; 3691a9a457f3SSelvin Xavier u8 reserved8; 3692a9a457f3SSelvin Xavier __le32 reserved32; 3693a9a457f3SSelvin Xavier __le32 wr_id[2]; 3694a9a457f3SSelvin Xavier #define RQ_WQE_WR_ID_MASK 0xfffffUL 3695a9a457f3SSelvin Xavier #define RQ_WQE_WR_ID_SFT 0 3696a9a457f3SSelvin Xavier u8 reserved128[16]; 3697a9a457f3SSelvin Xavier __le32 data[24]; 3698a9a457f3SSelvin Xavier }; 3699a9a457f3SSelvin Xavier 3700a9a457f3SSelvin Xavier /* rq_wqe_hdr (size:256b/32B) */ 3701a9a457f3SSelvin Xavier struct rq_wqe_hdr { 3702a9a457f3SSelvin Xavier u8 wqe_type; 3703a9a457f3SSelvin Xavier #define RQ_WQE_HDR_WQE_TYPE_RCV 0x80UL 3704a9a457f3SSelvin Xavier #define RQ_WQE_HDR_WQE_TYPE_LAST RQ_WQE_HDR_WQE_TYPE_RCV 3705a9a457f3SSelvin Xavier u8 flags; 3706a9a457f3SSelvin Xavier u8 wqe_size; 3707a9a457f3SSelvin Xavier u8 reserved8; 3708a9a457f3SSelvin Xavier __le32 reserved32; 3709a9a457f3SSelvin Xavier __le32 wr_id[2]; 3710a9a457f3SSelvin Xavier #define RQ_WQE_HDR_WR_ID_MASK 0xfffffUL 3711a9a457f3SSelvin Xavier #define RQ_WQE_HDR_WR_ID_SFT 0 3712a9a457f3SSelvin Xavier u8 reserved128[16]; 3713a9a457f3SSelvin Xavier }; 3714a9a457f3SSelvin Xavier 3715a9a457f3SSelvin Xavier /* cq_base (size:256b/32B) */ 3716a9a457f3SSelvin Xavier struct cq_base { 3717a9a457f3SSelvin Xavier __le64 reserved64_1; 3718a9a457f3SSelvin Xavier __le64 reserved64_2; 3719a9a457f3SSelvin Xavier __le64 reserved64_3; 3720a9a457f3SSelvin Xavier u8 cqe_type_toggle; 3721a9a457f3SSelvin Xavier #define CQ_BASE_TOGGLE 0x1UL 3722a9a457f3SSelvin Xavier #define CQ_BASE_CQE_TYPE_MASK 0x1eUL 3723a9a457f3SSelvin Xavier #define CQ_BASE_CQE_TYPE_SFT 1 3724a9a457f3SSelvin Xavier #define CQ_BASE_CQE_TYPE_REQ (0x0UL << 1) 3725a9a457f3SSelvin Xavier #define CQ_BASE_CQE_TYPE_RES_RC (0x1UL << 1) 3726a9a457f3SSelvin Xavier #define CQ_BASE_CQE_TYPE_RES_UD (0x2UL << 1) 3727a9a457f3SSelvin Xavier #define CQ_BASE_CQE_TYPE_RES_RAWETH_QP1 (0x3UL << 1) 3728a9a457f3SSelvin Xavier #define CQ_BASE_CQE_TYPE_RES_UD_CFA (0x4UL << 1) 37299a54460bSSelvin Xavier #define CQ_BASE_CQE_TYPE_REQ_V3 (0x8UL << 1) 37309a54460bSSelvin Xavier #define CQ_BASE_CQE_TYPE_RES_RC_V3 (0x9UL << 1) 37319a54460bSSelvin Xavier #define CQ_BASE_CQE_TYPE_RES_UD_V3 (0xaUL << 1) 37329a54460bSSelvin Xavier #define CQ_BASE_CQE_TYPE_RES_RAWETH_QP1_V3 (0xbUL << 1) 37339a54460bSSelvin Xavier #define CQ_BASE_CQE_TYPE_RES_UD_CFA_V3 (0xcUL << 1) 3734a9a457f3SSelvin Xavier #define CQ_BASE_CQE_TYPE_NO_OP (0xdUL << 1) 3735a9a457f3SSelvin Xavier #define CQ_BASE_CQE_TYPE_TERMINAL (0xeUL << 1) 3736a9a457f3SSelvin Xavier #define CQ_BASE_CQE_TYPE_CUT_OFF (0xfUL << 1) 3737a9a457f3SSelvin Xavier #define CQ_BASE_CQE_TYPE_LAST CQ_BASE_CQE_TYPE_CUT_OFF 3738a9a457f3SSelvin Xavier u8 status; 37399a54460bSSelvin Xavier #define CQ_BASE_STATUS_OK 0x0UL 37409a54460bSSelvin Xavier #define CQ_BASE_STATUS_BAD_RESPONSE_ERR 0x1UL 37419a54460bSSelvin Xavier #define CQ_BASE_STATUS_LOCAL_LENGTH_ERR 0x2UL 37429a54460bSSelvin Xavier #define CQ_BASE_STATUS_HW_LOCAL_LENGTH_ERR 0x3UL 37439a54460bSSelvin Xavier #define CQ_BASE_STATUS_LOCAL_QP_OPERATION_ERR 0x4UL 37449a54460bSSelvin Xavier #define CQ_BASE_STATUS_LOCAL_PROTECTION_ERR 0x5UL 37459a54460bSSelvin Xavier #define CQ_BASE_STATUS_LOCAL_ACCESS_ERROR 0x6UL 37469a54460bSSelvin Xavier #define CQ_BASE_STATUS_MEMORY_MGT_OPERATION_ERR 0x7UL 37479a54460bSSelvin Xavier #define CQ_BASE_STATUS_REMOTE_INVALID_REQUEST_ERR 0x8UL 37489a54460bSSelvin Xavier #define CQ_BASE_STATUS_REMOTE_ACCESS_ERR 0x9UL 37499a54460bSSelvin Xavier #define CQ_BASE_STATUS_REMOTE_OPERATION_ERR 0xaUL 37509a54460bSSelvin Xavier #define CQ_BASE_STATUS_RNR_NAK_RETRY_CNT_ERR 0xbUL 37519a54460bSSelvin Xavier #define CQ_BASE_STATUS_TRANSPORT_RETRY_CNT_ERR 0xcUL 37529a54460bSSelvin Xavier #define CQ_BASE_STATUS_WORK_REQUEST_FLUSHED_ERR 0xdUL 37539a54460bSSelvin Xavier #define CQ_BASE_STATUS_HW_FLUSH_ERR 0xeUL 37549a54460bSSelvin Xavier #define CQ_BASE_STATUS_OVERFLOW_ERR 0xfUL 37559a54460bSSelvin Xavier #define CQ_BASE_STATUS_LAST CQ_BASE_STATUS_OVERFLOW_ERR 3756a9a457f3SSelvin Xavier __le16 reserved16; 37579a54460bSSelvin Xavier __le32 opaque; 3758a9a457f3SSelvin Xavier }; 3759a9a457f3SSelvin Xavier 3760a9a457f3SSelvin Xavier /* cq_req (size:256b/32B) */ 3761a9a457f3SSelvin Xavier struct cq_req { 3762a9a457f3SSelvin Xavier __le64 qp_handle; 3763a9a457f3SSelvin Xavier __le16 sq_cons_idx; 3764a9a457f3SSelvin Xavier __le16 reserved16_1; 3765a9a457f3SSelvin Xavier __le32 reserved32_2; 3766a9a457f3SSelvin Xavier __le64 reserved64; 3767a9a457f3SSelvin Xavier u8 cqe_type_toggle; 3768a9a457f3SSelvin Xavier #define CQ_REQ_TOGGLE 0x1UL 3769a9a457f3SSelvin Xavier #define CQ_REQ_CQE_TYPE_MASK 0x1eUL 3770a9a457f3SSelvin Xavier #define CQ_REQ_CQE_TYPE_SFT 1 3771a9a457f3SSelvin Xavier #define CQ_REQ_CQE_TYPE_REQ (0x0UL << 1) 3772a9a457f3SSelvin Xavier #define CQ_REQ_CQE_TYPE_LAST CQ_REQ_CQE_TYPE_REQ 3773a9a457f3SSelvin Xavier #define CQ_REQ_PUSH 0x20UL 3774a9a457f3SSelvin Xavier u8 status; 3775a9a457f3SSelvin Xavier #define CQ_REQ_STATUS_OK 0x0UL 3776a9a457f3SSelvin Xavier #define CQ_REQ_STATUS_BAD_RESPONSE_ERR 0x1UL 3777a9a457f3SSelvin Xavier #define CQ_REQ_STATUS_LOCAL_LENGTH_ERR 0x2UL 3778a9a457f3SSelvin Xavier #define CQ_REQ_STATUS_LOCAL_QP_OPERATION_ERR 0x3UL 3779a9a457f3SSelvin Xavier #define CQ_REQ_STATUS_LOCAL_PROTECTION_ERR 0x4UL 3780a9a457f3SSelvin Xavier #define CQ_REQ_STATUS_MEMORY_MGT_OPERATION_ERR 0x5UL 3781a9a457f3SSelvin Xavier #define CQ_REQ_STATUS_REMOTE_INVALID_REQUEST_ERR 0x6UL 3782a9a457f3SSelvin Xavier #define CQ_REQ_STATUS_REMOTE_ACCESS_ERR 0x7UL 3783a9a457f3SSelvin Xavier #define CQ_REQ_STATUS_REMOTE_OPERATION_ERR 0x8UL 3784a9a457f3SSelvin Xavier #define CQ_REQ_STATUS_RNR_NAK_RETRY_CNT_ERR 0x9UL 3785a9a457f3SSelvin Xavier #define CQ_REQ_STATUS_TRANSPORT_RETRY_CNT_ERR 0xaUL 3786a9a457f3SSelvin Xavier #define CQ_REQ_STATUS_WORK_REQUEST_FLUSHED_ERR 0xbUL 3787a9a457f3SSelvin Xavier #define CQ_REQ_STATUS_LAST CQ_REQ_STATUS_WORK_REQUEST_FLUSHED_ERR 3788a9a457f3SSelvin Xavier __le16 reserved16_2; 3789a9a457f3SSelvin Xavier __le32 reserved32_1; 3790a9a457f3SSelvin Xavier }; 3791a9a457f3SSelvin Xavier 3792a9a457f3SSelvin Xavier /* cq_res_rc (size:256b/32B) */ 3793a9a457f3SSelvin Xavier struct cq_res_rc { 3794a9a457f3SSelvin Xavier __le32 length; 3795a9a457f3SSelvin Xavier __le32 imm_data_or_inv_r_key; 3796a9a457f3SSelvin Xavier __le64 qp_handle; 3797a9a457f3SSelvin Xavier __le64 mr_handle; 3798a9a457f3SSelvin Xavier u8 cqe_type_toggle; 3799a9a457f3SSelvin Xavier #define CQ_RES_RC_TOGGLE 0x1UL 3800a9a457f3SSelvin Xavier #define CQ_RES_RC_CQE_TYPE_MASK 0x1eUL 3801a9a457f3SSelvin Xavier #define CQ_RES_RC_CQE_TYPE_SFT 1 3802a9a457f3SSelvin Xavier #define CQ_RES_RC_CQE_TYPE_RES_RC (0x1UL << 1) 3803a9a457f3SSelvin Xavier #define CQ_RES_RC_CQE_TYPE_LAST CQ_RES_RC_CQE_TYPE_RES_RC 3804a9a457f3SSelvin Xavier u8 status; 3805a9a457f3SSelvin Xavier #define CQ_RES_RC_STATUS_OK 0x0UL 3806a9a457f3SSelvin Xavier #define CQ_RES_RC_STATUS_LOCAL_ACCESS_ERROR 0x1UL 3807a9a457f3SSelvin Xavier #define CQ_RES_RC_STATUS_LOCAL_LENGTH_ERR 0x2UL 3808a9a457f3SSelvin Xavier #define CQ_RES_RC_STATUS_LOCAL_PROTECTION_ERR 0x3UL 3809a9a457f3SSelvin Xavier #define CQ_RES_RC_STATUS_LOCAL_QP_OPERATION_ERR 0x4UL 3810a9a457f3SSelvin Xavier #define CQ_RES_RC_STATUS_MEMORY_MGT_OPERATION_ERR 0x5UL 3811a9a457f3SSelvin Xavier #define CQ_RES_RC_STATUS_REMOTE_INVALID_REQUEST_ERR 0x6UL 3812a9a457f3SSelvin Xavier #define CQ_RES_RC_STATUS_WORK_REQUEST_FLUSHED_ERR 0x7UL 3813a9a457f3SSelvin Xavier #define CQ_RES_RC_STATUS_HW_FLUSH_ERR 0x8UL 3814a9a457f3SSelvin Xavier #define CQ_RES_RC_STATUS_LAST CQ_RES_RC_STATUS_HW_FLUSH_ERR 3815a9a457f3SSelvin Xavier __le16 flags; 3816a9a457f3SSelvin Xavier #define CQ_RES_RC_FLAGS_SRQ 0x1UL 3817a9a457f3SSelvin Xavier #define CQ_RES_RC_FLAGS_SRQ_RQ 0x0UL 3818a9a457f3SSelvin Xavier #define CQ_RES_RC_FLAGS_SRQ_SRQ 0x1UL 3819a9a457f3SSelvin Xavier #define CQ_RES_RC_FLAGS_SRQ_LAST CQ_RES_RC_FLAGS_SRQ_SRQ 3820a9a457f3SSelvin Xavier #define CQ_RES_RC_FLAGS_IMM 0x2UL 3821a9a457f3SSelvin Xavier #define CQ_RES_RC_FLAGS_INV 0x4UL 3822a9a457f3SSelvin Xavier #define CQ_RES_RC_FLAGS_RDMA 0x8UL 3823a9a457f3SSelvin Xavier #define CQ_RES_RC_FLAGS_RDMA_SEND (0x0UL << 3) 3824a9a457f3SSelvin Xavier #define CQ_RES_RC_FLAGS_RDMA_RDMA_WRITE (0x1UL << 3) 3825a9a457f3SSelvin Xavier #define CQ_RES_RC_FLAGS_RDMA_LAST CQ_RES_RC_FLAGS_RDMA_RDMA_WRITE 3826a9a457f3SSelvin Xavier __le32 srq_or_rq_wr_id; 3827a9a457f3SSelvin Xavier #define CQ_RES_RC_SRQ_OR_RQ_WR_ID_MASK 0xfffffUL 3828a9a457f3SSelvin Xavier #define CQ_RES_RC_SRQ_OR_RQ_WR_ID_SFT 0 3829a9a457f3SSelvin Xavier }; 3830a9a457f3SSelvin Xavier 3831a9a457f3SSelvin Xavier /* cq_res_ud (size:256b/32B) */ 3832a9a457f3SSelvin Xavier struct cq_res_ud { 3833a9a457f3SSelvin Xavier __le16 length; 3834a9a457f3SSelvin Xavier #define CQ_RES_UD_LENGTH_MASK 0x3fffUL 3835a9a457f3SSelvin Xavier #define CQ_RES_UD_LENGTH_SFT 0 3836a9a457f3SSelvin Xavier __le16 cfa_metadata; 3837a9a457f3SSelvin Xavier #define CQ_RES_UD_CFA_METADATA_VID_MASK 0xfffUL 3838a9a457f3SSelvin Xavier #define CQ_RES_UD_CFA_METADATA_VID_SFT 0 3839a9a457f3SSelvin Xavier #define CQ_RES_UD_CFA_METADATA_DE 0x1000UL 3840a9a457f3SSelvin Xavier #define CQ_RES_UD_CFA_METADATA_PRI_MASK 0xe000UL 3841a9a457f3SSelvin Xavier #define CQ_RES_UD_CFA_METADATA_PRI_SFT 13 3842a9a457f3SSelvin Xavier __le32 imm_data; 3843a9a457f3SSelvin Xavier __le64 qp_handle; 3844a9a457f3SSelvin Xavier __le16 src_mac[3]; 3845a9a457f3SSelvin Xavier __le16 src_qp_low; 3846a9a457f3SSelvin Xavier u8 cqe_type_toggle; 3847a9a457f3SSelvin Xavier #define CQ_RES_UD_TOGGLE 0x1UL 3848a9a457f3SSelvin Xavier #define CQ_RES_UD_CQE_TYPE_MASK 0x1eUL 3849a9a457f3SSelvin Xavier #define CQ_RES_UD_CQE_TYPE_SFT 1 3850a9a457f3SSelvin Xavier #define CQ_RES_UD_CQE_TYPE_RES_UD (0x2UL << 1) 3851a9a457f3SSelvin Xavier #define CQ_RES_UD_CQE_TYPE_LAST CQ_RES_UD_CQE_TYPE_RES_UD 3852a9a457f3SSelvin Xavier u8 status; 3853a9a457f3SSelvin Xavier #define CQ_RES_UD_STATUS_OK 0x0UL 3854a9a457f3SSelvin Xavier #define CQ_RES_UD_STATUS_LOCAL_ACCESS_ERROR 0x1UL 3855a9a457f3SSelvin Xavier #define CQ_RES_UD_STATUS_HW_LOCAL_LENGTH_ERR 0x2UL 3856a9a457f3SSelvin Xavier #define CQ_RES_UD_STATUS_LOCAL_PROTECTION_ERR 0x3UL 3857a9a457f3SSelvin Xavier #define CQ_RES_UD_STATUS_LOCAL_QP_OPERATION_ERR 0x4UL 3858a9a457f3SSelvin Xavier #define CQ_RES_UD_STATUS_MEMORY_MGT_OPERATION_ERR 0x5UL 3859a9a457f3SSelvin Xavier #define CQ_RES_UD_STATUS_WORK_REQUEST_FLUSHED_ERR 0x7UL 3860a9a457f3SSelvin Xavier #define CQ_RES_UD_STATUS_HW_FLUSH_ERR 0x8UL 3861a9a457f3SSelvin Xavier #define CQ_RES_UD_STATUS_LAST CQ_RES_UD_STATUS_HW_FLUSH_ERR 3862a9a457f3SSelvin Xavier __le16 flags; 3863a9a457f3SSelvin Xavier #define CQ_RES_UD_FLAGS_SRQ 0x1UL 3864a9a457f3SSelvin Xavier #define CQ_RES_UD_FLAGS_SRQ_RQ 0x0UL 3865a9a457f3SSelvin Xavier #define CQ_RES_UD_FLAGS_SRQ_SRQ 0x1UL 3866a9a457f3SSelvin Xavier #define CQ_RES_UD_FLAGS_SRQ_LAST CQ_RES_UD_FLAGS_SRQ_SRQ 3867a9a457f3SSelvin Xavier #define CQ_RES_UD_FLAGS_IMM 0x2UL 3868a9a457f3SSelvin Xavier #define CQ_RES_UD_FLAGS_UNUSED_MASK 0xcUL 3869a9a457f3SSelvin Xavier #define CQ_RES_UD_FLAGS_UNUSED_SFT 2 3870a9a457f3SSelvin Xavier #define CQ_RES_UD_FLAGS_ROCE_IP_VER_MASK 0x30UL 3871a9a457f3SSelvin Xavier #define CQ_RES_UD_FLAGS_ROCE_IP_VER_SFT 4 3872a9a457f3SSelvin Xavier #define CQ_RES_UD_FLAGS_ROCE_IP_VER_V1 (0x0UL << 4) 3873a9a457f3SSelvin Xavier #define CQ_RES_UD_FLAGS_ROCE_IP_VER_V2IPV4 (0x2UL << 4) 3874a9a457f3SSelvin Xavier #define CQ_RES_UD_FLAGS_ROCE_IP_VER_V2IPV6 (0x3UL << 4) 3875a9a457f3SSelvin Xavier #define CQ_RES_UD_FLAGS_ROCE_IP_VER_LAST CQ_RES_UD_FLAGS_ROCE_IP_VER_V2IPV6 3876a9a457f3SSelvin Xavier #define CQ_RES_UD_FLAGS_META_FORMAT_MASK 0x3c0UL 3877a9a457f3SSelvin Xavier #define CQ_RES_UD_FLAGS_META_FORMAT_SFT 6 3878a9a457f3SSelvin Xavier #define CQ_RES_UD_FLAGS_META_FORMAT_NONE (0x0UL << 6) 3879a9a457f3SSelvin Xavier #define CQ_RES_UD_FLAGS_META_FORMAT_VLAN (0x1UL << 6) 3880a9a457f3SSelvin Xavier #define CQ_RES_UD_FLAGS_META_FORMAT_TUNNEL_ID (0x2UL << 6) 3881a9a457f3SSelvin Xavier #define CQ_RES_UD_FLAGS_META_FORMAT_CHDR_DATA (0x3UL << 6) 3882a9a457f3SSelvin Xavier #define CQ_RES_UD_FLAGS_META_FORMAT_HDR_OFFSET (0x4UL << 6) 3883a9a457f3SSelvin Xavier #define CQ_RES_UD_FLAGS_META_FORMAT_LAST CQ_RES_UD_FLAGS_META_FORMAT_HDR_OFFSET 3884a9a457f3SSelvin Xavier #define CQ_RES_UD_FLAGS_EXT_META_FORMAT_MASK 0xc00UL 3885a9a457f3SSelvin Xavier #define CQ_RES_UD_FLAGS_EXT_META_FORMAT_SFT 10 3886a9a457f3SSelvin Xavier __le32 src_qp_high_srq_or_rq_wr_id; 3887a9a457f3SSelvin Xavier #define CQ_RES_UD_SRQ_OR_RQ_WR_ID_MASK 0xfffffUL 3888a9a457f3SSelvin Xavier #define CQ_RES_UD_SRQ_OR_RQ_WR_ID_SFT 0 3889a9a457f3SSelvin Xavier #define CQ_RES_UD_SRC_QP_HIGH_MASK 0xff000000UL 3890a9a457f3SSelvin Xavier #define CQ_RES_UD_SRC_QP_HIGH_SFT 24 3891a9a457f3SSelvin Xavier }; 3892a9a457f3SSelvin Xavier 3893a9a457f3SSelvin Xavier /* cq_res_ud_v2 (size:256b/32B) */ 3894a9a457f3SSelvin Xavier struct cq_res_ud_v2 { 3895a9a457f3SSelvin Xavier __le16 length; 3896a9a457f3SSelvin Xavier #define CQ_RES_UD_V2_LENGTH_MASK 0x3fffUL 3897a9a457f3SSelvin Xavier #define CQ_RES_UD_V2_LENGTH_SFT 0 3898a9a457f3SSelvin Xavier __le16 cfa_metadata0; 3899a9a457f3SSelvin Xavier #define CQ_RES_UD_V2_CFA_METADATA0_VID_MASK 0xfffUL 3900a9a457f3SSelvin Xavier #define CQ_RES_UD_V2_CFA_METADATA0_VID_SFT 0 3901a9a457f3SSelvin Xavier #define CQ_RES_UD_V2_CFA_METADATA0_DE 0x1000UL 3902a9a457f3SSelvin Xavier #define CQ_RES_UD_V2_CFA_METADATA0_PRI_MASK 0xe000UL 3903a9a457f3SSelvin Xavier #define CQ_RES_UD_V2_CFA_METADATA0_PRI_SFT 13 3904a9a457f3SSelvin Xavier __le32 imm_data; 3905a9a457f3SSelvin Xavier __le64 qp_handle; 3906a9a457f3SSelvin Xavier __le16 src_mac[3]; 3907a9a457f3SSelvin Xavier __le16 src_qp_low; 3908a9a457f3SSelvin Xavier u8 cqe_type_toggle; 3909a9a457f3SSelvin Xavier #define CQ_RES_UD_V2_TOGGLE 0x1UL 3910a9a457f3SSelvin Xavier #define CQ_RES_UD_V2_CQE_TYPE_MASK 0x1eUL 3911a9a457f3SSelvin Xavier #define CQ_RES_UD_V2_CQE_TYPE_SFT 1 3912a9a457f3SSelvin Xavier #define CQ_RES_UD_V2_CQE_TYPE_RES_UD (0x2UL << 1) 3913a9a457f3SSelvin Xavier #define CQ_RES_UD_V2_CQE_TYPE_LAST CQ_RES_UD_V2_CQE_TYPE_RES_UD 3914a9a457f3SSelvin Xavier u8 status; 3915a9a457f3SSelvin Xavier #define CQ_RES_UD_V2_STATUS_OK 0x0UL 3916a9a457f3SSelvin Xavier #define CQ_RES_UD_V2_STATUS_LOCAL_ACCESS_ERROR 0x1UL 3917a9a457f3SSelvin Xavier #define CQ_RES_UD_V2_STATUS_HW_LOCAL_LENGTH_ERR 0x2UL 3918a9a457f3SSelvin Xavier #define CQ_RES_UD_V2_STATUS_LOCAL_PROTECTION_ERR 0x3UL 3919a9a457f3SSelvin Xavier #define CQ_RES_UD_V2_STATUS_LOCAL_QP_OPERATION_ERR 0x4UL 3920a9a457f3SSelvin Xavier #define CQ_RES_UD_V2_STATUS_MEMORY_MGT_OPERATION_ERR 0x5UL 3921a9a457f3SSelvin Xavier #define CQ_RES_UD_V2_STATUS_WORK_REQUEST_FLUSHED_ERR 0x7UL 3922a9a457f3SSelvin Xavier #define CQ_RES_UD_V2_STATUS_HW_FLUSH_ERR 0x8UL 3923a9a457f3SSelvin Xavier #define CQ_RES_UD_V2_STATUS_LAST CQ_RES_UD_V2_STATUS_HW_FLUSH_ERR 3924a9a457f3SSelvin Xavier __le16 flags; 3925a9a457f3SSelvin Xavier #define CQ_RES_UD_V2_FLAGS_SRQ 0x1UL 3926a9a457f3SSelvin Xavier #define CQ_RES_UD_V2_FLAGS_SRQ_RQ 0x0UL 3927a9a457f3SSelvin Xavier #define CQ_RES_UD_V2_FLAGS_SRQ_SRQ 0x1UL 3928a9a457f3SSelvin Xavier #define CQ_RES_UD_V2_FLAGS_SRQ_LAST CQ_RES_UD_V2_FLAGS_SRQ_SRQ 3929a9a457f3SSelvin Xavier #define CQ_RES_UD_V2_FLAGS_IMM 0x2UL 3930a9a457f3SSelvin Xavier #define CQ_RES_UD_V2_FLAGS_UNUSED_MASK 0xcUL 3931a9a457f3SSelvin Xavier #define CQ_RES_UD_V2_FLAGS_UNUSED_SFT 2 3932a9a457f3SSelvin Xavier #define CQ_RES_UD_V2_FLAGS_ROCE_IP_VER_MASK 0x30UL 3933a9a457f3SSelvin Xavier #define CQ_RES_UD_V2_FLAGS_ROCE_IP_VER_SFT 4 3934a9a457f3SSelvin Xavier #define CQ_RES_UD_V2_FLAGS_ROCE_IP_VER_V1 (0x0UL << 4) 3935a9a457f3SSelvin Xavier #define CQ_RES_UD_V2_FLAGS_ROCE_IP_VER_V2IPV4 (0x2UL << 4) 3936a9a457f3SSelvin Xavier #define CQ_RES_UD_V2_FLAGS_ROCE_IP_VER_V2IPV6 (0x3UL << 4) 3937a9a457f3SSelvin Xavier #define CQ_RES_UD_V2_FLAGS_ROCE_IP_VER_LAST CQ_RES_UD_V2_FLAGS_ROCE_IP_VER_V2IPV6 3938a9a457f3SSelvin Xavier #define CQ_RES_UD_V2_FLAGS_META_FORMAT_MASK 0x3c0UL 3939a9a457f3SSelvin Xavier #define CQ_RES_UD_V2_FLAGS_META_FORMAT_SFT 6 3940a9a457f3SSelvin Xavier #define CQ_RES_UD_V2_FLAGS_META_FORMAT_NONE (0x0UL << 6) 3941a9a457f3SSelvin Xavier #define CQ_RES_UD_V2_FLAGS_META_FORMAT_ACT_REC_PTR (0x1UL << 6) 3942a9a457f3SSelvin Xavier #define CQ_RES_UD_V2_FLAGS_META_FORMAT_TUNNEL_ID (0x2UL << 6) 3943a9a457f3SSelvin Xavier #define CQ_RES_UD_V2_FLAGS_META_FORMAT_CHDR_DATA (0x3UL << 6) 3944a9a457f3SSelvin Xavier #define CQ_RES_UD_V2_FLAGS_META_FORMAT_HDR_OFFSET (0x4UL << 6) 3945a9a457f3SSelvin Xavier #define CQ_RES_UD_V2_FLAGS_META_FORMAT_LAST CQ_RES_UD_V2_FLAGS_META_FORMAT_HDR_OFFSET 3946a9a457f3SSelvin Xavier __le32 src_qp_high_srq_or_rq_wr_id; 3947a9a457f3SSelvin Xavier #define CQ_RES_UD_V2_SRQ_OR_RQ_WR_ID_MASK 0xfffffUL 3948a9a457f3SSelvin Xavier #define CQ_RES_UD_V2_SRQ_OR_RQ_WR_ID_SFT 0 3949a9a457f3SSelvin Xavier #define CQ_RES_UD_V2_CFA_METADATA1_MASK 0xf00000UL 3950a9a457f3SSelvin Xavier #define CQ_RES_UD_V2_CFA_METADATA1_SFT 20 3951a9a457f3SSelvin Xavier #define CQ_RES_UD_V2_CFA_METADATA1_TPID_SEL_MASK 0x700000UL 3952a9a457f3SSelvin Xavier #define CQ_RES_UD_V2_CFA_METADATA1_TPID_SEL_SFT 20 3953a9a457f3SSelvin Xavier #define CQ_RES_UD_V2_CFA_METADATA1_TPID_SEL_TPID88A8 (0x0UL << 20) 3954a9a457f3SSelvin Xavier #define CQ_RES_UD_V2_CFA_METADATA1_TPID_SEL_TPID8100 (0x1UL << 20) 3955a9a457f3SSelvin Xavier #define CQ_RES_UD_V2_CFA_METADATA1_TPID_SEL_TPID9100 (0x2UL << 20) 3956a9a457f3SSelvin Xavier #define CQ_RES_UD_V2_CFA_METADATA1_TPID_SEL_TPID9200 (0x3UL << 20) 3957a9a457f3SSelvin Xavier #define CQ_RES_UD_V2_CFA_METADATA1_TPID_SEL_TPID9300 (0x4UL << 20) 3958a9a457f3SSelvin Xavier #define CQ_RES_UD_V2_CFA_METADATA1_TPID_SEL_TPIDCFG (0x5UL << 20) 3959a9a457f3SSelvin Xavier #define CQ_RES_UD_V2_CFA_METADATA1_TPID_SEL_LAST CQ_RES_UD_V2_CFA_METADATA1_TPID_SEL_TPIDCFG 3960a9a457f3SSelvin Xavier #define CQ_RES_UD_V2_CFA_METADATA1_VALID 0x800000UL 3961a9a457f3SSelvin Xavier #define CQ_RES_UD_V2_SRC_QP_HIGH_MASK 0xff000000UL 3962a9a457f3SSelvin Xavier #define CQ_RES_UD_V2_SRC_QP_HIGH_SFT 24 3963a9a457f3SSelvin Xavier }; 3964a9a457f3SSelvin Xavier 3965a9a457f3SSelvin Xavier /* cq_res_ud_cfa (size:256b/32B) */ 3966a9a457f3SSelvin Xavier struct cq_res_ud_cfa { 3967a9a457f3SSelvin Xavier __le16 length; 3968a9a457f3SSelvin Xavier #define CQ_RES_UD_CFA_LENGTH_MASK 0x3fffUL 3969a9a457f3SSelvin Xavier #define CQ_RES_UD_CFA_LENGTH_SFT 0 3970a9a457f3SSelvin Xavier __le16 cfa_code; 3971a9a457f3SSelvin Xavier __le32 imm_data; 3972a9a457f3SSelvin Xavier __le32 qid; 3973a9a457f3SSelvin Xavier #define CQ_RES_UD_CFA_QID_MASK 0xfffffUL 3974a9a457f3SSelvin Xavier #define CQ_RES_UD_CFA_QID_SFT 0 3975a9a457f3SSelvin Xavier __le32 cfa_metadata; 3976a9a457f3SSelvin Xavier #define CQ_RES_UD_CFA_CFA_METADATA_VID_MASK 0xfffUL 3977a9a457f3SSelvin Xavier #define CQ_RES_UD_CFA_CFA_METADATA_VID_SFT 0 3978a9a457f3SSelvin Xavier #define CQ_RES_UD_CFA_CFA_METADATA_DE 0x1000UL 3979a9a457f3SSelvin Xavier #define CQ_RES_UD_CFA_CFA_METADATA_PRI_MASK 0xe000UL 3980a9a457f3SSelvin Xavier #define CQ_RES_UD_CFA_CFA_METADATA_PRI_SFT 13 3981a9a457f3SSelvin Xavier #define CQ_RES_UD_CFA_CFA_METADATA_TPID_MASK 0xffff0000UL 3982a9a457f3SSelvin Xavier #define CQ_RES_UD_CFA_CFA_METADATA_TPID_SFT 16 3983a9a457f3SSelvin Xavier __le16 src_mac[3]; 3984a9a457f3SSelvin Xavier __le16 src_qp_low; 3985a9a457f3SSelvin Xavier u8 cqe_type_toggle; 3986a9a457f3SSelvin Xavier #define CQ_RES_UD_CFA_TOGGLE 0x1UL 3987a9a457f3SSelvin Xavier #define CQ_RES_UD_CFA_CQE_TYPE_MASK 0x1eUL 3988a9a457f3SSelvin Xavier #define CQ_RES_UD_CFA_CQE_TYPE_SFT 1 3989a9a457f3SSelvin Xavier #define CQ_RES_UD_CFA_CQE_TYPE_RES_UD_CFA (0x4UL << 1) 3990a9a457f3SSelvin Xavier #define CQ_RES_UD_CFA_CQE_TYPE_LAST CQ_RES_UD_CFA_CQE_TYPE_RES_UD_CFA 3991a9a457f3SSelvin Xavier u8 status; 3992a9a457f3SSelvin Xavier #define CQ_RES_UD_CFA_STATUS_OK 0x0UL 3993a9a457f3SSelvin Xavier #define CQ_RES_UD_CFA_STATUS_LOCAL_ACCESS_ERROR 0x1UL 3994a9a457f3SSelvin Xavier #define CQ_RES_UD_CFA_STATUS_HW_LOCAL_LENGTH_ERR 0x2UL 3995a9a457f3SSelvin Xavier #define CQ_RES_UD_CFA_STATUS_LOCAL_PROTECTION_ERR 0x3UL 3996a9a457f3SSelvin Xavier #define CQ_RES_UD_CFA_STATUS_LOCAL_QP_OPERATION_ERR 0x4UL 3997a9a457f3SSelvin Xavier #define CQ_RES_UD_CFA_STATUS_MEMORY_MGT_OPERATION_ERR 0x5UL 3998a9a457f3SSelvin Xavier #define CQ_RES_UD_CFA_STATUS_WORK_REQUEST_FLUSHED_ERR 0x7UL 3999a9a457f3SSelvin Xavier #define CQ_RES_UD_CFA_STATUS_HW_FLUSH_ERR 0x8UL 4000a9a457f3SSelvin Xavier #define CQ_RES_UD_CFA_STATUS_LAST CQ_RES_UD_CFA_STATUS_HW_FLUSH_ERR 4001a9a457f3SSelvin Xavier __le16 flags; 4002a9a457f3SSelvin Xavier #define CQ_RES_UD_CFA_FLAGS_SRQ 0x1UL 4003a9a457f3SSelvin Xavier #define CQ_RES_UD_CFA_FLAGS_SRQ_RQ 0x0UL 4004a9a457f3SSelvin Xavier #define CQ_RES_UD_CFA_FLAGS_SRQ_SRQ 0x1UL 4005a9a457f3SSelvin Xavier #define CQ_RES_UD_CFA_FLAGS_SRQ_LAST CQ_RES_UD_CFA_FLAGS_SRQ_SRQ 4006a9a457f3SSelvin Xavier #define CQ_RES_UD_CFA_FLAGS_IMM 0x2UL 4007a9a457f3SSelvin Xavier #define CQ_RES_UD_CFA_FLAGS_UNUSED_MASK 0xcUL 4008a9a457f3SSelvin Xavier #define CQ_RES_UD_CFA_FLAGS_UNUSED_SFT 2 4009a9a457f3SSelvin Xavier #define CQ_RES_UD_CFA_FLAGS_ROCE_IP_VER_MASK 0x30UL 4010a9a457f3SSelvin Xavier #define CQ_RES_UD_CFA_FLAGS_ROCE_IP_VER_SFT 4 4011a9a457f3SSelvin Xavier #define CQ_RES_UD_CFA_FLAGS_ROCE_IP_VER_V1 (0x0UL << 4) 4012a9a457f3SSelvin Xavier #define CQ_RES_UD_CFA_FLAGS_ROCE_IP_VER_V2IPV4 (0x2UL << 4) 4013a9a457f3SSelvin Xavier #define CQ_RES_UD_CFA_FLAGS_ROCE_IP_VER_V2IPV6 (0x3UL << 4) 4014a9a457f3SSelvin Xavier #define CQ_RES_UD_CFA_FLAGS_ROCE_IP_VER_LAST CQ_RES_UD_CFA_FLAGS_ROCE_IP_VER_V2IPV6 4015a9a457f3SSelvin Xavier #define CQ_RES_UD_CFA_FLAGS_META_FORMAT_MASK 0x3c0UL 4016a9a457f3SSelvin Xavier #define CQ_RES_UD_CFA_FLAGS_META_FORMAT_SFT 6 4017a9a457f3SSelvin Xavier #define CQ_RES_UD_CFA_FLAGS_META_FORMAT_NONE (0x0UL << 6) 4018a9a457f3SSelvin Xavier #define CQ_RES_UD_CFA_FLAGS_META_FORMAT_VLAN (0x1UL << 6) 4019a9a457f3SSelvin Xavier #define CQ_RES_UD_CFA_FLAGS_META_FORMAT_TUNNEL_ID (0x2UL << 6) 4020a9a457f3SSelvin Xavier #define CQ_RES_UD_CFA_FLAGS_META_FORMAT_CHDR_DATA (0x3UL << 6) 4021a9a457f3SSelvin Xavier #define CQ_RES_UD_CFA_FLAGS_META_FORMAT_HDR_OFFSET (0x4UL << 6) 4022a9a457f3SSelvin Xavier #define CQ_RES_UD_CFA_FLAGS_META_FORMAT_LAST CQ_RES_UD_CFA_FLAGS_META_FORMAT_HDR_OFFSET 4023a9a457f3SSelvin Xavier #define CQ_RES_UD_CFA_FLAGS_EXT_META_FORMAT_MASK 0xc00UL 4024a9a457f3SSelvin Xavier #define CQ_RES_UD_CFA_FLAGS_EXT_META_FORMAT_SFT 10 4025a9a457f3SSelvin Xavier __le32 src_qp_high_srq_or_rq_wr_id; 4026a9a457f3SSelvin Xavier #define CQ_RES_UD_CFA_SRQ_OR_RQ_WR_ID_MASK 0xfffffUL 4027a9a457f3SSelvin Xavier #define CQ_RES_UD_CFA_SRQ_OR_RQ_WR_ID_SFT 0 4028a9a457f3SSelvin Xavier #define CQ_RES_UD_CFA_SRC_QP_HIGH_MASK 0xff000000UL 4029a9a457f3SSelvin Xavier #define CQ_RES_UD_CFA_SRC_QP_HIGH_SFT 24 4030a9a457f3SSelvin Xavier }; 4031a9a457f3SSelvin Xavier 4032a9a457f3SSelvin Xavier /* cq_res_ud_cfa_v2 (size:256b/32B) */ 4033a9a457f3SSelvin Xavier struct cq_res_ud_cfa_v2 { 4034a9a457f3SSelvin Xavier __le16 length; 4035a9a457f3SSelvin Xavier #define CQ_RES_UD_CFA_V2_LENGTH_MASK 0x3fffUL 4036a9a457f3SSelvin Xavier #define CQ_RES_UD_CFA_V2_LENGTH_SFT 0 4037a9a457f3SSelvin Xavier __le16 cfa_metadata0; 4038a9a457f3SSelvin Xavier #define CQ_RES_UD_CFA_V2_CFA_METADATA0_VID_MASK 0xfffUL 4039a9a457f3SSelvin Xavier #define CQ_RES_UD_CFA_V2_CFA_METADATA0_VID_SFT 0 4040a9a457f3SSelvin Xavier #define CQ_RES_UD_CFA_V2_CFA_METADATA0_DE 0x1000UL 4041a9a457f3SSelvin Xavier #define CQ_RES_UD_CFA_V2_CFA_METADATA0_PRI_MASK 0xe000UL 4042a9a457f3SSelvin Xavier #define CQ_RES_UD_CFA_V2_CFA_METADATA0_PRI_SFT 13 4043a9a457f3SSelvin Xavier __le32 imm_data; 4044a9a457f3SSelvin Xavier __le32 qid; 4045a9a457f3SSelvin Xavier #define CQ_RES_UD_CFA_V2_QID_MASK 0xfffffUL 4046a9a457f3SSelvin Xavier #define CQ_RES_UD_CFA_V2_QID_SFT 0 4047a9a457f3SSelvin Xavier __le32 cfa_metadata2; 4048a9a457f3SSelvin Xavier __le16 src_mac[3]; 4049a9a457f3SSelvin Xavier __le16 src_qp_low; 4050a9a457f3SSelvin Xavier u8 cqe_type_toggle; 4051a9a457f3SSelvin Xavier #define CQ_RES_UD_CFA_V2_TOGGLE 0x1UL 4052a9a457f3SSelvin Xavier #define CQ_RES_UD_CFA_V2_CQE_TYPE_MASK 0x1eUL 4053a9a457f3SSelvin Xavier #define CQ_RES_UD_CFA_V2_CQE_TYPE_SFT 1 4054a9a457f3SSelvin Xavier #define CQ_RES_UD_CFA_V2_CQE_TYPE_RES_UD_CFA (0x4UL << 1) 4055a9a457f3SSelvin Xavier #define CQ_RES_UD_CFA_V2_CQE_TYPE_LAST CQ_RES_UD_CFA_V2_CQE_TYPE_RES_UD_CFA 4056a9a457f3SSelvin Xavier u8 status; 4057a9a457f3SSelvin Xavier #define CQ_RES_UD_CFA_V2_STATUS_OK 0x0UL 4058a9a457f3SSelvin Xavier #define CQ_RES_UD_CFA_V2_STATUS_LOCAL_ACCESS_ERROR 0x1UL 4059a9a457f3SSelvin Xavier #define CQ_RES_UD_CFA_V2_STATUS_HW_LOCAL_LENGTH_ERR 0x2UL 4060a9a457f3SSelvin Xavier #define CQ_RES_UD_CFA_V2_STATUS_LOCAL_PROTECTION_ERR 0x3UL 4061a9a457f3SSelvin Xavier #define CQ_RES_UD_CFA_V2_STATUS_LOCAL_QP_OPERATION_ERR 0x4UL 4062a9a457f3SSelvin Xavier #define CQ_RES_UD_CFA_V2_STATUS_MEMORY_MGT_OPERATION_ERR 0x5UL 4063a9a457f3SSelvin Xavier #define CQ_RES_UD_CFA_V2_STATUS_WORK_REQUEST_FLUSHED_ERR 0x7UL 4064a9a457f3SSelvin Xavier #define CQ_RES_UD_CFA_V2_STATUS_HW_FLUSH_ERR 0x8UL 4065a9a457f3SSelvin Xavier #define CQ_RES_UD_CFA_V2_STATUS_LAST CQ_RES_UD_CFA_V2_STATUS_HW_FLUSH_ERR 4066a9a457f3SSelvin Xavier __le16 flags; 4067a9a457f3SSelvin Xavier #define CQ_RES_UD_CFA_V2_FLAGS_SRQ 0x1UL 4068a9a457f3SSelvin Xavier #define CQ_RES_UD_CFA_V2_FLAGS_SRQ_RQ 0x0UL 4069a9a457f3SSelvin Xavier #define CQ_RES_UD_CFA_V2_FLAGS_SRQ_SRQ 0x1UL 4070a9a457f3SSelvin Xavier #define CQ_RES_UD_CFA_V2_FLAGS_SRQ_LAST CQ_RES_UD_CFA_V2_FLAGS_SRQ_SRQ 4071a9a457f3SSelvin Xavier #define CQ_RES_UD_CFA_V2_FLAGS_IMM 0x2UL 4072a9a457f3SSelvin Xavier #define CQ_RES_UD_CFA_V2_FLAGS_UNUSED_MASK 0xcUL 4073a9a457f3SSelvin Xavier #define CQ_RES_UD_CFA_V2_FLAGS_UNUSED_SFT 2 4074a9a457f3SSelvin Xavier #define CQ_RES_UD_CFA_V2_FLAGS_ROCE_IP_VER_MASK 0x30UL 4075a9a457f3SSelvin Xavier #define CQ_RES_UD_CFA_V2_FLAGS_ROCE_IP_VER_SFT 4 4076a9a457f3SSelvin Xavier #define CQ_RES_UD_CFA_V2_FLAGS_ROCE_IP_VER_V1 (0x0UL << 4) 4077a9a457f3SSelvin Xavier #define CQ_RES_UD_CFA_V2_FLAGS_ROCE_IP_VER_V2IPV4 (0x2UL << 4) 4078a9a457f3SSelvin Xavier #define CQ_RES_UD_CFA_V2_FLAGS_ROCE_IP_VER_V2IPV6 (0x3UL << 4) 4079a9a457f3SSelvin Xavier #define CQ_RES_UD_CFA_V2_FLAGS_ROCE_IP_VER_LAST CQ_RES_UD_CFA_V2_FLAGS_ROCE_IP_VER_V2IPV6 4080a9a457f3SSelvin Xavier #define CQ_RES_UD_CFA_V2_FLAGS_META_FORMAT_MASK 0x3c0UL 4081a9a457f3SSelvin Xavier #define CQ_RES_UD_CFA_V2_FLAGS_META_FORMAT_SFT 6 4082a9a457f3SSelvin Xavier #define CQ_RES_UD_CFA_V2_FLAGS_META_FORMAT_NONE (0x0UL << 6) 4083a9a457f3SSelvin Xavier #define CQ_RES_UD_CFA_V2_FLAGS_META_FORMAT_ACT_REC_PTR (0x1UL << 6) 4084a9a457f3SSelvin Xavier #define CQ_RES_UD_CFA_V2_FLAGS_META_FORMAT_TUNNEL_ID (0x2UL << 6) 4085a9a457f3SSelvin Xavier #define CQ_RES_UD_CFA_V2_FLAGS_META_FORMAT_CHDR_DATA (0x3UL << 6) 4086a9a457f3SSelvin Xavier #define CQ_RES_UD_CFA_V2_FLAGS_META_FORMAT_HDR_OFFSET (0x4UL << 6) 4087a9a457f3SSelvin Xavier #define CQ_RES_UD_CFA_V2_FLAGS_META_FORMAT_LAST \ 4088a9a457f3SSelvin Xavier CQ_RES_UD_CFA_V2_FLAGS_META_FORMAT_HDR_OFFSET 4089a9a457f3SSelvin Xavier __le32 src_qp_high_srq_or_rq_wr_id; 4090a9a457f3SSelvin Xavier #define CQ_RES_UD_CFA_V2_SRQ_OR_RQ_WR_ID_MASK 0xfffffUL 4091a9a457f3SSelvin Xavier #define CQ_RES_UD_CFA_V2_SRQ_OR_RQ_WR_ID_SFT 0 4092a9a457f3SSelvin Xavier #define CQ_RES_UD_CFA_V2_CFA_METADATA1_MASK 0xf00000UL 4093a9a457f3SSelvin Xavier #define CQ_RES_UD_CFA_V2_CFA_METADATA1_SFT 20 4094a9a457f3SSelvin Xavier #define CQ_RES_UD_CFA_V2_CFA_METADATA1_TPID_SEL_MASK 0x700000UL 4095a9a457f3SSelvin Xavier #define CQ_RES_UD_CFA_V2_CFA_METADATA1_TPID_SEL_SFT 20 4096a9a457f3SSelvin Xavier #define CQ_RES_UD_CFA_V2_CFA_METADATA1_TPID_SEL_TPID88A8 (0x0UL << 20) 4097a9a457f3SSelvin Xavier #define CQ_RES_UD_CFA_V2_CFA_METADATA1_TPID_SEL_TPID8100 (0x1UL << 20) 4098a9a457f3SSelvin Xavier #define CQ_RES_UD_CFA_V2_CFA_METADATA1_TPID_SEL_TPID9100 (0x2UL << 20) 4099a9a457f3SSelvin Xavier #define CQ_RES_UD_CFA_V2_CFA_METADATA1_TPID_SEL_TPID9200 (0x3UL << 20) 4100a9a457f3SSelvin Xavier #define CQ_RES_UD_CFA_V2_CFA_METADATA1_TPID_SEL_TPID9300 (0x4UL << 20) 4101a9a457f3SSelvin Xavier #define CQ_RES_UD_CFA_V2_CFA_METADATA1_TPID_SEL_TPIDCFG (0x5UL << 20) 4102a9a457f3SSelvin Xavier #define CQ_RES_UD_CFA_V2_CFA_METADATA1_TPID_SEL_LAST \ 4103a9a457f3SSelvin Xavier CQ_RES_UD_CFA_V2_CFA_METADATA1_TPID_SEL_TPIDCFG 4104a9a457f3SSelvin Xavier #define CQ_RES_UD_CFA_V2_CFA_METADATA1_VALID 0x800000UL 4105a9a457f3SSelvin Xavier #define CQ_RES_UD_CFA_V2_SRC_QP_HIGH_MASK 0xff000000UL 4106a9a457f3SSelvin Xavier #define CQ_RES_UD_CFA_V2_SRC_QP_HIGH_SFT 24 4107a9a457f3SSelvin Xavier }; 4108a9a457f3SSelvin Xavier 4109a9a457f3SSelvin Xavier /* cq_res_raweth_qp1 (size:256b/32B) */ 4110a9a457f3SSelvin Xavier struct cq_res_raweth_qp1 { 4111a9a457f3SSelvin Xavier __le16 length; 4112a9a457f3SSelvin Xavier #define CQ_RES_RAWETH_QP1_LENGTH_MASK 0x3fffUL 4113a9a457f3SSelvin Xavier #define CQ_RES_RAWETH_QP1_LENGTH_SFT 0 4114a9a457f3SSelvin Xavier __le16 raweth_qp1_flags; 4115a9a457f3SSelvin Xavier #define CQ_RES_RAWETH_QP1_RAWETH_QP1_FLAGS_MASK 0x3ffUL 4116a9a457f3SSelvin Xavier #define CQ_RES_RAWETH_QP1_RAWETH_QP1_FLAGS_SFT 0 4117a9a457f3SSelvin Xavier #define CQ_RES_RAWETH_QP1_RAWETH_QP1_FLAGS_ERROR 0x1UL 4118a9a457f3SSelvin Xavier #define CQ_RES_RAWETH_QP1_RAWETH_QP1_FLAGS_ITYPE_MASK 0x3c0UL 4119a9a457f3SSelvin Xavier #define CQ_RES_RAWETH_QP1_RAWETH_QP1_FLAGS_ITYPE_SFT 6 4120a9a457f3SSelvin Xavier #define CQ_RES_RAWETH_QP1_RAWETH_QP1_FLAGS_ITYPE_NOT_KNOWN (0x0UL << 6) 4121a9a457f3SSelvin Xavier #define CQ_RES_RAWETH_QP1_RAWETH_QP1_FLAGS_ITYPE_IP (0x1UL << 6) 4122a9a457f3SSelvin Xavier #define CQ_RES_RAWETH_QP1_RAWETH_QP1_FLAGS_ITYPE_TCP (0x2UL << 6) 4123a9a457f3SSelvin Xavier #define CQ_RES_RAWETH_QP1_RAWETH_QP1_FLAGS_ITYPE_UDP (0x3UL << 6) 4124a9a457f3SSelvin Xavier #define CQ_RES_RAWETH_QP1_RAWETH_QP1_FLAGS_ITYPE_FCOE (0x4UL << 6) 4125a9a457f3SSelvin Xavier #define CQ_RES_RAWETH_QP1_RAWETH_QP1_FLAGS_ITYPE_ROCE (0x5UL << 6) 4126a9a457f3SSelvin Xavier #define CQ_RES_RAWETH_QP1_RAWETH_QP1_FLAGS_ITYPE_ICMP (0x7UL << 6) 4127a9a457f3SSelvin Xavier #define CQ_RES_RAWETH_QP1_RAWETH_QP1_FLAGS_ITYPE_PTP_WO_TIMESTAMP (0x8UL << 6) 4128a9a457f3SSelvin Xavier #define CQ_RES_RAWETH_QP1_RAWETH_QP1_FLAGS_ITYPE_PTP_W_TIMESTAMP (0x9UL << 6) 4129a9a457f3SSelvin Xavier #define CQ_RES_RAWETH_QP1_RAWETH_QP1_FLAGS_ITYPE_LAST \ 4130a9a457f3SSelvin Xavier CQ_RES_RAWETH_QP1_RAWETH_QP1_FLAGS_ITYPE_PTP_W_TIMESTAMP 4131a9a457f3SSelvin Xavier __le16 raweth_qp1_errors; 4132a9a457f3SSelvin Xavier #define CQ_RES_RAWETH_QP1_RAWETH_QP1_ERRORS_IP_CS_ERROR 0x10UL 4133a9a457f3SSelvin Xavier #define CQ_RES_RAWETH_QP1_RAWETH_QP1_ERRORS_L4_CS_ERROR 0x20UL 4134a9a457f3SSelvin Xavier #define CQ_RES_RAWETH_QP1_RAWETH_QP1_ERRORS_T_IP_CS_ERROR 0x40UL 4135a9a457f3SSelvin Xavier #define CQ_RES_RAWETH_QP1_RAWETH_QP1_ERRORS_T_L4_CS_ERROR 0x80UL 4136a9a457f3SSelvin Xavier #define CQ_RES_RAWETH_QP1_RAWETH_QP1_ERRORS_CRC_ERROR 0x100UL 4137a9a457f3SSelvin Xavier #define CQ_RES_RAWETH_QP1_RAWETH_QP1_ERRORS_T_PKT_ERROR_MASK 0xe00UL 4138a9a457f3SSelvin Xavier #define CQ_RES_RAWETH_QP1_RAWETH_QP1_ERRORS_T_PKT_ERROR_SFT 9 4139a9a457f3SSelvin Xavier #define CQ_RES_RAWETH_QP1_RAWETH_QP1_ERRORS_T_PKT_ERROR_NO_ERROR (0x0UL << 9) 4140a9a457f3SSelvin Xavier #define CQ_RES_RAWETH_QP1_RAWETH_QP1_ERRORS_T_PKT_ERROR_T_L3_BAD_VERSION (0x1UL << 9) 4141a9a457f3SSelvin Xavier #define CQ_RES_RAWETH_QP1_RAWETH_QP1_ERRORS_T_PKT_ERROR_T_L3_BAD_HDR_LEN (0x2UL << 9) 4142a9a457f3SSelvin Xavier #define CQ_RES_RAWETH_QP1_RAWETH_QP1_ERRORS_T_PKT_ERROR_TUNNEL_TOTAL_ERROR (0x3UL << 9) 4143a9a457f3SSelvin Xavier #define CQ_RES_RAWETH_QP1_RAWETH_QP1_ERRORS_T_PKT_ERROR_T_IP_TOTAL_ERROR (0x4UL << 9) 4144a9a457f3SSelvin Xavier #define CQ_RES_RAWETH_QP1_RAWETH_QP1_ERRORS_T_PKT_ERROR_T_UDP_TOTAL_ERROR (0x5UL << 9) 4145a9a457f3SSelvin Xavier #define CQ_RES_RAWETH_QP1_RAWETH_QP1_ERRORS_T_PKT_ERROR_T_L3_BAD_TTL (0x6UL << 9) 4146a9a457f3SSelvin Xavier #define CQ_RES_RAWETH_QP1_RAWETH_QP1_ERRORS_T_PKT_ERROR_LAST \ 4147a9a457f3SSelvin Xavier CQ_RES_RAWETH_QP1_RAWETH_QP1_ERRORS_T_PKT_ERROR_T_L3_BAD_TTL 4148a9a457f3SSelvin Xavier #define CQ_RES_RAWETH_QP1_RAWETH_QP1_ERRORS_PKT_ERROR_MASK 0xf000UL 4149a9a457f3SSelvin Xavier #define CQ_RES_RAWETH_QP1_RAWETH_QP1_ERRORS_PKT_ERROR_SFT 12 4150a9a457f3SSelvin Xavier #define CQ_RES_RAWETH_QP1_RAWETH_QP1_ERRORS_PKT_ERROR_NO_ERROR (0x0UL << 12) 4151a9a457f3SSelvin Xavier #define CQ_RES_RAWETH_QP1_RAWETH_QP1_ERRORS_PKT_ERROR_L3_BAD_VERSION (0x1UL << 12) 4152a9a457f3SSelvin Xavier #define CQ_RES_RAWETH_QP1_RAWETH_QP1_ERRORS_PKT_ERROR_L3_BAD_HDR_LEN (0x2UL << 12) 4153a9a457f3SSelvin Xavier #define CQ_RES_RAWETH_QP1_RAWETH_QP1_ERRORS_PKT_ERROR_L3_BAD_TTL (0x3UL << 12) 4154a9a457f3SSelvin Xavier #define CQ_RES_RAWETH_QP1_RAWETH_QP1_ERRORS_PKT_ERROR_IP_TOTAL_ERROR (0x4UL << 12) 4155a9a457f3SSelvin Xavier #define CQ_RES_RAWETH_QP1_RAWETH_QP1_ERRORS_PKT_ERROR_UDP_TOTAL_ERROR (0x5UL << 12) 4156a9a457f3SSelvin Xavier #define CQ_RES_RAWETH_QP1_RAWETH_QP1_ERRORS_PKT_ERROR_L4_BAD_HDR_LEN (0x6UL << 12) 4157a9a457f3SSelvin Xavier #define CQ_RES_RAWETH_QP1_RAWETH_QP1_ERRORS_PKT_ERROR_L4_BAD_HDR_LEN_TOO_SMALL (0x7UL << 12) 4158a9a457f3SSelvin Xavier #define CQ_RES_RAWETH_QP1_RAWETH_QP1_ERRORS_PKT_ERROR_L4_BAD_OPT_LEN (0x8UL << 12) 4159a9a457f3SSelvin Xavier #define CQ_RES_RAWETH_QP1_RAWETH_QP1_ERRORS_PKT_ERROR_LAST \ 4160a9a457f3SSelvin Xavier CQ_RES_RAWETH_QP1_RAWETH_QP1_ERRORS_PKT_ERROR_L4_BAD_OPT_LEN 4161a9a457f3SSelvin Xavier __le16 raweth_qp1_cfa_code; 4162a9a457f3SSelvin Xavier __le64 qp_handle; 4163a9a457f3SSelvin Xavier __le32 raweth_qp1_flags2; 4164a9a457f3SSelvin Xavier #define CQ_RES_RAWETH_QP1_RAWETH_QP1_FLAGS2_IP_CS_CALC 0x1UL 4165a9a457f3SSelvin Xavier #define CQ_RES_RAWETH_QP1_RAWETH_QP1_FLAGS2_L4_CS_CALC 0x2UL 4166a9a457f3SSelvin Xavier #define CQ_RES_RAWETH_QP1_RAWETH_QP1_FLAGS2_T_IP_CS_CALC 0x4UL 4167a9a457f3SSelvin Xavier #define CQ_RES_RAWETH_QP1_RAWETH_QP1_FLAGS2_T_L4_CS_CALC 0x8UL 4168a9a457f3SSelvin Xavier #define CQ_RES_RAWETH_QP1_RAWETH_QP1_FLAGS2_META_FORMAT_MASK 0xf0UL 4169a9a457f3SSelvin Xavier #define CQ_RES_RAWETH_QP1_RAWETH_QP1_FLAGS2_META_FORMAT_SFT 4 4170a9a457f3SSelvin Xavier #define CQ_RES_RAWETH_QP1_RAWETH_QP1_FLAGS2_META_FORMAT_NONE (0x0UL << 4) 4171a9a457f3SSelvin Xavier #define CQ_RES_RAWETH_QP1_RAWETH_QP1_FLAGS2_META_FORMAT_VLAN (0x1UL << 4) 4172a9a457f3SSelvin Xavier #define CQ_RES_RAWETH_QP1_RAWETH_QP1_FLAGS2_META_FORMAT_TUNNEL_ID (0x2UL << 4) 4173a9a457f3SSelvin Xavier #define CQ_RES_RAWETH_QP1_RAWETH_QP1_FLAGS2_META_FORMAT_CHDR_DATA (0x3UL << 4) 4174a9a457f3SSelvin Xavier #define CQ_RES_RAWETH_QP1_RAWETH_QP1_FLAGS2_META_FORMAT_HDR_OFFSET (0x4UL << 4) 4175a9a457f3SSelvin Xavier #define CQ_RES_RAWETH_QP1_RAWETH_QP1_FLAGS2_META_FORMAT_LAST \ 4176a9a457f3SSelvin Xavier CQ_RES_RAWETH_QP1_RAWETH_QP1_FLAGS2_META_FORMAT_HDR_OFFSET 4177a9a457f3SSelvin Xavier #define CQ_RES_RAWETH_QP1_RAWETH_QP1_FLAGS2_IP_TYPE 0x100UL 4178a9a457f3SSelvin Xavier #define CQ_RES_RAWETH_QP1_RAWETH_QP1_FLAGS2_COMPLETE_CHECKSUM_CALC 0x200UL 4179a9a457f3SSelvin Xavier #define CQ_RES_RAWETH_QP1_RAWETH_QP1_FLAGS2_EXT_META_FORMAT_MASK 0xc00UL 4180a9a457f3SSelvin Xavier #define CQ_RES_RAWETH_QP1_RAWETH_QP1_FLAGS2_EXT_META_FORMAT_SFT 10 4181a9a457f3SSelvin Xavier #define CQ_RES_RAWETH_QP1_RAWETH_QP1_FLAGS2_COMPLETE_CHECKSUM_MASK 0xffff0000UL 4182a9a457f3SSelvin Xavier #define CQ_RES_RAWETH_QP1_RAWETH_QP1_FLAGS2_COMPLETE_CHECKSUM_SFT 16 4183a9a457f3SSelvin Xavier __le32 raweth_qp1_metadata; 4184a9a457f3SSelvin Xavier #define CQ_RES_RAWETH_QP1_RAWETH_QP1_METADATA_PRI_DE_VID_MASK 0xffffUL 4185a9a457f3SSelvin Xavier #define CQ_RES_RAWETH_QP1_RAWETH_QP1_METADATA_PRI_DE_VID_SFT 0 4186a9a457f3SSelvin Xavier #define CQ_RES_RAWETH_QP1_RAWETH_QP1_METADATA_VID_MASK 0xfffUL 4187a9a457f3SSelvin Xavier #define CQ_RES_RAWETH_QP1_RAWETH_QP1_METADATA_VID_SFT 0 4188a9a457f3SSelvin Xavier #define CQ_RES_RAWETH_QP1_RAWETH_QP1_METADATA_DE 0x1000UL 4189a9a457f3SSelvin Xavier #define CQ_RES_RAWETH_QP1_RAWETH_QP1_METADATA_PRI_MASK 0xe000UL 4190a9a457f3SSelvin Xavier #define CQ_RES_RAWETH_QP1_RAWETH_QP1_METADATA_PRI_SFT 13 4191a9a457f3SSelvin Xavier #define CQ_RES_RAWETH_QP1_RAWETH_QP1_METADATA_TPID_MASK 0xffff0000UL 4192a9a457f3SSelvin Xavier #define CQ_RES_RAWETH_QP1_RAWETH_QP1_METADATA_TPID_SFT 16 4193a9a457f3SSelvin Xavier u8 cqe_type_toggle; 4194a9a457f3SSelvin Xavier #define CQ_RES_RAWETH_QP1_TOGGLE 0x1UL 4195a9a457f3SSelvin Xavier #define CQ_RES_RAWETH_QP1_CQE_TYPE_MASK 0x1eUL 4196a9a457f3SSelvin Xavier #define CQ_RES_RAWETH_QP1_CQE_TYPE_SFT 1 4197a9a457f3SSelvin Xavier #define CQ_RES_RAWETH_QP1_CQE_TYPE_RES_RAWETH_QP1 (0x3UL << 1) 4198a9a457f3SSelvin Xavier #define CQ_RES_RAWETH_QP1_CQE_TYPE_LAST CQ_RES_RAWETH_QP1_CQE_TYPE_RES_RAWETH_QP1 4199a9a457f3SSelvin Xavier u8 status; 4200a9a457f3SSelvin Xavier #define CQ_RES_RAWETH_QP1_STATUS_OK 0x0UL 4201a9a457f3SSelvin Xavier #define CQ_RES_RAWETH_QP1_STATUS_LOCAL_ACCESS_ERROR 0x1UL 4202a9a457f3SSelvin Xavier #define CQ_RES_RAWETH_QP1_STATUS_HW_LOCAL_LENGTH_ERR 0x2UL 4203a9a457f3SSelvin Xavier #define CQ_RES_RAWETH_QP1_STATUS_LOCAL_PROTECTION_ERR 0x3UL 4204a9a457f3SSelvin Xavier #define CQ_RES_RAWETH_QP1_STATUS_LOCAL_QP_OPERATION_ERR 0x4UL 4205a9a457f3SSelvin Xavier #define CQ_RES_RAWETH_QP1_STATUS_MEMORY_MGT_OPERATION_ERR 0x5UL 4206a9a457f3SSelvin Xavier #define CQ_RES_RAWETH_QP1_STATUS_WORK_REQUEST_FLUSHED_ERR 0x7UL 4207a9a457f3SSelvin Xavier #define CQ_RES_RAWETH_QP1_STATUS_HW_FLUSH_ERR 0x8UL 4208a9a457f3SSelvin Xavier #define CQ_RES_RAWETH_QP1_STATUS_LAST CQ_RES_RAWETH_QP1_STATUS_HW_FLUSH_ERR 4209a9a457f3SSelvin Xavier __le16 flags; 4210a9a457f3SSelvin Xavier #define CQ_RES_RAWETH_QP1_FLAGS_SRQ 0x1UL 4211a9a457f3SSelvin Xavier #define CQ_RES_RAWETH_QP1_FLAGS_SRQ_RQ 0x0UL 4212a9a457f3SSelvin Xavier #define CQ_RES_RAWETH_QP1_FLAGS_SRQ_SRQ 0x1UL 4213a9a457f3SSelvin Xavier #define CQ_RES_RAWETH_QP1_FLAGS_SRQ_LAST CQ_RES_RAWETH_QP1_FLAGS_SRQ_SRQ 4214a9a457f3SSelvin Xavier __le32 raweth_qp1_payload_offset_srq_or_rq_wr_id; 4215a9a457f3SSelvin Xavier #define CQ_RES_RAWETH_QP1_SRQ_OR_RQ_WR_ID_MASK 0xfffffUL 4216a9a457f3SSelvin Xavier #define CQ_RES_RAWETH_QP1_SRQ_OR_RQ_WR_ID_SFT 0 4217a9a457f3SSelvin Xavier #define CQ_RES_RAWETH_QP1_RAWETH_QP1_PAYLOAD_OFFSET_MASK 0xff000000UL 4218a9a457f3SSelvin Xavier #define CQ_RES_RAWETH_QP1_RAWETH_QP1_PAYLOAD_OFFSET_SFT 24 4219a9a457f3SSelvin Xavier }; 4220a9a457f3SSelvin Xavier 4221a9a457f3SSelvin Xavier /* cq_res_raweth_qp1_v2 (size:256b/32B) */ 4222a9a457f3SSelvin Xavier struct cq_res_raweth_qp1_v2 { 4223a9a457f3SSelvin Xavier __le16 length; 4224a9a457f3SSelvin Xavier #define CQ_RES_RAWETH_QP1_V2_LENGTH_MASK 0x3fffUL 4225a9a457f3SSelvin Xavier #define CQ_RES_RAWETH_QP1_V2_LENGTH_SFT 0 4226a9a457f3SSelvin Xavier __le16 raweth_qp1_flags; 4227a9a457f3SSelvin Xavier #define CQ_RES_RAWETH_QP1_V2_RAWETH_QP1_FLAGS_MASK 0x3ffUL 4228a9a457f3SSelvin Xavier #define CQ_RES_RAWETH_QP1_V2_RAWETH_QP1_FLAGS_SFT 0 4229a9a457f3SSelvin Xavier #define CQ_RES_RAWETH_QP1_V2_RAWETH_QP1_FLAGS_ERROR 0x1UL 4230a9a457f3SSelvin Xavier #define CQ_RES_RAWETH_QP1_V2_RAWETH_QP1_FLAGS_ITYPE_MASK 0x3c0UL 4231a9a457f3SSelvin Xavier #define CQ_RES_RAWETH_QP1_V2_RAWETH_QP1_FLAGS_ITYPE_SFT 6 4232a9a457f3SSelvin Xavier #define CQ_RES_RAWETH_QP1_V2_RAWETH_QP1_FLAGS_ITYPE_NOT_KNOWN (0x0UL << 6) 4233a9a457f3SSelvin Xavier #define CQ_RES_RAWETH_QP1_V2_RAWETH_QP1_FLAGS_ITYPE_IP (0x1UL << 6) 4234a9a457f3SSelvin Xavier #define CQ_RES_RAWETH_QP1_V2_RAWETH_QP1_FLAGS_ITYPE_TCP (0x2UL << 6) 4235a9a457f3SSelvin Xavier #define CQ_RES_RAWETH_QP1_V2_RAWETH_QP1_FLAGS_ITYPE_UDP (0x3UL << 6) 4236a9a457f3SSelvin Xavier #define CQ_RES_RAWETH_QP1_V2_RAWETH_QP1_FLAGS_ITYPE_FCOE (0x4UL << 6) 4237a9a457f3SSelvin Xavier #define CQ_RES_RAWETH_QP1_V2_RAWETH_QP1_FLAGS_ITYPE_ROCE (0x5UL << 6) 4238a9a457f3SSelvin Xavier #define CQ_RES_RAWETH_QP1_V2_RAWETH_QP1_FLAGS_ITYPE_ICMP (0x7UL << 6) 4239a9a457f3SSelvin Xavier #define CQ_RES_RAWETH_QP1_V2_RAWETH_QP1_FLAGS_ITYPE_PTP_WO_TIMESTAMP (0x8UL << 6) 4240a9a457f3SSelvin Xavier #define CQ_RES_RAWETH_QP1_V2_RAWETH_QP1_FLAGS_ITYPE_PTP_W_TIMESTAMP (0x9UL << 6) 4241a9a457f3SSelvin Xavier #define CQ_RES_RAWETH_QP1_V2_RAWETH_QP1_FLAGS_ITYPE_LAST \ 4242a9a457f3SSelvin Xavier CQ_RES_RAWETH_QP1_V2_RAWETH_QP1_FLAGS_ITYPE_PTP_W_TIMESTAMP 4243a9a457f3SSelvin Xavier __le16 raweth_qp1_errors; 4244a9a457f3SSelvin Xavier #define CQ_RES_RAWETH_QP1_V2_RAWETH_QP1_ERRORS_IP_CS_ERROR 0x10UL 4245a9a457f3SSelvin Xavier #define CQ_RES_RAWETH_QP1_V2_RAWETH_QP1_ERRORS_L4_CS_ERROR 0x20UL 4246a9a457f3SSelvin Xavier #define CQ_RES_RAWETH_QP1_V2_RAWETH_QP1_ERRORS_T_IP_CS_ERROR 0x40UL 4247a9a457f3SSelvin Xavier #define CQ_RES_RAWETH_QP1_V2_RAWETH_QP1_ERRORS_T_L4_CS_ERROR 0x80UL 4248a9a457f3SSelvin Xavier #define CQ_RES_RAWETH_QP1_V2_RAWETH_QP1_ERRORS_CRC_ERROR 0x100UL 4249a9a457f3SSelvin Xavier #define CQ_RES_RAWETH_QP1_V2_RAWETH_QP1_ERRORS_T_PKT_ERROR_MASK 0xe00UL 4250a9a457f3SSelvin Xavier #define CQ_RES_RAWETH_QP1_V2_RAWETH_QP1_ERRORS_T_PKT_ERROR_SFT 9 4251a9a457f3SSelvin Xavier #define CQ_RES_RAWETH_QP1_V2_RAWETH_QP1_ERRORS_T_PKT_ERROR_NO_ERROR (0x0UL << 9) 4252a9a457f3SSelvin Xavier #define CQ_RES_RAWETH_QP1_V2_RAWETH_QP1_ERRORS_T_PKT_ERROR_T_L3_BAD_VERSION (0x1UL << 9) 4253a9a457f3SSelvin Xavier #define CQ_RES_RAWETH_QP1_V2_RAWETH_QP1_ERRORS_T_PKT_ERROR_T_L3_BAD_HDR_LEN (0x2UL << 9) 4254a9a457f3SSelvin Xavier #define CQ_RES_RAWETH_QP1_V2_RAWETH_QP1_ERRORS_T_PKT_ERROR_TUNNEL_TOTAL_ERROR (0x3UL << 9) 4255a9a457f3SSelvin Xavier #define CQ_RES_RAWETH_QP1_V2_RAWETH_QP1_ERRORS_T_PKT_ERROR_T_IP_TOTAL_ERROR (0x4UL << 9) 4256a9a457f3SSelvin Xavier #define CQ_RES_RAWETH_QP1_V2_RAWETH_QP1_ERRORS_T_PKT_ERROR_T_UDP_TOTAL_ERROR (0x5UL << 9) 4257a9a457f3SSelvin Xavier #define CQ_RES_RAWETH_QP1_V2_RAWETH_QP1_ERRORS_T_PKT_ERROR_T_L3_BAD_TTL (0x6UL << 9) 4258a9a457f3SSelvin Xavier #define CQ_RES_RAWETH_QP1_V2_RAWETH_QP1_ERRORS_T_PKT_ERROR_LAST \ 4259a9a457f3SSelvin Xavier CQ_RES_RAWETH_QP1_V2_RAWETH_QP1_ERRORS_T_PKT_ERROR_T_L3_BAD_TTL 4260a9a457f3SSelvin Xavier #define CQ_RES_RAWETH_QP1_V2_RAWETH_QP1_ERRORS_PKT_ERROR_MASK 0xf000UL 4261a9a457f3SSelvin Xavier #define CQ_RES_RAWETH_QP1_V2_RAWETH_QP1_ERRORS_PKT_ERROR_SFT 12 4262a9a457f3SSelvin Xavier #define CQ_RES_RAWETH_QP1_V2_RAWETH_QP1_ERRORS_PKT_ERROR_NO_ERROR (0x0UL << 12) 4263a9a457f3SSelvin Xavier #define CQ_RES_RAWETH_QP1_V2_RAWETH_QP1_ERRORS_PKT_ERROR_L3_BAD_VERSION (0x1UL << 12) 4264a9a457f3SSelvin Xavier #define CQ_RES_RAWETH_QP1_V2_RAWETH_QP1_ERRORS_PKT_ERROR_L3_BAD_HDR_LEN (0x2UL << 12) 4265a9a457f3SSelvin Xavier #define CQ_RES_RAWETH_QP1_V2_RAWETH_QP1_ERRORS_PKT_ERROR_L3_BAD_TTL (0x3UL << 12) 4266a9a457f3SSelvin Xavier #define CQ_RES_RAWETH_QP1_V2_RAWETH_QP1_ERRORS_PKT_ERROR_IP_TOTAL_ERROR (0x4UL << 12) 4267a9a457f3SSelvin Xavier #define CQ_RES_RAWETH_QP1_V2_RAWETH_QP1_ERRORS_PKT_ERROR_UDP_TOTAL_ERROR (0x5UL << 12) 4268a9a457f3SSelvin Xavier #define CQ_RES_RAWETH_QP1_V2_RAWETH_QP1_ERRORS_PKT_ERROR_L4_BAD_HDR_LEN (0x6UL << 12) 4269a9a457f3SSelvin Xavier #define CQ_RES_RAWETH_QP1_V2_RAWETH_QP1_ERRORS_PKT_ERROR_L4_BAD_HDR_LEN_TOO_SMALL \ 4270a9a457f3SSelvin Xavier (0x7UL << 12) 4271a9a457f3SSelvin Xavier #define CQ_RES_RAWETH_QP1_V2_RAWETH_QP1_ERRORS_PKT_ERROR_L4_BAD_OPT_LEN \ 4272a9a457f3SSelvin Xavier (0x8UL << 12) 4273a9a457f3SSelvin Xavier #define CQ_RES_RAWETH_QP1_V2_RAWETH_QP1_ERRORS_PKT_ERROR_LAST \ 4274a9a457f3SSelvin Xavier CQ_RES_RAWETH_QP1_V2_RAWETH_QP1_ERRORS_PKT_ERROR_L4_BAD_OPT_LEN 4275a9a457f3SSelvin Xavier __le16 cfa_metadata0; 4276a9a457f3SSelvin Xavier #define CQ_RES_RAWETH_QP1_V2_CFA_METADATA0_VID_MASK 0xfffUL 4277a9a457f3SSelvin Xavier #define CQ_RES_RAWETH_QP1_V2_CFA_METADATA0_VID_SFT 0 4278a9a457f3SSelvin Xavier #define CQ_RES_RAWETH_QP1_V2_CFA_METADATA0_DE 0x1000UL 4279a9a457f3SSelvin Xavier #define CQ_RES_RAWETH_QP1_V2_CFA_METADATA0_PRI_MASK 0xe000UL 4280a9a457f3SSelvin Xavier #define CQ_RES_RAWETH_QP1_V2_CFA_METADATA0_PRI_SFT 13 4281a9a457f3SSelvin Xavier __le64 qp_handle; 4282a9a457f3SSelvin Xavier __le32 raweth_qp1_flags2; 4283a9a457f3SSelvin Xavier #define CQ_RES_RAWETH_QP1_V2_RAWETH_QP1_FLAGS2_CS_ALL_OK_MODE 0x8UL 4284a9a457f3SSelvin Xavier #define CQ_RES_RAWETH_QP1_V2_RAWETH_QP1_FLAGS2_META_FORMAT_MASK 0xf0UL 4285a9a457f3SSelvin Xavier #define CQ_RES_RAWETH_QP1_V2_RAWETH_QP1_FLAGS2_META_FORMAT_SFT 4 4286a9a457f3SSelvin Xavier #define CQ_RES_RAWETH_QP1_V2_RAWETH_QP1_FLAGS2_META_FORMAT_NONE (0x0UL << 4) 4287a9a457f3SSelvin Xavier #define CQ_RES_RAWETH_QP1_V2_RAWETH_QP1_FLAGS2_META_FORMAT_ACT_REC_PTR (0x1UL << 4) 4288a9a457f3SSelvin Xavier #define CQ_RES_RAWETH_QP1_V2_RAWETH_QP1_FLAGS2_META_FORMAT_TUNNEL_ID (0x2UL << 4) 4289a9a457f3SSelvin Xavier #define CQ_RES_RAWETH_QP1_V2_RAWETH_QP1_FLAGS2_META_FORMAT_CHDR_DATA (0x3UL << 4) 4290a9a457f3SSelvin Xavier #define CQ_RES_RAWETH_QP1_V2_RAWETH_QP1_FLAGS2_META_FORMAT_HDR_OFFSET (0x4UL << 4) 4291a9a457f3SSelvin Xavier #define CQ_RES_RAWETH_QP1_V2_RAWETH_QP1_FLAGS2_META_FORMAT_LAST \ 4292a9a457f3SSelvin Xavier CQ_RES_RAWETH_QP1_V2_RAWETH_QP1_FLAGS2_META_FORMAT_HDR_OFFSET 4293a9a457f3SSelvin Xavier #define CQ_RES_RAWETH_QP1_V2_RAWETH_QP1_FLAGS2_IP_TYPE 0x100UL 4294a9a457f3SSelvin Xavier #define CQ_RES_RAWETH_QP1_V2_RAWETH_QP1_FLAGS2_COMPLETE_CHECKSUM_CALC 0x200UL 4295a9a457f3SSelvin Xavier #define CQ_RES_RAWETH_QP1_V2_RAWETH_QP1_FLAGS2_CS_OK_MASK 0xfc00UL 4296a9a457f3SSelvin Xavier #define CQ_RES_RAWETH_QP1_V2_RAWETH_QP1_FLAGS2_CS_OK_SFT 10 4297a9a457f3SSelvin Xavier #define CQ_RES_RAWETH_QP1_V2_RAWETH_QP1_FLAGS2_COMPLETE_CHECKSUM_MASK 0xffff0000UL 4298a9a457f3SSelvin Xavier #define CQ_RES_RAWETH_QP1_V2_RAWETH_QP1_FLAGS2_COMPLETE_CHECKSUM_SFT 16 4299a9a457f3SSelvin Xavier __le32 cfa_metadata2; 4300a9a457f3SSelvin Xavier u8 cqe_type_toggle; 4301a9a457f3SSelvin Xavier #define CQ_RES_RAWETH_QP1_V2_TOGGLE 0x1UL 4302a9a457f3SSelvin Xavier #define CQ_RES_RAWETH_QP1_V2_CQE_TYPE_MASK 0x1eUL 4303a9a457f3SSelvin Xavier #define CQ_RES_RAWETH_QP1_V2_CQE_TYPE_SFT 1 4304a9a457f3SSelvin Xavier #define CQ_RES_RAWETH_QP1_V2_CQE_TYPE_RES_RAWETH_QP1 (0x3UL << 1) 4305a9a457f3SSelvin Xavier #define CQ_RES_RAWETH_QP1_V2_CQE_TYPE_LAST CQ_RES_RAWETH_QP1_V2_CQE_TYPE_RES_RAWETH_QP1 4306a9a457f3SSelvin Xavier u8 status; 4307a9a457f3SSelvin Xavier #define CQ_RES_RAWETH_QP1_V2_STATUS_OK 0x0UL 4308a9a457f3SSelvin Xavier #define CQ_RES_RAWETH_QP1_V2_STATUS_LOCAL_ACCESS_ERROR 0x1UL 4309a9a457f3SSelvin Xavier #define CQ_RES_RAWETH_QP1_V2_STATUS_HW_LOCAL_LENGTH_ERR 0x2UL 4310a9a457f3SSelvin Xavier #define CQ_RES_RAWETH_QP1_V2_STATUS_LOCAL_PROTECTION_ERR 0x3UL 4311a9a457f3SSelvin Xavier #define CQ_RES_RAWETH_QP1_V2_STATUS_LOCAL_QP_OPERATION_ERR 0x4UL 4312a9a457f3SSelvin Xavier #define CQ_RES_RAWETH_QP1_V2_STATUS_MEMORY_MGT_OPERATION_ERR 0x5UL 4313a9a457f3SSelvin Xavier #define CQ_RES_RAWETH_QP1_V2_STATUS_WORK_REQUEST_FLUSHED_ERR 0x7UL 4314a9a457f3SSelvin Xavier #define CQ_RES_RAWETH_QP1_V2_STATUS_HW_FLUSH_ERR 0x8UL 4315a9a457f3SSelvin Xavier #define CQ_RES_RAWETH_QP1_V2_STATUS_LAST CQ_RES_RAWETH_QP1_V2_STATUS_HW_FLUSH_ERR 4316a9a457f3SSelvin Xavier __le16 flags; 4317a9a457f3SSelvin Xavier #define CQ_RES_RAWETH_QP1_V2_FLAGS_SRQ 0x1UL 4318a9a457f3SSelvin Xavier #define CQ_RES_RAWETH_QP1_V2_FLAGS_SRQ_RQ 0x0UL 4319a9a457f3SSelvin Xavier #define CQ_RES_RAWETH_QP1_V2_FLAGS_SRQ_SRQ 0x1UL 4320a9a457f3SSelvin Xavier #define CQ_RES_RAWETH_QP1_V2_FLAGS_SRQ_LAST CQ_RES_RAWETH_QP1_V2_FLAGS_SRQ_SRQ 4321a9a457f3SSelvin Xavier __le32 raweth_qp1_payload_offset_srq_or_rq_wr_id; 4322a9a457f3SSelvin Xavier #define CQ_RES_RAWETH_QP1_V2_SRQ_OR_RQ_WR_ID_MASK 0xfffffUL 4323a9a457f3SSelvin Xavier #define CQ_RES_RAWETH_QP1_V2_SRQ_OR_RQ_WR_ID_SFT 0 4324a9a457f3SSelvin Xavier #define CQ_RES_RAWETH_QP1_V2_CFA_METADATA1_MASK 0xf00000UL 4325a9a457f3SSelvin Xavier #define CQ_RES_RAWETH_QP1_V2_CFA_METADATA1_SFT 20 4326a9a457f3SSelvin Xavier #define CQ_RES_RAWETH_QP1_V2_CFA_METADATA1_TPID_SEL_MASK 0x700000UL 4327a9a457f3SSelvin Xavier #define CQ_RES_RAWETH_QP1_V2_CFA_METADATA1_TPID_SEL_SFT 20 4328a9a457f3SSelvin Xavier #define CQ_RES_RAWETH_QP1_V2_CFA_METADATA1_TPID_SEL_TPID88A8 (0x0UL << 20) 4329a9a457f3SSelvin Xavier #define CQ_RES_RAWETH_QP1_V2_CFA_METADATA1_TPID_SEL_TPID8100 (0x1UL << 20) 4330a9a457f3SSelvin Xavier #define CQ_RES_RAWETH_QP1_V2_CFA_METADATA1_TPID_SEL_TPID9100 (0x2UL << 20) 4331a9a457f3SSelvin Xavier #define CQ_RES_RAWETH_QP1_V2_CFA_METADATA1_TPID_SEL_TPID9200 (0x3UL << 20) 4332a9a457f3SSelvin Xavier #define CQ_RES_RAWETH_QP1_V2_CFA_METADATA1_TPID_SEL_TPID9300 (0x4UL << 20) 4333a9a457f3SSelvin Xavier #define CQ_RES_RAWETH_QP1_V2_CFA_METADATA1_TPID_SEL_TPIDCFG (0x5UL << 20) 4334a9a457f3SSelvin Xavier #define CQ_RES_RAWETH_QP1_V2_CFA_METADATA1_TPID_SEL_LAST \ 4335a9a457f3SSelvin Xavier CQ_RES_RAWETH_QP1_V2_CFA_METADATA1_TPID_SEL_TPIDCFG 4336a9a457f3SSelvin Xavier #define CQ_RES_RAWETH_QP1_V2_CFA_METADATA1_VALID 0x800000UL 4337a9a457f3SSelvin Xavier #define CQ_RES_RAWETH_QP1_V2_RAWETH_QP1_PAYLOAD_OFFSET_MASK 0xff000000UL 4338a9a457f3SSelvin Xavier #define CQ_RES_RAWETH_QP1_V2_RAWETH_QP1_PAYLOAD_OFFSET_SFT 24 4339a9a457f3SSelvin Xavier }; 4340a9a457f3SSelvin Xavier 4341a9a457f3SSelvin Xavier /* cq_terminal (size:256b/32B) */ 4342a9a457f3SSelvin Xavier struct cq_terminal { 4343a9a457f3SSelvin Xavier __le64 qp_handle; 4344a9a457f3SSelvin Xavier __le16 sq_cons_idx; 4345a9a457f3SSelvin Xavier __le16 rq_cons_idx; 4346a9a457f3SSelvin Xavier __le32 reserved32_1; 4347a9a457f3SSelvin Xavier __le64 reserved64_3; 4348a9a457f3SSelvin Xavier u8 cqe_type_toggle; 4349a9a457f3SSelvin Xavier #define CQ_TERMINAL_TOGGLE 0x1UL 4350a9a457f3SSelvin Xavier #define CQ_TERMINAL_CQE_TYPE_MASK 0x1eUL 4351a9a457f3SSelvin Xavier #define CQ_TERMINAL_CQE_TYPE_SFT 1 4352a9a457f3SSelvin Xavier #define CQ_TERMINAL_CQE_TYPE_TERMINAL (0xeUL << 1) 4353a9a457f3SSelvin Xavier #define CQ_TERMINAL_CQE_TYPE_LAST CQ_TERMINAL_CQE_TYPE_TERMINAL 4354a9a457f3SSelvin Xavier u8 status; 4355a9a457f3SSelvin Xavier #define CQ_TERMINAL_STATUS_OK 0x0UL 4356a9a457f3SSelvin Xavier #define CQ_TERMINAL_STATUS_LAST CQ_TERMINAL_STATUS_OK 4357a9a457f3SSelvin Xavier __le16 reserved16; 4358a9a457f3SSelvin Xavier __le32 reserved32_2; 4359a9a457f3SSelvin Xavier }; 4360a9a457f3SSelvin Xavier 4361a9a457f3SSelvin Xavier /* cq_cutoff (size:256b/32B) */ 4362a9a457f3SSelvin Xavier struct cq_cutoff { 4363a9a457f3SSelvin Xavier __le64 reserved64_1; 4364a9a457f3SSelvin Xavier __le64 reserved64_2; 4365a9a457f3SSelvin Xavier __le64 reserved64_3; 4366a9a457f3SSelvin Xavier u8 cqe_type_toggle; 4367a9a457f3SSelvin Xavier #define CQ_CUTOFF_TOGGLE 0x1UL 4368a9a457f3SSelvin Xavier #define CQ_CUTOFF_CQE_TYPE_MASK 0x1eUL 4369a9a457f3SSelvin Xavier #define CQ_CUTOFF_CQE_TYPE_SFT 1 4370a9a457f3SSelvin Xavier #define CQ_CUTOFF_CQE_TYPE_CUT_OFF (0xfUL << 1) 4371a9a457f3SSelvin Xavier #define CQ_CUTOFF_CQE_TYPE_LAST CQ_CUTOFF_CQE_TYPE_CUT_OFF 43729a54460bSSelvin Xavier #define CQ_CUTOFF_RESIZE_TOGGLE_MASK 0x60UL 43739a54460bSSelvin Xavier #define CQ_CUTOFF_RESIZE_TOGGLE_SFT 5 4374a9a457f3SSelvin Xavier u8 status; 4375a9a457f3SSelvin Xavier #define CQ_CUTOFF_STATUS_OK 0x0UL 4376a9a457f3SSelvin Xavier #define CQ_CUTOFF_STATUS_LAST CQ_CUTOFF_STATUS_OK 4377a9a457f3SSelvin Xavier __le16 reserved16; 4378a9a457f3SSelvin Xavier __le32 reserved32; 4379a9a457f3SSelvin Xavier }; 4380a9a457f3SSelvin Xavier 4381a9a457f3SSelvin Xavier /* nq_base (size:128b/16B) */ 4382a9a457f3SSelvin Xavier struct nq_base { 4383a9a457f3SSelvin Xavier __le16 info10_type; 4384a9a457f3SSelvin Xavier #define NQ_BASE_TYPE_MASK 0x3fUL 4385a9a457f3SSelvin Xavier #define NQ_BASE_TYPE_SFT 0 4386a9a457f3SSelvin Xavier #define NQ_BASE_TYPE_CQ_NOTIFICATION 0x30UL 4387a9a457f3SSelvin Xavier #define NQ_BASE_TYPE_SRQ_EVENT 0x32UL 4388a9a457f3SSelvin Xavier #define NQ_BASE_TYPE_DBQ_EVENT 0x34UL 4389a9a457f3SSelvin Xavier #define NQ_BASE_TYPE_QP_EVENT 0x38UL 4390a9a457f3SSelvin Xavier #define NQ_BASE_TYPE_FUNC_EVENT 0x3aUL 4391a9a457f3SSelvin Xavier #define NQ_BASE_TYPE_LAST NQ_BASE_TYPE_FUNC_EVENT 4392a9a457f3SSelvin Xavier #define NQ_BASE_INFO10_MASK 0xffc0UL 4393a9a457f3SSelvin Xavier #define NQ_BASE_INFO10_SFT 6 4394a9a457f3SSelvin Xavier __le16 info16; 4395a9a457f3SSelvin Xavier __le32 info32; 4396a9a457f3SSelvin Xavier __le32 info63_v[2]; 4397a9a457f3SSelvin Xavier #define NQ_BASE_V 0x1UL 4398a9a457f3SSelvin Xavier #define NQ_BASE_INFO63_MASK 0xfffffffeUL 4399a9a457f3SSelvin Xavier #define NQ_BASE_INFO63_SFT 1 4400a9a457f3SSelvin Xavier }; 4401a9a457f3SSelvin Xavier 4402a9a457f3SSelvin Xavier /* nq_cn (size:128b/16B) */ 4403a9a457f3SSelvin Xavier struct nq_cn { 4404a9a457f3SSelvin Xavier __le16 type; 4405a9a457f3SSelvin Xavier #define NQ_CN_TYPE_MASK 0x3fUL 4406a9a457f3SSelvin Xavier #define NQ_CN_TYPE_SFT 0 4407a9a457f3SSelvin Xavier #define NQ_CN_TYPE_CQ_NOTIFICATION 0x30UL 4408a9a457f3SSelvin Xavier #define NQ_CN_TYPE_LAST NQ_CN_TYPE_CQ_NOTIFICATION 4409a9a457f3SSelvin Xavier #define NQ_CN_TOGGLE_MASK 0xc0UL 4410a9a457f3SSelvin Xavier #define NQ_CN_TOGGLE_SFT 6 4411a9a457f3SSelvin Xavier __le16 reserved16; 4412a9a457f3SSelvin Xavier __le32 cq_handle_low; 4413a9a457f3SSelvin Xavier __le32 v; 4414a9a457f3SSelvin Xavier #define NQ_CN_V 0x1UL 4415a9a457f3SSelvin Xavier __le32 cq_handle_high; 4416a9a457f3SSelvin Xavier }; 4417a9a457f3SSelvin Xavier 4418a9a457f3SSelvin Xavier /* nq_srq_event (size:128b/16B) */ 4419a9a457f3SSelvin Xavier struct nq_srq_event { 4420a9a457f3SSelvin Xavier u8 type; 4421a9a457f3SSelvin Xavier #define NQ_SRQ_EVENT_TYPE_MASK 0x3fUL 4422a9a457f3SSelvin Xavier #define NQ_SRQ_EVENT_TYPE_SFT 0 4423a9a457f3SSelvin Xavier #define NQ_SRQ_EVENT_TYPE_SRQ_EVENT 0x32UL 4424a9a457f3SSelvin Xavier #define NQ_SRQ_EVENT_TYPE_LAST NQ_SRQ_EVENT_TYPE_SRQ_EVENT 44259a54460bSSelvin Xavier #define NQ_SRQ_EVENT_TOGGLE_MASK 0xc0UL 44269a54460bSSelvin Xavier #define NQ_SRQ_EVENT_TOGGLE_SFT 6 4427a9a457f3SSelvin Xavier u8 event; 4428a9a457f3SSelvin Xavier #define NQ_SRQ_EVENT_EVENT_SRQ_THRESHOLD_EVENT 0x1UL 4429a9a457f3SSelvin Xavier #define NQ_SRQ_EVENT_EVENT_LAST NQ_SRQ_EVENT_EVENT_SRQ_THRESHOLD_EVENT 4430a9a457f3SSelvin Xavier __le16 reserved16; 4431a9a457f3SSelvin Xavier __le32 srq_handle_low; 4432a9a457f3SSelvin Xavier __le32 v; 4433a9a457f3SSelvin Xavier #define NQ_SRQ_EVENT_V 0x1UL 4434a9a457f3SSelvin Xavier __le32 srq_handle_high; 4435a9a457f3SSelvin Xavier }; 4436a9a457f3SSelvin Xavier 4437a9a457f3SSelvin Xavier /* nq_dbq_event (size:128b/16B) */ 4438a9a457f3SSelvin Xavier struct nq_dbq_event { 4439a9a457f3SSelvin Xavier u8 type; 4440a9a457f3SSelvin Xavier #define NQ_DBQ_EVENT_TYPE_MASK 0x3fUL 4441a9a457f3SSelvin Xavier #define NQ_DBQ_EVENT_TYPE_SFT 0 4442a9a457f3SSelvin Xavier #define NQ_DBQ_EVENT_TYPE_DBQ_EVENT 0x34UL 4443a9a457f3SSelvin Xavier #define NQ_DBQ_EVENT_TYPE_LAST NQ_DBQ_EVENT_TYPE_DBQ_EVENT 4444a9a457f3SSelvin Xavier u8 event; 4445a9a457f3SSelvin Xavier #define NQ_DBQ_EVENT_EVENT_DBQ_THRESHOLD_EVENT 0x1UL 4446a9a457f3SSelvin Xavier #define NQ_DBQ_EVENT_EVENT_LAST NQ_DBQ_EVENT_EVENT_DBQ_THRESHOLD_EVENT 4447a9a457f3SSelvin Xavier __le16 db_pfid; 4448a9a457f3SSelvin Xavier #define NQ_DBQ_EVENT_DB_PFID_MASK 0xfUL 4449a9a457f3SSelvin Xavier #define NQ_DBQ_EVENT_DB_PFID_SFT 0 4450a9a457f3SSelvin Xavier __le32 db_dpi; 4451a9a457f3SSelvin Xavier #define NQ_DBQ_EVENT_DB_DPI_MASK 0xfffffUL 4452a9a457f3SSelvin Xavier #define NQ_DBQ_EVENT_DB_DPI_SFT 0 4453a9a457f3SSelvin Xavier __le32 v; 4454a9a457f3SSelvin Xavier #define NQ_DBQ_EVENT_V 0x1UL 4455a9a457f3SSelvin Xavier __le32 db_type_db_xid; 4456a9a457f3SSelvin Xavier #define NQ_DBQ_EVENT_DB_XID_MASK 0xfffffUL 4457a9a457f3SSelvin Xavier #define NQ_DBQ_EVENT_DB_XID_SFT 0 4458a9a457f3SSelvin Xavier #define NQ_DBQ_EVENT_DB_TYPE_MASK 0xf0000000UL 4459a9a457f3SSelvin Xavier #define NQ_DBQ_EVENT_DB_TYPE_SFT 28 4460a9a457f3SSelvin Xavier }; 4461a9a457f3SSelvin Xavier 4462a9a457f3SSelvin Xavier /* xrrq_irrq (size:256b/32B) */ 4463a9a457f3SSelvin Xavier struct xrrq_irrq { 4464a9a457f3SSelvin Xavier __le16 credits_type; 4465a9a457f3SSelvin Xavier #define XRRQ_IRRQ_TYPE 0x1UL 4466a9a457f3SSelvin Xavier #define XRRQ_IRRQ_TYPE_READ_REQ 0x0UL 4467a9a457f3SSelvin Xavier #define XRRQ_IRRQ_TYPE_ATOMIC_REQ 0x1UL 4468a9a457f3SSelvin Xavier #define XRRQ_IRRQ_TYPE_LAST XRRQ_IRRQ_TYPE_ATOMIC_REQ 4469a9a457f3SSelvin Xavier #define XRRQ_IRRQ_CREDITS_MASK 0xf800UL 4470a9a457f3SSelvin Xavier #define XRRQ_IRRQ_CREDITS_SFT 11 4471a9a457f3SSelvin Xavier __le16 reserved16; 4472a9a457f3SSelvin Xavier __le32 reserved32; 4473a9a457f3SSelvin Xavier __le32 psn; 4474a9a457f3SSelvin Xavier #define XRRQ_IRRQ_PSN_MASK 0xffffffUL 4475a9a457f3SSelvin Xavier #define XRRQ_IRRQ_PSN_SFT 0 4476a9a457f3SSelvin Xavier __le32 msn; 4477a9a457f3SSelvin Xavier #define XRRQ_IRRQ_MSN_MASK 0xffffffUL 4478a9a457f3SSelvin Xavier #define XRRQ_IRRQ_MSN_SFT 0 4479a9a457f3SSelvin Xavier __le64 va_or_atomic_result; 4480a9a457f3SSelvin Xavier __le32 rdma_r_key; 4481a9a457f3SSelvin Xavier __le32 length; 4482a9a457f3SSelvin Xavier }; 4483a9a457f3SSelvin Xavier 4484a9a457f3SSelvin Xavier /* xrrq_orrq (size:256b/32B) */ 4485a9a457f3SSelvin Xavier struct xrrq_orrq { 4486a9a457f3SSelvin Xavier __le16 num_sges_type; 4487a9a457f3SSelvin Xavier #define XRRQ_ORRQ_TYPE 0x1UL 4488a9a457f3SSelvin Xavier #define XRRQ_ORRQ_TYPE_READ_REQ 0x0UL 4489a9a457f3SSelvin Xavier #define XRRQ_ORRQ_TYPE_ATOMIC_REQ 0x1UL 4490a9a457f3SSelvin Xavier #define XRRQ_ORRQ_TYPE_LAST XRRQ_ORRQ_TYPE_ATOMIC_REQ 4491a9a457f3SSelvin Xavier #define XRRQ_ORRQ_NUM_SGES_MASK 0xf800UL 4492a9a457f3SSelvin Xavier #define XRRQ_ORRQ_NUM_SGES_SFT 11 4493a9a457f3SSelvin Xavier __le16 reserved16; 4494a9a457f3SSelvin Xavier __le32 length; 4495a9a457f3SSelvin Xavier __le32 psn; 4496a9a457f3SSelvin Xavier #define XRRQ_ORRQ_PSN_MASK 0xffffffUL 4497a9a457f3SSelvin Xavier #define XRRQ_ORRQ_PSN_SFT 0 4498a9a457f3SSelvin Xavier __le32 end_psn; 4499a9a457f3SSelvin Xavier #define XRRQ_ORRQ_END_PSN_MASK 0xffffffUL 4500a9a457f3SSelvin Xavier #define XRRQ_ORRQ_END_PSN_SFT 0 4501a9a457f3SSelvin Xavier __le64 first_sge_phy_or_sing_sge_va; 4502a9a457f3SSelvin Xavier __le32 single_sge_l_key; 4503a9a457f3SSelvin Xavier __le32 single_sge_size; 4504a9a457f3SSelvin Xavier }; 4505a9a457f3SSelvin Xavier 4506a9a457f3SSelvin Xavier /* ptu_pte (size:64b/8B) */ 4507a9a457f3SSelvin Xavier struct ptu_pte { 4508a9a457f3SSelvin Xavier __le32 page_next_to_last_last_valid[2]; 4509a9a457f3SSelvin Xavier #define PTU_PTE_VALID 0x1UL 4510a9a457f3SSelvin Xavier #define PTU_PTE_LAST 0x2UL 4511a9a457f3SSelvin Xavier #define PTU_PTE_NEXT_TO_LAST 0x4UL 4512a9a457f3SSelvin Xavier #define PTU_PTE_UNUSED_MASK 0xff8UL 4513a9a457f3SSelvin Xavier #define PTU_PTE_UNUSED_SFT 3 4514a9a457f3SSelvin Xavier #define PTU_PTE_PAGE_MASK 0xfffff000UL 4515a9a457f3SSelvin Xavier #define PTU_PTE_PAGE_SFT 12 4516a9a457f3SSelvin Xavier }; 4517a9a457f3SSelvin Xavier 4518a9a457f3SSelvin Xavier /* ptu_pde (size:64b/8B) */ 4519a9a457f3SSelvin Xavier struct ptu_pde { 4520a9a457f3SSelvin Xavier __le32 page_valid[2]; 4521a9a457f3SSelvin Xavier #define PTU_PDE_VALID 0x1UL 4522a9a457f3SSelvin Xavier #define PTU_PDE_UNUSED_MASK 0xffeUL 4523a9a457f3SSelvin Xavier #define PTU_PDE_UNUSED_SFT 1 4524a9a457f3SSelvin Xavier #define PTU_PDE_PAGE_MASK 0xfffff000UL 4525a9a457f3SSelvin Xavier #define PTU_PDE_PAGE_SFT 12 4526a9a457f3SSelvin Xavier }; 4527a9a457f3SSelvin Xavier 4528a9a457f3SSelvin Xavier #endif /* ___BNXT_RE_HSI_H__ */ 4529