1 /* 2 * Broadcom NetXtreme-E RoCE driver. 3 * 4 * Copyright (c) 2016 - 2017, Broadcom. All rights reserved. The term 5 * Broadcom refers to Broadcom Limited and/or its subsidiaries. 6 * 7 * This software is available to you under a choice of one of two 8 * licenses. You may choose to be licensed under the terms of the GNU 9 * General Public License (GPL) Version 2, available from the file 10 * COPYING in the main directory of this source tree, or the 11 * BSD license below: 12 * 13 * Redistribution and use in source and binary forms, with or without 14 * modification, are permitted provided that the following conditions 15 * are met: 16 * 17 * 1. Redistributions of source code must retain the above copyright 18 * notice, this list of conditions and the following disclaimer. 19 * 2. Redistributions in binary form must reproduce the above copyright 20 * notice, this list of conditions and the following disclaimer in 21 * the documentation and/or other materials provided with the 22 * distribution. 23 * 24 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' 25 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, 26 * THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR 27 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS 28 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 29 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 30 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR 31 * BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, 32 * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE 33 * OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN 34 * IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 35 * 36 * Description: Slow Path Operators 37 */ 38 39 #define dev_fmt(fmt) "QPLIB: " fmt 40 41 #include <linux/interrupt.h> 42 #include <linux/spinlock.h> 43 #include <linux/sched.h> 44 #include <linux/pci.h> 45 46 #include "roce_hsi.h" 47 48 #include "qplib_res.h" 49 #include "qplib_rcfw.h" 50 #include "qplib_sp.h" 51 52 const struct bnxt_qplib_gid bnxt_qplib_gid_zero = {{ 0, 0, 0, 0, 0, 0, 0, 0, 53 0, 0, 0, 0, 0, 0, 0, 0 } }; 54 55 /* Device */ 56 57 static bool bnxt_qplib_is_atomic_cap(struct bnxt_qplib_rcfw *rcfw) 58 { 59 u16 pcie_ctl2 = 0; 60 61 if (!bnxt_qplib_is_chip_gen_p5(rcfw->res->cctx)) 62 return false; 63 64 pcie_capability_read_word(rcfw->pdev, PCI_EXP_DEVCTL2, &pcie_ctl2); 65 return (pcie_ctl2 & PCI_EXP_DEVCTL2_ATOMIC_REQ); 66 } 67 68 static void bnxt_qplib_query_version(struct bnxt_qplib_rcfw *rcfw, 69 char *fw_ver) 70 { 71 struct cmdq_query_version req; 72 struct creq_query_version_resp resp; 73 int rc = 0; 74 75 bnxt_qplib_rcfw_cmd_prep((struct cmdq_base *)&req, 76 CMDQ_BASE_OPCODE_QUERY_VERSION, 77 sizeof(req)); 78 79 rc = bnxt_qplib_rcfw_send_message(rcfw, (void *)&req, 80 (void *)&resp, NULL, 0); 81 if (rc) 82 return; 83 fw_ver[0] = resp.fw_maj; 84 fw_ver[1] = resp.fw_minor; 85 fw_ver[2] = resp.fw_bld; 86 fw_ver[3] = resp.fw_rsvd; 87 } 88 89 int bnxt_qplib_get_dev_attr(struct bnxt_qplib_rcfw *rcfw, 90 struct bnxt_qplib_dev_attr *attr, bool vf) 91 { 92 struct creq_query_func_resp_sb *sb; 93 struct bnxt_qplib_rcfw_sbuf *sbuf; 94 struct creq_query_func_resp resp; 95 struct cmdq_query_func req; 96 u8 *tqm_alloc; 97 int i, rc = 0; 98 u32 temp; 99 100 bnxt_qplib_rcfw_cmd_prep((struct cmdq_base *)&req, 101 CMDQ_BASE_OPCODE_QUERY_FUNC, 102 sizeof(req)); 103 104 sbuf = bnxt_qplib_rcfw_alloc_sbuf(rcfw, sizeof(*sb)); 105 if (!sbuf) { 106 dev_err(&rcfw->pdev->dev, 107 "SP: QUERY_FUNC alloc side buffer failed\n"); 108 return -ENOMEM; 109 } 110 111 sb = sbuf->sb; 112 req.resp_size = sizeof(*sb) / BNXT_QPLIB_CMDQE_UNITS; 113 rc = bnxt_qplib_rcfw_send_message(rcfw, (void *)&req, (void *)&resp, 114 (void *)sbuf, 0); 115 if (rc) 116 goto bail; 117 118 /* Extract the context from the side buffer */ 119 attr->max_qp = le32_to_cpu(sb->max_qp); 120 /* max_qp value reported by FW for PF doesn't include the QP1 for PF */ 121 if (!vf) 122 attr->max_qp += 1; 123 attr->max_qp_rd_atom = 124 sb->max_qp_rd_atom > BNXT_QPLIB_MAX_OUT_RD_ATOM ? 125 BNXT_QPLIB_MAX_OUT_RD_ATOM : sb->max_qp_rd_atom; 126 attr->max_qp_init_rd_atom = 127 sb->max_qp_init_rd_atom > BNXT_QPLIB_MAX_OUT_RD_ATOM ? 128 BNXT_QPLIB_MAX_OUT_RD_ATOM : sb->max_qp_init_rd_atom; 129 attr->max_qp_wqes = le16_to_cpu(sb->max_qp_wr); 130 /* 131 * 128 WQEs needs to be reserved for the HW (8916). Prevent 132 * reporting the max number 133 */ 134 attr->max_qp_wqes -= BNXT_QPLIB_RESERVED_QP_WRS + 1; 135 attr->max_qp_sges = bnxt_qplib_is_chip_gen_p5(rcfw->res->cctx) ? 136 6 : sb->max_sge; 137 attr->max_cq = le32_to_cpu(sb->max_cq); 138 attr->max_cq_wqes = le32_to_cpu(sb->max_cqe); 139 attr->max_cq_sges = attr->max_qp_sges; 140 attr->max_mr = le32_to_cpu(sb->max_mr); 141 attr->max_mw = le32_to_cpu(sb->max_mw); 142 143 attr->max_mr_size = le64_to_cpu(sb->max_mr_size); 144 attr->max_pd = 64 * 1024; 145 attr->max_raw_ethy_qp = le32_to_cpu(sb->max_raw_eth_qp); 146 attr->max_ah = le32_to_cpu(sb->max_ah); 147 148 attr->max_srq = le16_to_cpu(sb->max_srq); 149 attr->max_srq_wqes = le32_to_cpu(sb->max_srq_wr) - 1; 150 attr->max_srq_sges = sb->max_srq_sge; 151 attr->max_pkey = 1; 152 attr->max_inline_data = le32_to_cpu(sb->max_inline_data); 153 attr->l2_db_size = (sb->l2_db_space_size + 1) * 154 (0x01 << RCFW_DBR_BASE_PAGE_SHIFT); 155 attr->max_sgid = BNXT_QPLIB_NUM_GIDS_SUPPORTED; 156 attr->dev_cap_flags = le16_to_cpu(sb->dev_cap_flags); 157 158 bnxt_qplib_query_version(rcfw, attr->fw_ver); 159 160 for (i = 0; i < MAX_TQM_ALLOC_REQ / 4; i++) { 161 temp = le32_to_cpu(sb->tqm_alloc_reqs[i]); 162 tqm_alloc = (u8 *)&temp; 163 attr->tqm_alloc_reqs[i * 4] = *tqm_alloc; 164 attr->tqm_alloc_reqs[i * 4 + 1] = *(++tqm_alloc); 165 attr->tqm_alloc_reqs[i * 4 + 2] = *(++tqm_alloc); 166 attr->tqm_alloc_reqs[i * 4 + 3] = *(++tqm_alloc); 167 } 168 169 attr->is_atomic = bnxt_qplib_is_atomic_cap(rcfw); 170 bail: 171 bnxt_qplib_rcfw_free_sbuf(rcfw, sbuf); 172 return rc; 173 } 174 175 int bnxt_qplib_set_func_resources(struct bnxt_qplib_res *res, 176 struct bnxt_qplib_rcfw *rcfw, 177 struct bnxt_qplib_ctx *ctx) 178 { 179 struct cmdq_set_func_resources req; 180 struct creq_set_func_resources_resp resp; 181 int rc = 0; 182 183 bnxt_qplib_rcfw_cmd_prep((struct cmdq_base *)&req, 184 CMDQ_BASE_OPCODE_SET_FUNC_RESOURCES, 185 sizeof(req)); 186 187 req.number_of_qp = cpu_to_le32(ctx->qpc_count); 188 req.number_of_mrw = cpu_to_le32(ctx->mrw_count); 189 req.number_of_srq = cpu_to_le32(ctx->srqc_count); 190 req.number_of_cq = cpu_to_le32(ctx->cq_count); 191 192 req.max_qp_per_vf = cpu_to_le32(ctx->vf_res.max_qp_per_vf); 193 req.max_mrw_per_vf = cpu_to_le32(ctx->vf_res.max_mrw_per_vf); 194 req.max_srq_per_vf = cpu_to_le32(ctx->vf_res.max_srq_per_vf); 195 req.max_cq_per_vf = cpu_to_le32(ctx->vf_res.max_cq_per_vf); 196 req.max_gid_per_vf = cpu_to_le32(ctx->vf_res.max_gid_per_vf); 197 198 rc = bnxt_qplib_rcfw_send_message(rcfw, (void *)&req, 199 (void *)&resp, 200 NULL, 0); 201 if (rc) { 202 dev_err(&res->pdev->dev, "Failed to set function resources\n"); 203 } 204 return rc; 205 } 206 207 /* SGID */ 208 int bnxt_qplib_get_sgid(struct bnxt_qplib_res *res, 209 struct bnxt_qplib_sgid_tbl *sgid_tbl, int index, 210 struct bnxt_qplib_gid *gid) 211 { 212 if (index >= sgid_tbl->max) { 213 dev_err(&res->pdev->dev, 214 "Index %d exceeded SGID table max (%d)\n", 215 index, sgid_tbl->max); 216 return -EINVAL; 217 } 218 memcpy(gid, &sgid_tbl->tbl[index].gid, sizeof(*gid)); 219 return 0; 220 } 221 222 int bnxt_qplib_del_sgid(struct bnxt_qplib_sgid_tbl *sgid_tbl, 223 struct bnxt_qplib_gid *gid, u16 vlan_id, bool update) 224 { 225 struct bnxt_qplib_res *res = to_bnxt_qplib(sgid_tbl, 226 struct bnxt_qplib_res, 227 sgid_tbl); 228 struct bnxt_qplib_rcfw *rcfw = res->rcfw; 229 int index; 230 231 if (!sgid_tbl) { 232 dev_err(&res->pdev->dev, "SGID table not allocated\n"); 233 return -EINVAL; 234 } 235 /* Do we need a sgid_lock here? */ 236 if (!sgid_tbl->active) { 237 dev_err(&res->pdev->dev, "SGID table has no active entries\n"); 238 return -ENOMEM; 239 } 240 for (index = 0; index < sgid_tbl->max; index++) { 241 if (!memcmp(&sgid_tbl->tbl[index].gid, gid, sizeof(*gid)) && 242 vlan_id == sgid_tbl->tbl[index].vlan_id) 243 break; 244 } 245 if (index == sgid_tbl->max) { 246 dev_warn(&res->pdev->dev, "GID not found in the SGID table\n"); 247 return 0; 248 } 249 /* Remove GID from the SGID table */ 250 if (update) { 251 struct cmdq_delete_gid req; 252 struct creq_delete_gid_resp resp; 253 int rc; 254 255 bnxt_qplib_rcfw_cmd_prep((struct cmdq_base *)&req, 256 CMDQ_BASE_OPCODE_DELETE_GID, 257 sizeof(req)); 258 if (sgid_tbl->hw_id[index] == 0xFFFF) { 259 dev_err(&res->pdev->dev, 260 "GID entry contains an invalid HW id\n"); 261 return -EINVAL; 262 } 263 req.gid_index = cpu_to_le16(sgid_tbl->hw_id[index]); 264 rc = bnxt_qplib_rcfw_send_message(rcfw, (void *)&req, 265 (void *)&resp, NULL, 0); 266 if (rc) 267 return rc; 268 } 269 memcpy(&sgid_tbl->tbl[index].gid, &bnxt_qplib_gid_zero, 270 sizeof(bnxt_qplib_gid_zero)); 271 sgid_tbl->tbl[index].vlan_id = 0xFFFF; 272 sgid_tbl->vlan[index] = 0; 273 sgid_tbl->active--; 274 dev_dbg(&res->pdev->dev, 275 "SGID deleted hw_id[0x%x] = 0x%x active = 0x%x\n", 276 index, sgid_tbl->hw_id[index], sgid_tbl->active); 277 sgid_tbl->hw_id[index] = (u16)-1; 278 279 /* unlock */ 280 return 0; 281 } 282 283 int bnxt_qplib_add_sgid(struct bnxt_qplib_sgid_tbl *sgid_tbl, 284 struct bnxt_qplib_gid *gid, const u8 *smac, 285 u16 vlan_id, bool update, u32 *index) 286 { 287 struct bnxt_qplib_res *res = to_bnxt_qplib(sgid_tbl, 288 struct bnxt_qplib_res, 289 sgid_tbl); 290 struct bnxt_qplib_rcfw *rcfw = res->rcfw; 291 int i, free_idx; 292 293 if (!sgid_tbl) { 294 dev_err(&res->pdev->dev, "SGID table not allocated\n"); 295 return -EINVAL; 296 } 297 /* Do we need a sgid_lock here? */ 298 if (sgid_tbl->active == sgid_tbl->max) { 299 dev_err(&res->pdev->dev, "SGID table is full\n"); 300 return -ENOMEM; 301 } 302 free_idx = sgid_tbl->max; 303 for (i = 0; i < sgid_tbl->max; i++) { 304 if (!memcmp(&sgid_tbl->tbl[i], gid, sizeof(*gid)) && 305 sgid_tbl->tbl[i].vlan_id == vlan_id) { 306 dev_dbg(&res->pdev->dev, 307 "SGID entry already exist in entry %d!\n", i); 308 *index = i; 309 return -EALREADY; 310 } else if (!memcmp(&sgid_tbl->tbl[i], &bnxt_qplib_gid_zero, 311 sizeof(bnxt_qplib_gid_zero)) && 312 free_idx == sgid_tbl->max) { 313 free_idx = i; 314 } 315 } 316 if (free_idx == sgid_tbl->max) { 317 dev_err(&res->pdev->dev, 318 "SGID table is FULL but count is not MAX??\n"); 319 return -ENOMEM; 320 } 321 if (update) { 322 struct cmdq_add_gid req; 323 struct creq_add_gid_resp resp; 324 int rc; 325 326 bnxt_qplib_rcfw_cmd_prep((struct cmdq_base *)&req, 327 CMDQ_BASE_OPCODE_ADD_GID, 328 sizeof(req)); 329 330 req.gid[0] = cpu_to_be32(((u32 *)gid->data)[3]); 331 req.gid[1] = cpu_to_be32(((u32 *)gid->data)[2]); 332 req.gid[2] = cpu_to_be32(((u32 *)gid->data)[1]); 333 req.gid[3] = cpu_to_be32(((u32 *)gid->data)[0]); 334 /* 335 * driver should ensure that all RoCE traffic is always VLAN 336 * tagged if RoCE traffic is running on non-zero VLAN ID or 337 * RoCE traffic is running on non-zero Priority. 338 */ 339 if ((vlan_id != 0xFFFF) || res->prio) { 340 if (vlan_id != 0xFFFF) 341 req.vlan = cpu_to_le16 342 (vlan_id & CMDQ_ADD_GID_VLAN_VLAN_ID_MASK); 343 req.vlan |= cpu_to_le16 344 (CMDQ_ADD_GID_VLAN_TPID_TPID_8100 | 345 CMDQ_ADD_GID_VLAN_VLAN_EN); 346 } 347 348 /* MAC in network format */ 349 req.src_mac[0] = cpu_to_be16(((u16 *)smac)[0]); 350 req.src_mac[1] = cpu_to_be16(((u16 *)smac)[1]); 351 req.src_mac[2] = cpu_to_be16(((u16 *)smac)[2]); 352 353 rc = bnxt_qplib_rcfw_send_message(rcfw, (void *)&req, 354 (void *)&resp, NULL, 0); 355 if (rc) 356 return rc; 357 sgid_tbl->hw_id[free_idx] = le32_to_cpu(resp.xid); 358 } 359 /* Add GID to the sgid_tbl */ 360 memcpy(&sgid_tbl->tbl[free_idx], gid, sizeof(*gid)); 361 sgid_tbl->tbl[free_idx].vlan_id = vlan_id; 362 sgid_tbl->active++; 363 if (vlan_id != 0xFFFF) 364 sgid_tbl->vlan[free_idx] = 1; 365 366 dev_dbg(&res->pdev->dev, 367 "SGID added hw_id[0x%x] = 0x%x active = 0x%x\n", 368 free_idx, sgid_tbl->hw_id[free_idx], sgid_tbl->active); 369 370 *index = free_idx; 371 /* unlock */ 372 return 0; 373 } 374 375 int bnxt_qplib_update_sgid(struct bnxt_qplib_sgid_tbl *sgid_tbl, 376 struct bnxt_qplib_gid *gid, u16 gid_idx, 377 const u8 *smac) 378 { 379 struct bnxt_qplib_res *res = to_bnxt_qplib(sgid_tbl, 380 struct bnxt_qplib_res, 381 sgid_tbl); 382 struct bnxt_qplib_rcfw *rcfw = res->rcfw; 383 struct creq_modify_gid_resp resp; 384 struct cmdq_modify_gid req; 385 int rc; 386 387 bnxt_qplib_rcfw_cmd_prep((struct cmdq_base *)&req, 388 CMDQ_BASE_OPCODE_MODIFY_GID, 389 sizeof(req)); 390 391 req.gid[0] = cpu_to_be32(((u32 *)gid->data)[3]); 392 req.gid[1] = cpu_to_be32(((u32 *)gid->data)[2]); 393 req.gid[2] = cpu_to_be32(((u32 *)gid->data)[1]); 394 req.gid[3] = cpu_to_be32(((u32 *)gid->data)[0]); 395 if (res->prio) { 396 req.vlan |= cpu_to_le16 397 (CMDQ_ADD_GID_VLAN_TPID_TPID_8100 | 398 CMDQ_ADD_GID_VLAN_VLAN_EN); 399 } 400 401 /* MAC in network format */ 402 req.src_mac[0] = cpu_to_be16(((u16 *)smac)[0]); 403 req.src_mac[1] = cpu_to_be16(((u16 *)smac)[1]); 404 req.src_mac[2] = cpu_to_be16(((u16 *)smac)[2]); 405 406 req.gid_index = cpu_to_le16(gid_idx); 407 408 rc = bnxt_qplib_rcfw_send_message(rcfw, (void *)&req, 409 (void *)&resp, NULL, 0); 410 return rc; 411 } 412 413 /* AH */ 414 int bnxt_qplib_create_ah(struct bnxt_qplib_res *res, struct bnxt_qplib_ah *ah, 415 bool block) 416 { 417 struct bnxt_qplib_rcfw *rcfw = res->rcfw; 418 struct cmdq_create_ah req; 419 struct creq_create_ah_resp resp; 420 u32 temp32[4]; 421 u16 temp16[3]; 422 int rc; 423 424 bnxt_qplib_rcfw_cmd_prep((struct cmdq_base *)&req, 425 CMDQ_BASE_OPCODE_CREATE_AH, 426 sizeof(req)); 427 428 memcpy(temp32, ah->dgid.data, sizeof(struct bnxt_qplib_gid)); 429 req.dgid[0] = cpu_to_le32(temp32[0]); 430 req.dgid[1] = cpu_to_le32(temp32[1]); 431 req.dgid[2] = cpu_to_le32(temp32[2]); 432 req.dgid[3] = cpu_to_le32(temp32[3]); 433 434 req.type = ah->nw_type; 435 req.hop_limit = ah->hop_limit; 436 req.sgid_index = cpu_to_le16(res->sgid_tbl.hw_id[ah->sgid_index]); 437 req.dest_vlan_id_flow_label = cpu_to_le32((ah->flow_label & 438 CMDQ_CREATE_AH_FLOW_LABEL_MASK) | 439 CMDQ_CREATE_AH_DEST_VLAN_ID_MASK); 440 req.pd_id = cpu_to_le32(ah->pd->id); 441 req.traffic_class = ah->traffic_class; 442 443 /* MAC in network format */ 444 memcpy(temp16, ah->dmac, 6); 445 req.dest_mac[0] = cpu_to_le16(temp16[0]); 446 req.dest_mac[1] = cpu_to_le16(temp16[1]); 447 req.dest_mac[2] = cpu_to_le16(temp16[2]); 448 449 rc = bnxt_qplib_rcfw_send_message(rcfw, (void *)&req, (void *)&resp, 450 NULL, block); 451 if (rc) 452 return rc; 453 454 ah->id = le32_to_cpu(resp.xid); 455 return 0; 456 } 457 458 void bnxt_qplib_destroy_ah(struct bnxt_qplib_res *res, struct bnxt_qplib_ah *ah, 459 bool block) 460 { 461 struct bnxt_qplib_rcfw *rcfw = res->rcfw; 462 struct cmdq_destroy_ah req; 463 struct creq_destroy_ah_resp resp; 464 465 /* Clean up the AH table in the device */ 466 bnxt_qplib_rcfw_cmd_prep((struct cmdq_base *)&req, 467 CMDQ_BASE_OPCODE_DESTROY_AH, 468 sizeof(req)); 469 470 req.ah_cid = cpu_to_le32(ah->id); 471 472 bnxt_qplib_rcfw_send_message(rcfw, (void *)&req, (void *)&resp, NULL, 473 block); 474 } 475 476 /* MRW */ 477 int bnxt_qplib_free_mrw(struct bnxt_qplib_res *res, struct bnxt_qplib_mrw *mrw) 478 { 479 struct bnxt_qplib_rcfw *rcfw = res->rcfw; 480 struct cmdq_deallocate_key req; 481 struct creq_deallocate_key_resp resp; 482 int rc; 483 484 if (mrw->lkey == 0xFFFFFFFF) { 485 dev_info(&res->pdev->dev, "SP: Free a reserved lkey MRW\n"); 486 return 0; 487 } 488 489 bnxt_qplib_rcfw_cmd_prep((struct cmdq_base *)&req, 490 CMDQ_BASE_OPCODE_DEALLOCATE_KEY, 491 sizeof(req)); 492 493 req.mrw_flags = mrw->type; 494 495 if ((mrw->type == CMDQ_ALLOCATE_MRW_MRW_FLAGS_MW_TYPE1) || 496 (mrw->type == CMDQ_ALLOCATE_MRW_MRW_FLAGS_MW_TYPE2A) || 497 (mrw->type == CMDQ_ALLOCATE_MRW_MRW_FLAGS_MW_TYPE2B)) 498 req.key = cpu_to_le32(mrw->rkey); 499 else 500 req.key = cpu_to_le32(mrw->lkey); 501 502 rc = bnxt_qplib_rcfw_send_message(rcfw, (void *)&req, (void *)&resp, 503 NULL, 0); 504 if (rc) 505 return rc; 506 507 /* Free the qplib's MRW memory */ 508 if (mrw->hwq.max_elements) 509 bnxt_qplib_free_hwq(res, &mrw->hwq); 510 511 return 0; 512 } 513 514 int bnxt_qplib_alloc_mrw(struct bnxt_qplib_res *res, struct bnxt_qplib_mrw *mrw) 515 { 516 struct bnxt_qplib_rcfw *rcfw = res->rcfw; 517 struct cmdq_allocate_mrw req; 518 struct creq_allocate_mrw_resp resp; 519 unsigned long tmp; 520 int rc; 521 522 bnxt_qplib_rcfw_cmd_prep((struct cmdq_base *)&req, 523 CMDQ_BASE_OPCODE_ALLOCATE_MRW, 524 sizeof(req)); 525 526 req.pd_id = cpu_to_le32(mrw->pd->id); 527 req.mrw_flags = mrw->type; 528 if ((mrw->type == CMDQ_ALLOCATE_MRW_MRW_FLAGS_PMR && 529 mrw->flags & BNXT_QPLIB_FR_PMR) || 530 mrw->type == CMDQ_ALLOCATE_MRW_MRW_FLAGS_MW_TYPE2A || 531 mrw->type == CMDQ_ALLOCATE_MRW_MRW_FLAGS_MW_TYPE2B) 532 req.access = CMDQ_ALLOCATE_MRW_ACCESS_CONSUMER_OWNED_KEY; 533 tmp = (unsigned long)mrw; 534 req.mrw_handle = cpu_to_le64(tmp); 535 536 rc = bnxt_qplib_rcfw_send_message(rcfw, (void *)&req, 537 (void *)&resp, NULL, 0); 538 if (rc) 539 return rc; 540 541 if ((mrw->type == CMDQ_ALLOCATE_MRW_MRW_FLAGS_MW_TYPE1) || 542 (mrw->type == CMDQ_ALLOCATE_MRW_MRW_FLAGS_MW_TYPE2A) || 543 (mrw->type == CMDQ_ALLOCATE_MRW_MRW_FLAGS_MW_TYPE2B)) 544 mrw->rkey = le32_to_cpu(resp.xid); 545 else 546 mrw->lkey = le32_to_cpu(resp.xid); 547 return 0; 548 } 549 550 int bnxt_qplib_dereg_mrw(struct bnxt_qplib_res *res, struct bnxt_qplib_mrw *mrw, 551 bool block) 552 { 553 struct bnxt_qplib_rcfw *rcfw = res->rcfw; 554 struct cmdq_deregister_mr req; 555 struct creq_deregister_mr_resp resp; 556 int rc; 557 558 bnxt_qplib_rcfw_cmd_prep((struct cmdq_base *)&req, 559 CMDQ_BASE_OPCODE_DEREGISTER_MR, 560 sizeof(req)); 561 562 req.lkey = cpu_to_le32(mrw->lkey); 563 rc = bnxt_qplib_rcfw_send_message(rcfw, (void *)&req, 564 (void *)&resp, NULL, block); 565 if (rc) 566 return rc; 567 568 /* Free the qplib's MR memory */ 569 if (mrw->hwq.max_elements) { 570 mrw->va = 0; 571 mrw->total_size = 0; 572 bnxt_qplib_free_hwq(res, &mrw->hwq); 573 } 574 575 return 0; 576 } 577 578 int bnxt_qplib_reg_mr(struct bnxt_qplib_res *res, struct bnxt_qplib_mrw *mr, 579 struct ib_umem *umem, int num_pbls, u32 buf_pg_size) 580 { 581 struct bnxt_qplib_rcfw *rcfw = res->rcfw; 582 struct bnxt_qplib_hwq_attr hwq_attr = {}; 583 struct bnxt_qplib_sg_info sginfo = {}; 584 struct creq_register_mr_resp resp; 585 struct cmdq_register_mr req; 586 int pages, rc; 587 u32 pg_size; 588 u16 level; 589 590 if (num_pbls) { 591 pages = roundup_pow_of_two(num_pbls); 592 /* Allocate memory for the non-leaf pages to store buf ptrs. 593 * Non-leaf pages always uses system PAGE_SIZE 594 */ 595 /* Free the hwq if it already exist, must be a rereg */ 596 if (mr->hwq.max_elements) 597 bnxt_qplib_free_hwq(res, &mr->hwq); 598 /* Use system PAGE_SIZE */ 599 hwq_attr.res = res; 600 hwq_attr.depth = pages; 601 hwq_attr.stride = buf_pg_size; 602 hwq_attr.type = HWQ_TYPE_MR; 603 hwq_attr.sginfo = &sginfo; 604 hwq_attr.sginfo->umem = umem; 605 hwq_attr.sginfo->npages = pages; 606 hwq_attr.sginfo->pgsize = PAGE_SIZE; 607 hwq_attr.sginfo->pgshft = PAGE_SHIFT; 608 rc = bnxt_qplib_alloc_init_hwq(&mr->hwq, &hwq_attr); 609 if (rc) { 610 dev_err(&res->pdev->dev, 611 "SP: Reg MR memory allocation failed\n"); 612 return -ENOMEM; 613 } 614 } 615 616 bnxt_qplib_rcfw_cmd_prep((struct cmdq_base *)&req, 617 CMDQ_BASE_OPCODE_REGISTER_MR, 618 sizeof(req)); 619 620 /* Configure the request */ 621 if (mr->hwq.level == PBL_LVL_MAX) { 622 /* No PBL provided, just use system PAGE_SIZE */ 623 level = 0; 624 req.pbl = 0; 625 pg_size = PAGE_SIZE; 626 } else { 627 level = mr->hwq.level; 628 req.pbl = cpu_to_le64(mr->hwq.pbl[PBL_LVL_0].pg_map_arr[0]); 629 } 630 pg_size = buf_pg_size ? buf_pg_size : PAGE_SIZE; 631 req.log2_pg_size_lvl = (level << CMDQ_REGISTER_MR_LVL_SFT) | 632 ((ilog2(pg_size) << 633 CMDQ_REGISTER_MR_LOG2_PG_SIZE_SFT) & 634 CMDQ_REGISTER_MR_LOG2_PG_SIZE_MASK); 635 req.log2_pbl_pg_size = cpu_to_le16(((ilog2(PAGE_SIZE) << 636 CMDQ_REGISTER_MR_LOG2_PBL_PG_SIZE_SFT) & 637 CMDQ_REGISTER_MR_LOG2_PBL_PG_SIZE_MASK)); 638 req.access = (mr->flags & 0xFFFF); 639 req.va = cpu_to_le64(mr->va); 640 req.key = cpu_to_le32(mr->lkey); 641 req.mr_size = cpu_to_le64(mr->total_size); 642 643 rc = bnxt_qplib_rcfw_send_message(rcfw, (void *)&req, 644 (void *)&resp, NULL, false); 645 if (rc) 646 goto fail; 647 648 return 0; 649 650 fail: 651 if (mr->hwq.max_elements) 652 bnxt_qplib_free_hwq(res, &mr->hwq); 653 return rc; 654 } 655 656 int bnxt_qplib_alloc_fast_reg_page_list(struct bnxt_qplib_res *res, 657 struct bnxt_qplib_frpl *frpl, 658 int max_pg_ptrs) 659 { 660 struct bnxt_qplib_hwq_attr hwq_attr = {}; 661 struct bnxt_qplib_sg_info sginfo = {}; 662 int pg_ptrs, pages, rc; 663 664 /* Re-calculate the max to fit the HWQ allocation model */ 665 pg_ptrs = roundup_pow_of_two(max_pg_ptrs); 666 pages = pg_ptrs >> MAX_PBL_LVL_1_PGS_SHIFT; 667 if (!pages) 668 pages++; 669 670 if (pages > MAX_PBL_LVL_1_PGS) 671 return -ENOMEM; 672 673 sginfo.pgsize = PAGE_SIZE; 674 sginfo.nopte = true; 675 676 hwq_attr.res = res; 677 hwq_attr.depth = pg_ptrs; 678 hwq_attr.stride = PAGE_SIZE; 679 hwq_attr.sginfo = &sginfo; 680 hwq_attr.type = HWQ_TYPE_CTX; 681 rc = bnxt_qplib_alloc_init_hwq(&frpl->hwq, &hwq_attr); 682 if (!rc) 683 frpl->max_pg_ptrs = pg_ptrs; 684 685 return rc; 686 } 687 688 int bnxt_qplib_free_fast_reg_page_list(struct bnxt_qplib_res *res, 689 struct bnxt_qplib_frpl *frpl) 690 { 691 bnxt_qplib_free_hwq(res, &frpl->hwq); 692 return 0; 693 } 694 695 int bnxt_qplib_get_roce_stats(struct bnxt_qplib_rcfw *rcfw, 696 struct bnxt_qplib_roce_stats *stats) 697 { 698 struct cmdq_query_roce_stats req; 699 struct creq_query_roce_stats_resp resp; 700 struct bnxt_qplib_rcfw_sbuf *sbuf; 701 struct creq_query_roce_stats_resp_sb *sb; 702 int rc = 0; 703 704 bnxt_qplib_rcfw_cmd_prep((struct cmdq_base *)&req, 705 CMDQ_BASE_OPCODE_QUERY_ROCE_STATS, 706 sizeof(req)); 707 708 sbuf = bnxt_qplib_rcfw_alloc_sbuf(rcfw, sizeof(*sb)); 709 if (!sbuf) { 710 dev_err(&rcfw->pdev->dev, 711 "SP: QUERY_ROCE_STATS alloc side buffer failed\n"); 712 return -ENOMEM; 713 } 714 715 sb = sbuf->sb; 716 req.resp_size = sizeof(*sb) / BNXT_QPLIB_CMDQE_UNITS; 717 rc = bnxt_qplib_rcfw_send_message(rcfw, (void *)&req, (void *)&resp, 718 (void *)sbuf, 0); 719 if (rc) 720 goto bail; 721 /* Extract the context from the side buffer */ 722 stats->to_retransmits = le64_to_cpu(sb->to_retransmits); 723 stats->seq_err_naks_rcvd = le64_to_cpu(sb->seq_err_naks_rcvd); 724 stats->max_retry_exceeded = le64_to_cpu(sb->max_retry_exceeded); 725 stats->rnr_naks_rcvd = le64_to_cpu(sb->rnr_naks_rcvd); 726 stats->missing_resp = le64_to_cpu(sb->missing_resp); 727 stats->unrecoverable_err = le64_to_cpu(sb->unrecoverable_err); 728 stats->bad_resp_err = le64_to_cpu(sb->bad_resp_err); 729 stats->local_qp_op_err = le64_to_cpu(sb->local_qp_op_err); 730 stats->local_protection_err = le64_to_cpu(sb->local_protection_err); 731 stats->mem_mgmt_op_err = le64_to_cpu(sb->mem_mgmt_op_err); 732 stats->remote_invalid_req_err = le64_to_cpu(sb->remote_invalid_req_err); 733 stats->remote_access_err = le64_to_cpu(sb->remote_access_err); 734 stats->remote_op_err = le64_to_cpu(sb->remote_op_err); 735 stats->dup_req = le64_to_cpu(sb->dup_req); 736 stats->res_exceed_max = le64_to_cpu(sb->res_exceed_max); 737 stats->res_length_mismatch = le64_to_cpu(sb->res_length_mismatch); 738 stats->res_exceeds_wqe = le64_to_cpu(sb->res_exceeds_wqe); 739 stats->res_opcode_err = le64_to_cpu(sb->res_opcode_err); 740 stats->res_rx_invalid_rkey = le64_to_cpu(sb->res_rx_invalid_rkey); 741 stats->res_rx_domain_err = le64_to_cpu(sb->res_rx_domain_err); 742 stats->res_rx_no_perm = le64_to_cpu(sb->res_rx_no_perm); 743 stats->res_rx_range_err = le64_to_cpu(sb->res_rx_range_err); 744 stats->res_tx_invalid_rkey = le64_to_cpu(sb->res_tx_invalid_rkey); 745 stats->res_tx_domain_err = le64_to_cpu(sb->res_tx_domain_err); 746 stats->res_tx_no_perm = le64_to_cpu(sb->res_tx_no_perm); 747 stats->res_tx_range_err = le64_to_cpu(sb->res_tx_range_err); 748 stats->res_irrq_oflow = le64_to_cpu(sb->res_irrq_oflow); 749 stats->res_unsup_opcode = le64_to_cpu(sb->res_unsup_opcode); 750 stats->res_unaligned_atomic = le64_to_cpu(sb->res_unaligned_atomic); 751 stats->res_rem_inv_err = le64_to_cpu(sb->res_rem_inv_err); 752 stats->res_mem_error = le64_to_cpu(sb->res_mem_error); 753 stats->res_srq_err = le64_to_cpu(sb->res_srq_err); 754 stats->res_cmp_err = le64_to_cpu(sb->res_cmp_err); 755 stats->res_invalid_dup_rkey = le64_to_cpu(sb->res_invalid_dup_rkey); 756 stats->res_wqe_format_err = le64_to_cpu(sb->res_wqe_format_err); 757 stats->res_cq_load_err = le64_to_cpu(sb->res_cq_load_err); 758 stats->res_srq_load_err = le64_to_cpu(sb->res_srq_load_err); 759 stats->res_tx_pci_err = le64_to_cpu(sb->res_tx_pci_err); 760 stats->res_rx_pci_err = le64_to_cpu(sb->res_rx_pci_err); 761 if (!rcfw->init_oos_stats) { 762 rcfw->oos_prev = le64_to_cpu(sb->res_oos_drop_count); 763 rcfw->init_oos_stats = 1; 764 } else { 765 stats->res_oos_drop_count += 766 (le64_to_cpu(sb->res_oos_drop_count) - 767 rcfw->oos_prev) & BNXT_QPLIB_OOS_COUNT_MASK; 768 rcfw->oos_prev = le64_to_cpu(sb->res_oos_drop_count); 769 } 770 771 bail: 772 bnxt_qplib_rcfw_free_sbuf(rcfw, sbuf); 773 return rc; 774 } 775 776 int bnxt_qplib_qext_stat(struct bnxt_qplib_rcfw *rcfw, u32 fid, 777 struct bnxt_qplib_ext_stat *estat) 778 { 779 struct creq_query_roce_stats_ext_resp resp = {}; 780 struct creq_query_roce_stats_ext_resp_sb *sb; 781 struct cmdq_query_roce_stats_ext req = {}; 782 struct bnxt_qplib_rcfw_sbuf *sbuf; 783 int rc; 784 785 sbuf = bnxt_qplib_rcfw_alloc_sbuf(rcfw, sizeof(*sb)); 786 if (!sbuf) { 787 dev_err(&rcfw->pdev->dev, 788 "SP: QUERY_ROCE_STATS_EXT alloc sb failed"); 789 return -ENOMEM; 790 } 791 792 bnxt_qplib_rcfw_cmd_prep((struct cmdq_base *)&req, 793 CMDQ_QUERY_ROCE_STATS_EXT_OPCODE_QUERY_ROCE_STATS, 794 sizeof(req)); 795 796 req.resp_size = ALIGN(sizeof(*sb), BNXT_QPLIB_CMDQE_UNITS); 797 req.resp_addr = cpu_to_le64(sbuf->dma_addr); 798 req.function_id = cpu_to_le32(fid); 799 req.flags = cpu_to_le16(CMDQ_QUERY_ROCE_STATS_EXT_FLAGS_FUNCTION_ID); 800 801 rc = bnxt_qplib_rcfw_send_message(rcfw, (void *)&req, 802 (void *)&resp, (void *)sbuf, 0); 803 if (rc) 804 goto bail; 805 806 sb = sbuf->sb; 807 estat->tx_atomic_req = le64_to_cpu(sb->tx_atomic_req_pkts); 808 estat->tx_read_req = le64_to_cpu(sb->tx_read_req_pkts); 809 estat->tx_read_res = le64_to_cpu(sb->tx_read_res_pkts); 810 estat->tx_write_req = le64_to_cpu(sb->tx_write_req_pkts); 811 estat->tx_send_req = le64_to_cpu(sb->tx_send_req_pkts); 812 estat->rx_atomic_req = le64_to_cpu(sb->rx_atomic_req_pkts); 813 estat->rx_read_req = le64_to_cpu(sb->rx_read_req_pkts); 814 estat->rx_read_res = le64_to_cpu(sb->rx_read_res_pkts); 815 estat->rx_write_req = le64_to_cpu(sb->rx_write_req_pkts); 816 estat->rx_send_req = le64_to_cpu(sb->rx_send_req_pkts); 817 estat->rx_roce_good_pkts = le64_to_cpu(sb->rx_roce_good_pkts); 818 estat->rx_roce_good_bytes = le64_to_cpu(sb->rx_roce_good_bytes); 819 estat->rx_out_of_buffer = le64_to_cpu(sb->rx_out_of_buffer_pkts); 820 estat->rx_out_of_sequence = le64_to_cpu(sb->rx_out_of_sequence_pkts); 821 822 bail: 823 bnxt_qplib_rcfw_free_sbuf(rcfw, sbuf); 824 return rc; 825 } 826