1 /* 2 * Broadcom NetXtreme-E RoCE driver. 3 * 4 * Copyright (c) 2016 - 2017, Broadcom. All rights reserved. The term 5 * Broadcom refers to Broadcom Limited and/or its subsidiaries. 6 * 7 * This software is available to you under a choice of one of two 8 * licenses. You may choose to be licensed under the terms of the GNU 9 * General Public License (GPL) Version 2, available from the file 10 * COPYING in the main directory of this source tree, or the 11 * BSD license below: 12 * 13 * Redistribution and use in source and binary forms, with or without 14 * modification, are permitted provided that the following conditions 15 * are met: 16 * 17 * 1. Redistributions of source code must retain the above copyright 18 * notice, this list of conditions and the following disclaimer. 19 * 2. Redistributions in binary form must reproduce the above copyright 20 * notice, this list of conditions and the following disclaimer in 21 * the documentation and/or other materials provided with the 22 * distribution. 23 * 24 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' 25 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, 26 * THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR 27 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS 28 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 29 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 30 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR 31 * BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, 32 * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE 33 * OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN 34 * IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 35 * 36 * Description: Slow Path Operators 37 */ 38 39 #define dev_fmt(fmt) "QPLIB: " fmt 40 41 #include <linux/interrupt.h> 42 #include <linux/spinlock.h> 43 #include <linux/sched.h> 44 #include <linux/pci.h> 45 46 #include "roce_hsi.h" 47 48 #include "qplib_res.h" 49 #include "qplib_rcfw.h" 50 #include "qplib_sp.h" 51 #include "qplib_tlv.h" 52 53 const struct bnxt_qplib_gid bnxt_qplib_gid_zero = {{ 0, 0, 0, 0, 0, 0, 0, 0, 54 0, 0, 0, 0, 0, 0, 0, 0 } }; 55 56 /* Device */ 57 58 static bool bnxt_qplib_is_atomic_cap(struct bnxt_qplib_rcfw *rcfw) 59 { 60 u16 pcie_ctl2 = 0; 61 62 if (!bnxt_qplib_is_chip_gen_p5_p7(rcfw->res->cctx)) 63 return false; 64 65 pcie_capability_read_word(rcfw->pdev, PCI_EXP_DEVCTL2, &pcie_ctl2); 66 return (pcie_ctl2 & PCI_EXP_DEVCTL2_ATOMIC_REQ); 67 } 68 69 static void bnxt_qplib_query_version(struct bnxt_qplib_rcfw *rcfw, 70 char *fw_ver) 71 { 72 struct creq_query_version_resp resp = {}; 73 struct bnxt_qplib_cmdqmsg msg = {}; 74 struct cmdq_query_version req = {}; 75 int rc; 76 77 bnxt_qplib_rcfw_cmd_prep((struct cmdq_base *)&req, 78 CMDQ_BASE_OPCODE_QUERY_VERSION, 79 sizeof(req)); 80 81 bnxt_qplib_fill_cmdqmsg(&msg, &req, &resp, NULL, sizeof(req), sizeof(resp), 0); 82 rc = bnxt_qplib_rcfw_send_message(rcfw, &msg); 83 if (rc) 84 return; 85 fw_ver[0] = resp.fw_maj; 86 fw_ver[1] = resp.fw_minor; 87 fw_ver[2] = resp.fw_bld; 88 fw_ver[3] = resp.fw_rsvd; 89 } 90 91 int bnxt_qplib_get_dev_attr(struct bnxt_qplib_rcfw *rcfw, 92 struct bnxt_qplib_dev_attr *attr) 93 { 94 struct creq_query_func_resp resp = {}; 95 struct bnxt_qplib_cmdqmsg msg = {}; 96 struct creq_query_func_resp_sb *sb; 97 struct bnxt_qplib_rcfw_sbuf sbuf; 98 struct cmdq_query_func req = {}; 99 u8 *tqm_alloc; 100 int i, rc; 101 u32 temp; 102 103 bnxt_qplib_rcfw_cmd_prep((struct cmdq_base *)&req, 104 CMDQ_BASE_OPCODE_QUERY_FUNC, 105 sizeof(req)); 106 107 sbuf.size = ALIGN(sizeof(*sb), BNXT_QPLIB_CMDQE_UNITS); 108 sbuf.sb = dma_alloc_coherent(&rcfw->pdev->dev, sbuf.size, 109 &sbuf.dma_addr, GFP_KERNEL); 110 if (!sbuf.sb) 111 return -ENOMEM; 112 sb = sbuf.sb; 113 req.resp_size = sbuf.size / BNXT_QPLIB_CMDQE_UNITS; 114 bnxt_qplib_fill_cmdqmsg(&msg, &req, &resp, &sbuf, sizeof(req), 115 sizeof(resp), 0); 116 rc = bnxt_qplib_rcfw_send_message(rcfw, &msg); 117 if (rc) 118 goto bail; 119 120 /* Extract the context from the side buffer */ 121 attr->max_qp = le32_to_cpu(sb->max_qp); 122 /* max_qp value reported by FW doesn't include the QP1 */ 123 attr->max_qp += 1; 124 attr->max_qp_rd_atom = 125 sb->max_qp_rd_atom > BNXT_QPLIB_MAX_OUT_RD_ATOM ? 126 BNXT_QPLIB_MAX_OUT_RD_ATOM : sb->max_qp_rd_atom; 127 attr->max_qp_init_rd_atom = 128 sb->max_qp_init_rd_atom > BNXT_QPLIB_MAX_OUT_RD_ATOM ? 129 BNXT_QPLIB_MAX_OUT_RD_ATOM : sb->max_qp_init_rd_atom; 130 attr->max_qp_wqes = le16_to_cpu(sb->max_qp_wr); 131 /* 132 * 128 WQEs needs to be reserved for the HW (8916). Prevent 133 * reporting the max number 134 */ 135 attr->max_qp_wqes -= BNXT_QPLIB_RESERVED_QP_WRS + 1; 136 attr->max_qp_sges = bnxt_qplib_is_chip_gen_p5_p7(rcfw->res->cctx) ? 137 6 : sb->max_sge; 138 attr->max_cq = le32_to_cpu(sb->max_cq); 139 attr->max_cq_wqes = le32_to_cpu(sb->max_cqe); 140 if (!bnxt_qplib_is_chip_gen_p7(rcfw->res->cctx)) 141 attr->max_cq_wqes = min_t(u32, BNXT_QPLIB_MAX_CQ_WQES, attr->max_cq_wqes); 142 attr->max_cq_sges = attr->max_qp_sges; 143 attr->max_mr = le32_to_cpu(sb->max_mr); 144 attr->max_mw = le32_to_cpu(sb->max_mw); 145 146 attr->max_mr_size = le64_to_cpu(sb->max_mr_size); 147 attr->max_pd = 64 * 1024; 148 attr->max_raw_ethy_qp = le32_to_cpu(sb->max_raw_eth_qp); 149 attr->max_ah = le32_to_cpu(sb->max_ah); 150 151 attr->max_srq = le16_to_cpu(sb->max_srq); 152 attr->max_srq_wqes = le32_to_cpu(sb->max_srq_wr) - 1; 153 attr->max_srq_sges = sb->max_srq_sge; 154 attr->max_pkey = 1; 155 attr->max_inline_data = le32_to_cpu(sb->max_inline_data); 156 if (!bnxt_qplib_is_chip_gen_p7(rcfw->res->cctx)) 157 attr->l2_db_size = (sb->l2_db_space_size + 1) * 158 (0x01 << RCFW_DBR_BASE_PAGE_SHIFT); 159 attr->max_sgid = BNXT_QPLIB_NUM_GIDS_SUPPORTED; 160 attr->dev_cap_flags = le16_to_cpu(sb->dev_cap_flags); 161 162 bnxt_qplib_query_version(rcfw, attr->fw_ver); 163 164 for (i = 0; i < MAX_TQM_ALLOC_REQ / 4; i++) { 165 temp = le32_to_cpu(sb->tqm_alloc_reqs[i]); 166 tqm_alloc = (u8 *)&temp; 167 attr->tqm_alloc_reqs[i * 4] = *tqm_alloc; 168 attr->tqm_alloc_reqs[i * 4 + 1] = *(++tqm_alloc); 169 attr->tqm_alloc_reqs[i * 4 + 2] = *(++tqm_alloc); 170 attr->tqm_alloc_reqs[i * 4 + 3] = *(++tqm_alloc); 171 } 172 173 if (rcfw->res->cctx->hwrm_intf_ver >= HWRM_VERSION_DEV_ATTR_MAX_DPI) 174 attr->max_dpi = le32_to_cpu(sb->max_dpi); 175 176 attr->is_atomic = bnxt_qplib_is_atomic_cap(rcfw); 177 bail: 178 dma_free_coherent(&rcfw->pdev->dev, sbuf.size, 179 sbuf.sb, sbuf.dma_addr); 180 return rc; 181 } 182 183 int bnxt_qplib_set_func_resources(struct bnxt_qplib_res *res, 184 struct bnxt_qplib_rcfw *rcfw, 185 struct bnxt_qplib_ctx *ctx) 186 { 187 struct creq_set_func_resources_resp resp = {}; 188 struct cmdq_set_func_resources req = {}; 189 struct bnxt_qplib_cmdqmsg msg = {}; 190 int rc; 191 192 bnxt_qplib_rcfw_cmd_prep((struct cmdq_base *)&req, 193 CMDQ_BASE_OPCODE_SET_FUNC_RESOURCES, 194 sizeof(req)); 195 196 req.number_of_qp = cpu_to_le32(ctx->qpc_count); 197 req.number_of_mrw = cpu_to_le32(ctx->mrw_count); 198 req.number_of_srq = cpu_to_le32(ctx->srqc_count); 199 req.number_of_cq = cpu_to_le32(ctx->cq_count); 200 201 req.max_qp_per_vf = cpu_to_le32(ctx->vf_res.max_qp_per_vf); 202 req.max_mrw_per_vf = cpu_to_le32(ctx->vf_res.max_mrw_per_vf); 203 req.max_srq_per_vf = cpu_to_le32(ctx->vf_res.max_srq_per_vf); 204 req.max_cq_per_vf = cpu_to_le32(ctx->vf_res.max_cq_per_vf); 205 req.max_gid_per_vf = cpu_to_le32(ctx->vf_res.max_gid_per_vf); 206 207 bnxt_qplib_fill_cmdqmsg(&msg, &req, &resp, NULL, sizeof(req), 208 sizeof(resp), 0); 209 rc = bnxt_qplib_rcfw_send_message(rcfw, &msg); 210 if (rc) { 211 dev_err(&res->pdev->dev, "Failed to set function resources\n"); 212 } 213 return rc; 214 } 215 216 /* SGID */ 217 int bnxt_qplib_get_sgid(struct bnxt_qplib_res *res, 218 struct bnxt_qplib_sgid_tbl *sgid_tbl, int index, 219 struct bnxt_qplib_gid *gid) 220 { 221 if (index >= sgid_tbl->max) { 222 dev_err(&res->pdev->dev, 223 "Index %d exceeded SGID table max (%d)\n", 224 index, sgid_tbl->max); 225 return -EINVAL; 226 } 227 memcpy(gid, &sgid_tbl->tbl[index].gid, sizeof(*gid)); 228 return 0; 229 } 230 231 int bnxt_qplib_del_sgid(struct bnxt_qplib_sgid_tbl *sgid_tbl, 232 struct bnxt_qplib_gid *gid, u16 vlan_id, bool update) 233 { 234 struct bnxt_qplib_res *res = to_bnxt_qplib(sgid_tbl, 235 struct bnxt_qplib_res, 236 sgid_tbl); 237 struct bnxt_qplib_rcfw *rcfw = res->rcfw; 238 int index; 239 240 /* Do we need a sgid_lock here? */ 241 if (!sgid_tbl->active) { 242 dev_err(&res->pdev->dev, "SGID table has no active entries\n"); 243 return -ENOMEM; 244 } 245 for (index = 0; index < sgid_tbl->max; index++) { 246 if (!memcmp(&sgid_tbl->tbl[index].gid, gid, sizeof(*gid)) && 247 vlan_id == sgid_tbl->tbl[index].vlan_id) 248 break; 249 } 250 if (index == sgid_tbl->max) { 251 dev_warn(&res->pdev->dev, "GID not found in the SGID table\n"); 252 return 0; 253 } 254 /* Remove GID from the SGID table */ 255 if (update) { 256 struct creq_delete_gid_resp resp = {}; 257 struct bnxt_qplib_cmdqmsg msg = {}; 258 struct cmdq_delete_gid req = {}; 259 int rc; 260 261 bnxt_qplib_rcfw_cmd_prep((struct cmdq_base *)&req, 262 CMDQ_BASE_OPCODE_DELETE_GID, 263 sizeof(req)); 264 if (sgid_tbl->hw_id[index] == 0xFFFF) { 265 dev_err(&res->pdev->dev, 266 "GID entry contains an invalid HW id\n"); 267 return -EINVAL; 268 } 269 req.gid_index = cpu_to_le16(sgid_tbl->hw_id[index]); 270 bnxt_qplib_fill_cmdqmsg(&msg, &req, &resp, NULL, sizeof(req), 271 sizeof(resp), 0); 272 rc = bnxt_qplib_rcfw_send_message(rcfw, &msg); 273 if (rc) 274 return rc; 275 } 276 memcpy(&sgid_tbl->tbl[index].gid, &bnxt_qplib_gid_zero, 277 sizeof(bnxt_qplib_gid_zero)); 278 sgid_tbl->tbl[index].vlan_id = 0xFFFF; 279 sgid_tbl->vlan[index] = 0; 280 sgid_tbl->active--; 281 dev_dbg(&res->pdev->dev, 282 "SGID deleted hw_id[0x%x] = 0x%x active = 0x%x\n", 283 index, sgid_tbl->hw_id[index], sgid_tbl->active); 284 sgid_tbl->hw_id[index] = (u16)-1; 285 286 /* unlock */ 287 return 0; 288 } 289 290 int bnxt_qplib_add_sgid(struct bnxt_qplib_sgid_tbl *sgid_tbl, 291 struct bnxt_qplib_gid *gid, const u8 *smac, 292 u16 vlan_id, bool update, u32 *index) 293 { 294 struct bnxt_qplib_res *res = to_bnxt_qplib(sgid_tbl, 295 struct bnxt_qplib_res, 296 sgid_tbl); 297 struct bnxt_qplib_rcfw *rcfw = res->rcfw; 298 int i, free_idx; 299 300 /* Do we need a sgid_lock here? */ 301 if (sgid_tbl->active == sgid_tbl->max) { 302 dev_err(&res->pdev->dev, "SGID table is full\n"); 303 return -ENOMEM; 304 } 305 free_idx = sgid_tbl->max; 306 for (i = 0; i < sgid_tbl->max; i++) { 307 if (!memcmp(&sgid_tbl->tbl[i], gid, sizeof(*gid)) && 308 sgid_tbl->tbl[i].vlan_id == vlan_id) { 309 dev_dbg(&res->pdev->dev, 310 "SGID entry already exist in entry %d!\n", i); 311 *index = i; 312 return -EALREADY; 313 } else if (!memcmp(&sgid_tbl->tbl[i], &bnxt_qplib_gid_zero, 314 sizeof(bnxt_qplib_gid_zero)) && 315 free_idx == sgid_tbl->max) { 316 free_idx = i; 317 } 318 } 319 if (free_idx == sgid_tbl->max) { 320 dev_err(&res->pdev->dev, 321 "SGID table is FULL but count is not MAX??\n"); 322 return -ENOMEM; 323 } 324 if (update) { 325 struct creq_add_gid_resp resp = {}; 326 struct bnxt_qplib_cmdqmsg msg = {}; 327 struct cmdq_add_gid req = {}; 328 int rc; 329 330 bnxt_qplib_rcfw_cmd_prep((struct cmdq_base *)&req, 331 CMDQ_BASE_OPCODE_ADD_GID, 332 sizeof(req)); 333 334 req.gid[0] = cpu_to_be32(((u32 *)gid->data)[3]); 335 req.gid[1] = cpu_to_be32(((u32 *)gid->data)[2]); 336 req.gid[2] = cpu_to_be32(((u32 *)gid->data)[1]); 337 req.gid[3] = cpu_to_be32(((u32 *)gid->data)[0]); 338 /* 339 * driver should ensure that all RoCE traffic is always VLAN 340 * tagged if RoCE traffic is running on non-zero VLAN ID or 341 * RoCE traffic is running on non-zero Priority. 342 */ 343 if ((vlan_id != 0xFFFF) || res->prio) { 344 if (vlan_id != 0xFFFF) 345 req.vlan = cpu_to_le16 346 (vlan_id & CMDQ_ADD_GID_VLAN_VLAN_ID_MASK); 347 req.vlan |= cpu_to_le16 348 (CMDQ_ADD_GID_VLAN_TPID_TPID_8100 | 349 CMDQ_ADD_GID_VLAN_VLAN_EN); 350 } 351 352 /* MAC in network format */ 353 req.src_mac[0] = cpu_to_be16(((u16 *)smac)[0]); 354 req.src_mac[1] = cpu_to_be16(((u16 *)smac)[1]); 355 req.src_mac[2] = cpu_to_be16(((u16 *)smac)[2]); 356 357 bnxt_qplib_fill_cmdqmsg(&msg, &req, &resp, NULL, sizeof(req), 358 sizeof(resp), 0); 359 rc = bnxt_qplib_rcfw_send_message(rcfw, &msg); 360 if (rc) 361 return rc; 362 sgid_tbl->hw_id[free_idx] = le32_to_cpu(resp.xid); 363 } 364 /* Add GID to the sgid_tbl */ 365 memcpy(&sgid_tbl->tbl[free_idx], gid, sizeof(*gid)); 366 sgid_tbl->tbl[free_idx].vlan_id = vlan_id; 367 sgid_tbl->active++; 368 if (vlan_id != 0xFFFF) 369 sgid_tbl->vlan[free_idx] = 1; 370 371 dev_dbg(&res->pdev->dev, 372 "SGID added hw_id[0x%x] = 0x%x active = 0x%x\n", 373 free_idx, sgid_tbl->hw_id[free_idx], sgid_tbl->active); 374 375 *index = free_idx; 376 /* unlock */ 377 return 0; 378 } 379 380 int bnxt_qplib_update_sgid(struct bnxt_qplib_sgid_tbl *sgid_tbl, 381 struct bnxt_qplib_gid *gid, u16 gid_idx, 382 const u8 *smac) 383 { 384 struct bnxt_qplib_res *res = to_bnxt_qplib(sgid_tbl, 385 struct bnxt_qplib_res, 386 sgid_tbl); 387 struct bnxt_qplib_rcfw *rcfw = res->rcfw; 388 struct creq_modify_gid_resp resp = {}; 389 struct bnxt_qplib_cmdqmsg msg = {}; 390 struct cmdq_modify_gid req = {}; 391 int rc; 392 393 bnxt_qplib_rcfw_cmd_prep((struct cmdq_base *)&req, 394 CMDQ_BASE_OPCODE_MODIFY_GID, 395 sizeof(req)); 396 397 req.gid[0] = cpu_to_be32(((u32 *)gid->data)[3]); 398 req.gid[1] = cpu_to_be32(((u32 *)gid->data)[2]); 399 req.gid[2] = cpu_to_be32(((u32 *)gid->data)[1]); 400 req.gid[3] = cpu_to_be32(((u32 *)gid->data)[0]); 401 if (res->prio) { 402 req.vlan |= cpu_to_le16 403 (CMDQ_ADD_GID_VLAN_TPID_TPID_8100 | 404 CMDQ_ADD_GID_VLAN_VLAN_EN); 405 } 406 407 /* MAC in network format */ 408 req.src_mac[0] = cpu_to_be16(((u16 *)smac)[0]); 409 req.src_mac[1] = cpu_to_be16(((u16 *)smac)[1]); 410 req.src_mac[2] = cpu_to_be16(((u16 *)smac)[2]); 411 412 req.gid_index = cpu_to_le16(gid_idx); 413 414 bnxt_qplib_fill_cmdqmsg(&msg, &req, &resp, NULL, sizeof(req), 415 sizeof(resp), 0); 416 rc = bnxt_qplib_rcfw_send_message(rcfw, &msg); 417 return rc; 418 } 419 420 /* AH */ 421 int bnxt_qplib_create_ah(struct bnxt_qplib_res *res, struct bnxt_qplib_ah *ah, 422 bool block) 423 { 424 struct bnxt_qplib_rcfw *rcfw = res->rcfw; 425 struct creq_create_ah_resp resp = {}; 426 struct bnxt_qplib_cmdqmsg msg = {}; 427 struct cmdq_create_ah req = {}; 428 u32 temp32[4]; 429 u16 temp16[3]; 430 int rc; 431 432 bnxt_qplib_rcfw_cmd_prep((struct cmdq_base *)&req, 433 CMDQ_BASE_OPCODE_CREATE_AH, 434 sizeof(req)); 435 436 memcpy(temp32, ah->dgid.data, sizeof(struct bnxt_qplib_gid)); 437 req.dgid[0] = cpu_to_le32(temp32[0]); 438 req.dgid[1] = cpu_to_le32(temp32[1]); 439 req.dgid[2] = cpu_to_le32(temp32[2]); 440 req.dgid[3] = cpu_to_le32(temp32[3]); 441 442 req.type = ah->nw_type; 443 req.hop_limit = ah->hop_limit; 444 req.sgid_index = cpu_to_le16(res->sgid_tbl.hw_id[ah->sgid_index]); 445 req.dest_vlan_id_flow_label = cpu_to_le32((ah->flow_label & 446 CMDQ_CREATE_AH_FLOW_LABEL_MASK) | 447 CMDQ_CREATE_AH_DEST_VLAN_ID_MASK); 448 req.pd_id = cpu_to_le32(ah->pd->id); 449 req.traffic_class = ah->traffic_class; 450 451 /* MAC in network format */ 452 memcpy(temp16, ah->dmac, 6); 453 req.dest_mac[0] = cpu_to_le16(temp16[0]); 454 req.dest_mac[1] = cpu_to_le16(temp16[1]); 455 req.dest_mac[2] = cpu_to_le16(temp16[2]); 456 457 bnxt_qplib_fill_cmdqmsg(&msg, &req, &resp, NULL, sizeof(req), 458 sizeof(resp), block); 459 rc = bnxt_qplib_rcfw_send_message(rcfw, &msg); 460 if (rc) 461 return rc; 462 463 ah->id = le32_to_cpu(resp.xid); 464 return 0; 465 } 466 467 int bnxt_qplib_destroy_ah(struct bnxt_qplib_res *res, struct bnxt_qplib_ah *ah, 468 bool block) 469 { 470 struct bnxt_qplib_rcfw *rcfw = res->rcfw; 471 struct creq_destroy_ah_resp resp = {}; 472 struct bnxt_qplib_cmdqmsg msg = {}; 473 struct cmdq_destroy_ah req = {}; 474 int rc; 475 476 /* Clean up the AH table in the device */ 477 bnxt_qplib_rcfw_cmd_prep((struct cmdq_base *)&req, 478 CMDQ_BASE_OPCODE_DESTROY_AH, 479 sizeof(req)); 480 481 req.ah_cid = cpu_to_le32(ah->id); 482 483 bnxt_qplib_fill_cmdqmsg(&msg, &req, &resp, NULL, sizeof(req), 484 sizeof(resp), block); 485 rc = bnxt_qplib_rcfw_send_message(rcfw, &msg); 486 return rc; 487 } 488 489 /* MRW */ 490 int bnxt_qplib_free_mrw(struct bnxt_qplib_res *res, struct bnxt_qplib_mrw *mrw) 491 { 492 struct creq_deallocate_key_resp resp = {}; 493 struct bnxt_qplib_rcfw *rcfw = res->rcfw; 494 struct cmdq_deallocate_key req = {}; 495 struct bnxt_qplib_cmdqmsg msg = {}; 496 int rc; 497 498 if (mrw->lkey == 0xFFFFFFFF) { 499 dev_info(&res->pdev->dev, "SP: Free a reserved lkey MRW\n"); 500 return 0; 501 } 502 503 bnxt_qplib_rcfw_cmd_prep((struct cmdq_base *)&req, 504 CMDQ_BASE_OPCODE_DEALLOCATE_KEY, 505 sizeof(req)); 506 507 req.mrw_flags = mrw->type; 508 509 if ((mrw->type == CMDQ_ALLOCATE_MRW_MRW_FLAGS_MW_TYPE1) || 510 (mrw->type == CMDQ_ALLOCATE_MRW_MRW_FLAGS_MW_TYPE2A) || 511 (mrw->type == CMDQ_ALLOCATE_MRW_MRW_FLAGS_MW_TYPE2B)) 512 req.key = cpu_to_le32(mrw->rkey); 513 else 514 req.key = cpu_to_le32(mrw->lkey); 515 516 bnxt_qplib_fill_cmdqmsg(&msg, &req, &resp, NULL, sizeof(req), 517 sizeof(resp), 0); 518 rc = bnxt_qplib_rcfw_send_message(rcfw, &msg); 519 if (rc) 520 return rc; 521 522 /* Free the qplib's MRW memory */ 523 if (mrw->hwq.max_elements) 524 bnxt_qplib_free_hwq(res, &mrw->hwq); 525 526 return 0; 527 } 528 529 int bnxt_qplib_alloc_mrw(struct bnxt_qplib_res *res, struct bnxt_qplib_mrw *mrw) 530 { 531 struct bnxt_qplib_rcfw *rcfw = res->rcfw; 532 struct creq_allocate_mrw_resp resp = {}; 533 struct bnxt_qplib_cmdqmsg msg = {}; 534 struct cmdq_allocate_mrw req = {}; 535 unsigned long tmp; 536 int rc; 537 538 bnxt_qplib_rcfw_cmd_prep((struct cmdq_base *)&req, 539 CMDQ_BASE_OPCODE_ALLOCATE_MRW, 540 sizeof(req)); 541 542 req.pd_id = cpu_to_le32(mrw->pd->id); 543 req.mrw_flags = mrw->type; 544 if ((mrw->type == CMDQ_ALLOCATE_MRW_MRW_FLAGS_PMR && 545 mrw->flags & BNXT_QPLIB_FR_PMR) || 546 mrw->type == CMDQ_ALLOCATE_MRW_MRW_FLAGS_MW_TYPE2A || 547 mrw->type == CMDQ_ALLOCATE_MRW_MRW_FLAGS_MW_TYPE2B) 548 req.access = CMDQ_ALLOCATE_MRW_ACCESS_CONSUMER_OWNED_KEY; 549 tmp = (unsigned long)mrw; 550 req.mrw_handle = cpu_to_le64(tmp); 551 552 bnxt_qplib_fill_cmdqmsg(&msg, &req, &resp, NULL, sizeof(req), 553 sizeof(resp), 0); 554 rc = bnxt_qplib_rcfw_send_message(rcfw, &msg); 555 if (rc) 556 return rc; 557 558 if ((mrw->type == CMDQ_ALLOCATE_MRW_MRW_FLAGS_MW_TYPE1) || 559 (mrw->type == CMDQ_ALLOCATE_MRW_MRW_FLAGS_MW_TYPE2A) || 560 (mrw->type == CMDQ_ALLOCATE_MRW_MRW_FLAGS_MW_TYPE2B)) 561 mrw->rkey = le32_to_cpu(resp.xid); 562 else 563 mrw->lkey = le32_to_cpu(resp.xid); 564 return 0; 565 } 566 567 int bnxt_qplib_dereg_mrw(struct bnxt_qplib_res *res, struct bnxt_qplib_mrw *mrw, 568 bool block) 569 { 570 struct bnxt_qplib_rcfw *rcfw = res->rcfw; 571 struct creq_deregister_mr_resp resp = {}; 572 struct bnxt_qplib_cmdqmsg msg = {}; 573 struct cmdq_deregister_mr req = {}; 574 int rc; 575 576 bnxt_qplib_rcfw_cmd_prep((struct cmdq_base *)&req, 577 CMDQ_BASE_OPCODE_DEREGISTER_MR, 578 sizeof(req)); 579 580 req.lkey = cpu_to_le32(mrw->lkey); 581 bnxt_qplib_fill_cmdqmsg(&msg, &req, &resp, NULL, sizeof(req), 582 sizeof(resp), block); 583 rc = bnxt_qplib_rcfw_send_message(rcfw, &msg); 584 if (rc) 585 return rc; 586 587 /* Free the qplib's MR memory */ 588 if (mrw->hwq.max_elements) { 589 mrw->va = 0; 590 mrw->total_size = 0; 591 bnxt_qplib_free_hwq(res, &mrw->hwq); 592 } 593 594 return 0; 595 } 596 597 int bnxt_qplib_reg_mr(struct bnxt_qplib_res *res, struct bnxt_qplib_mrw *mr, 598 struct ib_umem *umem, int num_pbls, u32 buf_pg_size) 599 { 600 struct bnxt_qplib_rcfw *rcfw = res->rcfw; 601 struct bnxt_qplib_hwq_attr hwq_attr = {}; 602 struct bnxt_qplib_sg_info sginfo = {}; 603 struct creq_register_mr_resp resp = {}; 604 struct bnxt_qplib_cmdqmsg msg = {}; 605 struct cmdq_register_mr req = {}; 606 int pages, rc; 607 u32 pg_size; 608 u16 level; 609 610 if (num_pbls) { 611 pages = roundup_pow_of_two(num_pbls); 612 /* Allocate memory for the non-leaf pages to store buf ptrs. 613 * Non-leaf pages always uses system PAGE_SIZE 614 */ 615 /* Free the hwq if it already exist, must be a rereg */ 616 if (mr->hwq.max_elements) 617 bnxt_qplib_free_hwq(res, &mr->hwq); 618 hwq_attr.res = res; 619 hwq_attr.depth = pages; 620 hwq_attr.stride = sizeof(dma_addr_t); 621 hwq_attr.type = HWQ_TYPE_MR; 622 hwq_attr.sginfo = &sginfo; 623 hwq_attr.sginfo->umem = umem; 624 hwq_attr.sginfo->npages = pages; 625 hwq_attr.sginfo->pgsize = buf_pg_size; 626 hwq_attr.sginfo->pgshft = ilog2(buf_pg_size); 627 rc = bnxt_qplib_alloc_init_hwq(&mr->hwq, &hwq_attr); 628 if (rc) { 629 dev_err(&res->pdev->dev, 630 "SP: Reg MR memory allocation failed\n"); 631 return -ENOMEM; 632 } 633 } 634 635 bnxt_qplib_rcfw_cmd_prep((struct cmdq_base *)&req, 636 CMDQ_BASE_OPCODE_REGISTER_MR, 637 sizeof(req)); 638 639 /* Configure the request */ 640 if (mr->hwq.level == PBL_LVL_MAX) { 641 /* No PBL provided, just use system PAGE_SIZE */ 642 level = 0; 643 req.pbl = 0; 644 pg_size = PAGE_SIZE; 645 } else { 646 level = mr->hwq.level; 647 req.pbl = cpu_to_le64(mr->hwq.pbl[PBL_LVL_0].pg_map_arr[0]); 648 } 649 pg_size = buf_pg_size ? buf_pg_size : PAGE_SIZE; 650 req.log2_pg_size_lvl = (level << CMDQ_REGISTER_MR_LVL_SFT) | 651 ((ilog2(pg_size) << 652 CMDQ_REGISTER_MR_LOG2_PG_SIZE_SFT) & 653 CMDQ_REGISTER_MR_LOG2_PG_SIZE_MASK); 654 req.log2_pbl_pg_size = cpu_to_le16(((ilog2(PAGE_SIZE) << 655 CMDQ_REGISTER_MR_LOG2_PBL_PG_SIZE_SFT) & 656 CMDQ_REGISTER_MR_LOG2_PBL_PG_SIZE_MASK)); 657 req.access = (mr->flags & 0xFFFF); 658 req.va = cpu_to_le64(mr->va); 659 req.key = cpu_to_le32(mr->lkey); 660 req.mr_size = cpu_to_le64(mr->total_size); 661 662 bnxt_qplib_fill_cmdqmsg(&msg, &req, &resp, NULL, sizeof(req), 663 sizeof(resp), 0); 664 rc = bnxt_qplib_rcfw_send_message(rcfw, &msg); 665 if (rc) 666 goto fail; 667 668 return 0; 669 670 fail: 671 if (mr->hwq.max_elements) 672 bnxt_qplib_free_hwq(res, &mr->hwq); 673 return rc; 674 } 675 676 int bnxt_qplib_alloc_fast_reg_page_list(struct bnxt_qplib_res *res, 677 struct bnxt_qplib_frpl *frpl, 678 int max_pg_ptrs) 679 { 680 struct bnxt_qplib_hwq_attr hwq_attr = {}; 681 struct bnxt_qplib_sg_info sginfo = {}; 682 int pg_ptrs, pages, rc; 683 684 /* Re-calculate the max to fit the HWQ allocation model */ 685 pg_ptrs = roundup_pow_of_two(max_pg_ptrs); 686 pages = pg_ptrs >> MAX_PBL_LVL_1_PGS_SHIFT; 687 if (!pages) 688 pages++; 689 690 if (pages > MAX_PBL_LVL_1_PGS) 691 return -ENOMEM; 692 693 sginfo.pgsize = PAGE_SIZE; 694 sginfo.nopte = true; 695 696 hwq_attr.res = res; 697 hwq_attr.depth = pg_ptrs; 698 hwq_attr.stride = PAGE_SIZE; 699 hwq_attr.sginfo = &sginfo; 700 hwq_attr.type = HWQ_TYPE_CTX; 701 rc = bnxt_qplib_alloc_init_hwq(&frpl->hwq, &hwq_attr); 702 if (!rc) 703 frpl->max_pg_ptrs = pg_ptrs; 704 705 return rc; 706 } 707 708 int bnxt_qplib_free_fast_reg_page_list(struct bnxt_qplib_res *res, 709 struct bnxt_qplib_frpl *frpl) 710 { 711 bnxt_qplib_free_hwq(res, &frpl->hwq); 712 return 0; 713 } 714 715 int bnxt_qplib_get_roce_stats(struct bnxt_qplib_rcfw *rcfw, 716 struct bnxt_qplib_roce_stats *stats) 717 { 718 struct creq_query_roce_stats_resp resp = {}; 719 struct creq_query_roce_stats_resp_sb *sb; 720 struct cmdq_query_roce_stats req = {}; 721 struct bnxt_qplib_cmdqmsg msg = {}; 722 struct bnxt_qplib_rcfw_sbuf sbuf; 723 int rc; 724 725 bnxt_qplib_rcfw_cmd_prep((struct cmdq_base *)&req, 726 CMDQ_BASE_OPCODE_QUERY_ROCE_STATS, 727 sizeof(req)); 728 729 sbuf.size = ALIGN(sizeof(*sb), BNXT_QPLIB_CMDQE_UNITS); 730 sbuf.sb = dma_alloc_coherent(&rcfw->pdev->dev, sbuf.size, 731 &sbuf.dma_addr, GFP_KERNEL); 732 if (!sbuf.sb) 733 return -ENOMEM; 734 sb = sbuf.sb; 735 736 req.resp_size = sbuf.size / BNXT_QPLIB_CMDQE_UNITS; 737 bnxt_qplib_fill_cmdqmsg(&msg, &req, &resp, &sbuf, sizeof(req), 738 sizeof(resp), 0); 739 rc = bnxt_qplib_rcfw_send_message(rcfw, &msg); 740 if (rc) 741 goto bail; 742 /* Extract the context from the side buffer */ 743 stats->to_retransmits = le64_to_cpu(sb->to_retransmits); 744 stats->seq_err_naks_rcvd = le64_to_cpu(sb->seq_err_naks_rcvd); 745 stats->max_retry_exceeded = le64_to_cpu(sb->max_retry_exceeded); 746 stats->rnr_naks_rcvd = le64_to_cpu(sb->rnr_naks_rcvd); 747 stats->missing_resp = le64_to_cpu(sb->missing_resp); 748 stats->unrecoverable_err = le64_to_cpu(sb->unrecoverable_err); 749 stats->bad_resp_err = le64_to_cpu(sb->bad_resp_err); 750 stats->local_qp_op_err = le64_to_cpu(sb->local_qp_op_err); 751 stats->local_protection_err = le64_to_cpu(sb->local_protection_err); 752 stats->mem_mgmt_op_err = le64_to_cpu(sb->mem_mgmt_op_err); 753 stats->remote_invalid_req_err = le64_to_cpu(sb->remote_invalid_req_err); 754 stats->remote_access_err = le64_to_cpu(sb->remote_access_err); 755 stats->remote_op_err = le64_to_cpu(sb->remote_op_err); 756 stats->dup_req = le64_to_cpu(sb->dup_req); 757 stats->res_exceed_max = le64_to_cpu(sb->res_exceed_max); 758 stats->res_length_mismatch = le64_to_cpu(sb->res_length_mismatch); 759 stats->res_exceeds_wqe = le64_to_cpu(sb->res_exceeds_wqe); 760 stats->res_opcode_err = le64_to_cpu(sb->res_opcode_err); 761 stats->res_rx_invalid_rkey = le64_to_cpu(sb->res_rx_invalid_rkey); 762 stats->res_rx_domain_err = le64_to_cpu(sb->res_rx_domain_err); 763 stats->res_rx_no_perm = le64_to_cpu(sb->res_rx_no_perm); 764 stats->res_rx_range_err = le64_to_cpu(sb->res_rx_range_err); 765 stats->res_tx_invalid_rkey = le64_to_cpu(sb->res_tx_invalid_rkey); 766 stats->res_tx_domain_err = le64_to_cpu(sb->res_tx_domain_err); 767 stats->res_tx_no_perm = le64_to_cpu(sb->res_tx_no_perm); 768 stats->res_tx_range_err = le64_to_cpu(sb->res_tx_range_err); 769 stats->res_irrq_oflow = le64_to_cpu(sb->res_irrq_oflow); 770 stats->res_unsup_opcode = le64_to_cpu(sb->res_unsup_opcode); 771 stats->res_unaligned_atomic = le64_to_cpu(sb->res_unaligned_atomic); 772 stats->res_rem_inv_err = le64_to_cpu(sb->res_rem_inv_err); 773 stats->res_mem_error = le64_to_cpu(sb->res_mem_error); 774 stats->res_srq_err = le64_to_cpu(sb->res_srq_err); 775 stats->res_cmp_err = le64_to_cpu(sb->res_cmp_err); 776 stats->res_invalid_dup_rkey = le64_to_cpu(sb->res_invalid_dup_rkey); 777 stats->res_wqe_format_err = le64_to_cpu(sb->res_wqe_format_err); 778 stats->res_cq_load_err = le64_to_cpu(sb->res_cq_load_err); 779 stats->res_srq_load_err = le64_to_cpu(sb->res_srq_load_err); 780 stats->res_tx_pci_err = le64_to_cpu(sb->res_tx_pci_err); 781 stats->res_rx_pci_err = le64_to_cpu(sb->res_rx_pci_err); 782 if (!rcfw->init_oos_stats) { 783 rcfw->oos_prev = le64_to_cpu(sb->res_oos_drop_count); 784 rcfw->init_oos_stats = 1; 785 } else { 786 stats->res_oos_drop_count += 787 (le64_to_cpu(sb->res_oos_drop_count) - 788 rcfw->oos_prev) & BNXT_QPLIB_OOS_COUNT_MASK; 789 rcfw->oos_prev = le64_to_cpu(sb->res_oos_drop_count); 790 } 791 792 bail: 793 dma_free_coherent(&rcfw->pdev->dev, sbuf.size, 794 sbuf.sb, sbuf.dma_addr); 795 return rc; 796 } 797 798 int bnxt_qplib_qext_stat(struct bnxt_qplib_rcfw *rcfw, u32 fid, 799 struct bnxt_qplib_ext_stat *estat) 800 { 801 struct creq_query_roce_stats_ext_resp resp = {}; 802 struct creq_query_roce_stats_ext_resp_sb *sb; 803 struct cmdq_query_roce_stats_ext req = {}; 804 struct bnxt_qplib_cmdqmsg msg = {}; 805 struct bnxt_qplib_rcfw_sbuf sbuf; 806 int rc; 807 808 sbuf.size = ALIGN(sizeof(*sb), BNXT_QPLIB_CMDQE_UNITS); 809 sbuf.sb = dma_alloc_coherent(&rcfw->pdev->dev, sbuf.size, 810 &sbuf.dma_addr, GFP_KERNEL); 811 if (!sbuf.sb) 812 return -ENOMEM; 813 814 sb = sbuf.sb; 815 bnxt_qplib_rcfw_cmd_prep((struct cmdq_base *)&req, 816 CMDQ_QUERY_ROCE_STATS_EXT_OPCODE_QUERY_ROCE_STATS, 817 sizeof(req)); 818 819 req.resp_size = sbuf.size / BNXT_QPLIB_CMDQE_UNITS; 820 req.resp_addr = cpu_to_le64(sbuf.dma_addr); 821 req.function_id = cpu_to_le32(fid); 822 req.flags = cpu_to_le16(CMDQ_QUERY_ROCE_STATS_EXT_FLAGS_FUNCTION_ID); 823 824 bnxt_qplib_fill_cmdqmsg(&msg, &req, &resp, &sbuf, sizeof(req), 825 sizeof(resp), 0); 826 rc = bnxt_qplib_rcfw_send_message(rcfw, &msg); 827 if (rc) 828 goto bail; 829 830 estat->tx_atomic_req = le64_to_cpu(sb->tx_atomic_req_pkts); 831 estat->tx_read_req = le64_to_cpu(sb->tx_read_req_pkts); 832 estat->tx_read_res = le64_to_cpu(sb->tx_read_res_pkts); 833 estat->tx_write_req = le64_to_cpu(sb->tx_write_req_pkts); 834 estat->tx_send_req = le64_to_cpu(sb->tx_send_req_pkts); 835 estat->tx_roce_pkts = le64_to_cpu(sb->tx_roce_pkts); 836 estat->tx_roce_bytes = le64_to_cpu(sb->tx_roce_bytes); 837 estat->rx_atomic_req = le64_to_cpu(sb->rx_atomic_req_pkts); 838 estat->rx_read_req = le64_to_cpu(sb->rx_read_req_pkts); 839 estat->rx_read_res = le64_to_cpu(sb->rx_read_res_pkts); 840 estat->rx_write_req = le64_to_cpu(sb->rx_write_req_pkts); 841 estat->rx_send_req = le64_to_cpu(sb->rx_send_req_pkts); 842 estat->rx_roce_pkts = le64_to_cpu(sb->rx_roce_pkts); 843 estat->rx_roce_bytes = le64_to_cpu(sb->rx_roce_bytes); 844 estat->rx_roce_good_pkts = le64_to_cpu(sb->rx_roce_good_pkts); 845 estat->rx_roce_good_bytes = le64_to_cpu(sb->rx_roce_good_bytes); 846 estat->rx_out_of_buffer = le64_to_cpu(sb->rx_out_of_buffer_pkts); 847 estat->rx_out_of_sequence = le64_to_cpu(sb->rx_out_of_sequence_pkts); 848 estat->tx_cnp = le64_to_cpu(sb->tx_cnp_pkts); 849 estat->rx_cnp = le64_to_cpu(sb->rx_cnp_pkts); 850 estat->rx_ecn_marked = le64_to_cpu(sb->rx_ecn_marked_pkts); 851 852 bail: 853 dma_free_coherent(&rcfw->pdev->dev, sbuf.size, 854 sbuf.sb, sbuf.dma_addr); 855 return rc; 856 } 857 858 static void bnxt_qplib_fill_cc_gen1(struct cmdq_modify_roce_cc_gen1_tlv *ext_req, 859 struct bnxt_qplib_cc_param_ext *cc_ext) 860 { 861 ext_req->modify_mask = cpu_to_le64(cc_ext->ext_mask); 862 cc_ext->ext_mask = 0; 863 ext_req->inactivity_th_hi = cpu_to_le16(cc_ext->inact_th_hi); 864 ext_req->min_time_between_cnps = cpu_to_le16(cc_ext->min_delta_cnp); 865 ext_req->init_cp = cpu_to_le16(cc_ext->init_cp); 866 ext_req->tr_update_mode = cc_ext->tr_update_mode; 867 ext_req->tr_update_cycles = cc_ext->tr_update_cyls; 868 ext_req->fr_num_rtts = cc_ext->fr_rtt; 869 ext_req->ai_rate_increase = cc_ext->ai_rate_incr; 870 ext_req->reduction_relax_rtts_th = cpu_to_le16(cc_ext->rr_rtt_th); 871 ext_req->additional_relax_cr_th = cpu_to_le16(cc_ext->ar_cr_th); 872 ext_req->cr_min_th = cpu_to_le16(cc_ext->cr_min_th); 873 ext_req->bw_avg_weight = cc_ext->bw_avg_weight; 874 ext_req->actual_cr_factor = cc_ext->cr_factor; 875 ext_req->max_cp_cr_th = cpu_to_le16(cc_ext->cr_th_max_cp); 876 ext_req->cp_bias_en = cc_ext->cp_bias_en; 877 ext_req->cp_bias = cc_ext->cp_bias; 878 ext_req->cnp_ecn = cc_ext->cnp_ecn; 879 ext_req->rtt_jitter_en = cc_ext->rtt_jitter_en; 880 ext_req->link_bytes_per_usec = cpu_to_le16(cc_ext->bytes_per_usec); 881 ext_req->reset_cc_cr_th = cpu_to_le16(cc_ext->cc_cr_reset_th); 882 ext_req->cr_width = cc_ext->cr_width; 883 ext_req->quota_period_min = cc_ext->min_quota; 884 ext_req->quota_period_max = cc_ext->max_quota; 885 ext_req->quota_period_abs_max = cc_ext->abs_max_quota; 886 ext_req->tr_lower_bound = cpu_to_le16(cc_ext->tr_lb); 887 ext_req->cr_prob_factor = cc_ext->cr_prob_fac; 888 ext_req->tr_prob_factor = cc_ext->tr_prob_fac; 889 ext_req->fairness_cr_th = cpu_to_le16(cc_ext->fair_cr_th); 890 ext_req->red_div = cc_ext->red_div; 891 ext_req->cnp_ratio_th = cc_ext->cnp_ratio_th; 892 ext_req->exp_ai_rtts = cpu_to_le16(cc_ext->ai_ext_rtt); 893 ext_req->exp_ai_cr_cp_ratio = cc_ext->exp_crcp_ratio; 894 ext_req->use_rate_table = cc_ext->low_rate_en; 895 ext_req->cp_exp_update_th = cpu_to_le16(cc_ext->cpcr_update_th); 896 ext_req->high_exp_ai_rtts_th1 = cpu_to_le16(cc_ext->ai_rtt_th1); 897 ext_req->high_exp_ai_rtts_th2 = cpu_to_le16(cc_ext->ai_rtt_th2); 898 ext_req->actual_cr_cong_free_rtts_th = cpu_to_le16(cc_ext->cf_rtt_th); 899 ext_req->severe_cong_cr_th1 = cpu_to_le16(cc_ext->sc_cr_th1); 900 ext_req->severe_cong_cr_th2 = cpu_to_le16(cc_ext->sc_cr_th2); 901 ext_req->link64B_per_rtt = cpu_to_le32(cc_ext->l64B_per_rtt); 902 ext_req->cc_ack_bytes = cc_ext->cc_ack_bytes; 903 } 904 905 int bnxt_qplib_modify_cc(struct bnxt_qplib_res *res, 906 struct bnxt_qplib_cc_param *cc_param) 907 { 908 struct bnxt_qplib_tlv_modify_cc_req tlv_req = {}; 909 struct creq_modify_roce_cc_resp resp = {}; 910 struct bnxt_qplib_cmdqmsg msg = {}; 911 struct cmdq_modify_roce_cc *req; 912 int req_size; 913 void *cmd; 914 int rc; 915 916 /* Prepare the older base command */ 917 req = &tlv_req.base_req; 918 cmd = req; 919 req_size = sizeof(*req); 920 bnxt_qplib_rcfw_cmd_prep((struct cmdq_base *)req, CMDQ_BASE_OPCODE_MODIFY_ROCE_CC, 921 sizeof(*req)); 922 req->modify_mask = cpu_to_le32(cc_param->mask); 923 req->enable_cc = cc_param->enable; 924 req->g = cc_param->g; 925 req->num_phases_per_state = cc_param->nph_per_state; 926 req->time_per_phase = cc_param->time_pph; 927 req->pkts_per_phase = cc_param->pkts_pph; 928 req->init_cr = cpu_to_le16(cc_param->init_cr); 929 req->init_tr = cpu_to_le16(cc_param->init_tr); 930 req->tos_dscp_tos_ecn = (cc_param->tos_dscp << CMDQ_MODIFY_ROCE_CC_TOS_DSCP_SFT) | 931 (cc_param->tos_ecn & CMDQ_MODIFY_ROCE_CC_TOS_ECN_MASK); 932 req->alt_vlan_pcp = cc_param->alt_vlan_pcp; 933 req->alt_tos_dscp = cpu_to_le16(cc_param->alt_tos_dscp); 934 req->rtt = cpu_to_le16(cc_param->rtt); 935 req->tcp_cp = cpu_to_le16(cc_param->tcp_cp); 936 req->cc_mode = cc_param->cc_mode; 937 req->inactivity_th = cpu_to_le16(cc_param->inact_th); 938 939 /* For chip gen P5 onwards fill extended cmd and header */ 940 if (bnxt_qplib_is_chip_gen_p5_p7(res->cctx)) { 941 struct roce_tlv *hdr; 942 u32 payload; 943 u32 chunks; 944 945 cmd = &tlv_req; 946 req_size = sizeof(tlv_req); 947 /* Prepare primary tlv header */ 948 hdr = &tlv_req.tlv_hdr; 949 chunks = CHUNKS(sizeof(struct bnxt_qplib_tlv_modify_cc_req)); 950 payload = sizeof(struct cmdq_modify_roce_cc); 951 __roce_1st_tlv_prep(hdr, chunks, payload, true); 952 /* Prepare secondary tlv header */ 953 hdr = (struct roce_tlv *)&tlv_req.ext_req; 954 payload = sizeof(struct cmdq_modify_roce_cc_gen1_tlv) - 955 sizeof(struct roce_tlv); 956 __roce_ext_tlv_prep(hdr, TLV_TYPE_MODIFY_ROCE_CC_GEN1, payload, false, true); 957 bnxt_qplib_fill_cc_gen1(&tlv_req.ext_req, &cc_param->cc_ext); 958 } 959 960 bnxt_qplib_fill_cmdqmsg(&msg, cmd, &resp, NULL, req_size, 961 sizeof(resp), 0); 962 rc = bnxt_qplib_rcfw_send_message(res->rcfw, &msg); 963 return rc; 964 } 965