1 /* 2 * Broadcom NetXtreme-E RoCE driver. 3 * 4 * Copyright (c) 2016 - 2017, Broadcom. All rights reserved. The term 5 * Broadcom refers to Broadcom Limited and/or its subsidiaries. 6 * 7 * This software is available to you under a choice of one of two 8 * licenses. You may choose to be licensed under the terms of the GNU 9 * General Public License (GPL) Version 2, available from the file 10 * COPYING in the main directory of this source tree, or the 11 * BSD license below: 12 * 13 * Redistribution and use in source and binary forms, with or without 14 * modification, are permitted provided that the following conditions 15 * are met: 16 * 17 * 1. Redistributions of source code must retain the above copyright 18 * notice, this list of conditions and the following disclaimer. 19 * 2. Redistributions in binary form must reproduce the above copyright 20 * notice, this list of conditions and the following disclaimer in 21 * the documentation and/or other materials provided with the 22 * distribution. 23 * 24 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' 25 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, 26 * THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR 27 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS 28 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 29 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 30 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR 31 * BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, 32 * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE 33 * OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN 34 * IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 35 * 36 * Description: Slow Path Operators 37 */ 38 39 #define dev_fmt(fmt) "QPLIB: " fmt 40 41 #include <linux/interrupt.h> 42 #include <linux/spinlock.h> 43 #include <linux/sched.h> 44 #include <linux/pci.h> 45 46 #include "roce_hsi.h" 47 48 #include "qplib_res.h" 49 #include "qplib_rcfw.h" 50 #include "qplib_sp.h" 51 #include "qplib_tlv.h" 52 53 const struct bnxt_qplib_gid bnxt_qplib_gid_zero = {{ 0, 0, 0, 0, 0, 0, 0, 0, 54 0, 0, 0, 0, 0, 0, 0, 0 } }; 55 56 /* Device */ 57 58 static bool bnxt_qplib_is_atomic_cap(struct bnxt_qplib_rcfw *rcfw) 59 { 60 u16 pcie_ctl2 = 0; 61 62 if (!bnxt_qplib_is_chip_gen_p5(rcfw->res->cctx)) 63 return false; 64 65 pcie_capability_read_word(rcfw->pdev, PCI_EXP_DEVCTL2, &pcie_ctl2); 66 return (pcie_ctl2 & PCI_EXP_DEVCTL2_ATOMIC_REQ); 67 } 68 69 static void bnxt_qplib_query_version(struct bnxt_qplib_rcfw *rcfw, 70 char *fw_ver) 71 { 72 struct creq_query_version_resp resp = {}; 73 struct bnxt_qplib_cmdqmsg msg = {}; 74 struct cmdq_query_version req = {}; 75 int rc = 0; 76 77 bnxt_qplib_rcfw_cmd_prep((struct cmdq_base *)&req, 78 CMDQ_BASE_OPCODE_QUERY_VERSION, 79 sizeof(req)); 80 81 bnxt_qplib_fill_cmdqmsg(&msg, &req, &resp, NULL, sizeof(req), sizeof(resp), 0); 82 rc = bnxt_qplib_rcfw_send_message(rcfw, &msg); 83 if (rc) 84 return; 85 fw_ver[0] = resp.fw_maj; 86 fw_ver[1] = resp.fw_minor; 87 fw_ver[2] = resp.fw_bld; 88 fw_ver[3] = resp.fw_rsvd; 89 } 90 91 int bnxt_qplib_get_dev_attr(struct bnxt_qplib_rcfw *rcfw, 92 struct bnxt_qplib_dev_attr *attr, bool vf) 93 { 94 struct creq_query_func_resp resp = {}; 95 struct bnxt_qplib_cmdqmsg msg = {}; 96 struct creq_query_func_resp_sb *sb; 97 struct bnxt_qplib_rcfw_sbuf *sbuf; 98 struct cmdq_query_func req = {}; 99 u8 *tqm_alloc; 100 int i, rc = 0; 101 u32 temp; 102 103 bnxt_qplib_rcfw_cmd_prep((struct cmdq_base *)&req, 104 CMDQ_BASE_OPCODE_QUERY_FUNC, 105 sizeof(req)); 106 107 sbuf = bnxt_qplib_rcfw_alloc_sbuf(rcfw, sizeof(*sb)); 108 if (!sbuf) { 109 dev_err(&rcfw->pdev->dev, 110 "SP: QUERY_FUNC alloc side buffer failed\n"); 111 return -ENOMEM; 112 } 113 114 sb = sbuf->sb; 115 req.resp_size = sizeof(*sb) / BNXT_QPLIB_CMDQE_UNITS; 116 bnxt_qplib_fill_cmdqmsg(&msg, &req, &resp, sbuf, sizeof(req), 117 sizeof(resp), 0); 118 rc = bnxt_qplib_rcfw_send_message(rcfw, &msg); 119 if (rc) 120 goto bail; 121 122 /* Extract the context from the side buffer */ 123 attr->max_qp = le32_to_cpu(sb->max_qp); 124 /* max_qp value reported by FW for PF doesn't include the QP1 for PF */ 125 if (!vf) 126 attr->max_qp += 1; 127 attr->max_qp_rd_atom = 128 sb->max_qp_rd_atom > BNXT_QPLIB_MAX_OUT_RD_ATOM ? 129 BNXT_QPLIB_MAX_OUT_RD_ATOM : sb->max_qp_rd_atom; 130 attr->max_qp_init_rd_atom = 131 sb->max_qp_init_rd_atom > BNXT_QPLIB_MAX_OUT_RD_ATOM ? 132 BNXT_QPLIB_MAX_OUT_RD_ATOM : sb->max_qp_init_rd_atom; 133 attr->max_qp_wqes = le16_to_cpu(sb->max_qp_wr); 134 /* 135 * 128 WQEs needs to be reserved for the HW (8916). Prevent 136 * reporting the max number 137 */ 138 attr->max_qp_wqes -= BNXT_QPLIB_RESERVED_QP_WRS + 1; 139 attr->max_qp_sges = bnxt_qplib_is_chip_gen_p5(rcfw->res->cctx) ? 140 6 : sb->max_sge; 141 attr->max_cq = le32_to_cpu(sb->max_cq); 142 attr->max_cq_wqes = le32_to_cpu(sb->max_cqe); 143 attr->max_cq_sges = attr->max_qp_sges; 144 attr->max_mr = le32_to_cpu(sb->max_mr); 145 attr->max_mw = le32_to_cpu(sb->max_mw); 146 147 attr->max_mr_size = le64_to_cpu(sb->max_mr_size); 148 attr->max_pd = 64 * 1024; 149 attr->max_raw_ethy_qp = le32_to_cpu(sb->max_raw_eth_qp); 150 attr->max_ah = le32_to_cpu(sb->max_ah); 151 152 attr->max_srq = le16_to_cpu(sb->max_srq); 153 attr->max_srq_wqes = le32_to_cpu(sb->max_srq_wr) - 1; 154 attr->max_srq_sges = sb->max_srq_sge; 155 attr->max_pkey = 1; 156 attr->max_inline_data = le32_to_cpu(sb->max_inline_data); 157 attr->l2_db_size = (sb->l2_db_space_size + 1) * 158 (0x01 << RCFW_DBR_BASE_PAGE_SHIFT); 159 attr->max_sgid = BNXT_QPLIB_NUM_GIDS_SUPPORTED; 160 attr->dev_cap_flags = le16_to_cpu(sb->dev_cap_flags); 161 162 bnxt_qplib_query_version(rcfw, attr->fw_ver); 163 164 for (i = 0; i < MAX_TQM_ALLOC_REQ / 4; i++) { 165 temp = le32_to_cpu(sb->tqm_alloc_reqs[i]); 166 tqm_alloc = (u8 *)&temp; 167 attr->tqm_alloc_reqs[i * 4] = *tqm_alloc; 168 attr->tqm_alloc_reqs[i * 4 + 1] = *(++tqm_alloc); 169 attr->tqm_alloc_reqs[i * 4 + 2] = *(++tqm_alloc); 170 attr->tqm_alloc_reqs[i * 4 + 3] = *(++tqm_alloc); 171 } 172 173 attr->is_atomic = bnxt_qplib_is_atomic_cap(rcfw); 174 bail: 175 bnxt_qplib_rcfw_free_sbuf(rcfw, sbuf); 176 return rc; 177 } 178 179 int bnxt_qplib_set_func_resources(struct bnxt_qplib_res *res, 180 struct bnxt_qplib_rcfw *rcfw, 181 struct bnxt_qplib_ctx *ctx) 182 { 183 struct creq_set_func_resources_resp resp = {}; 184 struct cmdq_set_func_resources req = {}; 185 struct bnxt_qplib_cmdqmsg msg = {}; 186 int rc = 0; 187 188 bnxt_qplib_rcfw_cmd_prep((struct cmdq_base *)&req, 189 CMDQ_BASE_OPCODE_SET_FUNC_RESOURCES, 190 sizeof(req)); 191 192 req.number_of_qp = cpu_to_le32(ctx->qpc_count); 193 req.number_of_mrw = cpu_to_le32(ctx->mrw_count); 194 req.number_of_srq = cpu_to_le32(ctx->srqc_count); 195 req.number_of_cq = cpu_to_le32(ctx->cq_count); 196 197 req.max_qp_per_vf = cpu_to_le32(ctx->vf_res.max_qp_per_vf); 198 req.max_mrw_per_vf = cpu_to_le32(ctx->vf_res.max_mrw_per_vf); 199 req.max_srq_per_vf = cpu_to_le32(ctx->vf_res.max_srq_per_vf); 200 req.max_cq_per_vf = cpu_to_le32(ctx->vf_res.max_cq_per_vf); 201 req.max_gid_per_vf = cpu_to_le32(ctx->vf_res.max_gid_per_vf); 202 203 bnxt_qplib_fill_cmdqmsg(&msg, &req, &resp, NULL, sizeof(req), 204 sizeof(resp), 0); 205 rc = bnxt_qplib_rcfw_send_message(rcfw, &msg); 206 if (rc) { 207 dev_err(&res->pdev->dev, "Failed to set function resources\n"); 208 } 209 return rc; 210 } 211 212 /* SGID */ 213 int bnxt_qplib_get_sgid(struct bnxt_qplib_res *res, 214 struct bnxt_qplib_sgid_tbl *sgid_tbl, int index, 215 struct bnxt_qplib_gid *gid) 216 { 217 if (index >= sgid_tbl->max) { 218 dev_err(&res->pdev->dev, 219 "Index %d exceeded SGID table max (%d)\n", 220 index, sgid_tbl->max); 221 return -EINVAL; 222 } 223 memcpy(gid, &sgid_tbl->tbl[index].gid, sizeof(*gid)); 224 return 0; 225 } 226 227 int bnxt_qplib_del_sgid(struct bnxt_qplib_sgid_tbl *sgid_tbl, 228 struct bnxt_qplib_gid *gid, u16 vlan_id, bool update) 229 { 230 struct bnxt_qplib_res *res = to_bnxt_qplib(sgid_tbl, 231 struct bnxt_qplib_res, 232 sgid_tbl); 233 struct bnxt_qplib_rcfw *rcfw = res->rcfw; 234 int index; 235 236 if (!sgid_tbl) { 237 dev_err(&res->pdev->dev, "SGID table not allocated\n"); 238 return -EINVAL; 239 } 240 /* Do we need a sgid_lock here? */ 241 if (!sgid_tbl->active) { 242 dev_err(&res->pdev->dev, "SGID table has no active entries\n"); 243 return -ENOMEM; 244 } 245 for (index = 0; index < sgid_tbl->max; index++) { 246 if (!memcmp(&sgid_tbl->tbl[index].gid, gid, sizeof(*gid)) && 247 vlan_id == sgid_tbl->tbl[index].vlan_id) 248 break; 249 } 250 if (index == sgid_tbl->max) { 251 dev_warn(&res->pdev->dev, "GID not found in the SGID table\n"); 252 return 0; 253 } 254 /* Remove GID from the SGID table */ 255 if (update) { 256 struct creq_delete_gid_resp resp = {}; 257 struct bnxt_qplib_cmdqmsg msg = {}; 258 struct cmdq_delete_gid req = {}; 259 int rc; 260 261 bnxt_qplib_rcfw_cmd_prep((struct cmdq_base *)&req, 262 CMDQ_BASE_OPCODE_DELETE_GID, 263 sizeof(req)); 264 if (sgid_tbl->hw_id[index] == 0xFFFF) { 265 dev_err(&res->pdev->dev, 266 "GID entry contains an invalid HW id\n"); 267 return -EINVAL; 268 } 269 req.gid_index = cpu_to_le16(sgid_tbl->hw_id[index]); 270 bnxt_qplib_fill_cmdqmsg(&msg, &req, &resp, NULL, sizeof(req), 271 sizeof(resp), 0); 272 rc = bnxt_qplib_rcfw_send_message(rcfw, &msg); 273 if (rc) 274 return rc; 275 } 276 memcpy(&sgid_tbl->tbl[index].gid, &bnxt_qplib_gid_zero, 277 sizeof(bnxt_qplib_gid_zero)); 278 sgid_tbl->tbl[index].vlan_id = 0xFFFF; 279 sgid_tbl->vlan[index] = 0; 280 sgid_tbl->active--; 281 dev_dbg(&res->pdev->dev, 282 "SGID deleted hw_id[0x%x] = 0x%x active = 0x%x\n", 283 index, sgid_tbl->hw_id[index], sgid_tbl->active); 284 sgid_tbl->hw_id[index] = (u16)-1; 285 286 /* unlock */ 287 return 0; 288 } 289 290 int bnxt_qplib_add_sgid(struct bnxt_qplib_sgid_tbl *sgid_tbl, 291 struct bnxt_qplib_gid *gid, const u8 *smac, 292 u16 vlan_id, bool update, u32 *index) 293 { 294 struct bnxt_qplib_res *res = to_bnxt_qplib(sgid_tbl, 295 struct bnxt_qplib_res, 296 sgid_tbl); 297 struct bnxt_qplib_rcfw *rcfw = res->rcfw; 298 int i, free_idx; 299 300 if (!sgid_tbl) { 301 dev_err(&res->pdev->dev, "SGID table not allocated\n"); 302 return -EINVAL; 303 } 304 /* Do we need a sgid_lock here? */ 305 if (sgid_tbl->active == sgid_tbl->max) { 306 dev_err(&res->pdev->dev, "SGID table is full\n"); 307 return -ENOMEM; 308 } 309 free_idx = sgid_tbl->max; 310 for (i = 0; i < sgid_tbl->max; i++) { 311 if (!memcmp(&sgid_tbl->tbl[i], gid, sizeof(*gid)) && 312 sgid_tbl->tbl[i].vlan_id == vlan_id) { 313 dev_dbg(&res->pdev->dev, 314 "SGID entry already exist in entry %d!\n", i); 315 *index = i; 316 return -EALREADY; 317 } else if (!memcmp(&sgid_tbl->tbl[i], &bnxt_qplib_gid_zero, 318 sizeof(bnxt_qplib_gid_zero)) && 319 free_idx == sgid_tbl->max) { 320 free_idx = i; 321 } 322 } 323 if (free_idx == sgid_tbl->max) { 324 dev_err(&res->pdev->dev, 325 "SGID table is FULL but count is not MAX??\n"); 326 return -ENOMEM; 327 } 328 if (update) { 329 struct creq_add_gid_resp resp = {}; 330 struct bnxt_qplib_cmdqmsg msg = {}; 331 struct cmdq_add_gid req = {}; 332 int rc; 333 334 bnxt_qplib_rcfw_cmd_prep((struct cmdq_base *)&req, 335 CMDQ_BASE_OPCODE_ADD_GID, 336 sizeof(req)); 337 338 req.gid[0] = cpu_to_be32(((u32 *)gid->data)[3]); 339 req.gid[1] = cpu_to_be32(((u32 *)gid->data)[2]); 340 req.gid[2] = cpu_to_be32(((u32 *)gid->data)[1]); 341 req.gid[3] = cpu_to_be32(((u32 *)gid->data)[0]); 342 /* 343 * driver should ensure that all RoCE traffic is always VLAN 344 * tagged if RoCE traffic is running on non-zero VLAN ID or 345 * RoCE traffic is running on non-zero Priority. 346 */ 347 if ((vlan_id != 0xFFFF) || res->prio) { 348 if (vlan_id != 0xFFFF) 349 req.vlan = cpu_to_le16 350 (vlan_id & CMDQ_ADD_GID_VLAN_VLAN_ID_MASK); 351 req.vlan |= cpu_to_le16 352 (CMDQ_ADD_GID_VLAN_TPID_TPID_8100 | 353 CMDQ_ADD_GID_VLAN_VLAN_EN); 354 } 355 356 /* MAC in network format */ 357 req.src_mac[0] = cpu_to_be16(((u16 *)smac)[0]); 358 req.src_mac[1] = cpu_to_be16(((u16 *)smac)[1]); 359 req.src_mac[2] = cpu_to_be16(((u16 *)smac)[2]); 360 361 bnxt_qplib_fill_cmdqmsg(&msg, &req, &resp, NULL, sizeof(req), 362 sizeof(resp), 0); 363 rc = bnxt_qplib_rcfw_send_message(rcfw, &msg); 364 if (rc) 365 return rc; 366 sgid_tbl->hw_id[free_idx] = le32_to_cpu(resp.xid); 367 } 368 /* Add GID to the sgid_tbl */ 369 memcpy(&sgid_tbl->tbl[free_idx], gid, sizeof(*gid)); 370 sgid_tbl->tbl[free_idx].vlan_id = vlan_id; 371 sgid_tbl->active++; 372 if (vlan_id != 0xFFFF) 373 sgid_tbl->vlan[free_idx] = 1; 374 375 dev_dbg(&res->pdev->dev, 376 "SGID added hw_id[0x%x] = 0x%x active = 0x%x\n", 377 free_idx, sgid_tbl->hw_id[free_idx], sgid_tbl->active); 378 379 *index = free_idx; 380 /* unlock */ 381 return 0; 382 } 383 384 int bnxt_qplib_update_sgid(struct bnxt_qplib_sgid_tbl *sgid_tbl, 385 struct bnxt_qplib_gid *gid, u16 gid_idx, 386 const u8 *smac) 387 { 388 struct bnxt_qplib_res *res = to_bnxt_qplib(sgid_tbl, 389 struct bnxt_qplib_res, 390 sgid_tbl); 391 struct bnxt_qplib_rcfw *rcfw = res->rcfw; 392 struct creq_modify_gid_resp resp = {}; 393 struct bnxt_qplib_cmdqmsg msg = {}; 394 struct cmdq_modify_gid req = {}; 395 int rc; 396 397 bnxt_qplib_rcfw_cmd_prep((struct cmdq_base *)&req, 398 CMDQ_BASE_OPCODE_MODIFY_GID, 399 sizeof(req)); 400 401 req.gid[0] = cpu_to_be32(((u32 *)gid->data)[3]); 402 req.gid[1] = cpu_to_be32(((u32 *)gid->data)[2]); 403 req.gid[2] = cpu_to_be32(((u32 *)gid->data)[1]); 404 req.gid[3] = cpu_to_be32(((u32 *)gid->data)[0]); 405 if (res->prio) { 406 req.vlan |= cpu_to_le16 407 (CMDQ_ADD_GID_VLAN_TPID_TPID_8100 | 408 CMDQ_ADD_GID_VLAN_VLAN_EN); 409 } 410 411 /* MAC in network format */ 412 req.src_mac[0] = cpu_to_be16(((u16 *)smac)[0]); 413 req.src_mac[1] = cpu_to_be16(((u16 *)smac)[1]); 414 req.src_mac[2] = cpu_to_be16(((u16 *)smac)[2]); 415 416 req.gid_index = cpu_to_le16(gid_idx); 417 418 bnxt_qplib_fill_cmdqmsg(&msg, &req, &resp, NULL, sizeof(req), 419 sizeof(resp), 0); 420 rc = bnxt_qplib_rcfw_send_message(rcfw, &msg); 421 return rc; 422 } 423 424 /* AH */ 425 int bnxt_qplib_create_ah(struct bnxt_qplib_res *res, struct bnxt_qplib_ah *ah, 426 bool block) 427 { 428 struct bnxt_qplib_rcfw *rcfw = res->rcfw; 429 struct creq_create_ah_resp resp = {}; 430 struct bnxt_qplib_cmdqmsg msg = {}; 431 struct cmdq_create_ah req = {}; 432 u32 temp32[4]; 433 u16 temp16[3]; 434 int rc; 435 436 bnxt_qplib_rcfw_cmd_prep((struct cmdq_base *)&req, 437 CMDQ_BASE_OPCODE_CREATE_AH, 438 sizeof(req)); 439 440 memcpy(temp32, ah->dgid.data, sizeof(struct bnxt_qplib_gid)); 441 req.dgid[0] = cpu_to_le32(temp32[0]); 442 req.dgid[1] = cpu_to_le32(temp32[1]); 443 req.dgid[2] = cpu_to_le32(temp32[2]); 444 req.dgid[3] = cpu_to_le32(temp32[3]); 445 446 req.type = ah->nw_type; 447 req.hop_limit = ah->hop_limit; 448 req.sgid_index = cpu_to_le16(res->sgid_tbl.hw_id[ah->sgid_index]); 449 req.dest_vlan_id_flow_label = cpu_to_le32((ah->flow_label & 450 CMDQ_CREATE_AH_FLOW_LABEL_MASK) | 451 CMDQ_CREATE_AH_DEST_VLAN_ID_MASK); 452 req.pd_id = cpu_to_le32(ah->pd->id); 453 req.traffic_class = ah->traffic_class; 454 455 /* MAC in network format */ 456 memcpy(temp16, ah->dmac, 6); 457 req.dest_mac[0] = cpu_to_le16(temp16[0]); 458 req.dest_mac[1] = cpu_to_le16(temp16[1]); 459 req.dest_mac[2] = cpu_to_le16(temp16[2]); 460 461 bnxt_qplib_fill_cmdqmsg(&msg, &req, &resp, NULL, sizeof(req), 462 sizeof(resp), block); 463 rc = bnxt_qplib_rcfw_send_message(rcfw, &msg); 464 if (rc) 465 return rc; 466 467 ah->id = le32_to_cpu(resp.xid); 468 return 0; 469 } 470 471 void bnxt_qplib_destroy_ah(struct bnxt_qplib_res *res, struct bnxt_qplib_ah *ah, 472 bool block) 473 { 474 struct bnxt_qplib_rcfw *rcfw = res->rcfw; 475 struct creq_destroy_ah_resp resp = {}; 476 struct bnxt_qplib_cmdqmsg msg = {}; 477 struct cmdq_destroy_ah req = {}; 478 479 /* Clean up the AH table in the device */ 480 bnxt_qplib_rcfw_cmd_prep((struct cmdq_base *)&req, 481 CMDQ_BASE_OPCODE_DESTROY_AH, 482 sizeof(req)); 483 484 req.ah_cid = cpu_to_le32(ah->id); 485 486 bnxt_qplib_fill_cmdqmsg(&msg, &req, &resp, NULL, sizeof(req), 487 sizeof(resp), block); 488 bnxt_qplib_rcfw_send_message(rcfw, &msg); 489 } 490 491 /* MRW */ 492 int bnxt_qplib_free_mrw(struct bnxt_qplib_res *res, struct bnxt_qplib_mrw *mrw) 493 { 494 struct creq_deallocate_key_resp resp = {}; 495 struct bnxt_qplib_rcfw *rcfw = res->rcfw; 496 struct cmdq_deallocate_key req = {}; 497 struct bnxt_qplib_cmdqmsg msg = {}; 498 int rc; 499 500 if (mrw->lkey == 0xFFFFFFFF) { 501 dev_info(&res->pdev->dev, "SP: Free a reserved lkey MRW\n"); 502 return 0; 503 } 504 505 bnxt_qplib_rcfw_cmd_prep((struct cmdq_base *)&req, 506 CMDQ_BASE_OPCODE_DEALLOCATE_KEY, 507 sizeof(req)); 508 509 req.mrw_flags = mrw->type; 510 511 if ((mrw->type == CMDQ_ALLOCATE_MRW_MRW_FLAGS_MW_TYPE1) || 512 (mrw->type == CMDQ_ALLOCATE_MRW_MRW_FLAGS_MW_TYPE2A) || 513 (mrw->type == CMDQ_ALLOCATE_MRW_MRW_FLAGS_MW_TYPE2B)) 514 req.key = cpu_to_le32(mrw->rkey); 515 else 516 req.key = cpu_to_le32(mrw->lkey); 517 518 bnxt_qplib_fill_cmdqmsg(&msg, &req, &resp, NULL, sizeof(req), 519 sizeof(resp), 0); 520 rc = bnxt_qplib_rcfw_send_message(rcfw, &msg); 521 if (rc) 522 return rc; 523 524 /* Free the qplib's MRW memory */ 525 if (mrw->hwq.max_elements) 526 bnxt_qplib_free_hwq(res, &mrw->hwq); 527 528 return 0; 529 } 530 531 int bnxt_qplib_alloc_mrw(struct bnxt_qplib_res *res, struct bnxt_qplib_mrw *mrw) 532 { 533 struct bnxt_qplib_rcfw *rcfw = res->rcfw; 534 struct creq_allocate_mrw_resp resp = {}; 535 struct bnxt_qplib_cmdqmsg msg = {}; 536 struct cmdq_allocate_mrw req = {}; 537 unsigned long tmp; 538 int rc; 539 540 bnxt_qplib_rcfw_cmd_prep((struct cmdq_base *)&req, 541 CMDQ_BASE_OPCODE_ALLOCATE_MRW, 542 sizeof(req)); 543 544 req.pd_id = cpu_to_le32(mrw->pd->id); 545 req.mrw_flags = mrw->type; 546 if ((mrw->type == CMDQ_ALLOCATE_MRW_MRW_FLAGS_PMR && 547 mrw->flags & BNXT_QPLIB_FR_PMR) || 548 mrw->type == CMDQ_ALLOCATE_MRW_MRW_FLAGS_MW_TYPE2A || 549 mrw->type == CMDQ_ALLOCATE_MRW_MRW_FLAGS_MW_TYPE2B) 550 req.access = CMDQ_ALLOCATE_MRW_ACCESS_CONSUMER_OWNED_KEY; 551 tmp = (unsigned long)mrw; 552 req.mrw_handle = cpu_to_le64(tmp); 553 554 bnxt_qplib_fill_cmdqmsg(&msg, &req, &resp, NULL, sizeof(req), 555 sizeof(resp), 0); 556 rc = bnxt_qplib_rcfw_send_message(rcfw, &msg); 557 if (rc) 558 return rc; 559 560 if ((mrw->type == CMDQ_ALLOCATE_MRW_MRW_FLAGS_MW_TYPE1) || 561 (mrw->type == CMDQ_ALLOCATE_MRW_MRW_FLAGS_MW_TYPE2A) || 562 (mrw->type == CMDQ_ALLOCATE_MRW_MRW_FLAGS_MW_TYPE2B)) 563 mrw->rkey = le32_to_cpu(resp.xid); 564 else 565 mrw->lkey = le32_to_cpu(resp.xid); 566 return 0; 567 } 568 569 int bnxt_qplib_dereg_mrw(struct bnxt_qplib_res *res, struct bnxt_qplib_mrw *mrw, 570 bool block) 571 { 572 struct bnxt_qplib_rcfw *rcfw = res->rcfw; 573 struct creq_deregister_mr_resp resp = {}; 574 struct bnxt_qplib_cmdqmsg msg = {}; 575 struct cmdq_deregister_mr req = {}; 576 int rc; 577 578 bnxt_qplib_rcfw_cmd_prep((struct cmdq_base *)&req, 579 CMDQ_BASE_OPCODE_DEREGISTER_MR, 580 sizeof(req)); 581 582 req.lkey = cpu_to_le32(mrw->lkey); 583 bnxt_qplib_fill_cmdqmsg(&msg, &req, &resp, NULL, sizeof(req), 584 sizeof(resp), block); 585 rc = bnxt_qplib_rcfw_send_message(rcfw, &msg); 586 if (rc) 587 return rc; 588 589 /* Free the qplib's MR memory */ 590 if (mrw->hwq.max_elements) { 591 mrw->va = 0; 592 mrw->total_size = 0; 593 bnxt_qplib_free_hwq(res, &mrw->hwq); 594 } 595 596 return 0; 597 } 598 599 int bnxt_qplib_reg_mr(struct bnxt_qplib_res *res, struct bnxt_qplib_mrw *mr, 600 struct ib_umem *umem, int num_pbls, u32 buf_pg_size) 601 { 602 struct bnxt_qplib_rcfw *rcfw = res->rcfw; 603 struct bnxt_qplib_hwq_attr hwq_attr = {}; 604 struct bnxt_qplib_sg_info sginfo = {}; 605 struct creq_register_mr_resp resp = {}; 606 struct bnxt_qplib_cmdqmsg msg = {}; 607 struct cmdq_register_mr req = {}; 608 int pages, rc; 609 u32 pg_size; 610 u16 level; 611 612 if (num_pbls) { 613 pages = roundup_pow_of_two(num_pbls); 614 /* Allocate memory for the non-leaf pages to store buf ptrs. 615 * Non-leaf pages always uses system PAGE_SIZE 616 */ 617 /* Free the hwq if it already exist, must be a rereg */ 618 if (mr->hwq.max_elements) 619 bnxt_qplib_free_hwq(res, &mr->hwq); 620 hwq_attr.res = res; 621 hwq_attr.depth = pages; 622 hwq_attr.stride = sizeof(dma_addr_t); 623 hwq_attr.type = HWQ_TYPE_MR; 624 hwq_attr.sginfo = &sginfo; 625 hwq_attr.sginfo->umem = umem; 626 hwq_attr.sginfo->npages = pages; 627 hwq_attr.sginfo->pgsize = buf_pg_size; 628 hwq_attr.sginfo->pgshft = ilog2(buf_pg_size); 629 rc = bnxt_qplib_alloc_init_hwq(&mr->hwq, &hwq_attr); 630 if (rc) { 631 dev_err(&res->pdev->dev, 632 "SP: Reg MR memory allocation failed\n"); 633 return -ENOMEM; 634 } 635 } 636 637 bnxt_qplib_rcfw_cmd_prep((struct cmdq_base *)&req, 638 CMDQ_BASE_OPCODE_REGISTER_MR, 639 sizeof(req)); 640 641 /* Configure the request */ 642 if (mr->hwq.level == PBL_LVL_MAX) { 643 /* No PBL provided, just use system PAGE_SIZE */ 644 level = 0; 645 req.pbl = 0; 646 pg_size = PAGE_SIZE; 647 } else { 648 level = mr->hwq.level; 649 req.pbl = cpu_to_le64(mr->hwq.pbl[PBL_LVL_0].pg_map_arr[0]); 650 } 651 pg_size = buf_pg_size ? buf_pg_size : PAGE_SIZE; 652 req.log2_pg_size_lvl = (level << CMDQ_REGISTER_MR_LVL_SFT) | 653 ((ilog2(pg_size) << 654 CMDQ_REGISTER_MR_LOG2_PG_SIZE_SFT) & 655 CMDQ_REGISTER_MR_LOG2_PG_SIZE_MASK); 656 req.log2_pbl_pg_size = cpu_to_le16(((ilog2(PAGE_SIZE) << 657 CMDQ_REGISTER_MR_LOG2_PBL_PG_SIZE_SFT) & 658 CMDQ_REGISTER_MR_LOG2_PBL_PG_SIZE_MASK)); 659 req.access = (mr->flags & 0xFFFF); 660 req.va = cpu_to_le64(mr->va); 661 req.key = cpu_to_le32(mr->lkey); 662 req.mr_size = cpu_to_le64(mr->total_size); 663 664 bnxt_qplib_fill_cmdqmsg(&msg, &req, &resp, NULL, sizeof(req), 665 sizeof(resp), 0); 666 rc = bnxt_qplib_rcfw_send_message(rcfw, &msg); 667 if (rc) 668 goto fail; 669 670 return 0; 671 672 fail: 673 if (mr->hwq.max_elements) 674 bnxt_qplib_free_hwq(res, &mr->hwq); 675 return rc; 676 } 677 678 int bnxt_qplib_alloc_fast_reg_page_list(struct bnxt_qplib_res *res, 679 struct bnxt_qplib_frpl *frpl, 680 int max_pg_ptrs) 681 { 682 struct bnxt_qplib_hwq_attr hwq_attr = {}; 683 struct bnxt_qplib_sg_info sginfo = {}; 684 int pg_ptrs, pages, rc; 685 686 /* Re-calculate the max to fit the HWQ allocation model */ 687 pg_ptrs = roundup_pow_of_two(max_pg_ptrs); 688 pages = pg_ptrs >> MAX_PBL_LVL_1_PGS_SHIFT; 689 if (!pages) 690 pages++; 691 692 if (pages > MAX_PBL_LVL_1_PGS) 693 return -ENOMEM; 694 695 sginfo.pgsize = PAGE_SIZE; 696 sginfo.nopte = true; 697 698 hwq_attr.res = res; 699 hwq_attr.depth = pg_ptrs; 700 hwq_attr.stride = PAGE_SIZE; 701 hwq_attr.sginfo = &sginfo; 702 hwq_attr.type = HWQ_TYPE_CTX; 703 rc = bnxt_qplib_alloc_init_hwq(&frpl->hwq, &hwq_attr); 704 if (!rc) 705 frpl->max_pg_ptrs = pg_ptrs; 706 707 return rc; 708 } 709 710 int bnxt_qplib_free_fast_reg_page_list(struct bnxt_qplib_res *res, 711 struct bnxt_qplib_frpl *frpl) 712 { 713 bnxt_qplib_free_hwq(res, &frpl->hwq); 714 return 0; 715 } 716 717 int bnxt_qplib_get_roce_stats(struct bnxt_qplib_rcfw *rcfw, 718 struct bnxt_qplib_roce_stats *stats) 719 { 720 struct creq_query_roce_stats_resp resp = {}; 721 struct creq_query_roce_stats_resp_sb *sb; 722 struct cmdq_query_roce_stats req = {}; 723 struct bnxt_qplib_cmdqmsg msg = {}; 724 struct bnxt_qplib_rcfw_sbuf *sbuf; 725 int rc = 0; 726 727 bnxt_qplib_rcfw_cmd_prep((struct cmdq_base *)&req, 728 CMDQ_BASE_OPCODE_QUERY_ROCE_STATS, 729 sizeof(req)); 730 731 sbuf = bnxt_qplib_rcfw_alloc_sbuf(rcfw, sizeof(*sb)); 732 if (!sbuf) { 733 dev_err(&rcfw->pdev->dev, 734 "SP: QUERY_ROCE_STATS alloc side buffer failed\n"); 735 return -ENOMEM; 736 } 737 738 sb = sbuf->sb; 739 req.resp_size = sizeof(*sb) / BNXT_QPLIB_CMDQE_UNITS; 740 bnxt_qplib_fill_cmdqmsg(&msg, &req, &resp, sbuf, sizeof(req), 741 sizeof(resp), 0); 742 rc = bnxt_qplib_rcfw_send_message(rcfw, &msg); 743 if (rc) 744 goto bail; 745 /* Extract the context from the side buffer */ 746 stats->to_retransmits = le64_to_cpu(sb->to_retransmits); 747 stats->seq_err_naks_rcvd = le64_to_cpu(sb->seq_err_naks_rcvd); 748 stats->max_retry_exceeded = le64_to_cpu(sb->max_retry_exceeded); 749 stats->rnr_naks_rcvd = le64_to_cpu(sb->rnr_naks_rcvd); 750 stats->missing_resp = le64_to_cpu(sb->missing_resp); 751 stats->unrecoverable_err = le64_to_cpu(sb->unrecoverable_err); 752 stats->bad_resp_err = le64_to_cpu(sb->bad_resp_err); 753 stats->local_qp_op_err = le64_to_cpu(sb->local_qp_op_err); 754 stats->local_protection_err = le64_to_cpu(sb->local_protection_err); 755 stats->mem_mgmt_op_err = le64_to_cpu(sb->mem_mgmt_op_err); 756 stats->remote_invalid_req_err = le64_to_cpu(sb->remote_invalid_req_err); 757 stats->remote_access_err = le64_to_cpu(sb->remote_access_err); 758 stats->remote_op_err = le64_to_cpu(sb->remote_op_err); 759 stats->dup_req = le64_to_cpu(sb->dup_req); 760 stats->res_exceed_max = le64_to_cpu(sb->res_exceed_max); 761 stats->res_length_mismatch = le64_to_cpu(sb->res_length_mismatch); 762 stats->res_exceeds_wqe = le64_to_cpu(sb->res_exceeds_wqe); 763 stats->res_opcode_err = le64_to_cpu(sb->res_opcode_err); 764 stats->res_rx_invalid_rkey = le64_to_cpu(sb->res_rx_invalid_rkey); 765 stats->res_rx_domain_err = le64_to_cpu(sb->res_rx_domain_err); 766 stats->res_rx_no_perm = le64_to_cpu(sb->res_rx_no_perm); 767 stats->res_rx_range_err = le64_to_cpu(sb->res_rx_range_err); 768 stats->res_tx_invalid_rkey = le64_to_cpu(sb->res_tx_invalid_rkey); 769 stats->res_tx_domain_err = le64_to_cpu(sb->res_tx_domain_err); 770 stats->res_tx_no_perm = le64_to_cpu(sb->res_tx_no_perm); 771 stats->res_tx_range_err = le64_to_cpu(sb->res_tx_range_err); 772 stats->res_irrq_oflow = le64_to_cpu(sb->res_irrq_oflow); 773 stats->res_unsup_opcode = le64_to_cpu(sb->res_unsup_opcode); 774 stats->res_unaligned_atomic = le64_to_cpu(sb->res_unaligned_atomic); 775 stats->res_rem_inv_err = le64_to_cpu(sb->res_rem_inv_err); 776 stats->res_mem_error = le64_to_cpu(sb->res_mem_error); 777 stats->res_srq_err = le64_to_cpu(sb->res_srq_err); 778 stats->res_cmp_err = le64_to_cpu(sb->res_cmp_err); 779 stats->res_invalid_dup_rkey = le64_to_cpu(sb->res_invalid_dup_rkey); 780 stats->res_wqe_format_err = le64_to_cpu(sb->res_wqe_format_err); 781 stats->res_cq_load_err = le64_to_cpu(sb->res_cq_load_err); 782 stats->res_srq_load_err = le64_to_cpu(sb->res_srq_load_err); 783 stats->res_tx_pci_err = le64_to_cpu(sb->res_tx_pci_err); 784 stats->res_rx_pci_err = le64_to_cpu(sb->res_rx_pci_err); 785 if (!rcfw->init_oos_stats) { 786 rcfw->oos_prev = le64_to_cpu(sb->res_oos_drop_count); 787 rcfw->init_oos_stats = 1; 788 } else { 789 stats->res_oos_drop_count += 790 (le64_to_cpu(sb->res_oos_drop_count) - 791 rcfw->oos_prev) & BNXT_QPLIB_OOS_COUNT_MASK; 792 rcfw->oos_prev = le64_to_cpu(sb->res_oos_drop_count); 793 } 794 795 bail: 796 bnxt_qplib_rcfw_free_sbuf(rcfw, sbuf); 797 return rc; 798 } 799 800 int bnxt_qplib_qext_stat(struct bnxt_qplib_rcfw *rcfw, u32 fid, 801 struct bnxt_qplib_ext_stat *estat) 802 { 803 struct creq_query_roce_stats_ext_resp resp = {}; 804 struct creq_query_roce_stats_ext_resp_sb *sb; 805 struct cmdq_query_roce_stats_ext req = {}; 806 struct bnxt_qplib_cmdqmsg msg = {}; 807 struct bnxt_qplib_rcfw_sbuf *sbuf; 808 int rc; 809 810 sbuf = bnxt_qplib_rcfw_alloc_sbuf(rcfw, sizeof(*sb)); 811 if (!sbuf) { 812 dev_err(&rcfw->pdev->dev, 813 "SP: QUERY_ROCE_STATS_EXT alloc sb failed"); 814 return -ENOMEM; 815 } 816 817 bnxt_qplib_rcfw_cmd_prep((struct cmdq_base *)&req, 818 CMDQ_QUERY_ROCE_STATS_EXT_OPCODE_QUERY_ROCE_STATS, 819 sizeof(req)); 820 821 req.resp_size = ALIGN(sizeof(*sb), BNXT_QPLIB_CMDQE_UNITS); 822 req.resp_addr = cpu_to_le64(sbuf->dma_addr); 823 req.function_id = cpu_to_le32(fid); 824 req.flags = cpu_to_le16(CMDQ_QUERY_ROCE_STATS_EXT_FLAGS_FUNCTION_ID); 825 826 bnxt_qplib_fill_cmdqmsg(&msg, &req, &resp, sbuf, sizeof(req), 827 sizeof(resp), 0); 828 rc = bnxt_qplib_rcfw_send_message(rcfw, &msg); 829 if (rc) 830 goto bail; 831 832 sb = sbuf->sb; 833 estat->tx_atomic_req = le64_to_cpu(sb->tx_atomic_req_pkts); 834 estat->tx_read_req = le64_to_cpu(sb->tx_read_req_pkts); 835 estat->tx_read_res = le64_to_cpu(sb->tx_read_res_pkts); 836 estat->tx_write_req = le64_to_cpu(sb->tx_write_req_pkts); 837 estat->tx_send_req = le64_to_cpu(sb->tx_send_req_pkts); 838 estat->rx_atomic_req = le64_to_cpu(sb->rx_atomic_req_pkts); 839 estat->rx_read_req = le64_to_cpu(sb->rx_read_req_pkts); 840 estat->rx_read_res = le64_to_cpu(sb->rx_read_res_pkts); 841 estat->rx_write_req = le64_to_cpu(sb->rx_write_req_pkts); 842 estat->rx_send_req = le64_to_cpu(sb->rx_send_req_pkts); 843 estat->rx_roce_good_pkts = le64_to_cpu(sb->rx_roce_good_pkts); 844 estat->rx_roce_good_bytes = le64_to_cpu(sb->rx_roce_good_bytes); 845 estat->rx_out_of_buffer = le64_to_cpu(sb->rx_out_of_buffer_pkts); 846 estat->rx_out_of_sequence = le64_to_cpu(sb->rx_out_of_sequence_pkts); 847 848 bail: 849 bnxt_qplib_rcfw_free_sbuf(rcfw, sbuf); 850 return rc; 851 } 852 853 static void bnxt_qplib_fill_cc_gen1(struct cmdq_modify_roce_cc_gen1_tlv *ext_req, 854 struct bnxt_qplib_cc_param_ext *cc_ext) 855 { 856 ext_req->modify_mask = cpu_to_le64(cc_ext->ext_mask); 857 cc_ext->ext_mask = 0; 858 ext_req->inactivity_th_hi = cpu_to_le16(cc_ext->inact_th_hi); 859 ext_req->min_time_between_cnps = cpu_to_le16(cc_ext->min_delta_cnp); 860 ext_req->init_cp = cpu_to_le16(cc_ext->init_cp); 861 ext_req->tr_update_mode = cc_ext->tr_update_mode; 862 ext_req->tr_update_cycles = cc_ext->tr_update_cyls; 863 ext_req->fr_num_rtts = cc_ext->fr_rtt; 864 ext_req->ai_rate_increase = cc_ext->ai_rate_incr; 865 ext_req->reduction_relax_rtts_th = cpu_to_le16(cc_ext->rr_rtt_th); 866 ext_req->additional_relax_cr_th = cpu_to_le16(cc_ext->ar_cr_th); 867 ext_req->cr_min_th = cpu_to_le16(cc_ext->cr_min_th); 868 ext_req->bw_avg_weight = cc_ext->bw_avg_weight; 869 ext_req->actual_cr_factor = cc_ext->cr_factor; 870 ext_req->max_cp_cr_th = cpu_to_le16(cc_ext->cr_th_max_cp); 871 ext_req->cp_bias_en = cc_ext->cp_bias_en; 872 ext_req->cp_bias = cc_ext->cp_bias; 873 ext_req->cnp_ecn = cc_ext->cnp_ecn; 874 ext_req->rtt_jitter_en = cc_ext->rtt_jitter_en; 875 ext_req->link_bytes_per_usec = cpu_to_le16(cc_ext->bytes_per_usec); 876 ext_req->reset_cc_cr_th = cpu_to_le16(cc_ext->cc_cr_reset_th); 877 ext_req->cr_width = cc_ext->cr_width; 878 ext_req->quota_period_min = cc_ext->min_quota; 879 ext_req->quota_period_max = cc_ext->max_quota; 880 ext_req->quota_period_abs_max = cc_ext->abs_max_quota; 881 ext_req->tr_lower_bound = cpu_to_le16(cc_ext->tr_lb); 882 ext_req->cr_prob_factor = cc_ext->cr_prob_fac; 883 ext_req->tr_prob_factor = cc_ext->tr_prob_fac; 884 ext_req->fairness_cr_th = cpu_to_le16(cc_ext->fair_cr_th); 885 ext_req->red_div = cc_ext->red_div; 886 ext_req->cnp_ratio_th = cc_ext->cnp_ratio_th; 887 ext_req->exp_ai_rtts = cpu_to_le16(cc_ext->ai_ext_rtt); 888 ext_req->exp_ai_cr_cp_ratio = cc_ext->exp_crcp_ratio; 889 ext_req->use_rate_table = cc_ext->low_rate_en; 890 ext_req->cp_exp_update_th = cpu_to_le16(cc_ext->cpcr_update_th); 891 ext_req->high_exp_ai_rtts_th1 = cpu_to_le16(cc_ext->ai_rtt_th1); 892 ext_req->high_exp_ai_rtts_th2 = cpu_to_le16(cc_ext->ai_rtt_th2); 893 ext_req->actual_cr_cong_free_rtts_th = cpu_to_le16(cc_ext->cf_rtt_th); 894 ext_req->severe_cong_cr_th1 = cpu_to_le16(cc_ext->sc_cr_th1); 895 ext_req->severe_cong_cr_th2 = cpu_to_le16(cc_ext->sc_cr_th2); 896 ext_req->link64B_per_rtt = cpu_to_le32(cc_ext->l64B_per_rtt); 897 ext_req->cc_ack_bytes = cc_ext->cc_ack_bytes; 898 } 899 900 int bnxt_qplib_modify_cc(struct bnxt_qplib_res *res, 901 struct bnxt_qplib_cc_param *cc_param) 902 { 903 struct bnxt_qplib_tlv_modify_cc_req tlv_req = {}; 904 struct creq_modify_roce_cc_resp resp = {}; 905 struct bnxt_qplib_cmdqmsg msg = {}; 906 struct cmdq_modify_roce_cc *req; 907 int req_size; 908 void *cmd; 909 int rc; 910 911 /* Prepare the older base command */ 912 req = &tlv_req.base_req; 913 cmd = req; 914 req_size = sizeof(*req); 915 bnxt_qplib_rcfw_cmd_prep((struct cmdq_base *)req, CMDQ_BASE_OPCODE_MODIFY_ROCE_CC, 916 sizeof(*req)); 917 req->modify_mask = cpu_to_le32(cc_param->mask); 918 req->enable_cc = cc_param->enable; 919 req->g = cc_param->g; 920 req->num_phases_per_state = cc_param->nph_per_state; 921 req->time_per_phase = cc_param->time_pph; 922 req->pkts_per_phase = cc_param->pkts_pph; 923 req->init_cr = cpu_to_le16(cc_param->init_cr); 924 req->init_tr = cpu_to_le16(cc_param->init_tr); 925 req->tos_dscp_tos_ecn = (cc_param->tos_dscp << CMDQ_MODIFY_ROCE_CC_TOS_DSCP_SFT) | 926 (cc_param->tos_ecn & CMDQ_MODIFY_ROCE_CC_TOS_ECN_MASK); 927 req->alt_vlan_pcp = cc_param->alt_vlan_pcp; 928 req->alt_tos_dscp = cpu_to_le16(cc_param->alt_tos_dscp); 929 req->rtt = cpu_to_le16(cc_param->rtt); 930 req->tcp_cp = cpu_to_le16(cc_param->tcp_cp); 931 req->cc_mode = cc_param->cc_mode; 932 req->inactivity_th = cpu_to_le16(cc_param->inact_th); 933 934 /* For chip gen P5 onwards fill extended cmd and header */ 935 if (bnxt_qplib_is_chip_gen_p5(res->cctx)) { 936 struct roce_tlv *hdr; 937 u32 payload; 938 u32 chunks; 939 940 cmd = &tlv_req; 941 req_size = sizeof(tlv_req); 942 /* Prepare primary tlv header */ 943 hdr = &tlv_req.tlv_hdr; 944 chunks = CHUNKS(sizeof(struct bnxt_qplib_tlv_modify_cc_req)); 945 payload = sizeof(struct cmdq_modify_roce_cc); 946 __roce_1st_tlv_prep(hdr, chunks, payload, true); 947 /* Prepare secondary tlv header */ 948 hdr = (struct roce_tlv *)&tlv_req.ext_req; 949 payload = sizeof(struct cmdq_modify_roce_cc_gen1_tlv) - 950 sizeof(struct roce_tlv); 951 __roce_ext_tlv_prep(hdr, TLV_TYPE_MODIFY_ROCE_CC_GEN1, payload, false, true); 952 bnxt_qplib_fill_cc_gen1(&tlv_req.ext_req, &cc_param->cc_ext); 953 } 954 955 bnxt_qplib_fill_cmdqmsg(&msg, cmd, &resp, NULL, req_size, 956 sizeof(resp), 0); 957 rc = bnxt_qplib_rcfw_send_message(res->rcfw, &msg); 958 return rc; 959 } 960