1 /* 2 * Broadcom NetXtreme-E RoCE driver. 3 * 4 * Copyright (c) 2016 - 2017, Broadcom. All rights reserved. The term 5 * Broadcom refers to Broadcom Limited and/or its subsidiaries. 6 * 7 * This software is available to you under a choice of one of two 8 * licenses. You may choose to be licensed under the terms of the GNU 9 * General Public License (GPL) Version 2, available from the file 10 * COPYING in the main directory of this source tree, or the 11 * BSD license below: 12 * 13 * Redistribution and use in source and binary forms, with or without 14 * modification, are permitted provided that the following conditions 15 * are met: 16 * 17 * 1. Redistributions of source code must retain the above copyright 18 * notice, this list of conditions and the following disclaimer. 19 * 2. Redistributions in binary form must reproduce the above copyright 20 * notice, this list of conditions and the following disclaimer in 21 * the documentation and/or other materials provided with the 22 * distribution. 23 * 24 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' 25 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, 26 * THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR 27 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS 28 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 29 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 30 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR 31 * BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, 32 * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE 33 * OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN 34 * IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 35 * 36 * Description: QPLib resource manager (header) 37 */ 38 39 #ifndef __BNXT_QPLIB_RES_H__ 40 #define __BNXT_QPLIB_RES_H__ 41 42 extern const struct bnxt_qplib_gid bnxt_qplib_gid_zero; 43 44 #define CHIP_NUM_57508 0x1750 45 #define CHIP_NUM_57504 0x1751 46 #define CHIP_NUM_57502 0x1752 47 48 enum bnxt_qplib_wqe_mode { 49 BNXT_QPLIB_WQE_MODE_STATIC = 0x00, 50 BNXT_QPLIB_WQE_MODE_VARIABLE = 0x01, 51 BNXT_QPLIB_WQE_MODE_INVALID = 0x02 52 }; 53 54 struct bnxt_qplib_drv_modes { 55 u8 wqe_mode; 56 /* Other modes to follow here */ 57 }; 58 59 struct bnxt_qplib_chip_ctx { 60 u16 chip_num; 61 u8 chip_rev; 62 u8 chip_metal; 63 struct bnxt_qplib_drv_modes modes; 64 }; 65 66 #define PTR_CNT_PER_PG (PAGE_SIZE / sizeof(void *)) 67 #define PTR_MAX_IDX_PER_PG (PTR_CNT_PER_PG - 1) 68 #define PTR_PG(x) (((x) & ~PTR_MAX_IDX_PER_PG) / PTR_CNT_PER_PG) 69 #define PTR_IDX(x) ((x) & PTR_MAX_IDX_PER_PG) 70 71 #define HWQ_CMP(idx, hwq) ((idx) & ((hwq)->max_elements - 1)) 72 73 #define HWQ_FREE_SLOTS(hwq) (hwq->max_elements - \ 74 ((HWQ_CMP(hwq->prod, hwq)\ 75 - HWQ_CMP(hwq->cons, hwq))\ 76 & (hwq->max_elements - 1))) 77 enum bnxt_qplib_hwq_type { 78 HWQ_TYPE_CTX, 79 HWQ_TYPE_QUEUE, 80 HWQ_TYPE_L2_CMPL, 81 HWQ_TYPE_MR 82 }; 83 84 #define MAX_PBL_LVL_0_PGS 1 85 #define MAX_PBL_LVL_1_PGS 512 86 #define MAX_PBL_LVL_1_PGS_SHIFT 9 87 #define MAX_PBL_LVL_1_PGS_FOR_LVL_2 256 88 #define MAX_PBL_LVL_2_PGS (256 * 512) 89 #define MAX_PDL_LVL_SHIFT 9 90 91 enum bnxt_qplib_pbl_lvl { 92 PBL_LVL_0, 93 PBL_LVL_1, 94 PBL_LVL_2, 95 PBL_LVL_MAX 96 }; 97 98 #define ROCE_PG_SIZE_4K (4 * 1024) 99 #define ROCE_PG_SIZE_8K (8 * 1024) 100 #define ROCE_PG_SIZE_64K (64 * 1024) 101 #define ROCE_PG_SIZE_2M (2 * 1024 * 1024) 102 #define ROCE_PG_SIZE_8M (8 * 1024 * 1024) 103 #define ROCE_PG_SIZE_1G (1024 * 1024 * 1024) 104 105 enum bnxt_qplib_hwrm_pg_size { 106 BNXT_QPLIB_HWRM_PG_SIZE_4K = 0, 107 BNXT_QPLIB_HWRM_PG_SIZE_8K = 1, 108 BNXT_QPLIB_HWRM_PG_SIZE_64K = 2, 109 BNXT_QPLIB_HWRM_PG_SIZE_2M = 3, 110 BNXT_QPLIB_HWRM_PG_SIZE_8M = 4, 111 BNXT_QPLIB_HWRM_PG_SIZE_1G = 5, 112 }; 113 114 struct bnxt_qplib_reg_desc { 115 u8 bar_id; 116 resource_size_t bar_base; 117 void __iomem *bar_reg; 118 size_t len; 119 }; 120 121 struct bnxt_qplib_pbl { 122 u32 pg_count; 123 u32 pg_size; 124 void **pg_arr; 125 dma_addr_t *pg_map_arr; 126 }; 127 128 struct bnxt_qplib_sg_info { 129 struct scatterlist *sghead; 130 u32 nmap; 131 u32 npages; 132 u32 pgshft; 133 u32 pgsize; 134 bool nopte; 135 }; 136 137 struct bnxt_qplib_hwq_attr { 138 struct bnxt_qplib_res *res; 139 struct bnxt_qplib_sg_info *sginfo; 140 enum bnxt_qplib_hwq_type type; 141 u32 depth; 142 u32 stride; 143 u32 aux_stride; 144 u32 aux_depth; 145 }; 146 147 struct bnxt_qplib_hwq { 148 struct pci_dev *pdev; 149 /* lock to protect qplib_hwq */ 150 spinlock_t lock; 151 struct bnxt_qplib_pbl pbl[PBL_LVL_MAX + 1]; 152 enum bnxt_qplib_pbl_lvl level; /* 0, 1, or 2 */ 153 /* ptr for easy access to the PBL entries */ 154 void **pbl_ptr; 155 /* ptr for easy access to the dma_addr */ 156 dma_addr_t *pbl_dma_ptr; 157 u32 max_elements; 158 u32 depth; 159 u16 element_size; /* Size of each entry */ 160 u16 qe_ppg; /* queue entry per page */ 161 162 u32 prod; /* raw */ 163 u32 cons; /* raw */ 164 u8 cp_bit; 165 u8 is_user; 166 u64 *pad_pg; 167 u32 pad_stride; 168 u32 pad_pgofft; 169 }; 170 171 struct bnxt_qplib_db_info { 172 void __iomem *db; 173 void __iomem *priv_db; 174 struct bnxt_qplib_hwq *hwq; 175 u32 xid; 176 u32 max_slot; 177 }; 178 179 /* Tables */ 180 struct bnxt_qplib_pd_tbl { 181 unsigned long *tbl; 182 u32 max; 183 }; 184 185 struct bnxt_qplib_sgid_tbl { 186 struct bnxt_qplib_gid_info *tbl; 187 u16 *hw_id; 188 u16 max; 189 u16 active; 190 void *ctx; 191 u8 *vlan; 192 }; 193 194 struct bnxt_qplib_pkey_tbl { 195 u16 *tbl; 196 u16 max; 197 u16 active; 198 }; 199 200 struct bnxt_qplib_dpi { 201 u32 dpi; 202 void __iomem *dbr; 203 u64 umdbr; 204 }; 205 206 struct bnxt_qplib_dpi_tbl { 207 void **app_tbl; 208 unsigned long *tbl; 209 u16 max; 210 void __iomem *dbr_bar_reg_iomem; 211 u64 unmapped_dbr; 212 }; 213 214 struct bnxt_qplib_stats { 215 dma_addr_t dma_map; 216 void *dma; 217 u32 size; 218 u32 fw_id; 219 }; 220 221 struct bnxt_qplib_vf_res { 222 u32 max_qp_per_vf; 223 u32 max_mrw_per_vf; 224 u32 max_srq_per_vf; 225 u32 max_cq_per_vf; 226 u32 max_gid_per_vf; 227 }; 228 229 #define BNXT_QPLIB_MAX_QP_CTX_ENTRY_SIZE 448 230 #define BNXT_QPLIB_MAX_SRQ_CTX_ENTRY_SIZE 64 231 #define BNXT_QPLIB_MAX_CQ_CTX_ENTRY_SIZE 64 232 #define BNXT_QPLIB_MAX_MRW_CTX_ENTRY_SIZE 128 233 234 #define MAX_TQM_ALLOC_REQ 48 235 #define MAX_TQM_ALLOC_BLK_SIZE 8 236 struct bnxt_qplib_tqm_ctx { 237 struct bnxt_qplib_hwq pde; 238 u8 pde_level; /* Original level */ 239 struct bnxt_qplib_hwq qtbl[MAX_TQM_ALLOC_REQ]; 240 u8 qcount[MAX_TQM_ALLOC_REQ]; 241 }; 242 243 struct bnxt_qplib_ctx { 244 u32 qpc_count; 245 struct bnxt_qplib_hwq qpc_tbl; 246 u32 mrw_count; 247 struct bnxt_qplib_hwq mrw_tbl; 248 u32 srqc_count; 249 struct bnxt_qplib_hwq srqc_tbl; 250 u32 cq_count; 251 struct bnxt_qplib_hwq cq_tbl; 252 struct bnxt_qplib_hwq tim_tbl; 253 struct bnxt_qplib_tqm_ctx tqm_ctx; 254 struct bnxt_qplib_stats stats; 255 struct bnxt_qplib_vf_res vf_res; 256 u64 hwrm_intf_ver; 257 }; 258 259 struct bnxt_qplib_res { 260 struct pci_dev *pdev; 261 struct bnxt_qplib_chip_ctx *cctx; 262 struct net_device *netdev; 263 264 struct bnxt_qplib_rcfw *rcfw; 265 struct bnxt_qplib_pd_tbl pd_tbl; 266 struct bnxt_qplib_sgid_tbl sgid_tbl; 267 struct bnxt_qplib_pkey_tbl pkey_tbl; 268 struct bnxt_qplib_dpi_tbl dpi_tbl; 269 bool prio; 270 }; 271 272 static inline bool bnxt_qplib_is_chip_gen_p5(struct bnxt_qplib_chip_ctx *cctx) 273 { 274 return (cctx->chip_num == CHIP_NUM_57508 || 275 cctx->chip_num == CHIP_NUM_57504 || 276 cctx->chip_num == CHIP_NUM_57502); 277 } 278 279 static inline u8 bnxt_qplib_get_hwq_type(struct bnxt_qplib_res *res) 280 { 281 return bnxt_qplib_is_chip_gen_p5(res->cctx) ? 282 HWQ_TYPE_QUEUE : HWQ_TYPE_L2_CMPL; 283 } 284 285 static inline u8 bnxt_qplib_get_ring_type(struct bnxt_qplib_chip_ctx *cctx) 286 { 287 return bnxt_qplib_is_chip_gen_p5(cctx) ? 288 RING_ALLOC_REQ_RING_TYPE_NQ : 289 RING_ALLOC_REQ_RING_TYPE_ROCE_CMPL; 290 } 291 292 static inline u8 bnxt_qplib_base_pg_size(struct bnxt_qplib_hwq *hwq) 293 { 294 u8 pg_size = BNXT_QPLIB_HWRM_PG_SIZE_4K; 295 struct bnxt_qplib_pbl *pbl; 296 297 pbl = &hwq->pbl[PBL_LVL_0]; 298 switch (pbl->pg_size) { 299 case ROCE_PG_SIZE_4K: 300 pg_size = BNXT_QPLIB_HWRM_PG_SIZE_4K; 301 break; 302 case ROCE_PG_SIZE_8K: 303 pg_size = BNXT_QPLIB_HWRM_PG_SIZE_8K; 304 break; 305 case ROCE_PG_SIZE_64K: 306 pg_size = BNXT_QPLIB_HWRM_PG_SIZE_64K; 307 break; 308 case ROCE_PG_SIZE_2M: 309 pg_size = BNXT_QPLIB_HWRM_PG_SIZE_2M; 310 break; 311 case ROCE_PG_SIZE_8M: 312 pg_size = BNXT_QPLIB_HWRM_PG_SIZE_8M; 313 break; 314 case ROCE_PG_SIZE_1G: 315 pg_size = BNXT_QPLIB_HWRM_PG_SIZE_1G; 316 break; 317 default: 318 break; 319 } 320 321 return pg_size; 322 } 323 324 static inline void *bnxt_qplib_get_qe(struct bnxt_qplib_hwq *hwq, 325 u32 indx, u64 *pg) 326 { 327 u32 pg_num, pg_idx; 328 329 pg_num = (indx / hwq->qe_ppg); 330 pg_idx = (indx % hwq->qe_ppg); 331 if (pg) 332 *pg = (u64)&hwq->pbl_ptr[pg_num]; 333 return (void *)(hwq->pbl_ptr[pg_num] + hwq->element_size * pg_idx); 334 } 335 336 static inline void *bnxt_qplib_get_prod_qe(struct bnxt_qplib_hwq *hwq, u32 idx) 337 { 338 idx += hwq->prod; 339 if (idx >= hwq->depth) 340 idx -= hwq->depth; 341 return bnxt_qplib_get_qe(hwq, idx, NULL); 342 } 343 344 #define to_bnxt_qplib(ptr, type, member) \ 345 container_of(ptr, type, member) 346 347 struct bnxt_qplib_pd; 348 struct bnxt_qplib_dev_attr; 349 350 void bnxt_qplib_free_hwq(struct bnxt_qplib_res *res, 351 struct bnxt_qplib_hwq *hwq); 352 int bnxt_qplib_alloc_init_hwq(struct bnxt_qplib_hwq *hwq, 353 struct bnxt_qplib_hwq_attr *hwq_attr); 354 void bnxt_qplib_get_guid(u8 *dev_addr, u8 *guid); 355 int bnxt_qplib_alloc_pd(struct bnxt_qplib_pd_tbl *pd_tbl, 356 struct bnxt_qplib_pd *pd); 357 int bnxt_qplib_dealloc_pd(struct bnxt_qplib_res *res, 358 struct bnxt_qplib_pd_tbl *pd_tbl, 359 struct bnxt_qplib_pd *pd); 360 int bnxt_qplib_alloc_dpi(struct bnxt_qplib_dpi_tbl *dpit, 361 struct bnxt_qplib_dpi *dpi, 362 void *app); 363 int bnxt_qplib_dealloc_dpi(struct bnxt_qplib_res *res, 364 struct bnxt_qplib_dpi_tbl *dpi_tbl, 365 struct bnxt_qplib_dpi *dpi); 366 void bnxt_qplib_cleanup_res(struct bnxt_qplib_res *res); 367 int bnxt_qplib_init_res(struct bnxt_qplib_res *res); 368 void bnxt_qplib_free_res(struct bnxt_qplib_res *res); 369 int bnxt_qplib_alloc_res(struct bnxt_qplib_res *res, struct pci_dev *pdev, 370 struct net_device *netdev, 371 struct bnxt_qplib_dev_attr *dev_attr); 372 void bnxt_qplib_free_ctx(struct bnxt_qplib_res *res, 373 struct bnxt_qplib_ctx *ctx); 374 int bnxt_qplib_alloc_ctx(struct bnxt_qplib_res *res, 375 struct bnxt_qplib_ctx *ctx, 376 bool virt_fn, bool is_p5); 377 378 static inline void bnxt_qplib_hwq_incr_prod(struct bnxt_qplib_hwq *hwq, u32 cnt) 379 { 380 hwq->prod = (hwq->prod + cnt) % hwq->depth; 381 } 382 383 static inline void bnxt_qplib_hwq_incr_cons(struct bnxt_qplib_hwq *hwq, 384 u32 cnt) 385 { 386 hwq->cons = (hwq->cons + cnt) % hwq->depth; 387 } 388 389 static inline void bnxt_qplib_ring_db32(struct bnxt_qplib_db_info *info, 390 bool arm) 391 { 392 u32 key; 393 394 key = info->hwq->cons & (info->hwq->max_elements - 1); 395 key |= (CMPL_DOORBELL_IDX_VALID | 396 (CMPL_DOORBELL_KEY_CMPL & CMPL_DOORBELL_KEY_MASK)); 397 if (!arm) 398 key |= CMPL_DOORBELL_MASK; 399 writel(key, info->db); 400 } 401 402 static inline void bnxt_qplib_ring_db(struct bnxt_qplib_db_info *info, 403 u32 type) 404 { 405 u64 key = 0; 406 407 key = (info->xid & DBC_DBC_XID_MASK) | DBC_DBC_PATH_ROCE | type; 408 key <<= 32; 409 key |= (info->hwq->cons & (info->hwq->max_elements - 1)) & 410 DBC_DBC_INDEX_MASK; 411 writeq(key, info->db); 412 } 413 414 static inline void bnxt_qplib_ring_prod_db(struct bnxt_qplib_db_info *info, 415 u32 type) 416 { 417 u64 key = 0; 418 419 key = (info->xid & DBC_DBC_XID_MASK) | DBC_DBC_PATH_ROCE | type; 420 key <<= 32; 421 key |= ((info->hwq->prod / info->max_slot)) & DBC_DBC_INDEX_MASK; 422 writeq(key, info->db); 423 } 424 425 static inline void bnxt_qplib_armen_db(struct bnxt_qplib_db_info *info, 426 u32 type) 427 { 428 u64 key = 0; 429 430 key = (info->xid & DBC_DBC_XID_MASK) | DBC_DBC_PATH_ROCE | type; 431 key <<= 32; 432 writeq(key, info->priv_db); 433 } 434 435 static inline void bnxt_qplib_srq_arm_db(struct bnxt_qplib_db_info *info, 436 u32 th) 437 { 438 u64 key = 0; 439 440 key = (info->xid & DBC_DBC_XID_MASK) | DBC_DBC_PATH_ROCE | th; 441 key <<= 32; 442 key |= th & DBC_DBC_INDEX_MASK; 443 writeq(key, info->priv_db); 444 } 445 446 static inline void bnxt_qplib_ring_nq_db(struct bnxt_qplib_db_info *info, 447 struct bnxt_qplib_chip_ctx *cctx, 448 bool arm) 449 { 450 u32 type; 451 452 type = arm ? DBC_DBC_TYPE_NQ_ARM : DBC_DBC_TYPE_NQ; 453 if (bnxt_qplib_is_chip_gen_p5(cctx)) 454 bnxt_qplib_ring_db(info, type); 455 else 456 bnxt_qplib_ring_db32(info, arm); 457 } 458 #endif /* __BNXT_QPLIB_RES_H__ */ 459