1 /* 2 * Broadcom NetXtreme-E RoCE driver. 3 * 4 * Copyright (c) 2016 - 2017, Broadcom. All rights reserved. The term 5 * Broadcom refers to Broadcom Limited and/or its subsidiaries. 6 * 7 * This software is available to you under a choice of one of two 8 * licenses. You may choose to be licensed under the terms of the GNU 9 * General Public License (GPL) Version 2, available from the file 10 * COPYING in the main directory of this source tree, or the 11 * BSD license below: 12 * 13 * Redistribution and use in source and binary forms, with or without 14 * modification, are permitted provided that the following conditions 15 * are met: 16 * 17 * 1. Redistributions of source code must retain the above copyright 18 * notice, this list of conditions and the following disclaimer. 19 * 2. Redistributions in binary form must reproduce the above copyright 20 * notice, this list of conditions and the following disclaimer in 21 * the documentation and/or other materials provided with the 22 * distribution. 23 * 24 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' 25 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, 26 * THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR 27 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS 28 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 29 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 30 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR 31 * BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, 32 * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE 33 * OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN 34 * IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 35 * 36 * Description: QPLib resource manager (header) 37 */ 38 39 #ifndef __BNXT_QPLIB_RES_H__ 40 #define __BNXT_QPLIB_RES_H__ 41 42 extern const struct bnxt_qplib_gid bnxt_qplib_gid_zero; 43 44 #define CHIP_NUM_57508 0x1750 45 #define CHIP_NUM_57504 0x1751 46 #define CHIP_NUM_57502 0x1752 47 48 struct bnxt_qplib_drv_modes { 49 u8 wqe_mode; 50 /* Other modes to follow here */ 51 }; 52 53 struct bnxt_qplib_chip_ctx { 54 u16 chip_num; 55 u8 chip_rev; 56 u8 chip_metal; 57 u16 hw_stats_size; 58 struct bnxt_qplib_drv_modes modes; 59 }; 60 61 #define PTR_CNT_PER_PG (PAGE_SIZE / sizeof(void *)) 62 #define PTR_MAX_IDX_PER_PG (PTR_CNT_PER_PG - 1) 63 #define PTR_PG(x) (((x) & ~PTR_MAX_IDX_PER_PG) / PTR_CNT_PER_PG) 64 #define PTR_IDX(x) ((x) & PTR_MAX_IDX_PER_PG) 65 66 #define HWQ_CMP(idx, hwq) ((idx) & ((hwq)->max_elements - 1)) 67 68 #define HWQ_FREE_SLOTS(hwq) (hwq->max_elements - \ 69 ((HWQ_CMP(hwq->prod, hwq)\ 70 - HWQ_CMP(hwq->cons, hwq))\ 71 & (hwq->max_elements - 1))) 72 enum bnxt_qplib_hwq_type { 73 HWQ_TYPE_CTX, 74 HWQ_TYPE_QUEUE, 75 HWQ_TYPE_L2_CMPL, 76 HWQ_TYPE_MR 77 }; 78 79 #define MAX_PBL_LVL_0_PGS 1 80 #define MAX_PBL_LVL_1_PGS 512 81 #define MAX_PBL_LVL_1_PGS_SHIFT 9 82 #define MAX_PBL_LVL_1_PGS_FOR_LVL_2 256 83 #define MAX_PBL_LVL_2_PGS (256 * 512) 84 #define MAX_PDL_LVL_SHIFT 9 85 86 enum bnxt_qplib_pbl_lvl { 87 PBL_LVL_0, 88 PBL_LVL_1, 89 PBL_LVL_2, 90 PBL_LVL_MAX 91 }; 92 93 #define ROCE_PG_SIZE_4K (4 * 1024) 94 #define ROCE_PG_SIZE_8K (8 * 1024) 95 #define ROCE_PG_SIZE_64K (64 * 1024) 96 #define ROCE_PG_SIZE_2M (2 * 1024 * 1024) 97 #define ROCE_PG_SIZE_8M (8 * 1024 * 1024) 98 #define ROCE_PG_SIZE_1G (1024 * 1024 * 1024) 99 100 enum bnxt_qplib_hwrm_pg_size { 101 BNXT_QPLIB_HWRM_PG_SIZE_4K = 0, 102 BNXT_QPLIB_HWRM_PG_SIZE_8K = 1, 103 BNXT_QPLIB_HWRM_PG_SIZE_64K = 2, 104 BNXT_QPLIB_HWRM_PG_SIZE_2M = 3, 105 BNXT_QPLIB_HWRM_PG_SIZE_8M = 4, 106 BNXT_QPLIB_HWRM_PG_SIZE_1G = 5, 107 }; 108 109 struct bnxt_qplib_reg_desc { 110 u8 bar_id; 111 resource_size_t bar_base; 112 void __iomem *bar_reg; 113 size_t len; 114 }; 115 116 struct bnxt_qplib_pbl { 117 u32 pg_count; 118 u32 pg_size; 119 void **pg_arr; 120 dma_addr_t *pg_map_arr; 121 }; 122 123 struct bnxt_qplib_sg_info { 124 struct ib_umem *umem; 125 u32 npages; 126 u32 pgshft; 127 u32 pgsize; 128 bool nopte; 129 }; 130 131 struct bnxt_qplib_hwq_attr { 132 struct bnxt_qplib_res *res; 133 struct bnxt_qplib_sg_info *sginfo; 134 enum bnxt_qplib_hwq_type type; 135 u32 depth; 136 u32 stride; 137 u32 aux_stride; 138 u32 aux_depth; 139 }; 140 141 struct bnxt_qplib_hwq { 142 struct pci_dev *pdev; 143 /* lock to protect qplib_hwq */ 144 spinlock_t lock; 145 struct bnxt_qplib_pbl pbl[PBL_LVL_MAX + 1]; 146 enum bnxt_qplib_pbl_lvl level; /* 0, 1, or 2 */ 147 /* ptr for easy access to the PBL entries */ 148 void **pbl_ptr; 149 /* ptr for easy access to the dma_addr */ 150 dma_addr_t *pbl_dma_ptr; 151 u32 max_elements; 152 u32 depth; 153 u16 element_size; /* Size of each entry */ 154 u16 qe_ppg; /* queue entry per page */ 155 156 u32 prod; /* raw */ 157 u32 cons; /* raw */ 158 u8 cp_bit; 159 u8 is_user; 160 u64 *pad_pg; 161 u32 pad_stride; 162 u32 pad_pgofft; 163 }; 164 165 struct bnxt_qplib_db_info { 166 void __iomem *db; 167 void __iomem *priv_db; 168 struct bnxt_qplib_hwq *hwq; 169 u32 xid; 170 u32 max_slot; 171 }; 172 173 /* Tables */ 174 struct bnxt_qplib_pd_tbl { 175 unsigned long *tbl; 176 u32 max; 177 }; 178 179 struct bnxt_qplib_sgid_tbl { 180 struct bnxt_qplib_gid_info *tbl; 181 u16 *hw_id; 182 u16 max; 183 u16 active; 184 void *ctx; 185 u8 *vlan; 186 }; 187 188 struct bnxt_qplib_pkey_tbl { 189 u16 *tbl; 190 u16 max; 191 u16 active; 192 }; 193 194 struct bnxt_qplib_dpi { 195 u32 dpi; 196 void __iomem *dbr; 197 u64 umdbr; 198 }; 199 200 struct bnxt_qplib_dpi_tbl { 201 void **app_tbl; 202 unsigned long *tbl; 203 u16 max; 204 void __iomem *dbr_bar_reg_iomem; 205 u64 unmapped_dbr; 206 }; 207 208 struct bnxt_qplib_stats { 209 dma_addr_t dma_map; 210 void *dma; 211 u32 size; 212 u32 fw_id; 213 }; 214 215 struct bnxt_qplib_vf_res { 216 u32 max_qp_per_vf; 217 u32 max_mrw_per_vf; 218 u32 max_srq_per_vf; 219 u32 max_cq_per_vf; 220 u32 max_gid_per_vf; 221 }; 222 223 #define BNXT_QPLIB_MAX_QP_CTX_ENTRY_SIZE 448 224 #define BNXT_QPLIB_MAX_SRQ_CTX_ENTRY_SIZE 64 225 #define BNXT_QPLIB_MAX_CQ_CTX_ENTRY_SIZE 64 226 #define BNXT_QPLIB_MAX_MRW_CTX_ENTRY_SIZE 128 227 228 #define MAX_TQM_ALLOC_REQ 48 229 #define MAX_TQM_ALLOC_BLK_SIZE 8 230 struct bnxt_qplib_tqm_ctx { 231 struct bnxt_qplib_hwq pde; 232 u8 pde_level; /* Original level */ 233 struct bnxt_qplib_hwq qtbl[MAX_TQM_ALLOC_REQ]; 234 u8 qcount[MAX_TQM_ALLOC_REQ]; 235 }; 236 237 struct bnxt_qplib_ctx { 238 u32 qpc_count; 239 struct bnxt_qplib_hwq qpc_tbl; 240 u32 mrw_count; 241 struct bnxt_qplib_hwq mrw_tbl; 242 u32 srqc_count; 243 struct bnxt_qplib_hwq srqc_tbl; 244 u32 cq_count; 245 struct bnxt_qplib_hwq cq_tbl; 246 struct bnxt_qplib_hwq tim_tbl; 247 struct bnxt_qplib_tqm_ctx tqm_ctx; 248 struct bnxt_qplib_stats stats; 249 struct bnxt_qplib_vf_res vf_res; 250 u64 hwrm_intf_ver; 251 }; 252 253 struct bnxt_qplib_res { 254 struct pci_dev *pdev; 255 struct bnxt_qplib_chip_ctx *cctx; 256 struct net_device *netdev; 257 258 struct bnxt_qplib_rcfw *rcfw; 259 struct bnxt_qplib_pd_tbl pd_tbl; 260 struct bnxt_qplib_sgid_tbl sgid_tbl; 261 struct bnxt_qplib_pkey_tbl pkey_tbl; 262 struct bnxt_qplib_dpi_tbl dpi_tbl; 263 bool prio; 264 }; 265 266 static inline bool bnxt_qplib_is_chip_gen_p5(struct bnxt_qplib_chip_ctx *cctx) 267 { 268 return (cctx->chip_num == CHIP_NUM_57508 || 269 cctx->chip_num == CHIP_NUM_57504 || 270 cctx->chip_num == CHIP_NUM_57502); 271 } 272 273 static inline u8 bnxt_qplib_get_hwq_type(struct bnxt_qplib_res *res) 274 { 275 return bnxt_qplib_is_chip_gen_p5(res->cctx) ? 276 HWQ_TYPE_QUEUE : HWQ_TYPE_L2_CMPL; 277 } 278 279 static inline u8 bnxt_qplib_get_ring_type(struct bnxt_qplib_chip_ctx *cctx) 280 { 281 return bnxt_qplib_is_chip_gen_p5(cctx) ? 282 RING_ALLOC_REQ_RING_TYPE_NQ : 283 RING_ALLOC_REQ_RING_TYPE_ROCE_CMPL; 284 } 285 286 static inline u8 bnxt_qplib_base_pg_size(struct bnxt_qplib_hwq *hwq) 287 { 288 u8 pg_size = BNXT_QPLIB_HWRM_PG_SIZE_4K; 289 struct bnxt_qplib_pbl *pbl; 290 291 pbl = &hwq->pbl[PBL_LVL_0]; 292 switch (pbl->pg_size) { 293 case ROCE_PG_SIZE_4K: 294 pg_size = BNXT_QPLIB_HWRM_PG_SIZE_4K; 295 break; 296 case ROCE_PG_SIZE_8K: 297 pg_size = BNXT_QPLIB_HWRM_PG_SIZE_8K; 298 break; 299 case ROCE_PG_SIZE_64K: 300 pg_size = BNXT_QPLIB_HWRM_PG_SIZE_64K; 301 break; 302 case ROCE_PG_SIZE_2M: 303 pg_size = BNXT_QPLIB_HWRM_PG_SIZE_2M; 304 break; 305 case ROCE_PG_SIZE_8M: 306 pg_size = BNXT_QPLIB_HWRM_PG_SIZE_8M; 307 break; 308 case ROCE_PG_SIZE_1G: 309 pg_size = BNXT_QPLIB_HWRM_PG_SIZE_1G; 310 break; 311 default: 312 break; 313 } 314 315 return pg_size; 316 } 317 318 static inline void *bnxt_qplib_get_qe(struct bnxt_qplib_hwq *hwq, 319 u32 indx, u64 *pg) 320 { 321 u32 pg_num, pg_idx; 322 323 pg_num = (indx / hwq->qe_ppg); 324 pg_idx = (indx % hwq->qe_ppg); 325 if (pg) 326 *pg = (u64)&hwq->pbl_ptr[pg_num]; 327 return (void *)(hwq->pbl_ptr[pg_num] + hwq->element_size * pg_idx); 328 } 329 330 static inline void *bnxt_qplib_get_prod_qe(struct bnxt_qplib_hwq *hwq, u32 idx) 331 { 332 idx += hwq->prod; 333 if (idx >= hwq->depth) 334 idx -= hwq->depth; 335 return bnxt_qplib_get_qe(hwq, idx, NULL); 336 } 337 338 #define to_bnxt_qplib(ptr, type, member) \ 339 container_of(ptr, type, member) 340 341 struct bnxt_qplib_pd; 342 struct bnxt_qplib_dev_attr; 343 344 void bnxt_qplib_free_hwq(struct bnxt_qplib_res *res, 345 struct bnxt_qplib_hwq *hwq); 346 int bnxt_qplib_alloc_init_hwq(struct bnxt_qplib_hwq *hwq, 347 struct bnxt_qplib_hwq_attr *hwq_attr); 348 void bnxt_qplib_get_guid(u8 *dev_addr, u8 *guid); 349 int bnxt_qplib_alloc_pd(struct bnxt_qplib_pd_tbl *pd_tbl, 350 struct bnxt_qplib_pd *pd); 351 int bnxt_qplib_dealloc_pd(struct bnxt_qplib_res *res, 352 struct bnxt_qplib_pd_tbl *pd_tbl, 353 struct bnxt_qplib_pd *pd); 354 int bnxt_qplib_alloc_dpi(struct bnxt_qplib_dpi_tbl *dpit, 355 struct bnxt_qplib_dpi *dpi, 356 void *app); 357 int bnxt_qplib_dealloc_dpi(struct bnxt_qplib_res *res, 358 struct bnxt_qplib_dpi_tbl *dpi_tbl, 359 struct bnxt_qplib_dpi *dpi); 360 void bnxt_qplib_cleanup_res(struct bnxt_qplib_res *res); 361 int bnxt_qplib_init_res(struct bnxt_qplib_res *res); 362 void bnxt_qplib_free_res(struct bnxt_qplib_res *res); 363 int bnxt_qplib_alloc_res(struct bnxt_qplib_res *res, struct pci_dev *pdev, 364 struct net_device *netdev, 365 struct bnxt_qplib_dev_attr *dev_attr); 366 void bnxt_qplib_free_ctx(struct bnxt_qplib_res *res, 367 struct bnxt_qplib_ctx *ctx); 368 int bnxt_qplib_alloc_ctx(struct bnxt_qplib_res *res, 369 struct bnxt_qplib_ctx *ctx, 370 bool virt_fn, bool is_p5); 371 int bnxt_qplib_determine_atomics(struct pci_dev *dev); 372 373 static inline void bnxt_qplib_hwq_incr_prod(struct bnxt_qplib_hwq *hwq, u32 cnt) 374 { 375 hwq->prod = (hwq->prod + cnt) % hwq->depth; 376 } 377 378 static inline void bnxt_qplib_hwq_incr_cons(struct bnxt_qplib_hwq *hwq, 379 u32 cnt) 380 { 381 hwq->cons = (hwq->cons + cnt) % hwq->depth; 382 } 383 384 static inline void bnxt_qplib_ring_db32(struct bnxt_qplib_db_info *info, 385 bool arm) 386 { 387 u32 key; 388 389 key = info->hwq->cons & (info->hwq->max_elements - 1); 390 key |= (CMPL_DOORBELL_IDX_VALID | 391 (CMPL_DOORBELL_KEY_CMPL & CMPL_DOORBELL_KEY_MASK)); 392 if (!arm) 393 key |= CMPL_DOORBELL_MASK; 394 writel(key, info->db); 395 } 396 397 static inline void bnxt_qplib_ring_db(struct bnxt_qplib_db_info *info, 398 u32 type) 399 { 400 u64 key = 0; 401 402 key = (info->xid & DBC_DBC_XID_MASK) | DBC_DBC_PATH_ROCE | type; 403 key <<= 32; 404 key |= (info->hwq->cons & (info->hwq->max_elements - 1)) & 405 DBC_DBC_INDEX_MASK; 406 writeq(key, info->db); 407 } 408 409 static inline void bnxt_qplib_ring_prod_db(struct bnxt_qplib_db_info *info, 410 u32 type) 411 { 412 u64 key = 0; 413 414 key = (info->xid & DBC_DBC_XID_MASK) | DBC_DBC_PATH_ROCE | type; 415 key <<= 32; 416 key |= ((info->hwq->prod / info->max_slot)) & DBC_DBC_INDEX_MASK; 417 writeq(key, info->db); 418 } 419 420 static inline void bnxt_qplib_armen_db(struct bnxt_qplib_db_info *info, 421 u32 type) 422 { 423 u64 key = 0; 424 425 key = (info->xid & DBC_DBC_XID_MASK) | DBC_DBC_PATH_ROCE | type; 426 key <<= 32; 427 writeq(key, info->priv_db); 428 } 429 430 static inline void bnxt_qplib_srq_arm_db(struct bnxt_qplib_db_info *info, 431 u32 th) 432 { 433 u64 key = 0; 434 435 key = (info->xid & DBC_DBC_XID_MASK) | DBC_DBC_PATH_ROCE | th; 436 key <<= 32; 437 key |= th & DBC_DBC_INDEX_MASK; 438 writeq(key, info->priv_db); 439 } 440 441 static inline void bnxt_qplib_ring_nq_db(struct bnxt_qplib_db_info *info, 442 struct bnxt_qplib_chip_ctx *cctx, 443 bool arm) 444 { 445 u32 type; 446 447 type = arm ? DBC_DBC_TYPE_NQ_ARM : DBC_DBC_TYPE_NQ; 448 if (bnxt_qplib_is_chip_gen_p5(cctx)) 449 bnxt_qplib_ring_db(info, type); 450 else 451 bnxt_qplib_ring_db32(info, arm); 452 } 453 #endif /* __BNXT_QPLIB_RES_H__ */ 454