1 /* 2 * Broadcom NetXtreme-E RoCE driver. 3 * 4 * Copyright (c) 2016 - 2017, Broadcom. All rights reserved. The term 5 * Broadcom refers to Broadcom Limited and/or its subsidiaries. 6 * 7 * This software is available to you under a choice of one of two 8 * licenses. You may choose to be licensed under the terms of the GNU 9 * General Public License (GPL) Version 2, available from the file 10 * COPYING in the main directory of this source tree, or the 11 * BSD license below: 12 * 13 * Redistribution and use in source and binary forms, with or without 14 * modification, are permitted provided that the following conditions 15 * are met: 16 * 17 * 1. Redistributions of source code must retain the above copyright 18 * notice, this list of conditions and the following disclaimer. 19 * 2. Redistributions in binary form must reproduce the above copyright 20 * notice, this list of conditions and the following disclaimer in 21 * the documentation and/or other materials provided with the 22 * distribution. 23 * 24 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' 25 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, 26 * THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR 27 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS 28 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 29 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 30 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR 31 * BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, 32 * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE 33 * OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN 34 * IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 35 * 36 * Description: RDMA Controller HW interface (header) 37 */ 38 39 #ifndef __BNXT_QPLIB_RCFW_H__ 40 #define __BNXT_QPLIB_RCFW_H__ 41 42 #include "qplib_tlv.h" 43 44 #define RCFW_CMDQ_TRIG_VAL 1 45 #define RCFW_COMM_PCI_BAR_REGION 0 46 #define RCFW_COMM_CONS_PCI_BAR_REGION 2 47 #define RCFW_COMM_BASE_OFFSET 0x600 48 #define RCFW_PF_COMM_PROD_OFFSET 0xc 49 #define RCFW_VF_COMM_PROD_OFFSET 0xc 50 #define RCFW_COMM_TRIG_OFFSET 0x100 51 #define RCFW_COMM_SIZE 0x104 52 53 #define RCFW_DBR_PCI_BAR_REGION 2 54 #define RCFW_DBR_BASE_PAGE_SHIFT 12 55 56 /* Cmdq contains a fix number of a 16-Byte slots */ 57 struct bnxt_qplib_cmdqe { 58 u8 data[16]; 59 }; 60 61 #define BNXT_QPLIB_CMDQE_UNITS sizeof(struct bnxt_qplib_cmdqe) 62 63 static inline void bnxt_qplib_rcfw_cmd_prep(struct cmdq_base *req, 64 u8 opcode, u8 cmd_size) 65 { 66 req->opcode = opcode; 67 req->cmd_size = cmd_size; 68 } 69 70 #define RCFW_CMD_WAIT_TIME_MS 20000 /* 20 Seconds timeout */ 71 72 /* CMDQ elements */ 73 #define BNXT_QPLIB_CMDQE_MAX_CNT_256 256 74 #define BNXT_QPLIB_CMDQE_MAX_CNT_8192 8192 75 #define BNXT_QPLIB_CMDQE_BYTES(depth) ((depth) * BNXT_QPLIB_CMDQE_UNITS) 76 77 static inline u32 bnxt_qplib_cmdqe_npages(u32 depth) 78 { 79 u32 npages; 80 81 npages = BNXT_QPLIB_CMDQE_BYTES(depth) / PAGE_SIZE; 82 if (BNXT_QPLIB_CMDQE_BYTES(depth) % PAGE_SIZE) 83 npages++; 84 return npages; 85 } 86 87 static inline u32 bnxt_qplib_cmdqe_page_size(u32 depth) 88 { 89 return (bnxt_qplib_cmdqe_npages(depth) * PAGE_SIZE); 90 } 91 92 static inline u32 bnxt_qplib_set_cmd_slots(struct cmdq_base *req) 93 { 94 u32 cmd_byte = 0; 95 96 if (HAS_TLV_HEADER(req)) { 97 struct roce_tlv *tlv_req = (struct roce_tlv *)req; 98 99 cmd_byte = tlv_req->total_size * BNXT_QPLIB_CMDQE_UNITS; 100 } else { 101 cmd_byte = req->cmd_size; 102 req->cmd_size = (req->cmd_size + BNXT_QPLIB_CMDQE_UNITS - 1) / 103 BNXT_QPLIB_CMDQE_UNITS; 104 } 105 106 return cmd_byte; 107 } 108 109 #define RCFW_MAX_COOKIE_VALUE 0x7FFF 110 #define RCFW_CMD_IS_BLOCKING 0x8000 111 #define RCFW_BLOCKED_CMD_WAIT_COUNT 20000000UL /* 20 sec */ 112 113 #define HWRM_VERSION_RCFW_CMDQ_DEPTH_CHECK 0x1000900020011ULL 114 115 /* Crsq buf is 1024-Byte */ 116 struct bnxt_qplib_crsbe { 117 u8 data[1024]; 118 }; 119 120 /* CREQ */ 121 /* Allocate 1 per QP for async error notification for now */ 122 #define BNXT_QPLIB_CREQE_MAX_CNT (64 * 1024) 123 #define BNXT_QPLIB_CREQE_UNITS 16 /* 16-Bytes per prod unit */ 124 #define CREQ_CMP_VALID(hdr, raw_cons, cp_bit) \ 125 (!!((hdr)->v & CREQ_BASE_V) == \ 126 !((raw_cons) & (cp_bit))) 127 #define CREQ_ENTRY_POLL_BUDGET 0x100 128 129 /* HWQ */ 130 typedef int (*aeq_handler_t)(struct bnxt_qplib_rcfw *, void *, void *); 131 132 struct bnxt_qplib_crsqe { 133 struct creq_qp_event *resp; 134 u32 req_size; 135 }; 136 137 struct bnxt_qplib_rcfw_sbuf { 138 void *sb; 139 dma_addr_t dma_addr; 140 u32 size; 141 }; 142 143 struct bnxt_qplib_qp_node { 144 u32 qp_id; /* QP id */ 145 void *qp_handle; /* ptr to qplib_qp */ 146 }; 147 148 #define BNXT_QPLIB_OOS_COUNT_MASK 0xFFFFFFFF 149 150 #define FIRMWARE_INITIALIZED_FLAG (0) 151 #define FIRMWARE_FIRST_FLAG (31) 152 #define FIRMWARE_TIMED_OUT (3) 153 #define ERR_DEVICE_DETACHED (4) 154 155 struct bnxt_qplib_cmdq_mbox { 156 struct bnxt_qplib_reg_desc reg; 157 void __iomem *prod; 158 void __iomem *db; 159 }; 160 161 struct bnxt_qplib_cmdq_ctx { 162 struct bnxt_qplib_hwq hwq; 163 struct bnxt_qplib_cmdq_mbox cmdq_mbox; 164 wait_queue_head_t waitq; 165 unsigned long flags; 166 unsigned long *cmdq_bitmap; 167 u32 seq_num; 168 }; 169 170 struct bnxt_qplib_creq_db { 171 struct bnxt_qplib_reg_desc reg; 172 struct bnxt_qplib_db_info dbinfo; 173 }; 174 175 struct bnxt_qplib_creq_stat { 176 u64 creq_qp_event_processed; 177 u64 creq_func_event_processed; 178 }; 179 180 struct bnxt_qplib_creq_ctx { 181 struct bnxt_qplib_hwq hwq; 182 struct bnxt_qplib_creq_db creq_db; 183 struct bnxt_qplib_creq_stat stats; 184 struct tasklet_struct creq_tasklet; 185 aeq_handler_t aeq_handler; 186 u16 ring_id; 187 int msix_vec; 188 bool requested; /*irq handler installed */ 189 }; 190 191 /* RCFW Communication Channels */ 192 struct bnxt_qplib_rcfw { 193 struct pci_dev *pdev; 194 struct bnxt_qplib_res *res; 195 struct bnxt_qplib_cmdq_ctx cmdq; 196 struct bnxt_qplib_creq_ctx creq; 197 struct bnxt_qplib_crsqe *crsqe_tbl; 198 int qp_tbl_size; 199 struct bnxt_qplib_qp_node *qp_tbl; 200 u64 oos_prev; 201 u32 init_oos_stats; 202 u32 cmdq_depth; 203 }; 204 205 struct bnxt_qplib_cmdqmsg { 206 struct cmdq_base *req; 207 struct creq_base *resp; 208 void *sb; 209 u32 req_sz; 210 u32 res_sz; 211 u8 block; 212 }; 213 214 static inline void bnxt_qplib_fill_cmdqmsg(struct bnxt_qplib_cmdqmsg *msg, 215 void *req, void *resp, void *sb, 216 u32 req_sz, u32 res_sz, u8 block) 217 { 218 msg->req = req; 219 msg->resp = resp; 220 msg->sb = sb; 221 msg->req_sz = req_sz; 222 msg->res_sz = res_sz; 223 msg->block = block; 224 } 225 226 void bnxt_qplib_free_rcfw_channel(struct bnxt_qplib_rcfw *rcfw); 227 int bnxt_qplib_alloc_rcfw_channel(struct bnxt_qplib_res *res, 228 struct bnxt_qplib_rcfw *rcfw, 229 struct bnxt_qplib_ctx *ctx, 230 int qp_tbl_sz); 231 void bnxt_qplib_rcfw_stop_irq(struct bnxt_qplib_rcfw *rcfw, bool kill); 232 void bnxt_qplib_disable_rcfw_channel(struct bnxt_qplib_rcfw *rcfw); 233 int bnxt_qplib_rcfw_start_irq(struct bnxt_qplib_rcfw *rcfw, int msix_vector, 234 bool need_init); 235 int bnxt_qplib_enable_rcfw_channel(struct bnxt_qplib_rcfw *rcfw, 236 int msix_vector, 237 int cp_bar_reg_off, int virt_fn, 238 aeq_handler_t aeq_handler); 239 240 struct bnxt_qplib_rcfw_sbuf *bnxt_qplib_rcfw_alloc_sbuf( 241 struct bnxt_qplib_rcfw *rcfw, 242 u32 size); 243 void bnxt_qplib_rcfw_free_sbuf(struct bnxt_qplib_rcfw *rcfw, 244 struct bnxt_qplib_rcfw_sbuf *sbuf); 245 int bnxt_qplib_rcfw_send_message(struct bnxt_qplib_rcfw *rcfw, 246 struct bnxt_qplib_cmdqmsg *msg); 247 248 int bnxt_qplib_deinit_rcfw(struct bnxt_qplib_rcfw *rcfw); 249 int bnxt_qplib_init_rcfw(struct bnxt_qplib_rcfw *rcfw, 250 struct bnxt_qplib_ctx *ctx, int is_virtfn); 251 void bnxt_qplib_mark_qp_error(void *qp_handle); 252 static inline u32 map_qp_id_to_tbl_indx(u32 qid, struct bnxt_qplib_rcfw *rcfw) 253 { 254 /* Last index of the qp_tbl is for QP1 ie. qp_tbl_size - 1*/ 255 return (qid == 1) ? rcfw->qp_tbl_size - 1 : qid % rcfw->qp_tbl_size - 2; 256 } 257 #endif /* __BNXT_QPLIB_RCFW_H__ */ 258