1 /* 2 * Broadcom NetXtreme-E RoCE driver. 3 * 4 * Copyright (c) 2016 - 2017, Broadcom. All rights reserved. The term 5 * Broadcom refers to Broadcom Limited and/or its subsidiaries. 6 * 7 * This software is available to you under a choice of one of two 8 * licenses. You may choose to be licensed under the terms of the GNU 9 * General Public License (GPL) Version 2, available from the file 10 * COPYING in the main directory of this source tree, or the 11 * BSD license below: 12 * 13 * Redistribution and use in source and binary forms, with or without 14 * modification, are permitted provided that the following conditions 15 * are met: 16 * 17 * 1. Redistributions of source code must retain the above copyright 18 * notice, this list of conditions and the following disclaimer. 19 * 2. Redistributions in binary form must reproduce the above copyright 20 * notice, this list of conditions and the following disclaimer in 21 * the documentation and/or other materials provided with the 22 * distribution. 23 * 24 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' 25 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, 26 * THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR 27 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS 28 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 29 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 30 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR 31 * BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, 32 * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE 33 * OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN 34 * IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 35 * 36 * Description: RDMA Controller HW interface 37 */ 38 39 #define dev_fmt(fmt) "QPLIB: " fmt 40 41 #include <linux/interrupt.h> 42 #include <linux/spinlock.h> 43 #include <linux/pci.h> 44 #include <linux/prefetch.h> 45 #include <linux/delay.h> 46 47 #include "roce_hsi.h" 48 #include "qplib_res.h" 49 #include "qplib_rcfw.h" 50 #include "qplib_sp.h" 51 #include "qplib_fp.h" 52 53 static void bnxt_qplib_service_creq(struct tasklet_struct *t); 54 55 /* Hardware communication channel */ 56 static int __wait_for_resp(struct bnxt_qplib_rcfw *rcfw, u16 cookie) 57 { 58 struct bnxt_qplib_cmdq_ctx *cmdq; 59 u16 cbit; 60 int rc; 61 62 cmdq = &rcfw->cmdq; 63 cbit = cookie % rcfw->cmdq_depth; 64 rc = wait_event_timeout(cmdq->waitq, 65 !test_bit(cbit, cmdq->cmdq_bitmap), 66 msecs_to_jiffies(RCFW_CMD_WAIT_TIME_MS)); 67 return rc ? 0 : -ETIMEDOUT; 68 }; 69 70 static int __block_for_resp(struct bnxt_qplib_rcfw *rcfw, u16 cookie) 71 { 72 u32 count = RCFW_BLOCKED_CMD_WAIT_COUNT; 73 struct bnxt_qplib_cmdq_ctx *cmdq; 74 u16 cbit; 75 76 cmdq = &rcfw->cmdq; 77 cbit = cookie % rcfw->cmdq_depth; 78 if (!test_bit(cbit, cmdq->cmdq_bitmap)) 79 goto done; 80 do { 81 mdelay(1); /* 1m sec */ 82 bnxt_qplib_service_creq(&rcfw->creq.creq_tasklet); 83 } while (test_bit(cbit, cmdq->cmdq_bitmap) && --count); 84 done: 85 return count ? 0 : -ETIMEDOUT; 86 }; 87 88 static int __send_message(struct bnxt_qplib_rcfw *rcfw, struct cmdq_base *req, 89 struct creq_base *resp, void *sb, u8 is_block) 90 { 91 struct bnxt_qplib_cmdq_ctx *cmdq = &rcfw->cmdq; 92 struct bnxt_qplib_hwq *hwq = &cmdq->hwq; 93 struct bnxt_qplib_crsqe *crsqe; 94 struct bnxt_qplib_cmdqe *cmdqe; 95 u32 sw_prod, cmdq_prod; 96 struct pci_dev *pdev; 97 unsigned long flags; 98 u32 size, opcode; 99 u16 cookie, cbit; 100 u8 *preq; 101 102 pdev = rcfw->pdev; 103 104 opcode = req->opcode; 105 if (!test_bit(FIRMWARE_INITIALIZED_FLAG, &cmdq->flags) && 106 (opcode != CMDQ_BASE_OPCODE_QUERY_FUNC && 107 opcode != CMDQ_BASE_OPCODE_INITIALIZE_FW && 108 opcode != CMDQ_BASE_OPCODE_QUERY_VERSION)) { 109 dev_err(&pdev->dev, 110 "RCFW not initialized, reject opcode 0x%x\n", opcode); 111 return -EINVAL; 112 } 113 114 if (test_bit(FIRMWARE_INITIALIZED_FLAG, &cmdq->flags) && 115 opcode == CMDQ_BASE_OPCODE_INITIALIZE_FW) { 116 dev_err(&pdev->dev, "RCFW already initialized!\n"); 117 return -EINVAL; 118 } 119 120 if (test_bit(FIRMWARE_TIMED_OUT, &cmdq->flags)) 121 return -ETIMEDOUT; 122 123 /* Cmdq are in 16-byte units, each request can consume 1 or more 124 * cmdqe 125 */ 126 spin_lock_irqsave(&hwq->lock, flags); 127 if (req->cmd_size >= HWQ_FREE_SLOTS(hwq)) { 128 dev_err(&pdev->dev, "RCFW: CMDQ is full!\n"); 129 spin_unlock_irqrestore(&hwq->lock, flags); 130 return -EAGAIN; 131 } 132 133 134 cookie = cmdq->seq_num & RCFW_MAX_COOKIE_VALUE; 135 cbit = cookie % rcfw->cmdq_depth; 136 if (is_block) 137 cookie |= RCFW_CMD_IS_BLOCKING; 138 139 set_bit(cbit, cmdq->cmdq_bitmap); 140 req->cookie = cpu_to_le16(cookie); 141 crsqe = &rcfw->crsqe_tbl[cbit]; 142 if (crsqe->resp) { 143 spin_unlock_irqrestore(&hwq->lock, flags); 144 return -EBUSY; 145 } 146 147 size = req->cmd_size; 148 /* change the cmd_size to the number of 16byte cmdq unit. 149 * req->cmd_size is modified here 150 */ 151 bnxt_qplib_set_cmd_slots(req); 152 153 memset(resp, 0, sizeof(*resp)); 154 crsqe->resp = (struct creq_qp_event *)resp; 155 crsqe->resp->cookie = req->cookie; 156 crsqe->req_size = req->cmd_size; 157 if (req->resp_size && sb) { 158 struct bnxt_qplib_rcfw_sbuf *sbuf = sb; 159 160 req->resp_addr = cpu_to_le64(sbuf->dma_addr); 161 req->resp_size = (sbuf->size + BNXT_QPLIB_CMDQE_UNITS - 1) / 162 BNXT_QPLIB_CMDQE_UNITS; 163 } 164 165 preq = (u8 *)req; 166 do { 167 /* Locate the next cmdq slot */ 168 sw_prod = HWQ_CMP(hwq->prod, hwq); 169 cmdqe = bnxt_qplib_get_qe(hwq, sw_prod, NULL); 170 if (!cmdqe) { 171 dev_err(&pdev->dev, 172 "RCFW request failed with no cmdqe!\n"); 173 goto done; 174 } 175 /* Copy a segment of the req cmd to the cmdq */ 176 memset(cmdqe, 0, sizeof(*cmdqe)); 177 memcpy(cmdqe, preq, min_t(u32, size, sizeof(*cmdqe))); 178 preq += min_t(u32, size, sizeof(*cmdqe)); 179 size -= min_t(u32, size, sizeof(*cmdqe)); 180 hwq->prod++; 181 } while (size > 0); 182 cmdq->seq_num++; 183 184 cmdq_prod = hwq->prod; 185 if (test_bit(FIRMWARE_FIRST_FLAG, &cmdq->flags)) { 186 /* The very first doorbell write 187 * is required to set this flag 188 * which prompts the FW to reset 189 * its internal pointers 190 */ 191 cmdq_prod |= BIT(FIRMWARE_FIRST_FLAG); 192 clear_bit(FIRMWARE_FIRST_FLAG, &cmdq->flags); 193 } 194 195 /* ring CMDQ DB */ 196 wmb(); 197 writel(cmdq_prod, cmdq->cmdq_mbox.prod); 198 writel(RCFW_CMDQ_TRIG_VAL, cmdq->cmdq_mbox.db); 199 done: 200 spin_unlock_irqrestore(&hwq->lock, flags); 201 /* Return the CREQ response pointer */ 202 return 0; 203 } 204 205 int bnxt_qplib_rcfw_send_message(struct bnxt_qplib_rcfw *rcfw, 206 struct cmdq_base *req, 207 struct creq_base *resp, 208 void *sb, u8 is_block) 209 { 210 struct creq_qp_event *evnt = (struct creq_qp_event *)resp; 211 u16 cookie; 212 u8 opcode, retry_cnt = 0xFF; 213 int rc = 0; 214 215 do { 216 opcode = req->opcode; 217 rc = __send_message(rcfw, req, resp, sb, is_block); 218 cookie = le16_to_cpu(req->cookie) & RCFW_MAX_COOKIE_VALUE; 219 if (!rc) 220 break; 221 222 if (!retry_cnt || (rc != -EAGAIN && rc != -EBUSY)) { 223 /* send failed */ 224 dev_err(&rcfw->pdev->dev, "cmdq[%#x]=%#x send failed\n", 225 cookie, opcode); 226 return rc; 227 } 228 is_block ? mdelay(1) : usleep_range(500, 1000); 229 230 } while (retry_cnt--); 231 232 if (is_block) 233 rc = __block_for_resp(rcfw, cookie); 234 else 235 rc = __wait_for_resp(rcfw, cookie); 236 if (rc) { 237 /* timed out */ 238 dev_err(&rcfw->pdev->dev, "cmdq[%#x]=%#x timedout (%d)msec\n", 239 cookie, opcode, RCFW_CMD_WAIT_TIME_MS); 240 set_bit(FIRMWARE_TIMED_OUT, &rcfw->cmdq.flags); 241 return rc; 242 } 243 244 if (evnt->status) { 245 /* failed with status */ 246 dev_err(&rcfw->pdev->dev, "cmdq[%#x]=%#x status %#x\n", 247 cookie, opcode, evnt->status); 248 rc = -EFAULT; 249 } 250 251 return rc; 252 } 253 /* Completions */ 254 static int bnxt_qplib_process_func_event(struct bnxt_qplib_rcfw *rcfw, 255 struct creq_func_event *func_event) 256 { 257 int rc; 258 259 switch (func_event->event) { 260 case CREQ_FUNC_EVENT_EVENT_TX_WQE_ERROR: 261 break; 262 case CREQ_FUNC_EVENT_EVENT_TX_DATA_ERROR: 263 break; 264 case CREQ_FUNC_EVENT_EVENT_RX_WQE_ERROR: 265 break; 266 case CREQ_FUNC_EVENT_EVENT_RX_DATA_ERROR: 267 break; 268 case CREQ_FUNC_EVENT_EVENT_CQ_ERROR: 269 break; 270 case CREQ_FUNC_EVENT_EVENT_TQM_ERROR: 271 break; 272 case CREQ_FUNC_EVENT_EVENT_CFCQ_ERROR: 273 break; 274 case CREQ_FUNC_EVENT_EVENT_CFCS_ERROR: 275 /* SRQ ctx error, call srq_handler?? 276 * But there's no SRQ handle! 277 */ 278 break; 279 case CREQ_FUNC_EVENT_EVENT_CFCC_ERROR: 280 break; 281 case CREQ_FUNC_EVENT_EVENT_CFCM_ERROR: 282 break; 283 case CREQ_FUNC_EVENT_EVENT_TIM_ERROR: 284 break; 285 case CREQ_FUNC_EVENT_EVENT_VF_COMM_REQUEST: 286 break; 287 case CREQ_FUNC_EVENT_EVENT_RESOURCE_EXHAUSTED: 288 break; 289 default: 290 return -EINVAL; 291 } 292 293 rc = rcfw->creq.aeq_handler(rcfw, (void *)func_event, NULL); 294 return rc; 295 } 296 297 static int bnxt_qplib_process_qp_event(struct bnxt_qplib_rcfw *rcfw, 298 struct creq_qp_event *qp_event) 299 { 300 struct creq_qp_error_notification *err_event; 301 struct bnxt_qplib_hwq *hwq = &rcfw->cmdq.hwq; 302 struct bnxt_qplib_crsqe *crsqe; 303 struct bnxt_qplib_qp *qp; 304 u16 cbit, blocked = 0; 305 struct pci_dev *pdev; 306 unsigned long flags; 307 __le16 mcookie; 308 u16 cookie; 309 int rc = 0; 310 u32 qp_id, tbl_indx; 311 312 pdev = rcfw->pdev; 313 switch (qp_event->event) { 314 case CREQ_QP_EVENT_EVENT_QP_ERROR_NOTIFICATION: 315 err_event = (struct creq_qp_error_notification *)qp_event; 316 qp_id = le32_to_cpu(err_event->xid); 317 tbl_indx = map_qp_id_to_tbl_indx(qp_id, rcfw); 318 qp = rcfw->qp_tbl[tbl_indx].qp_handle; 319 dev_dbg(&pdev->dev, "Received QP error notification\n"); 320 dev_dbg(&pdev->dev, 321 "qpid 0x%x, req_err=0x%x, resp_err=0x%x\n", 322 qp_id, err_event->req_err_state_reason, 323 err_event->res_err_state_reason); 324 if (!qp) 325 break; 326 bnxt_qplib_mark_qp_error(qp); 327 rc = rcfw->creq.aeq_handler(rcfw, qp_event, qp); 328 break; 329 default: 330 /* 331 * Command Response 332 * cmdq->lock needs to be acquired to synchronie 333 * the command send and completion reaping. This function 334 * is always called with creq->lock held. Using 335 * the nested variant of spin_lock. 336 * 337 */ 338 339 spin_lock_irqsave_nested(&hwq->lock, flags, 340 SINGLE_DEPTH_NESTING); 341 cookie = le16_to_cpu(qp_event->cookie); 342 mcookie = qp_event->cookie; 343 blocked = cookie & RCFW_CMD_IS_BLOCKING; 344 cookie &= RCFW_MAX_COOKIE_VALUE; 345 cbit = cookie % rcfw->cmdq_depth; 346 crsqe = &rcfw->crsqe_tbl[cbit]; 347 if (crsqe->resp && 348 crsqe->resp->cookie == mcookie) { 349 memcpy(crsqe->resp, qp_event, sizeof(*qp_event)); 350 crsqe->resp = NULL; 351 } else { 352 if (crsqe->resp && crsqe->resp->cookie) 353 dev_err(&pdev->dev, 354 "CMD %s cookie sent=%#x, recd=%#x\n", 355 crsqe->resp ? "mismatch" : "collision", 356 crsqe->resp ? crsqe->resp->cookie : 0, 357 mcookie); 358 } 359 if (!test_and_clear_bit(cbit, rcfw->cmdq.cmdq_bitmap)) 360 dev_warn(&pdev->dev, 361 "CMD bit %d was not requested\n", cbit); 362 hwq->cons += crsqe->req_size; 363 crsqe->req_size = 0; 364 365 if (!blocked) 366 wake_up(&rcfw->cmdq.waitq); 367 spin_unlock_irqrestore(&hwq->lock, flags); 368 } 369 return rc; 370 } 371 372 /* SP - CREQ Completion handlers */ 373 static void bnxt_qplib_service_creq(struct tasklet_struct *t) 374 { 375 struct bnxt_qplib_rcfw *rcfw = from_tasklet(rcfw, t, creq.creq_tasklet); 376 struct bnxt_qplib_creq_ctx *creq = &rcfw->creq; 377 u32 type, budget = CREQ_ENTRY_POLL_BUDGET; 378 struct bnxt_qplib_hwq *hwq = &creq->hwq; 379 struct creq_base *creqe; 380 u32 sw_cons, raw_cons; 381 unsigned long flags; 382 383 /* Service the CREQ until budget is over */ 384 spin_lock_irqsave(&hwq->lock, flags); 385 raw_cons = hwq->cons; 386 while (budget > 0) { 387 sw_cons = HWQ_CMP(raw_cons, hwq); 388 creqe = bnxt_qplib_get_qe(hwq, sw_cons, NULL); 389 if (!CREQ_CMP_VALID(creqe, raw_cons, hwq->max_elements)) 390 break; 391 /* The valid test of the entry must be done first before 392 * reading any further. 393 */ 394 dma_rmb(); 395 396 type = creqe->type & CREQ_BASE_TYPE_MASK; 397 switch (type) { 398 case CREQ_BASE_TYPE_QP_EVENT: 399 bnxt_qplib_process_qp_event 400 (rcfw, (struct creq_qp_event *)creqe); 401 creq->stats.creq_qp_event_processed++; 402 break; 403 case CREQ_BASE_TYPE_FUNC_EVENT: 404 if (!bnxt_qplib_process_func_event 405 (rcfw, (struct creq_func_event *)creqe)) 406 creq->stats.creq_func_event_processed++; 407 else 408 dev_warn(&rcfw->pdev->dev, 409 "aeqe:%#x Not handled\n", type); 410 break; 411 default: 412 if (type != ASYNC_EVENT_CMPL_TYPE_HWRM_ASYNC_EVENT) 413 dev_warn(&rcfw->pdev->dev, 414 "creqe with event 0x%x not handled\n", 415 type); 416 break; 417 } 418 raw_cons++; 419 budget--; 420 } 421 422 if (hwq->cons != raw_cons) { 423 hwq->cons = raw_cons; 424 bnxt_qplib_ring_nq_db(&creq->creq_db.dbinfo, 425 rcfw->res->cctx, true); 426 } 427 spin_unlock_irqrestore(&hwq->lock, flags); 428 } 429 430 static irqreturn_t bnxt_qplib_creq_irq(int irq, void *dev_instance) 431 { 432 struct bnxt_qplib_rcfw *rcfw = dev_instance; 433 struct bnxt_qplib_creq_ctx *creq; 434 struct bnxt_qplib_hwq *hwq; 435 u32 sw_cons; 436 437 creq = &rcfw->creq; 438 hwq = &creq->hwq; 439 /* Prefetch the CREQ element */ 440 sw_cons = HWQ_CMP(hwq->cons, hwq); 441 prefetch(bnxt_qplib_get_qe(hwq, sw_cons, NULL)); 442 443 tasklet_schedule(&creq->creq_tasklet); 444 445 return IRQ_HANDLED; 446 } 447 448 /* RCFW */ 449 int bnxt_qplib_deinit_rcfw(struct bnxt_qplib_rcfw *rcfw) 450 { 451 struct cmdq_deinitialize_fw req; 452 struct creq_deinitialize_fw_resp resp; 453 u16 cmd_flags = 0; 454 int rc; 455 456 RCFW_CMD_PREP(req, DEINITIALIZE_FW, cmd_flags); 457 rc = bnxt_qplib_rcfw_send_message(rcfw, (void *)&req, (void *)&resp, 458 NULL, 0); 459 if (rc) 460 return rc; 461 462 clear_bit(FIRMWARE_INITIALIZED_FLAG, &rcfw->cmdq.flags); 463 return 0; 464 } 465 466 int bnxt_qplib_init_rcfw(struct bnxt_qplib_rcfw *rcfw, 467 struct bnxt_qplib_ctx *ctx, int is_virtfn) 468 { 469 struct creq_initialize_fw_resp resp; 470 struct cmdq_initialize_fw req; 471 u16 cmd_flags = 0; 472 u8 pgsz, lvl; 473 int rc; 474 475 RCFW_CMD_PREP(req, INITIALIZE_FW, cmd_flags); 476 /* Supply (log-base-2-of-host-page-size - base-page-shift) 477 * to bono to adjust the doorbell page sizes. 478 */ 479 req.log2_dbr_pg_size = cpu_to_le16(PAGE_SHIFT - 480 RCFW_DBR_BASE_PAGE_SHIFT); 481 /* 482 * Gen P5 devices doesn't require this allocation 483 * as the L2 driver does the same for RoCE also. 484 * Also, VFs need not setup the HW context area, PF 485 * shall setup this area for VF. Skipping the 486 * HW programming 487 */ 488 if (is_virtfn) 489 goto skip_ctx_setup; 490 if (bnxt_qplib_is_chip_gen_p5(rcfw->res->cctx)) 491 goto config_vf_res; 492 493 lvl = ctx->qpc_tbl.level; 494 pgsz = bnxt_qplib_base_pg_size(&ctx->qpc_tbl); 495 req.qpc_pg_size_qpc_lvl = (pgsz << CMDQ_INITIALIZE_FW_QPC_PG_SIZE_SFT) | 496 lvl; 497 lvl = ctx->mrw_tbl.level; 498 pgsz = bnxt_qplib_base_pg_size(&ctx->mrw_tbl); 499 req.mrw_pg_size_mrw_lvl = (pgsz << CMDQ_INITIALIZE_FW_QPC_PG_SIZE_SFT) | 500 lvl; 501 lvl = ctx->srqc_tbl.level; 502 pgsz = bnxt_qplib_base_pg_size(&ctx->srqc_tbl); 503 req.srq_pg_size_srq_lvl = (pgsz << CMDQ_INITIALIZE_FW_QPC_PG_SIZE_SFT) | 504 lvl; 505 lvl = ctx->cq_tbl.level; 506 pgsz = bnxt_qplib_base_pg_size(&ctx->cq_tbl); 507 req.cq_pg_size_cq_lvl = (pgsz << CMDQ_INITIALIZE_FW_QPC_PG_SIZE_SFT) | 508 lvl; 509 lvl = ctx->tim_tbl.level; 510 pgsz = bnxt_qplib_base_pg_size(&ctx->tim_tbl); 511 req.tim_pg_size_tim_lvl = (pgsz << CMDQ_INITIALIZE_FW_QPC_PG_SIZE_SFT) | 512 lvl; 513 lvl = ctx->tqm_ctx.pde.level; 514 pgsz = bnxt_qplib_base_pg_size(&ctx->tqm_ctx.pde); 515 req.tqm_pg_size_tqm_lvl = (pgsz << CMDQ_INITIALIZE_FW_QPC_PG_SIZE_SFT) | 516 lvl; 517 req.qpc_page_dir = 518 cpu_to_le64(ctx->qpc_tbl.pbl[PBL_LVL_0].pg_map_arr[0]); 519 req.mrw_page_dir = 520 cpu_to_le64(ctx->mrw_tbl.pbl[PBL_LVL_0].pg_map_arr[0]); 521 req.srq_page_dir = 522 cpu_to_le64(ctx->srqc_tbl.pbl[PBL_LVL_0].pg_map_arr[0]); 523 req.cq_page_dir = 524 cpu_to_le64(ctx->cq_tbl.pbl[PBL_LVL_0].pg_map_arr[0]); 525 req.tim_page_dir = 526 cpu_to_le64(ctx->tim_tbl.pbl[PBL_LVL_0].pg_map_arr[0]); 527 req.tqm_page_dir = 528 cpu_to_le64(ctx->tqm_ctx.pde.pbl[PBL_LVL_0].pg_map_arr[0]); 529 530 req.number_of_qp = cpu_to_le32(ctx->qpc_tbl.max_elements); 531 req.number_of_mrw = cpu_to_le32(ctx->mrw_tbl.max_elements); 532 req.number_of_srq = cpu_to_le32(ctx->srqc_tbl.max_elements); 533 req.number_of_cq = cpu_to_le32(ctx->cq_tbl.max_elements); 534 535 config_vf_res: 536 req.max_qp_per_vf = cpu_to_le32(ctx->vf_res.max_qp_per_vf); 537 req.max_mrw_per_vf = cpu_to_le32(ctx->vf_res.max_mrw_per_vf); 538 req.max_srq_per_vf = cpu_to_le32(ctx->vf_res.max_srq_per_vf); 539 req.max_cq_per_vf = cpu_to_le32(ctx->vf_res.max_cq_per_vf); 540 req.max_gid_per_vf = cpu_to_le32(ctx->vf_res.max_gid_per_vf); 541 542 skip_ctx_setup: 543 req.stat_ctx_id = cpu_to_le32(ctx->stats.fw_id); 544 rc = bnxt_qplib_rcfw_send_message(rcfw, (void *)&req, (void *)&resp, 545 NULL, 0); 546 if (rc) 547 return rc; 548 set_bit(FIRMWARE_INITIALIZED_FLAG, &rcfw->cmdq.flags); 549 return 0; 550 } 551 552 void bnxt_qplib_free_rcfw_channel(struct bnxt_qplib_rcfw *rcfw) 553 { 554 kfree(rcfw->cmdq.cmdq_bitmap); 555 kfree(rcfw->qp_tbl); 556 kfree(rcfw->crsqe_tbl); 557 bnxt_qplib_free_hwq(rcfw->res, &rcfw->cmdq.hwq); 558 bnxt_qplib_free_hwq(rcfw->res, &rcfw->creq.hwq); 559 rcfw->pdev = NULL; 560 } 561 562 int bnxt_qplib_alloc_rcfw_channel(struct bnxt_qplib_res *res, 563 struct bnxt_qplib_rcfw *rcfw, 564 struct bnxt_qplib_ctx *ctx, 565 int qp_tbl_sz) 566 { 567 struct bnxt_qplib_hwq_attr hwq_attr = {}; 568 struct bnxt_qplib_sg_info sginfo = {}; 569 struct bnxt_qplib_cmdq_ctx *cmdq; 570 struct bnxt_qplib_creq_ctx *creq; 571 u32 bmap_size = 0; 572 573 rcfw->pdev = res->pdev; 574 cmdq = &rcfw->cmdq; 575 creq = &rcfw->creq; 576 rcfw->res = res; 577 578 sginfo.pgsize = PAGE_SIZE; 579 sginfo.pgshft = PAGE_SHIFT; 580 581 hwq_attr.sginfo = &sginfo; 582 hwq_attr.res = rcfw->res; 583 hwq_attr.depth = BNXT_QPLIB_CREQE_MAX_CNT; 584 hwq_attr.stride = BNXT_QPLIB_CREQE_UNITS; 585 hwq_attr.type = bnxt_qplib_get_hwq_type(res); 586 587 if (bnxt_qplib_alloc_init_hwq(&creq->hwq, &hwq_attr)) { 588 dev_err(&rcfw->pdev->dev, 589 "HW channel CREQ allocation failed\n"); 590 goto fail; 591 } 592 if (ctx->hwrm_intf_ver < HWRM_VERSION_RCFW_CMDQ_DEPTH_CHECK) 593 rcfw->cmdq_depth = BNXT_QPLIB_CMDQE_MAX_CNT_256; 594 else 595 rcfw->cmdq_depth = BNXT_QPLIB_CMDQE_MAX_CNT_8192; 596 597 sginfo.pgsize = bnxt_qplib_cmdqe_page_size(rcfw->cmdq_depth); 598 hwq_attr.depth = rcfw->cmdq_depth; 599 hwq_attr.stride = BNXT_QPLIB_CMDQE_UNITS; 600 hwq_attr.type = HWQ_TYPE_CTX; 601 if (bnxt_qplib_alloc_init_hwq(&cmdq->hwq, &hwq_attr)) { 602 dev_err(&rcfw->pdev->dev, 603 "HW channel CMDQ allocation failed\n"); 604 goto fail; 605 } 606 607 rcfw->crsqe_tbl = kcalloc(cmdq->hwq.max_elements, 608 sizeof(*rcfw->crsqe_tbl), GFP_KERNEL); 609 if (!rcfw->crsqe_tbl) 610 goto fail; 611 612 bmap_size = BITS_TO_LONGS(rcfw->cmdq_depth) * sizeof(unsigned long); 613 cmdq->cmdq_bitmap = kzalloc(bmap_size, GFP_KERNEL); 614 if (!cmdq->cmdq_bitmap) 615 goto fail; 616 617 cmdq->bmap_size = bmap_size; 618 619 /* Allocate one extra to hold the QP1 entries */ 620 rcfw->qp_tbl_size = qp_tbl_sz + 1; 621 rcfw->qp_tbl = kcalloc(rcfw->qp_tbl_size, sizeof(struct bnxt_qplib_qp_node), 622 GFP_KERNEL); 623 if (!rcfw->qp_tbl) 624 goto fail; 625 626 return 0; 627 628 fail: 629 bnxt_qplib_free_rcfw_channel(rcfw); 630 return -ENOMEM; 631 } 632 633 void bnxt_qplib_rcfw_stop_irq(struct bnxt_qplib_rcfw *rcfw, bool kill) 634 { 635 struct bnxt_qplib_creq_ctx *creq; 636 637 creq = &rcfw->creq; 638 tasklet_disable(&creq->creq_tasklet); 639 /* Mask h/w interrupts */ 640 bnxt_qplib_ring_nq_db(&creq->creq_db.dbinfo, rcfw->res->cctx, false); 641 /* Sync with last running IRQ-handler */ 642 synchronize_irq(creq->msix_vec); 643 if (kill) 644 tasklet_kill(&creq->creq_tasklet); 645 646 if (creq->requested) { 647 free_irq(creq->msix_vec, rcfw); 648 creq->requested = false; 649 } 650 } 651 652 void bnxt_qplib_disable_rcfw_channel(struct bnxt_qplib_rcfw *rcfw) 653 { 654 struct bnxt_qplib_creq_ctx *creq; 655 struct bnxt_qplib_cmdq_ctx *cmdq; 656 unsigned long indx; 657 658 creq = &rcfw->creq; 659 cmdq = &rcfw->cmdq; 660 /* Make sure the HW channel is stopped! */ 661 bnxt_qplib_rcfw_stop_irq(rcfw, true); 662 663 iounmap(cmdq->cmdq_mbox.reg.bar_reg); 664 iounmap(creq->creq_db.reg.bar_reg); 665 666 indx = find_first_bit(cmdq->cmdq_bitmap, cmdq->bmap_size); 667 if (indx != cmdq->bmap_size) 668 dev_err(&rcfw->pdev->dev, 669 "disabling RCFW with pending cmd-bit %lx\n", indx); 670 671 cmdq->cmdq_mbox.reg.bar_reg = NULL; 672 creq->creq_db.reg.bar_reg = NULL; 673 creq->aeq_handler = NULL; 674 creq->msix_vec = 0; 675 } 676 677 int bnxt_qplib_rcfw_start_irq(struct bnxt_qplib_rcfw *rcfw, int msix_vector, 678 bool need_init) 679 { 680 struct bnxt_qplib_creq_ctx *creq; 681 int rc; 682 683 creq = &rcfw->creq; 684 685 if (creq->requested) 686 return -EFAULT; 687 688 creq->msix_vec = msix_vector; 689 if (need_init) 690 tasklet_setup(&creq->creq_tasklet, bnxt_qplib_service_creq); 691 else 692 tasklet_enable(&creq->creq_tasklet); 693 rc = request_irq(creq->msix_vec, bnxt_qplib_creq_irq, 0, 694 "bnxt_qplib_creq", rcfw); 695 if (rc) 696 return rc; 697 creq->requested = true; 698 699 bnxt_qplib_ring_nq_db(&creq->creq_db.dbinfo, rcfw->res->cctx, true); 700 701 return 0; 702 } 703 704 static int bnxt_qplib_map_cmdq_mbox(struct bnxt_qplib_rcfw *rcfw, bool is_vf) 705 { 706 struct bnxt_qplib_cmdq_mbox *mbox; 707 resource_size_t bar_reg; 708 struct pci_dev *pdev; 709 u16 prod_offt; 710 int rc = 0; 711 712 pdev = rcfw->pdev; 713 mbox = &rcfw->cmdq.cmdq_mbox; 714 715 mbox->reg.bar_id = RCFW_COMM_PCI_BAR_REGION; 716 mbox->reg.len = RCFW_COMM_SIZE; 717 mbox->reg.bar_base = pci_resource_start(pdev, mbox->reg.bar_id); 718 if (!mbox->reg.bar_base) { 719 dev_err(&pdev->dev, 720 "QPLIB: CMDQ BAR region %d resc start is 0!\n", 721 mbox->reg.bar_id); 722 return -ENOMEM; 723 } 724 725 bar_reg = mbox->reg.bar_base + RCFW_COMM_BASE_OFFSET; 726 mbox->reg.len = RCFW_COMM_SIZE; 727 mbox->reg.bar_reg = ioremap(bar_reg, mbox->reg.len); 728 if (!mbox->reg.bar_reg) { 729 dev_err(&pdev->dev, 730 "QPLIB: CMDQ BAR region %d mapping failed\n", 731 mbox->reg.bar_id); 732 return -ENOMEM; 733 } 734 735 prod_offt = is_vf ? RCFW_VF_COMM_PROD_OFFSET : 736 RCFW_PF_COMM_PROD_OFFSET; 737 mbox->prod = (void __iomem *)(mbox->reg.bar_reg + prod_offt); 738 mbox->db = (void __iomem *)(mbox->reg.bar_reg + RCFW_COMM_TRIG_OFFSET); 739 return rc; 740 } 741 742 static int bnxt_qplib_map_creq_db(struct bnxt_qplib_rcfw *rcfw, u32 reg_offt) 743 { 744 struct bnxt_qplib_creq_db *creq_db; 745 resource_size_t bar_reg; 746 struct pci_dev *pdev; 747 748 pdev = rcfw->pdev; 749 creq_db = &rcfw->creq.creq_db; 750 751 creq_db->reg.bar_id = RCFW_COMM_CONS_PCI_BAR_REGION; 752 creq_db->reg.bar_base = pci_resource_start(pdev, creq_db->reg.bar_id); 753 if (!creq_db->reg.bar_id) 754 dev_err(&pdev->dev, 755 "QPLIB: CREQ BAR region %d resc start is 0!", 756 creq_db->reg.bar_id); 757 758 bar_reg = creq_db->reg.bar_base + reg_offt; 759 /* Unconditionally map 8 bytes to support 57500 series */ 760 creq_db->reg.len = 8; 761 creq_db->reg.bar_reg = ioremap(bar_reg, creq_db->reg.len); 762 if (!creq_db->reg.bar_reg) { 763 dev_err(&pdev->dev, 764 "QPLIB: CREQ BAR region %d mapping failed", 765 creq_db->reg.bar_id); 766 return -ENOMEM; 767 } 768 creq_db->dbinfo.db = creq_db->reg.bar_reg; 769 creq_db->dbinfo.hwq = &rcfw->creq.hwq; 770 creq_db->dbinfo.xid = rcfw->creq.ring_id; 771 return 0; 772 } 773 774 static void bnxt_qplib_start_rcfw(struct bnxt_qplib_rcfw *rcfw) 775 { 776 struct bnxt_qplib_cmdq_ctx *cmdq; 777 struct bnxt_qplib_creq_ctx *creq; 778 struct bnxt_qplib_cmdq_mbox *mbox; 779 struct cmdq_init init = {0}; 780 781 cmdq = &rcfw->cmdq; 782 creq = &rcfw->creq; 783 mbox = &cmdq->cmdq_mbox; 784 785 init.cmdq_pbl = cpu_to_le64(cmdq->hwq.pbl[PBL_LVL_0].pg_map_arr[0]); 786 init.cmdq_size_cmdq_lvl = 787 cpu_to_le16(((rcfw->cmdq_depth << 788 CMDQ_INIT_CMDQ_SIZE_SFT) & 789 CMDQ_INIT_CMDQ_SIZE_MASK) | 790 ((cmdq->hwq.level << 791 CMDQ_INIT_CMDQ_LVL_SFT) & 792 CMDQ_INIT_CMDQ_LVL_MASK)); 793 init.creq_ring_id = cpu_to_le16(creq->ring_id); 794 /* Write to the Bono mailbox register */ 795 __iowrite32_copy(mbox->reg.bar_reg, &init, sizeof(init) / 4); 796 } 797 798 int bnxt_qplib_enable_rcfw_channel(struct bnxt_qplib_rcfw *rcfw, 799 int msix_vector, 800 int cp_bar_reg_off, int virt_fn, 801 aeq_handler_t aeq_handler) 802 { 803 struct bnxt_qplib_cmdq_ctx *cmdq; 804 struct bnxt_qplib_creq_ctx *creq; 805 int rc; 806 807 cmdq = &rcfw->cmdq; 808 creq = &rcfw->creq; 809 810 /* Clear to defaults */ 811 812 cmdq->seq_num = 0; 813 set_bit(FIRMWARE_FIRST_FLAG, &cmdq->flags); 814 init_waitqueue_head(&cmdq->waitq); 815 816 creq->stats.creq_qp_event_processed = 0; 817 creq->stats.creq_func_event_processed = 0; 818 creq->aeq_handler = aeq_handler; 819 820 rc = bnxt_qplib_map_cmdq_mbox(rcfw, virt_fn); 821 if (rc) 822 return rc; 823 824 rc = bnxt_qplib_map_creq_db(rcfw, cp_bar_reg_off); 825 if (rc) 826 return rc; 827 828 rc = bnxt_qplib_rcfw_start_irq(rcfw, msix_vector, true); 829 if (rc) { 830 dev_err(&rcfw->pdev->dev, 831 "Failed to request IRQ for CREQ rc = 0x%x\n", rc); 832 bnxt_qplib_disable_rcfw_channel(rcfw); 833 return rc; 834 } 835 836 bnxt_qplib_start_rcfw(rcfw); 837 838 return 0; 839 } 840 841 struct bnxt_qplib_rcfw_sbuf *bnxt_qplib_rcfw_alloc_sbuf( 842 struct bnxt_qplib_rcfw *rcfw, 843 u32 size) 844 { 845 struct bnxt_qplib_rcfw_sbuf *sbuf; 846 847 sbuf = kzalloc(sizeof(*sbuf), GFP_ATOMIC); 848 if (!sbuf) 849 return NULL; 850 851 sbuf->size = size; 852 sbuf->sb = dma_alloc_coherent(&rcfw->pdev->dev, sbuf->size, 853 &sbuf->dma_addr, GFP_ATOMIC); 854 if (!sbuf->sb) 855 goto bail; 856 857 return sbuf; 858 bail: 859 kfree(sbuf); 860 return NULL; 861 } 862 863 void bnxt_qplib_rcfw_free_sbuf(struct bnxt_qplib_rcfw *rcfw, 864 struct bnxt_qplib_rcfw_sbuf *sbuf) 865 { 866 if (sbuf->sb) 867 dma_free_coherent(&rcfw->pdev->dev, sbuf->size, 868 sbuf->sb, sbuf->dma_addr); 869 kfree(sbuf); 870 } 871