1 /* 2 * Broadcom NetXtreme-E RoCE driver. 3 * 4 * Copyright (c) 2016 - 2017, Broadcom. All rights reserved. The term 5 * Broadcom refers to Broadcom Limited and/or its subsidiaries. 6 * 7 * This software is available to you under a choice of one of two 8 * licenses. You may choose to be licensed under the terms of the GNU 9 * General Public License (GPL) Version 2, available from the file 10 * COPYING in the main directory of this source tree, or the 11 * BSD license below: 12 * 13 * Redistribution and use in source and binary forms, with or without 14 * modification, are permitted provided that the following conditions 15 * are met: 16 * 17 * 1. Redistributions of source code must retain the above copyright 18 * notice, this list of conditions and the following disclaimer. 19 * 2. Redistributions in binary form must reproduce the above copyright 20 * notice, this list of conditions and the following disclaimer in 21 * the documentation and/or other materials provided with the 22 * distribution. 23 * 24 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' 25 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, 26 * THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR 27 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS 28 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 29 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 30 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR 31 * BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, 32 * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE 33 * OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN 34 * IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 35 * 36 * Description: RDMA Controller HW interface 37 */ 38 39 #define dev_fmt(fmt) "QPLIB: " fmt 40 41 #include <linux/interrupt.h> 42 #include <linux/spinlock.h> 43 #include <linux/pci.h> 44 #include <linux/prefetch.h> 45 #include <linux/delay.h> 46 47 #include "roce_hsi.h" 48 #include "qplib_res.h" 49 #include "qplib_rcfw.h" 50 #include "qplib_sp.h" 51 #include "qplib_fp.h" 52 #include "qplib_tlv.h" 53 54 static void bnxt_qplib_service_creq(struct tasklet_struct *t); 55 56 /** 57 * bnxt_qplib_map_rc - map return type based on opcode 58 * @opcode: roce slow path opcode 59 * 60 * case #1 61 * Firmware initiated error recovery is a safe state machine and 62 * driver can consider all the underlying rdma resources are free. 63 * In this state, it is safe to return success for opcodes related to 64 * destroying rdma resources (like destroy qp, destroy cq etc.). 65 * 66 * case #2 67 * If driver detect potential firmware stall, it is not safe state machine 68 * and the driver can not consider all the underlying rdma resources are 69 * freed. 70 * In this state, it is not safe to return success for opcodes related to 71 * destroying rdma resources (like destroy qp, destroy cq etc.). 72 * 73 * Scope of this helper function is only for case #1. 74 * 75 * Returns: 76 * 0 to communicate success to caller. 77 * Non zero error code to communicate failure to caller. 78 */ 79 static int bnxt_qplib_map_rc(u8 opcode) 80 { 81 switch (opcode) { 82 case CMDQ_BASE_OPCODE_DESTROY_QP: 83 case CMDQ_BASE_OPCODE_DESTROY_SRQ: 84 case CMDQ_BASE_OPCODE_DESTROY_CQ: 85 case CMDQ_BASE_OPCODE_DEALLOCATE_KEY: 86 case CMDQ_BASE_OPCODE_DEREGISTER_MR: 87 case CMDQ_BASE_OPCODE_DELETE_GID: 88 case CMDQ_BASE_OPCODE_DESTROY_QP1: 89 case CMDQ_BASE_OPCODE_DESTROY_AH: 90 case CMDQ_BASE_OPCODE_DEINITIALIZE_FW: 91 case CMDQ_BASE_OPCODE_MODIFY_ROCE_CC: 92 case CMDQ_BASE_OPCODE_SET_LINK_AGGR_MODE: 93 return 0; 94 default: 95 return -ETIMEDOUT; 96 } 97 } 98 99 /** 100 * bnxt_re_is_fw_stalled - Check firmware health 101 * @rcfw: rcfw channel instance of rdev 102 * @cookie: cookie to track the command 103 * 104 * If firmware has not responded any rcfw command within 105 * rcfw->max_timeout, consider firmware as stalled. 106 * 107 * Returns: 108 * 0 if firmware is responding 109 * -ENODEV if firmware is not responding 110 */ 111 static int bnxt_re_is_fw_stalled(struct bnxt_qplib_rcfw *rcfw, 112 u16 cookie) 113 { 114 struct bnxt_qplib_cmdq_ctx *cmdq; 115 struct bnxt_qplib_crsqe *crsqe; 116 117 crsqe = &rcfw->crsqe_tbl[cookie]; 118 cmdq = &rcfw->cmdq; 119 120 if (time_after(jiffies, cmdq->last_seen + 121 (rcfw->max_timeout * HZ))) { 122 dev_warn_ratelimited(&rcfw->pdev->dev, 123 "%s: FW STALL Detected. cmdq[%#x]=%#x waited (%d > %d) msec active %d ", 124 __func__, cookie, crsqe->opcode, 125 jiffies_to_msecs(jiffies - cmdq->last_seen), 126 rcfw->max_timeout * 1000, 127 crsqe->is_in_used); 128 return -ENODEV; 129 } 130 131 return 0; 132 } 133 134 /** 135 * __wait_for_resp - Don't hold the cpu context and wait for response 136 * @rcfw: rcfw channel instance of rdev 137 * @cookie: cookie to track the command 138 * 139 * Wait for command completion in sleepable context. 140 * 141 * Returns: 142 * 0 if command is completed by firmware. 143 * Non zero error code for rest of the case. 144 */ 145 static int __wait_for_resp(struct bnxt_qplib_rcfw *rcfw, u16 cookie) 146 { 147 struct bnxt_qplib_cmdq_ctx *cmdq; 148 struct bnxt_qplib_crsqe *crsqe; 149 int ret; 150 151 cmdq = &rcfw->cmdq; 152 crsqe = &rcfw->crsqe_tbl[cookie]; 153 154 do { 155 if (test_bit(ERR_DEVICE_DETACHED, &cmdq->flags)) 156 return bnxt_qplib_map_rc(crsqe->opcode); 157 if (test_bit(FIRMWARE_STALL_DETECTED, &cmdq->flags)) 158 return -ETIMEDOUT; 159 160 wait_event_timeout(cmdq->waitq, 161 !crsqe->is_in_used || 162 test_bit(ERR_DEVICE_DETACHED, &cmdq->flags), 163 msecs_to_jiffies(rcfw->max_timeout * 1000)); 164 165 if (!crsqe->is_in_used) 166 return 0; 167 168 bnxt_qplib_service_creq(&rcfw->creq.creq_tasklet); 169 170 if (!crsqe->is_in_used) 171 return 0; 172 173 ret = bnxt_re_is_fw_stalled(rcfw, cookie); 174 if (ret) 175 return ret; 176 177 } while (true); 178 }; 179 180 /** 181 * __block_for_resp - hold the cpu context and wait for response 182 * @rcfw: rcfw channel instance of rdev 183 * @cookie: cookie to track the command 184 * 185 * This function will hold the cpu (non-sleepable context) and 186 * wait for command completion. Maximum holding interval is 8 second. 187 * 188 * Returns: 189 * -ETIMEOUT if command is not completed in specific time interval. 190 * 0 if command is completed by firmware. 191 */ 192 static int __block_for_resp(struct bnxt_qplib_rcfw *rcfw, u16 cookie) 193 { 194 struct bnxt_qplib_cmdq_ctx *cmdq = &rcfw->cmdq; 195 struct bnxt_qplib_crsqe *crsqe; 196 unsigned long issue_time = 0; 197 198 issue_time = jiffies; 199 crsqe = &rcfw->crsqe_tbl[cookie]; 200 201 do { 202 if (test_bit(ERR_DEVICE_DETACHED, &cmdq->flags)) 203 return bnxt_qplib_map_rc(crsqe->opcode); 204 if (test_bit(FIRMWARE_STALL_DETECTED, &cmdq->flags)) 205 return -ETIMEDOUT; 206 207 udelay(1); 208 209 bnxt_qplib_service_creq(&rcfw->creq.creq_tasklet); 210 if (!crsqe->is_in_used) 211 return 0; 212 213 } while (time_before(jiffies, issue_time + (8 * HZ))); 214 215 return -ETIMEDOUT; 216 }; 217 218 /* __send_message_no_waiter - get cookie and post the message. 219 * @rcfw: rcfw channel instance of rdev 220 * @msg: qplib message internal 221 * 222 * This function will just post and don't bother about completion. 223 * Current design of this function is - 224 * user must hold the completion queue hwq->lock. 225 * user must have used existing completion and free the resources. 226 * this function will not check queue full condition. 227 * this function will explicitly set is_waiter_alive=false. 228 * current use case is - send destroy_ah if create_ah is return 229 * after waiter of create_ah is lost. It can be extended for other 230 * use case as well. 231 * 232 * Returns: Nothing 233 * 234 */ 235 static void __send_message_no_waiter(struct bnxt_qplib_rcfw *rcfw, 236 struct bnxt_qplib_cmdqmsg *msg) 237 { 238 struct bnxt_qplib_cmdq_ctx *cmdq = &rcfw->cmdq; 239 struct bnxt_qplib_hwq *hwq = &cmdq->hwq; 240 struct bnxt_qplib_crsqe *crsqe; 241 struct bnxt_qplib_cmdqe *cmdqe; 242 u32 sw_prod, cmdq_prod; 243 u16 cookie; 244 u32 bsize; 245 u8 *preq; 246 247 cookie = cmdq->seq_num & RCFW_MAX_COOKIE_VALUE; 248 __set_cmdq_base_cookie(msg->req, msg->req_sz, cpu_to_le16(cookie)); 249 crsqe = &rcfw->crsqe_tbl[cookie]; 250 251 /* Set cmd_size in terms of 16B slots in req. */ 252 bsize = bnxt_qplib_set_cmd_slots(msg->req); 253 /* GET_CMD_SIZE would return number of slots in either case of tlv 254 * and non-tlv commands after call to bnxt_qplib_set_cmd_slots() 255 */ 256 crsqe->is_internal_cmd = true; 257 crsqe->is_waiter_alive = false; 258 crsqe->is_in_used = true; 259 crsqe->req_size = __get_cmdq_base_cmd_size(msg->req, msg->req_sz); 260 261 preq = (u8 *)msg->req; 262 do { 263 /* Locate the next cmdq slot */ 264 sw_prod = HWQ_CMP(hwq->prod, hwq); 265 cmdqe = bnxt_qplib_get_qe(hwq, sw_prod, NULL); 266 /* Copy a segment of the req cmd to the cmdq */ 267 memset(cmdqe, 0, sizeof(*cmdqe)); 268 memcpy(cmdqe, preq, min_t(u32, bsize, sizeof(*cmdqe))); 269 preq += min_t(u32, bsize, sizeof(*cmdqe)); 270 bsize -= min_t(u32, bsize, sizeof(*cmdqe)); 271 hwq->prod++; 272 } while (bsize > 0); 273 cmdq->seq_num++; 274 275 cmdq_prod = hwq->prod; 276 atomic_inc(&rcfw->timeout_send); 277 /* ring CMDQ DB */ 278 wmb(); 279 writel(cmdq_prod, cmdq->cmdq_mbox.prod); 280 writel(RCFW_CMDQ_TRIG_VAL, cmdq->cmdq_mbox.db); 281 } 282 283 static int __send_message(struct bnxt_qplib_rcfw *rcfw, 284 struct bnxt_qplib_cmdqmsg *msg, u8 opcode) 285 { 286 u32 bsize, free_slots, required_slots; 287 struct bnxt_qplib_cmdq_ctx *cmdq; 288 struct bnxt_qplib_crsqe *crsqe; 289 struct bnxt_qplib_cmdqe *cmdqe; 290 struct bnxt_qplib_hwq *hwq; 291 u32 sw_prod, cmdq_prod; 292 struct pci_dev *pdev; 293 u16 cookie; 294 u8 *preq; 295 296 cmdq = &rcfw->cmdq; 297 hwq = &cmdq->hwq; 298 pdev = rcfw->pdev; 299 300 /* Cmdq are in 16-byte units, each request can consume 1 or more 301 * cmdqe 302 */ 303 spin_lock_bh(&hwq->lock); 304 required_slots = bnxt_qplib_get_cmd_slots(msg->req); 305 free_slots = HWQ_FREE_SLOTS(hwq); 306 cookie = cmdq->seq_num & RCFW_MAX_COOKIE_VALUE; 307 crsqe = &rcfw->crsqe_tbl[cookie]; 308 309 if (required_slots >= free_slots) { 310 dev_info_ratelimited(&pdev->dev, 311 "CMDQ is full req/free %d/%d!", 312 required_slots, free_slots); 313 spin_unlock_bh(&hwq->lock); 314 return -EAGAIN; 315 } 316 if (msg->block) 317 cookie |= RCFW_CMD_IS_BLOCKING; 318 __set_cmdq_base_cookie(msg->req, msg->req_sz, cpu_to_le16(cookie)); 319 320 bsize = bnxt_qplib_set_cmd_slots(msg->req); 321 crsqe->free_slots = free_slots; 322 crsqe->resp = (struct creq_qp_event *)msg->resp; 323 crsqe->resp->cookie = cpu_to_le16(cookie); 324 crsqe->is_internal_cmd = false; 325 crsqe->is_waiter_alive = true; 326 crsqe->is_in_used = true; 327 crsqe->opcode = opcode; 328 329 crsqe->req_size = __get_cmdq_base_cmd_size(msg->req, msg->req_sz); 330 if (__get_cmdq_base_resp_size(msg->req, msg->req_sz) && msg->sb) { 331 struct bnxt_qplib_rcfw_sbuf *sbuf = msg->sb; 332 333 __set_cmdq_base_resp_addr(msg->req, msg->req_sz, 334 cpu_to_le64(sbuf->dma_addr)); 335 __set_cmdq_base_resp_size(msg->req, msg->req_sz, 336 ALIGN(sbuf->size, 337 BNXT_QPLIB_CMDQE_UNITS) / 338 BNXT_QPLIB_CMDQE_UNITS); 339 } 340 341 preq = (u8 *)msg->req; 342 do { 343 /* Locate the next cmdq slot */ 344 sw_prod = HWQ_CMP(hwq->prod, hwq); 345 cmdqe = bnxt_qplib_get_qe(hwq, sw_prod, NULL); 346 /* Copy a segment of the req cmd to the cmdq */ 347 memset(cmdqe, 0, sizeof(*cmdqe)); 348 memcpy(cmdqe, preq, min_t(u32, bsize, sizeof(*cmdqe))); 349 preq += min_t(u32, bsize, sizeof(*cmdqe)); 350 bsize -= min_t(u32, bsize, sizeof(*cmdqe)); 351 hwq->prod++; 352 } while (bsize > 0); 353 cmdq->seq_num++; 354 355 cmdq_prod = hwq->prod & 0xFFFF; 356 if (test_bit(FIRMWARE_FIRST_FLAG, &cmdq->flags)) { 357 /* The very first doorbell write 358 * is required to set this flag 359 * which prompts the FW to reset 360 * its internal pointers 361 */ 362 cmdq_prod |= BIT(FIRMWARE_FIRST_FLAG); 363 clear_bit(FIRMWARE_FIRST_FLAG, &cmdq->flags); 364 } 365 /* ring CMDQ DB */ 366 wmb(); 367 writel(cmdq_prod, cmdq->cmdq_mbox.prod); 368 writel(RCFW_CMDQ_TRIG_VAL, cmdq->cmdq_mbox.db); 369 spin_unlock_bh(&hwq->lock); 370 /* Return the CREQ response pointer */ 371 return 0; 372 } 373 374 /** 375 * __poll_for_resp - self poll completion for rcfw command 376 * @rcfw: rcfw channel instance of rdev 377 * @cookie: cookie to track the command 378 * 379 * It works same as __wait_for_resp except this function will 380 * do self polling in sort interval since interrupt is disabled. 381 * This function can not be called from non-sleepable context. 382 * 383 * Returns: 384 * -ETIMEOUT if command is not completed in specific time interval. 385 * 0 if command is completed by firmware. 386 */ 387 static int __poll_for_resp(struct bnxt_qplib_rcfw *rcfw, u16 cookie) 388 { 389 struct bnxt_qplib_cmdq_ctx *cmdq = &rcfw->cmdq; 390 struct bnxt_qplib_crsqe *crsqe; 391 unsigned long issue_time; 392 int ret; 393 394 issue_time = jiffies; 395 crsqe = &rcfw->crsqe_tbl[cookie]; 396 397 do { 398 if (test_bit(ERR_DEVICE_DETACHED, &cmdq->flags)) 399 return bnxt_qplib_map_rc(crsqe->opcode); 400 if (test_bit(FIRMWARE_STALL_DETECTED, &cmdq->flags)) 401 return -ETIMEDOUT; 402 403 usleep_range(1000, 1001); 404 405 bnxt_qplib_service_creq(&rcfw->creq.creq_tasklet); 406 if (!crsqe->is_in_used) 407 return 0; 408 if (jiffies_to_msecs(jiffies - issue_time) > 409 (rcfw->max_timeout * 1000)) { 410 ret = bnxt_re_is_fw_stalled(rcfw, cookie); 411 if (ret) 412 return ret; 413 } 414 } while (true); 415 }; 416 417 static int __send_message_basic_sanity(struct bnxt_qplib_rcfw *rcfw, 418 struct bnxt_qplib_cmdqmsg *msg, 419 u8 opcode) 420 { 421 struct bnxt_qplib_cmdq_ctx *cmdq; 422 423 cmdq = &rcfw->cmdq; 424 425 /* Prevent posting if f/w is not in a state to process */ 426 if (test_bit(ERR_DEVICE_DETACHED, &rcfw->cmdq.flags)) 427 return bnxt_qplib_map_rc(opcode); 428 if (test_bit(FIRMWARE_STALL_DETECTED, &cmdq->flags)) 429 return -ETIMEDOUT; 430 431 if (test_bit(FIRMWARE_INITIALIZED_FLAG, &cmdq->flags) && 432 opcode == CMDQ_BASE_OPCODE_INITIALIZE_FW) { 433 dev_err(&rcfw->pdev->dev, "QPLIB: RCFW already initialized!"); 434 return -EINVAL; 435 } 436 437 if (!test_bit(FIRMWARE_INITIALIZED_FLAG, &cmdq->flags) && 438 (opcode != CMDQ_BASE_OPCODE_QUERY_FUNC && 439 opcode != CMDQ_BASE_OPCODE_INITIALIZE_FW && 440 opcode != CMDQ_BASE_OPCODE_QUERY_VERSION)) { 441 dev_err(&rcfw->pdev->dev, 442 "QPLIB: RCFW not initialized, reject opcode 0x%x", 443 opcode); 444 return -EOPNOTSUPP; 445 } 446 447 return 0; 448 } 449 450 /* This function will just post and do not bother about completion */ 451 static void __destroy_timedout_ah(struct bnxt_qplib_rcfw *rcfw, 452 struct creq_create_ah_resp *create_ah_resp) 453 { 454 struct bnxt_qplib_cmdqmsg msg = {}; 455 struct cmdq_destroy_ah req = {}; 456 457 bnxt_qplib_rcfw_cmd_prep((struct cmdq_base *)&req, 458 CMDQ_BASE_OPCODE_DESTROY_AH, 459 sizeof(req)); 460 req.ah_cid = create_ah_resp->xid; 461 msg.req = (struct cmdq_base *)&req; 462 msg.req_sz = sizeof(req); 463 __send_message_no_waiter(rcfw, &msg); 464 dev_info_ratelimited(&rcfw->pdev->dev, 465 "From %s: ah_cid = %d timeout_send %d\n", 466 __func__, req.ah_cid, 467 atomic_read(&rcfw->timeout_send)); 468 } 469 470 /** 471 * __bnxt_qplib_rcfw_send_message - qplib interface to send 472 * and complete rcfw command. 473 * @rcfw: rcfw channel instance of rdev 474 * @msg: qplib message internal 475 * 476 * This function does not account shadow queue depth. It will send 477 * all the command unconditionally as long as send queue is not full. 478 * 479 * Returns: 480 * 0 if command completed by firmware. 481 * Non zero if the command is not completed by firmware. 482 */ 483 static int __bnxt_qplib_rcfw_send_message(struct bnxt_qplib_rcfw *rcfw, 484 struct bnxt_qplib_cmdqmsg *msg) 485 { 486 struct creq_qp_event *evnt = (struct creq_qp_event *)msg->resp; 487 struct bnxt_qplib_crsqe *crsqe; 488 u16 cookie; 489 int rc; 490 u8 opcode; 491 492 opcode = __get_cmdq_base_opcode(msg->req, msg->req_sz); 493 494 rc = __send_message_basic_sanity(rcfw, msg, opcode); 495 if (rc) 496 return rc; 497 498 rc = __send_message(rcfw, msg, opcode); 499 if (rc) 500 return rc; 501 502 cookie = le16_to_cpu(__get_cmdq_base_cookie(msg->req, msg->req_sz)) 503 & RCFW_MAX_COOKIE_VALUE; 504 505 if (msg->block) 506 rc = __block_for_resp(rcfw, cookie); 507 else if (atomic_read(&rcfw->rcfw_intr_enabled)) 508 rc = __wait_for_resp(rcfw, cookie); 509 else 510 rc = __poll_for_resp(rcfw, cookie); 511 512 if (rc) { 513 spin_lock_bh(&rcfw->cmdq.hwq.lock); 514 crsqe = &rcfw->crsqe_tbl[cookie]; 515 crsqe->is_waiter_alive = false; 516 if (rc == -ENODEV) 517 set_bit(FIRMWARE_STALL_DETECTED, &rcfw->cmdq.flags); 518 spin_unlock_bh(&rcfw->cmdq.hwq.lock); 519 return -ETIMEDOUT; 520 } 521 522 if (evnt->status) { 523 /* failed with status */ 524 dev_err(&rcfw->pdev->dev, "cmdq[%#x]=%#x status %#x\n", 525 cookie, opcode, evnt->status); 526 rc = -EIO; 527 } 528 529 return rc; 530 } 531 532 /** 533 * bnxt_qplib_rcfw_send_message - qplib interface to send 534 * and complete rcfw command. 535 * @rcfw: rcfw channel instance of rdev 536 * @msg: qplib message internal 537 * 538 * Driver interact with Firmware through rcfw channel/slow path in two ways. 539 * a. Blocking rcfw command send. In this path, driver cannot hold 540 * the context for longer period since it is holding cpu until 541 * command is not completed. 542 * b. Non-blocking rcfw command send. In this path, driver can hold the 543 * context for longer period. There may be many pending command waiting 544 * for completion because of non-blocking nature. 545 * 546 * Driver will use shadow queue depth. Current queue depth of 8K 547 * (due to size of rcfw message there can be actual ~4K rcfw outstanding) 548 * is not optimal for rcfw command processing in firmware. 549 * 550 * Restrict at max #RCFW_CMD_NON_BLOCKING_SHADOW_QD Non-Blocking rcfw commands. 551 * Allow all blocking commands until there is no queue full. 552 * 553 * Returns: 554 * 0 if command completed by firmware. 555 * Non zero if the command is not completed by firmware. 556 */ 557 int bnxt_qplib_rcfw_send_message(struct bnxt_qplib_rcfw *rcfw, 558 struct bnxt_qplib_cmdqmsg *msg) 559 { 560 int ret; 561 562 if (!msg->block) { 563 down(&rcfw->rcfw_inflight); 564 ret = __bnxt_qplib_rcfw_send_message(rcfw, msg); 565 up(&rcfw->rcfw_inflight); 566 } else { 567 ret = __bnxt_qplib_rcfw_send_message(rcfw, msg); 568 } 569 570 return ret; 571 } 572 573 /* Completions */ 574 static int bnxt_qplib_process_func_event(struct bnxt_qplib_rcfw *rcfw, 575 struct creq_func_event *func_event) 576 { 577 int rc; 578 579 switch (func_event->event) { 580 case CREQ_FUNC_EVENT_EVENT_TX_WQE_ERROR: 581 break; 582 case CREQ_FUNC_EVENT_EVENT_TX_DATA_ERROR: 583 break; 584 case CREQ_FUNC_EVENT_EVENT_RX_WQE_ERROR: 585 break; 586 case CREQ_FUNC_EVENT_EVENT_RX_DATA_ERROR: 587 break; 588 case CREQ_FUNC_EVENT_EVENT_CQ_ERROR: 589 break; 590 case CREQ_FUNC_EVENT_EVENT_TQM_ERROR: 591 break; 592 case CREQ_FUNC_EVENT_EVENT_CFCQ_ERROR: 593 break; 594 case CREQ_FUNC_EVENT_EVENT_CFCS_ERROR: 595 /* SRQ ctx error, call srq_handler?? 596 * But there's no SRQ handle! 597 */ 598 break; 599 case CREQ_FUNC_EVENT_EVENT_CFCC_ERROR: 600 break; 601 case CREQ_FUNC_EVENT_EVENT_CFCM_ERROR: 602 break; 603 case CREQ_FUNC_EVENT_EVENT_TIM_ERROR: 604 break; 605 case CREQ_FUNC_EVENT_EVENT_VF_COMM_REQUEST: 606 break; 607 case CREQ_FUNC_EVENT_EVENT_RESOURCE_EXHAUSTED: 608 break; 609 default: 610 return -EINVAL; 611 } 612 613 rc = rcfw->creq.aeq_handler(rcfw, (void *)func_event, NULL); 614 return rc; 615 } 616 617 static int bnxt_qplib_process_qp_event(struct bnxt_qplib_rcfw *rcfw, 618 struct creq_qp_event *qp_event, 619 u32 *num_wait) 620 { 621 struct creq_qp_error_notification *err_event; 622 struct bnxt_qplib_hwq *hwq = &rcfw->cmdq.hwq; 623 struct bnxt_qplib_crsqe *crsqe; 624 u32 qp_id, tbl_indx, req_size; 625 struct bnxt_qplib_qp *qp; 626 u16 cookie, blocked = 0; 627 bool is_waiter_alive; 628 struct pci_dev *pdev; 629 u32 wait_cmds = 0; 630 int rc = 0; 631 632 pdev = rcfw->pdev; 633 switch (qp_event->event) { 634 case CREQ_QP_EVENT_EVENT_QP_ERROR_NOTIFICATION: 635 err_event = (struct creq_qp_error_notification *)qp_event; 636 qp_id = le32_to_cpu(err_event->xid); 637 spin_lock(&rcfw->tbl_lock); 638 tbl_indx = map_qp_id_to_tbl_indx(qp_id, rcfw); 639 qp = rcfw->qp_tbl[tbl_indx].qp_handle; 640 if (!qp) { 641 spin_unlock(&rcfw->tbl_lock); 642 break; 643 } 644 bnxt_qplib_mark_qp_error(qp); 645 rc = rcfw->creq.aeq_handler(rcfw, qp_event, qp); 646 spin_unlock(&rcfw->tbl_lock); 647 dev_dbg(&pdev->dev, "Received QP error notification\n"); 648 dev_dbg(&pdev->dev, 649 "qpid 0x%x, req_err=0x%x, resp_err=0x%x\n", 650 qp_id, err_event->req_err_state_reason, 651 err_event->res_err_state_reason); 652 break; 653 default: 654 /* 655 * Command Response 656 * cmdq->lock needs to be acquired to synchronie 657 * the command send and completion reaping. This function 658 * is always called with creq->lock held. Using 659 * the nested variant of spin_lock. 660 * 661 */ 662 663 spin_lock_nested(&hwq->lock, SINGLE_DEPTH_NESTING); 664 cookie = le16_to_cpu(qp_event->cookie); 665 blocked = cookie & RCFW_CMD_IS_BLOCKING; 666 cookie &= RCFW_MAX_COOKIE_VALUE; 667 crsqe = &rcfw->crsqe_tbl[cookie]; 668 669 if (WARN_ONCE(test_bit(FIRMWARE_STALL_DETECTED, 670 &rcfw->cmdq.flags), 671 "QPLIB: Unreponsive rcfw channel detected.!!")) { 672 dev_info(&pdev->dev, 673 "rcfw timedout: cookie = %#x, free_slots = %d", 674 cookie, crsqe->free_slots); 675 spin_unlock(&hwq->lock); 676 return rc; 677 } 678 679 if (crsqe->is_internal_cmd && !qp_event->status) 680 atomic_dec(&rcfw->timeout_send); 681 682 if (crsqe->is_waiter_alive) { 683 if (crsqe->resp) { 684 memcpy(crsqe->resp, qp_event, sizeof(*qp_event)); 685 /* Insert write memory barrier to ensure that 686 * response data is copied before clearing the 687 * flags 688 */ 689 smp_wmb(); 690 } 691 if (!blocked) 692 wait_cmds++; 693 } 694 695 req_size = crsqe->req_size; 696 is_waiter_alive = crsqe->is_waiter_alive; 697 698 crsqe->req_size = 0; 699 if (!is_waiter_alive) 700 crsqe->resp = NULL; 701 702 crsqe->is_in_used = false; 703 704 hwq->cons += req_size; 705 706 /* This is a case to handle below scenario - 707 * Create AH is completed successfully by firmware, 708 * but completion took more time and driver already lost 709 * the context of create_ah from caller. 710 * We have already return failure for create_ah verbs, 711 * so let's destroy the same address vector since it is 712 * no more used in stack. We don't care about completion 713 * in __send_message_no_waiter. 714 * If destroy_ah is failued by firmware, there will be AH 715 * resource leak and relatively not critical + unlikely 716 * scenario. Current design is not to handle such case. 717 */ 718 if (!is_waiter_alive && !qp_event->status && 719 qp_event->event == CREQ_QP_EVENT_EVENT_CREATE_AH) 720 __destroy_timedout_ah(rcfw, 721 (struct creq_create_ah_resp *) 722 qp_event); 723 spin_unlock(&hwq->lock); 724 } 725 *num_wait += wait_cmds; 726 return rc; 727 } 728 729 /* SP - CREQ Completion handlers */ 730 static void bnxt_qplib_service_creq(struct tasklet_struct *t) 731 { 732 struct bnxt_qplib_rcfw *rcfw = from_tasklet(rcfw, t, creq.creq_tasklet); 733 struct bnxt_qplib_creq_ctx *creq = &rcfw->creq; 734 u32 type, budget = CREQ_ENTRY_POLL_BUDGET; 735 struct bnxt_qplib_hwq *hwq = &creq->hwq; 736 struct creq_base *creqe; 737 u32 num_wakeup = 0; 738 u32 hw_polled = 0; 739 740 /* Service the CREQ until budget is over */ 741 spin_lock_bh(&hwq->lock); 742 while (budget > 0) { 743 creqe = bnxt_qplib_get_qe(hwq, hwq->cons, NULL); 744 if (!CREQ_CMP_VALID(creqe, creq->creq_db.dbinfo.flags)) 745 break; 746 /* The valid test of the entry must be done first before 747 * reading any further. 748 */ 749 dma_rmb(); 750 rcfw->cmdq.last_seen = jiffies; 751 752 type = creqe->type & CREQ_BASE_TYPE_MASK; 753 switch (type) { 754 case CREQ_BASE_TYPE_QP_EVENT: 755 bnxt_qplib_process_qp_event 756 (rcfw, (struct creq_qp_event *)creqe, 757 &num_wakeup); 758 creq->stats.creq_qp_event_processed++; 759 break; 760 case CREQ_BASE_TYPE_FUNC_EVENT: 761 if (!bnxt_qplib_process_func_event 762 (rcfw, (struct creq_func_event *)creqe)) 763 creq->stats.creq_func_event_processed++; 764 else 765 dev_warn(&rcfw->pdev->dev, 766 "aeqe:%#x Not handled\n", type); 767 break; 768 default: 769 if (type != ASYNC_EVENT_CMPL_TYPE_HWRM_ASYNC_EVENT) 770 dev_warn(&rcfw->pdev->dev, 771 "creqe with event 0x%x not handled\n", 772 type); 773 break; 774 } 775 budget--; 776 hw_polled++; 777 bnxt_qplib_hwq_incr_cons(hwq->max_elements, &hwq->cons, 778 1, &creq->creq_db.dbinfo.flags); 779 } 780 781 if (hw_polled) 782 bnxt_qplib_ring_nq_db(&creq->creq_db.dbinfo, 783 rcfw->res->cctx, true); 784 spin_unlock_bh(&hwq->lock); 785 if (num_wakeup) 786 wake_up_nr(&rcfw->cmdq.waitq, num_wakeup); 787 } 788 789 static irqreturn_t bnxt_qplib_creq_irq(int irq, void *dev_instance) 790 { 791 struct bnxt_qplib_rcfw *rcfw = dev_instance; 792 struct bnxt_qplib_creq_ctx *creq; 793 struct bnxt_qplib_hwq *hwq; 794 u32 sw_cons; 795 796 creq = &rcfw->creq; 797 hwq = &creq->hwq; 798 /* Prefetch the CREQ element */ 799 sw_cons = HWQ_CMP(hwq->cons, hwq); 800 prefetch(bnxt_qplib_get_qe(hwq, sw_cons, NULL)); 801 802 tasklet_schedule(&creq->creq_tasklet); 803 804 return IRQ_HANDLED; 805 } 806 807 /* RCFW */ 808 int bnxt_qplib_deinit_rcfw(struct bnxt_qplib_rcfw *rcfw) 809 { 810 struct creq_deinitialize_fw_resp resp = {}; 811 struct cmdq_deinitialize_fw req = {}; 812 struct bnxt_qplib_cmdqmsg msg = {}; 813 int rc; 814 815 bnxt_qplib_rcfw_cmd_prep((struct cmdq_base *)&req, 816 CMDQ_BASE_OPCODE_DEINITIALIZE_FW, 817 sizeof(req)); 818 bnxt_qplib_fill_cmdqmsg(&msg, &req, &resp, NULL, 819 sizeof(req), sizeof(resp), 0); 820 rc = bnxt_qplib_rcfw_send_message(rcfw, &msg); 821 if (rc) 822 return rc; 823 824 clear_bit(FIRMWARE_INITIALIZED_FLAG, &rcfw->cmdq.flags); 825 return 0; 826 } 827 828 int bnxt_qplib_init_rcfw(struct bnxt_qplib_rcfw *rcfw, 829 struct bnxt_qplib_ctx *ctx, int is_virtfn) 830 { 831 struct creq_initialize_fw_resp resp = {}; 832 struct cmdq_initialize_fw req = {}; 833 struct bnxt_qplib_cmdqmsg msg = {}; 834 u8 pgsz, lvl; 835 int rc; 836 837 bnxt_qplib_rcfw_cmd_prep((struct cmdq_base *)&req, 838 CMDQ_BASE_OPCODE_INITIALIZE_FW, 839 sizeof(req)); 840 /* Supply (log-base-2-of-host-page-size - base-page-shift) 841 * to bono to adjust the doorbell page sizes. 842 */ 843 req.log2_dbr_pg_size = cpu_to_le16(PAGE_SHIFT - 844 RCFW_DBR_BASE_PAGE_SHIFT); 845 /* 846 * Gen P5 devices doesn't require this allocation 847 * as the L2 driver does the same for RoCE also. 848 * Also, VFs need not setup the HW context area, PF 849 * shall setup this area for VF. Skipping the 850 * HW programming 851 */ 852 if (is_virtfn) 853 goto skip_ctx_setup; 854 if (bnxt_qplib_is_chip_gen_p5_p7(rcfw->res->cctx)) 855 goto config_vf_res; 856 857 lvl = ctx->qpc_tbl.level; 858 pgsz = bnxt_qplib_base_pg_size(&ctx->qpc_tbl); 859 req.qpc_pg_size_qpc_lvl = (pgsz << CMDQ_INITIALIZE_FW_QPC_PG_SIZE_SFT) | 860 lvl; 861 lvl = ctx->mrw_tbl.level; 862 pgsz = bnxt_qplib_base_pg_size(&ctx->mrw_tbl); 863 req.mrw_pg_size_mrw_lvl = (pgsz << CMDQ_INITIALIZE_FW_QPC_PG_SIZE_SFT) | 864 lvl; 865 lvl = ctx->srqc_tbl.level; 866 pgsz = bnxt_qplib_base_pg_size(&ctx->srqc_tbl); 867 req.srq_pg_size_srq_lvl = (pgsz << CMDQ_INITIALIZE_FW_QPC_PG_SIZE_SFT) | 868 lvl; 869 lvl = ctx->cq_tbl.level; 870 pgsz = bnxt_qplib_base_pg_size(&ctx->cq_tbl); 871 req.cq_pg_size_cq_lvl = (pgsz << CMDQ_INITIALIZE_FW_QPC_PG_SIZE_SFT) | 872 lvl; 873 lvl = ctx->tim_tbl.level; 874 pgsz = bnxt_qplib_base_pg_size(&ctx->tim_tbl); 875 req.tim_pg_size_tim_lvl = (pgsz << CMDQ_INITIALIZE_FW_QPC_PG_SIZE_SFT) | 876 lvl; 877 lvl = ctx->tqm_ctx.pde.level; 878 pgsz = bnxt_qplib_base_pg_size(&ctx->tqm_ctx.pde); 879 req.tqm_pg_size_tqm_lvl = (pgsz << CMDQ_INITIALIZE_FW_QPC_PG_SIZE_SFT) | 880 lvl; 881 req.qpc_page_dir = 882 cpu_to_le64(ctx->qpc_tbl.pbl[PBL_LVL_0].pg_map_arr[0]); 883 req.mrw_page_dir = 884 cpu_to_le64(ctx->mrw_tbl.pbl[PBL_LVL_0].pg_map_arr[0]); 885 req.srq_page_dir = 886 cpu_to_le64(ctx->srqc_tbl.pbl[PBL_LVL_0].pg_map_arr[0]); 887 req.cq_page_dir = 888 cpu_to_le64(ctx->cq_tbl.pbl[PBL_LVL_0].pg_map_arr[0]); 889 req.tim_page_dir = 890 cpu_to_le64(ctx->tim_tbl.pbl[PBL_LVL_0].pg_map_arr[0]); 891 req.tqm_page_dir = 892 cpu_to_le64(ctx->tqm_ctx.pde.pbl[PBL_LVL_0].pg_map_arr[0]); 893 894 req.number_of_qp = cpu_to_le32(ctx->qpc_tbl.max_elements); 895 req.number_of_mrw = cpu_to_le32(ctx->mrw_tbl.max_elements); 896 req.number_of_srq = cpu_to_le32(ctx->srqc_tbl.max_elements); 897 req.number_of_cq = cpu_to_le32(ctx->cq_tbl.max_elements); 898 899 config_vf_res: 900 req.max_qp_per_vf = cpu_to_le32(ctx->vf_res.max_qp_per_vf); 901 req.max_mrw_per_vf = cpu_to_le32(ctx->vf_res.max_mrw_per_vf); 902 req.max_srq_per_vf = cpu_to_le32(ctx->vf_res.max_srq_per_vf); 903 req.max_cq_per_vf = cpu_to_le32(ctx->vf_res.max_cq_per_vf); 904 req.max_gid_per_vf = cpu_to_le32(ctx->vf_res.max_gid_per_vf); 905 906 skip_ctx_setup: 907 if (BNXT_RE_HW_RETX(rcfw->res->dattr->dev_cap_flags)) 908 req.flags |= cpu_to_le16(CMDQ_INITIALIZE_FW_FLAGS_HW_REQUESTER_RETX_SUPPORTED); 909 req.stat_ctx_id = cpu_to_le32(ctx->stats.fw_id); 910 bnxt_qplib_fill_cmdqmsg(&msg, &req, &resp, NULL, sizeof(req), sizeof(resp), 0); 911 rc = bnxt_qplib_rcfw_send_message(rcfw, &msg); 912 if (rc) 913 return rc; 914 set_bit(FIRMWARE_INITIALIZED_FLAG, &rcfw->cmdq.flags); 915 return 0; 916 } 917 918 void bnxt_qplib_free_rcfw_channel(struct bnxt_qplib_rcfw *rcfw) 919 { 920 kfree(rcfw->qp_tbl); 921 kfree(rcfw->crsqe_tbl); 922 bnxt_qplib_free_hwq(rcfw->res, &rcfw->cmdq.hwq); 923 bnxt_qplib_free_hwq(rcfw->res, &rcfw->creq.hwq); 924 rcfw->pdev = NULL; 925 } 926 927 int bnxt_qplib_alloc_rcfw_channel(struct bnxt_qplib_res *res, 928 struct bnxt_qplib_rcfw *rcfw, 929 struct bnxt_qplib_ctx *ctx, 930 int qp_tbl_sz) 931 { 932 struct bnxt_qplib_hwq_attr hwq_attr = {}; 933 struct bnxt_qplib_sg_info sginfo = {}; 934 struct bnxt_qplib_cmdq_ctx *cmdq; 935 struct bnxt_qplib_creq_ctx *creq; 936 937 rcfw->pdev = res->pdev; 938 cmdq = &rcfw->cmdq; 939 creq = &rcfw->creq; 940 rcfw->res = res; 941 942 sginfo.pgsize = PAGE_SIZE; 943 sginfo.pgshft = PAGE_SHIFT; 944 945 hwq_attr.sginfo = &sginfo; 946 hwq_attr.res = rcfw->res; 947 hwq_attr.depth = BNXT_QPLIB_CREQE_MAX_CNT; 948 hwq_attr.stride = BNXT_QPLIB_CREQE_UNITS; 949 hwq_attr.type = bnxt_qplib_get_hwq_type(res); 950 951 if (bnxt_qplib_alloc_init_hwq(&creq->hwq, &hwq_attr)) { 952 dev_err(&rcfw->pdev->dev, 953 "HW channel CREQ allocation failed\n"); 954 goto fail; 955 } 956 957 rcfw->cmdq_depth = BNXT_QPLIB_CMDQE_MAX_CNT; 958 959 sginfo.pgsize = bnxt_qplib_cmdqe_page_size(rcfw->cmdq_depth); 960 hwq_attr.depth = rcfw->cmdq_depth & 0x7FFFFFFF; 961 hwq_attr.stride = BNXT_QPLIB_CMDQE_UNITS; 962 hwq_attr.type = HWQ_TYPE_CTX; 963 if (bnxt_qplib_alloc_init_hwq(&cmdq->hwq, &hwq_attr)) { 964 dev_err(&rcfw->pdev->dev, 965 "HW channel CMDQ allocation failed\n"); 966 goto fail; 967 } 968 969 rcfw->crsqe_tbl = kcalloc(cmdq->hwq.max_elements, 970 sizeof(*rcfw->crsqe_tbl), GFP_KERNEL); 971 if (!rcfw->crsqe_tbl) 972 goto fail; 973 974 /* Allocate one extra to hold the QP1 entries */ 975 rcfw->qp_tbl_size = qp_tbl_sz + 1; 976 rcfw->qp_tbl = kcalloc(rcfw->qp_tbl_size, sizeof(struct bnxt_qplib_qp_node), 977 GFP_KERNEL); 978 if (!rcfw->qp_tbl) 979 goto fail; 980 spin_lock_init(&rcfw->tbl_lock); 981 982 rcfw->max_timeout = res->cctx->hwrm_cmd_max_timeout; 983 984 return 0; 985 986 fail: 987 bnxt_qplib_free_rcfw_channel(rcfw); 988 return -ENOMEM; 989 } 990 991 void bnxt_qplib_rcfw_stop_irq(struct bnxt_qplib_rcfw *rcfw, bool kill) 992 { 993 struct bnxt_qplib_creq_ctx *creq; 994 995 creq = &rcfw->creq; 996 997 if (!creq->requested) 998 return; 999 1000 creq->requested = false; 1001 /* Mask h/w interrupts */ 1002 bnxt_qplib_ring_nq_db(&creq->creq_db.dbinfo, rcfw->res->cctx, false); 1003 /* Sync with last running IRQ-handler */ 1004 synchronize_irq(creq->msix_vec); 1005 free_irq(creq->msix_vec, rcfw); 1006 kfree(creq->irq_name); 1007 creq->irq_name = NULL; 1008 atomic_set(&rcfw->rcfw_intr_enabled, 0); 1009 if (kill) 1010 tasklet_kill(&creq->creq_tasklet); 1011 tasklet_disable(&creq->creq_tasklet); 1012 } 1013 1014 void bnxt_qplib_disable_rcfw_channel(struct bnxt_qplib_rcfw *rcfw) 1015 { 1016 struct bnxt_qplib_creq_ctx *creq; 1017 struct bnxt_qplib_cmdq_ctx *cmdq; 1018 1019 creq = &rcfw->creq; 1020 cmdq = &rcfw->cmdq; 1021 /* Make sure the HW channel is stopped! */ 1022 bnxt_qplib_rcfw_stop_irq(rcfw, true); 1023 1024 iounmap(cmdq->cmdq_mbox.reg.bar_reg); 1025 iounmap(creq->creq_db.reg.bar_reg); 1026 1027 cmdq->cmdq_mbox.reg.bar_reg = NULL; 1028 creq->creq_db.reg.bar_reg = NULL; 1029 creq->aeq_handler = NULL; 1030 creq->msix_vec = 0; 1031 } 1032 1033 int bnxt_qplib_rcfw_start_irq(struct bnxt_qplib_rcfw *rcfw, int msix_vector, 1034 bool need_init) 1035 { 1036 struct bnxt_qplib_creq_ctx *creq; 1037 struct bnxt_qplib_res *res; 1038 int rc; 1039 1040 creq = &rcfw->creq; 1041 res = rcfw->res; 1042 1043 if (creq->requested) 1044 return -EFAULT; 1045 1046 creq->msix_vec = msix_vector; 1047 if (need_init) 1048 tasklet_setup(&creq->creq_tasklet, bnxt_qplib_service_creq); 1049 else 1050 tasklet_enable(&creq->creq_tasklet); 1051 1052 creq->irq_name = kasprintf(GFP_KERNEL, "bnxt_re-creq@pci:%s", 1053 pci_name(res->pdev)); 1054 if (!creq->irq_name) 1055 return -ENOMEM; 1056 rc = request_irq(creq->msix_vec, bnxt_qplib_creq_irq, 0, 1057 creq->irq_name, rcfw); 1058 if (rc) { 1059 kfree(creq->irq_name); 1060 creq->irq_name = NULL; 1061 tasklet_disable(&creq->creq_tasklet); 1062 return rc; 1063 } 1064 creq->requested = true; 1065 1066 bnxt_qplib_ring_nq_db(&creq->creq_db.dbinfo, res->cctx, true); 1067 atomic_inc(&rcfw->rcfw_intr_enabled); 1068 1069 return 0; 1070 } 1071 1072 static int bnxt_qplib_map_cmdq_mbox(struct bnxt_qplib_rcfw *rcfw) 1073 { 1074 struct bnxt_qplib_cmdq_mbox *mbox; 1075 resource_size_t bar_reg; 1076 struct pci_dev *pdev; 1077 1078 pdev = rcfw->pdev; 1079 mbox = &rcfw->cmdq.cmdq_mbox; 1080 1081 mbox->reg.bar_id = RCFW_COMM_PCI_BAR_REGION; 1082 mbox->reg.len = RCFW_COMM_SIZE; 1083 mbox->reg.bar_base = pci_resource_start(pdev, mbox->reg.bar_id); 1084 if (!mbox->reg.bar_base) { 1085 dev_err(&pdev->dev, 1086 "QPLIB: CMDQ BAR region %d resc start is 0!\n", 1087 mbox->reg.bar_id); 1088 return -ENOMEM; 1089 } 1090 1091 bar_reg = mbox->reg.bar_base + RCFW_COMM_BASE_OFFSET; 1092 mbox->reg.len = RCFW_COMM_SIZE; 1093 mbox->reg.bar_reg = ioremap(bar_reg, mbox->reg.len); 1094 if (!mbox->reg.bar_reg) { 1095 dev_err(&pdev->dev, 1096 "QPLIB: CMDQ BAR region %d mapping failed\n", 1097 mbox->reg.bar_id); 1098 return -ENOMEM; 1099 } 1100 1101 mbox->prod = (void __iomem *)(mbox->reg.bar_reg + 1102 RCFW_PF_VF_COMM_PROD_OFFSET); 1103 mbox->db = (void __iomem *)(mbox->reg.bar_reg + RCFW_COMM_TRIG_OFFSET); 1104 return 0; 1105 } 1106 1107 static int bnxt_qplib_map_creq_db(struct bnxt_qplib_rcfw *rcfw, u32 reg_offt) 1108 { 1109 struct bnxt_qplib_creq_db *creq_db; 1110 resource_size_t bar_reg; 1111 struct pci_dev *pdev; 1112 1113 pdev = rcfw->pdev; 1114 creq_db = &rcfw->creq.creq_db; 1115 1116 creq_db->dbinfo.flags = 0; 1117 creq_db->reg.bar_id = RCFW_COMM_CONS_PCI_BAR_REGION; 1118 creq_db->reg.bar_base = pci_resource_start(pdev, creq_db->reg.bar_id); 1119 if (!creq_db->reg.bar_id) 1120 dev_err(&pdev->dev, 1121 "QPLIB: CREQ BAR region %d resc start is 0!", 1122 creq_db->reg.bar_id); 1123 1124 bar_reg = creq_db->reg.bar_base + reg_offt; 1125 /* Unconditionally map 8 bytes to support 57500 series */ 1126 creq_db->reg.len = 8; 1127 creq_db->reg.bar_reg = ioremap(bar_reg, creq_db->reg.len); 1128 if (!creq_db->reg.bar_reg) { 1129 dev_err(&pdev->dev, 1130 "QPLIB: CREQ BAR region %d mapping failed", 1131 creq_db->reg.bar_id); 1132 return -ENOMEM; 1133 } 1134 creq_db->dbinfo.db = creq_db->reg.bar_reg; 1135 creq_db->dbinfo.hwq = &rcfw->creq.hwq; 1136 creq_db->dbinfo.xid = rcfw->creq.ring_id; 1137 return 0; 1138 } 1139 1140 static void bnxt_qplib_start_rcfw(struct bnxt_qplib_rcfw *rcfw) 1141 { 1142 struct bnxt_qplib_cmdq_ctx *cmdq; 1143 struct bnxt_qplib_creq_ctx *creq; 1144 struct bnxt_qplib_cmdq_mbox *mbox; 1145 struct cmdq_init init = {0}; 1146 1147 cmdq = &rcfw->cmdq; 1148 creq = &rcfw->creq; 1149 mbox = &cmdq->cmdq_mbox; 1150 1151 init.cmdq_pbl = cpu_to_le64(cmdq->hwq.pbl[PBL_LVL_0].pg_map_arr[0]); 1152 init.cmdq_size_cmdq_lvl = 1153 cpu_to_le16(((rcfw->cmdq_depth << 1154 CMDQ_INIT_CMDQ_SIZE_SFT) & 1155 CMDQ_INIT_CMDQ_SIZE_MASK) | 1156 ((cmdq->hwq.level << 1157 CMDQ_INIT_CMDQ_LVL_SFT) & 1158 CMDQ_INIT_CMDQ_LVL_MASK)); 1159 init.creq_ring_id = cpu_to_le16(creq->ring_id); 1160 /* Write to the Bono mailbox register */ 1161 __iowrite32_copy(mbox->reg.bar_reg, &init, sizeof(init) / 4); 1162 } 1163 1164 int bnxt_qplib_enable_rcfw_channel(struct bnxt_qplib_rcfw *rcfw, 1165 int msix_vector, 1166 int cp_bar_reg_off, 1167 aeq_handler_t aeq_handler) 1168 { 1169 struct bnxt_qplib_cmdq_ctx *cmdq; 1170 struct bnxt_qplib_creq_ctx *creq; 1171 int rc; 1172 1173 cmdq = &rcfw->cmdq; 1174 creq = &rcfw->creq; 1175 1176 /* Clear to defaults */ 1177 1178 cmdq->seq_num = 0; 1179 set_bit(FIRMWARE_FIRST_FLAG, &cmdq->flags); 1180 init_waitqueue_head(&cmdq->waitq); 1181 1182 creq->stats.creq_qp_event_processed = 0; 1183 creq->stats.creq_func_event_processed = 0; 1184 creq->aeq_handler = aeq_handler; 1185 1186 rc = bnxt_qplib_map_cmdq_mbox(rcfw); 1187 if (rc) 1188 return rc; 1189 1190 rc = bnxt_qplib_map_creq_db(rcfw, cp_bar_reg_off); 1191 if (rc) 1192 return rc; 1193 1194 rc = bnxt_qplib_rcfw_start_irq(rcfw, msix_vector, true); 1195 if (rc) { 1196 dev_err(&rcfw->pdev->dev, 1197 "Failed to request IRQ for CREQ rc = 0x%x\n", rc); 1198 bnxt_qplib_disable_rcfw_channel(rcfw); 1199 return rc; 1200 } 1201 1202 sema_init(&rcfw->rcfw_inflight, RCFW_CMD_NON_BLOCKING_SHADOW_QD); 1203 bnxt_qplib_start_rcfw(rcfw); 1204 1205 return 0; 1206 } 1207