1 /* 2 * Broadcom NetXtreme-E RoCE driver. 3 * 4 * Copyright (c) 2016 - 2017, Broadcom. All rights reserved. The term 5 * Broadcom refers to Broadcom Limited and/or its subsidiaries. 6 * 7 * This software is available to you under a choice of one of two 8 * licenses. You may choose to be licensed under the terms of the GNU 9 * General Public License (GPL) Version 2, available from the file 10 * COPYING in the main directory of this source tree, or the 11 * BSD license below: 12 * 13 * Redistribution and use in source and binary forms, with or without 14 * modification, are permitted provided that the following conditions 15 * are met: 16 * 17 * 1. Redistributions of source code must retain the above copyright 18 * notice, this list of conditions and the following disclaimer. 19 * 2. Redistributions in binary form must reproduce the above copyright 20 * notice, this list of conditions and the following disclaimer in 21 * the documentation and/or other materials provided with the 22 * distribution. 23 * 24 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' 25 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, 26 * THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR 27 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS 28 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 29 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 30 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR 31 * BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, 32 * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE 33 * OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN 34 * IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 35 * 36 * Description: RDMA Controller HW interface 37 */ 38 39 #define dev_fmt(fmt) "QPLIB: " fmt 40 41 #include <linux/interrupt.h> 42 #include <linux/spinlock.h> 43 #include <linux/pci.h> 44 #include <linux/prefetch.h> 45 #include <linux/delay.h> 46 47 #include "roce_hsi.h" 48 #include "qplib_res.h" 49 #include "qplib_rcfw.h" 50 #include "qplib_sp.h" 51 #include "qplib_fp.h" 52 53 static void bnxt_qplib_service_creq(unsigned long data); 54 55 /* Hardware communication channel */ 56 static int __wait_for_resp(struct bnxt_qplib_rcfw *rcfw, u16 cookie) 57 { 58 struct bnxt_qplib_cmdq_ctx *cmdq; 59 u16 cbit; 60 int rc; 61 62 cmdq = &rcfw->cmdq; 63 cbit = cookie % rcfw->cmdq_depth; 64 rc = wait_event_timeout(cmdq->waitq, 65 !test_bit(cbit, cmdq->cmdq_bitmap), 66 msecs_to_jiffies(RCFW_CMD_WAIT_TIME_MS)); 67 return rc ? 0 : -ETIMEDOUT; 68 }; 69 70 static int __block_for_resp(struct bnxt_qplib_rcfw *rcfw, u16 cookie) 71 { 72 u32 count = RCFW_BLOCKED_CMD_WAIT_COUNT; 73 struct bnxt_qplib_cmdq_ctx *cmdq; 74 u16 cbit; 75 76 cmdq = &rcfw->cmdq; 77 cbit = cookie % rcfw->cmdq_depth; 78 if (!test_bit(cbit, cmdq->cmdq_bitmap)) 79 goto done; 80 do { 81 mdelay(1); /* 1m sec */ 82 bnxt_qplib_service_creq((unsigned long)rcfw); 83 } while (test_bit(cbit, cmdq->cmdq_bitmap) && --count); 84 done: 85 return count ? 0 : -ETIMEDOUT; 86 }; 87 88 static int __send_message(struct bnxt_qplib_rcfw *rcfw, struct cmdq_base *req, 89 struct creq_base *resp, void *sb, u8 is_block) 90 { 91 struct bnxt_qplib_cmdq_ctx *cmdq = &rcfw->cmdq; 92 struct bnxt_qplib_hwq *hwq = &cmdq->hwq; 93 struct bnxt_qplib_crsqe *crsqe; 94 struct bnxt_qplib_cmdqe *cmdqe; 95 u32 sw_prod, cmdq_prod; 96 struct pci_dev *pdev; 97 unsigned long flags; 98 u32 size, opcode; 99 u16 cookie, cbit; 100 u8 *preq; 101 102 pdev = rcfw->pdev; 103 104 opcode = req->opcode; 105 if (!test_bit(FIRMWARE_INITIALIZED_FLAG, &cmdq->flags) && 106 (opcode != CMDQ_BASE_OPCODE_QUERY_FUNC && 107 opcode != CMDQ_BASE_OPCODE_INITIALIZE_FW && 108 opcode != CMDQ_BASE_OPCODE_QUERY_VERSION)) { 109 dev_err(&pdev->dev, 110 "RCFW not initialized, reject opcode 0x%x\n", opcode); 111 return -EINVAL; 112 } 113 114 if (test_bit(FIRMWARE_INITIALIZED_FLAG, &cmdq->flags) && 115 opcode == CMDQ_BASE_OPCODE_INITIALIZE_FW) { 116 dev_err(&pdev->dev, "RCFW already initialized!\n"); 117 return -EINVAL; 118 } 119 120 if (test_bit(FIRMWARE_TIMED_OUT, &cmdq->flags)) 121 return -ETIMEDOUT; 122 123 /* Cmdq are in 16-byte units, each request can consume 1 or more 124 * cmdqe 125 */ 126 spin_lock_irqsave(&hwq->lock, flags); 127 if (req->cmd_size >= HWQ_FREE_SLOTS(hwq)) { 128 dev_err(&pdev->dev, "RCFW: CMDQ is full!\n"); 129 spin_unlock_irqrestore(&hwq->lock, flags); 130 return -EAGAIN; 131 } 132 133 134 cookie = cmdq->seq_num & RCFW_MAX_COOKIE_VALUE; 135 cbit = cookie % rcfw->cmdq_depth; 136 if (is_block) 137 cookie |= RCFW_CMD_IS_BLOCKING; 138 139 set_bit(cbit, cmdq->cmdq_bitmap); 140 req->cookie = cpu_to_le16(cookie); 141 crsqe = &rcfw->crsqe_tbl[cbit]; 142 if (crsqe->resp) { 143 spin_unlock_irqrestore(&hwq->lock, flags); 144 return -EBUSY; 145 } 146 147 size = req->cmd_size; 148 /* change the cmd_size to the number of 16byte cmdq unit. 149 * req->cmd_size is modified here 150 */ 151 bnxt_qplib_set_cmd_slots(req); 152 153 memset(resp, 0, sizeof(*resp)); 154 crsqe->resp = (struct creq_qp_event *)resp; 155 crsqe->resp->cookie = req->cookie; 156 crsqe->req_size = req->cmd_size; 157 if (req->resp_size && sb) { 158 struct bnxt_qplib_rcfw_sbuf *sbuf = sb; 159 160 req->resp_addr = cpu_to_le64(sbuf->dma_addr); 161 req->resp_size = (sbuf->size + BNXT_QPLIB_CMDQE_UNITS - 1) / 162 BNXT_QPLIB_CMDQE_UNITS; 163 } 164 165 preq = (u8 *)req; 166 do { 167 /* Locate the next cmdq slot */ 168 sw_prod = HWQ_CMP(hwq->prod, hwq); 169 cmdqe = bnxt_qplib_get_qe(hwq, sw_prod, NULL); 170 if (!cmdqe) { 171 dev_err(&pdev->dev, 172 "RCFW request failed with no cmdqe!\n"); 173 goto done; 174 } 175 /* Copy a segment of the req cmd to the cmdq */ 176 memset(cmdqe, 0, sizeof(*cmdqe)); 177 memcpy(cmdqe, preq, min_t(u32, size, sizeof(*cmdqe))); 178 preq += min_t(u32, size, sizeof(*cmdqe)); 179 size -= min_t(u32, size, sizeof(*cmdqe)); 180 hwq->prod++; 181 } while (size > 0); 182 cmdq->seq_num++; 183 184 cmdq_prod = hwq->prod; 185 if (test_bit(FIRMWARE_FIRST_FLAG, &cmdq->flags)) { 186 /* The very first doorbell write 187 * is required to set this flag 188 * which prompts the FW to reset 189 * its internal pointers 190 */ 191 cmdq_prod |= BIT(FIRMWARE_FIRST_FLAG); 192 clear_bit(FIRMWARE_FIRST_FLAG, &cmdq->flags); 193 } 194 195 /* ring CMDQ DB */ 196 wmb(); 197 writel(cmdq_prod, cmdq->cmdq_mbox.prod); 198 writel(RCFW_CMDQ_TRIG_VAL, cmdq->cmdq_mbox.db); 199 done: 200 spin_unlock_irqrestore(&hwq->lock, flags); 201 /* Return the CREQ response pointer */ 202 return 0; 203 } 204 205 int bnxt_qplib_rcfw_send_message(struct bnxt_qplib_rcfw *rcfw, 206 struct cmdq_base *req, 207 struct creq_base *resp, 208 void *sb, u8 is_block) 209 { 210 struct creq_qp_event *evnt = (struct creq_qp_event *)resp; 211 u16 cookie; 212 u8 opcode, retry_cnt = 0xFF; 213 int rc = 0; 214 215 do { 216 opcode = req->opcode; 217 rc = __send_message(rcfw, req, resp, sb, is_block); 218 cookie = le16_to_cpu(req->cookie) & RCFW_MAX_COOKIE_VALUE; 219 if (!rc) 220 break; 221 222 if (!retry_cnt || (rc != -EAGAIN && rc != -EBUSY)) { 223 /* send failed */ 224 dev_err(&rcfw->pdev->dev, "cmdq[%#x]=%#x send failed\n", 225 cookie, opcode); 226 return rc; 227 } 228 is_block ? mdelay(1) : usleep_range(500, 1000); 229 230 } while (retry_cnt--); 231 232 if (is_block) 233 rc = __block_for_resp(rcfw, cookie); 234 else 235 rc = __wait_for_resp(rcfw, cookie); 236 if (rc) { 237 /* timed out */ 238 dev_err(&rcfw->pdev->dev, "cmdq[%#x]=%#x timedout (%d)msec\n", 239 cookie, opcode, RCFW_CMD_WAIT_TIME_MS); 240 set_bit(FIRMWARE_TIMED_OUT, &rcfw->cmdq.flags); 241 return rc; 242 } 243 244 if (evnt->status) { 245 /* failed with status */ 246 dev_err(&rcfw->pdev->dev, "cmdq[%#x]=%#x status %#x\n", 247 cookie, opcode, evnt->status); 248 rc = -EFAULT; 249 } 250 251 return rc; 252 } 253 /* Completions */ 254 static int bnxt_qplib_process_func_event(struct bnxt_qplib_rcfw *rcfw, 255 struct creq_func_event *func_event) 256 { 257 int rc; 258 259 switch (func_event->event) { 260 case CREQ_FUNC_EVENT_EVENT_TX_WQE_ERROR: 261 break; 262 case CREQ_FUNC_EVENT_EVENT_TX_DATA_ERROR: 263 break; 264 case CREQ_FUNC_EVENT_EVENT_RX_WQE_ERROR: 265 break; 266 case CREQ_FUNC_EVENT_EVENT_RX_DATA_ERROR: 267 break; 268 case CREQ_FUNC_EVENT_EVENT_CQ_ERROR: 269 break; 270 case CREQ_FUNC_EVENT_EVENT_TQM_ERROR: 271 break; 272 case CREQ_FUNC_EVENT_EVENT_CFCQ_ERROR: 273 break; 274 case CREQ_FUNC_EVENT_EVENT_CFCS_ERROR: 275 /* SRQ ctx error, call srq_handler?? 276 * But there's no SRQ handle! 277 */ 278 break; 279 case CREQ_FUNC_EVENT_EVENT_CFCC_ERROR: 280 break; 281 case CREQ_FUNC_EVENT_EVENT_CFCM_ERROR: 282 break; 283 case CREQ_FUNC_EVENT_EVENT_TIM_ERROR: 284 break; 285 case CREQ_FUNC_EVENT_EVENT_VF_COMM_REQUEST: 286 break; 287 case CREQ_FUNC_EVENT_EVENT_RESOURCE_EXHAUSTED: 288 break; 289 default: 290 return -EINVAL; 291 } 292 293 rc = rcfw->creq.aeq_handler(rcfw, (void *)func_event, NULL); 294 return rc; 295 } 296 297 static int bnxt_qplib_process_qp_event(struct bnxt_qplib_rcfw *rcfw, 298 struct creq_qp_event *qp_event) 299 { 300 struct creq_qp_error_notification *err_event; 301 struct bnxt_qplib_hwq *hwq = &rcfw->cmdq.hwq; 302 struct bnxt_qplib_crsqe *crsqe; 303 struct bnxt_qplib_qp *qp; 304 u16 cbit, blocked = 0; 305 struct pci_dev *pdev; 306 unsigned long flags; 307 __le16 mcookie; 308 u16 cookie; 309 int rc = 0; 310 u32 qp_id; 311 312 pdev = rcfw->pdev; 313 switch (qp_event->event) { 314 case CREQ_QP_EVENT_EVENT_QP_ERROR_NOTIFICATION: 315 err_event = (struct creq_qp_error_notification *)qp_event; 316 qp_id = le32_to_cpu(err_event->xid); 317 qp = rcfw->qp_tbl[qp_id].qp_handle; 318 dev_dbg(&pdev->dev, "Received QP error notification\n"); 319 dev_dbg(&pdev->dev, 320 "qpid 0x%x, req_err=0x%x, resp_err=0x%x\n", 321 qp_id, err_event->req_err_state_reason, 322 err_event->res_err_state_reason); 323 if (!qp) 324 break; 325 bnxt_qplib_mark_qp_error(qp); 326 rc = rcfw->creq.aeq_handler(rcfw, qp_event, qp); 327 break; 328 default: 329 /* 330 * Command Response 331 * cmdq->lock needs to be acquired to synchronie 332 * the command send and completion reaping. This function 333 * is always called with creq->lock held. Using 334 * the nested variant of spin_lock. 335 * 336 */ 337 338 spin_lock_irqsave_nested(&hwq->lock, flags, 339 SINGLE_DEPTH_NESTING); 340 cookie = le16_to_cpu(qp_event->cookie); 341 mcookie = qp_event->cookie; 342 blocked = cookie & RCFW_CMD_IS_BLOCKING; 343 cookie &= RCFW_MAX_COOKIE_VALUE; 344 cbit = cookie % rcfw->cmdq_depth; 345 crsqe = &rcfw->crsqe_tbl[cbit]; 346 if (crsqe->resp && 347 crsqe->resp->cookie == mcookie) { 348 memcpy(crsqe->resp, qp_event, sizeof(*qp_event)); 349 crsqe->resp = NULL; 350 } else { 351 if (crsqe->resp && crsqe->resp->cookie) 352 dev_err(&pdev->dev, 353 "CMD %s cookie sent=%#x, recd=%#x\n", 354 crsqe->resp ? "mismatch" : "collision", 355 crsqe->resp ? crsqe->resp->cookie : 0, 356 mcookie); 357 } 358 if (!test_and_clear_bit(cbit, rcfw->cmdq.cmdq_bitmap)) 359 dev_warn(&pdev->dev, 360 "CMD bit %d was not requested\n", cbit); 361 hwq->cons += crsqe->req_size; 362 crsqe->req_size = 0; 363 364 if (!blocked) 365 wake_up(&rcfw->cmdq.waitq); 366 spin_unlock_irqrestore(&hwq->lock, flags); 367 } 368 return rc; 369 } 370 371 /* SP - CREQ Completion handlers */ 372 static void bnxt_qplib_service_creq(unsigned long data) 373 { 374 struct bnxt_qplib_rcfw *rcfw = (struct bnxt_qplib_rcfw *)data; 375 struct bnxt_qplib_creq_ctx *creq = &rcfw->creq; 376 u32 type, budget = CREQ_ENTRY_POLL_BUDGET; 377 struct bnxt_qplib_hwq *hwq = &creq->hwq; 378 struct creq_base *creqe; 379 u32 sw_cons, raw_cons; 380 unsigned long flags; 381 382 /* Service the CREQ until budget is over */ 383 spin_lock_irqsave(&hwq->lock, flags); 384 raw_cons = hwq->cons; 385 while (budget > 0) { 386 sw_cons = HWQ_CMP(raw_cons, hwq); 387 creqe = bnxt_qplib_get_qe(hwq, sw_cons, NULL); 388 if (!CREQ_CMP_VALID(creqe, raw_cons, hwq->max_elements)) 389 break; 390 /* The valid test of the entry must be done first before 391 * reading any further. 392 */ 393 dma_rmb(); 394 395 type = creqe->type & CREQ_BASE_TYPE_MASK; 396 switch (type) { 397 case CREQ_BASE_TYPE_QP_EVENT: 398 bnxt_qplib_process_qp_event 399 (rcfw, (struct creq_qp_event *)creqe); 400 creq->stats.creq_qp_event_processed++; 401 break; 402 case CREQ_BASE_TYPE_FUNC_EVENT: 403 if (!bnxt_qplib_process_func_event 404 (rcfw, (struct creq_func_event *)creqe)) 405 creq->stats.creq_func_event_processed++; 406 else 407 dev_warn(&rcfw->pdev->dev, 408 "aeqe:%#x Not handled\n", type); 409 break; 410 default: 411 if (type != ASYNC_EVENT_CMPL_TYPE_HWRM_ASYNC_EVENT) 412 dev_warn(&rcfw->pdev->dev, 413 "creqe with event 0x%x not handled\n", 414 type); 415 break; 416 } 417 raw_cons++; 418 budget--; 419 } 420 421 if (hwq->cons != raw_cons) { 422 hwq->cons = raw_cons; 423 bnxt_qplib_ring_nq_db(&creq->creq_db.dbinfo, 424 rcfw->res->cctx, true); 425 } 426 spin_unlock_irqrestore(&hwq->lock, flags); 427 } 428 429 static irqreturn_t bnxt_qplib_creq_irq(int irq, void *dev_instance) 430 { 431 struct bnxt_qplib_rcfw *rcfw = dev_instance; 432 struct bnxt_qplib_creq_ctx *creq; 433 struct bnxt_qplib_hwq *hwq; 434 u32 sw_cons; 435 436 creq = &rcfw->creq; 437 hwq = &creq->hwq; 438 /* Prefetch the CREQ element */ 439 sw_cons = HWQ_CMP(hwq->cons, hwq); 440 prefetch(bnxt_qplib_get_qe(hwq, sw_cons, NULL)); 441 442 tasklet_schedule(&creq->creq_tasklet); 443 444 return IRQ_HANDLED; 445 } 446 447 /* RCFW */ 448 int bnxt_qplib_deinit_rcfw(struct bnxt_qplib_rcfw *rcfw) 449 { 450 struct cmdq_deinitialize_fw req; 451 struct creq_deinitialize_fw_resp resp; 452 u16 cmd_flags = 0; 453 int rc; 454 455 RCFW_CMD_PREP(req, DEINITIALIZE_FW, cmd_flags); 456 rc = bnxt_qplib_rcfw_send_message(rcfw, (void *)&req, (void *)&resp, 457 NULL, 0); 458 if (rc) 459 return rc; 460 461 clear_bit(FIRMWARE_INITIALIZED_FLAG, &rcfw->cmdq.flags); 462 return 0; 463 } 464 465 int bnxt_qplib_init_rcfw(struct bnxt_qplib_rcfw *rcfw, 466 struct bnxt_qplib_ctx *ctx, int is_virtfn) 467 { 468 struct creq_initialize_fw_resp resp; 469 struct cmdq_initialize_fw req; 470 u16 cmd_flags = 0; 471 u8 pgsz, lvl; 472 int rc; 473 474 RCFW_CMD_PREP(req, INITIALIZE_FW, cmd_flags); 475 /* Supply (log-base-2-of-host-page-size - base-page-shift) 476 * to bono to adjust the doorbell page sizes. 477 */ 478 req.log2_dbr_pg_size = cpu_to_le16(PAGE_SHIFT - 479 RCFW_DBR_BASE_PAGE_SHIFT); 480 /* 481 * Gen P5 devices doesn't require this allocation 482 * as the L2 driver does the same for RoCE also. 483 * Also, VFs need not setup the HW context area, PF 484 * shall setup this area for VF. Skipping the 485 * HW programming 486 */ 487 if (is_virtfn) 488 goto skip_ctx_setup; 489 if (bnxt_qplib_is_chip_gen_p5(rcfw->res->cctx)) 490 goto config_vf_res; 491 492 lvl = ctx->qpc_tbl.level; 493 pgsz = bnxt_qplib_base_pg_size(&ctx->qpc_tbl); 494 req.qpc_pg_size_qpc_lvl = (pgsz << CMDQ_INITIALIZE_FW_QPC_PG_SIZE_SFT) | 495 lvl; 496 lvl = ctx->mrw_tbl.level; 497 pgsz = bnxt_qplib_base_pg_size(&ctx->mrw_tbl); 498 req.mrw_pg_size_mrw_lvl = (pgsz << CMDQ_INITIALIZE_FW_QPC_PG_SIZE_SFT) | 499 lvl; 500 lvl = ctx->srqc_tbl.level; 501 pgsz = bnxt_qplib_base_pg_size(&ctx->srqc_tbl); 502 req.srq_pg_size_srq_lvl = (pgsz << CMDQ_INITIALIZE_FW_QPC_PG_SIZE_SFT) | 503 lvl; 504 lvl = ctx->cq_tbl.level; 505 pgsz = bnxt_qplib_base_pg_size(&ctx->cq_tbl); 506 req.cq_pg_size_cq_lvl = (pgsz << CMDQ_INITIALIZE_FW_QPC_PG_SIZE_SFT) | 507 lvl; 508 lvl = ctx->tim_tbl.level; 509 pgsz = bnxt_qplib_base_pg_size(&ctx->tim_tbl); 510 req.tim_pg_size_tim_lvl = (pgsz << CMDQ_INITIALIZE_FW_QPC_PG_SIZE_SFT) | 511 lvl; 512 lvl = ctx->tqm_ctx.pde.level; 513 pgsz = bnxt_qplib_base_pg_size(&ctx->tqm_ctx.pde); 514 req.tqm_pg_size_tqm_lvl = (pgsz << CMDQ_INITIALIZE_FW_QPC_PG_SIZE_SFT) | 515 lvl; 516 req.qpc_page_dir = 517 cpu_to_le64(ctx->qpc_tbl.pbl[PBL_LVL_0].pg_map_arr[0]); 518 req.mrw_page_dir = 519 cpu_to_le64(ctx->mrw_tbl.pbl[PBL_LVL_0].pg_map_arr[0]); 520 req.srq_page_dir = 521 cpu_to_le64(ctx->srqc_tbl.pbl[PBL_LVL_0].pg_map_arr[0]); 522 req.cq_page_dir = 523 cpu_to_le64(ctx->cq_tbl.pbl[PBL_LVL_0].pg_map_arr[0]); 524 req.tim_page_dir = 525 cpu_to_le64(ctx->tim_tbl.pbl[PBL_LVL_0].pg_map_arr[0]); 526 req.tqm_page_dir = 527 cpu_to_le64(ctx->tqm_ctx.pde.pbl[PBL_LVL_0].pg_map_arr[0]); 528 529 req.number_of_qp = cpu_to_le32(ctx->qpc_tbl.max_elements); 530 req.number_of_mrw = cpu_to_le32(ctx->mrw_tbl.max_elements); 531 req.number_of_srq = cpu_to_le32(ctx->srqc_tbl.max_elements); 532 req.number_of_cq = cpu_to_le32(ctx->cq_tbl.max_elements); 533 534 config_vf_res: 535 req.max_qp_per_vf = cpu_to_le32(ctx->vf_res.max_qp_per_vf); 536 req.max_mrw_per_vf = cpu_to_le32(ctx->vf_res.max_mrw_per_vf); 537 req.max_srq_per_vf = cpu_to_le32(ctx->vf_res.max_srq_per_vf); 538 req.max_cq_per_vf = cpu_to_le32(ctx->vf_res.max_cq_per_vf); 539 req.max_gid_per_vf = cpu_to_le32(ctx->vf_res.max_gid_per_vf); 540 541 skip_ctx_setup: 542 req.stat_ctx_id = cpu_to_le32(ctx->stats.fw_id); 543 rc = bnxt_qplib_rcfw_send_message(rcfw, (void *)&req, (void *)&resp, 544 NULL, 0); 545 if (rc) 546 return rc; 547 set_bit(FIRMWARE_INITIALIZED_FLAG, &rcfw->cmdq.flags); 548 return 0; 549 } 550 551 void bnxt_qplib_free_rcfw_channel(struct bnxt_qplib_rcfw *rcfw) 552 { 553 kfree(rcfw->cmdq.cmdq_bitmap); 554 kfree(rcfw->qp_tbl); 555 kfree(rcfw->crsqe_tbl); 556 bnxt_qplib_free_hwq(rcfw->res, &rcfw->cmdq.hwq); 557 bnxt_qplib_free_hwq(rcfw->res, &rcfw->creq.hwq); 558 rcfw->pdev = NULL; 559 } 560 561 int bnxt_qplib_alloc_rcfw_channel(struct bnxt_qplib_res *res, 562 struct bnxt_qplib_rcfw *rcfw, 563 struct bnxt_qplib_ctx *ctx, 564 int qp_tbl_sz) 565 { 566 struct bnxt_qplib_hwq_attr hwq_attr = {}; 567 struct bnxt_qplib_sg_info sginfo = {}; 568 struct bnxt_qplib_cmdq_ctx *cmdq; 569 struct bnxt_qplib_creq_ctx *creq; 570 u32 bmap_size = 0; 571 572 rcfw->pdev = res->pdev; 573 cmdq = &rcfw->cmdq; 574 creq = &rcfw->creq; 575 rcfw->res = res; 576 577 sginfo.pgsize = PAGE_SIZE; 578 sginfo.pgshft = PAGE_SHIFT; 579 580 hwq_attr.sginfo = &sginfo; 581 hwq_attr.res = rcfw->res; 582 hwq_attr.depth = BNXT_QPLIB_CREQE_MAX_CNT; 583 hwq_attr.stride = BNXT_QPLIB_CREQE_UNITS; 584 hwq_attr.type = bnxt_qplib_get_hwq_type(res); 585 586 if (bnxt_qplib_alloc_init_hwq(&creq->hwq, &hwq_attr)) { 587 dev_err(&rcfw->pdev->dev, 588 "HW channel CREQ allocation failed\n"); 589 goto fail; 590 } 591 if (ctx->hwrm_intf_ver < HWRM_VERSION_RCFW_CMDQ_DEPTH_CHECK) 592 rcfw->cmdq_depth = BNXT_QPLIB_CMDQE_MAX_CNT_256; 593 else 594 rcfw->cmdq_depth = BNXT_QPLIB_CMDQE_MAX_CNT_8192; 595 596 sginfo.pgsize = bnxt_qplib_cmdqe_page_size(rcfw->cmdq_depth); 597 hwq_attr.depth = rcfw->cmdq_depth; 598 hwq_attr.stride = BNXT_QPLIB_CMDQE_UNITS; 599 hwq_attr.type = HWQ_TYPE_CTX; 600 if (bnxt_qplib_alloc_init_hwq(&cmdq->hwq, &hwq_attr)) { 601 dev_err(&rcfw->pdev->dev, 602 "HW channel CMDQ allocation failed\n"); 603 goto fail; 604 } 605 606 rcfw->crsqe_tbl = kcalloc(cmdq->hwq.max_elements, 607 sizeof(*rcfw->crsqe_tbl), GFP_KERNEL); 608 if (!rcfw->crsqe_tbl) 609 goto fail; 610 611 bmap_size = BITS_TO_LONGS(rcfw->cmdq_depth) * sizeof(unsigned long); 612 cmdq->cmdq_bitmap = kzalloc(bmap_size, GFP_KERNEL); 613 if (!cmdq->cmdq_bitmap) 614 goto fail; 615 616 cmdq->bmap_size = bmap_size; 617 618 rcfw->qp_tbl_size = qp_tbl_sz; 619 rcfw->qp_tbl = kcalloc(qp_tbl_sz, sizeof(struct bnxt_qplib_qp_node), 620 GFP_KERNEL); 621 if (!rcfw->qp_tbl) 622 goto fail; 623 624 return 0; 625 626 fail: 627 bnxt_qplib_free_rcfw_channel(rcfw); 628 return -ENOMEM; 629 } 630 631 void bnxt_qplib_rcfw_stop_irq(struct bnxt_qplib_rcfw *rcfw, bool kill) 632 { 633 struct bnxt_qplib_creq_ctx *creq; 634 635 creq = &rcfw->creq; 636 tasklet_disable(&creq->creq_tasklet); 637 /* Mask h/w interrupts */ 638 bnxt_qplib_ring_nq_db(&creq->creq_db.dbinfo, rcfw->res->cctx, false); 639 /* Sync with last running IRQ-handler */ 640 synchronize_irq(creq->msix_vec); 641 if (kill) 642 tasklet_kill(&creq->creq_tasklet); 643 644 if (creq->requested) { 645 free_irq(creq->msix_vec, rcfw); 646 creq->requested = false; 647 } 648 } 649 650 void bnxt_qplib_disable_rcfw_channel(struct bnxt_qplib_rcfw *rcfw) 651 { 652 struct bnxt_qplib_creq_ctx *creq; 653 struct bnxt_qplib_cmdq_ctx *cmdq; 654 unsigned long indx; 655 656 creq = &rcfw->creq; 657 cmdq = &rcfw->cmdq; 658 /* Make sure the HW channel is stopped! */ 659 bnxt_qplib_rcfw_stop_irq(rcfw, true); 660 661 iounmap(cmdq->cmdq_mbox.reg.bar_reg); 662 iounmap(creq->creq_db.reg.bar_reg); 663 664 indx = find_first_bit(cmdq->cmdq_bitmap, cmdq->bmap_size); 665 if (indx != cmdq->bmap_size) 666 dev_err(&rcfw->pdev->dev, 667 "disabling RCFW with pending cmd-bit %lx\n", indx); 668 669 cmdq->cmdq_mbox.reg.bar_reg = NULL; 670 creq->creq_db.reg.bar_reg = NULL; 671 creq->aeq_handler = NULL; 672 creq->msix_vec = 0; 673 } 674 675 int bnxt_qplib_rcfw_start_irq(struct bnxt_qplib_rcfw *rcfw, int msix_vector, 676 bool need_init) 677 { 678 struct bnxt_qplib_creq_ctx *creq; 679 int rc; 680 681 creq = &rcfw->creq; 682 683 if (creq->requested) 684 return -EFAULT; 685 686 creq->msix_vec = msix_vector; 687 if (need_init) 688 tasklet_init(&creq->creq_tasklet, 689 bnxt_qplib_service_creq, (unsigned long)rcfw); 690 else 691 tasklet_enable(&creq->creq_tasklet); 692 rc = request_irq(creq->msix_vec, bnxt_qplib_creq_irq, 0, 693 "bnxt_qplib_creq", rcfw); 694 if (rc) 695 return rc; 696 creq->requested = true; 697 698 bnxt_qplib_ring_nq_db(&creq->creq_db.dbinfo, rcfw->res->cctx, true); 699 700 return 0; 701 } 702 703 static int bnxt_qplib_map_cmdq_mbox(struct bnxt_qplib_rcfw *rcfw, bool is_vf) 704 { 705 struct bnxt_qplib_cmdq_mbox *mbox; 706 resource_size_t bar_reg; 707 struct pci_dev *pdev; 708 u16 prod_offt; 709 int rc = 0; 710 711 pdev = rcfw->pdev; 712 mbox = &rcfw->cmdq.cmdq_mbox; 713 714 mbox->reg.bar_id = RCFW_COMM_PCI_BAR_REGION; 715 mbox->reg.len = RCFW_COMM_SIZE; 716 mbox->reg.bar_base = pci_resource_start(pdev, mbox->reg.bar_id); 717 if (!mbox->reg.bar_base) { 718 dev_err(&pdev->dev, 719 "QPLIB: CMDQ BAR region %d resc start is 0!\n", 720 mbox->reg.bar_id); 721 return -ENOMEM; 722 } 723 724 bar_reg = mbox->reg.bar_base + RCFW_COMM_BASE_OFFSET; 725 mbox->reg.len = RCFW_COMM_SIZE; 726 mbox->reg.bar_reg = ioremap(bar_reg, mbox->reg.len); 727 if (!mbox->reg.bar_reg) { 728 dev_err(&pdev->dev, 729 "QPLIB: CMDQ BAR region %d mapping failed\n", 730 mbox->reg.bar_id); 731 return -ENOMEM; 732 } 733 734 prod_offt = is_vf ? RCFW_VF_COMM_PROD_OFFSET : 735 RCFW_PF_COMM_PROD_OFFSET; 736 mbox->prod = (void __iomem *)(mbox->reg.bar_reg + prod_offt); 737 mbox->db = (void __iomem *)(mbox->reg.bar_reg + RCFW_COMM_TRIG_OFFSET); 738 return rc; 739 } 740 741 static int bnxt_qplib_map_creq_db(struct bnxt_qplib_rcfw *rcfw, u32 reg_offt) 742 { 743 struct bnxt_qplib_creq_db *creq_db; 744 resource_size_t bar_reg; 745 struct pci_dev *pdev; 746 747 pdev = rcfw->pdev; 748 creq_db = &rcfw->creq.creq_db; 749 750 creq_db->reg.bar_id = RCFW_COMM_CONS_PCI_BAR_REGION; 751 creq_db->reg.bar_base = pci_resource_start(pdev, creq_db->reg.bar_id); 752 if (!creq_db->reg.bar_id) 753 dev_err(&pdev->dev, 754 "QPLIB: CREQ BAR region %d resc start is 0!", 755 creq_db->reg.bar_id); 756 757 bar_reg = creq_db->reg.bar_base + reg_offt; 758 /* Unconditionally map 8 bytes to support 57500 series */ 759 creq_db->reg.len = 8; 760 creq_db->reg.bar_reg = ioremap(bar_reg, creq_db->reg.len); 761 if (!creq_db->reg.bar_reg) { 762 dev_err(&pdev->dev, 763 "QPLIB: CREQ BAR region %d mapping failed", 764 creq_db->reg.bar_id); 765 return -ENOMEM; 766 } 767 creq_db->dbinfo.db = creq_db->reg.bar_reg; 768 creq_db->dbinfo.hwq = &rcfw->creq.hwq; 769 creq_db->dbinfo.xid = rcfw->creq.ring_id; 770 return 0; 771 } 772 773 static void bnxt_qplib_start_rcfw(struct bnxt_qplib_rcfw *rcfw) 774 { 775 struct bnxt_qplib_cmdq_ctx *cmdq; 776 struct bnxt_qplib_creq_ctx *creq; 777 struct bnxt_qplib_cmdq_mbox *mbox; 778 struct cmdq_init init = {0}; 779 780 cmdq = &rcfw->cmdq; 781 creq = &rcfw->creq; 782 mbox = &cmdq->cmdq_mbox; 783 784 init.cmdq_pbl = cpu_to_le64(cmdq->hwq.pbl[PBL_LVL_0].pg_map_arr[0]); 785 init.cmdq_size_cmdq_lvl = 786 cpu_to_le16(((rcfw->cmdq_depth << 787 CMDQ_INIT_CMDQ_SIZE_SFT) & 788 CMDQ_INIT_CMDQ_SIZE_MASK) | 789 ((cmdq->hwq.level << 790 CMDQ_INIT_CMDQ_LVL_SFT) & 791 CMDQ_INIT_CMDQ_LVL_MASK)); 792 init.creq_ring_id = cpu_to_le16(creq->ring_id); 793 /* Write to the Bono mailbox register */ 794 __iowrite32_copy(mbox->reg.bar_reg, &init, sizeof(init) / 4); 795 } 796 797 int bnxt_qplib_enable_rcfw_channel(struct bnxt_qplib_rcfw *rcfw, 798 int msix_vector, 799 int cp_bar_reg_off, int virt_fn, 800 aeq_handler_t aeq_handler) 801 { 802 struct bnxt_qplib_cmdq_ctx *cmdq; 803 struct bnxt_qplib_creq_ctx *creq; 804 int rc; 805 806 cmdq = &rcfw->cmdq; 807 creq = &rcfw->creq; 808 809 /* Clear to defaults */ 810 811 cmdq->seq_num = 0; 812 set_bit(FIRMWARE_FIRST_FLAG, &cmdq->flags); 813 init_waitqueue_head(&cmdq->waitq); 814 815 creq->stats.creq_qp_event_processed = 0; 816 creq->stats.creq_func_event_processed = 0; 817 creq->aeq_handler = aeq_handler; 818 819 rc = bnxt_qplib_map_cmdq_mbox(rcfw, virt_fn); 820 if (rc) 821 return rc; 822 823 rc = bnxt_qplib_map_creq_db(rcfw, cp_bar_reg_off); 824 if (rc) 825 return rc; 826 827 rc = bnxt_qplib_rcfw_start_irq(rcfw, msix_vector, true); 828 if (rc) { 829 dev_err(&rcfw->pdev->dev, 830 "Failed to request IRQ for CREQ rc = 0x%x\n", rc); 831 bnxt_qplib_disable_rcfw_channel(rcfw); 832 return rc; 833 } 834 835 bnxt_qplib_start_rcfw(rcfw); 836 837 return 0; 838 } 839 840 struct bnxt_qplib_rcfw_sbuf *bnxt_qplib_rcfw_alloc_sbuf( 841 struct bnxt_qplib_rcfw *rcfw, 842 u32 size) 843 { 844 struct bnxt_qplib_rcfw_sbuf *sbuf; 845 846 sbuf = kzalloc(sizeof(*sbuf), GFP_ATOMIC); 847 if (!sbuf) 848 return NULL; 849 850 sbuf->size = size; 851 sbuf->sb = dma_alloc_coherent(&rcfw->pdev->dev, sbuf->size, 852 &sbuf->dma_addr, GFP_ATOMIC); 853 if (!sbuf->sb) 854 goto bail; 855 856 return sbuf; 857 bail: 858 kfree(sbuf); 859 return NULL; 860 } 861 862 void bnxt_qplib_rcfw_free_sbuf(struct bnxt_qplib_rcfw *rcfw, 863 struct bnxt_qplib_rcfw_sbuf *sbuf) 864 { 865 if (sbuf->sb) 866 dma_free_coherent(&rcfw->pdev->dev, sbuf->size, 867 sbuf->sb, sbuf->dma_addr); 868 kfree(sbuf); 869 } 870