1 /* 2 * Broadcom NetXtreme-E RoCE driver. 3 * 4 * Copyright (c) 2016 - 2017, Broadcom. All rights reserved. The term 5 * Broadcom refers to Broadcom Limited and/or its subsidiaries. 6 * 7 * This software is available to you under a choice of one of two 8 * licenses. You may choose to be licensed under the terms of the GNU 9 * General Public License (GPL) Version 2, available from the file 10 * COPYING in the main directory of this source tree, or the 11 * BSD license below: 12 * 13 * Redistribution and use in source and binary forms, with or without 14 * modification, are permitted provided that the following conditions 15 * are met: 16 * 17 * 1. Redistributions of source code must retain the above copyright 18 * notice, this list of conditions and the following disclaimer. 19 * 2. Redistributions in binary form must reproduce the above copyright 20 * notice, this list of conditions and the following disclaimer in 21 * the documentation and/or other materials provided with the 22 * distribution. 23 * 24 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' 25 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, 26 * THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR 27 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS 28 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 29 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 30 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR 31 * BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, 32 * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE 33 * OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN 34 * IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 35 * 36 * Description: RDMA Controller HW interface 37 */ 38 39 #define dev_fmt(fmt) "QPLIB: " fmt 40 41 #include <linux/interrupt.h> 42 #include <linux/spinlock.h> 43 #include <linux/pci.h> 44 #include <linux/prefetch.h> 45 #include <linux/delay.h> 46 47 #include "roce_hsi.h" 48 #include "qplib_res.h" 49 #include "qplib_rcfw.h" 50 #include "qplib_sp.h" 51 #include "qplib_fp.h" 52 #include "qplib_tlv.h" 53 54 static void bnxt_qplib_service_creq(struct tasklet_struct *t); 55 56 /* Hardware communication channel */ 57 static int __wait_for_resp(struct bnxt_qplib_rcfw *rcfw, u16 cookie) 58 { 59 struct bnxt_qplib_cmdq_ctx *cmdq; 60 u16 cbit; 61 int rc; 62 63 cmdq = &rcfw->cmdq; 64 cbit = cookie % rcfw->cmdq_depth; 65 rc = wait_event_timeout(cmdq->waitq, 66 !test_bit(cbit, cmdq->cmdq_bitmap), 67 msecs_to_jiffies(RCFW_CMD_WAIT_TIME_MS)); 68 return rc ? 0 : -ETIMEDOUT; 69 }; 70 71 static int __block_for_resp(struct bnxt_qplib_rcfw *rcfw, u16 cookie) 72 { 73 u32 count = RCFW_BLOCKED_CMD_WAIT_COUNT; 74 struct bnxt_qplib_cmdq_ctx *cmdq; 75 u16 cbit; 76 77 cmdq = &rcfw->cmdq; 78 cbit = cookie % rcfw->cmdq_depth; 79 if (!test_bit(cbit, cmdq->cmdq_bitmap)) 80 goto done; 81 do { 82 udelay(1); 83 bnxt_qplib_service_creq(&rcfw->creq.creq_tasklet); 84 } while (test_bit(cbit, cmdq->cmdq_bitmap) && --count); 85 done: 86 return count ? 0 : -ETIMEDOUT; 87 }; 88 89 static int __send_message(struct bnxt_qplib_rcfw *rcfw, 90 struct bnxt_qplib_cmdqmsg *msg) 91 { 92 struct bnxt_qplib_cmdq_ctx *cmdq = &rcfw->cmdq; 93 struct bnxt_qplib_hwq *hwq = &cmdq->hwq; 94 struct bnxt_qplib_crsqe *crsqe; 95 struct bnxt_qplib_cmdqe *cmdqe; 96 u32 sw_prod, cmdq_prod; 97 struct pci_dev *pdev; 98 unsigned long flags; 99 u32 bsize, opcode; 100 u16 cookie, cbit; 101 u8 *preq; 102 103 pdev = rcfw->pdev; 104 105 opcode = __get_cmdq_base_opcode(msg->req, msg->req_sz); 106 if (!test_bit(FIRMWARE_INITIALIZED_FLAG, &cmdq->flags) && 107 (opcode != CMDQ_BASE_OPCODE_QUERY_FUNC && 108 opcode != CMDQ_BASE_OPCODE_INITIALIZE_FW && 109 opcode != CMDQ_BASE_OPCODE_QUERY_VERSION)) { 110 dev_err(&pdev->dev, 111 "RCFW not initialized, reject opcode 0x%x\n", opcode); 112 return -EINVAL; 113 } 114 115 if (test_bit(FIRMWARE_INITIALIZED_FLAG, &cmdq->flags) && 116 opcode == CMDQ_BASE_OPCODE_INITIALIZE_FW) { 117 dev_err(&pdev->dev, "RCFW already initialized!\n"); 118 return -EINVAL; 119 } 120 121 if (test_bit(FIRMWARE_TIMED_OUT, &cmdq->flags)) 122 return -ETIMEDOUT; 123 124 /* Cmdq are in 16-byte units, each request can consume 1 or more 125 * cmdqe 126 */ 127 spin_lock_irqsave(&hwq->lock, flags); 128 if (msg->req->cmd_size >= HWQ_FREE_SLOTS(hwq)) { 129 dev_err(&pdev->dev, "RCFW: CMDQ is full!\n"); 130 spin_unlock_irqrestore(&hwq->lock, flags); 131 return -EAGAIN; 132 } 133 134 135 cookie = cmdq->seq_num & RCFW_MAX_COOKIE_VALUE; 136 cbit = cookie % rcfw->cmdq_depth; 137 if (msg->block) 138 cookie |= RCFW_CMD_IS_BLOCKING; 139 140 set_bit(cbit, cmdq->cmdq_bitmap); 141 __set_cmdq_base_cookie(msg->req, msg->req_sz, cpu_to_le16(cookie)); 142 crsqe = &rcfw->crsqe_tbl[cbit]; 143 if (crsqe->resp) { 144 spin_unlock_irqrestore(&hwq->lock, flags); 145 return -EBUSY; 146 } 147 148 /* change the cmd_size to the number of 16byte cmdq unit. 149 * req->cmd_size is modified here 150 */ 151 bsize = bnxt_qplib_set_cmd_slots(msg->req); 152 153 memset(msg->resp, 0, sizeof(*msg->resp)); 154 crsqe->resp = (struct creq_qp_event *)msg->resp; 155 crsqe->resp->cookie = cpu_to_le16(cookie); 156 crsqe->req_size = __get_cmdq_base_cmd_size(msg->req, msg->req_sz); 157 if (__get_cmdq_base_resp_size(msg->req, msg->req_sz) && msg->sb) { 158 struct bnxt_qplib_rcfw_sbuf *sbuf = msg->sb; 159 __set_cmdq_base_resp_addr(msg->req, msg->req_sz, cpu_to_le64(sbuf->dma_addr)); 160 __set_cmdq_base_resp_size(msg->req, msg->req_sz, 161 ALIGN(sbuf->size, BNXT_QPLIB_CMDQE_UNITS)); 162 } 163 164 preq = (u8 *)msg->req; 165 do { 166 /* Locate the next cmdq slot */ 167 sw_prod = HWQ_CMP(hwq->prod, hwq); 168 cmdqe = bnxt_qplib_get_qe(hwq, sw_prod, NULL); 169 if (!cmdqe) { 170 dev_err(&pdev->dev, 171 "RCFW request failed with no cmdqe!\n"); 172 goto done; 173 } 174 /* Copy a segment of the req cmd to the cmdq */ 175 memset(cmdqe, 0, sizeof(*cmdqe)); 176 memcpy(cmdqe, preq, min_t(u32, bsize, sizeof(*cmdqe))); 177 preq += min_t(u32, bsize, sizeof(*cmdqe)); 178 bsize -= min_t(u32, bsize, sizeof(*cmdqe)); 179 hwq->prod++; 180 } while (bsize > 0); 181 cmdq->seq_num++; 182 183 cmdq_prod = hwq->prod; 184 if (test_bit(FIRMWARE_FIRST_FLAG, &cmdq->flags)) { 185 /* The very first doorbell write 186 * is required to set this flag 187 * which prompts the FW to reset 188 * its internal pointers 189 */ 190 cmdq_prod |= BIT(FIRMWARE_FIRST_FLAG); 191 clear_bit(FIRMWARE_FIRST_FLAG, &cmdq->flags); 192 } 193 /* ring CMDQ DB */ 194 wmb(); 195 writel(cmdq_prod, cmdq->cmdq_mbox.prod); 196 writel(RCFW_CMDQ_TRIG_VAL, cmdq->cmdq_mbox.db); 197 done: 198 spin_unlock_irqrestore(&hwq->lock, flags); 199 /* Return the CREQ response pointer */ 200 return 0; 201 } 202 203 int bnxt_qplib_rcfw_send_message(struct bnxt_qplib_rcfw *rcfw, 204 struct bnxt_qplib_cmdqmsg *msg) 205 { 206 struct creq_qp_event *evnt = (struct creq_qp_event *)msg->resp; 207 u16 cookie; 208 u8 opcode, retry_cnt = 0xFF; 209 int rc = 0; 210 211 /* Prevent posting if f/w is not in a state to process */ 212 if (test_bit(ERR_DEVICE_DETACHED, &rcfw->cmdq.flags)) 213 return 0; 214 215 do { 216 opcode = __get_cmdq_base_opcode(msg->req, msg->req_sz); 217 rc = __send_message(rcfw, msg); 218 cookie = le16_to_cpu(__get_cmdq_base_cookie(msg->req, msg->req_sz)) & 219 RCFW_MAX_COOKIE_VALUE; 220 if (!rc) 221 break; 222 if (!retry_cnt || (rc != -EAGAIN && rc != -EBUSY)) { 223 /* send failed */ 224 dev_err(&rcfw->pdev->dev, "cmdq[%#x]=%#x send failed\n", 225 cookie, opcode); 226 return rc; 227 } 228 msg->block ? mdelay(1) : usleep_range(500, 1000); 229 230 } while (retry_cnt--); 231 232 if (msg->block) 233 rc = __block_for_resp(rcfw, cookie); 234 else 235 rc = __wait_for_resp(rcfw, cookie); 236 if (rc) { 237 /* timed out */ 238 dev_err(&rcfw->pdev->dev, "cmdq[%#x]=%#x timedout (%d)msec\n", 239 cookie, opcode, RCFW_CMD_WAIT_TIME_MS); 240 set_bit(FIRMWARE_TIMED_OUT, &rcfw->cmdq.flags); 241 return rc; 242 } 243 244 if (evnt->status) { 245 /* failed with status */ 246 dev_err(&rcfw->pdev->dev, "cmdq[%#x]=%#x status %#x\n", 247 cookie, opcode, evnt->status); 248 rc = -EFAULT; 249 } 250 251 return rc; 252 } 253 /* Completions */ 254 static int bnxt_qplib_process_func_event(struct bnxt_qplib_rcfw *rcfw, 255 struct creq_func_event *func_event) 256 { 257 int rc; 258 259 switch (func_event->event) { 260 case CREQ_FUNC_EVENT_EVENT_TX_WQE_ERROR: 261 break; 262 case CREQ_FUNC_EVENT_EVENT_TX_DATA_ERROR: 263 break; 264 case CREQ_FUNC_EVENT_EVENT_RX_WQE_ERROR: 265 break; 266 case CREQ_FUNC_EVENT_EVENT_RX_DATA_ERROR: 267 break; 268 case CREQ_FUNC_EVENT_EVENT_CQ_ERROR: 269 break; 270 case CREQ_FUNC_EVENT_EVENT_TQM_ERROR: 271 break; 272 case CREQ_FUNC_EVENT_EVENT_CFCQ_ERROR: 273 break; 274 case CREQ_FUNC_EVENT_EVENT_CFCS_ERROR: 275 /* SRQ ctx error, call srq_handler?? 276 * But there's no SRQ handle! 277 */ 278 break; 279 case CREQ_FUNC_EVENT_EVENT_CFCC_ERROR: 280 break; 281 case CREQ_FUNC_EVENT_EVENT_CFCM_ERROR: 282 break; 283 case CREQ_FUNC_EVENT_EVENT_TIM_ERROR: 284 break; 285 case CREQ_FUNC_EVENT_EVENT_VF_COMM_REQUEST: 286 break; 287 case CREQ_FUNC_EVENT_EVENT_RESOURCE_EXHAUSTED: 288 break; 289 default: 290 return -EINVAL; 291 } 292 293 rc = rcfw->creq.aeq_handler(rcfw, (void *)func_event, NULL); 294 return rc; 295 } 296 297 static int bnxt_qplib_process_qp_event(struct bnxt_qplib_rcfw *rcfw, 298 struct creq_qp_event *qp_event) 299 { 300 struct creq_qp_error_notification *err_event; 301 struct bnxt_qplib_hwq *hwq = &rcfw->cmdq.hwq; 302 struct bnxt_qplib_crsqe *crsqe; 303 struct bnxt_qplib_qp *qp; 304 u16 cbit, blocked = 0; 305 struct pci_dev *pdev; 306 unsigned long flags; 307 __le16 mcookie; 308 u16 cookie; 309 int rc = 0; 310 u32 qp_id, tbl_indx; 311 312 pdev = rcfw->pdev; 313 switch (qp_event->event) { 314 case CREQ_QP_EVENT_EVENT_QP_ERROR_NOTIFICATION: 315 err_event = (struct creq_qp_error_notification *)qp_event; 316 qp_id = le32_to_cpu(err_event->xid); 317 tbl_indx = map_qp_id_to_tbl_indx(qp_id, rcfw); 318 qp = rcfw->qp_tbl[tbl_indx].qp_handle; 319 dev_dbg(&pdev->dev, "Received QP error notification\n"); 320 dev_dbg(&pdev->dev, 321 "qpid 0x%x, req_err=0x%x, resp_err=0x%x\n", 322 qp_id, err_event->req_err_state_reason, 323 err_event->res_err_state_reason); 324 if (!qp) 325 break; 326 bnxt_qplib_mark_qp_error(qp); 327 rc = rcfw->creq.aeq_handler(rcfw, qp_event, qp); 328 break; 329 default: 330 /* 331 * Command Response 332 * cmdq->lock needs to be acquired to synchronie 333 * the command send and completion reaping. This function 334 * is always called with creq->lock held. Using 335 * the nested variant of spin_lock. 336 * 337 */ 338 339 spin_lock_irqsave_nested(&hwq->lock, flags, 340 SINGLE_DEPTH_NESTING); 341 cookie = le16_to_cpu(qp_event->cookie); 342 mcookie = qp_event->cookie; 343 blocked = cookie & RCFW_CMD_IS_BLOCKING; 344 cookie &= RCFW_MAX_COOKIE_VALUE; 345 cbit = cookie % rcfw->cmdq_depth; 346 crsqe = &rcfw->crsqe_tbl[cbit]; 347 if (crsqe->resp && 348 crsqe->resp->cookie == mcookie) { 349 memcpy(crsqe->resp, qp_event, sizeof(*qp_event)); 350 crsqe->resp = NULL; 351 } else { 352 if (crsqe->resp && crsqe->resp->cookie) 353 dev_err(&pdev->dev, 354 "CMD %s cookie sent=%#x, recd=%#x\n", 355 crsqe->resp ? "mismatch" : "collision", 356 crsqe->resp ? crsqe->resp->cookie : 0, 357 mcookie); 358 } 359 if (!test_and_clear_bit(cbit, rcfw->cmdq.cmdq_bitmap)) 360 dev_warn(&pdev->dev, 361 "CMD bit %d was not requested\n", cbit); 362 hwq->cons += crsqe->req_size; 363 crsqe->req_size = 0; 364 365 if (!blocked) 366 wake_up(&rcfw->cmdq.waitq); 367 spin_unlock_irqrestore(&hwq->lock, flags); 368 } 369 return rc; 370 } 371 372 /* SP - CREQ Completion handlers */ 373 static void bnxt_qplib_service_creq(struct tasklet_struct *t) 374 { 375 struct bnxt_qplib_rcfw *rcfw = from_tasklet(rcfw, t, creq.creq_tasklet); 376 struct bnxt_qplib_creq_ctx *creq = &rcfw->creq; 377 u32 type, budget = CREQ_ENTRY_POLL_BUDGET; 378 struct bnxt_qplib_hwq *hwq = &creq->hwq; 379 struct creq_base *creqe; 380 u32 sw_cons, raw_cons; 381 unsigned long flags; 382 383 /* Service the CREQ until budget is over */ 384 spin_lock_irqsave(&hwq->lock, flags); 385 raw_cons = hwq->cons; 386 while (budget > 0) { 387 sw_cons = HWQ_CMP(raw_cons, hwq); 388 creqe = bnxt_qplib_get_qe(hwq, sw_cons, NULL); 389 if (!CREQ_CMP_VALID(creqe, raw_cons, hwq->max_elements)) 390 break; 391 /* The valid test of the entry must be done first before 392 * reading any further. 393 */ 394 dma_rmb(); 395 396 type = creqe->type & CREQ_BASE_TYPE_MASK; 397 switch (type) { 398 case CREQ_BASE_TYPE_QP_EVENT: 399 bnxt_qplib_process_qp_event 400 (rcfw, (struct creq_qp_event *)creqe); 401 creq->stats.creq_qp_event_processed++; 402 break; 403 case CREQ_BASE_TYPE_FUNC_EVENT: 404 if (!bnxt_qplib_process_func_event 405 (rcfw, (struct creq_func_event *)creqe)) 406 creq->stats.creq_func_event_processed++; 407 else 408 dev_warn(&rcfw->pdev->dev, 409 "aeqe:%#x Not handled\n", type); 410 break; 411 default: 412 if (type != ASYNC_EVENT_CMPL_TYPE_HWRM_ASYNC_EVENT) 413 dev_warn(&rcfw->pdev->dev, 414 "creqe with event 0x%x not handled\n", 415 type); 416 break; 417 } 418 raw_cons++; 419 budget--; 420 } 421 422 if (hwq->cons != raw_cons) { 423 hwq->cons = raw_cons; 424 bnxt_qplib_ring_nq_db(&creq->creq_db.dbinfo, 425 rcfw->res->cctx, true); 426 } 427 spin_unlock_irqrestore(&hwq->lock, flags); 428 } 429 430 static irqreturn_t bnxt_qplib_creq_irq(int irq, void *dev_instance) 431 { 432 struct bnxt_qplib_rcfw *rcfw = dev_instance; 433 struct bnxt_qplib_creq_ctx *creq; 434 struct bnxt_qplib_hwq *hwq; 435 u32 sw_cons; 436 437 creq = &rcfw->creq; 438 hwq = &creq->hwq; 439 /* Prefetch the CREQ element */ 440 sw_cons = HWQ_CMP(hwq->cons, hwq); 441 prefetch(bnxt_qplib_get_qe(hwq, sw_cons, NULL)); 442 443 tasklet_schedule(&creq->creq_tasklet); 444 445 return IRQ_HANDLED; 446 } 447 448 /* RCFW */ 449 int bnxt_qplib_deinit_rcfw(struct bnxt_qplib_rcfw *rcfw) 450 { 451 struct creq_deinitialize_fw_resp resp = {}; 452 struct cmdq_deinitialize_fw req = {}; 453 struct bnxt_qplib_cmdqmsg msg = {}; 454 int rc; 455 456 bnxt_qplib_rcfw_cmd_prep((struct cmdq_base *)&req, 457 CMDQ_BASE_OPCODE_DEINITIALIZE_FW, 458 sizeof(req)); 459 bnxt_qplib_fill_cmdqmsg(&msg, &req, &resp, NULL, 460 sizeof(req), sizeof(resp), 0); 461 rc = bnxt_qplib_rcfw_send_message(rcfw, &msg); 462 if (rc) 463 return rc; 464 465 clear_bit(FIRMWARE_INITIALIZED_FLAG, &rcfw->cmdq.flags); 466 return 0; 467 } 468 469 int bnxt_qplib_init_rcfw(struct bnxt_qplib_rcfw *rcfw, 470 struct bnxt_qplib_ctx *ctx, int is_virtfn) 471 { 472 struct creq_initialize_fw_resp resp = {}; 473 struct cmdq_initialize_fw req = {}; 474 struct bnxt_qplib_cmdqmsg msg = {}; 475 u8 pgsz, lvl; 476 int rc; 477 478 bnxt_qplib_rcfw_cmd_prep((struct cmdq_base *)&req, 479 CMDQ_BASE_OPCODE_INITIALIZE_FW, 480 sizeof(req)); 481 /* Supply (log-base-2-of-host-page-size - base-page-shift) 482 * to bono to adjust the doorbell page sizes. 483 */ 484 req.log2_dbr_pg_size = cpu_to_le16(PAGE_SHIFT - 485 RCFW_DBR_BASE_PAGE_SHIFT); 486 /* 487 * Gen P5 devices doesn't require this allocation 488 * as the L2 driver does the same for RoCE also. 489 * Also, VFs need not setup the HW context area, PF 490 * shall setup this area for VF. Skipping the 491 * HW programming 492 */ 493 if (is_virtfn) 494 goto skip_ctx_setup; 495 if (bnxt_qplib_is_chip_gen_p5(rcfw->res->cctx)) 496 goto config_vf_res; 497 498 lvl = ctx->qpc_tbl.level; 499 pgsz = bnxt_qplib_base_pg_size(&ctx->qpc_tbl); 500 req.qpc_pg_size_qpc_lvl = (pgsz << CMDQ_INITIALIZE_FW_QPC_PG_SIZE_SFT) | 501 lvl; 502 lvl = ctx->mrw_tbl.level; 503 pgsz = bnxt_qplib_base_pg_size(&ctx->mrw_tbl); 504 req.mrw_pg_size_mrw_lvl = (pgsz << CMDQ_INITIALIZE_FW_QPC_PG_SIZE_SFT) | 505 lvl; 506 lvl = ctx->srqc_tbl.level; 507 pgsz = bnxt_qplib_base_pg_size(&ctx->srqc_tbl); 508 req.srq_pg_size_srq_lvl = (pgsz << CMDQ_INITIALIZE_FW_QPC_PG_SIZE_SFT) | 509 lvl; 510 lvl = ctx->cq_tbl.level; 511 pgsz = bnxt_qplib_base_pg_size(&ctx->cq_tbl); 512 req.cq_pg_size_cq_lvl = (pgsz << CMDQ_INITIALIZE_FW_QPC_PG_SIZE_SFT) | 513 lvl; 514 lvl = ctx->tim_tbl.level; 515 pgsz = bnxt_qplib_base_pg_size(&ctx->tim_tbl); 516 req.tim_pg_size_tim_lvl = (pgsz << CMDQ_INITIALIZE_FW_QPC_PG_SIZE_SFT) | 517 lvl; 518 lvl = ctx->tqm_ctx.pde.level; 519 pgsz = bnxt_qplib_base_pg_size(&ctx->tqm_ctx.pde); 520 req.tqm_pg_size_tqm_lvl = (pgsz << CMDQ_INITIALIZE_FW_QPC_PG_SIZE_SFT) | 521 lvl; 522 req.qpc_page_dir = 523 cpu_to_le64(ctx->qpc_tbl.pbl[PBL_LVL_0].pg_map_arr[0]); 524 req.mrw_page_dir = 525 cpu_to_le64(ctx->mrw_tbl.pbl[PBL_LVL_0].pg_map_arr[0]); 526 req.srq_page_dir = 527 cpu_to_le64(ctx->srqc_tbl.pbl[PBL_LVL_0].pg_map_arr[0]); 528 req.cq_page_dir = 529 cpu_to_le64(ctx->cq_tbl.pbl[PBL_LVL_0].pg_map_arr[0]); 530 req.tim_page_dir = 531 cpu_to_le64(ctx->tim_tbl.pbl[PBL_LVL_0].pg_map_arr[0]); 532 req.tqm_page_dir = 533 cpu_to_le64(ctx->tqm_ctx.pde.pbl[PBL_LVL_0].pg_map_arr[0]); 534 535 req.number_of_qp = cpu_to_le32(ctx->qpc_tbl.max_elements); 536 req.number_of_mrw = cpu_to_le32(ctx->mrw_tbl.max_elements); 537 req.number_of_srq = cpu_to_le32(ctx->srqc_tbl.max_elements); 538 req.number_of_cq = cpu_to_le32(ctx->cq_tbl.max_elements); 539 540 config_vf_res: 541 req.max_qp_per_vf = cpu_to_le32(ctx->vf_res.max_qp_per_vf); 542 req.max_mrw_per_vf = cpu_to_le32(ctx->vf_res.max_mrw_per_vf); 543 req.max_srq_per_vf = cpu_to_le32(ctx->vf_res.max_srq_per_vf); 544 req.max_cq_per_vf = cpu_to_le32(ctx->vf_res.max_cq_per_vf); 545 req.max_gid_per_vf = cpu_to_le32(ctx->vf_res.max_gid_per_vf); 546 547 skip_ctx_setup: 548 req.stat_ctx_id = cpu_to_le32(ctx->stats.fw_id); 549 bnxt_qplib_fill_cmdqmsg(&msg, &req, &resp, NULL, sizeof(req), sizeof(resp), 0); 550 rc = bnxt_qplib_rcfw_send_message(rcfw, &msg); 551 if (rc) 552 return rc; 553 set_bit(FIRMWARE_INITIALIZED_FLAG, &rcfw->cmdq.flags); 554 return 0; 555 } 556 557 void bnxt_qplib_free_rcfw_channel(struct bnxt_qplib_rcfw *rcfw) 558 { 559 bitmap_free(rcfw->cmdq.cmdq_bitmap); 560 kfree(rcfw->qp_tbl); 561 kfree(rcfw->crsqe_tbl); 562 bnxt_qplib_free_hwq(rcfw->res, &rcfw->cmdq.hwq); 563 bnxt_qplib_free_hwq(rcfw->res, &rcfw->creq.hwq); 564 rcfw->pdev = NULL; 565 } 566 567 int bnxt_qplib_alloc_rcfw_channel(struct bnxt_qplib_res *res, 568 struct bnxt_qplib_rcfw *rcfw, 569 struct bnxt_qplib_ctx *ctx, 570 int qp_tbl_sz) 571 { 572 struct bnxt_qplib_hwq_attr hwq_attr = {}; 573 struct bnxt_qplib_sg_info sginfo = {}; 574 struct bnxt_qplib_cmdq_ctx *cmdq; 575 struct bnxt_qplib_creq_ctx *creq; 576 577 rcfw->pdev = res->pdev; 578 cmdq = &rcfw->cmdq; 579 creq = &rcfw->creq; 580 rcfw->res = res; 581 582 sginfo.pgsize = PAGE_SIZE; 583 sginfo.pgshft = PAGE_SHIFT; 584 585 hwq_attr.sginfo = &sginfo; 586 hwq_attr.res = rcfw->res; 587 hwq_attr.depth = BNXT_QPLIB_CREQE_MAX_CNT; 588 hwq_attr.stride = BNXT_QPLIB_CREQE_UNITS; 589 hwq_attr.type = bnxt_qplib_get_hwq_type(res); 590 591 if (bnxt_qplib_alloc_init_hwq(&creq->hwq, &hwq_attr)) { 592 dev_err(&rcfw->pdev->dev, 593 "HW channel CREQ allocation failed\n"); 594 goto fail; 595 } 596 if (ctx->hwrm_intf_ver < HWRM_VERSION_RCFW_CMDQ_DEPTH_CHECK) 597 rcfw->cmdq_depth = BNXT_QPLIB_CMDQE_MAX_CNT_256; 598 else 599 rcfw->cmdq_depth = BNXT_QPLIB_CMDQE_MAX_CNT_8192; 600 601 sginfo.pgsize = bnxt_qplib_cmdqe_page_size(rcfw->cmdq_depth); 602 hwq_attr.depth = rcfw->cmdq_depth; 603 hwq_attr.stride = BNXT_QPLIB_CMDQE_UNITS; 604 hwq_attr.type = HWQ_TYPE_CTX; 605 if (bnxt_qplib_alloc_init_hwq(&cmdq->hwq, &hwq_attr)) { 606 dev_err(&rcfw->pdev->dev, 607 "HW channel CMDQ allocation failed\n"); 608 goto fail; 609 } 610 611 rcfw->crsqe_tbl = kcalloc(cmdq->hwq.max_elements, 612 sizeof(*rcfw->crsqe_tbl), GFP_KERNEL); 613 if (!rcfw->crsqe_tbl) 614 goto fail; 615 616 cmdq->cmdq_bitmap = bitmap_zalloc(rcfw->cmdq_depth, GFP_KERNEL); 617 if (!cmdq->cmdq_bitmap) 618 goto fail; 619 620 /* Allocate one extra to hold the QP1 entries */ 621 rcfw->qp_tbl_size = qp_tbl_sz + 1; 622 rcfw->qp_tbl = kcalloc(rcfw->qp_tbl_size, sizeof(struct bnxt_qplib_qp_node), 623 GFP_KERNEL); 624 if (!rcfw->qp_tbl) 625 goto fail; 626 627 return 0; 628 629 fail: 630 bnxt_qplib_free_rcfw_channel(rcfw); 631 return -ENOMEM; 632 } 633 634 void bnxt_qplib_rcfw_stop_irq(struct bnxt_qplib_rcfw *rcfw, bool kill) 635 { 636 struct bnxt_qplib_creq_ctx *creq; 637 638 creq = &rcfw->creq; 639 tasklet_disable(&creq->creq_tasklet); 640 /* Mask h/w interrupts */ 641 bnxt_qplib_ring_nq_db(&creq->creq_db.dbinfo, rcfw->res->cctx, false); 642 /* Sync with last running IRQ-handler */ 643 synchronize_irq(creq->msix_vec); 644 if (kill) 645 tasklet_kill(&creq->creq_tasklet); 646 647 if (creq->requested) { 648 free_irq(creq->msix_vec, rcfw); 649 creq->requested = false; 650 } 651 } 652 653 void bnxt_qplib_disable_rcfw_channel(struct bnxt_qplib_rcfw *rcfw) 654 { 655 struct bnxt_qplib_creq_ctx *creq; 656 struct bnxt_qplib_cmdq_ctx *cmdq; 657 unsigned long indx; 658 659 creq = &rcfw->creq; 660 cmdq = &rcfw->cmdq; 661 /* Make sure the HW channel is stopped! */ 662 bnxt_qplib_rcfw_stop_irq(rcfw, true); 663 664 iounmap(cmdq->cmdq_mbox.reg.bar_reg); 665 iounmap(creq->creq_db.reg.bar_reg); 666 667 indx = find_first_bit(cmdq->cmdq_bitmap, rcfw->cmdq_depth); 668 if (indx != rcfw->cmdq_depth) 669 dev_err(&rcfw->pdev->dev, 670 "disabling RCFW with pending cmd-bit %lx\n", indx); 671 672 cmdq->cmdq_mbox.reg.bar_reg = NULL; 673 creq->creq_db.reg.bar_reg = NULL; 674 creq->aeq_handler = NULL; 675 creq->msix_vec = 0; 676 } 677 678 int bnxt_qplib_rcfw_start_irq(struct bnxt_qplib_rcfw *rcfw, int msix_vector, 679 bool need_init) 680 { 681 struct bnxt_qplib_creq_ctx *creq; 682 int rc; 683 684 creq = &rcfw->creq; 685 686 if (creq->requested) 687 return -EFAULT; 688 689 creq->msix_vec = msix_vector; 690 if (need_init) 691 tasklet_setup(&creq->creq_tasklet, bnxt_qplib_service_creq); 692 else 693 tasklet_enable(&creq->creq_tasklet); 694 rc = request_irq(creq->msix_vec, bnxt_qplib_creq_irq, 0, 695 "bnxt_qplib_creq", rcfw); 696 if (rc) 697 return rc; 698 creq->requested = true; 699 700 bnxt_qplib_ring_nq_db(&creq->creq_db.dbinfo, rcfw->res->cctx, true); 701 702 return 0; 703 } 704 705 static int bnxt_qplib_map_cmdq_mbox(struct bnxt_qplib_rcfw *rcfw, bool is_vf) 706 { 707 struct bnxt_qplib_cmdq_mbox *mbox; 708 resource_size_t bar_reg; 709 struct pci_dev *pdev; 710 u16 prod_offt; 711 int rc = 0; 712 713 pdev = rcfw->pdev; 714 mbox = &rcfw->cmdq.cmdq_mbox; 715 716 mbox->reg.bar_id = RCFW_COMM_PCI_BAR_REGION; 717 mbox->reg.len = RCFW_COMM_SIZE; 718 mbox->reg.bar_base = pci_resource_start(pdev, mbox->reg.bar_id); 719 if (!mbox->reg.bar_base) { 720 dev_err(&pdev->dev, 721 "QPLIB: CMDQ BAR region %d resc start is 0!\n", 722 mbox->reg.bar_id); 723 return -ENOMEM; 724 } 725 726 bar_reg = mbox->reg.bar_base + RCFW_COMM_BASE_OFFSET; 727 mbox->reg.len = RCFW_COMM_SIZE; 728 mbox->reg.bar_reg = ioremap(bar_reg, mbox->reg.len); 729 if (!mbox->reg.bar_reg) { 730 dev_err(&pdev->dev, 731 "QPLIB: CMDQ BAR region %d mapping failed\n", 732 mbox->reg.bar_id); 733 return -ENOMEM; 734 } 735 736 prod_offt = is_vf ? RCFW_VF_COMM_PROD_OFFSET : 737 RCFW_PF_COMM_PROD_OFFSET; 738 mbox->prod = (void __iomem *)(mbox->reg.bar_reg + prod_offt); 739 mbox->db = (void __iomem *)(mbox->reg.bar_reg + RCFW_COMM_TRIG_OFFSET); 740 return rc; 741 } 742 743 static int bnxt_qplib_map_creq_db(struct bnxt_qplib_rcfw *rcfw, u32 reg_offt) 744 { 745 struct bnxt_qplib_creq_db *creq_db; 746 resource_size_t bar_reg; 747 struct pci_dev *pdev; 748 749 pdev = rcfw->pdev; 750 creq_db = &rcfw->creq.creq_db; 751 752 creq_db->reg.bar_id = RCFW_COMM_CONS_PCI_BAR_REGION; 753 creq_db->reg.bar_base = pci_resource_start(pdev, creq_db->reg.bar_id); 754 if (!creq_db->reg.bar_id) 755 dev_err(&pdev->dev, 756 "QPLIB: CREQ BAR region %d resc start is 0!", 757 creq_db->reg.bar_id); 758 759 bar_reg = creq_db->reg.bar_base + reg_offt; 760 /* Unconditionally map 8 bytes to support 57500 series */ 761 creq_db->reg.len = 8; 762 creq_db->reg.bar_reg = ioremap(bar_reg, creq_db->reg.len); 763 if (!creq_db->reg.bar_reg) { 764 dev_err(&pdev->dev, 765 "QPLIB: CREQ BAR region %d mapping failed", 766 creq_db->reg.bar_id); 767 return -ENOMEM; 768 } 769 creq_db->dbinfo.db = creq_db->reg.bar_reg; 770 creq_db->dbinfo.hwq = &rcfw->creq.hwq; 771 creq_db->dbinfo.xid = rcfw->creq.ring_id; 772 return 0; 773 } 774 775 static void bnxt_qplib_start_rcfw(struct bnxt_qplib_rcfw *rcfw) 776 { 777 struct bnxt_qplib_cmdq_ctx *cmdq; 778 struct bnxt_qplib_creq_ctx *creq; 779 struct bnxt_qplib_cmdq_mbox *mbox; 780 struct cmdq_init init = {0}; 781 782 cmdq = &rcfw->cmdq; 783 creq = &rcfw->creq; 784 mbox = &cmdq->cmdq_mbox; 785 786 init.cmdq_pbl = cpu_to_le64(cmdq->hwq.pbl[PBL_LVL_0].pg_map_arr[0]); 787 init.cmdq_size_cmdq_lvl = 788 cpu_to_le16(((rcfw->cmdq_depth << 789 CMDQ_INIT_CMDQ_SIZE_SFT) & 790 CMDQ_INIT_CMDQ_SIZE_MASK) | 791 ((cmdq->hwq.level << 792 CMDQ_INIT_CMDQ_LVL_SFT) & 793 CMDQ_INIT_CMDQ_LVL_MASK)); 794 init.creq_ring_id = cpu_to_le16(creq->ring_id); 795 /* Write to the Bono mailbox register */ 796 __iowrite32_copy(mbox->reg.bar_reg, &init, sizeof(init) / 4); 797 } 798 799 int bnxt_qplib_enable_rcfw_channel(struct bnxt_qplib_rcfw *rcfw, 800 int msix_vector, 801 int cp_bar_reg_off, int virt_fn, 802 aeq_handler_t aeq_handler) 803 { 804 struct bnxt_qplib_cmdq_ctx *cmdq; 805 struct bnxt_qplib_creq_ctx *creq; 806 int rc; 807 808 cmdq = &rcfw->cmdq; 809 creq = &rcfw->creq; 810 811 /* Clear to defaults */ 812 813 cmdq->seq_num = 0; 814 set_bit(FIRMWARE_FIRST_FLAG, &cmdq->flags); 815 init_waitqueue_head(&cmdq->waitq); 816 817 creq->stats.creq_qp_event_processed = 0; 818 creq->stats.creq_func_event_processed = 0; 819 creq->aeq_handler = aeq_handler; 820 821 rc = bnxt_qplib_map_cmdq_mbox(rcfw, virt_fn); 822 if (rc) 823 return rc; 824 825 rc = bnxt_qplib_map_creq_db(rcfw, cp_bar_reg_off); 826 if (rc) 827 return rc; 828 829 rc = bnxt_qplib_rcfw_start_irq(rcfw, msix_vector, true); 830 if (rc) { 831 dev_err(&rcfw->pdev->dev, 832 "Failed to request IRQ for CREQ rc = 0x%x\n", rc); 833 bnxt_qplib_disable_rcfw_channel(rcfw); 834 return rc; 835 } 836 837 bnxt_qplib_start_rcfw(rcfw); 838 839 return 0; 840 } 841 842 struct bnxt_qplib_rcfw_sbuf *bnxt_qplib_rcfw_alloc_sbuf( 843 struct bnxt_qplib_rcfw *rcfw, 844 u32 size) 845 { 846 struct bnxt_qplib_rcfw_sbuf *sbuf; 847 848 sbuf = kzalloc(sizeof(*sbuf), GFP_KERNEL); 849 if (!sbuf) 850 return NULL; 851 852 sbuf->size = size; 853 sbuf->sb = dma_alloc_coherent(&rcfw->pdev->dev, sbuf->size, 854 &sbuf->dma_addr, GFP_KERNEL); 855 if (!sbuf->sb) 856 goto bail; 857 858 return sbuf; 859 bail: 860 kfree(sbuf); 861 return NULL; 862 } 863 864 void bnxt_qplib_rcfw_free_sbuf(struct bnxt_qplib_rcfw *rcfw, 865 struct bnxt_qplib_rcfw_sbuf *sbuf) 866 { 867 if (sbuf->sb) 868 dma_free_coherent(&rcfw->pdev->dev, sbuf->size, 869 sbuf->sb, sbuf->dma_addr); 870 kfree(sbuf); 871 } 872