1 /* 2 * Broadcom NetXtreme-E RoCE driver. 3 * 4 * Copyright (c) 2016 - 2017, Broadcom. All rights reserved. The term 5 * Broadcom refers to Broadcom Limited and/or its subsidiaries. 6 * 7 * This software is available to you under a choice of one of two 8 * licenses. You may choose to be licensed under the terms of the GNU 9 * General Public License (GPL) Version 2, available from the file 10 * COPYING in the main directory of this source tree, or the 11 * BSD license below: 12 * 13 * Redistribution and use in source and binary forms, with or without 14 * modification, are permitted provided that the following conditions 15 * are met: 16 * 17 * 1. Redistributions of source code must retain the above copyright 18 * notice, this list of conditions and the following disclaimer. 19 * 2. Redistributions in binary form must reproduce the above copyright 20 * notice, this list of conditions and the following disclaimer in 21 * the documentation and/or other materials provided with the 22 * distribution. 23 * 24 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' 25 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, 26 * THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR 27 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS 28 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 29 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 30 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR 31 * BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, 32 * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE 33 * OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN 34 * IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 35 * 36 * Description: Fast Path Operators (header) 37 */ 38 39 #ifndef __BNXT_QPLIB_FP_H__ 40 #define __BNXT_QPLIB_FP_H__ 41 42 struct bnxt_qplib_srq { 43 struct bnxt_qplib_pd *pd; 44 struct bnxt_qplib_dpi *dpi; 45 void __iomem *dbr_base; 46 u64 srq_handle; 47 u32 id; 48 u32 max_wqe; 49 u32 max_sge; 50 u32 threshold; 51 bool arm_req; 52 struct bnxt_qplib_cq *cq; 53 struct bnxt_qplib_hwq hwq; 54 struct bnxt_qplib_swq *swq; 55 struct scatterlist *sglist; 56 int start_idx; 57 int last_idx; 58 u32 nmap; 59 u16 eventq_hw_ring_id; 60 spinlock_t lock; /* protect SRQE link list */ 61 }; 62 63 struct bnxt_qplib_sge { 64 u64 addr; 65 u32 lkey; 66 u32 size; 67 }; 68 69 #define BNXT_QPLIB_MAX_SQE_ENTRY_SIZE sizeof(struct sq_send) 70 71 #define SQE_CNT_PER_PG (PAGE_SIZE / BNXT_QPLIB_MAX_SQE_ENTRY_SIZE) 72 #define SQE_MAX_IDX_PER_PG (SQE_CNT_PER_PG - 1) 73 74 static inline u32 get_sqe_pg(u32 val) 75 { 76 return ((val & ~SQE_MAX_IDX_PER_PG) / SQE_CNT_PER_PG); 77 } 78 79 static inline u32 get_sqe_idx(u32 val) 80 { 81 return (val & SQE_MAX_IDX_PER_PG); 82 } 83 84 #define BNXT_QPLIB_MAX_PSNE_ENTRY_SIZE sizeof(struct sq_psn_search) 85 86 #define PSNE_CNT_PER_PG (PAGE_SIZE / BNXT_QPLIB_MAX_PSNE_ENTRY_SIZE) 87 #define PSNE_MAX_IDX_PER_PG (PSNE_CNT_PER_PG - 1) 88 89 static inline u32 get_psne_pg(u32 val) 90 { 91 return ((val & ~PSNE_MAX_IDX_PER_PG) / PSNE_CNT_PER_PG); 92 } 93 94 static inline u32 get_psne_idx(u32 val) 95 { 96 return (val & PSNE_MAX_IDX_PER_PG); 97 } 98 99 #define BNXT_QPLIB_QP_MAX_SGL 6 100 101 struct bnxt_qplib_swq { 102 u64 wr_id; 103 int next_idx; 104 u8 type; 105 u8 flags; 106 u32 start_psn; 107 u32 next_psn; 108 struct sq_psn_search *psn_search; 109 struct sq_psn_search_ext *psn_ext; 110 }; 111 112 struct bnxt_qplib_swqe { 113 /* General */ 114 #define BNXT_QPLIB_FENCE_WRID 0x46454E43 /* "FENC" */ 115 u64 wr_id; 116 u8 reqs_type; 117 u8 type; 118 #define BNXT_QPLIB_SWQE_TYPE_SEND 0 119 #define BNXT_QPLIB_SWQE_TYPE_SEND_WITH_IMM 1 120 #define BNXT_QPLIB_SWQE_TYPE_SEND_WITH_INV 2 121 #define BNXT_QPLIB_SWQE_TYPE_RDMA_WRITE 4 122 #define BNXT_QPLIB_SWQE_TYPE_RDMA_WRITE_WITH_IMM 5 123 #define BNXT_QPLIB_SWQE_TYPE_RDMA_READ 6 124 #define BNXT_QPLIB_SWQE_TYPE_ATOMIC_CMP_AND_SWP 8 125 #define BNXT_QPLIB_SWQE_TYPE_ATOMIC_FETCH_AND_ADD 11 126 #define BNXT_QPLIB_SWQE_TYPE_LOCAL_INV 12 127 #define BNXT_QPLIB_SWQE_TYPE_FAST_REG_MR 13 128 #define BNXT_QPLIB_SWQE_TYPE_REG_MR 13 129 #define BNXT_QPLIB_SWQE_TYPE_BIND_MW 14 130 #define BNXT_QPLIB_SWQE_TYPE_RECV 128 131 #define BNXT_QPLIB_SWQE_TYPE_RECV_RDMA_IMM 129 132 u8 flags; 133 #define BNXT_QPLIB_SWQE_FLAGS_SIGNAL_COMP BIT(0) 134 #define BNXT_QPLIB_SWQE_FLAGS_RD_ATOMIC_FENCE BIT(1) 135 #define BNXT_QPLIB_SWQE_FLAGS_UC_FENCE BIT(2) 136 #define BNXT_QPLIB_SWQE_FLAGS_SOLICIT_EVENT BIT(3) 137 #define BNXT_QPLIB_SWQE_FLAGS_INLINE BIT(4) 138 struct bnxt_qplib_sge sg_list[BNXT_QPLIB_QP_MAX_SGL]; 139 int num_sge; 140 /* Max inline data is 96 bytes */ 141 u32 inline_len; 142 #define BNXT_QPLIB_SWQE_MAX_INLINE_LENGTH 96 143 u8 inline_data[BNXT_QPLIB_SWQE_MAX_INLINE_LENGTH]; 144 145 union { 146 /* Send, with imm, inval key */ 147 struct { 148 union { 149 __be32 imm_data; 150 u32 inv_key; 151 }; 152 u32 q_key; 153 u32 dst_qp; 154 u16 avid; 155 } send; 156 157 /* Send Raw Ethernet and QP1 */ 158 struct { 159 u16 lflags; 160 u16 cfa_action; 161 u32 cfa_meta; 162 } rawqp1; 163 164 /* RDMA write, with imm, read */ 165 struct { 166 union { 167 __be32 imm_data; 168 u32 inv_key; 169 }; 170 u64 remote_va; 171 u32 r_key; 172 } rdma; 173 174 /* Atomic cmp/swap, fetch/add */ 175 struct { 176 u64 remote_va; 177 u32 r_key; 178 u64 swap_data; 179 u64 cmp_data; 180 } atomic; 181 182 /* Local Invalidate */ 183 struct { 184 u32 inv_l_key; 185 } local_inv; 186 187 /* FR-PMR */ 188 struct { 189 u8 access_cntl; 190 u8 pg_sz_log; 191 bool zero_based; 192 u32 l_key; 193 u32 length; 194 u8 pbl_pg_sz_log; 195 #define BNXT_QPLIB_SWQE_PAGE_SIZE_4K 0 196 #define BNXT_QPLIB_SWQE_PAGE_SIZE_8K 1 197 #define BNXT_QPLIB_SWQE_PAGE_SIZE_64K 4 198 #define BNXT_QPLIB_SWQE_PAGE_SIZE_256K 6 199 #define BNXT_QPLIB_SWQE_PAGE_SIZE_1M 8 200 #define BNXT_QPLIB_SWQE_PAGE_SIZE_2M 9 201 #define BNXT_QPLIB_SWQE_PAGE_SIZE_4M 10 202 #define BNXT_QPLIB_SWQE_PAGE_SIZE_1G 18 203 u8 levels; 204 #define PAGE_SHIFT_4K 12 205 __le64 *pbl_ptr; 206 dma_addr_t pbl_dma_ptr; 207 u64 *page_list; 208 u16 page_list_len; 209 u64 va; 210 } frmr; 211 212 /* Bind */ 213 struct { 214 u8 access_cntl; 215 #define BNXT_QPLIB_BIND_SWQE_ACCESS_LOCAL_WRITE BIT(0) 216 #define BNXT_QPLIB_BIND_SWQE_ACCESS_REMOTE_READ BIT(1) 217 #define BNXT_QPLIB_BIND_SWQE_ACCESS_REMOTE_WRITE BIT(2) 218 #define BNXT_QPLIB_BIND_SWQE_ACCESS_REMOTE_ATOMIC BIT(3) 219 #define BNXT_QPLIB_BIND_SWQE_ACCESS_WINDOW_BIND BIT(4) 220 bool zero_based; 221 u8 mw_type; 222 u32 parent_l_key; 223 u32 r_key; 224 u64 va; 225 u32 length; 226 } bind; 227 }; 228 }; 229 230 #define BNXT_QPLIB_MAX_RQE_ENTRY_SIZE sizeof(struct rq_wqe) 231 232 #define RQE_CNT_PER_PG (PAGE_SIZE / BNXT_QPLIB_MAX_RQE_ENTRY_SIZE) 233 #define RQE_MAX_IDX_PER_PG (RQE_CNT_PER_PG - 1) 234 #define RQE_PG(x) (((x) & ~RQE_MAX_IDX_PER_PG) / RQE_CNT_PER_PG) 235 #define RQE_IDX(x) ((x) & RQE_MAX_IDX_PER_PG) 236 237 struct bnxt_qplib_q { 238 struct bnxt_qplib_hwq hwq; 239 struct bnxt_qplib_swq *swq; 240 struct scatterlist *sglist; 241 u32 nmap; 242 u32 max_wqe; 243 u16 q_full_delta; 244 u16 max_sge; 245 u32 psn; 246 bool condition; 247 bool single; 248 bool send_phantom; 249 u32 phantom_wqe_cnt; 250 u32 phantom_cqe_cnt; 251 u32 next_cq_cons; 252 bool flushed; 253 }; 254 255 struct bnxt_qplib_qp { 256 struct bnxt_qplib_pd *pd; 257 struct bnxt_qplib_dpi *dpi; 258 struct bnxt_qplib_chip_ctx *cctx; 259 u64 qp_handle; 260 #define BNXT_QPLIB_QP_ID_INVALID 0xFFFFFFFF 261 u32 id; 262 u8 type; 263 u8 sig_type; 264 u32 modify_flags; 265 u8 state; 266 u8 cur_qp_state; 267 u32 max_inline_data; 268 u32 mtu; 269 u8 path_mtu; 270 bool en_sqd_async_notify; 271 u16 pkey_index; 272 u32 qkey; 273 u32 dest_qp_id; 274 u8 access; 275 u8 timeout; 276 u8 retry_cnt; 277 u8 rnr_retry; 278 u64 wqe_cnt; 279 u32 min_rnr_timer; 280 u32 max_rd_atomic; 281 u32 max_dest_rd_atomic; 282 u32 dest_qpn; 283 u8 smac[6]; 284 u16 vlan_id; 285 u8 nw_type; 286 struct bnxt_qplib_ah ah; 287 288 #define BTH_PSN_MASK ((1 << 24) - 1) 289 /* SQ */ 290 struct bnxt_qplib_q sq; 291 /* RQ */ 292 struct bnxt_qplib_q rq; 293 /* SRQ */ 294 struct bnxt_qplib_srq *srq; 295 /* CQ */ 296 struct bnxt_qplib_cq *scq; 297 struct bnxt_qplib_cq *rcq; 298 /* IRRQ and ORRQ */ 299 struct bnxt_qplib_hwq irrq; 300 struct bnxt_qplib_hwq orrq; 301 /* Header buffer for QP1 */ 302 int sq_hdr_buf_size; 303 int rq_hdr_buf_size; 304 /* 305 * Buffer space for ETH(14), IP or GRH(40), UDP header(8) 306 * and ib_bth + ib_deth (20). 307 * Max required is 82 when RoCE V2 is enabled 308 */ 309 #define BNXT_QPLIB_MAX_QP1_SQ_HDR_SIZE_V2 86 310 /* Ethernet header = 14 */ 311 /* ib_grh = 40 (provided by MAD) */ 312 /* ib_bth + ib_deth = 20 */ 313 /* MAD = 256 (provided by MAD) */ 314 /* iCRC = 4 */ 315 #define BNXT_QPLIB_MAX_QP1_RQ_ETH_HDR_SIZE 14 316 #define BNXT_QPLIB_MAX_QP1_RQ_HDR_SIZE_V2 512 317 #define BNXT_QPLIB_MAX_GRH_HDR_SIZE_IPV4 20 318 #define BNXT_QPLIB_MAX_GRH_HDR_SIZE_IPV6 40 319 #define BNXT_QPLIB_MAX_QP1_RQ_BDETH_HDR_SIZE 20 320 void *sq_hdr_buf; 321 dma_addr_t sq_hdr_buf_map; 322 void *rq_hdr_buf; 323 dma_addr_t rq_hdr_buf_map; 324 struct list_head sq_flush; 325 struct list_head rq_flush; 326 }; 327 328 #define BNXT_QPLIB_MAX_CQE_ENTRY_SIZE sizeof(struct cq_base) 329 330 #define CQE_CNT_PER_PG (PAGE_SIZE / BNXT_QPLIB_MAX_CQE_ENTRY_SIZE) 331 #define CQE_MAX_IDX_PER_PG (CQE_CNT_PER_PG - 1) 332 #define CQE_PG(x) (((x) & ~CQE_MAX_IDX_PER_PG) / CQE_CNT_PER_PG) 333 #define CQE_IDX(x) ((x) & CQE_MAX_IDX_PER_PG) 334 335 #define ROCE_CQE_CMP_V 0 336 #define CQE_CMP_VALID(hdr, raw_cons, cp_bit) \ 337 (!!((hdr)->cqe_type_toggle & CQ_BASE_TOGGLE) == \ 338 !((raw_cons) & (cp_bit))) 339 340 static inline bool bnxt_qplib_queue_full(struct bnxt_qplib_q *qplib_q) 341 { 342 return HWQ_CMP((qplib_q->hwq.prod + qplib_q->q_full_delta), 343 &qplib_q->hwq) == HWQ_CMP(qplib_q->hwq.cons, 344 &qplib_q->hwq); 345 } 346 347 struct bnxt_qplib_cqe { 348 u8 status; 349 u8 type; 350 u8 opcode; 351 u32 length; 352 u16 cfa_meta; 353 u64 wr_id; 354 union { 355 __be32 immdata; 356 u32 invrkey; 357 }; 358 u64 qp_handle; 359 u64 mr_handle; 360 u16 flags; 361 u8 smac[6]; 362 u32 src_qp; 363 u16 raweth_qp1_flags; 364 u16 raweth_qp1_errors; 365 u16 raweth_qp1_cfa_code; 366 u32 raweth_qp1_flags2; 367 u32 raweth_qp1_metadata; 368 u8 raweth_qp1_payload_offset; 369 u16 pkey_index; 370 }; 371 372 #define BNXT_QPLIB_QUEUE_START_PERIOD 0x01 373 struct bnxt_qplib_cq { 374 struct bnxt_qplib_dpi *dpi; 375 void __iomem *dbr_base; 376 u32 max_wqe; 377 u32 id; 378 u16 count; 379 u16 period; 380 struct bnxt_qplib_hwq hwq; 381 u32 cnq_hw_ring_id; 382 struct bnxt_qplib_nq *nq; 383 bool resize_in_progress; 384 struct scatterlist *sghead; 385 u32 nmap; 386 u64 cq_handle; 387 388 #define CQ_RESIZE_WAIT_TIME_MS 500 389 unsigned long flags; 390 #define CQ_FLAGS_RESIZE_IN_PROG 1 391 wait_queue_head_t waitq; 392 struct list_head sqf_head, rqf_head; 393 atomic_t arm_state; 394 spinlock_t compl_lock; /* synch CQ handlers */ 395 /* Locking Notes: 396 * QP can move to error state from modify_qp, async error event or error 397 * CQE as part of poll_cq. When QP is moved to error state, it gets added 398 * to two flush lists, one each for SQ and RQ. 399 * Each flush list is protected by qplib_cq->flush_lock. Both scq and rcq 400 * flush_locks should be acquired when QP is moved to error. The control path 401 * operations(modify_qp and async error events) are synchronized with poll_cq 402 * using upper level CQ locks (bnxt_re_cq->cq_lock) of both SCQ and RCQ. 403 * The qplib_cq->flush_lock is required to synchronize two instances of poll_cq 404 * of the same QP while manipulating the flush list. 405 */ 406 spinlock_t flush_lock; /* QP flush management */ 407 }; 408 409 #define BNXT_QPLIB_MAX_IRRQE_ENTRY_SIZE sizeof(struct xrrq_irrq) 410 #define BNXT_QPLIB_MAX_ORRQE_ENTRY_SIZE sizeof(struct xrrq_orrq) 411 #define IRD_LIMIT_TO_IRRQ_SLOTS(x) (2 * (x) + 2) 412 #define IRRQ_SLOTS_TO_IRD_LIMIT(s) (((s) >> 1) - 1) 413 #define ORD_LIMIT_TO_ORRQ_SLOTS(x) ((x) + 1) 414 #define ORRQ_SLOTS_TO_ORD_LIMIT(s) ((s) - 1) 415 416 #define BNXT_QPLIB_MAX_NQE_ENTRY_SIZE sizeof(struct nq_base) 417 418 #define NQE_CNT_PER_PG (PAGE_SIZE / BNXT_QPLIB_MAX_NQE_ENTRY_SIZE) 419 #define NQE_MAX_IDX_PER_PG (NQE_CNT_PER_PG - 1) 420 #define NQE_PG(x) (((x) & ~NQE_MAX_IDX_PER_PG) / NQE_CNT_PER_PG) 421 #define NQE_IDX(x) ((x) & NQE_MAX_IDX_PER_PG) 422 423 #define NQE_CMP_VALID(hdr, raw_cons, cp_bit) \ 424 (!!(le32_to_cpu((hdr)->info63_v[0]) & NQ_BASE_V) == \ 425 !((raw_cons) & (cp_bit))) 426 427 #define BNXT_QPLIB_NQE_MAX_CNT (128 * 1024) 428 429 #define NQ_CONS_PCI_BAR_REGION 2 430 #define NQ_DB_KEY_CP (0x2 << CMPL_DOORBELL_KEY_SFT) 431 #define NQ_DB_IDX_VALID CMPL_DOORBELL_IDX_VALID 432 #define NQ_DB_IRQ_DIS CMPL_DOORBELL_MASK 433 #define NQ_DB_CP_FLAGS_REARM (NQ_DB_KEY_CP | \ 434 NQ_DB_IDX_VALID) 435 #define NQ_DB_CP_FLAGS (NQ_DB_KEY_CP | \ 436 NQ_DB_IDX_VALID | \ 437 NQ_DB_IRQ_DIS) 438 439 static inline void bnxt_qplib_ring_nq_db64(void __iomem *db, u32 index, 440 u32 xid, bool arm) 441 { 442 u64 val; 443 444 val = xid & DBC_DBC_XID_MASK; 445 val |= DBC_DBC_PATH_ROCE; 446 val |= arm ? DBC_DBC_TYPE_NQ_ARM : DBC_DBC_TYPE_NQ; 447 val <<= 32; 448 val |= index & DBC_DBC_INDEX_MASK; 449 writeq(val, db); 450 } 451 452 static inline void bnxt_qplib_ring_nq_db_rearm(void __iomem *db, u32 raw_cons, 453 u32 max_elements, u32 xid, 454 bool gen_p5) 455 { 456 u32 index = raw_cons & (max_elements - 1); 457 458 if (gen_p5) 459 bnxt_qplib_ring_nq_db64(db, index, xid, true); 460 else 461 writel(NQ_DB_CP_FLAGS_REARM | (index & DBC_DBC32_XID_MASK), db); 462 } 463 464 static inline void bnxt_qplib_ring_nq_db(void __iomem *db, u32 raw_cons, 465 u32 max_elements, u32 xid, 466 bool gen_p5) 467 { 468 u32 index = raw_cons & (max_elements - 1); 469 470 if (gen_p5) 471 bnxt_qplib_ring_nq_db64(db, index, xid, false); 472 else 473 writel(NQ_DB_CP_FLAGS | (index & DBC_DBC32_XID_MASK), db); 474 } 475 476 struct bnxt_qplib_nq { 477 struct pci_dev *pdev; 478 struct bnxt_qplib_res *res; 479 480 int vector; 481 cpumask_t mask; 482 int budget; 483 bool requested; 484 struct tasklet_struct worker; 485 struct bnxt_qplib_hwq hwq; 486 487 u16 bar_reg; 488 u32 bar_reg_off; 489 u16 ring_id; 490 void __iomem *bar_reg_iomem; 491 492 int (*cqn_handler)(struct bnxt_qplib_nq *nq, 493 struct bnxt_qplib_cq *cq); 494 int (*srqn_handler)(struct bnxt_qplib_nq *nq, 495 struct bnxt_qplib_srq *srq, 496 u8 event); 497 struct workqueue_struct *cqn_wq; 498 char name[32]; 499 }; 500 501 struct bnxt_qplib_nq_work { 502 struct work_struct work; 503 struct bnxt_qplib_nq *nq; 504 struct bnxt_qplib_cq *cq; 505 }; 506 507 void bnxt_qplib_nq_stop_irq(struct bnxt_qplib_nq *nq, bool kill); 508 void bnxt_qplib_disable_nq(struct bnxt_qplib_nq *nq); 509 int bnxt_qplib_nq_start_irq(struct bnxt_qplib_nq *nq, int nq_indx, 510 int msix_vector, bool need_init); 511 int bnxt_qplib_enable_nq(struct pci_dev *pdev, struct bnxt_qplib_nq *nq, 512 int nq_idx, int msix_vector, int bar_reg_offset, 513 int (*cqn_handler)(struct bnxt_qplib_nq *nq, 514 struct bnxt_qplib_cq *cq), 515 int (*srqn_handler)(struct bnxt_qplib_nq *nq, 516 struct bnxt_qplib_srq *srq, 517 u8 event)); 518 int bnxt_qplib_create_srq(struct bnxt_qplib_res *res, 519 struct bnxt_qplib_srq *srq); 520 int bnxt_qplib_modify_srq(struct bnxt_qplib_res *res, 521 struct bnxt_qplib_srq *srq); 522 int bnxt_qplib_query_srq(struct bnxt_qplib_res *res, 523 struct bnxt_qplib_srq *srq); 524 int bnxt_qplib_destroy_srq(struct bnxt_qplib_res *res, 525 struct bnxt_qplib_srq *srq); 526 int bnxt_qplib_post_srq_recv(struct bnxt_qplib_srq *srq, 527 struct bnxt_qplib_swqe *wqe); 528 int bnxt_qplib_create_qp1(struct bnxt_qplib_res *res, struct bnxt_qplib_qp *qp); 529 int bnxt_qplib_create_qp(struct bnxt_qplib_res *res, struct bnxt_qplib_qp *qp); 530 int bnxt_qplib_modify_qp(struct bnxt_qplib_res *res, struct bnxt_qplib_qp *qp); 531 int bnxt_qplib_query_qp(struct bnxt_qplib_res *res, struct bnxt_qplib_qp *qp); 532 int bnxt_qplib_destroy_qp(struct bnxt_qplib_res *res, struct bnxt_qplib_qp *qp); 533 void bnxt_qplib_clean_qp(struct bnxt_qplib_qp *qp); 534 void bnxt_qplib_free_qp_res(struct bnxt_qplib_res *res, 535 struct bnxt_qplib_qp *qp); 536 void *bnxt_qplib_get_qp1_sq_buf(struct bnxt_qplib_qp *qp, 537 struct bnxt_qplib_sge *sge); 538 void *bnxt_qplib_get_qp1_rq_buf(struct bnxt_qplib_qp *qp, 539 struct bnxt_qplib_sge *sge); 540 u32 bnxt_qplib_get_rq_prod_index(struct bnxt_qplib_qp *qp); 541 dma_addr_t bnxt_qplib_get_qp_buf_from_index(struct bnxt_qplib_qp *qp, 542 u32 index); 543 void bnxt_qplib_post_send_db(struct bnxt_qplib_qp *qp); 544 int bnxt_qplib_post_send(struct bnxt_qplib_qp *qp, 545 struct bnxt_qplib_swqe *wqe); 546 void bnxt_qplib_post_recv_db(struct bnxt_qplib_qp *qp); 547 int bnxt_qplib_post_recv(struct bnxt_qplib_qp *qp, 548 struct bnxt_qplib_swqe *wqe); 549 int bnxt_qplib_create_cq(struct bnxt_qplib_res *res, struct bnxt_qplib_cq *cq); 550 int bnxt_qplib_destroy_cq(struct bnxt_qplib_res *res, struct bnxt_qplib_cq *cq); 551 int bnxt_qplib_poll_cq(struct bnxt_qplib_cq *cq, struct bnxt_qplib_cqe *cqe, 552 int num, struct bnxt_qplib_qp **qp); 553 bool bnxt_qplib_is_cq_empty(struct bnxt_qplib_cq *cq); 554 void bnxt_qplib_req_notify_cq(struct bnxt_qplib_cq *cq, u32 arm_type); 555 void bnxt_qplib_free_nq(struct bnxt_qplib_nq *nq); 556 int bnxt_qplib_alloc_nq(struct pci_dev *pdev, struct bnxt_qplib_nq *nq); 557 void bnxt_qplib_add_flush_qp(struct bnxt_qplib_qp *qp); 558 void bnxt_qplib_acquire_cq_locks(struct bnxt_qplib_qp *qp, 559 unsigned long *flags); 560 void bnxt_qplib_release_cq_locks(struct bnxt_qplib_qp *qp, 561 unsigned long *flags); 562 int bnxt_qplib_process_flush_list(struct bnxt_qplib_cq *cq, 563 struct bnxt_qplib_cqe *cqe, 564 int num_cqes); 565 void bnxt_qplib_flush_cqn_wq(struct bnxt_qplib_qp *qp); 566 #endif /* __BNXT_QPLIB_FP_H__ */ 567