1 /* 2 * Broadcom NetXtreme-E RoCE driver. 3 * 4 * Copyright (c) 2016 - 2017, Broadcom. All rights reserved. The term 5 * Broadcom refers to Broadcom Limited and/or its subsidiaries. 6 * 7 * This software is available to you under a choice of one of two 8 * licenses. You may choose to be licensed under the terms of the GNU 9 * General Public License (GPL) Version 2, available from the file 10 * COPYING in the main directory of this source tree, or the 11 * BSD license below: 12 * 13 * Redistribution and use in source and binary forms, with or without 14 * modification, are permitted provided that the following conditions 15 * are met: 16 * 17 * 1. Redistributions of source code must retain the above copyright 18 * notice, this list of conditions and the following disclaimer. 19 * 2. Redistributions in binary form must reproduce the above copyright 20 * notice, this list of conditions and the following disclaimer in 21 * the documentation and/or other materials provided with the 22 * distribution. 23 * 24 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' 25 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, 26 * THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR 27 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS 28 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 29 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 30 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR 31 * BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, 32 * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE 33 * OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN 34 * IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 35 * 36 * Description: Fast Path Operators 37 */ 38 39 #define dev_fmt(fmt) "QPLIB: " fmt 40 41 #include <linux/interrupt.h> 42 #include <linux/spinlock.h> 43 #include <linux/sched.h> 44 #include <linux/slab.h> 45 #include <linux/pci.h> 46 #include <linux/delay.h> 47 #include <linux/prefetch.h> 48 #include <linux/if_ether.h> 49 50 #include "roce_hsi.h" 51 52 #include "qplib_res.h" 53 #include "qplib_rcfw.h" 54 #include "qplib_sp.h" 55 #include "qplib_fp.h" 56 57 static void __clean_cq(struct bnxt_qplib_cq *cq, u64 qp); 58 59 static void bnxt_qplib_cancel_phantom_processing(struct bnxt_qplib_qp *qp) 60 { 61 qp->sq.condition = false; 62 qp->sq.send_phantom = false; 63 qp->sq.single = false; 64 } 65 66 /* Flush list */ 67 static void __bnxt_qplib_add_flush_qp(struct bnxt_qplib_qp *qp) 68 { 69 struct bnxt_qplib_cq *scq, *rcq; 70 71 scq = qp->scq; 72 rcq = qp->rcq; 73 74 if (!qp->sq.flushed) { 75 dev_dbg(&scq->hwq.pdev->dev, 76 "FP: Adding to SQ Flush list = %p\n", qp); 77 bnxt_qplib_cancel_phantom_processing(qp); 78 list_add_tail(&qp->sq_flush, &scq->sqf_head); 79 qp->sq.flushed = true; 80 } 81 if (!qp->srq) { 82 if (!qp->rq.flushed) { 83 dev_dbg(&rcq->hwq.pdev->dev, 84 "FP: Adding to RQ Flush list = %p\n", qp); 85 list_add_tail(&qp->rq_flush, &rcq->rqf_head); 86 qp->rq.flushed = true; 87 } 88 } 89 } 90 91 static void bnxt_qplib_acquire_cq_flush_locks(struct bnxt_qplib_qp *qp, 92 unsigned long *flags) 93 __acquires(&qp->scq->flush_lock) __acquires(&qp->rcq->flush_lock) 94 { 95 spin_lock_irqsave(&qp->scq->flush_lock, *flags); 96 if (qp->scq == qp->rcq) 97 __acquire(&qp->rcq->flush_lock); 98 else 99 spin_lock(&qp->rcq->flush_lock); 100 } 101 102 static void bnxt_qplib_release_cq_flush_locks(struct bnxt_qplib_qp *qp, 103 unsigned long *flags) 104 __releases(&qp->scq->flush_lock) __releases(&qp->rcq->flush_lock) 105 { 106 if (qp->scq == qp->rcq) 107 __release(&qp->rcq->flush_lock); 108 else 109 spin_unlock(&qp->rcq->flush_lock); 110 spin_unlock_irqrestore(&qp->scq->flush_lock, *flags); 111 } 112 113 void bnxt_qplib_add_flush_qp(struct bnxt_qplib_qp *qp) 114 { 115 unsigned long flags; 116 117 bnxt_qplib_acquire_cq_flush_locks(qp, &flags); 118 __bnxt_qplib_add_flush_qp(qp); 119 bnxt_qplib_release_cq_flush_locks(qp, &flags); 120 } 121 122 static void __bnxt_qplib_del_flush_qp(struct bnxt_qplib_qp *qp) 123 { 124 if (qp->sq.flushed) { 125 qp->sq.flushed = false; 126 list_del(&qp->sq_flush); 127 } 128 if (!qp->srq) { 129 if (qp->rq.flushed) { 130 qp->rq.flushed = false; 131 list_del(&qp->rq_flush); 132 } 133 } 134 } 135 136 void bnxt_qplib_clean_qp(struct bnxt_qplib_qp *qp) 137 { 138 unsigned long flags; 139 140 bnxt_qplib_acquire_cq_flush_locks(qp, &flags); 141 __clean_cq(qp->scq, (u64)(unsigned long)qp); 142 qp->sq.hwq.prod = 0; 143 qp->sq.hwq.cons = 0; 144 __clean_cq(qp->rcq, (u64)(unsigned long)qp); 145 qp->rq.hwq.prod = 0; 146 qp->rq.hwq.cons = 0; 147 148 __bnxt_qplib_del_flush_qp(qp); 149 bnxt_qplib_release_cq_flush_locks(qp, &flags); 150 } 151 152 static void bnxt_qpn_cqn_sched_task(struct work_struct *work) 153 { 154 struct bnxt_qplib_nq_work *nq_work = 155 container_of(work, struct bnxt_qplib_nq_work, work); 156 157 struct bnxt_qplib_cq *cq = nq_work->cq; 158 struct bnxt_qplib_nq *nq = nq_work->nq; 159 160 if (cq && nq) { 161 spin_lock_bh(&cq->compl_lock); 162 if (atomic_read(&cq->arm_state) && nq->cqn_handler) { 163 dev_dbg(&nq->pdev->dev, 164 "%s:Trigger cq = %p event nq = %p\n", 165 __func__, cq, nq); 166 nq->cqn_handler(nq, cq); 167 } 168 spin_unlock_bh(&cq->compl_lock); 169 } 170 kfree(nq_work); 171 } 172 173 static void bnxt_qplib_free_qp_hdr_buf(struct bnxt_qplib_res *res, 174 struct bnxt_qplib_qp *qp) 175 { 176 struct bnxt_qplib_q *rq = &qp->rq; 177 struct bnxt_qplib_q *sq = &qp->sq; 178 179 if (qp->rq_hdr_buf) 180 dma_free_coherent(&res->pdev->dev, 181 rq->max_wqe * qp->rq_hdr_buf_size, 182 qp->rq_hdr_buf, qp->rq_hdr_buf_map); 183 if (qp->sq_hdr_buf) 184 dma_free_coherent(&res->pdev->dev, 185 sq->max_wqe * qp->sq_hdr_buf_size, 186 qp->sq_hdr_buf, qp->sq_hdr_buf_map); 187 qp->rq_hdr_buf = NULL; 188 qp->sq_hdr_buf = NULL; 189 qp->rq_hdr_buf_map = 0; 190 qp->sq_hdr_buf_map = 0; 191 qp->sq_hdr_buf_size = 0; 192 qp->rq_hdr_buf_size = 0; 193 } 194 195 static int bnxt_qplib_alloc_qp_hdr_buf(struct bnxt_qplib_res *res, 196 struct bnxt_qplib_qp *qp) 197 { 198 struct bnxt_qplib_q *rq = &qp->rq; 199 struct bnxt_qplib_q *sq = &qp->sq; 200 int rc = 0; 201 202 if (qp->sq_hdr_buf_size && sq->max_wqe) { 203 qp->sq_hdr_buf = dma_alloc_coherent(&res->pdev->dev, 204 sq->max_wqe * qp->sq_hdr_buf_size, 205 &qp->sq_hdr_buf_map, GFP_KERNEL); 206 if (!qp->sq_hdr_buf) { 207 rc = -ENOMEM; 208 dev_err(&res->pdev->dev, 209 "Failed to create sq_hdr_buf\n"); 210 goto fail; 211 } 212 } 213 214 if (qp->rq_hdr_buf_size && rq->max_wqe) { 215 qp->rq_hdr_buf = dma_alloc_coherent(&res->pdev->dev, 216 rq->max_wqe * 217 qp->rq_hdr_buf_size, 218 &qp->rq_hdr_buf_map, 219 GFP_KERNEL); 220 if (!qp->rq_hdr_buf) { 221 rc = -ENOMEM; 222 dev_err(&res->pdev->dev, 223 "Failed to create rq_hdr_buf\n"); 224 goto fail; 225 } 226 } 227 return 0; 228 229 fail: 230 bnxt_qplib_free_qp_hdr_buf(res, qp); 231 return rc; 232 } 233 234 static void clean_nq(struct bnxt_qplib_nq *nq, struct bnxt_qplib_cq *cq) 235 { 236 struct bnxt_qplib_hwq *hwq = &nq->hwq; 237 struct nq_base *nqe, **nq_ptr; 238 int budget = nq->budget; 239 u32 sw_cons, raw_cons; 240 uintptr_t q_handle; 241 u16 type; 242 243 spin_lock_bh(&hwq->lock); 244 /* Service the NQ until empty */ 245 raw_cons = hwq->cons; 246 while (budget--) { 247 sw_cons = HWQ_CMP(raw_cons, hwq); 248 nq_ptr = (struct nq_base **)hwq->pbl_ptr; 249 nqe = &nq_ptr[NQE_PG(sw_cons)][NQE_IDX(sw_cons)]; 250 if (!NQE_CMP_VALID(nqe, raw_cons, hwq->max_elements)) 251 break; 252 253 /* 254 * The valid test of the entry must be done first before 255 * reading any further. 256 */ 257 dma_rmb(); 258 259 type = le16_to_cpu(nqe->info10_type) & NQ_BASE_TYPE_MASK; 260 switch (type) { 261 case NQ_BASE_TYPE_CQ_NOTIFICATION: 262 { 263 struct nq_cn *nqcne = (struct nq_cn *)nqe; 264 265 q_handle = le32_to_cpu(nqcne->cq_handle_low); 266 q_handle |= (u64)le32_to_cpu(nqcne->cq_handle_high) 267 << 32; 268 if ((unsigned long)cq == q_handle) { 269 nqcne->cq_handle_low = 0; 270 nqcne->cq_handle_high = 0; 271 cq->cnq_events++; 272 } 273 break; 274 } 275 default: 276 break; 277 } 278 raw_cons++; 279 } 280 spin_unlock_bh(&hwq->lock); 281 } 282 283 /* Wait for receiving all NQEs for this CQ and clean the NQEs associated with 284 * this CQ. 285 */ 286 static void __wait_for_all_nqes(struct bnxt_qplib_cq *cq, u16 cnq_events) 287 { 288 u32 retry_cnt = 100; 289 290 while (retry_cnt--) { 291 if (cnq_events == cq->cnq_events) 292 return; 293 usleep_range(50, 100); 294 clean_nq(cq->nq, cq); 295 } 296 } 297 298 static void bnxt_qplib_service_nq(unsigned long data) 299 { 300 struct bnxt_qplib_nq *nq = (struct bnxt_qplib_nq *)data; 301 struct bnxt_qplib_hwq *hwq = &nq->hwq; 302 int num_srqne_processed = 0; 303 int num_cqne_processed = 0; 304 struct bnxt_qplib_cq *cq; 305 int budget = nq->budget; 306 u32 sw_cons, raw_cons; 307 struct nq_base *nqe; 308 uintptr_t q_handle; 309 u16 type; 310 311 spin_lock_bh(&hwq->lock); 312 /* Service the NQ until empty */ 313 raw_cons = hwq->cons; 314 while (budget--) { 315 sw_cons = HWQ_CMP(raw_cons, hwq); 316 nqe = bnxt_qplib_get_qe(hwq, sw_cons, NULL); 317 if (!NQE_CMP_VALID(nqe, raw_cons, hwq->max_elements)) 318 break; 319 320 /* 321 * The valid test of the entry must be done first before 322 * reading any further. 323 */ 324 dma_rmb(); 325 326 type = le16_to_cpu(nqe->info10_type) & NQ_BASE_TYPE_MASK; 327 switch (type) { 328 case NQ_BASE_TYPE_CQ_NOTIFICATION: 329 { 330 struct nq_cn *nqcne = (struct nq_cn *)nqe; 331 332 q_handle = le32_to_cpu(nqcne->cq_handle_low); 333 q_handle |= (u64)le32_to_cpu(nqcne->cq_handle_high) 334 << 32; 335 cq = (struct bnxt_qplib_cq *)(unsigned long)q_handle; 336 if (!cq) 337 break; 338 bnxt_qplib_armen_db(&cq->dbinfo, 339 DBC_DBC_TYPE_CQ_ARMENA); 340 spin_lock_bh(&cq->compl_lock); 341 atomic_set(&cq->arm_state, 0); 342 if (!nq->cqn_handler(nq, (cq))) 343 num_cqne_processed++; 344 else 345 dev_warn(&nq->pdev->dev, 346 "cqn - type 0x%x not handled\n", type); 347 cq->cnq_events++; 348 spin_unlock_bh(&cq->compl_lock); 349 break; 350 } 351 case NQ_BASE_TYPE_SRQ_EVENT: 352 { 353 struct bnxt_qplib_srq *srq; 354 struct nq_srq_event *nqsrqe = 355 (struct nq_srq_event *)nqe; 356 357 q_handle = le32_to_cpu(nqsrqe->srq_handle_low); 358 q_handle |= (u64)le32_to_cpu(nqsrqe->srq_handle_high) 359 << 32; 360 srq = (struct bnxt_qplib_srq *)q_handle; 361 bnxt_qplib_armen_db(&srq->dbinfo, 362 DBC_DBC_TYPE_SRQ_ARMENA); 363 if (!nq->srqn_handler(nq, 364 (struct bnxt_qplib_srq *)q_handle, 365 nqsrqe->event)) 366 num_srqne_processed++; 367 else 368 dev_warn(&nq->pdev->dev, 369 "SRQ event 0x%x not handled\n", 370 nqsrqe->event); 371 break; 372 } 373 case NQ_BASE_TYPE_DBQ_EVENT: 374 break; 375 default: 376 dev_warn(&nq->pdev->dev, 377 "nqe with type = 0x%x not handled\n", type); 378 break; 379 } 380 raw_cons++; 381 } 382 if (hwq->cons != raw_cons) { 383 hwq->cons = raw_cons; 384 bnxt_qplib_ring_nq_db(&nq->nq_db.dbinfo, nq->res->cctx, true); 385 } 386 spin_unlock_bh(&hwq->lock); 387 } 388 389 static irqreturn_t bnxt_qplib_nq_irq(int irq, void *dev_instance) 390 { 391 struct bnxt_qplib_nq *nq = dev_instance; 392 struct bnxt_qplib_hwq *hwq = &nq->hwq; 393 u32 sw_cons; 394 395 /* Prefetch the NQ element */ 396 sw_cons = HWQ_CMP(hwq->cons, hwq); 397 prefetch(bnxt_qplib_get_qe(hwq, sw_cons, NULL)); 398 399 /* Fan out to CPU affinitized kthreads? */ 400 tasklet_schedule(&nq->nq_tasklet); 401 402 return IRQ_HANDLED; 403 } 404 405 void bnxt_qplib_nq_stop_irq(struct bnxt_qplib_nq *nq, bool kill) 406 { 407 tasklet_disable(&nq->nq_tasklet); 408 /* Mask h/w interrupt */ 409 bnxt_qplib_ring_nq_db(&nq->nq_db.dbinfo, nq->res->cctx, false); 410 /* Sync with last running IRQ handler */ 411 synchronize_irq(nq->msix_vec); 412 if (kill) 413 tasklet_kill(&nq->nq_tasklet); 414 if (nq->requested) { 415 irq_set_affinity_hint(nq->msix_vec, NULL); 416 free_irq(nq->msix_vec, nq); 417 nq->requested = false; 418 } 419 } 420 421 void bnxt_qplib_disable_nq(struct bnxt_qplib_nq *nq) 422 { 423 if (nq->cqn_wq) { 424 destroy_workqueue(nq->cqn_wq); 425 nq->cqn_wq = NULL; 426 } 427 428 /* Make sure the HW is stopped! */ 429 bnxt_qplib_nq_stop_irq(nq, true); 430 431 if (nq->nq_db.reg.bar_reg) { 432 iounmap(nq->nq_db.reg.bar_reg); 433 nq->nq_db.reg.bar_reg = NULL; 434 } 435 436 nq->cqn_handler = NULL; 437 nq->srqn_handler = NULL; 438 nq->msix_vec = 0; 439 } 440 441 int bnxt_qplib_nq_start_irq(struct bnxt_qplib_nq *nq, int nq_indx, 442 int msix_vector, bool need_init) 443 { 444 int rc; 445 446 if (nq->requested) 447 return -EFAULT; 448 449 nq->msix_vec = msix_vector; 450 if (need_init) 451 tasklet_init(&nq->nq_tasklet, bnxt_qplib_service_nq, 452 (unsigned long)nq); 453 else 454 tasklet_enable(&nq->nq_tasklet); 455 456 snprintf(nq->name, sizeof(nq->name), "bnxt_qplib_nq-%d", nq_indx); 457 rc = request_irq(nq->msix_vec, bnxt_qplib_nq_irq, 0, nq->name, nq); 458 if (rc) 459 return rc; 460 461 cpumask_clear(&nq->mask); 462 cpumask_set_cpu(nq_indx, &nq->mask); 463 rc = irq_set_affinity_hint(nq->msix_vec, &nq->mask); 464 if (rc) { 465 dev_warn(&nq->pdev->dev, 466 "set affinity failed; vector: %d nq_idx: %d\n", 467 nq->msix_vec, nq_indx); 468 } 469 nq->requested = true; 470 bnxt_qplib_ring_nq_db(&nq->nq_db.dbinfo, nq->res->cctx, true); 471 472 return rc; 473 } 474 475 static int bnxt_qplib_map_nq_db(struct bnxt_qplib_nq *nq, u32 reg_offt) 476 { 477 resource_size_t reg_base; 478 struct bnxt_qplib_nq_db *nq_db; 479 struct pci_dev *pdev; 480 int rc = 0; 481 482 pdev = nq->pdev; 483 nq_db = &nq->nq_db; 484 485 nq_db->reg.bar_id = NQ_CONS_PCI_BAR_REGION; 486 nq_db->reg.bar_base = pci_resource_start(pdev, nq_db->reg.bar_id); 487 if (!nq_db->reg.bar_base) { 488 dev_err(&pdev->dev, "QPLIB: NQ BAR region %d resc start is 0!", 489 nq_db->reg.bar_id); 490 rc = -ENOMEM; 491 goto fail; 492 } 493 494 reg_base = nq_db->reg.bar_base + reg_offt; 495 /* Unconditionally map 8 bytes to support 57500 series */ 496 nq_db->reg.len = 8; 497 nq_db->reg.bar_reg = ioremap(reg_base, nq_db->reg.len); 498 if (!nq_db->reg.bar_reg) { 499 dev_err(&pdev->dev, "QPLIB: NQ BAR region %d mapping failed", 500 nq_db->reg.bar_id); 501 rc = -ENOMEM; 502 goto fail; 503 } 504 505 nq_db->dbinfo.db = nq_db->reg.bar_reg; 506 nq_db->dbinfo.hwq = &nq->hwq; 507 nq_db->dbinfo.xid = nq->ring_id; 508 fail: 509 return rc; 510 } 511 512 int bnxt_qplib_enable_nq(struct pci_dev *pdev, struct bnxt_qplib_nq *nq, 513 int nq_idx, int msix_vector, int bar_reg_offset, 514 cqn_handler_t cqn_handler, 515 srqn_handler_t srqn_handler) 516 { 517 int rc = -1; 518 519 nq->pdev = pdev; 520 nq->cqn_handler = cqn_handler; 521 nq->srqn_handler = srqn_handler; 522 523 /* Have a task to schedule CQ notifiers in post send case */ 524 nq->cqn_wq = create_singlethread_workqueue("bnxt_qplib_nq"); 525 if (!nq->cqn_wq) 526 return -ENOMEM; 527 528 rc = bnxt_qplib_map_nq_db(nq, bar_reg_offset); 529 if (rc) 530 goto fail; 531 532 rc = bnxt_qplib_nq_start_irq(nq, nq_idx, msix_vector, true); 533 if (rc) { 534 dev_err(&nq->pdev->dev, 535 "Failed to request irq for nq-idx %d\n", nq_idx); 536 goto fail; 537 } 538 539 return 0; 540 fail: 541 bnxt_qplib_disable_nq(nq); 542 return rc; 543 } 544 545 void bnxt_qplib_free_nq(struct bnxt_qplib_nq *nq) 546 { 547 if (nq->hwq.max_elements) { 548 bnxt_qplib_free_hwq(nq->res, &nq->hwq); 549 nq->hwq.max_elements = 0; 550 } 551 } 552 553 int bnxt_qplib_alloc_nq(struct bnxt_qplib_res *res, struct bnxt_qplib_nq *nq) 554 { 555 struct bnxt_qplib_hwq_attr hwq_attr = {}; 556 struct bnxt_qplib_sg_info sginfo = {}; 557 558 nq->pdev = res->pdev; 559 nq->res = res; 560 if (!nq->hwq.max_elements || 561 nq->hwq.max_elements > BNXT_QPLIB_NQE_MAX_CNT) 562 nq->hwq.max_elements = BNXT_QPLIB_NQE_MAX_CNT; 563 564 sginfo.pgsize = PAGE_SIZE; 565 sginfo.pgshft = PAGE_SHIFT; 566 hwq_attr.res = res; 567 hwq_attr.sginfo = &sginfo; 568 hwq_attr.depth = nq->hwq.max_elements; 569 hwq_attr.stride = sizeof(struct nq_base); 570 hwq_attr.type = bnxt_qplib_get_hwq_type(nq->res); 571 if (bnxt_qplib_alloc_init_hwq(&nq->hwq, &hwq_attr)) { 572 dev_err(&nq->pdev->dev, "FP NQ allocation failed"); 573 return -ENOMEM; 574 } 575 nq->budget = 8; 576 return 0; 577 } 578 579 /* SRQ */ 580 void bnxt_qplib_destroy_srq(struct bnxt_qplib_res *res, 581 struct bnxt_qplib_srq *srq) 582 { 583 struct bnxt_qplib_rcfw *rcfw = res->rcfw; 584 struct cmdq_destroy_srq req; 585 struct creq_destroy_srq_resp resp; 586 u16 cmd_flags = 0; 587 int rc; 588 589 RCFW_CMD_PREP(req, DESTROY_SRQ, cmd_flags); 590 591 /* Configure the request */ 592 req.srq_cid = cpu_to_le32(srq->id); 593 594 rc = bnxt_qplib_rcfw_send_message(rcfw, (struct cmdq_base *)&req, 595 (struct creq_base *)&resp, NULL, 0); 596 kfree(srq->swq); 597 if (rc) 598 return; 599 bnxt_qplib_free_hwq(res, &srq->hwq); 600 } 601 602 int bnxt_qplib_create_srq(struct bnxt_qplib_res *res, 603 struct bnxt_qplib_srq *srq) 604 { 605 struct bnxt_qplib_rcfw *rcfw = res->rcfw; 606 struct bnxt_qplib_hwq_attr hwq_attr = {}; 607 struct creq_create_srq_resp resp; 608 struct cmdq_create_srq req; 609 struct bnxt_qplib_pbl *pbl; 610 u16 cmd_flags = 0; 611 u16 pg_sz_lvl; 612 int rc, idx; 613 614 hwq_attr.res = res; 615 hwq_attr.sginfo = &srq->sg_info; 616 hwq_attr.depth = srq->max_wqe; 617 hwq_attr.stride = srq->wqe_size; 618 hwq_attr.type = HWQ_TYPE_QUEUE; 619 rc = bnxt_qplib_alloc_init_hwq(&srq->hwq, &hwq_attr); 620 if (rc) 621 goto exit; 622 623 srq->swq = kcalloc(srq->hwq.max_elements, sizeof(*srq->swq), 624 GFP_KERNEL); 625 if (!srq->swq) { 626 rc = -ENOMEM; 627 goto fail; 628 } 629 630 RCFW_CMD_PREP(req, CREATE_SRQ, cmd_flags); 631 632 /* Configure the request */ 633 req.dpi = cpu_to_le32(srq->dpi->dpi); 634 req.srq_handle = cpu_to_le64((uintptr_t)srq); 635 636 req.srq_size = cpu_to_le16((u16)srq->hwq.max_elements); 637 pbl = &srq->hwq.pbl[PBL_LVL_0]; 638 pg_sz_lvl = ((u16)bnxt_qplib_base_pg_size(&srq->hwq) << 639 CMDQ_CREATE_SRQ_PG_SIZE_SFT); 640 pg_sz_lvl |= (srq->hwq.level & CMDQ_CREATE_SRQ_LVL_MASK) << 641 CMDQ_CREATE_SRQ_LVL_SFT; 642 req.pg_size_lvl = cpu_to_le16(pg_sz_lvl); 643 req.pbl = cpu_to_le64(pbl->pg_map_arr[0]); 644 req.pd_id = cpu_to_le32(srq->pd->id); 645 req.eventq_id = cpu_to_le16(srq->eventq_hw_ring_id); 646 647 rc = bnxt_qplib_rcfw_send_message(rcfw, (void *)&req, 648 (void *)&resp, NULL, 0); 649 if (rc) 650 goto fail; 651 652 spin_lock_init(&srq->lock); 653 srq->start_idx = 0; 654 srq->last_idx = srq->hwq.max_elements - 1; 655 for (idx = 0; idx < srq->hwq.max_elements; idx++) 656 srq->swq[idx].next_idx = idx + 1; 657 srq->swq[srq->last_idx].next_idx = -1; 658 659 srq->id = le32_to_cpu(resp.xid); 660 srq->dbinfo.hwq = &srq->hwq; 661 srq->dbinfo.xid = srq->id; 662 srq->dbinfo.db = srq->dpi->dbr; 663 srq->dbinfo.max_slot = 1; 664 srq->dbinfo.priv_db = res->dpi_tbl.dbr_bar_reg_iomem; 665 if (srq->threshold) 666 bnxt_qplib_armen_db(&srq->dbinfo, DBC_DBC_TYPE_SRQ_ARMENA); 667 srq->arm_req = false; 668 669 return 0; 670 fail: 671 bnxt_qplib_free_hwq(res, &srq->hwq); 672 kfree(srq->swq); 673 exit: 674 return rc; 675 } 676 677 int bnxt_qplib_modify_srq(struct bnxt_qplib_res *res, 678 struct bnxt_qplib_srq *srq) 679 { 680 struct bnxt_qplib_hwq *srq_hwq = &srq->hwq; 681 u32 sw_prod, sw_cons, count = 0; 682 683 sw_prod = HWQ_CMP(srq_hwq->prod, srq_hwq); 684 sw_cons = HWQ_CMP(srq_hwq->cons, srq_hwq); 685 686 count = sw_prod > sw_cons ? sw_prod - sw_cons : 687 srq_hwq->max_elements - sw_cons + sw_prod; 688 if (count > srq->threshold) { 689 srq->arm_req = false; 690 bnxt_qplib_srq_arm_db(&srq->dbinfo, srq->threshold); 691 } else { 692 /* Deferred arming */ 693 srq->arm_req = true; 694 } 695 696 return 0; 697 } 698 699 int bnxt_qplib_query_srq(struct bnxt_qplib_res *res, 700 struct bnxt_qplib_srq *srq) 701 { 702 struct bnxt_qplib_rcfw *rcfw = res->rcfw; 703 struct cmdq_query_srq req; 704 struct creq_query_srq_resp resp; 705 struct bnxt_qplib_rcfw_sbuf *sbuf; 706 struct creq_query_srq_resp_sb *sb; 707 u16 cmd_flags = 0; 708 int rc = 0; 709 710 RCFW_CMD_PREP(req, QUERY_SRQ, cmd_flags); 711 req.srq_cid = cpu_to_le32(srq->id); 712 713 /* Configure the request */ 714 sbuf = bnxt_qplib_rcfw_alloc_sbuf(rcfw, sizeof(*sb)); 715 if (!sbuf) 716 return -ENOMEM; 717 sb = sbuf->sb; 718 rc = bnxt_qplib_rcfw_send_message(rcfw, (void *)&req, (void *)&resp, 719 (void *)sbuf, 0); 720 srq->threshold = le16_to_cpu(sb->srq_limit); 721 bnxt_qplib_rcfw_free_sbuf(rcfw, sbuf); 722 723 return rc; 724 } 725 726 int bnxt_qplib_post_srq_recv(struct bnxt_qplib_srq *srq, 727 struct bnxt_qplib_swqe *wqe) 728 { 729 struct bnxt_qplib_hwq *srq_hwq = &srq->hwq; 730 struct rq_wqe *srqe; 731 struct sq_sge *hw_sge; 732 u32 sw_prod, sw_cons, count = 0; 733 int i, rc = 0, next; 734 735 spin_lock(&srq_hwq->lock); 736 if (srq->start_idx == srq->last_idx) { 737 dev_err(&srq_hwq->pdev->dev, 738 "FP: SRQ (0x%x) is full!\n", srq->id); 739 rc = -EINVAL; 740 spin_unlock(&srq_hwq->lock); 741 goto done; 742 } 743 next = srq->start_idx; 744 srq->start_idx = srq->swq[next].next_idx; 745 spin_unlock(&srq_hwq->lock); 746 747 sw_prod = HWQ_CMP(srq_hwq->prod, srq_hwq); 748 srqe = bnxt_qplib_get_qe(srq_hwq, sw_prod, NULL); 749 memset(srqe, 0, srq->wqe_size); 750 /* Calculate wqe_size16 and data_len */ 751 for (i = 0, hw_sge = (struct sq_sge *)srqe->data; 752 i < wqe->num_sge; i++, hw_sge++) { 753 hw_sge->va_or_pa = cpu_to_le64(wqe->sg_list[i].addr); 754 hw_sge->l_key = cpu_to_le32(wqe->sg_list[i].lkey); 755 hw_sge->size = cpu_to_le32(wqe->sg_list[i].size); 756 } 757 srqe->wqe_type = wqe->type; 758 srqe->flags = wqe->flags; 759 srqe->wqe_size = wqe->num_sge + 760 ((offsetof(typeof(*srqe), data) + 15) >> 4); 761 srqe->wr_id[0] = cpu_to_le32((u32)next); 762 srq->swq[next].wr_id = wqe->wr_id; 763 764 srq_hwq->prod++; 765 766 spin_lock(&srq_hwq->lock); 767 sw_prod = HWQ_CMP(srq_hwq->prod, srq_hwq); 768 /* retaining srq_hwq->cons for this logic 769 * actually the lock is only required to 770 * read srq_hwq->cons. 771 */ 772 sw_cons = HWQ_CMP(srq_hwq->cons, srq_hwq); 773 count = sw_prod > sw_cons ? sw_prod - sw_cons : 774 srq_hwq->max_elements - sw_cons + sw_prod; 775 spin_unlock(&srq_hwq->lock); 776 /* Ring DB */ 777 bnxt_qplib_ring_prod_db(&srq->dbinfo, DBC_DBC_TYPE_SRQ); 778 if (srq->arm_req == true && count > srq->threshold) { 779 srq->arm_req = false; 780 bnxt_qplib_srq_arm_db(&srq->dbinfo, srq->threshold); 781 } 782 done: 783 return rc; 784 } 785 786 /* QP */ 787 788 static int bnxt_qplib_alloc_init_swq(struct bnxt_qplib_q *que) 789 { 790 int rc = 0; 791 int indx; 792 793 que->swq = kcalloc(que->max_wqe, sizeof(*que->swq), GFP_KERNEL); 794 if (!que->swq) { 795 rc = -ENOMEM; 796 goto out; 797 } 798 799 que->swq_start = 0; 800 que->swq_last = que->max_wqe - 1; 801 for (indx = 0; indx < que->max_wqe; indx++) 802 que->swq[indx].next_idx = indx + 1; 803 que->swq[que->swq_last].next_idx = 0; /* Make it circular */ 804 que->swq_last = 0; 805 out: 806 return rc; 807 } 808 809 int bnxt_qplib_create_qp1(struct bnxt_qplib_res *res, struct bnxt_qplib_qp *qp) 810 { 811 struct bnxt_qplib_hwq_attr hwq_attr = {}; 812 struct bnxt_qplib_rcfw *rcfw = res->rcfw; 813 struct bnxt_qplib_q *sq = &qp->sq; 814 struct bnxt_qplib_q *rq = &qp->rq; 815 struct creq_create_qp1_resp resp; 816 struct cmdq_create_qp1 req; 817 struct bnxt_qplib_pbl *pbl; 818 u16 cmd_flags = 0; 819 u32 qp_flags = 0; 820 u8 pg_sz_lvl; 821 u32 tbl_indx; 822 int rc; 823 824 RCFW_CMD_PREP(req, CREATE_QP1, cmd_flags); 825 826 /* General */ 827 req.type = qp->type; 828 req.dpi = cpu_to_le32(qp->dpi->dpi); 829 req.qp_handle = cpu_to_le64(qp->qp_handle); 830 831 /* SQ */ 832 hwq_attr.res = res; 833 hwq_attr.sginfo = &sq->sg_info; 834 hwq_attr.stride = sizeof(struct sq_sge); 835 hwq_attr.depth = bnxt_qplib_get_depth(sq); 836 hwq_attr.type = HWQ_TYPE_QUEUE; 837 rc = bnxt_qplib_alloc_init_hwq(&sq->hwq, &hwq_attr); 838 if (rc) 839 goto exit; 840 841 rc = bnxt_qplib_alloc_init_swq(sq); 842 if (rc) 843 goto fail_sq; 844 845 req.sq_size = cpu_to_le32(bnxt_qplib_set_sq_size(sq, qp->wqe_mode)); 846 pbl = &sq->hwq.pbl[PBL_LVL_0]; 847 req.sq_pbl = cpu_to_le64(pbl->pg_map_arr[0]); 848 pg_sz_lvl = (bnxt_qplib_base_pg_size(&sq->hwq) << 849 CMDQ_CREATE_QP1_SQ_PG_SIZE_SFT); 850 pg_sz_lvl |= (sq->hwq.level & CMDQ_CREATE_QP1_SQ_LVL_MASK); 851 req.sq_pg_size_sq_lvl = pg_sz_lvl; 852 req.sq_fwo_sq_sge = 853 cpu_to_le16((sq->max_sge & CMDQ_CREATE_QP1_SQ_SGE_MASK) << 854 CMDQ_CREATE_QP1_SQ_SGE_SFT); 855 req.scq_cid = cpu_to_le32(qp->scq->id); 856 857 /* RQ */ 858 if (rq->max_wqe) { 859 hwq_attr.res = res; 860 hwq_attr.sginfo = &rq->sg_info; 861 hwq_attr.stride = sizeof(struct sq_sge); 862 hwq_attr.depth = bnxt_qplib_get_depth(rq); 863 hwq_attr.type = HWQ_TYPE_QUEUE; 864 rc = bnxt_qplib_alloc_init_hwq(&rq->hwq, &hwq_attr); 865 if (rc) 866 goto sq_swq; 867 rc = bnxt_qplib_alloc_init_swq(rq); 868 if (rc) 869 goto fail_rq; 870 req.rq_size = cpu_to_le32(rq->max_wqe); 871 pbl = &rq->hwq.pbl[PBL_LVL_0]; 872 req.rq_pbl = cpu_to_le64(pbl->pg_map_arr[0]); 873 pg_sz_lvl = (bnxt_qplib_base_pg_size(&rq->hwq) << 874 CMDQ_CREATE_QP1_RQ_PG_SIZE_SFT); 875 pg_sz_lvl |= (rq->hwq.level & CMDQ_CREATE_QP1_RQ_LVL_MASK); 876 req.rq_pg_size_rq_lvl = pg_sz_lvl; 877 req.rq_fwo_rq_sge = 878 cpu_to_le16((rq->max_sge & 879 CMDQ_CREATE_QP1_RQ_SGE_MASK) << 880 CMDQ_CREATE_QP1_RQ_SGE_SFT); 881 } 882 req.rcq_cid = cpu_to_le32(qp->rcq->id); 883 /* Header buffer - allow hdr_buf pass in */ 884 rc = bnxt_qplib_alloc_qp_hdr_buf(res, qp); 885 if (rc) { 886 rc = -ENOMEM; 887 goto rq_rwq; 888 } 889 qp_flags |= CMDQ_CREATE_QP1_QP_FLAGS_RESERVED_LKEY_ENABLE; 890 req.qp_flags = cpu_to_le32(qp_flags); 891 req.pd_id = cpu_to_le32(qp->pd->id); 892 893 rc = bnxt_qplib_rcfw_send_message(rcfw, (void *)&req, 894 (void *)&resp, NULL, 0); 895 if (rc) 896 goto fail; 897 898 qp->id = le32_to_cpu(resp.xid); 899 qp->cur_qp_state = CMDQ_MODIFY_QP_NEW_STATE_RESET; 900 qp->cctx = res->cctx; 901 sq->dbinfo.hwq = &sq->hwq; 902 sq->dbinfo.xid = qp->id; 903 sq->dbinfo.db = qp->dpi->dbr; 904 sq->dbinfo.max_slot = bnxt_qplib_set_sq_max_slot(qp->wqe_mode); 905 if (rq->max_wqe) { 906 rq->dbinfo.hwq = &rq->hwq; 907 rq->dbinfo.xid = qp->id; 908 rq->dbinfo.db = qp->dpi->dbr; 909 rq->dbinfo.max_slot = bnxt_qplib_set_rq_max_slot(rq->wqe_size); 910 } 911 tbl_indx = map_qp_id_to_tbl_indx(qp->id, rcfw); 912 rcfw->qp_tbl[tbl_indx].qp_id = qp->id; 913 rcfw->qp_tbl[tbl_indx].qp_handle = (void *)qp; 914 915 return 0; 916 917 fail: 918 bnxt_qplib_free_qp_hdr_buf(res, qp); 919 rq_rwq: 920 kfree(rq->swq); 921 fail_rq: 922 bnxt_qplib_free_hwq(res, &rq->hwq); 923 sq_swq: 924 kfree(sq->swq); 925 fail_sq: 926 bnxt_qplib_free_hwq(res, &sq->hwq); 927 exit: 928 return rc; 929 } 930 931 static void bnxt_qplib_init_psn_ptr(struct bnxt_qplib_qp *qp, int size) 932 { 933 struct bnxt_qplib_hwq *hwq; 934 struct bnxt_qplib_q *sq; 935 u64 fpsne, psn_pg; 936 u16 indx_pad = 0; 937 938 sq = &qp->sq; 939 hwq = &sq->hwq; 940 /* First psn entry */ 941 fpsne = (u64)bnxt_qplib_get_qe(hwq, hwq->depth, &psn_pg); 942 if (!IS_ALIGNED(fpsne, PAGE_SIZE)) 943 indx_pad = (fpsne & ~PAGE_MASK) / size; 944 hwq->pad_pgofft = indx_pad; 945 hwq->pad_pg = (u64 *)psn_pg; 946 hwq->pad_stride = size; 947 } 948 949 int bnxt_qplib_create_qp(struct bnxt_qplib_res *res, struct bnxt_qplib_qp *qp) 950 { 951 struct bnxt_qplib_rcfw *rcfw = res->rcfw; 952 struct bnxt_qplib_hwq_attr hwq_attr = {}; 953 struct bnxt_qplib_sg_info sginfo = {}; 954 struct bnxt_qplib_q *sq = &qp->sq; 955 struct bnxt_qplib_q *rq = &qp->rq; 956 struct creq_create_qp_resp resp; 957 int rc, req_size, psn_sz = 0; 958 struct bnxt_qplib_hwq *xrrq; 959 struct bnxt_qplib_pbl *pbl; 960 struct cmdq_create_qp req; 961 u16 cmd_flags = 0; 962 u32 qp_flags = 0; 963 u8 pg_sz_lvl; 964 u32 tbl_indx; 965 u16 nsge; 966 967 RCFW_CMD_PREP(req, CREATE_QP, cmd_flags); 968 969 /* General */ 970 req.type = qp->type; 971 req.dpi = cpu_to_le32(qp->dpi->dpi); 972 req.qp_handle = cpu_to_le64(qp->qp_handle); 973 974 /* SQ */ 975 if (qp->type == CMDQ_CREATE_QP_TYPE_RC) { 976 psn_sz = bnxt_qplib_is_chip_gen_p5(res->cctx) ? 977 sizeof(struct sq_psn_search_ext) : 978 sizeof(struct sq_psn_search); 979 } 980 981 hwq_attr.res = res; 982 hwq_attr.sginfo = &sq->sg_info; 983 hwq_attr.stride = sizeof(struct sq_sge); 984 hwq_attr.depth = bnxt_qplib_get_depth(sq); 985 hwq_attr.aux_stride = psn_sz; 986 hwq_attr.aux_depth = bnxt_qplib_set_sq_size(sq, qp->wqe_mode); 987 hwq_attr.type = HWQ_TYPE_QUEUE; 988 rc = bnxt_qplib_alloc_init_hwq(&sq->hwq, &hwq_attr); 989 if (rc) 990 goto exit; 991 992 rc = bnxt_qplib_alloc_init_swq(sq); 993 if (rc) 994 goto fail_sq; 995 996 if (psn_sz) 997 bnxt_qplib_init_psn_ptr(qp, psn_sz); 998 999 req.sq_size = cpu_to_le32(bnxt_qplib_set_sq_size(sq, qp->wqe_mode)); 1000 pbl = &sq->hwq.pbl[PBL_LVL_0]; 1001 req.sq_pbl = cpu_to_le64(pbl->pg_map_arr[0]); 1002 pg_sz_lvl = (bnxt_qplib_base_pg_size(&sq->hwq) << 1003 CMDQ_CREATE_QP_SQ_PG_SIZE_SFT); 1004 pg_sz_lvl |= (sq->hwq.level & CMDQ_CREATE_QP_SQ_LVL_MASK); 1005 req.sq_pg_size_sq_lvl = pg_sz_lvl; 1006 req.sq_fwo_sq_sge = 1007 cpu_to_le16(((sq->max_sge & CMDQ_CREATE_QP_SQ_SGE_MASK) << 1008 CMDQ_CREATE_QP_SQ_SGE_SFT) | 0); 1009 req.scq_cid = cpu_to_le32(qp->scq->id); 1010 1011 /* RQ */ 1012 if (!qp->srq) { 1013 hwq_attr.res = res; 1014 hwq_attr.sginfo = &rq->sg_info; 1015 hwq_attr.stride = sizeof(struct sq_sge); 1016 hwq_attr.depth = bnxt_qplib_get_depth(rq); 1017 hwq_attr.aux_stride = 0; 1018 hwq_attr.aux_depth = 0; 1019 hwq_attr.type = HWQ_TYPE_QUEUE; 1020 rc = bnxt_qplib_alloc_init_hwq(&rq->hwq, &hwq_attr); 1021 if (rc) 1022 goto sq_swq; 1023 rc = bnxt_qplib_alloc_init_swq(rq); 1024 if (rc) 1025 goto fail_rq; 1026 1027 req.rq_size = cpu_to_le32(rq->max_wqe); 1028 pbl = &rq->hwq.pbl[PBL_LVL_0]; 1029 req.rq_pbl = cpu_to_le64(pbl->pg_map_arr[0]); 1030 pg_sz_lvl = (bnxt_qplib_base_pg_size(&rq->hwq) << 1031 CMDQ_CREATE_QP_RQ_PG_SIZE_SFT); 1032 pg_sz_lvl |= (rq->hwq.level & CMDQ_CREATE_QP_RQ_LVL_MASK); 1033 req.rq_pg_size_rq_lvl = pg_sz_lvl; 1034 nsge = (qp->wqe_mode == BNXT_QPLIB_WQE_MODE_STATIC) ? 1035 6 : rq->max_sge; 1036 req.rq_fwo_rq_sge = 1037 cpu_to_le16(((nsge & 1038 CMDQ_CREATE_QP_RQ_SGE_MASK) << 1039 CMDQ_CREATE_QP_RQ_SGE_SFT) | 0); 1040 } else { 1041 /* SRQ */ 1042 qp_flags |= CMDQ_CREATE_QP_QP_FLAGS_SRQ_USED; 1043 req.srq_cid = cpu_to_le32(qp->srq->id); 1044 } 1045 req.rcq_cid = cpu_to_le32(qp->rcq->id); 1046 1047 qp_flags |= CMDQ_CREATE_QP_QP_FLAGS_RESERVED_LKEY_ENABLE; 1048 qp_flags |= CMDQ_CREATE_QP_QP_FLAGS_FR_PMR_ENABLED; 1049 if (qp->sig_type) 1050 qp_flags |= CMDQ_CREATE_QP_QP_FLAGS_FORCE_COMPLETION; 1051 if (qp->wqe_mode == BNXT_QPLIB_WQE_MODE_VARIABLE) 1052 qp_flags |= CMDQ_CREATE_QP_QP_FLAGS_VARIABLE_SIZED_WQE_ENABLED; 1053 req.qp_flags = cpu_to_le32(qp_flags); 1054 1055 /* ORRQ and IRRQ */ 1056 if (psn_sz) { 1057 xrrq = &qp->orrq; 1058 xrrq->max_elements = 1059 ORD_LIMIT_TO_ORRQ_SLOTS(qp->max_rd_atomic); 1060 req_size = xrrq->max_elements * 1061 BNXT_QPLIB_MAX_ORRQE_ENTRY_SIZE + PAGE_SIZE - 1; 1062 req_size &= ~(PAGE_SIZE - 1); 1063 sginfo.pgsize = req_size; 1064 sginfo.pgshft = PAGE_SHIFT; 1065 1066 hwq_attr.res = res; 1067 hwq_attr.sginfo = &sginfo; 1068 hwq_attr.depth = xrrq->max_elements; 1069 hwq_attr.stride = BNXT_QPLIB_MAX_ORRQE_ENTRY_SIZE; 1070 hwq_attr.aux_stride = 0; 1071 hwq_attr.aux_depth = 0; 1072 hwq_attr.type = HWQ_TYPE_CTX; 1073 rc = bnxt_qplib_alloc_init_hwq(xrrq, &hwq_attr); 1074 if (rc) 1075 goto rq_swq; 1076 pbl = &xrrq->pbl[PBL_LVL_0]; 1077 req.orrq_addr = cpu_to_le64(pbl->pg_map_arr[0]); 1078 1079 xrrq = &qp->irrq; 1080 xrrq->max_elements = IRD_LIMIT_TO_IRRQ_SLOTS( 1081 qp->max_dest_rd_atomic); 1082 req_size = xrrq->max_elements * 1083 BNXT_QPLIB_MAX_IRRQE_ENTRY_SIZE + PAGE_SIZE - 1; 1084 req_size &= ~(PAGE_SIZE - 1); 1085 sginfo.pgsize = req_size; 1086 hwq_attr.depth = xrrq->max_elements; 1087 hwq_attr.stride = BNXT_QPLIB_MAX_IRRQE_ENTRY_SIZE; 1088 rc = bnxt_qplib_alloc_init_hwq(xrrq, &hwq_attr); 1089 if (rc) 1090 goto fail_orrq; 1091 1092 pbl = &xrrq->pbl[PBL_LVL_0]; 1093 req.irrq_addr = cpu_to_le64(pbl->pg_map_arr[0]); 1094 } 1095 req.pd_id = cpu_to_le32(qp->pd->id); 1096 1097 rc = bnxt_qplib_rcfw_send_message(rcfw, (void *)&req, 1098 (void *)&resp, NULL, 0); 1099 if (rc) 1100 goto fail; 1101 1102 qp->id = le32_to_cpu(resp.xid); 1103 qp->cur_qp_state = CMDQ_MODIFY_QP_NEW_STATE_RESET; 1104 INIT_LIST_HEAD(&qp->sq_flush); 1105 INIT_LIST_HEAD(&qp->rq_flush); 1106 qp->cctx = res->cctx; 1107 sq->dbinfo.hwq = &sq->hwq; 1108 sq->dbinfo.xid = qp->id; 1109 sq->dbinfo.db = qp->dpi->dbr; 1110 sq->dbinfo.max_slot = bnxt_qplib_set_sq_max_slot(qp->wqe_mode); 1111 if (rq->max_wqe) { 1112 rq->dbinfo.hwq = &rq->hwq; 1113 rq->dbinfo.xid = qp->id; 1114 rq->dbinfo.db = qp->dpi->dbr; 1115 rq->dbinfo.max_slot = bnxt_qplib_set_rq_max_slot(rq->wqe_size); 1116 } 1117 tbl_indx = map_qp_id_to_tbl_indx(qp->id, rcfw); 1118 rcfw->qp_tbl[tbl_indx].qp_id = qp->id; 1119 rcfw->qp_tbl[tbl_indx].qp_handle = (void *)qp; 1120 1121 return 0; 1122 fail: 1123 bnxt_qplib_free_hwq(res, &qp->irrq); 1124 fail_orrq: 1125 bnxt_qplib_free_hwq(res, &qp->orrq); 1126 rq_swq: 1127 kfree(rq->swq); 1128 fail_rq: 1129 bnxt_qplib_free_hwq(res, &rq->hwq); 1130 sq_swq: 1131 kfree(sq->swq); 1132 fail_sq: 1133 bnxt_qplib_free_hwq(res, &sq->hwq); 1134 exit: 1135 return rc; 1136 } 1137 1138 static void __modify_flags_from_init_state(struct bnxt_qplib_qp *qp) 1139 { 1140 switch (qp->state) { 1141 case CMDQ_MODIFY_QP_NEW_STATE_RTR: 1142 /* INIT->RTR, configure the path_mtu to the default 1143 * 2048 if not being requested 1144 */ 1145 if (!(qp->modify_flags & 1146 CMDQ_MODIFY_QP_MODIFY_MASK_PATH_MTU)) { 1147 qp->modify_flags |= 1148 CMDQ_MODIFY_QP_MODIFY_MASK_PATH_MTU; 1149 qp->path_mtu = 1150 CMDQ_MODIFY_QP_PATH_MTU_MTU_2048; 1151 } 1152 qp->modify_flags &= 1153 ~CMDQ_MODIFY_QP_MODIFY_MASK_VLAN_ID; 1154 /* Bono FW require the max_dest_rd_atomic to be >= 1 */ 1155 if (qp->max_dest_rd_atomic < 1) 1156 qp->max_dest_rd_atomic = 1; 1157 qp->modify_flags &= ~CMDQ_MODIFY_QP_MODIFY_MASK_SRC_MAC; 1158 /* Bono FW 20.6.5 requires SGID_INDEX configuration */ 1159 if (!(qp->modify_flags & 1160 CMDQ_MODIFY_QP_MODIFY_MASK_SGID_INDEX)) { 1161 qp->modify_flags |= 1162 CMDQ_MODIFY_QP_MODIFY_MASK_SGID_INDEX; 1163 qp->ah.sgid_index = 0; 1164 } 1165 break; 1166 default: 1167 break; 1168 } 1169 } 1170 1171 static void __modify_flags_from_rtr_state(struct bnxt_qplib_qp *qp) 1172 { 1173 switch (qp->state) { 1174 case CMDQ_MODIFY_QP_NEW_STATE_RTS: 1175 /* Bono FW requires the max_rd_atomic to be >= 1 */ 1176 if (qp->max_rd_atomic < 1) 1177 qp->max_rd_atomic = 1; 1178 /* Bono FW does not allow PKEY_INDEX, 1179 * DGID, FLOW_LABEL, SGID_INDEX, HOP_LIMIT, 1180 * TRAFFIC_CLASS, DEST_MAC, PATH_MTU, RQ_PSN, 1181 * MIN_RNR_TIMER, MAX_DEST_RD_ATOMIC, DEST_QP_ID 1182 * modification 1183 */ 1184 qp->modify_flags &= 1185 ~(CMDQ_MODIFY_QP_MODIFY_MASK_PKEY | 1186 CMDQ_MODIFY_QP_MODIFY_MASK_DGID | 1187 CMDQ_MODIFY_QP_MODIFY_MASK_FLOW_LABEL | 1188 CMDQ_MODIFY_QP_MODIFY_MASK_SGID_INDEX | 1189 CMDQ_MODIFY_QP_MODIFY_MASK_HOP_LIMIT | 1190 CMDQ_MODIFY_QP_MODIFY_MASK_TRAFFIC_CLASS | 1191 CMDQ_MODIFY_QP_MODIFY_MASK_DEST_MAC | 1192 CMDQ_MODIFY_QP_MODIFY_MASK_PATH_MTU | 1193 CMDQ_MODIFY_QP_MODIFY_MASK_RQ_PSN | 1194 CMDQ_MODIFY_QP_MODIFY_MASK_MIN_RNR_TIMER | 1195 CMDQ_MODIFY_QP_MODIFY_MASK_MAX_DEST_RD_ATOMIC | 1196 CMDQ_MODIFY_QP_MODIFY_MASK_DEST_QP_ID); 1197 break; 1198 default: 1199 break; 1200 } 1201 } 1202 1203 static void __filter_modify_flags(struct bnxt_qplib_qp *qp) 1204 { 1205 switch (qp->cur_qp_state) { 1206 case CMDQ_MODIFY_QP_NEW_STATE_RESET: 1207 break; 1208 case CMDQ_MODIFY_QP_NEW_STATE_INIT: 1209 __modify_flags_from_init_state(qp); 1210 break; 1211 case CMDQ_MODIFY_QP_NEW_STATE_RTR: 1212 __modify_flags_from_rtr_state(qp); 1213 break; 1214 case CMDQ_MODIFY_QP_NEW_STATE_RTS: 1215 break; 1216 case CMDQ_MODIFY_QP_NEW_STATE_SQD: 1217 break; 1218 case CMDQ_MODIFY_QP_NEW_STATE_SQE: 1219 break; 1220 case CMDQ_MODIFY_QP_NEW_STATE_ERR: 1221 break; 1222 default: 1223 break; 1224 } 1225 } 1226 1227 int bnxt_qplib_modify_qp(struct bnxt_qplib_res *res, struct bnxt_qplib_qp *qp) 1228 { 1229 struct bnxt_qplib_rcfw *rcfw = res->rcfw; 1230 struct cmdq_modify_qp req; 1231 struct creq_modify_qp_resp resp; 1232 u16 cmd_flags = 0, pkey; 1233 u32 temp32[4]; 1234 u32 bmask; 1235 int rc; 1236 1237 RCFW_CMD_PREP(req, MODIFY_QP, cmd_flags); 1238 1239 /* Filter out the qp_attr_mask based on the state->new transition */ 1240 __filter_modify_flags(qp); 1241 bmask = qp->modify_flags; 1242 req.modify_mask = cpu_to_le32(qp->modify_flags); 1243 req.qp_cid = cpu_to_le32(qp->id); 1244 if (bmask & CMDQ_MODIFY_QP_MODIFY_MASK_STATE) { 1245 req.network_type_en_sqd_async_notify_new_state = 1246 (qp->state & CMDQ_MODIFY_QP_NEW_STATE_MASK) | 1247 (qp->en_sqd_async_notify ? 1248 CMDQ_MODIFY_QP_EN_SQD_ASYNC_NOTIFY : 0); 1249 } 1250 req.network_type_en_sqd_async_notify_new_state |= qp->nw_type; 1251 1252 if (bmask & CMDQ_MODIFY_QP_MODIFY_MASK_ACCESS) 1253 req.access = qp->access; 1254 1255 if (bmask & CMDQ_MODIFY_QP_MODIFY_MASK_PKEY) { 1256 if (!bnxt_qplib_get_pkey(res, &res->pkey_tbl, 1257 qp->pkey_index, &pkey)) 1258 req.pkey = cpu_to_le16(pkey); 1259 } 1260 if (bmask & CMDQ_MODIFY_QP_MODIFY_MASK_QKEY) 1261 req.qkey = cpu_to_le32(qp->qkey); 1262 1263 if (bmask & CMDQ_MODIFY_QP_MODIFY_MASK_DGID) { 1264 memcpy(temp32, qp->ah.dgid.data, sizeof(struct bnxt_qplib_gid)); 1265 req.dgid[0] = cpu_to_le32(temp32[0]); 1266 req.dgid[1] = cpu_to_le32(temp32[1]); 1267 req.dgid[2] = cpu_to_le32(temp32[2]); 1268 req.dgid[3] = cpu_to_le32(temp32[3]); 1269 } 1270 if (bmask & CMDQ_MODIFY_QP_MODIFY_MASK_FLOW_LABEL) 1271 req.flow_label = cpu_to_le32(qp->ah.flow_label); 1272 1273 if (bmask & CMDQ_MODIFY_QP_MODIFY_MASK_SGID_INDEX) 1274 req.sgid_index = cpu_to_le16(res->sgid_tbl.hw_id 1275 [qp->ah.sgid_index]); 1276 1277 if (bmask & CMDQ_MODIFY_QP_MODIFY_MASK_HOP_LIMIT) 1278 req.hop_limit = qp->ah.hop_limit; 1279 1280 if (bmask & CMDQ_MODIFY_QP_MODIFY_MASK_TRAFFIC_CLASS) 1281 req.traffic_class = qp->ah.traffic_class; 1282 1283 if (bmask & CMDQ_MODIFY_QP_MODIFY_MASK_DEST_MAC) 1284 memcpy(req.dest_mac, qp->ah.dmac, 6); 1285 1286 if (bmask & CMDQ_MODIFY_QP_MODIFY_MASK_PATH_MTU) 1287 req.path_mtu = qp->path_mtu; 1288 1289 if (bmask & CMDQ_MODIFY_QP_MODIFY_MASK_TIMEOUT) 1290 req.timeout = qp->timeout; 1291 1292 if (bmask & CMDQ_MODIFY_QP_MODIFY_MASK_RETRY_CNT) 1293 req.retry_cnt = qp->retry_cnt; 1294 1295 if (bmask & CMDQ_MODIFY_QP_MODIFY_MASK_RNR_RETRY) 1296 req.rnr_retry = qp->rnr_retry; 1297 1298 if (bmask & CMDQ_MODIFY_QP_MODIFY_MASK_MIN_RNR_TIMER) 1299 req.min_rnr_timer = qp->min_rnr_timer; 1300 1301 if (bmask & CMDQ_MODIFY_QP_MODIFY_MASK_RQ_PSN) 1302 req.rq_psn = cpu_to_le32(qp->rq.psn); 1303 1304 if (bmask & CMDQ_MODIFY_QP_MODIFY_MASK_SQ_PSN) 1305 req.sq_psn = cpu_to_le32(qp->sq.psn); 1306 1307 if (bmask & CMDQ_MODIFY_QP_MODIFY_MASK_MAX_RD_ATOMIC) 1308 req.max_rd_atomic = 1309 ORD_LIMIT_TO_ORRQ_SLOTS(qp->max_rd_atomic); 1310 1311 if (bmask & CMDQ_MODIFY_QP_MODIFY_MASK_MAX_DEST_RD_ATOMIC) 1312 req.max_dest_rd_atomic = 1313 IRD_LIMIT_TO_IRRQ_SLOTS(qp->max_dest_rd_atomic); 1314 1315 req.sq_size = cpu_to_le32(qp->sq.hwq.max_elements); 1316 req.rq_size = cpu_to_le32(qp->rq.hwq.max_elements); 1317 req.sq_sge = cpu_to_le16(qp->sq.max_sge); 1318 req.rq_sge = cpu_to_le16(qp->rq.max_sge); 1319 req.max_inline_data = cpu_to_le32(qp->max_inline_data); 1320 if (bmask & CMDQ_MODIFY_QP_MODIFY_MASK_DEST_QP_ID) 1321 req.dest_qp_id = cpu_to_le32(qp->dest_qpn); 1322 1323 req.vlan_pcp_vlan_dei_vlan_id = cpu_to_le16(qp->vlan_id); 1324 1325 rc = bnxt_qplib_rcfw_send_message(rcfw, (void *)&req, 1326 (void *)&resp, NULL, 0); 1327 if (rc) 1328 return rc; 1329 qp->cur_qp_state = qp->state; 1330 return 0; 1331 } 1332 1333 int bnxt_qplib_query_qp(struct bnxt_qplib_res *res, struct bnxt_qplib_qp *qp) 1334 { 1335 struct bnxt_qplib_rcfw *rcfw = res->rcfw; 1336 struct cmdq_query_qp req; 1337 struct creq_query_qp_resp resp; 1338 struct bnxt_qplib_rcfw_sbuf *sbuf; 1339 struct creq_query_qp_resp_sb *sb; 1340 u16 cmd_flags = 0; 1341 u32 temp32[4]; 1342 int i, rc = 0; 1343 1344 RCFW_CMD_PREP(req, QUERY_QP, cmd_flags); 1345 1346 sbuf = bnxt_qplib_rcfw_alloc_sbuf(rcfw, sizeof(*sb)); 1347 if (!sbuf) 1348 return -ENOMEM; 1349 sb = sbuf->sb; 1350 1351 req.qp_cid = cpu_to_le32(qp->id); 1352 req.resp_size = sizeof(*sb) / BNXT_QPLIB_CMDQE_UNITS; 1353 rc = bnxt_qplib_rcfw_send_message(rcfw, (void *)&req, (void *)&resp, 1354 (void *)sbuf, 0); 1355 if (rc) 1356 goto bail; 1357 /* Extract the context from the side buffer */ 1358 qp->state = sb->en_sqd_async_notify_state & 1359 CREQ_QUERY_QP_RESP_SB_STATE_MASK; 1360 qp->en_sqd_async_notify = sb->en_sqd_async_notify_state & 1361 CREQ_QUERY_QP_RESP_SB_EN_SQD_ASYNC_NOTIFY ? 1362 true : false; 1363 qp->access = sb->access; 1364 qp->pkey_index = le16_to_cpu(sb->pkey); 1365 qp->qkey = le32_to_cpu(sb->qkey); 1366 1367 temp32[0] = le32_to_cpu(sb->dgid[0]); 1368 temp32[1] = le32_to_cpu(sb->dgid[1]); 1369 temp32[2] = le32_to_cpu(sb->dgid[2]); 1370 temp32[3] = le32_to_cpu(sb->dgid[3]); 1371 memcpy(qp->ah.dgid.data, temp32, sizeof(qp->ah.dgid.data)); 1372 1373 qp->ah.flow_label = le32_to_cpu(sb->flow_label); 1374 1375 qp->ah.sgid_index = 0; 1376 for (i = 0; i < res->sgid_tbl.max; i++) { 1377 if (res->sgid_tbl.hw_id[i] == le16_to_cpu(sb->sgid_index)) { 1378 qp->ah.sgid_index = i; 1379 break; 1380 } 1381 } 1382 if (i == res->sgid_tbl.max) 1383 dev_warn(&res->pdev->dev, "SGID not found??\n"); 1384 1385 qp->ah.hop_limit = sb->hop_limit; 1386 qp->ah.traffic_class = sb->traffic_class; 1387 memcpy(qp->ah.dmac, sb->dest_mac, 6); 1388 qp->ah.vlan_id = (le16_to_cpu(sb->path_mtu_dest_vlan_id) & 1389 CREQ_QUERY_QP_RESP_SB_VLAN_ID_MASK) >> 1390 CREQ_QUERY_QP_RESP_SB_VLAN_ID_SFT; 1391 qp->path_mtu = (le16_to_cpu(sb->path_mtu_dest_vlan_id) & 1392 CREQ_QUERY_QP_RESP_SB_PATH_MTU_MASK) >> 1393 CREQ_QUERY_QP_RESP_SB_PATH_MTU_SFT; 1394 qp->timeout = sb->timeout; 1395 qp->retry_cnt = sb->retry_cnt; 1396 qp->rnr_retry = sb->rnr_retry; 1397 qp->min_rnr_timer = sb->min_rnr_timer; 1398 qp->rq.psn = le32_to_cpu(sb->rq_psn); 1399 qp->max_rd_atomic = ORRQ_SLOTS_TO_ORD_LIMIT(sb->max_rd_atomic); 1400 qp->sq.psn = le32_to_cpu(sb->sq_psn); 1401 qp->max_dest_rd_atomic = 1402 IRRQ_SLOTS_TO_IRD_LIMIT(sb->max_dest_rd_atomic); 1403 qp->sq.max_wqe = qp->sq.hwq.max_elements; 1404 qp->rq.max_wqe = qp->rq.hwq.max_elements; 1405 qp->sq.max_sge = le16_to_cpu(sb->sq_sge); 1406 qp->rq.max_sge = le16_to_cpu(sb->rq_sge); 1407 qp->max_inline_data = le32_to_cpu(sb->max_inline_data); 1408 qp->dest_qpn = le32_to_cpu(sb->dest_qp_id); 1409 memcpy(qp->smac, sb->src_mac, 6); 1410 qp->vlan_id = le16_to_cpu(sb->vlan_pcp_vlan_dei_vlan_id); 1411 bail: 1412 bnxt_qplib_rcfw_free_sbuf(rcfw, sbuf); 1413 return rc; 1414 } 1415 1416 static void __clean_cq(struct bnxt_qplib_cq *cq, u64 qp) 1417 { 1418 struct bnxt_qplib_hwq *cq_hwq = &cq->hwq; 1419 struct cq_base *hw_cqe; 1420 int i; 1421 1422 for (i = 0; i < cq_hwq->max_elements; i++) { 1423 hw_cqe = bnxt_qplib_get_qe(cq_hwq, i, NULL); 1424 if (!CQE_CMP_VALID(hw_cqe, i, cq_hwq->max_elements)) 1425 continue; 1426 /* 1427 * The valid test of the entry must be done first before 1428 * reading any further. 1429 */ 1430 dma_rmb(); 1431 switch (hw_cqe->cqe_type_toggle & CQ_BASE_CQE_TYPE_MASK) { 1432 case CQ_BASE_CQE_TYPE_REQ: 1433 case CQ_BASE_CQE_TYPE_TERMINAL: 1434 { 1435 struct cq_req *cqe = (struct cq_req *)hw_cqe; 1436 1437 if (qp == le64_to_cpu(cqe->qp_handle)) 1438 cqe->qp_handle = 0; 1439 break; 1440 } 1441 case CQ_BASE_CQE_TYPE_RES_RC: 1442 case CQ_BASE_CQE_TYPE_RES_UD: 1443 case CQ_BASE_CQE_TYPE_RES_RAWETH_QP1: 1444 { 1445 struct cq_res_rc *cqe = (struct cq_res_rc *)hw_cqe; 1446 1447 if (qp == le64_to_cpu(cqe->qp_handle)) 1448 cqe->qp_handle = 0; 1449 break; 1450 } 1451 default: 1452 break; 1453 } 1454 } 1455 } 1456 1457 int bnxt_qplib_destroy_qp(struct bnxt_qplib_res *res, 1458 struct bnxt_qplib_qp *qp) 1459 { 1460 struct bnxt_qplib_rcfw *rcfw = res->rcfw; 1461 struct cmdq_destroy_qp req; 1462 struct creq_destroy_qp_resp resp; 1463 u16 cmd_flags = 0; 1464 u32 tbl_indx; 1465 int rc; 1466 1467 tbl_indx = map_qp_id_to_tbl_indx(qp->id, rcfw); 1468 rcfw->qp_tbl[tbl_indx].qp_id = BNXT_QPLIB_QP_ID_INVALID; 1469 rcfw->qp_tbl[tbl_indx].qp_handle = NULL; 1470 1471 RCFW_CMD_PREP(req, DESTROY_QP, cmd_flags); 1472 1473 req.qp_cid = cpu_to_le32(qp->id); 1474 rc = bnxt_qplib_rcfw_send_message(rcfw, (void *)&req, 1475 (void *)&resp, NULL, 0); 1476 if (rc) { 1477 rcfw->qp_tbl[tbl_indx].qp_id = qp->id; 1478 rcfw->qp_tbl[tbl_indx].qp_handle = qp; 1479 return rc; 1480 } 1481 1482 return 0; 1483 } 1484 1485 void bnxt_qplib_free_qp_res(struct bnxt_qplib_res *res, 1486 struct bnxt_qplib_qp *qp) 1487 { 1488 bnxt_qplib_free_qp_hdr_buf(res, qp); 1489 bnxt_qplib_free_hwq(res, &qp->sq.hwq); 1490 kfree(qp->sq.swq); 1491 1492 bnxt_qplib_free_hwq(res, &qp->rq.hwq); 1493 kfree(qp->rq.swq); 1494 1495 if (qp->irrq.max_elements) 1496 bnxt_qplib_free_hwq(res, &qp->irrq); 1497 if (qp->orrq.max_elements) 1498 bnxt_qplib_free_hwq(res, &qp->orrq); 1499 1500 } 1501 1502 void *bnxt_qplib_get_qp1_sq_buf(struct bnxt_qplib_qp *qp, 1503 struct bnxt_qplib_sge *sge) 1504 { 1505 struct bnxt_qplib_q *sq = &qp->sq; 1506 u32 sw_prod; 1507 1508 memset(sge, 0, sizeof(*sge)); 1509 1510 if (qp->sq_hdr_buf) { 1511 sw_prod = sq->swq_start; 1512 sge->addr = (dma_addr_t)(qp->sq_hdr_buf_map + 1513 sw_prod * qp->sq_hdr_buf_size); 1514 sge->lkey = 0xFFFFFFFF; 1515 sge->size = qp->sq_hdr_buf_size; 1516 return qp->sq_hdr_buf + sw_prod * sge->size; 1517 } 1518 return NULL; 1519 } 1520 1521 u32 bnxt_qplib_get_rq_prod_index(struct bnxt_qplib_qp *qp) 1522 { 1523 struct bnxt_qplib_q *rq = &qp->rq; 1524 1525 return rq->swq_start; 1526 } 1527 1528 dma_addr_t bnxt_qplib_get_qp_buf_from_index(struct bnxt_qplib_qp *qp, u32 index) 1529 { 1530 return (qp->rq_hdr_buf_map + index * qp->rq_hdr_buf_size); 1531 } 1532 1533 void *bnxt_qplib_get_qp1_rq_buf(struct bnxt_qplib_qp *qp, 1534 struct bnxt_qplib_sge *sge) 1535 { 1536 struct bnxt_qplib_q *rq = &qp->rq; 1537 u32 sw_prod; 1538 1539 memset(sge, 0, sizeof(*sge)); 1540 1541 if (qp->rq_hdr_buf) { 1542 sw_prod = rq->swq_start; 1543 sge->addr = (dma_addr_t)(qp->rq_hdr_buf_map + 1544 sw_prod * qp->rq_hdr_buf_size); 1545 sge->lkey = 0xFFFFFFFF; 1546 sge->size = qp->rq_hdr_buf_size; 1547 return qp->rq_hdr_buf + sw_prod * sge->size; 1548 } 1549 return NULL; 1550 } 1551 1552 static void bnxt_qplib_fill_psn_search(struct bnxt_qplib_qp *qp, 1553 struct bnxt_qplib_swqe *wqe, 1554 struct bnxt_qplib_swq *swq) 1555 { 1556 struct sq_psn_search_ext *psns_ext; 1557 struct sq_psn_search *psns; 1558 u32 flg_npsn; 1559 u32 op_spsn; 1560 1561 if (!swq->psn_search) 1562 return; 1563 psns = swq->psn_search; 1564 psns_ext = swq->psn_ext; 1565 1566 op_spsn = ((swq->start_psn << SQ_PSN_SEARCH_START_PSN_SFT) & 1567 SQ_PSN_SEARCH_START_PSN_MASK); 1568 op_spsn |= ((wqe->type << SQ_PSN_SEARCH_OPCODE_SFT) & 1569 SQ_PSN_SEARCH_OPCODE_MASK); 1570 flg_npsn = ((swq->next_psn << SQ_PSN_SEARCH_NEXT_PSN_SFT) & 1571 SQ_PSN_SEARCH_NEXT_PSN_MASK); 1572 1573 if (bnxt_qplib_is_chip_gen_p5(qp->cctx)) { 1574 psns_ext->opcode_start_psn = cpu_to_le32(op_spsn); 1575 psns_ext->flags_next_psn = cpu_to_le32(flg_npsn); 1576 psns_ext->start_slot_idx = cpu_to_le16(swq->slot_idx); 1577 } else { 1578 psns->opcode_start_psn = cpu_to_le32(op_spsn); 1579 psns->flags_next_psn = cpu_to_le32(flg_npsn); 1580 } 1581 } 1582 1583 static int bnxt_qplib_put_inline(struct bnxt_qplib_qp *qp, 1584 struct bnxt_qplib_swqe *wqe, 1585 u16 *idx) 1586 { 1587 struct bnxt_qplib_hwq *hwq; 1588 int len, t_len, offt; 1589 bool pull_dst = true; 1590 void *il_dst = NULL; 1591 void *il_src = NULL; 1592 int t_cplen, cplen; 1593 int indx; 1594 1595 hwq = &qp->sq.hwq; 1596 t_len = 0; 1597 for (indx = 0; indx < wqe->num_sge; indx++) { 1598 len = wqe->sg_list[indx].size; 1599 il_src = (void *)wqe->sg_list[indx].addr; 1600 t_len += len; 1601 if (t_len > qp->max_inline_data) 1602 goto bad; 1603 while (len) { 1604 if (pull_dst) { 1605 pull_dst = false; 1606 il_dst = bnxt_qplib_get_prod_qe(hwq, *idx); 1607 (*idx)++; 1608 t_cplen = 0; 1609 offt = 0; 1610 } 1611 cplen = min_t(int, len, sizeof(struct sq_sge)); 1612 cplen = min_t(int, cplen, 1613 (sizeof(struct sq_sge) - offt)); 1614 memcpy(il_dst, il_src, cplen); 1615 t_cplen += cplen; 1616 il_src += cplen; 1617 il_dst += cplen; 1618 offt += cplen; 1619 len -= cplen; 1620 if (t_cplen == sizeof(struct sq_sge)) 1621 pull_dst = true; 1622 } 1623 } 1624 1625 return t_len; 1626 bad: 1627 return -ENOMEM; 1628 } 1629 1630 static u32 bnxt_qplib_put_sges(struct bnxt_qplib_hwq *hwq, 1631 struct bnxt_qplib_sge *ssge, 1632 u16 nsge, u16 *idx) 1633 { 1634 struct sq_sge *dsge; 1635 int indx, len = 0; 1636 1637 for (indx = 0; indx < nsge; indx++, (*idx)++) { 1638 dsge = bnxt_qplib_get_prod_qe(hwq, *idx); 1639 dsge->va_or_pa = cpu_to_le64(ssge[indx].addr); 1640 dsge->l_key = cpu_to_le32(ssge[indx].lkey); 1641 dsge->size = cpu_to_le32(ssge[indx].size); 1642 len += ssge[indx].size; 1643 } 1644 1645 return len; 1646 } 1647 1648 static u16 bnxt_qplib_required_slots(struct bnxt_qplib_qp *qp, 1649 struct bnxt_qplib_swqe *wqe, 1650 u16 *wqe_sz, u16 *qdf, u8 mode) 1651 { 1652 u32 ilsize, bytes; 1653 u16 nsge; 1654 u16 slot; 1655 1656 nsge = wqe->num_sge; 1657 /* Adding sq_send_hdr is a misnomer, for rq also hdr size is same. */ 1658 bytes = sizeof(struct sq_send_hdr) + nsge * sizeof(struct sq_sge); 1659 if (wqe->flags & BNXT_QPLIB_SWQE_FLAGS_INLINE) { 1660 ilsize = bnxt_qplib_calc_ilsize(wqe, qp->max_inline_data); 1661 bytes = ALIGN(ilsize, sizeof(struct sq_sge)); 1662 bytes += sizeof(struct sq_send_hdr); 1663 } 1664 1665 *qdf = __xlate_qfd(qp->sq.q_full_delta, bytes); 1666 slot = bytes >> 4; 1667 *wqe_sz = slot; 1668 if (mode == BNXT_QPLIB_WQE_MODE_STATIC) 1669 slot = 8; 1670 return slot; 1671 } 1672 1673 static void bnxt_qplib_pull_psn_buff(struct bnxt_qplib_q *sq, 1674 struct bnxt_qplib_swq *swq) 1675 { 1676 struct bnxt_qplib_hwq *hwq; 1677 u32 pg_num, pg_indx; 1678 void *buff; 1679 u32 tail; 1680 1681 hwq = &sq->hwq; 1682 if (!hwq->pad_pg) 1683 return; 1684 tail = swq->slot_idx / sq->dbinfo.max_slot; 1685 pg_num = (tail + hwq->pad_pgofft) / (PAGE_SIZE / hwq->pad_stride); 1686 pg_indx = (tail + hwq->pad_pgofft) % (PAGE_SIZE / hwq->pad_stride); 1687 buff = (void *)(hwq->pad_pg[pg_num] + pg_indx * hwq->pad_stride); 1688 swq->psn_ext = buff; 1689 swq->psn_search = buff; 1690 } 1691 1692 void bnxt_qplib_post_send_db(struct bnxt_qplib_qp *qp) 1693 { 1694 struct bnxt_qplib_q *sq = &qp->sq; 1695 1696 bnxt_qplib_ring_prod_db(&sq->dbinfo, DBC_DBC_TYPE_SQ); 1697 } 1698 1699 int bnxt_qplib_post_send(struct bnxt_qplib_qp *qp, 1700 struct bnxt_qplib_swqe *wqe) 1701 { 1702 struct bnxt_qplib_nq_work *nq_work = NULL; 1703 int i, rc = 0, data_len = 0, pkt_num = 0; 1704 struct bnxt_qplib_q *sq = &qp->sq; 1705 struct bnxt_qplib_hwq *hwq; 1706 struct bnxt_qplib_swq *swq; 1707 bool sch_handler = false; 1708 u16 wqe_sz, qdf = 0; 1709 void *base_hdr; 1710 void *ext_hdr; 1711 __le32 temp32; 1712 u32 wqe_idx; 1713 u32 slots; 1714 u16 idx; 1715 1716 hwq = &sq->hwq; 1717 if (qp->state != CMDQ_MODIFY_QP_NEW_STATE_RTS && 1718 qp->state != CMDQ_MODIFY_QP_NEW_STATE_ERR) { 1719 dev_err(&hwq->pdev->dev, 1720 "QPLIB: FP: QP (0x%x) is in the 0x%x state", 1721 qp->id, qp->state); 1722 rc = -EINVAL; 1723 goto done; 1724 } 1725 1726 slots = bnxt_qplib_required_slots(qp, wqe, &wqe_sz, &qdf, qp->wqe_mode); 1727 if (bnxt_qplib_queue_full(sq, slots + qdf)) { 1728 dev_err(&hwq->pdev->dev, 1729 "prod = %#x cons = %#x qdepth = %#x delta = %#x\n", 1730 hwq->prod, hwq->cons, hwq->depth, sq->q_full_delta); 1731 rc = -ENOMEM; 1732 goto done; 1733 } 1734 1735 swq = bnxt_qplib_get_swqe(sq, &wqe_idx); 1736 bnxt_qplib_pull_psn_buff(sq, swq); 1737 1738 idx = 0; 1739 swq->slot_idx = hwq->prod; 1740 swq->slots = slots; 1741 swq->wr_id = wqe->wr_id; 1742 swq->type = wqe->type; 1743 swq->flags = wqe->flags; 1744 swq->start_psn = sq->psn & BTH_PSN_MASK; 1745 if (qp->sig_type) 1746 swq->flags |= SQ_SEND_FLAGS_SIGNAL_COMP; 1747 1748 if (qp->state == CMDQ_MODIFY_QP_NEW_STATE_ERR) { 1749 sch_handler = true; 1750 dev_dbg(&hwq->pdev->dev, 1751 "%s Error QP. Scheduling for poll_cq\n", __func__); 1752 goto queue_err; 1753 } 1754 1755 base_hdr = bnxt_qplib_get_prod_qe(hwq, idx++); 1756 ext_hdr = bnxt_qplib_get_prod_qe(hwq, idx++); 1757 memset(base_hdr, 0, sizeof(struct sq_sge)); 1758 memset(ext_hdr, 0, sizeof(struct sq_sge)); 1759 1760 if (wqe->flags & BNXT_QPLIB_SWQE_FLAGS_INLINE) 1761 /* Copy the inline data */ 1762 data_len = bnxt_qplib_put_inline(qp, wqe, &idx); 1763 else 1764 data_len = bnxt_qplib_put_sges(hwq, wqe->sg_list, wqe->num_sge, 1765 &idx); 1766 if (data_len < 0) 1767 goto queue_err; 1768 /* Specifics */ 1769 switch (wqe->type) { 1770 case BNXT_QPLIB_SWQE_TYPE_SEND: 1771 if (qp->type == CMDQ_CREATE_QP1_TYPE_GSI) { 1772 struct sq_send_raweth_qp1_hdr *sqe = base_hdr; 1773 struct sq_raw_ext_hdr *ext_sqe = ext_hdr; 1774 /* Assemble info for Raw Ethertype QPs */ 1775 1776 sqe->wqe_type = wqe->type; 1777 sqe->flags = wqe->flags; 1778 sqe->wqe_size = wqe_sz; 1779 sqe->cfa_action = cpu_to_le16(wqe->rawqp1.cfa_action); 1780 sqe->lflags = cpu_to_le16(wqe->rawqp1.lflags); 1781 sqe->length = cpu_to_le32(data_len); 1782 ext_sqe->cfa_meta = cpu_to_le32((wqe->rawqp1.cfa_meta & 1783 SQ_SEND_RAWETH_QP1_CFA_META_VLAN_VID_MASK) << 1784 SQ_SEND_RAWETH_QP1_CFA_META_VLAN_VID_SFT); 1785 1786 break; 1787 } 1788 fallthrough; 1789 case BNXT_QPLIB_SWQE_TYPE_SEND_WITH_IMM: 1790 case BNXT_QPLIB_SWQE_TYPE_SEND_WITH_INV: 1791 { 1792 struct sq_ud_ext_hdr *ext_sqe = ext_hdr; 1793 struct sq_send_hdr *sqe = base_hdr; 1794 1795 sqe->wqe_type = wqe->type; 1796 sqe->flags = wqe->flags; 1797 sqe->wqe_size = wqe_sz; 1798 sqe->inv_key_or_imm_data = cpu_to_le32(wqe->send.inv_key); 1799 if (qp->type == CMDQ_CREATE_QP_TYPE_UD || 1800 qp->type == CMDQ_CREATE_QP_TYPE_GSI) { 1801 sqe->q_key = cpu_to_le32(wqe->send.q_key); 1802 sqe->length = cpu_to_le32(data_len); 1803 sq->psn = (sq->psn + 1) & BTH_PSN_MASK; 1804 ext_sqe->dst_qp = cpu_to_le32(wqe->send.dst_qp & 1805 SQ_SEND_DST_QP_MASK); 1806 ext_sqe->avid = cpu_to_le32(wqe->send.avid & 1807 SQ_SEND_AVID_MASK); 1808 } else { 1809 sqe->length = cpu_to_le32(data_len); 1810 if (qp->mtu) 1811 pkt_num = (data_len + qp->mtu - 1) / qp->mtu; 1812 if (!pkt_num) 1813 pkt_num = 1; 1814 sq->psn = (sq->psn + pkt_num) & BTH_PSN_MASK; 1815 } 1816 break; 1817 } 1818 case BNXT_QPLIB_SWQE_TYPE_RDMA_WRITE: 1819 case BNXT_QPLIB_SWQE_TYPE_RDMA_WRITE_WITH_IMM: 1820 case BNXT_QPLIB_SWQE_TYPE_RDMA_READ: 1821 { 1822 struct sq_rdma_ext_hdr *ext_sqe = ext_hdr; 1823 struct sq_rdma_hdr *sqe = base_hdr; 1824 1825 sqe->wqe_type = wqe->type; 1826 sqe->flags = wqe->flags; 1827 sqe->wqe_size = wqe_sz; 1828 sqe->imm_data = cpu_to_le32(wqe->rdma.inv_key); 1829 sqe->length = cpu_to_le32((u32)data_len); 1830 ext_sqe->remote_va = cpu_to_le64(wqe->rdma.remote_va); 1831 ext_sqe->remote_key = cpu_to_le32(wqe->rdma.r_key); 1832 if (qp->mtu) 1833 pkt_num = (data_len + qp->mtu - 1) / qp->mtu; 1834 if (!pkt_num) 1835 pkt_num = 1; 1836 sq->psn = (sq->psn + pkt_num) & BTH_PSN_MASK; 1837 break; 1838 } 1839 case BNXT_QPLIB_SWQE_TYPE_ATOMIC_CMP_AND_SWP: 1840 case BNXT_QPLIB_SWQE_TYPE_ATOMIC_FETCH_AND_ADD: 1841 { 1842 struct sq_atomic_ext_hdr *ext_sqe = ext_hdr; 1843 struct sq_atomic_hdr *sqe = base_hdr; 1844 1845 sqe->wqe_type = wqe->type; 1846 sqe->flags = wqe->flags; 1847 sqe->remote_key = cpu_to_le32(wqe->atomic.r_key); 1848 sqe->remote_va = cpu_to_le64(wqe->atomic.remote_va); 1849 ext_sqe->swap_data = cpu_to_le64(wqe->atomic.swap_data); 1850 ext_sqe->cmp_data = cpu_to_le64(wqe->atomic.cmp_data); 1851 if (qp->mtu) 1852 pkt_num = (data_len + qp->mtu - 1) / qp->mtu; 1853 if (!pkt_num) 1854 pkt_num = 1; 1855 sq->psn = (sq->psn + pkt_num) & BTH_PSN_MASK; 1856 break; 1857 } 1858 case BNXT_QPLIB_SWQE_TYPE_LOCAL_INV: 1859 { 1860 struct sq_localinvalidate *sqe = base_hdr; 1861 1862 sqe->wqe_type = wqe->type; 1863 sqe->flags = wqe->flags; 1864 sqe->inv_l_key = cpu_to_le32(wqe->local_inv.inv_l_key); 1865 1866 break; 1867 } 1868 case BNXT_QPLIB_SWQE_TYPE_FAST_REG_MR: 1869 { 1870 struct sq_fr_pmr_ext_hdr *ext_sqe = ext_hdr; 1871 struct sq_fr_pmr_hdr *sqe = base_hdr; 1872 1873 sqe->wqe_type = wqe->type; 1874 sqe->flags = wqe->flags; 1875 sqe->access_cntl = wqe->frmr.access_cntl | 1876 SQ_FR_PMR_ACCESS_CNTL_LOCAL_WRITE; 1877 sqe->zero_based_page_size_log = 1878 (wqe->frmr.pg_sz_log & SQ_FR_PMR_PAGE_SIZE_LOG_MASK) << 1879 SQ_FR_PMR_PAGE_SIZE_LOG_SFT | 1880 (wqe->frmr.zero_based ? SQ_FR_PMR_ZERO_BASED : 0); 1881 sqe->l_key = cpu_to_le32(wqe->frmr.l_key); 1882 temp32 = cpu_to_le32(wqe->frmr.length); 1883 memcpy(sqe->length, &temp32, sizeof(wqe->frmr.length)); 1884 sqe->numlevels_pbl_page_size_log = 1885 ((wqe->frmr.pbl_pg_sz_log << 1886 SQ_FR_PMR_PBL_PAGE_SIZE_LOG_SFT) & 1887 SQ_FR_PMR_PBL_PAGE_SIZE_LOG_MASK) | 1888 ((wqe->frmr.levels << SQ_FR_PMR_NUMLEVELS_SFT) & 1889 SQ_FR_PMR_NUMLEVELS_MASK); 1890 1891 for (i = 0; i < wqe->frmr.page_list_len; i++) 1892 wqe->frmr.pbl_ptr[i] = cpu_to_le64( 1893 wqe->frmr.page_list[i] | 1894 PTU_PTE_VALID); 1895 ext_sqe->pblptr = cpu_to_le64(wqe->frmr.pbl_dma_ptr); 1896 ext_sqe->va = cpu_to_le64(wqe->frmr.va); 1897 1898 break; 1899 } 1900 case BNXT_QPLIB_SWQE_TYPE_BIND_MW: 1901 { 1902 struct sq_bind_ext_hdr *ext_sqe = ext_hdr; 1903 struct sq_bind_hdr *sqe = base_hdr; 1904 1905 sqe->wqe_type = wqe->type; 1906 sqe->flags = wqe->flags; 1907 sqe->access_cntl = wqe->bind.access_cntl; 1908 sqe->mw_type_zero_based = wqe->bind.mw_type | 1909 (wqe->bind.zero_based ? SQ_BIND_ZERO_BASED : 0); 1910 sqe->parent_l_key = cpu_to_le32(wqe->bind.parent_l_key); 1911 sqe->l_key = cpu_to_le32(wqe->bind.r_key); 1912 ext_sqe->va = cpu_to_le64(wqe->bind.va); 1913 ext_sqe->length_lo = cpu_to_le32(wqe->bind.length); 1914 break; 1915 } 1916 default: 1917 /* Bad wqe, return error */ 1918 rc = -EINVAL; 1919 goto done; 1920 } 1921 swq->next_psn = sq->psn & BTH_PSN_MASK; 1922 bnxt_qplib_fill_psn_search(qp, wqe, swq); 1923 queue_err: 1924 bnxt_qplib_swq_mod_start(sq, wqe_idx); 1925 bnxt_qplib_hwq_incr_prod(hwq, swq->slots); 1926 qp->wqe_cnt++; 1927 done: 1928 if (sch_handler) { 1929 nq_work = kzalloc(sizeof(*nq_work), GFP_ATOMIC); 1930 if (nq_work) { 1931 nq_work->cq = qp->scq; 1932 nq_work->nq = qp->scq->nq; 1933 INIT_WORK(&nq_work->work, bnxt_qpn_cqn_sched_task); 1934 queue_work(qp->scq->nq->cqn_wq, &nq_work->work); 1935 } else { 1936 dev_err(&hwq->pdev->dev, 1937 "FP: Failed to allocate SQ nq_work!\n"); 1938 rc = -ENOMEM; 1939 } 1940 } 1941 return rc; 1942 } 1943 1944 void bnxt_qplib_post_recv_db(struct bnxt_qplib_qp *qp) 1945 { 1946 struct bnxt_qplib_q *rq = &qp->rq; 1947 1948 bnxt_qplib_ring_prod_db(&rq->dbinfo, DBC_DBC_TYPE_RQ); 1949 } 1950 1951 int bnxt_qplib_post_recv(struct bnxt_qplib_qp *qp, 1952 struct bnxt_qplib_swqe *wqe) 1953 { 1954 struct bnxt_qplib_nq_work *nq_work = NULL; 1955 struct bnxt_qplib_q *rq = &qp->rq; 1956 struct rq_wqe_hdr *base_hdr; 1957 struct rq_ext_hdr *ext_hdr; 1958 struct bnxt_qplib_hwq *hwq; 1959 struct bnxt_qplib_swq *swq; 1960 bool sch_handler = false; 1961 u16 wqe_sz, idx; 1962 u32 wqe_idx; 1963 int rc = 0; 1964 1965 hwq = &rq->hwq; 1966 if (qp->state == CMDQ_MODIFY_QP_NEW_STATE_RESET) { 1967 dev_err(&hwq->pdev->dev, 1968 "QPLIB: FP: QP (0x%x) is in the 0x%x state", 1969 qp->id, qp->state); 1970 rc = -EINVAL; 1971 goto done; 1972 } 1973 1974 if (bnxt_qplib_queue_full(rq, rq->dbinfo.max_slot)) { 1975 dev_err(&hwq->pdev->dev, 1976 "FP: QP (0x%x) RQ is full!\n", qp->id); 1977 rc = -EINVAL; 1978 goto done; 1979 } 1980 1981 swq = bnxt_qplib_get_swqe(rq, &wqe_idx); 1982 swq->wr_id = wqe->wr_id; 1983 swq->slots = rq->dbinfo.max_slot; 1984 1985 if (qp->state == CMDQ_MODIFY_QP_NEW_STATE_ERR) { 1986 sch_handler = true; 1987 dev_dbg(&hwq->pdev->dev, 1988 "%s: Error QP. Scheduling for poll_cq\n", __func__); 1989 goto queue_err; 1990 } 1991 1992 idx = 0; 1993 base_hdr = bnxt_qplib_get_prod_qe(hwq, idx++); 1994 ext_hdr = bnxt_qplib_get_prod_qe(hwq, idx++); 1995 memset(base_hdr, 0, sizeof(struct sq_sge)); 1996 memset(ext_hdr, 0, sizeof(struct sq_sge)); 1997 wqe_sz = (sizeof(struct rq_wqe_hdr) + 1998 wqe->num_sge * sizeof(struct sq_sge)) >> 4; 1999 bnxt_qplib_put_sges(hwq, wqe->sg_list, wqe->num_sge, &idx); 2000 if (!wqe->num_sge) { 2001 struct sq_sge *sge; 2002 2003 sge = bnxt_qplib_get_prod_qe(hwq, idx++); 2004 sge->size = 0; 2005 wqe_sz++; 2006 } 2007 base_hdr->wqe_type = wqe->type; 2008 base_hdr->flags = wqe->flags; 2009 base_hdr->wqe_size = wqe_sz; 2010 base_hdr->wr_id[0] = cpu_to_le32(wqe_idx); 2011 queue_err: 2012 bnxt_qplib_swq_mod_start(rq, wqe_idx); 2013 bnxt_qplib_hwq_incr_prod(hwq, swq->slots); 2014 done: 2015 if (sch_handler) { 2016 nq_work = kzalloc(sizeof(*nq_work), GFP_ATOMIC); 2017 if (nq_work) { 2018 nq_work->cq = qp->rcq; 2019 nq_work->nq = qp->rcq->nq; 2020 INIT_WORK(&nq_work->work, bnxt_qpn_cqn_sched_task); 2021 queue_work(qp->rcq->nq->cqn_wq, &nq_work->work); 2022 } else { 2023 dev_err(&hwq->pdev->dev, 2024 "FP: Failed to allocate RQ nq_work!\n"); 2025 rc = -ENOMEM; 2026 } 2027 } 2028 2029 return rc; 2030 } 2031 2032 /* CQ */ 2033 int bnxt_qplib_create_cq(struct bnxt_qplib_res *res, struct bnxt_qplib_cq *cq) 2034 { 2035 struct bnxt_qplib_rcfw *rcfw = res->rcfw; 2036 struct bnxt_qplib_hwq_attr hwq_attr = {}; 2037 struct creq_create_cq_resp resp; 2038 struct bnxt_qplib_pbl *pbl; 2039 struct cmdq_create_cq req; 2040 u16 cmd_flags = 0; 2041 u32 pg_sz_lvl; 2042 int rc; 2043 2044 hwq_attr.res = res; 2045 hwq_attr.depth = cq->max_wqe; 2046 hwq_attr.stride = sizeof(struct cq_base); 2047 hwq_attr.type = HWQ_TYPE_QUEUE; 2048 hwq_attr.sginfo = &cq->sg_info; 2049 rc = bnxt_qplib_alloc_init_hwq(&cq->hwq, &hwq_attr); 2050 if (rc) 2051 goto exit; 2052 2053 RCFW_CMD_PREP(req, CREATE_CQ, cmd_flags); 2054 2055 if (!cq->dpi) { 2056 dev_err(&rcfw->pdev->dev, 2057 "FP: CREATE_CQ failed due to NULL DPI\n"); 2058 return -EINVAL; 2059 } 2060 req.dpi = cpu_to_le32(cq->dpi->dpi); 2061 req.cq_handle = cpu_to_le64(cq->cq_handle); 2062 req.cq_size = cpu_to_le32(cq->hwq.max_elements); 2063 pbl = &cq->hwq.pbl[PBL_LVL_0]; 2064 pg_sz_lvl = (bnxt_qplib_base_pg_size(&cq->hwq) << 2065 CMDQ_CREATE_CQ_PG_SIZE_SFT); 2066 pg_sz_lvl |= (cq->hwq.level & CMDQ_CREATE_CQ_LVL_MASK); 2067 req.pg_size_lvl = cpu_to_le32(pg_sz_lvl); 2068 req.pbl = cpu_to_le64(pbl->pg_map_arr[0]); 2069 req.cq_fco_cnq_id = cpu_to_le32( 2070 (cq->cnq_hw_ring_id & CMDQ_CREATE_CQ_CNQ_ID_MASK) << 2071 CMDQ_CREATE_CQ_CNQ_ID_SFT); 2072 2073 rc = bnxt_qplib_rcfw_send_message(rcfw, (void *)&req, 2074 (void *)&resp, NULL, 0); 2075 if (rc) 2076 goto fail; 2077 2078 cq->id = le32_to_cpu(resp.xid); 2079 cq->period = BNXT_QPLIB_QUEUE_START_PERIOD; 2080 init_waitqueue_head(&cq->waitq); 2081 INIT_LIST_HEAD(&cq->sqf_head); 2082 INIT_LIST_HEAD(&cq->rqf_head); 2083 spin_lock_init(&cq->compl_lock); 2084 spin_lock_init(&cq->flush_lock); 2085 2086 cq->dbinfo.hwq = &cq->hwq; 2087 cq->dbinfo.xid = cq->id; 2088 cq->dbinfo.db = cq->dpi->dbr; 2089 cq->dbinfo.priv_db = res->dpi_tbl.dbr_bar_reg_iomem; 2090 2091 bnxt_qplib_armen_db(&cq->dbinfo, DBC_DBC_TYPE_CQ_ARMENA); 2092 2093 return 0; 2094 2095 fail: 2096 bnxt_qplib_free_hwq(res, &cq->hwq); 2097 exit: 2098 return rc; 2099 } 2100 2101 int bnxt_qplib_destroy_cq(struct bnxt_qplib_res *res, struct bnxt_qplib_cq *cq) 2102 { 2103 struct bnxt_qplib_rcfw *rcfw = res->rcfw; 2104 struct cmdq_destroy_cq req; 2105 struct creq_destroy_cq_resp resp; 2106 u16 total_cnq_events; 2107 u16 cmd_flags = 0; 2108 int rc; 2109 2110 RCFW_CMD_PREP(req, DESTROY_CQ, cmd_flags); 2111 2112 req.cq_cid = cpu_to_le32(cq->id); 2113 rc = bnxt_qplib_rcfw_send_message(rcfw, (void *)&req, 2114 (void *)&resp, NULL, 0); 2115 if (rc) 2116 return rc; 2117 total_cnq_events = le16_to_cpu(resp.total_cnq_events); 2118 __wait_for_all_nqes(cq, total_cnq_events); 2119 bnxt_qplib_free_hwq(res, &cq->hwq); 2120 return 0; 2121 } 2122 2123 static int __flush_sq(struct bnxt_qplib_q *sq, struct bnxt_qplib_qp *qp, 2124 struct bnxt_qplib_cqe **pcqe, int *budget) 2125 { 2126 struct bnxt_qplib_cqe *cqe; 2127 u32 start, last; 2128 int rc = 0; 2129 2130 /* Now complete all outstanding SQEs with FLUSHED_ERR */ 2131 start = sq->swq_start; 2132 cqe = *pcqe; 2133 while (*budget) { 2134 last = sq->swq_last; 2135 if (start == last) 2136 break; 2137 /* Skip the FENCE WQE completions */ 2138 if (sq->swq[last].wr_id == BNXT_QPLIB_FENCE_WRID) { 2139 bnxt_qplib_cancel_phantom_processing(qp); 2140 goto skip_compl; 2141 } 2142 memset(cqe, 0, sizeof(*cqe)); 2143 cqe->status = CQ_REQ_STATUS_WORK_REQUEST_FLUSHED_ERR; 2144 cqe->opcode = CQ_BASE_CQE_TYPE_REQ; 2145 cqe->qp_handle = (u64)(unsigned long)qp; 2146 cqe->wr_id = sq->swq[last].wr_id; 2147 cqe->src_qp = qp->id; 2148 cqe->type = sq->swq[last].type; 2149 cqe++; 2150 (*budget)--; 2151 skip_compl: 2152 bnxt_qplib_hwq_incr_cons(&sq->hwq, sq->swq[last].slots); 2153 sq->swq_last = sq->swq[last].next_idx; 2154 } 2155 *pcqe = cqe; 2156 if (!(*budget) && sq->swq_last != start) 2157 /* Out of budget */ 2158 rc = -EAGAIN; 2159 2160 return rc; 2161 } 2162 2163 static int __flush_rq(struct bnxt_qplib_q *rq, struct bnxt_qplib_qp *qp, 2164 struct bnxt_qplib_cqe **pcqe, int *budget) 2165 { 2166 struct bnxt_qplib_cqe *cqe; 2167 u32 start, last; 2168 int opcode = 0; 2169 int rc = 0; 2170 2171 switch (qp->type) { 2172 case CMDQ_CREATE_QP1_TYPE_GSI: 2173 opcode = CQ_BASE_CQE_TYPE_RES_RAWETH_QP1; 2174 break; 2175 case CMDQ_CREATE_QP_TYPE_RC: 2176 opcode = CQ_BASE_CQE_TYPE_RES_RC; 2177 break; 2178 case CMDQ_CREATE_QP_TYPE_UD: 2179 case CMDQ_CREATE_QP_TYPE_GSI: 2180 opcode = CQ_BASE_CQE_TYPE_RES_UD; 2181 break; 2182 } 2183 2184 /* Flush the rest of the RQ */ 2185 start = rq->swq_start; 2186 cqe = *pcqe; 2187 while (*budget) { 2188 last = rq->swq_last; 2189 if (last == start) 2190 break; 2191 memset(cqe, 0, sizeof(*cqe)); 2192 cqe->status = 2193 CQ_RES_RC_STATUS_WORK_REQUEST_FLUSHED_ERR; 2194 cqe->opcode = opcode; 2195 cqe->qp_handle = (unsigned long)qp; 2196 cqe->wr_id = rq->swq[last].wr_id; 2197 cqe++; 2198 (*budget)--; 2199 bnxt_qplib_hwq_incr_cons(&rq->hwq, rq->swq[last].slots); 2200 rq->swq_last = rq->swq[last].next_idx; 2201 } 2202 *pcqe = cqe; 2203 if (!*budget && rq->swq_last != start) 2204 /* Out of budget */ 2205 rc = -EAGAIN; 2206 2207 return rc; 2208 } 2209 2210 void bnxt_qplib_mark_qp_error(void *qp_handle) 2211 { 2212 struct bnxt_qplib_qp *qp = qp_handle; 2213 2214 if (!qp) 2215 return; 2216 2217 /* Must block new posting of SQ and RQ */ 2218 qp->state = CMDQ_MODIFY_QP_NEW_STATE_ERR; 2219 bnxt_qplib_cancel_phantom_processing(qp); 2220 } 2221 2222 /* Note: SQE is valid from sw_sq_cons up to cqe_sq_cons (exclusive) 2223 * CQE is track from sw_cq_cons to max_element but valid only if VALID=1 2224 */ 2225 static int do_wa9060(struct bnxt_qplib_qp *qp, struct bnxt_qplib_cq *cq, 2226 u32 cq_cons, u32 swq_last, u32 cqe_sq_cons) 2227 { 2228 u32 peek_sw_cq_cons, peek_raw_cq_cons, peek_sq_cons_idx; 2229 struct bnxt_qplib_q *sq = &qp->sq; 2230 struct cq_req *peek_req_hwcqe; 2231 struct bnxt_qplib_qp *peek_qp; 2232 struct bnxt_qplib_q *peek_sq; 2233 struct bnxt_qplib_swq *swq; 2234 struct cq_base *peek_hwcqe; 2235 int i, rc = 0; 2236 2237 /* Normal mode */ 2238 /* Check for the psn_search marking before completing */ 2239 swq = &sq->swq[swq_last]; 2240 if (swq->psn_search && 2241 le32_to_cpu(swq->psn_search->flags_next_psn) & 0x80000000) { 2242 /* Unmark */ 2243 swq->psn_search->flags_next_psn = cpu_to_le32 2244 (le32_to_cpu(swq->psn_search->flags_next_psn) 2245 & ~0x80000000); 2246 dev_dbg(&cq->hwq.pdev->dev, 2247 "FP: Process Req cq_cons=0x%x qp=0x%x sq cons sw=0x%x cqe=0x%x marked!\n", 2248 cq_cons, qp->id, swq_last, cqe_sq_cons); 2249 sq->condition = true; 2250 sq->send_phantom = true; 2251 2252 /* TODO: Only ARM if the previous SQE is ARMALL */ 2253 bnxt_qplib_ring_db(&cq->dbinfo, DBC_DBC_TYPE_CQ_ARMALL); 2254 rc = -EAGAIN; 2255 goto out; 2256 } 2257 if (sq->condition) { 2258 /* Peek at the completions */ 2259 peek_raw_cq_cons = cq->hwq.cons; 2260 peek_sw_cq_cons = cq_cons; 2261 i = cq->hwq.max_elements; 2262 while (i--) { 2263 peek_sw_cq_cons = HWQ_CMP((peek_sw_cq_cons), &cq->hwq); 2264 peek_hwcqe = bnxt_qplib_get_qe(&cq->hwq, 2265 peek_sw_cq_cons, NULL); 2266 /* If the next hwcqe is VALID */ 2267 if (CQE_CMP_VALID(peek_hwcqe, peek_raw_cq_cons, 2268 cq->hwq.max_elements)) { 2269 /* 2270 * The valid test of the entry must be done first before 2271 * reading any further. 2272 */ 2273 dma_rmb(); 2274 /* If the next hwcqe is a REQ */ 2275 if ((peek_hwcqe->cqe_type_toggle & 2276 CQ_BASE_CQE_TYPE_MASK) == 2277 CQ_BASE_CQE_TYPE_REQ) { 2278 peek_req_hwcqe = (struct cq_req *) 2279 peek_hwcqe; 2280 peek_qp = (struct bnxt_qplib_qp *) 2281 ((unsigned long) 2282 le64_to_cpu 2283 (peek_req_hwcqe->qp_handle)); 2284 peek_sq = &peek_qp->sq; 2285 peek_sq_cons_idx = 2286 ((le16_to_cpu( 2287 peek_req_hwcqe->sq_cons_idx) 2288 - 1) % sq->max_wqe); 2289 /* If the hwcqe's sq's wr_id matches */ 2290 if (peek_sq == sq && 2291 sq->swq[peek_sq_cons_idx].wr_id == 2292 BNXT_QPLIB_FENCE_WRID) { 2293 /* 2294 * Unbreak only if the phantom 2295 * comes back 2296 */ 2297 dev_dbg(&cq->hwq.pdev->dev, 2298 "FP: Got Phantom CQE\n"); 2299 sq->condition = false; 2300 sq->single = true; 2301 rc = 0; 2302 goto out; 2303 } 2304 } 2305 /* Valid but not the phantom, so keep looping */ 2306 } else { 2307 /* Not valid yet, just exit and wait */ 2308 rc = -EINVAL; 2309 goto out; 2310 } 2311 peek_sw_cq_cons++; 2312 peek_raw_cq_cons++; 2313 } 2314 dev_err(&cq->hwq.pdev->dev, 2315 "Should not have come here! cq_cons=0x%x qp=0x%x sq cons sw=0x%x hw=0x%x\n", 2316 cq_cons, qp->id, swq_last, cqe_sq_cons); 2317 rc = -EINVAL; 2318 } 2319 out: 2320 return rc; 2321 } 2322 2323 static int bnxt_qplib_cq_process_req(struct bnxt_qplib_cq *cq, 2324 struct cq_req *hwcqe, 2325 struct bnxt_qplib_cqe **pcqe, int *budget, 2326 u32 cq_cons, struct bnxt_qplib_qp **lib_qp) 2327 { 2328 struct bnxt_qplib_swq *swq; 2329 struct bnxt_qplib_cqe *cqe; 2330 struct bnxt_qplib_qp *qp; 2331 struct bnxt_qplib_q *sq; 2332 u32 cqe_sq_cons; 2333 int rc = 0; 2334 2335 qp = (struct bnxt_qplib_qp *)((unsigned long) 2336 le64_to_cpu(hwcqe->qp_handle)); 2337 if (!qp) { 2338 dev_err(&cq->hwq.pdev->dev, 2339 "FP: Process Req qp is NULL\n"); 2340 return -EINVAL; 2341 } 2342 sq = &qp->sq; 2343 2344 cqe_sq_cons = le16_to_cpu(hwcqe->sq_cons_idx) % sq->max_wqe; 2345 if (qp->sq.flushed) { 2346 dev_dbg(&cq->hwq.pdev->dev, 2347 "%s: QP in Flush QP = %p\n", __func__, qp); 2348 goto done; 2349 } 2350 /* Require to walk the sq's swq to fabricate CQEs for all previously 2351 * signaled SWQEs due to CQE aggregation from the current sq cons 2352 * to the cqe_sq_cons 2353 */ 2354 cqe = *pcqe; 2355 while (*budget) { 2356 if (sq->swq_last == cqe_sq_cons) 2357 /* Done */ 2358 break; 2359 2360 swq = &sq->swq[sq->swq_last]; 2361 memset(cqe, 0, sizeof(*cqe)); 2362 cqe->opcode = CQ_BASE_CQE_TYPE_REQ; 2363 cqe->qp_handle = (u64)(unsigned long)qp; 2364 cqe->src_qp = qp->id; 2365 cqe->wr_id = swq->wr_id; 2366 if (cqe->wr_id == BNXT_QPLIB_FENCE_WRID) 2367 goto skip; 2368 cqe->type = swq->type; 2369 2370 /* For the last CQE, check for status. For errors, regardless 2371 * of the request being signaled or not, it must complete with 2372 * the hwcqe error status 2373 */ 2374 if (swq->next_idx == cqe_sq_cons && 2375 hwcqe->status != CQ_REQ_STATUS_OK) { 2376 cqe->status = hwcqe->status; 2377 dev_err(&cq->hwq.pdev->dev, 2378 "FP: CQ Processed Req wr_id[%d] = 0x%llx with status 0x%x\n", 2379 sq->swq_last, cqe->wr_id, cqe->status); 2380 cqe++; 2381 (*budget)--; 2382 bnxt_qplib_mark_qp_error(qp); 2383 /* Add qp to flush list of the CQ */ 2384 bnxt_qplib_add_flush_qp(qp); 2385 } else { 2386 /* Before we complete, do WA 9060 */ 2387 if (do_wa9060(qp, cq, cq_cons, sq->swq_last, 2388 cqe_sq_cons)) { 2389 *lib_qp = qp; 2390 goto out; 2391 } 2392 if (swq->flags & SQ_SEND_FLAGS_SIGNAL_COMP) { 2393 cqe->status = CQ_REQ_STATUS_OK; 2394 cqe++; 2395 (*budget)--; 2396 } 2397 } 2398 skip: 2399 bnxt_qplib_hwq_incr_cons(&sq->hwq, swq->slots); 2400 sq->swq_last = swq->next_idx; 2401 if (sq->single) 2402 break; 2403 } 2404 out: 2405 *pcqe = cqe; 2406 if (sq->swq_last != cqe_sq_cons) { 2407 /* Out of budget */ 2408 rc = -EAGAIN; 2409 goto done; 2410 } 2411 /* 2412 * Back to normal completion mode only after it has completed all of 2413 * the WC for this CQE 2414 */ 2415 sq->single = false; 2416 done: 2417 return rc; 2418 } 2419 2420 static void bnxt_qplib_release_srqe(struct bnxt_qplib_srq *srq, u32 tag) 2421 { 2422 spin_lock(&srq->hwq.lock); 2423 srq->swq[srq->last_idx].next_idx = (int)tag; 2424 srq->last_idx = (int)tag; 2425 srq->swq[srq->last_idx].next_idx = -1; 2426 srq->hwq.cons++; /* Support for SRQE counter */ 2427 spin_unlock(&srq->hwq.lock); 2428 } 2429 2430 static int bnxt_qplib_cq_process_res_rc(struct bnxt_qplib_cq *cq, 2431 struct cq_res_rc *hwcqe, 2432 struct bnxt_qplib_cqe **pcqe, 2433 int *budget) 2434 { 2435 struct bnxt_qplib_srq *srq; 2436 struct bnxt_qplib_cqe *cqe; 2437 struct bnxt_qplib_qp *qp; 2438 struct bnxt_qplib_q *rq; 2439 u32 wr_id_idx; 2440 int rc = 0; 2441 2442 qp = (struct bnxt_qplib_qp *)((unsigned long) 2443 le64_to_cpu(hwcqe->qp_handle)); 2444 if (!qp) { 2445 dev_err(&cq->hwq.pdev->dev, "process_cq RC qp is NULL\n"); 2446 return -EINVAL; 2447 } 2448 if (qp->rq.flushed) { 2449 dev_dbg(&cq->hwq.pdev->dev, 2450 "%s: QP in Flush QP = %p\n", __func__, qp); 2451 goto done; 2452 } 2453 2454 cqe = *pcqe; 2455 cqe->opcode = hwcqe->cqe_type_toggle & CQ_BASE_CQE_TYPE_MASK; 2456 cqe->length = le32_to_cpu(hwcqe->length); 2457 cqe->invrkey = le32_to_cpu(hwcqe->imm_data_or_inv_r_key); 2458 cqe->mr_handle = le64_to_cpu(hwcqe->mr_handle); 2459 cqe->flags = le16_to_cpu(hwcqe->flags); 2460 cqe->status = hwcqe->status; 2461 cqe->qp_handle = (u64)(unsigned long)qp; 2462 2463 wr_id_idx = le32_to_cpu(hwcqe->srq_or_rq_wr_id) & 2464 CQ_RES_RC_SRQ_OR_RQ_WR_ID_MASK; 2465 if (cqe->flags & CQ_RES_RC_FLAGS_SRQ_SRQ) { 2466 srq = qp->srq; 2467 if (!srq) 2468 return -EINVAL; 2469 if (wr_id_idx >= srq->hwq.max_elements) { 2470 dev_err(&cq->hwq.pdev->dev, 2471 "FP: CQ Process RC wr_id idx 0x%x exceeded SRQ max 0x%x\n", 2472 wr_id_idx, srq->hwq.max_elements); 2473 return -EINVAL; 2474 } 2475 cqe->wr_id = srq->swq[wr_id_idx].wr_id; 2476 bnxt_qplib_release_srqe(srq, wr_id_idx); 2477 cqe++; 2478 (*budget)--; 2479 *pcqe = cqe; 2480 } else { 2481 struct bnxt_qplib_swq *swq; 2482 2483 rq = &qp->rq; 2484 if (wr_id_idx > (rq->max_wqe - 1)) { 2485 dev_err(&cq->hwq.pdev->dev, 2486 "FP: CQ Process RC wr_id idx 0x%x exceeded RQ max 0x%x\n", 2487 wr_id_idx, rq->max_wqe); 2488 return -EINVAL; 2489 } 2490 if (wr_id_idx != rq->swq_last) 2491 return -EINVAL; 2492 swq = &rq->swq[rq->swq_last]; 2493 cqe->wr_id = swq->wr_id; 2494 cqe++; 2495 (*budget)--; 2496 bnxt_qplib_hwq_incr_cons(&rq->hwq, swq->slots); 2497 rq->swq_last = swq->next_idx; 2498 *pcqe = cqe; 2499 2500 if (hwcqe->status != CQ_RES_RC_STATUS_OK) { 2501 qp->state = CMDQ_MODIFY_QP_NEW_STATE_ERR; 2502 /* Add qp to flush list of the CQ */ 2503 bnxt_qplib_add_flush_qp(qp); 2504 } 2505 } 2506 2507 done: 2508 return rc; 2509 } 2510 2511 static int bnxt_qplib_cq_process_res_ud(struct bnxt_qplib_cq *cq, 2512 struct cq_res_ud *hwcqe, 2513 struct bnxt_qplib_cqe **pcqe, 2514 int *budget) 2515 { 2516 struct bnxt_qplib_srq *srq; 2517 struct bnxt_qplib_cqe *cqe; 2518 struct bnxt_qplib_qp *qp; 2519 struct bnxt_qplib_q *rq; 2520 u32 wr_id_idx; 2521 int rc = 0; 2522 2523 qp = (struct bnxt_qplib_qp *)((unsigned long) 2524 le64_to_cpu(hwcqe->qp_handle)); 2525 if (!qp) { 2526 dev_err(&cq->hwq.pdev->dev, "process_cq UD qp is NULL\n"); 2527 return -EINVAL; 2528 } 2529 if (qp->rq.flushed) { 2530 dev_dbg(&cq->hwq.pdev->dev, 2531 "%s: QP in Flush QP = %p\n", __func__, qp); 2532 goto done; 2533 } 2534 cqe = *pcqe; 2535 cqe->opcode = hwcqe->cqe_type_toggle & CQ_BASE_CQE_TYPE_MASK; 2536 cqe->length = le16_to_cpu(hwcqe->length) & CQ_RES_UD_LENGTH_MASK; 2537 cqe->cfa_meta = le16_to_cpu(hwcqe->cfa_metadata); 2538 cqe->invrkey = le32_to_cpu(hwcqe->imm_data); 2539 cqe->flags = le16_to_cpu(hwcqe->flags); 2540 cqe->status = hwcqe->status; 2541 cqe->qp_handle = (u64)(unsigned long)qp; 2542 /*FIXME: Endianness fix needed for smace */ 2543 memcpy(cqe->smac, hwcqe->src_mac, ETH_ALEN); 2544 wr_id_idx = le32_to_cpu(hwcqe->src_qp_high_srq_or_rq_wr_id) 2545 & CQ_RES_UD_SRQ_OR_RQ_WR_ID_MASK; 2546 cqe->src_qp = le16_to_cpu(hwcqe->src_qp_low) | 2547 ((le32_to_cpu( 2548 hwcqe->src_qp_high_srq_or_rq_wr_id) & 2549 CQ_RES_UD_SRC_QP_HIGH_MASK) >> 8); 2550 2551 if (cqe->flags & CQ_RES_RC_FLAGS_SRQ_SRQ) { 2552 srq = qp->srq; 2553 if (!srq) 2554 return -EINVAL; 2555 2556 if (wr_id_idx >= srq->hwq.max_elements) { 2557 dev_err(&cq->hwq.pdev->dev, 2558 "FP: CQ Process UD wr_id idx 0x%x exceeded SRQ max 0x%x\n", 2559 wr_id_idx, srq->hwq.max_elements); 2560 return -EINVAL; 2561 } 2562 cqe->wr_id = srq->swq[wr_id_idx].wr_id; 2563 bnxt_qplib_release_srqe(srq, wr_id_idx); 2564 cqe++; 2565 (*budget)--; 2566 *pcqe = cqe; 2567 } else { 2568 struct bnxt_qplib_swq *swq; 2569 2570 rq = &qp->rq; 2571 if (wr_id_idx > (rq->max_wqe - 1)) { 2572 dev_err(&cq->hwq.pdev->dev, 2573 "FP: CQ Process UD wr_id idx 0x%x exceeded RQ max 0x%x\n", 2574 wr_id_idx, rq->max_wqe); 2575 return -EINVAL; 2576 } 2577 2578 if (rq->swq_last != wr_id_idx) 2579 return -EINVAL; 2580 swq = &rq->swq[rq->swq_last]; 2581 cqe->wr_id = swq->wr_id; 2582 cqe++; 2583 (*budget)--; 2584 bnxt_qplib_hwq_incr_cons(&rq->hwq, swq->slots); 2585 rq->swq_last = swq->next_idx; 2586 *pcqe = cqe; 2587 2588 if (hwcqe->status != CQ_RES_RC_STATUS_OK) { 2589 qp->state = CMDQ_MODIFY_QP_NEW_STATE_ERR; 2590 /* Add qp to flush list of the CQ */ 2591 bnxt_qplib_add_flush_qp(qp); 2592 } 2593 } 2594 done: 2595 return rc; 2596 } 2597 2598 bool bnxt_qplib_is_cq_empty(struct bnxt_qplib_cq *cq) 2599 { 2600 struct cq_base *hw_cqe; 2601 u32 sw_cons, raw_cons; 2602 bool rc = true; 2603 2604 raw_cons = cq->hwq.cons; 2605 sw_cons = HWQ_CMP(raw_cons, &cq->hwq); 2606 hw_cqe = bnxt_qplib_get_qe(&cq->hwq, sw_cons, NULL); 2607 /* Check for Valid bit. If the CQE is valid, return false */ 2608 rc = !CQE_CMP_VALID(hw_cqe, raw_cons, cq->hwq.max_elements); 2609 return rc; 2610 } 2611 2612 static int bnxt_qplib_cq_process_res_raweth_qp1(struct bnxt_qplib_cq *cq, 2613 struct cq_res_raweth_qp1 *hwcqe, 2614 struct bnxt_qplib_cqe **pcqe, 2615 int *budget) 2616 { 2617 struct bnxt_qplib_qp *qp; 2618 struct bnxt_qplib_q *rq; 2619 struct bnxt_qplib_srq *srq; 2620 struct bnxt_qplib_cqe *cqe; 2621 u32 wr_id_idx; 2622 int rc = 0; 2623 2624 qp = (struct bnxt_qplib_qp *)((unsigned long) 2625 le64_to_cpu(hwcqe->qp_handle)); 2626 if (!qp) { 2627 dev_err(&cq->hwq.pdev->dev, "process_cq Raw/QP1 qp is NULL\n"); 2628 return -EINVAL; 2629 } 2630 if (qp->rq.flushed) { 2631 dev_dbg(&cq->hwq.pdev->dev, 2632 "%s: QP in Flush QP = %p\n", __func__, qp); 2633 goto done; 2634 } 2635 cqe = *pcqe; 2636 cqe->opcode = hwcqe->cqe_type_toggle & CQ_BASE_CQE_TYPE_MASK; 2637 cqe->flags = le16_to_cpu(hwcqe->flags); 2638 cqe->qp_handle = (u64)(unsigned long)qp; 2639 2640 wr_id_idx = 2641 le32_to_cpu(hwcqe->raweth_qp1_payload_offset_srq_or_rq_wr_id) 2642 & CQ_RES_RAWETH_QP1_SRQ_OR_RQ_WR_ID_MASK; 2643 cqe->src_qp = qp->id; 2644 if (qp->id == 1 && !cqe->length) { 2645 /* Add workaround for the length misdetection */ 2646 cqe->length = 296; 2647 } else { 2648 cqe->length = le16_to_cpu(hwcqe->length); 2649 } 2650 cqe->pkey_index = qp->pkey_index; 2651 memcpy(cqe->smac, qp->smac, 6); 2652 2653 cqe->raweth_qp1_flags = le16_to_cpu(hwcqe->raweth_qp1_flags); 2654 cqe->raweth_qp1_flags2 = le32_to_cpu(hwcqe->raweth_qp1_flags2); 2655 cqe->raweth_qp1_metadata = le32_to_cpu(hwcqe->raweth_qp1_metadata); 2656 2657 if (cqe->flags & CQ_RES_RAWETH_QP1_FLAGS_SRQ_SRQ) { 2658 srq = qp->srq; 2659 if (!srq) { 2660 dev_err(&cq->hwq.pdev->dev, 2661 "FP: SRQ used but not defined??\n"); 2662 return -EINVAL; 2663 } 2664 if (wr_id_idx >= srq->hwq.max_elements) { 2665 dev_err(&cq->hwq.pdev->dev, 2666 "FP: CQ Process Raw/QP1 wr_id idx 0x%x exceeded SRQ max 0x%x\n", 2667 wr_id_idx, srq->hwq.max_elements); 2668 return -EINVAL; 2669 } 2670 cqe->wr_id = srq->swq[wr_id_idx].wr_id; 2671 bnxt_qplib_release_srqe(srq, wr_id_idx); 2672 cqe++; 2673 (*budget)--; 2674 *pcqe = cqe; 2675 } else { 2676 struct bnxt_qplib_swq *swq; 2677 2678 rq = &qp->rq; 2679 if (wr_id_idx > (rq->max_wqe - 1)) { 2680 dev_err(&cq->hwq.pdev->dev, 2681 "FP: CQ Process Raw/QP1 RQ wr_id idx 0x%x exceeded RQ max 0x%x\n", 2682 wr_id_idx, rq->max_wqe); 2683 return -EINVAL; 2684 } 2685 if (rq->swq_last != wr_id_idx) 2686 return -EINVAL; 2687 swq = &rq->swq[rq->swq_last]; 2688 cqe->wr_id = swq->wr_id; 2689 cqe++; 2690 (*budget)--; 2691 bnxt_qplib_hwq_incr_cons(&rq->hwq, swq->slots); 2692 rq->swq_last = swq->next_idx; 2693 *pcqe = cqe; 2694 2695 if (hwcqe->status != CQ_RES_RC_STATUS_OK) { 2696 qp->state = CMDQ_MODIFY_QP_NEW_STATE_ERR; 2697 /* Add qp to flush list of the CQ */ 2698 bnxt_qplib_add_flush_qp(qp); 2699 } 2700 } 2701 2702 done: 2703 return rc; 2704 } 2705 2706 static int bnxt_qplib_cq_process_terminal(struct bnxt_qplib_cq *cq, 2707 struct cq_terminal *hwcqe, 2708 struct bnxt_qplib_cqe **pcqe, 2709 int *budget) 2710 { 2711 struct bnxt_qplib_qp *qp; 2712 struct bnxt_qplib_q *sq, *rq; 2713 struct bnxt_qplib_cqe *cqe; 2714 u32 swq_last = 0, cqe_cons; 2715 int rc = 0; 2716 2717 /* Check the Status */ 2718 if (hwcqe->status != CQ_TERMINAL_STATUS_OK) 2719 dev_warn(&cq->hwq.pdev->dev, 2720 "FP: CQ Process Terminal Error status = 0x%x\n", 2721 hwcqe->status); 2722 2723 qp = (struct bnxt_qplib_qp *)((unsigned long) 2724 le64_to_cpu(hwcqe->qp_handle)); 2725 if (!qp) { 2726 dev_err(&cq->hwq.pdev->dev, 2727 "FP: CQ Process terminal qp is NULL\n"); 2728 return -EINVAL; 2729 } 2730 2731 /* Must block new posting of SQ and RQ */ 2732 qp->state = CMDQ_MODIFY_QP_NEW_STATE_ERR; 2733 2734 sq = &qp->sq; 2735 rq = &qp->rq; 2736 2737 cqe_cons = le16_to_cpu(hwcqe->sq_cons_idx); 2738 if (cqe_cons == 0xFFFF) 2739 goto do_rq; 2740 cqe_cons %= sq->max_wqe; 2741 2742 if (qp->sq.flushed) { 2743 dev_dbg(&cq->hwq.pdev->dev, 2744 "%s: QP in Flush QP = %p\n", __func__, qp); 2745 goto sq_done; 2746 } 2747 2748 /* Terminal CQE can also include aggregated successful CQEs prior. 2749 * So we must complete all CQEs from the current sq's cons to the 2750 * cq_cons with status OK 2751 */ 2752 cqe = *pcqe; 2753 while (*budget) { 2754 swq_last = sq->swq_last; 2755 if (swq_last == cqe_cons) 2756 break; 2757 if (sq->swq[swq_last].flags & SQ_SEND_FLAGS_SIGNAL_COMP) { 2758 memset(cqe, 0, sizeof(*cqe)); 2759 cqe->status = CQ_REQ_STATUS_OK; 2760 cqe->opcode = CQ_BASE_CQE_TYPE_REQ; 2761 cqe->qp_handle = (u64)(unsigned long)qp; 2762 cqe->src_qp = qp->id; 2763 cqe->wr_id = sq->swq[swq_last].wr_id; 2764 cqe->type = sq->swq[swq_last].type; 2765 cqe++; 2766 (*budget)--; 2767 } 2768 bnxt_qplib_hwq_incr_cons(&sq->hwq, sq->swq[swq_last].slots); 2769 sq->swq_last = sq->swq[swq_last].next_idx; 2770 } 2771 *pcqe = cqe; 2772 if (!(*budget) && swq_last != cqe_cons) { 2773 /* Out of budget */ 2774 rc = -EAGAIN; 2775 goto sq_done; 2776 } 2777 sq_done: 2778 if (rc) 2779 return rc; 2780 do_rq: 2781 cqe_cons = le16_to_cpu(hwcqe->rq_cons_idx); 2782 if (cqe_cons == 0xFFFF) { 2783 goto done; 2784 } else if (cqe_cons > rq->max_wqe - 1) { 2785 dev_err(&cq->hwq.pdev->dev, 2786 "FP: CQ Processed terminal reported rq_cons_idx 0x%x exceeds max 0x%x\n", 2787 cqe_cons, rq->max_wqe); 2788 goto done; 2789 } 2790 2791 if (qp->rq.flushed) { 2792 dev_dbg(&cq->hwq.pdev->dev, 2793 "%s: QP in Flush QP = %p\n", __func__, qp); 2794 rc = 0; 2795 goto done; 2796 } 2797 2798 /* Terminal CQE requires all posted RQEs to complete with FLUSHED_ERR 2799 * from the current rq->cons to the rq->prod regardless what the 2800 * rq->cons the terminal CQE indicates 2801 */ 2802 2803 /* Add qp to flush list of the CQ */ 2804 bnxt_qplib_add_flush_qp(qp); 2805 done: 2806 return rc; 2807 } 2808 2809 static int bnxt_qplib_cq_process_cutoff(struct bnxt_qplib_cq *cq, 2810 struct cq_cutoff *hwcqe) 2811 { 2812 /* Check the Status */ 2813 if (hwcqe->status != CQ_CUTOFF_STATUS_OK) { 2814 dev_err(&cq->hwq.pdev->dev, 2815 "FP: CQ Process Cutoff Error status = 0x%x\n", 2816 hwcqe->status); 2817 return -EINVAL; 2818 } 2819 clear_bit(CQ_FLAGS_RESIZE_IN_PROG, &cq->flags); 2820 wake_up_interruptible(&cq->waitq); 2821 2822 return 0; 2823 } 2824 2825 int bnxt_qplib_process_flush_list(struct bnxt_qplib_cq *cq, 2826 struct bnxt_qplib_cqe *cqe, 2827 int num_cqes) 2828 { 2829 struct bnxt_qplib_qp *qp = NULL; 2830 u32 budget = num_cqes; 2831 unsigned long flags; 2832 2833 spin_lock_irqsave(&cq->flush_lock, flags); 2834 list_for_each_entry(qp, &cq->sqf_head, sq_flush) { 2835 dev_dbg(&cq->hwq.pdev->dev, "FP: Flushing SQ QP= %p\n", qp); 2836 __flush_sq(&qp->sq, qp, &cqe, &budget); 2837 } 2838 2839 list_for_each_entry(qp, &cq->rqf_head, rq_flush) { 2840 dev_dbg(&cq->hwq.pdev->dev, "FP: Flushing RQ QP= %p\n", qp); 2841 __flush_rq(&qp->rq, qp, &cqe, &budget); 2842 } 2843 spin_unlock_irqrestore(&cq->flush_lock, flags); 2844 2845 return num_cqes - budget; 2846 } 2847 2848 int bnxt_qplib_poll_cq(struct bnxt_qplib_cq *cq, struct bnxt_qplib_cqe *cqe, 2849 int num_cqes, struct bnxt_qplib_qp **lib_qp) 2850 { 2851 struct cq_base *hw_cqe; 2852 u32 sw_cons, raw_cons; 2853 int budget, rc = 0; 2854 2855 raw_cons = cq->hwq.cons; 2856 budget = num_cqes; 2857 2858 while (budget) { 2859 sw_cons = HWQ_CMP(raw_cons, &cq->hwq); 2860 hw_cqe = bnxt_qplib_get_qe(&cq->hwq, sw_cons, NULL); 2861 2862 /* Check for Valid bit */ 2863 if (!CQE_CMP_VALID(hw_cqe, raw_cons, cq->hwq.max_elements)) 2864 break; 2865 2866 /* 2867 * The valid test of the entry must be done first before 2868 * reading any further. 2869 */ 2870 dma_rmb(); 2871 /* From the device's respective CQE format to qplib_wc*/ 2872 switch (hw_cqe->cqe_type_toggle & CQ_BASE_CQE_TYPE_MASK) { 2873 case CQ_BASE_CQE_TYPE_REQ: 2874 rc = bnxt_qplib_cq_process_req(cq, 2875 (struct cq_req *)hw_cqe, 2876 &cqe, &budget, 2877 sw_cons, lib_qp); 2878 break; 2879 case CQ_BASE_CQE_TYPE_RES_RC: 2880 rc = bnxt_qplib_cq_process_res_rc(cq, 2881 (struct cq_res_rc *) 2882 hw_cqe, &cqe, 2883 &budget); 2884 break; 2885 case CQ_BASE_CQE_TYPE_RES_UD: 2886 rc = bnxt_qplib_cq_process_res_ud 2887 (cq, (struct cq_res_ud *)hw_cqe, &cqe, 2888 &budget); 2889 break; 2890 case CQ_BASE_CQE_TYPE_RES_RAWETH_QP1: 2891 rc = bnxt_qplib_cq_process_res_raweth_qp1 2892 (cq, (struct cq_res_raweth_qp1 *) 2893 hw_cqe, &cqe, &budget); 2894 break; 2895 case CQ_BASE_CQE_TYPE_TERMINAL: 2896 rc = bnxt_qplib_cq_process_terminal 2897 (cq, (struct cq_terminal *)hw_cqe, 2898 &cqe, &budget); 2899 break; 2900 case CQ_BASE_CQE_TYPE_CUT_OFF: 2901 bnxt_qplib_cq_process_cutoff 2902 (cq, (struct cq_cutoff *)hw_cqe); 2903 /* Done processing this CQ */ 2904 goto exit; 2905 default: 2906 dev_err(&cq->hwq.pdev->dev, 2907 "process_cq unknown type 0x%lx\n", 2908 hw_cqe->cqe_type_toggle & 2909 CQ_BASE_CQE_TYPE_MASK); 2910 rc = -EINVAL; 2911 break; 2912 } 2913 if (rc < 0) { 2914 if (rc == -EAGAIN) 2915 break; 2916 /* Error while processing the CQE, just skip to the 2917 * next one 2918 */ 2919 dev_err(&cq->hwq.pdev->dev, 2920 "process_cqe error rc = 0x%x\n", rc); 2921 } 2922 raw_cons++; 2923 } 2924 if (cq->hwq.cons != raw_cons) { 2925 cq->hwq.cons = raw_cons; 2926 bnxt_qplib_ring_db(&cq->dbinfo, DBC_DBC_TYPE_CQ); 2927 } 2928 exit: 2929 return num_cqes - budget; 2930 } 2931 2932 void bnxt_qplib_req_notify_cq(struct bnxt_qplib_cq *cq, u32 arm_type) 2933 { 2934 if (arm_type) 2935 bnxt_qplib_ring_db(&cq->dbinfo, arm_type); 2936 /* Using cq->arm_state variable to track whether to issue cq handler */ 2937 atomic_set(&cq->arm_state, 1); 2938 } 2939 2940 void bnxt_qplib_flush_cqn_wq(struct bnxt_qplib_qp *qp) 2941 { 2942 flush_workqueue(qp->scq->nq->cqn_wq); 2943 if (qp->scq != qp->rcq) 2944 flush_workqueue(qp->rcq->nq->cqn_wq); 2945 } 2946