1 /* 2 * Broadcom NetXtreme-E RoCE driver. 3 * 4 * Copyright (c) 2016 - 2017, Broadcom. All rights reserved. The term 5 * Broadcom refers to Broadcom Limited and/or its subsidiaries. 6 * 7 * This software is available to you under a choice of one of two 8 * licenses. You may choose to be licensed under the terms of the GNU 9 * General Public License (GPL) Version 2, available from the file 10 * COPYING in the main directory of this source tree, or the 11 * BSD license below: 12 * 13 * Redistribution and use in source and binary forms, with or without 14 * modification, are permitted provided that the following conditions 15 * are met: 16 * 17 * 1. Redistributions of source code must retain the above copyright 18 * notice, this list of conditions and the following disclaimer. 19 * 2. Redistributions in binary form must reproduce the above copyright 20 * notice, this list of conditions and the following disclaimer in 21 * the documentation and/or other materials provided with the 22 * distribution. 23 * 24 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' 25 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, 26 * THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR 27 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS 28 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 29 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 30 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR 31 * BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, 32 * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE 33 * OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN 34 * IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 35 * 36 * Description: Main component of the bnxt_re driver 37 */ 38 39 #include <linux/module.h> 40 #include <linux/netdevice.h> 41 #include <linux/ethtool.h> 42 #include <linux/mutex.h> 43 #include <linux/list.h> 44 #include <linux/rculist.h> 45 #include <linux/spinlock.h> 46 #include <linux/pci.h> 47 #include <net/dcbnl.h> 48 #include <net/ipv6.h> 49 #include <net/addrconf.h> 50 #include <linux/if_ether.h> 51 #include <linux/auxiliary_bus.h> 52 53 #include <rdma/ib_verbs.h> 54 #include <rdma/ib_user_verbs.h> 55 #include <rdma/ib_umem.h> 56 #include <rdma/ib_addr.h> 57 58 #include "bnxt_ulp.h" 59 #include "roce_hsi.h" 60 #include "qplib_res.h" 61 #include "qplib_sp.h" 62 #include "qplib_fp.h" 63 #include "qplib_rcfw.h" 64 #include "bnxt_re.h" 65 #include "ib_verbs.h" 66 #include <rdma/bnxt_re-abi.h> 67 #include "bnxt.h" 68 #include "hw_counters.h" 69 70 static char version[] = 71 BNXT_RE_DESC "\n"; 72 73 MODULE_AUTHOR("Eddie Wai <eddie.wai@broadcom.com>"); 74 MODULE_DESCRIPTION(BNXT_RE_DESC " Driver"); 75 MODULE_LICENSE("Dual BSD/GPL"); 76 77 /* globals */ 78 static DEFINE_MUTEX(bnxt_re_mutex); 79 80 static void bnxt_re_stop_irq(void *handle); 81 static void bnxt_re_dev_stop(struct bnxt_re_dev *rdev); 82 static int bnxt_re_netdev_event(struct notifier_block *notifier, 83 unsigned long event, void *ptr); 84 static struct bnxt_re_dev *bnxt_re_from_netdev(struct net_device *netdev); 85 static void bnxt_re_dev_uninit(struct bnxt_re_dev *rdev); 86 static int bnxt_re_hwrm_qcaps(struct bnxt_re_dev *rdev); 87 88 static int bnxt_re_hwrm_qcfg(struct bnxt_re_dev *rdev, u32 *db_len, 89 u32 *offset); 90 static void bnxt_re_set_db_offset(struct bnxt_re_dev *rdev) 91 { 92 struct bnxt_qplib_chip_ctx *cctx; 93 struct bnxt_en_dev *en_dev; 94 struct bnxt_qplib_res *res; 95 u32 l2db_len = 0; 96 u32 offset = 0; 97 u32 barlen; 98 int rc; 99 100 res = &rdev->qplib_res; 101 en_dev = rdev->en_dev; 102 cctx = rdev->chip_ctx; 103 104 /* Issue qcfg */ 105 rc = bnxt_re_hwrm_qcfg(rdev, &l2db_len, &offset); 106 if (rc) 107 dev_info(rdev_to_dev(rdev), 108 "Couldn't get DB bar size, Low latency framework is disabled\n"); 109 /* set register offsets for both UC and WC */ 110 res->dpi_tbl.ucreg.offset = res->is_vf ? BNXT_QPLIB_DBR_VF_DB_OFFSET : 111 BNXT_QPLIB_DBR_PF_DB_OFFSET; 112 res->dpi_tbl.wcreg.offset = res->dpi_tbl.ucreg.offset; 113 114 /* If WC mapping is disabled by L2 driver then en_dev->l2_db_size 115 * is equal to the DB-Bar actual size. This indicates that L2 116 * is mapping entire bar as UC-. RoCE driver can't enable WC mapping 117 * in such cases and DB-push will be disabled. 118 */ 119 barlen = pci_resource_len(res->pdev, RCFW_DBR_PCI_BAR_REGION); 120 if (cctx->modes.db_push && l2db_len && en_dev->l2_db_size != barlen) { 121 res->dpi_tbl.wcreg.offset = en_dev->l2_db_size; 122 dev_info(rdev_to_dev(rdev), "Low latency framework is enabled\n"); 123 } 124 } 125 126 static void bnxt_re_set_drv_mode(struct bnxt_re_dev *rdev, u8 mode) 127 { 128 struct bnxt_qplib_chip_ctx *cctx; 129 130 cctx = rdev->chip_ctx; 131 cctx->modes.wqe_mode = bnxt_qplib_is_chip_gen_p5(rdev->chip_ctx) ? 132 mode : BNXT_QPLIB_WQE_MODE_STATIC; 133 if (bnxt_re_hwrm_qcaps(rdev)) 134 dev_err(rdev_to_dev(rdev), 135 "Failed to query hwrm qcaps\n"); 136 } 137 138 static void bnxt_re_destroy_chip_ctx(struct bnxt_re_dev *rdev) 139 { 140 struct bnxt_qplib_chip_ctx *chip_ctx; 141 142 if (!rdev->chip_ctx) 143 return; 144 chip_ctx = rdev->chip_ctx; 145 rdev->chip_ctx = NULL; 146 rdev->rcfw.res = NULL; 147 rdev->qplib_res.cctx = NULL; 148 rdev->qplib_res.pdev = NULL; 149 rdev->qplib_res.netdev = NULL; 150 kfree(chip_ctx); 151 } 152 153 static int bnxt_re_setup_chip_ctx(struct bnxt_re_dev *rdev, u8 wqe_mode) 154 { 155 struct bnxt_qplib_chip_ctx *chip_ctx; 156 struct bnxt_en_dev *en_dev; 157 int rc; 158 159 en_dev = rdev->en_dev; 160 161 chip_ctx = kzalloc(sizeof(*chip_ctx), GFP_KERNEL); 162 if (!chip_ctx) 163 return -ENOMEM; 164 chip_ctx->chip_num = en_dev->chip_num; 165 chip_ctx->hw_stats_size = en_dev->hw_ring_stats_size; 166 167 rdev->chip_ctx = chip_ctx; 168 /* rest members to follow eventually */ 169 170 rdev->qplib_res.cctx = rdev->chip_ctx; 171 rdev->rcfw.res = &rdev->qplib_res; 172 rdev->qplib_res.dattr = &rdev->dev_attr; 173 rdev->qplib_res.is_vf = BNXT_EN_VF(en_dev); 174 175 bnxt_re_set_drv_mode(rdev, wqe_mode); 176 177 bnxt_re_set_db_offset(rdev); 178 rc = bnxt_qplib_map_db_bar(&rdev->qplib_res); 179 if (rc) 180 return rc; 181 182 if (bnxt_qplib_determine_atomics(en_dev->pdev)) 183 ibdev_info(&rdev->ibdev, 184 "platform doesn't support global atomics."); 185 return 0; 186 } 187 188 /* SR-IOV helper functions */ 189 190 static void bnxt_re_get_sriov_func_type(struct bnxt_re_dev *rdev) 191 { 192 if (BNXT_EN_VF(rdev->en_dev)) 193 rdev->is_virtfn = 1; 194 } 195 196 /* Set the maximum number of each resource that the driver actually wants 197 * to allocate. This may be up to the maximum number the firmware has 198 * reserved for the function. The driver may choose to allocate fewer 199 * resources than the firmware maximum. 200 */ 201 static void bnxt_re_limit_pf_res(struct bnxt_re_dev *rdev) 202 { 203 struct bnxt_qplib_dev_attr *attr; 204 struct bnxt_qplib_ctx *ctx; 205 int i; 206 207 attr = &rdev->dev_attr; 208 ctx = &rdev->qplib_ctx; 209 210 ctx->qpc_count = min_t(u32, BNXT_RE_MAX_QPC_COUNT, 211 attr->max_qp); 212 ctx->mrw_count = BNXT_RE_MAX_MRW_COUNT_256K; 213 /* Use max_mr from fw since max_mrw does not get set */ 214 ctx->mrw_count = min_t(u32, ctx->mrw_count, attr->max_mr); 215 ctx->srqc_count = min_t(u32, BNXT_RE_MAX_SRQC_COUNT, 216 attr->max_srq); 217 ctx->cq_count = min_t(u32, BNXT_RE_MAX_CQ_COUNT, attr->max_cq); 218 if (!bnxt_qplib_is_chip_gen_p5(rdev->chip_ctx)) 219 for (i = 0; i < MAX_TQM_ALLOC_REQ; i++) 220 rdev->qplib_ctx.tqm_ctx.qcount[i] = 221 rdev->dev_attr.tqm_alloc_reqs[i]; 222 } 223 224 static void bnxt_re_limit_vf_res(struct bnxt_qplib_ctx *qplib_ctx, u32 num_vf) 225 { 226 struct bnxt_qplib_vf_res *vf_res; 227 u32 mrws = 0; 228 u32 vf_pct; 229 u32 nvfs; 230 231 vf_res = &qplib_ctx->vf_res; 232 /* 233 * Reserve a set of resources for the PF. Divide the remaining 234 * resources among the VFs 235 */ 236 vf_pct = 100 - BNXT_RE_PCT_RSVD_FOR_PF; 237 nvfs = num_vf; 238 num_vf = 100 * num_vf; 239 vf_res->max_qp_per_vf = (qplib_ctx->qpc_count * vf_pct) / num_vf; 240 vf_res->max_srq_per_vf = (qplib_ctx->srqc_count * vf_pct) / num_vf; 241 vf_res->max_cq_per_vf = (qplib_ctx->cq_count * vf_pct) / num_vf; 242 /* 243 * The driver allows many more MRs than other resources. If the 244 * firmware does also, then reserve a fixed amount for the PF and 245 * divide the rest among VFs. VFs may use many MRs for NFS 246 * mounts, ISER, NVME applications, etc. If the firmware severely 247 * restricts the number of MRs, then let PF have half and divide 248 * the rest among VFs, as for the other resource types. 249 */ 250 if (qplib_ctx->mrw_count < BNXT_RE_MAX_MRW_COUNT_64K) { 251 mrws = qplib_ctx->mrw_count * vf_pct; 252 nvfs = num_vf; 253 } else { 254 mrws = qplib_ctx->mrw_count - BNXT_RE_RESVD_MR_FOR_PF; 255 } 256 vf_res->max_mrw_per_vf = (mrws / nvfs); 257 vf_res->max_gid_per_vf = BNXT_RE_MAX_GID_PER_VF; 258 } 259 260 static void bnxt_re_set_resource_limits(struct bnxt_re_dev *rdev) 261 { 262 u32 num_vfs; 263 264 memset(&rdev->qplib_ctx.vf_res, 0, sizeof(struct bnxt_qplib_vf_res)); 265 bnxt_re_limit_pf_res(rdev); 266 267 num_vfs = bnxt_qplib_is_chip_gen_p5(rdev->chip_ctx) ? 268 BNXT_RE_GEN_P5_MAX_VF : rdev->num_vfs; 269 if (num_vfs) 270 bnxt_re_limit_vf_res(&rdev->qplib_ctx, num_vfs); 271 } 272 273 static void bnxt_re_vf_res_config(struct bnxt_re_dev *rdev) 274 { 275 276 if (test_bit(BNXT_RE_FLAG_ERR_DEVICE_DETACHED, &rdev->flags)) 277 return; 278 rdev->num_vfs = pci_sriov_get_totalvfs(rdev->en_dev->pdev); 279 if (!bnxt_qplib_is_chip_gen_p5(rdev->chip_ctx)) { 280 bnxt_re_set_resource_limits(rdev); 281 bnxt_qplib_set_func_resources(&rdev->qplib_res, &rdev->rcfw, 282 &rdev->qplib_ctx); 283 } 284 } 285 286 static void bnxt_re_shutdown(struct auxiliary_device *adev) 287 { 288 struct bnxt_re_dev *rdev = auxiliary_get_drvdata(adev); 289 290 if (!rdev) 291 return; 292 ib_unregister_device(&rdev->ibdev); 293 bnxt_re_dev_uninit(rdev); 294 } 295 296 static void bnxt_re_stop_irq(void *handle) 297 { 298 struct bnxt_re_dev *rdev = (struct bnxt_re_dev *)handle; 299 struct bnxt_qplib_rcfw *rcfw = &rdev->rcfw; 300 struct bnxt_qplib_nq *nq; 301 int indx; 302 303 for (indx = BNXT_RE_NQ_IDX; indx < rdev->num_msix; indx++) { 304 nq = &rdev->nq[indx - 1]; 305 bnxt_qplib_nq_stop_irq(nq, false); 306 } 307 308 bnxt_qplib_rcfw_stop_irq(rcfw, false); 309 } 310 311 static void bnxt_re_start_irq(void *handle, struct bnxt_msix_entry *ent) 312 { 313 struct bnxt_re_dev *rdev = (struct bnxt_re_dev *)handle; 314 struct bnxt_msix_entry *msix_ent = rdev->en_dev->msix_entries; 315 struct bnxt_qplib_rcfw *rcfw = &rdev->rcfw; 316 struct bnxt_qplib_nq *nq; 317 int indx, rc; 318 319 if (!ent) { 320 /* Not setting the f/w timeout bit in rcfw. 321 * During the driver unload the first command 322 * to f/w will timeout and that will set the 323 * timeout bit. 324 */ 325 ibdev_err(&rdev->ibdev, "Failed to re-start IRQs\n"); 326 return; 327 } 328 329 /* Vectors may change after restart, so update with new vectors 330 * in device sctructure. 331 */ 332 for (indx = 0; indx < rdev->num_msix; indx++) 333 rdev->en_dev->msix_entries[indx].vector = ent[indx].vector; 334 335 rc = bnxt_qplib_rcfw_start_irq(rcfw, msix_ent[BNXT_RE_AEQ_IDX].vector, 336 false); 337 if (rc) { 338 ibdev_warn(&rdev->ibdev, "Failed to reinit CREQ\n"); 339 return; 340 } 341 for (indx = BNXT_RE_NQ_IDX ; indx < rdev->num_msix; indx++) { 342 nq = &rdev->nq[indx - 1]; 343 rc = bnxt_qplib_nq_start_irq(nq, indx - 1, 344 msix_ent[indx].vector, false); 345 if (rc) { 346 ibdev_warn(&rdev->ibdev, "Failed to reinit NQ index %d\n", 347 indx - 1); 348 return; 349 } 350 } 351 } 352 353 static struct bnxt_ulp_ops bnxt_re_ulp_ops = { 354 .ulp_irq_stop = bnxt_re_stop_irq, 355 .ulp_irq_restart = bnxt_re_start_irq 356 }; 357 358 /* RoCE -> Net driver */ 359 360 static int bnxt_re_register_netdev(struct bnxt_re_dev *rdev) 361 { 362 struct bnxt_en_dev *en_dev; 363 int rc = 0; 364 365 en_dev = rdev->en_dev; 366 367 rc = bnxt_register_dev(en_dev, &bnxt_re_ulp_ops, rdev); 368 if (!rc) 369 rdev->qplib_res.pdev = rdev->en_dev->pdev; 370 return rc; 371 } 372 373 static void bnxt_re_init_hwrm_hdr(struct input *hdr, u16 opcd) 374 { 375 hdr->req_type = cpu_to_le16(opcd); 376 hdr->cmpl_ring = cpu_to_le16(-1); 377 hdr->target_id = cpu_to_le16(-1); 378 } 379 380 static void bnxt_re_fill_fw_msg(struct bnxt_fw_msg *fw_msg, void *msg, 381 int msg_len, void *resp, int resp_max_len, 382 int timeout) 383 { 384 fw_msg->msg = msg; 385 fw_msg->msg_len = msg_len; 386 fw_msg->resp = resp; 387 fw_msg->resp_max_len = resp_max_len; 388 fw_msg->timeout = timeout; 389 } 390 391 /* Query device config using common hwrm */ 392 static int bnxt_re_hwrm_qcfg(struct bnxt_re_dev *rdev, u32 *db_len, 393 u32 *offset) 394 { 395 struct bnxt_en_dev *en_dev = rdev->en_dev; 396 struct hwrm_func_qcfg_output resp = {0}; 397 struct hwrm_func_qcfg_input req = {0}; 398 struct bnxt_fw_msg fw_msg; 399 int rc; 400 401 memset(&fw_msg, 0, sizeof(fw_msg)); 402 bnxt_re_init_hwrm_hdr((void *)&req, HWRM_FUNC_QCFG); 403 req.fid = cpu_to_le16(0xffff); 404 bnxt_re_fill_fw_msg(&fw_msg, (void *)&req, sizeof(req), (void *)&resp, 405 sizeof(resp), DFLT_HWRM_CMD_TIMEOUT); 406 rc = bnxt_send_msg(en_dev, &fw_msg); 407 if (!rc) { 408 *db_len = PAGE_ALIGN(le16_to_cpu(resp.l2_doorbell_bar_size_kb) * 1024); 409 *offset = PAGE_ALIGN(le16_to_cpu(resp.legacy_l2_db_size_kb) * 1024); 410 } 411 return rc; 412 } 413 414 /* Query function capabilities using common hwrm */ 415 int bnxt_re_hwrm_qcaps(struct bnxt_re_dev *rdev) 416 { 417 struct bnxt_en_dev *en_dev = rdev->en_dev; 418 struct hwrm_func_qcaps_output resp = {}; 419 struct hwrm_func_qcaps_input req = {}; 420 struct bnxt_qplib_chip_ctx *cctx; 421 struct bnxt_fw_msg fw_msg = {}; 422 int rc; 423 424 cctx = rdev->chip_ctx; 425 bnxt_re_init_hwrm_hdr((void *)&req, HWRM_FUNC_QCAPS); 426 req.fid = cpu_to_le16(0xffff); 427 bnxt_re_fill_fw_msg(&fw_msg, (void *)&req, sizeof(req), (void *)&resp, 428 sizeof(resp), DFLT_HWRM_CMD_TIMEOUT); 429 430 rc = bnxt_send_msg(en_dev, &fw_msg); 431 if (rc) 432 return rc; 433 cctx->modes.db_push = le32_to_cpu(resp.flags) & FUNC_QCAPS_RESP_FLAGS_WCB_PUSH_MODE; 434 435 return 0; 436 } 437 438 static int bnxt_re_net_ring_free(struct bnxt_re_dev *rdev, 439 u16 fw_ring_id, int type) 440 { 441 struct bnxt_en_dev *en_dev; 442 struct hwrm_ring_free_input req = {}; 443 struct hwrm_ring_free_output resp; 444 struct bnxt_fw_msg fw_msg = {}; 445 int rc = -EINVAL; 446 447 if (!rdev) 448 return rc; 449 450 en_dev = rdev->en_dev; 451 452 if (!en_dev) 453 return rc; 454 455 if (test_bit(BNXT_RE_FLAG_ERR_DEVICE_DETACHED, &rdev->flags)) 456 return 0; 457 458 bnxt_re_init_hwrm_hdr((void *)&req, HWRM_RING_FREE); 459 req.ring_type = type; 460 req.ring_id = cpu_to_le16(fw_ring_id); 461 bnxt_re_fill_fw_msg(&fw_msg, (void *)&req, sizeof(req), (void *)&resp, 462 sizeof(resp), DFLT_HWRM_CMD_TIMEOUT); 463 rc = bnxt_send_msg(en_dev, &fw_msg); 464 if (rc) 465 ibdev_err(&rdev->ibdev, "Failed to free HW ring:%d :%#x", 466 req.ring_id, rc); 467 return rc; 468 } 469 470 static int bnxt_re_net_ring_alloc(struct bnxt_re_dev *rdev, 471 struct bnxt_re_ring_attr *ring_attr, 472 u16 *fw_ring_id) 473 { 474 struct bnxt_en_dev *en_dev = rdev->en_dev; 475 struct hwrm_ring_alloc_input req = {}; 476 struct hwrm_ring_alloc_output resp; 477 struct bnxt_fw_msg fw_msg = {}; 478 int rc = -EINVAL; 479 480 if (!en_dev) 481 return rc; 482 483 bnxt_re_init_hwrm_hdr((void *)&req, HWRM_RING_ALLOC); 484 req.enables = 0; 485 req.page_tbl_addr = cpu_to_le64(ring_attr->dma_arr[0]); 486 if (ring_attr->pages > 1) { 487 /* Page size is in log2 units */ 488 req.page_size = BNXT_PAGE_SHIFT; 489 req.page_tbl_depth = 1; 490 } 491 req.fbo = 0; 492 /* Association of ring index with doorbell index and MSIX number */ 493 req.logical_id = cpu_to_le16(ring_attr->lrid); 494 req.length = cpu_to_le32(ring_attr->depth + 1); 495 req.ring_type = ring_attr->type; 496 req.int_mode = ring_attr->mode; 497 bnxt_re_fill_fw_msg(&fw_msg, (void *)&req, sizeof(req), (void *)&resp, 498 sizeof(resp), DFLT_HWRM_CMD_TIMEOUT); 499 rc = bnxt_send_msg(en_dev, &fw_msg); 500 if (!rc) 501 *fw_ring_id = le16_to_cpu(resp.ring_id); 502 503 return rc; 504 } 505 506 static int bnxt_re_net_stats_ctx_free(struct bnxt_re_dev *rdev, 507 u32 fw_stats_ctx_id) 508 { 509 struct bnxt_en_dev *en_dev = rdev->en_dev; 510 struct hwrm_stat_ctx_free_input req = {}; 511 struct hwrm_stat_ctx_free_output resp = {}; 512 struct bnxt_fw_msg fw_msg = {}; 513 int rc = -EINVAL; 514 515 if (!en_dev) 516 return rc; 517 518 if (test_bit(BNXT_RE_FLAG_ERR_DEVICE_DETACHED, &rdev->flags)) 519 return 0; 520 521 bnxt_re_init_hwrm_hdr((void *)&req, HWRM_STAT_CTX_FREE); 522 req.stat_ctx_id = cpu_to_le32(fw_stats_ctx_id); 523 bnxt_re_fill_fw_msg(&fw_msg, (void *)&req, sizeof(req), (void *)&resp, 524 sizeof(resp), DFLT_HWRM_CMD_TIMEOUT); 525 rc = bnxt_send_msg(en_dev, &fw_msg); 526 if (rc) 527 ibdev_err(&rdev->ibdev, "Failed to free HW stats context %#x", 528 rc); 529 530 return rc; 531 } 532 533 static int bnxt_re_net_stats_ctx_alloc(struct bnxt_re_dev *rdev, 534 dma_addr_t dma_map, 535 u32 *fw_stats_ctx_id) 536 { 537 struct bnxt_qplib_chip_ctx *chip_ctx = rdev->chip_ctx; 538 struct hwrm_stat_ctx_alloc_output resp = {}; 539 struct hwrm_stat_ctx_alloc_input req = {}; 540 struct bnxt_en_dev *en_dev = rdev->en_dev; 541 struct bnxt_fw_msg fw_msg = {}; 542 int rc = -EINVAL; 543 544 *fw_stats_ctx_id = INVALID_STATS_CTX_ID; 545 546 if (!en_dev) 547 return rc; 548 549 bnxt_re_init_hwrm_hdr((void *)&req, HWRM_STAT_CTX_ALLOC); 550 req.update_period_ms = cpu_to_le32(1000); 551 req.stats_dma_addr = cpu_to_le64(dma_map); 552 req.stats_dma_length = cpu_to_le16(chip_ctx->hw_stats_size); 553 req.stat_ctx_flags = STAT_CTX_ALLOC_REQ_STAT_CTX_FLAGS_ROCE; 554 bnxt_re_fill_fw_msg(&fw_msg, (void *)&req, sizeof(req), (void *)&resp, 555 sizeof(resp), DFLT_HWRM_CMD_TIMEOUT); 556 rc = bnxt_send_msg(en_dev, &fw_msg); 557 if (!rc) 558 *fw_stats_ctx_id = le32_to_cpu(resp.stat_ctx_id); 559 560 return rc; 561 } 562 563 static void bnxt_re_disassociate_ucontext(struct ib_ucontext *ibcontext) 564 { 565 } 566 567 /* Device */ 568 569 static struct bnxt_re_dev *bnxt_re_from_netdev(struct net_device *netdev) 570 { 571 struct ib_device *ibdev = 572 ib_device_get_by_netdev(netdev, RDMA_DRIVER_BNXT_RE); 573 if (!ibdev) 574 return NULL; 575 576 return container_of(ibdev, struct bnxt_re_dev, ibdev); 577 } 578 579 static ssize_t hw_rev_show(struct device *device, struct device_attribute *attr, 580 char *buf) 581 { 582 struct bnxt_re_dev *rdev = 583 rdma_device_to_drv_device(device, struct bnxt_re_dev, ibdev); 584 585 return sysfs_emit(buf, "0x%x\n", rdev->en_dev->pdev->vendor); 586 } 587 static DEVICE_ATTR_RO(hw_rev); 588 589 static ssize_t hca_type_show(struct device *device, 590 struct device_attribute *attr, char *buf) 591 { 592 struct bnxt_re_dev *rdev = 593 rdma_device_to_drv_device(device, struct bnxt_re_dev, ibdev); 594 595 return sysfs_emit(buf, "%s\n", rdev->ibdev.node_desc); 596 } 597 static DEVICE_ATTR_RO(hca_type); 598 599 static struct attribute *bnxt_re_attributes[] = { 600 &dev_attr_hw_rev.attr, 601 &dev_attr_hca_type.attr, 602 NULL 603 }; 604 605 static const struct attribute_group bnxt_re_dev_attr_group = { 606 .attrs = bnxt_re_attributes, 607 }; 608 609 static const struct ib_device_ops bnxt_re_dev_ops = { 610 .owner = THIS_MODULE, 611 .driver_id = RDMA_DRIVER_BNXT_RE, 612 .uverbs_abi_ver = BNXT_RE_ABI_VERSION, 613 614 .add_gid = bnxt_re_add_gid, 615 .alloc_hw_port_stats = bnxt_re_ib_alloc_hw_port_stats, 616 .alloc_mr = bnxt_re_alloc_mr, 617 .alloc_pd = bnxt_re_alloc_pd, 618 .alloc_ucontext = bnxt_re_alloc_ucontext, 619 .create_ah = bnxt_re_create_ah, 620 .create_cq = bnxt_re_create_cq, 621 .create_qp = bnxt_re_create_qp, 622 .create_srq = bnxt_re_create_srq, 623 .create_user_ah = bnxt_re_create_ah, 624 .dealloc_pd = bnxt_re_dealloc_pd, 625 .dealloc_ucontext = bnxt_re_dealloc_ucontext, 626 .del_gid = bnxt_re_del_gid, 627 .dereg_mr = bnxt_re_dereg_mr, 628 .destroy_ah = bnxt_re_destroy_ah, 629 .destroy_cq = bnxt_re_destroy_cq, 630 .destroy_qp = bnxt_re_destroy_qp, 631 .destroy_srq = bnxt_re_destroy_srq, 632 .device_group = &bnxt_re_dev_attr_group, 633 .disassociate_ucontext = bnxt_re_disassociate_ucontext, 634 .get_dev_fw_str = bnxt_re_query_fw_str, 635 .get_dma_mr = bnxt_re_get_dma_mr, 636 .get_hw_stats = bnxt_re_ib_get_hw_stats, 637 .get_link_layer = bnxt_re_get_link_layer, 638 .get_port_immutable = bnxt_re_get_port_immutable, 639 .map_mr_sg = bnxt_re_map_mr_sg, 640 .mmap = bnxt_re_mmap, 641 .mmap_free = bnxt_re_mmap_free, 642 .modify_qp = bnxt_re_modify_qp, 643 .modify_srq = bnxt_re_modify_srq, 644 .poll_cq = bnxt_re_poll_cq, 645 .post_recv = bnxt_re_post_recv, 646 .post_send = bnxt_re_post_send, 647 .post_srq_recv = bnxt_re_post_srq_recv, 648 .query_ah = bnxt_re_query_ah, 649 .query_device = bnxt_re_query_device, 650 .query_pkey = bnxt_re_query_pkey, 651 .query_port = bnxt_re_query_port, 652 .query_qp = bnxt_re_query_qp, 653 .query_srq = bnxt_re_query_srq, 654 .reg_user_mr = bnxt_re_reg_user_mr, 655 .req_notify_cq = bnxt_re_req_notify_cq, 656 .resize_cq = bnxt_re_resize_cq, 657 INIT_RDMA_OBJ_SIZE(ib_ah, bnxt_re_ah, ib_ah), 658 INIT_RDMA_OBJ_SIZE(ib_cq, bnxt_re_cq, ib_cq), 659 INIT_RDMA_OBJ_SIZE(ib_pd, bnxt_re_pd, ib_pd), 660 INIT_RDMA_OBJ_SIZE(ib_qp, bnxt_re_qp, ib_qp), 661 INIT_RDMA_OBJ_SIZE(ib_srq, bnxt_re_srq, ib_srq), 662 INIT_RDMA_OBJ_SIZE(ib_ucontext, bnxt_re_ucontext, ib_uctx), 663 }; 664 665 static int bnxt_re_register_ib(struct bnxt_re_dev *rdev) 666 { 667 struct ib_device *ibdev = &rdev->ibdev; 668 int ret; 669 670 /* ib device init */ 671 ibdev->node_type = RDMA_NODE_IB_CA; 672 strscpy(ibdev->node_desc, BNXT_RE_DESC " HCA", 673 strlen(BNXT_RE_DESC) + 5); 674 ibdev->phys_port_cnt = 1; 675 676 addrconf_addr_eui48((u8 *)&ibdev->node_guid, rdev->netdev->dev_addr); 677 678 ibdev->num_comp_vectors = rdev->num_msix - 1; 679 ibdev->dev.parent = &rdev->en_dev->pdev->dev; 680 ibdev->local_dma_lkey = BNXT_QPLIB_RSVD_LKEY; 681 682 if (IS_ENABLED(CONFIG_INFINIBAND_USER_ACCESS)) 683 ibdev->driver_def = bnxt_re_uapi_defs; 684 685 ib_set_device_ops(ibdev, &bnxt_re_dev_ops); 686 ret = ib_device_set_netdev(&rdev->ibdev, rdev->netdev, 1); 687 if (ret) 688 return ret; 689 690 dma_set_max_seg_size(&rdev->en_dev->pdev->dev, UINT_MAX); 691 ibdev->uverbs_cmd_mask |= BIT_ULL(IB_USER_VERBS_CMD_POLL_CQ); 692 return ib_register_device(ibdev, "bnxt_re%d", &rdev->en_dev->pdev->dev); 693 } 694 695 static struct bnxt_re_dev *bnxt_re_dev_add(struct bnxt_aux_priv *aux_priv, 696 struct bnxt_en_dev *en_dev) 697 { 698 struct bnxt_re_dev *rdev; 699 700 /* Allocate bnxt_re_dev instance here */ 701 rdev = ib_alloc_device(bnxt_re_dev, ibdev); 702 if (!rdev) { 703 ibdev_err(NULL, "%s: bnxt_re_dev allocation failure!", 704 ROCE_DRV_MODULE_NAME); 705 return NULL; 706 } 707 /* Default values */ 708 rdev->nb.notifier_call = NULL; 709 rdev->netdev = en_dev->net; 710 rdev->en_dev = en_dev; 711 rdev->id = rdev->en_dev->pdev->devfn; 712 INIT_LIST_HEAD(&rdev->qp_list); 713 mutex_init(&rdev->qp_lock); 714 atomic_set(&rdev->qp_count, 0); 715 atomic_set(&rdev->cq_count, 0); 716 atomic_set(&rdev->srq_count, 0); 717 atomic_set(&rdev->mr_count, 0); 718 atomic_set(&rdev->mw_count, 0); 719 atomic_set(&rdev->ah_count, 0); 720 atomic_set(&rdev->pd_count, 0); 721 rdev->cosq[0] = 0xFFFF; 722 rdev->cosq[1] = 0xFFFF; 723 724 return rdev; 725 } 726 727 static int bnxt_re_handle_unaffi_async_event(struct creq_func_event 728 *unaffi_async) 729 { 730 switch (unaffi_async->event) { 731 case CREQ_FUNC_EVENT_EVENT_TX_WQE_ERROR: 732 break; 733 case CREQ_FUNC_EVENT_EVENT_TX_DATA_ERROR: 734 break; 735 case CREQ_FUNC_EVENT_EVENT_RX_WQE_ERROR: 736 break; 737 case CREQ_FUNC_EVENT_EVENT_RX_DATA_ERROR: 738 break; 739 case CREQ_FUNC_EVENT_EVENT_CQ_ERROR: 740 break; 741 case CREQ_FUNC_EVENT_EVENT_TQM_ERROR: 742 break; 743 case CREQ_FUNC_EVENT_EVENT_CFCQ_ERROR: 744 break; 745 case CREQ_FUNC_EVENT_EVENT_CFCS_ERROR: 746 break; 747 case CREQ_FUNC_EVENT_EVENT_CFCC_ERROR: 748 break; 749 case CREQ_FUNC_EVENT_EVENT_CFCM_ERROR: 750 break; 751 case CREQ_FUNC_EVENT_EVENT_TIM_ERROR: 752 break; 753 default: 754 return -EINVAL; 755 } 756 return 0; 757 } 758 759 static int bnxt_re_handle_qp_async_event(struct creq_qp_event *qp_event, 760 struct bnxt_re_qp *qp) 761 { 762 struct ib_event event; 763 unsigned int flags; 764 765 if (qp->qplib_qp.state == CMDQ_MODIFY_QP_NEW_STATE_ERR && 766 rdma_is_kernel_res(&qp->ib_qp.res)) { 767 flags = bnxt_re_lock_cqs(qp); 768 bnxt_qplib_add_flush_qp(&qp->qplib_qp); 769 bnxt_re_unlock_cqs(qp, flags); 770 } 771 772 memset(&event, 0, sizeof(event)); 773 if (qp->qplib_qp.srq) { 774 event.device = &qp->rdev->ibdev; 775 event.element.qp = &qp->ib_qp; 776 event.event = IB_EVENT_QP_LAST_WQE_REACHED; 777 } 778 779 if (event.device && qp->ib_qp.event_handler) 780 qp->ib_qp.event_handler(&event, qp->ib_qp.qp_context); 781 782 return 0; 783 } 784 785 static int bnxt_re_handle_affi_async_event(struct creq_qp_event *affi_async, 786 void *obj) 787 { 788 int rc = 0; 789 u8 event; 790 791 if (!obj) 792 return rc; /* QP was already dead, still return success */ 793 794 event = affi_async->event; 795 if (event == CREQ_QP_EVENT_EVENT_QP_ERROR_NOTIFICATION) { 796 struct bnxt_qplib_qp *lib_qp = obj; 797 struct bnxt_re_qp *qp = container_of(lib_qp, struct bnxt_re_qp, 798 qplib_qp); 799 rc = bnxt_re_handle_qp_async_event(affi_async, qp); 800 } 801 return rc; 802 } 803 804 static int bnxt_re_aeq_handler(struct bnxt_qplib_rcfw *rcfw, 805 void *aeqe, void *obj) 806 { 807 struct creq_qp_event *affi_async; 808 struct creq_func_event *unaffi_async; 809 u8 type; 810 int rc; 811 812 type = ((struct creq_base *)aeqe)->type; 813 if (type == CREQ_BASE_TYPE_FUNC_EVENT) { 814 unaffi_async = aeqe; 815 rc = bnxt_re_handle_unaffi_async_event(unaffi_async); 816 } else { 817 affi_async = aeqe; 818 rc = bnxt_re_handle_affi_async_event(affi_async, obj); 819 } 820 821 return rc; 822 } 823 824 static int bnxt_re_srqn_handler(struct bnxt_qplib_nq *nq, 825 struct bnxt_qplib_srq *handle, u8 event) 826 { 827 struct bnxt_re_srq *srq = container_of(handle, struct bnxt_re_srq, 828 qplib_srq); 829 struct ib_event ib_event; 830 831 ib_event.device = &srq->rdev->ibdev; 832 ib_event.element.srq = &srq->ib_srq; 833 if (event == NQ_SRQ_EVENT_EVENT_SRQ_THRESHOLD_EVENT) 834 ib_event.event = IB_EVENT_SRQ_LIMIT_REACHED; 835 else 836 ib_event.event = IB_EVENT_SRQ_ERR; 837 838 if (srq->ib_srq.event_handler) { 839 /* Lock event_handler? */ 840 (*srq->ib_srq.event_handler)(&ib_event, 841 srq->ib_srq.srq_context); 842 } 843 return 0; 844 } 845 846 static int bnxt_re_cqn_handler(struct bnxt_qplib_nq *nq, 847 struct bnxt_qplib_cq *handle) 848 { 849 struct bnxt_re_cq *cq = container_of(handle, struct bnxt_re_cq, 850 qplib_cq); 851 852 if (cq->ib_cq.comp_handler) { 853 /* Lock comp_handler? */ 854 (*cq->ib_cq.comp_handler)(&cq->ib_cq, cq->ib_cq.cq_context); 855 } 856 857 return 0; 858 } 859 860 #define BNXT_RE_GEN_P5_PF_NQ_DB 0x10000 861 #define BNXT_RE_GEN_P5_VF_NQ_DB 0x4000 862 static u32 bnxt_re_get_nqdb_offset(struct bnxt_re_dev *rdev, u16 indx) 863 { 864 return bnxt_qplib_is_chip_gen_p5(rdev->chip_ctx) ? 865 (rdev->is_virtfn ? BNXT_RE_GEN_P5_VF_NQ_DB : 866 BNXT_RE_GEN_P5_PF_NQ_DB) : 867 rdev->en_dev->msix_entries[indx].db_offset; 868 } 869 870 static void bnxt_re_cleanup_res(struct bnxt_re_dev *rdev) 871 { 872 int i; 873 874 for (i = 1; i < rdev->num_msix; i++) 875 bnxt_qplib_disable_nq(&rdev->nq[i - 1]); 876 877 if (rdev->qplib_res.rcfw) 878 bnxt_qplib_cleanup_res(&rdev->qplib_res); 879 } 880 881 static int bnxt_re_init_res(struct bnxt_re_dev *rdev) 882 { 883 int num_vec_enabled = 0; 884 int rc = 0, i; 885 u32 db_offt; 886 887 bnxt_qplib_init_res(&rdev->qplib_res); 888 889 for (i = 1; i < rdev->num_msix ; i++) { 890 db_offt = bnxt_re_get_nqdb_offset(rdev, i); 891 rc = bnxt_qplib_enable_nq(rdev->en_dev->pdev, &rdev->nq[i - 1], 892 i - 1, rdev->en_dev->msix_entries[i].vector, 893 db_offt, &bnxt_re_cqn_handler, 894 &bnxt_re_srqn_handler); 895 if (rc) { 896 ibdev_err(&rdev->ibdev, 897 "Failed to enable NQ with rc = 0x%x", rc); 898 goto fail; 899 } 900 num_vec_enabled++; 901 } 902 return 0; 903 fail: 904 for (i = num_vec_enabled; i >= 0; i--) 905 bnxt_qplib_disable_nq(&rdev->nq[i]); 906 return rc; 907 } 908 909 static void bnxt_re_free_nq_res(struct bnxt_re_dev *rdev) 910 { 911 u8 type; 912 int i; 913 914 for (i = 0; i < rdev->num_msix - 1; i++) { 915 type = bnxt_qplib_get_ring_type(rdev->chip_ctx); 916 bnxt_re_net_ring_free(rdev, rdev->nq[i].ring_id, type); 917 bnxt_qplib_free_nq(&rdev->nq[i]); 918 rdev->nq[i].res = NULL; 919 } 920 } 921 922 static void bnxt_re_free_res(struct bnxt_re_dev *rdev) 923 { 924 bnxt_re_free_nq_res(rdev); 925 926 if (rdev->qplib_res.dpi_tbl.max) { 927 bnxt_qplib_dealloc_dpi(&rdev->qplib_res, 928 &rdev->dpi_privileged); 929 } 930 if (rdev->qplib_res.rcfw) { 931 bnxt_qplib_free_res(&rdev->qplib_res); 932 rdev->qplib_res.rcfw = NULL; 933 } 934 } 935 936 static int bnxt_re_alloc_res(struct bnxt_re_dev *rdev) 937 { 938 struct bnxt_re_ring_attr rattr = {}; 939 int num_vec_created = 0; 940 int rc = 0, i; 941 u8 type; 942 943 /* Configure and allocate resources for qplib */ 944 rdev->qplib_res.rcfw = &rdev->rcfw; 945 rc = bnxt_qplib_get_dev_attr(&rdev->rcfw, &rdev->dev_attr, 946 rdev->is_virtfn); 947 if (rc) 948 goto fail; 949 950 rc = bnxt_qplib_alloc_res(&rdev->qplib_res, rdev->en_dev->pdev, 951 rdev->netdev, &rdev->dev_attr); 952 if (rc) 953 goto fail; 954 955 rc = bnxt_qplib_alloc_dpi(&rdev->qplib_res, 956 &rdev->dpi_privileged, 957 rdev, BNXT_QPLIB_DPI_TYPE_KERNEL); 958 if (rc) 959 goto dealloc_res; 960 961 for (i = 0; i < rdev->num_msix - 1; i++) { 962 struct bnxt_qplib_nq *nq; 963 964 nq = &rdev->nq[i]; 965 nq->hwq.max_elements = BNXT_QPLIB_NQE_MAX_CNT; 966 rc = bnxt_qplib_alloc_nq(&rdev->qplib_res, &rdev->nq[i]); 967 if (rc) { 968 ibdev_err(&rdev->ibdev, "Alloc Failed NQ%d rc:%#x", 969 i, rc); 970 goto free_nq; 971 } 972 type = bnxt_qplib_get_ring_type(rdev->chip_ctx); 973 rattr.dma_arr = nq->hwq.pbl[PBL_LVL_0].pg_map_arr; 974 rattr.pages = nq->hwq.pbl[rdev->nq[i].hwq.level].pg_count; 975 rattr.type = type; 976 rattr.mode = RING_ALLOC_REQ_INT_MODE_MSIX; 977 rattr.depth = BNXT_QPLIB_NQE_MAX_CNT - 1; 978 rattr.lrid = rdev->en_dev->msix_entries[i + 1].ring_idx; 979 rc = bnxt_re_net_ring_alloc(rdev, &rattr, &nq->ring_id); 980 if (rc) { 981 ibdev_err(&rdev->ibdev, 982 "Failed to allocate NQ fw id with rc = 0x%x", 983 rc); 984 bnxt_qplib_free_nq(&rdev->nq[i]); 985 goto free_nq; 986 } 987 num_vec_created++; 988 } 989 return 0; 990 free_nq: 991 for (i = num_vec_created - 1; i >= 0; i--) { 992 type = bnxt_qplib_get_ring_type(rdev->chip_ctx); 993 bnxt_re_net_ring_free(rdev, rdev->nq[i].ring_id, type); 994 bnxt_qplib_free_nq(&rdev->nq[i]); 995 } 996 bnxt_qplib_dealloc_dpi(&rdev->qplib_res, 997 &rdev->dpi_privileged); 998 dealloc_res: 999 bnxt_qplib_free_res(&rdev->qplib_res); 1000 1001 fail: 1002 rdev->qplib_res.rcfw = NULL; 1003 return rc; 1004 } 1005 1006 static void bnxt_re_dispatch_event(struct ib_device *ibdev, struct ib_qp *qp, 1007 u8 port_num, enum ib_event_type event) 1008 { 1009 struct ib_event ib_event; 1010 1011 ib_event.device = ibdev; 1012 if (qp) { 1013 ib_event.element.qp = qp; 1014 ib_event.event = event; 1015 if (qp->event_handler) 1016 qp->event_handler(&ib_event, qp->qp_context); 1017 1018 } else { 1019 ib_event.element.port_num = port_num; 1020 ib_event.event = event; 1021 ib_dispatch_event(&ib_event); 1022 } 1023 } 1024 1025 static bool bnxt_re_is_qp1_or_shadow_qp(struct bnxt_re_dev *rdev, 1026 struct bnxt_re_qp *qp) 1027 { 1028 return (qp->ib_qp.qp_type == IB_QPT_GSI) || 1029 (qp == rdev->gsi_ctx.gsi_sqp); 1030 } 1031 1032 static void bnxt_re_dev_stop(struct bnxt_re_dev *rdev) 1033 { 1034 int mask = IB_QP_STATE; 1035 struct ib_qp_attr qp_attr; 1036 struct bnxt_re_qp *qp; 1037 1038 qp_attr.qp_state = IB_QPS_ERR; 1039 mutex_lock(&rdev->qp_lock); 1040 list_for_each_entry(qp, &rdev->qp_list, list) { 1041 /* Modify the state of all QPs except QP1/Shadow QP */ 1042 if (!bnxt_re_is_qp1_or_shadow_qp(rdev, qp)) { 1043 if (qp->qplib_qp.state != 1044 CMDQ_MODIFY_QP_NEW_STATE_RESET && 1045 qp->qplib_qp.state != 1046 CMDQ_MODIFY_QP_NEW_STATE_ERR) { 1047 bnxt_re_dispatch_event(&rdev->ibdev, &qp->ib_qp, 1048 1, IB_EVENT_QP_FATAL); 1049 bnxt_re_modify_qp(&qp->ib_qp, &qp_attr, mask, 1050 NULL); 1051 } 1052 } 1053 } 1054 mutex_unlock(&rdev->qp_lock); 1055 } 1056 1057 static int bnxt_re_update_gid(struct bnxt_re_dev *rdev) 1058 { 1059 struct bnxt_qplib_sgid_tbl *sgid_tbl = &rdev->qplib_res.sgid_tbl; 1060 struct bnxt_qplib_gid gid; 1061 u16 gid_idx, index; 1062 int rc = 0; 1063 1064 if (!ib_device_try_get(&rdev->ibdev)) 1065 return 0; 1066 1067 for (index = 0; index < sgid_tbl->active; index++) { 1068 gid_idx = sgid_tbl->hw_id[index]; 1069 1070 if (!memcmp(&sgid_tbl->tbl[index], &bnxt_qplib_gid_zero, 1071 sizeof(bnxt_qplib_gid_zero))) 1072 continue; 1073 /* need to modify the VLAN enable setting of non VLAN GID only 1074 * as setting is done for VLAN GID while adding GID 1075 */ 1076 if (sgid_tbl->vlan[index]) 1077 continue; 1078 1079 memcpy(&gid, &sgid_tbl->tbl[index], sizeof(gid)); 1080 1081 rc = bnxt_qplib_update_sgid(sgid_tbl, &gid, gid_idx, 1082 rdev->qplib_res.netdev->dev_addr); 1083 } 1084 1085 ib_device_put(&rdev->ibdev); 1086 return rc; 1087 } 1088 1089 static u32 bnxt_re_get_priority_mask(struct bnxt_re_dev *rdev) 1090 { 1091 u32 prio_map = 0, tmp_map = 0; 1092 struct net_device *netdev; 1093 struct dcb_app app; 1094 1095 netdev = rdev->netdev; 1096 1097 memset(&app, 0, sizeof(app)); 1098 app.selector = IEEE_8021QAZ_APP_SEL_ETHERTYPE; 1099 app.protocol = ETH_P_IBOE; 1100 tmp_map = dcb_ieee_getapp_mask(netdev, &app); 1101 prio_map = tmp_map; 1102 1103 app.selector = IEEE_8021QAZ_APP_SEL_DGRAM; 1104 app.protocol = ROCE_V2_UDP_DPORT; 1105 tmp_map = dcb_ieee_getapp_mask(netdev, &app); 1106 prio_map |= tmp_map; 1107 1108 return prio_map; 1109 } 1110 1111 static int bnxt_re_setup_qos(struct bnxt_re_dev *rdev) 1112 { 1113 u8 prio_map = 0; 1114 1115 /* Get priority for roce */ 1116 prio_map = bnxt_re_get_priority_mask(rdev); 1117 1118 if (prio_map == rdev->cur_prio_map) 1119 return 0; 1120 rdev->cur_prio_map = prio_map; 1121 /* Actual priorities are not programmed as they are already 1122 * done by L2 driver; just enable or disable priority vlan tagging 1123 */ 1124 if ((prio_map == 0 && rdev->qplib_res.prio) || 1125 (prio_map != 0 && !rdev->qplib_res.prio)) { 1126 rdev->qplib_res.prio = prio_map ? true : false; 1127 1128 bnxt_re_update_gid(rdev); 1129 } 1130 1131 return 0; 1132 } 1133 1134 static void bnxt_re_query_hwrm_intf_version(struct bnxt_re_dev *rdev) 1135 { 1136 struct bnxt_en_dev *en_dev = rdev->en_dev; 1137 struct hwrm_ver_get_output resp = {}; 1138 struct hwrm_ver_get_input req = {}; 1139 struct bnxt_qplib_chip_ctx *cctx; 1140 struct bnxt_fw_msg fw_msg = {}; 1141 int rc = 0; 1142 1143 bnxt_re_init_hwrm_hdr((void *)&req, HWRM_VER_GET); 1144 req.hwrm_intf_maj = HWRM_VERSION_MAJOR; 1145 req.hwrm_intf_min = HWRM_VERSION_MINOR; 1146 req.hwrm_intf_upd = HWRM_VERSION_UPDATE; 1147 bnxt_re_fill_fw_msg(&fw_msg, (void *)&req, sizeof(req), (void *)&resp, 1148 sizeof(resp), DFLT_HWRM_CMD_TIMEOUT); 1149 rc = bnxt_send_msg(en_dev, &fw_msg); 1150 if (rc) { 1151 ibdev_err(&rdev->ibdev, "Failed to query HW version, rc = 0x%x", 1152 rc); 1153 return; 1154 } 1155 1156 cctx = rdev->chip_ctx; 1157 cctx->hwrm_intf_ver = 1158 (u64)le16_to_cpu(resp.hwrm_intf_major) << 48 | 1159 (u64)le16_to_cpu(resp.hwrm_intf_minor) << 32 | 1160 (u64)le16_to_cpu(resp.hwrm_intf_build) << 16 | 1161 le16_to_cpu(resp.hwrm_intf_patch); 1162 1163 cctx->hwrm_cmd_max_timeout = le16_to_cpu(resp.max_req_timeout); 1164 1165 if (!cctx->hwrm_cmd_max_timeout) 1166 cctx->hwrm_cmd_max_timeout = RCFW_FW_STALL_MAX_TIMEOUT; 1167 } 1168 1169 static int bnxt_re_ib_init(struct bnxt_re_dev *rdev) 1170 { 1171 int rc = 0; 1172 u32 event; 1173 1174 /* Register ib dev */ 1175 rc = bnxt_re_register_ib(rdev); 1176 if (rc) { 1177 pr_err("Failed to register with IB: %#x\n", rc); 1178 return rc; 1179 } 1180 dev_info(rdev_to_dev(rdev), "Device registered with IB successfully"); 1181 set_bit(BNXT_RE_FLAG_ISSUE_ROCE_STATS, &rdev->flags); 1182 1183 event = netif_running(rdev->netdev) && netif_carrier_ok(rdev->netdev) ? 1184 IB_EVENT_PORT_ACTIVE : IB_EVENT_PORT_ERR; 1185 1186 bnxt_re_dispatch_event(&rdev->ibdev, NULL, 1, event); 1187 1188 return rc; 1189 } 1190 1191 static void bnxt_re_dev_uninit(struct bnxt_re_dev *rdev) 1192 { 1193 u8 type; 1194 int rc; 1195 1196 if (test_and_clear_bit(BNXT_RE_FLAG_QOS_WORK_REG, &rdev->flags)) 1197 cancel_delayed_work_sync(&rdev->worker); 1198 1199 if (test_and_clear_bit(BNXT_RE_FLAG_RESOURCES_INITIALIZED, 1200 &rdev->flags)) 1201 bnxt_re_cleanup_res(rdev); 1202 if (test_and_clear_bit(BNXT_RE_FLAG_RESOURCES_ALLOCATED, &rdev->flags)) 1203 bnxt_re_free_res(rdev); 1204 1205 if (test_and_clear_bit(BNXT_RE_FLAG_RCFW_CHANNEL_EN, &rdev->flags)) { 1206 rc = bnxt_qplib_deinit_rcfw(&rdev->rcfw); 1207 if (rc) 1208 ibdev_warn(&rdev->ibdev, 1209 "Failed to deinitialize RCFW: %#x", rc); 1210 bnxt_re_net_stats_ctx_free(rdev, rdev->qplib_ctx.stats.fw_id); 1211 bnxt_qplib_free_ctx(&rdev->qplib_res, &rdev->qplib_ctx); 1212 bnxt_qplib_disable_rcfw_channel(&rdev->rcfw); 1213 type = bnxt_qplib_get_ring_type(rdev->chip_ctx); 1214 bnxt_re_net_ring_free(rdev, rdev->rcfw.creq.ring_id, type); 1215 bnxt_qplib_free_rcfw_channel(&rdev->rcfw); 1216 } 1217 if (test_and_clear_bit(BNXT_RE_FLAG_GOT_MSIX, &rdev->flags)) 1218 rdev->num_msix = 0; 1219 1220 bnxt_re_destroy_chip_ctx(rdev); 1221 if (test_and_clear_bit(BNXT_RE_FLAG_NETDEV_REGISTERED, &rdev->flags)) 1222 bnxt_unregister_dev(rdev->en_dev); 1223 } 1224 1225 /* worker thread for polling periodic events. Now used for QoS programming*/ 1226 static void bnxt_re_worker(struct work_struct *work) 1227 { 1228 struct bnxt_re_dev *rdev = container_of(work, struct bnxt_re_dev, 1229 worker.work); 1230 1231 bnxt_re_setup_qos(rdev); 1232 schedule_delayed_work(&rdev->worker, msecs_to_jiffies(30000)); 1233 } 1234 1235 static int bnxt_re_dev_init(struct bnxt_re_dev *rdev, u8 wqe_mode) 1236 { 1237 struct bnxt_qplib_creq_ctx *creq; 1238 struct bnxt_re_ring_attr rattr; 1239 u32 db_offt; 1240 int vid; 1241 u8 type; 1242 int rc; 1243 1244 /* Registered a new RoCE device instance to netdev */ 1245 memset(&rattr, 0, sizeof(rattr)); 1246 rc = bnxt_re_register_netdev(rdev); 1247 if (rc) { 1248 ibdev_err(&rdev->ibdev, 1249 "Failed to register with netedev: %#x\n", rc); 1250 return -EINVAL; 1251 } 1252 set_bit(BNXT_RE_FLAG_NETDEV_REGISTERED, &rdev->flags); 1253 1254 rc = bnxt_re_setup_chip_ctx(rdev, wqe_mode); 1255 if (rc) { 1256 ibdev_err(&rdev->ibdev, "Failed to get chip context\n"); 1257 return -EINVAL; 1258 } 1259 1260 /* Check whether VF or PF */ 1261 bnxt_re_get_sriov_func_type(rdev); 1262 1263 if (!rdev->en_dev->ulp_tbl->msix_requested) { 1264 ibdev_err(&rdev->ibdev, 1265 "Failed to get MSI-X vectors: %#x\n", rc); 1266 rc = -EINVAL; 1267 goto fail; 1268 } 1269 ibdev_dbg(&rdev->ibdev, "Got %d MSI-X vectors\n", 1270 rdev->en_dev->ulp_tbl->msix_requested); 1271 rdev->num_msix = rdev->en_dev->ulp_tbl->msix_requested; 1272 set_bit(BNXT_RE_FLAG_GOT_MSIX, &rdev->flags); 1273 1274 bnxt_re_query_hwrm_intf_version(rdev); 1275 1276 /* Establish RCFW Communication Channel to initialize the context 1277 * memory for the function and all child VFs 1278 */ 1279 rc = bnxt_qplib_alloc_rcfw_channel(&rdev->qplib_res, &rdev->rcfw, 1280 &rdev->qplib_ctx, 1281 BNXT_RE_MAX_QPC_COUNT); 1282 if (rc) { 1283 ibdev_err(&rdev->ibdev, 1284 "Failed to allocate RCFW Channel: %#x\n", rc); 1285 goto fail; 1286 } 1287 1288 type = bnxt_qplib_get_ring_type(rdev->chip_ctx); 1289 creq = &rdev->rcfw.creq; 1290 rattr.dma_arr = creq->hwq.pbl[PBL_LVL_0].pg_map_arr; 1291 rattr.pages = creq->hwq.pbl[creq->hwq.level].pg_count; 1292 rattr.type = type; 1293 rattr.mode = RING_ALLOC_REQ_INT_MODE_MSIX; 1294 rattr.depth = BNXT_QPLIB_CREQE_MAX_CNT - 1; 1295 rattr.lrid = rdev->en_dev->msix_entries[BNXT_RE_AEQ_IDX].ring_idx; 1296 rc = bnxt_re_net_ring_alloc(rdev, &rattr, &creq->ring_id); 1297 if (rc) { 1298 ibdev_err(&rdev->ibdev, "Failed to allocate CREQ: %#x\n", rc); 1299 goto free_rcfw; 1300 } 1301 db_offt = bnxt_re_get_nqdb_offset(rdev, BNXT_RE_AEQ_IDX); 1302 vid = rdev->en_dev->msix_entries[BNXT_RE_AEQ_IDX].vector; 1303 rc = bnxt_qplib_enable_rcfw_channel(&rdev->rcfw, 1304 vid, db_offt, 1305 &bnxt_re_aeq_handler); 1306 if (rc) { 1307 ibdev_err(&rdev->ibdev, "Failed to enable RCFW channel: %#x\n", 1308 rc); 1309 goto free_ring; 1310 } 1311 1312 rc = bnxt_qplib_get_dev_attr(&rdev->rcfw, &rdev->dev_attr, 1313 rdev->is_virtfn); 1314 if (rc) 1315 goto disable_rcfw; 1316 1317 bnxt_re_set_resource_limits(rdev); 1318 1319 rc = bnxt_qplib_alloc_ctx(&rdev->qplib_res, &rdev->qplib_ctx, 0, 1320 bnxt_qplib_is_chip_gen_p5(rdev->chip_ctx)); 1321 if (rc) { 1322 ibdev_err(&rdev->ibdev, 1323 "Failed to allocate QPLIB context: %#x\n", rc); 1324 goto disable_rcfw; 1325 } 1326 rc = bnxt_re_net_stats_ctx_alloc(rdev, 1327 rdev->qplib_ctx.stats.dma_map, 1328 &rdev->qplib_ctx.stats.fw_id); 1329 if (rc) { 1330 ibdev_err(&rdev->ibdev, 1331 "Failed to allocate stats context: %#x\n", rc); 1332 goto free_ctx; 1333 } 1334 1335 rc = bnxt_qplib_init_rcfw(&rdev->rcfw, &rdev->qplib_ctx, 1336 rdev->is_virtfn); 1337 if (rc) { 1338 ibdev_err(&rdev->ibdev, 1339 "Failed to initialize RCFW: %#x\n", rc); 1340 goto free_sctx; 1341 } 1342 set_bit(BNXT_RE_FLAG_RCFW_CHANNEL_EN, &rdev->flags); 1343 1344 /* Resources based on the 'new' device caps */ 1345 rc = bnxt_re_alloc_res(rdev); 1346 if (rc) { 1347 ibdev_err(&rdev->ibdev, 1348 "Failed to allocate resources: %#x\n", rc); 1349 goto fail; 1350 } 1351 set_bit(BNXT_RE_FLAG_RESOURCES_ALLOCATED, &rdev->flags); 1352 rc = bnxt_re_init_res(rdev); 1353 if (rc) { 1354 ibdev_err(&rdev->ibdev, 1355 "Failed to initialize resources: %#x\n", rc); 1356 goto fail; 1357 } 1358 1359 set_bit(BNXT_RE_FLAG_RESOURCES_INITIALIZED, &rdev->flags); 1360 1361 if (!rdev->is_virtfn) { 1362 rc = bnxt_re_setup_qos(rdev); 1363 if (rc) 1364 ibdev_info(&rdev->ibdev, 1365 "RoCE priority not yet configured\n"); 1366 1367 INIT_DELAYED_WORK(&rdev->worker, bnxt_re_worker); 1368 set_bit(BNXT_RE_FLAG_QOS_WORK_REG, &rdev->flags); 1369 schedule_delayed_work(&rdev->worker, msecs_to_jiffies(30000)); 1370 /* 1371 * Use the total VF count since the actual VF count may not be 1372 * available at this point. 1373 */ 1374 bnxt_re_vf_res_config(rdev); 1375 } 1376 1377 return 0; 1378 free_sctx: 1379 bnxt_re_net_stats_ctx_free(rdev, rdev->qplib_ctx.stats.fw_id); 1380 free_ctx: 1381 bnxt_qplib_free_ctx(&rdev->qplib_res, &rdev->qplib_ctx); 1382 disable_rcfw: 1383 bnxt_qplib_disable_rcfw_channel(&rdev->rcfw); 1384 free_ring: 1385 type = bnxt_qplib_get_ring_type(rdev->chip_ctx); 1386 bnxt_re_net_ring_free(rdev, rdev->rcfw.creq.ring_id, type); 1387 free_rcfw: 1388 bnxt_qplib_free_rcfw_channel(&rdev->rcfw); 1389 fail: 1390 bnxt_re_dev_uninit(rdev); 1391 1392 return rc; 1393 } 1394 1395 static int bnxt_re_add_device(struct auxiliary_device *adev, u8 wqe_mode) 1396 { 1397 struct bnxt_aux_priv *aux_priv = 1398 container_of(adev, struct bnxt_aux_priv, aux_dev); 1399 struct bnxt_en_dev *en_dev; 1400 struct bnxt_re_dev *rdev; 1401 int rc = 0; 1402 1403 /* en_dev should never be NULL as long as adev and aux_dev are valid. */ 1404 en_dev = aux_priv->edev; 1405 1406 rdev = bnxt_re_dev_add(aux_priv, en_dev); 1407 if (!rdev || !rdev_to_dev(rdev)) { 1408 rc = -ENOMEM; 1409 goto exit; 1410 } 1411 1412 rc = bnxt_re_dev_init(rdev, wqe_mode); 1413 if (rc) 1414 goto re_dev_dealloc; 1415 1416 rc = bnxt_re_ib_init(rdev); 1417 if (rc) { 1418 pr_err("Failed to register with IB: %s", 1419 aux_priv->aux_dev.name); 1420 goto re_dev_uninit; 1421 } 1422 auxiliary_set_drvdata(adev, rdev); 1423 1424 return 0; 1425 1426 re_dev_uninit: 1427 bnxt_re_dev_uninit(rdev); 1428 re_dev_dealloc: 1429 ib_dealloc_device(&rdev->ibdev); 1430 exit: 1431 return rc; 1432 } 1433 1434 static void bnxt_re_setup_cc(struct bnxt_re_dev *rdev, bool enable) 1435 { 1436 struct bnxt_qplib_cc_param cc_param = {}; 1437 1438 /* Do not enable congestion control on VFs */ 1439 if (rdev->is_virtfn) 1440 return; 1441 1442 /* Currently enabling only for GenP5 adapters */ 1443 if (!bnxt_qplib_is_chip_gen_p5(rdev->chip_ctx)) 1444 return; 1445 1446 if (enable) { 1447 cc_param.enable = 1; 1448 cc_param.cc_mode = CMDQ_MODIFY_ROCE_CC_CC_MODE_PROBABILISTIC_CC_MODE; 1449 } 1450 1451 cc_param.mask = (CMDQ_MODIFY_ROCE_CC_MODIFY_MASK_CC_MODE | 1452 CMDQ_MODIFY_ROCE_CC_MODIFY_MASK_ENABLE_CC | 1453 CMDQ_MODIFY_ROCE_CC_MODIFY_MASK_TOS_ECN); 1454 1455 if (bnxt_qplib_modify_cc(&rdev->qplib_res, &cc_param)) 1456 ibdev_err(&rdev->ibdev, "Failed to setup CC enable = %d\n", enable); 1457 } 1458 1459 /* 1460 * "Notifier chain callback can be invoked for the same chain from 1461 * different CPUs at the same time". 1462 * 1463 * For cases when the netdev is already present, our call to the 1464 * register_netdevice_notifier() will actually get the rtnl_lock() 1465 * before sending NETDEV_REGISTER and (if up) NETDEV_UP 1466 * events. 1467 * 1468 * But for cases when the netdev is not already present, the notifier 1469 * chain is subjected to be invoked from different CPUs simultaneously. 1470 * 1471 * This is protected by the netdev_mutex. 1472 */ 1473 static int bnxt_re_netdev_event(struct notifier_block *notifier, 1474 unsigned long event, void *ptr) 1475 { 1476 struct net_device *real_dev, *netdev = netdev_notifier_info_to_dev(ptr); 1477 struct bnxt_re_dev *rdev; 1478 1479 real_dev = rdma_vlan_dev_real_dev(netdev); 1480 if (!real_dev) 1481 real_dev = netdev; 1482 1483 if (real_dev != netdev) 1484 goto exit; 1485 1486 rdev = bnxt_re_from_netdev(real_dev); 1487 if (!rdev) 1488 return NOTIFY_DONE; 1489 1490 1491 switch (event) { 1492 case NETDEV_UP: 1493 case NETDEV_DOWN: 1494 case NETDEV_CHANGE: 1495 bnxt_re_dispatch_event(&rdev->ibdev, NULL, 1, 1496 netif_carrier_ok(real_dev) ? 1497 IB_EVENT_PORT_ACTIVE : 1498 IB_EVENT_PORT_ERR); 1499 break; 1500 default: 1501 break; 1502 } 1503 ib_device_put(&rdev->ibdev); 1504 exit: 1505 return NOTIFY_DONE; 1506 } 1507 1508 #define BNXT_ADEV_NAME "bnxt_en" 1509 1510 static void bnxt_re_remove(struct auxiliary_device *adev) 1511 { 1512 struct bnxt_re_dev *rdev = auxiliary_get_drvdata(adev); 1513 1514 if (!rdev) 1515 return; 1516 1517 mutex_lock(&bnxt_re_mutex); 1518 if (rdev->nb.notifier_call) { 1519 unregister_netdevice_notifier(&rdev->nb); 1520 rdev->nb.notifier_call = NULL; 1521 } else { 1522 /* If notifier is null, we should have already done a 1523 * clean up before coming here. 1524 */ 1525 goto skip_remove; 1526 } 1527 bnxt_re_setup_cc(rdev, false); 1528 ib_unregister_device(&rdev->ibdev); 1529 ib_dealloc_device(&rdev->ibdev); 1530 bnxt_re_dev_uninit(rdev); 1531 skip_remove: 1532 mutex_unlock(&bnxt_re_mutex); 1533 } 1534 1535 static int bnxt_re_probe(struct auxiliary_device *adev, 1536 const struct auxiliary_device_id *id) 1537 { 1538 struct bnxt_re_dev *rdev; 1539 int rc; 1540 1541 mutex_lock(&bnxt_re_mutex); 1542 rc = bnxt_re_add_device(adev, BNXT_QPLIB_WQE_MODE_STATIC); 1543 if (rc) { 1544 mutex_unlock(&bnxt_re_mutex); 1545 return rc; 1546 } 1547 1548 rdev = auxiliary_get_drvdata(adev); 1549 1550 rdev->nb.notifier_call = bnxt_re_netdev_event; 1551 rc = register_netdevice_notifier(&rdev->nb); 1552 if (rc) { 1553 rdev->nb.notifier_call = NULL; 1554 pr_err("%s: Cannot register to netdevice_notifier", 1555 ROCE_DRV_MODULE_NAME); 1556 goto err; 1557 } 1558 1559 bnxt_re_setup_cc(rdev, true); 1560 mutex_unlock(&bnxt_re_mutex); 1561 return 0; 1562 1563 err: 1564 mutex_unlock(&bnxt_re_mutex); 1565 bnxt_re_remove(adev); 1566 1567 return rc; 1568 } 1569 1570 static int bnxt_re_suspend(struct auxiliary_device *adev, pm_message_t state) 1571 { 1572 struct bnxt_re_dev *rdev = auxiliary_get_drvdata(adev); 1573 1574 if (!rdev) 1575 return 0; 1576 1577 mutex_lock(&bnxt_re_mutex); 1578 /* L2 driver may invoke this callback during device error/crash or device 1579 * reset. Current RoCE driver doesn't recover the device in case of 1580 * error. Handle the error by dispatching fatal events to all qps 1581 * ie. by calling bnxt_re_dev_stop and release the MSIx vectors as 1582 * L2 driver want to modify the MSIx table. 1583 */ 1584 1585 ibdev_info(&rdev->ibdev, "Handle device suspend call"); 1586 /* Check the current device state from bnxt_en_dev and move the 1587 * device to detached state if FW_FATAL_COND is set. 1588 * This prevents more commands to HW during clean-up, 1589 * in case the device is already in error. 1590 */ 1591 if (test_bit(BNXT_STATE_FW_FATAL_COND, &rdev->en_dev->en_state)) 1592 set_bit(ERR_DEVICE_DETACHED, &rdev->rcfw.cmdq.flags); 1593 1594 bnxt_re_dev_stop(rdev); 1595 bnxt_re_stop_irq(rdev); 1596 /* Move the device states to detached and avoid sending any more 1597 * commands to HW 1598 */ 1599 set_bit(BNXT_RE_FLAG_ERR_DEVICE_DETACHED, &rdev->flags); 1600 set_bit(ERR_DEVICE_DETACHED, &rdev->rcfw.cmdq.flags); 1601 wake_up_all(&rdev->rcfw.cmdq.waitq); 1602 mutex_unlock(&bnxt_re_mutex); 1603 1604 return 0; 1605 } 1606 1607 static int bnxt_re_resume(struct auxiliary_device *adev) 1608 { 1609 struct bnxt_re_dev *rdev = auxiliary_get_drvdata(adev); 1610 1611 if (!rdev) 1612 return 0; 1613 1614 mutex_lock(&bnxt_re_mutex); 1615 /* L2 driver may invoke this callback during device recovery, resume. 1616 * reset. Current RoCE driver doesn't recover the device in case of 1617 * error. Handle the error by dispatching fatal events to all qps 1618 * ie. by calling bnxt_re_dev_stop and release the MSIx vectors as 1619 * L2 driver want to modify the MSIx table. 1620 */ 1621 1622 ibdev_info(&rdev->ibdev, "Handle device resume call"); 1623 mutex_unlock(&bnxt_re_mutex); 1624 1625 return 0; 1626 } 1627 1628 static const struct auxiliary_device_id bnxt_re_id_table[] = { 1629 { .name = BNXT_ADEV_NAME ".rdma", }, 1630 {}, 1631 }; 1632 1633 MODULE_DEVICE_TABLE(auxiliary, bnxt_re_id_table); 1634 1635 static struct auxiliary_driver bnxt_re_driver = { 1636 .name = "rdma", 1637 .probe = bnxt_re_probe, 1638 .remove = bnxt_re_remove, 1639 .shutdown = bnxt_re_shutdown, 1640 .suspend = bnxt_re_suspend, 1641 .resume = bnxt_re_resume, 1642 .id_table = bnxt_re_id_table, 1643 }; 1644 1645 static int __init bnxt_re_mod_init(void) 1646 { 1647 int rc = 0; 1648 1649 pr_info("%s: %s", ROCE_DRV_MODULE_NAME, version); 1650 rc = auxiliary_driver_register(&bnxt_re_driver); 1651 if (rc) { 1652 pr_err("%s: Failed to register auxiliary driver\n", 1653 ROCE_DRV_MODULE_NAME); 1654 return rc; 1655 } 1656 return 0; 1657 } 1658 1659 static void __exit bnxt_re_mod_exit(void) 1660 { 1661 auxiliary_driver_unregister(&bnxt_re_driver); 1662 } 1663 1664 module_init(bnxt_re_mod_init); 1665 module_exit(bnxt_re_mod_exit); 1666