1 /*
2  * Broadcom NetXtreme-E RoCE driver.
3  *
4  * Copyright (c) 2016 - 2017, Broadcom. All rights reserved.  The term
5  * Broadcom refers to Broadcom Limited and/or its subsidiaries.
6  *
7  * This software is available to you under a choice of one of two
8  * licenses.  You may choose to be licensed under the terms of the GNU
9  * General Public License (GPL) Version 2, available from the file
10  * COPYING in the main directory of this source tree, or the
11  * BSD license below:
12  *
13  * Redistribution and use in source and binary forms, with or without
14  * modification, are permitted provided that the following conditions
15  * are met:
16  *
17  * 1. Redistributions of source code must retain the above copyright
18  *    notice, this list of conditions and the following disclaimer.
19  * 2. Redistributions in binary form must reproduce the above copyright
20  *    notice, this list of conditions and the following disclaimer in
21  *    the documentation and/or other materials provided with the
22  *    distribution.
23  *
24  * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS''
25  * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO,
26  * THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
27  * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS
28  * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
29  * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
30  * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR
31  * BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
32  * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE
33  * OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN
34  * IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
35  *
36  * Description: Main component of the bnxt_re driver
37  */
38 
39 #include <linux/module.h>
40 #include <linux/netdevice.h>
41 #include <linux/ethtool.h>
42 #include <linux/mutex.h>
43 #include <linux/list.h>
44 #include <linux/rculist.h>
45 #include <linux/spinlock.h>
46 #include <linux/pci.h>
47 #include <net/dcbnl.h>
48 #include <net/ipv6.h>
49 #include <net/addrconf.h>
50 #include <linux/if_ether.h>
51 #include <linux/auxiliary_bus.h>
52 
53 #include <rdma/ib_verbs.h>
54 #include <rdma/ib_user_verbs.h>
55 #include <rdma/ib_umem.h>
56 #include <rdma/ib_addr.h>
57 
58 #include "bnxt_ulp.h"
59 #include "roce_hsi.h"
60 #include "qplib_res.h"
61 #include "qplib_sp.h"
62 #include "qplib_fp.h"
63 #include "qplib_rcfw.h"
64 #include "bnxt_re.h"
65 #include "ib_verbs.h"
66 #include <rdma/bnxt_re-abi.h>
67 #include "bnxt.h"
68 #include "hw_counters.h"
69 
70 static char version[] =
71 		BNXT_RE_DESC "\n";
72 
73 MODULE_AUTHOR("Eddie Wai <eddie.wai@broadcom.com>");
74 MODULE_DESCRIPTION(BNXT_RE_DESC " Driver");
75 MODULE_LICENSE("Dual BSD/GPL");
76 
77 /* globals */
78 static DEFINE_MUTEX(bnxt_re_mutex);
79 
80 static void bnxt_re_stop_irq(void *handle);
81 static void bnxt_re_dev_stop(struct bnxt_re_dev *rdev);
82 static int bnxt_re_netdev_event(struct notifier_block *notifier,
83 				unsigned long event, void *ptr);
84 static struct bnxt_re_dev *bnxt_re_from_netdev(struct net_device *netdev);
85 static void bnxt_re_dev_uninit(struct bnxt_re_dev *rdev);
86 
87 static void bnxt_re_set_drv_mode(struct bnxt_re_dev *rdev, u8 mode)
88 {
89 	struct bnxt_qplib_chip_ctx *cctx;
90 
91 	cctx = rdev->chip_ctx;
92 	cctx->modes.wqe_mode = bnxt_qplib_is_chip_gen_p5(rdev->chip_ctx) ?
93 			       mode : BNXT_QPLIB_WQE_MODE_STATIC;
94 }
95 
96 static void bnxt_re_destroy_chip_ctx(struct bnxt_re_dev *rdev)
97 {
98 	struct bnxt_qplib_chip_ctx *chip_ctx;
99 
100 	if (!rdev->chip_ctx)
101 		return;
102 	chip_ctx = rdev->chip_ctx;
103 	rdev->chip_ctx = NULL;
104 	rdev->rcfw.res = NULL;
105 	rdev->qplib_res.cctx = NULL;
106 	rdev->qplib_res.pdev = NULL;
107 	rdev->qplib_res.netdev = NULL;
108 	kfree(chip_ctx);
109 }
110 
111 static int bnxt_re_setup_chip_ctx(struct bnxt_re_dev *rdev, u8 wqe_mode)
112 {
113 	struct bnxt_qplib_chip_ctx *chip_ctx;
114 	struct bnxt_en_dev *en_dev;
115 
116 	en_dev = rdev->en_dev;
117 
118 	chip_ctx = kzalloc(sizeof(*chip_ctx), GFP_KERNEL);
119 	if (!chip_ctx)
120 		return -ENOMEM;
121 	chip_ctx->chip_num = en_dev->chip_num;
122 	chip_ctx->hw_stats_size = en_dev->hw_ring_stats_size;
123 
124 	rdev->chip_ctx = chip_ctx;
125 	/* rest members to follow eventually */
126 
127 	rdev->qplib_res.cctx = rdev->chip_ctx;
128 	rdev->rcfw.res = &rdev->qplib_res;
129 	rdev->qplib_res.dattr = &rdev->dev_attr;
130 	rdev->qplib_res.is_vf = BNXT_EN_VF(en_dev);
131 
132 	bnxt_re_set_drv_mode(rdev, wqe_mode);
133 	if (bnxt_qplib_determine_atomics(en_dev->pdev))
134 		ibdev_info(&rdev->ibdev,
135 			   "platform doesn't support global atomics.");
136 	return 0;
137 }
138 
139 /* SR-IOV helper functions */
140 
141 static void bnxt_re_get_sriov_func_type(struct bnxt_re_dev *rdev)
142 {
143 	if (BNXT_EN_VF(rdev->en_dev))
144 		rdev->is_virtfn = 1;
145 }
146 
147 /* Set the maximum number of each resource that the driver actually wants
148  * to allocate. This may be up to the maximum number the firmware has
149  * reserved for the function. The driver may choose to allocate fewer
150  * resources than the firmware maximum.
151  */
152 static void bnxt_re_limit_pf_res(struct bnxt_re_dev *rdev)
153 {
154 	struct bnxt_qplib_dev_attr *attr;
155 	struct bnxt_qplib_ctx *ctx;
156 	int i;
157 
158 	attr = &rdev->dev_attr;
159 	ctx = &rdev->qplib_ctx;
160 
161 	ctx->qpc_count = min_t(u32, BNXT_RE_MAX_QPC_COUNT,
162 			       attr->max_qp);
163 	ctx->mrw_count = BNXT_RE_MAX_MRW_COUNT_256K;
164 	/* Use max_mr from fw since max_mrw does not get set */
165 	ctx->mrw_count = min_t(u32, ctx->mrw_count, attr->max_mr);
166 	ctx->srqc_count = min_t(u32, BNXT_RE_MAX_SRQC_COUNT,
167 				attr->max_srq);
168 	ctx->cq_count = min_t(u32, BNXT_RE_MAX_CQ_COUNT, attr->max_cq);
169 	if (!bnxt_qplib_is_chip_gen_p5(rdev->chip_ctx))
170 		for (i = 0; i < MAX_TQM_ALLOC_REQ; i++)
171 			rdev->qplib_ctx.tqm_ctx.qcount[i] =
172 			rdev->dev_attr.tqm_alloc_reqs[i];
173 }
174 
175 static void bnxt_re_limit_vf_res(struct bnxt_qplib_ctx *qplib_ctx, u32 num_vf)
176 {
177 	struct bnxt_qplib_vf_res *vf_res;
178 	u32 mrws = 0;
179 	u32 vf_pct;
180 	u32 nvfs;
181 
182 	vf_res = &qplib_ctx->vf_res;
183 	/*
184 	 * Reserve a set of resources for the PF. Divide the remaining
185 	 * resources among the VFs
186 	 */
187 	vf_pct = 100 - BNXT_RE_PCT_RSVD_FOR_PF;
188 	nvfs = num_vf;
189 	num_vf = 100 * num_vf;
190 	vf_res->max_qp_per_vf = (qplib_ctx->qpc_count * vf_pct) / num_vf;
191 	vf_res->max_srq_per_vf = (qplib_ctx->srqc_count * vf_pct) / num_vf;
192 	vf_res->max_cq_per_vf = (qplib_ctx->cq_count * vf_pct) / num_vf;
193 	/*
194 	 * The driver allows many more MRs than other resources. If the
195 	 * firmware does also, then reserve a fixed amount for the PF and
196 	 * divide the rest among VFs. VFs may use many MRs for NFS
197 	 * mounts, ISER, NVME applications, etc. If the firmware severely
198 	 * restricts the number of MRs, then let PF have half and divide
199 	 * the rest among VFs, as for the other resource types.
200 	 */
201 	if (qplib_ctx->mrw_count < BNXT_RE_MAX_MRW_COUNT_64K) {
202 		mrws = qplib_ctx->mrw_count * vf_pct;
203 		nvfs = num_vf;
204 	} else {
205 		mrws = qplib_ctx->mrw_count - BNXT_RE_RESVD_MR_FOR_PF;
206 	}
207 	vf_res->max_mrw_per_vf = (mrws / nvfs);
208 	vf_res->max_gid_per_vf = BNXT_RE_MAX_GID_PER_VF;
209 }
210 
211 static void bnxt_re_set_resource_limits(struct bnxt_re_dev *rdev)
212 {
213 	u32 num_vfs;
214 
215 	memset(&rdev->qplib_ctx.vf_res, 0, sizeof(struct bnxt_qplib_vf_res));
216 	bnxt_re_limit_pf_res(rdev);
217 
218 	num_vfs =  bnxt_qplib_is_chip_gen_p5(rdev->chip_ctx) ?
219 			BNXT_RE_GEN_P5_MAX_VF : rdev->num_vfs;
220 	if (num_vfs)
221 		bnxt_re_limit_vf_res(&rdev->qplib_ctx, num_vfs);
222 }
223 
224 static void bnxt_re_vf_res_config(struct bnxt_re_dev *rdev)
225 {
226 
227 	if (test_bit(BNXT_RE_FLAG_ERR_DEVICE_DETACHED, &rdev->flags))
228 		return;
229 	rdev->num_vfs = pci_sriov_get_totalvfs(rdev->en_dev->pdev);
230 	if (!bnxt_qplib_is_chip_gen_p5(rdev->chip_ctx)) {
231 		bnxt_re_set_resource_limits(rdev);
232 		bnxt_qplib_set_func_resources(&rdev->qplib_res, &rdev->rcfw,
233 					      &rdev->qplib_ctx);
234 	}
235 }
236 
237 static void bnxt_re_shutdown(struct auxiliary_device *adev)
238 {
239 	struct bnxt_re_dev *rdev = auxiliary_get_drvdata(adev);
240 
241 	if (!rdev)
242 		return;
243 	ib_unregister_device(&rdev->ibdev);
244 	bnxt_re_dev_uninit(rdev);
245 }
246 
247 static void bnxt_re_stop_irq(void *handle)
248 {
249 	struct bnxt_re_dev *rdev = (struct bnxt_re_dev *)handle;
250 	struct bnxt_qplib_rcfw *rcfw = &rdev->rcfw;
251 	struct bnxt_qplib_nq *nq;
252 	int indx;
253 
254 	for (indx = BNXT_RE_NQ_IDX; indx < rdev->num_msix; indx++) {
255 		nq = &rdev->nq[indx - 1];
256 		bnxt_qplib_nq_stop_irq(nq, false);
257 	}
258 
259 	bnxt_qplib_rcfw_stop_irq(rcfw, false);
260 }
261 
262 static void bnxt_re_start_irq(void *handle, struct bnxt_msix_entry *ent)
263 {
264 	struct bnxt_re_dev *rdev = (struct bnxt_re_dev *)handle;
265 	struct bnxt_msix_entry *msix_ent = rdev->en_dev->msix_entries;
266 	struct bnxt_qplib_rcfw *rcfw = &rdev->rcfw;
267 	struct bnxt_qplib_nq *nq;
268 	int indx, rc;
269 
270 	if (!ent) {
271 		/* Not setting the f/w timeout bit in rcfw.
272 		 * During the driver unload the first command
273 		 * to f/w will timeout and that will set the
274 		 * timeout bit.
275 		 */
276 		ibdev_err(&rdev->ibdev, "Failed to re-start IRQs\n");
277 		return;
278 	}
279 
280 	/* Vectors may change after restart, so update with new vectors
281 	 * in device sctructure.
282 	 */
283 	for (indx = 0; indx < rdev->num_msix; indx++)
284 		rdev->en_dev->msix_entries[indx].vector = ent[indx].vector;
285 
286 	bnxt_qplib_rcfw_start_irq(rcfw, msix_ent[BNXT_RE_AEQ_IDX].vector,
287 				  false);
288 	for (indx = BNXT_RE_NQ_IDX ; indx < rdev->num_msix; indx++) {
289 		nq = &rdev->nq[indx - 1];
290 		rc = bnxt_qplib_nq_start_irq(nq, indx - 1,
291 					     msix_ent[indx].vector, false);
292 		if (rc)
293 			ibdev_warn(&rdev->ibdev, "Failed to reinit NQ index %d\n",
294 				   indx - 1);
295 	}
296 }
297 
298 static struct bnxt_ulp_ops bnxt_re_ulp_ops = {
299 	.ulp_irq_stop = bnxt_re_stop_irq,
300 	.ulp_irq_restart = bnxt_re_start_irq
301 };
302 
303 /* RoCE -> Net driver */
304 
305 static int bnxt_re_register_netdev(struct bnxt_re_dev *rdev)
306 {
307 	struct bnxt_en_dev *en_dev;
308 	int rc = 0;
309 
310 	en_dev = rdev->en_dev;
311 
312 	rc = bnxt_register_dev(en_dev, &bnxt_re_ulp_ops, rdev);
313 	if (!rc)
314 		rdev->qplib_res.pdev = rdev->en_dev->pdev;
315 	return rc;
316 }
317 
318 static void bnxt_re_init_hwrm_hdr(struct bnxt_re_dev *rdev, struct input *hdr,
319 				  u16 opcd, u16 crid, u16 trid)
320 {
321 	hdr->req_type = cpu_to_le16(opcd);
322 	hdr->cmpl_ring = cpu_to_le16(crid);
323 	hdr->target_id = cpu_to_le16(trid);
324 }
325 
326 static void bnxt_re_fill_fw_msg(struct bnxt_fw_msg *fw_msg, void *msg,
327 				int msg_len, void *resp, int resp_max_len,
328 				int timeout)
329 {
330 	fw_msg->msg = msg;
331 	fw_msg->msg_len = msg_len;
332 	fw_msg->resp = resp;
333 	fw_msg->resp_max_len = resp_max_len;
334 	fw_msg->timeout = timeout;
335 }
336 
337 static int bnxt_re_net_ring_free(struct bnxt_re_dev *rdev,
338 				 u16 fw_ring_id, int type)
339 {
340 	struct bnxt_en_dev *en_dev;
341 	struct hwrm_ring_free_input req = {0};
342 	struct hwrm_ring_free_output resp;
343 	struct bnxt_fw_msg fw_msg;
344 	int rc = -EINVAL;
345 
346 	if (!rdev)
347 		return rc;
348 
349 	en_dev = rdev->en_dev;
350 
351 	if (!en_dev)
352 		return rc;
353 
354 	if (test_bit(BNXT_RE_FLAG_ERR_DEVICE_DETACHED, &rdev->flags))
355 		return 0;
356 
357 	memset(&fw_msg, 0, sizeof(fw_msg));
358 
359 	bnxt_re_init_hwrm_hdr(rdev, (void *)&req, HWRM_RING_FREE, -1, -1);
360 	req.ring_type = type;
361 	req.ring_id = cpu_to_le16(fw_ring_id);
362 	bnxt_re_fill_fw_msg(&fw_msg, (void *)&req, sizeof(req), (void *)&resp,
363 			    sizeof(resp), DFLT_HWRM_CMD_TIMEOUT);
364 	rc = bnxt_send_msg(en_dev, &fw_msg);
365 	if (rc)
366 		ibdev_err(&rdev->ibdev, "Failed to free HW ring:%d :%#x",
367 			  req.ring_id, rc);
368 	return rc;
369 }
370 
371 static int bnxt_re_net_ring_alloc(struct bnxt_re_dev *rdev,
372 				  struct bnxt_re_ring_attr *ring_attr,
373 				  u16 *fw_ring_id)
374 {
375 	struct bnxt_en_dev *en_dev = rdev->en_dev;
376 	struct hwrm_ring_alloc_input req = {0};
377 	struct hwrm_ring_alloc_output resp;
378 	struct bnxt_fw_msg fw_msg;
379 	int rc = -EINVAL;
380 
381 	if (!en_dev)
382 		return rc;
383 
384 	memset(&fw_msg, 0, sizeof(fw_msg));
385 	bnxt_re_init_hwrm_hdr(rdev, (void *)&req, HWRM_RING_ALLOC, -1, -1);
386 	req.enables = 0;
387 	req.page_tbl_addr =  cpu_to_le64(ring_attr->dma_arr[0]);
388 	if (ring_attr->pages > 1) {
389 		/* Page size is in log2 units */
390 		req.page_size = BNXT_PAGE_SHIFT;
391 		req.page_tbl_depth = 1;
392 	}
393 	req.fbo = 0;
394 	/* Association of ring index with doorbell index and MSIX number */
395 	req.logical_id = cpu_to_le16(ring_attr->lrid);
396 	req.length = cpu_to_le32(ring_attr->depth + 1);
397 	req.ring_type = ring_attr->type;
398 	req.int_mode = ring_attr->mode;
399 	bnxt_re_fill_fw_msg(&fw_msg, (void *)&req, sizeof(req), (void *)&resp,
400 			    sizeof(resp), DFLT_HWRM_CMD_TIMEOUT);
401 	rc = bnxt_send_msg(en_dev, &fw_msg);
402 	if (!rc)
403 		*fw_ring_id = le16_to_cpu(resp.ring_id);
404 
405 	return rc;
406 }
407 
408 static int bnxt_re_net_stats_ctx_free(struct bnxt_re_dev *rdev,
409 				      u32 fw_stats_ctx_id)
410 {
411 	struct bnxt_en_dev *en_dev = rdev->en_dev;
412 	struct hwrm_stat_ctx_free_input req = {};
413 	struct hwrm_stat_ctx_free_output resp = {};
414 	struct bnxt_fw_msg fw_msg;
415 	int rc = -EINVAL;
416 
417 	if (!en_dev)
418 		return rc;
419 
420 	if (test_bit(BNXT_RE_FLAG_ERR_DEVICE_DETACHED, &rdev->flags))
421 		return 0;
422 
423 	memset(&fw_msg, 0, sizeof(fw_msg));
424 
425 	bnxt_re_init_hwrm_hdr(rdev, (void *)&req, HWRM_STAT_CTX_FREE, -1, -1);
426 	req.stat_ctx_id = cpu_to_le32(fw_stats_ctx_id);
427 	bnxt_re_fill_fw_msg(&fw_msg, (void *)&req, sizeof(req), (void *)&resp,
428 			    sizeof(resp), DFLT_HWRM_CMD_TIMEOUT);
429 	rc = bnxt_send_msg(en_dev, &fw_msg);
430 	if (rc)
431 		ibdev_err(&rdev->ibdev, "Failed to free HW stats context %#x",
432 			  rc);
433 
434 	return rc;
435 }
436 
437 static int bnxt_re_net_stats_ctx_alloc(struct bnxt_re_dev *rdev,
438 				       dma_addr_t dma_map,
439 				       u32 *fw_stats_ctx_id)
440 {
441 	struct bnxt_qplib_chip_ctx *chip_ctx = rdev->chip_ctx;
442 	struct hwrm_stat_ctx_alloc_output resp = {0};
443 	struct hwrm_stat_ctx_alloc_input req = {0};
444 	struct bnxt_en_dev *en_dev = rdev->en_dev;
445 	struct bnxt_fw_msg fw_msg;
446 	int rc = -EINVAL;
447 
448 	*fw_stats_ctx_id = INVALID_STATS_CTX_ID;
449 
450 	if (!en_dev)
451 		return rc;
452 
453 	memset(&fw_msg, 0, sizeof(fw_msg));
454 
455 	bnxt_re_init_hwrm_hdr(rdev, (void *)&req, HWRM_STAT_CTX_ALLOC, -1, -1);
456 	req.update_period_ms = cpu_to_le32(1000);
457 	req.stats_dma_addr = cpu_to_le64(dma_map);
458 	req.stats_dma_length = cpu_to_le16(chip_ctx->hw_stats_size);
459 	req.stat_ctx_flags = STAT_CTX_ALLOC_REQ_STAT_CTX_FLAGS_ROCE;
460 	bnxt_re_fill_fw_msg(&fw_msg, (void *)&req, sizeof(req), (void *)&resp,
461 			    sizeof(resp), DFLT_HWRM_CMD_TIMEOUT);
462 	rc = bnxt_send_msg(en_dev, &fw_msg);
463 	if (!rc)
464 		*fw_stats_ctx_id = le32_to_cpu(resp.stat_ctx_id);
465 
466 	return rc;
467 }
468 
469 /* Device */
470 
471 static struct bnxt_re_dev *bnxt_re_from_netdev(struct net_device *netdev)
472 {
473 	struct ib_device *ibdev =
474 		ib_device_get_by_netdev(netdev, RDMA_DRIVER_BNXT_RE);
475 	if (!ibdev)
476 		return NULL;
477 
478 	return container_of(ibdev, struct bnxt_re_dev, ibdev);
479 }
480 
481 static ssize_t hw_rev_show(struct device *device, struct device_attribute *attr,
482 			   char *buf)
483 {
484 	struct bnxt_re_dev *rdev =
485 		rdma_device_to_drv_device(device, struct bnxt_re_dev, ibdev);
486 
487 	return sysfs_emit(buf, "0x%x\n", rdev->en_dev->pdev->vendor);
488 }
489 static DEVICE_ATTR_RO(hw_rev);
490 
491 static ssize_t hca_type_show(struct device *device,
492 			     struct device_attribute *attr, char *buf)
493 {
494 	struct bnxt_re_dev *rdev =
495 		rdma_device_to_drv_device(device, struct bnxt_re_dev, ibdev);
496 
497 	return sysfs_emit(buf, "%s\n", rdev->ibdev.node_desc);
498 }
499 static DEVICE_ATTR_RO(hca_type);
500 
501 static struct attribute *bnxt_re_attributes[] = {
502 	&dev_attr_hw_rev.attr,
503 	&dev_attr_hca_type.attr,
504 	NULL
505 };
506 
507 static const struct attribute_group bnxt_re_dev_attr_group = {
508 	.attrs = bnxt_re_attributes,
509 };
510 
511 static const struct ib_device_ops bnxt_re_dev_ops = {
512 	.owner = THIS_MODULE,
513 	.driver_id = RDMA_DRIVER_BNXT_RE,
514 	.uverbs_abi_ver = BNXT_RE_ABI_VERSION,
515 
516 	.add_gid = bnxt_re_add_gid,
517 	.alloc_hw_port_stats = bnxt_re_ib_alloc_hw_port_stats,
518 	.alloc_mr = bnxt_re_alloc_mr,
519 	.alloc_pd = bnxt_re_alloc_pd,
520 	.alloc_ucontext = bnxt_re_alloc_ucontext,
521 	.create_ah = bnxt_re_create_ah,
522 	.create_cq = bnxt_re_create_cq,
523 	.create_qp = bnxt_re_create_qp,
524 	.create_srq = bnxt_re_create_srq,
525 	.create_user_ah = bnxt_re_create_ah,
526 	.dealloc_pd = bnxt_re_dealloc_pd,
527 	.dealloc_ucontext = bnxt_re_dealloc_ucontext,
528 	.del_gid = bnxt_re_del_gid,
529 	.dereg_mr = bnxt_re_dereg_mr,
530 	.destroy_ah = bnxt_re_destroy_ah,
531 	.destroy_cq = bnxt_re_destroy_cq,
532 	.destroy_qp = bnxt_re_destroy_qp,
533 	.destroy_srq = bnxt_re_destroy_srq,
534 	.device_group = &bnxt_re_dev_attr_group,
535 	.get_dev_fw_str = bnxt_re_query_fw_str,
536 	.get_dma_mr = bnxt_re_get_dma_mr,
537 	.get_hw_stats = bnxt_re_ib_get_hw_stats,
538 	.get_link_layer = bnxt_re_get_link_layer,
539 	.get_port_immutable = bnxt_re_get_port_immutable,
540 	.map_mr_sg = bnxt_re_map_mr_sg,
541 	.mmap = bnxt_re_mmap,
542 	.modify_qp = bnxt_re_modify_qp,
543 	.modify_srq = bnxt_re_modify_srq,
544 	.poll_cq = bnxt_re_poll_cq,
545 	.post_recv = bnxt_re_post_recv,
546 	.post_send = bnxt_re_post_send,
547 	.post_srq_recv = bnxt_re_post_srq_recv,
548 	.query_ah = bnxt_re_query_ah,
549 	.query_device = bnxt_re_query_device,
550 	.query_pkey = bnxt_re_query_pkey,
551 	.query_port = bnxt_re_query_port,
552 	.query_qp = bnxt_re_query_qp,
553 	.query_srq = bnxt_re_query_srq,
554 	.reg_user_mr = bnxt_re_reg_user_mr,
555 	.req_notify_cq = bnxt_re_req_notify_cq,
556 	INIT_RDMA_OBJ_SIZE(ib_ah, bnxt_re_ah, ib_ah),
557 	INIT_RDMA_OBJ_SIZE(ib_cq, bnxt_re_cq, ib_cq),
558 	INIT_RDMA_OBJ_SIZE(ib_pd, bnxt_re_pd, ib_pd),
559 	INIT_RDMA_OBJ_SIZE(ib_qp, bnxt_re_qp, ib_qp),
560 	INIT_RDMA_OBJ_SIZE(ib_srq, bnxt_re_srq, ib_srq),
561 	INIT_RDMA_OBJ_SIZE(ib_ucontext, bnxt_re_ucontext, ib_uctx),
562 };
563 
564 static int bnxt_re_register_ib(struct bnxt_re_dev *rdev)
565 {
566 	struct ib_device *ibdev = &rdev->ibdev;
567 	int ret;
568 
569 	/* ib device init */
570 	ibdev->node_type = RDMA_NODE_IB_CA;
571 	strscpy(ibdev->node_desc, BNXT_RE_DESC " HCA",
572 		strlen(BNXT_RE_DESC) + 5);
573 	ibdev->phys_port_cnt = 1;
574 
575 	addrconf_addr_eui48((u8 *)&ibdev->node_guid, rdev->netdev->dev_addr);
576 
577 	ibdev->num_comp_vectors	= rdev->num_msix - 1;
578 	ibdev->dev.parent = &rdev->en_dev->pdev->dev;
579 	ibdev->local_dma_lkey = BNXT_QPLIB_RSVD_LKEY;
580 
581 	ib_set_device_ops(ibdev, &bnxt_re_dev_ops);
582 	ret = ib_device_set_netdev(&rdev->ibdev, rdev->netdev, 1);
583 	if (ret)
584 		return ret;
585 
586 	dma_set_max_seg_size(&rdev->en_dev->pdev->dev, UINT_MAX);
587 	return ib_register_device(ibdev, "bnxt_re%d", &rdev->en_dev->pdev->dev);
588 }
589 
590 static struct bnxt_re_dev *bnxt_re_dev_add(struct bnxt_aux_priv *aux_priv,
591 					   struct bnxt_en_dev *en_dev)
592 {
593 	struct bnxt_re_dev *rdev;
594 
595 	/* Allocate bnxt_re_dev instance here */
596 	rdev = ib_alloc_device(bnxt_re_dev, ibdev);
597 	if (!rdev) {
598 		ibdev_err(NULL, "%s: bnxt_re_dev allocation failure!",
599 			  ROCE_DRV_MODULE_NAME);
600 		return NULL;
601 	}
602 	/* Default values */
603 	rdev->nb.notifier_call = NULL;
604 	rdev->netdev = en_dev->net;
605 	rdev->en_dev = en_dev;
606 	rdev->id = rdev->en_dev->pdev->devfn;
607 	INIT_LIST_HEAD(&rdev->qp_list);
608 	mutex_init(&rdev->qp_lock);
609 	atomic_set(&rdev->qp_count, 0);
610 	atomic_set(&rdev->cq_count, 0);
611 	atomic_set(&rdev->srq_count, 0);
612 	atomic_set(&rdev->mr_count, 0);
613 	atomic_set(&rdev->mw_count, 0);
614 	atomic_set(&rdev->ah_count, 0);
615 	atomic_set(&rdev->pd_count, 0);
616 	rdev->cosq[0] = 0xFFFF;
617 	rdev->cosq[1] = 0xFFFF;
618 
619 	return rdev;
620 }
621 
622 static int bnxt_re_handle_unaffi_async_event(struct creq_func_event
623 					     *unaffi_async)
624 {
625 	switch (unaffi_async->event) {
626 	case CREQ_FUNC_EVENT_EVENT_TX_WQE_ERROR:
627 		break;
628 	case CREQ_FUNC_EVENT_EVENT_TX_DATA_ERROR:
629 		break;
630 	case CREQ_FUNC_EVENT_EVENT_RX_WQE_ERROR:
631 		break;
632 	case CREQ_FUNC_EVENT_EVENT_RX_DATA_ERROR:
633 		break;
634 	case CREQ_FUNC_EVENT_EVENT_CQ_ERROR:
635 		break;
636 	case CREQ_FUNC_EVENT_EVENT_TQM_ERROR:
637 		break;
638 	case CREQ_FUNC_EVENT_EVENT_CFCQ_ERROR:
639 		break;
640 	case CREQ_FUNC_EVENT_EVENT_CFCS_ERROR:
641 		break;
642 	case CREQ_FUNC_EVENT_EVENT_CFCC_ERROR:
643 		break;
644 	case CREQ_FUNC_EVENT_EVENT_CFCM_ERROR:
645 		break;
646 	case CREQ_FUNC_EVENT_EVENT_TIM_ERROR:
647 		break;
648 	default:
649 		return -EINVAL;
650 	}
651 	return 0;
652 }
653 
654 static int bnxt_re_handle_qp_async_event(struct creq_qp_event *qp_event,
655 					 struct bnxt_re_qp *qp)
656 {
657 	struct ib_event event;
658 	unsigned int flags;
659 
660 	if (qp->qplib_qp.state == CMDQ_MODIFY_QP_NEW_STATE_ERR &&
661 	    rdma_is_kernel_res(&qp->ib_qp.res)) {
662 		flags = bnxt_re_lock_cqs(qp);
663 		bnxt_qplib_add_flush_qp(&qp->qplib_qp);
664 		bnxt_re_unlock_cqs(qp, flags);
665 	}
666 
667 	memset(&event, 0, sizeof(event));
668 	if (qp->qplib_qp.srq) {
669 		event.device = &qp->rdev->ibdev;
670 		event.element.qp = &qp->ib_qp;
671 		event.event = IB_EVENT_QP_LAST_WQE_REACHED;
672 	}
673 
674 	if (event.device && qp->ib_qp.event_handler)
675 		qp->ib_qp.event_handler(&event, qp->ib_qp.qp_context);
676 
677 	return 0;
678 }
679 
680 static int bnxt_re_handle_affi_async_event(struct creq_qp_event *affi_async,
681 					   void *obj)
682 {
683 	int rc = 0;
684 	u8 event;
685 
686 	if (!obj)
687 		return rc; /* QP was already dead, still return success */
688 
689 	event = affi_async->event;
690 	if (event == CREQ_QP_EVENT_EVENT_QP_ERROR_NOTIFICATION) {
691 		struct bnxt_qplib_qp *lib_qp = obj;
692 		struct bnxt_re_qp *qp = container_of(lib_qp, struct bnxt_re_qp,
693 						     qplib_qp);
694 		rc = bnxt_re_handle_qp_async_event(affi_async, qp);
695 	}
696 	return rc;
697 }
698 
699 static int bnxt_re_aeq_handler(struct bnxt_qplib_rcfw *rcfw,
700 			       void *aeqe, void *obj)
701 {
702 	struct creq_qp_event *affi_async;
703 	struct creq_func_event *unaffi_async;
704 	u8 type;
705 	int rc;
706 
707 	type = ((struct creq_base *)aeqe)->type;
708 	if (type == CREQ_BASE_TYPE_FUNC_EVENT) {
709 		unaffi_async = aeqe;
710 		rc = bnxt_re_handle_unaffi_async_event(unaffi_async);
711 	} else {
712 		affi_async = aeqe;
713 		rc = bnxt_re_handle_affi_async_event(affi_async, obj);
714 	}
715 
716 	return rc;
717 }
718 
719 static int bnxt_re_srqn_handler(struct bnxt_qplib_nq *nq,
720 				struct bnxt_qplib_srq *handle, u8 event)
721 {
722 	struct bnxt_re_srq *srq = container_of(handle, struct bnxt_re_srq,
723 					       qplib_srq);
724 	struct ib_event ib_event;
725 
726 	ib_event.device = &srq->rdev->ibdev;
727 	ib_event.element.srq = &srq->ib_srq;
728 	if (event == NQ_SRQ_EVENT_EVENT_SRQ_THRESHOLD_EVENT)
729 		ib_event.event = IB_EVENT_SRQ_LIMIT_REACHED;
730 	else
731 		ib_event.event = IB_EVENT_SRQ_ERR;
732 
733 	if (srq->ib_srq.event_handler) {
734 		/* Lock event_handler? */
735 		(*srq->ib_srq.event_handler)(&ib_event,
736 					     srq->ib_srq.srq_context);
737 	}
738 	return 0;
739 }
740 
741 static int bnxt_re_cqn_handler(struct bnxt_qplib_nq *nq,
742 			       struct bnxt_qplib_cq *handle)
743 {
744 	struct bnxt_re_cq *cq = container_of(handle, struct bnxt_re_cq,
745 					     qplib_cq);
746 
747 	if (cq->ib_cq.comp_handler) {
748 		/* Lock comp_handler? */
749 		(*cq->ib_cq.comp_handler)(&cq->ib_cq, cq->ib_cq.cq_context);
750 	}
751 
752 	return 0;
753 }
754 
755 #define BNXT_RE_GEN_P5_PF_NQ_DB		0x10000
756 #define BNXT_RE_GEN_P5_VF_NQ_DB		0x4000
757 static u32 bnxt_re_get_nqdb_offset(struct bnxt_re_dev *rdev, u16 indx)
758 {
759 	return bnxt_qplib_is_chip_gen_p5(rdev->chip_ctx) ?
760 		(rdev->is_virtfn ? BNXT_RE_GEN_P5_VF_NQ_DB :
761 				   BNXT_RE_GEN_P5_PF_NQ_DB) :
762 				   rdev->en_dev->msix_entries[indx].db_offset;
763 }
764 
765 static void bnxt_re_cleanup_res(struct bnxt_re_dev *rdev)
766 {
767 	int i;
768 
769 	for (i = 1; i < rdev->num_msix; i++)
770 		bnxt_qplib_disable_nq(&rdev->nq[i - 1]);
771 
772 	if (rdev->qplib_res.rcfw)
773 		bnxt_qplib_cleanup_res(&rdev->qplib_res);
774 }
775 
776 static int bnxt_re_init_res(struct bnxt_re_dev *rdev)
777 {
778 	int num_vec_enabled = 0;
779 	int rc = 0, i;
780 	u32 db_offt;
781 
782 	bnxt_qplib_init_res(&rdev->qplib_res);
783 
784 	for (i = 1; i < rdev->num_msix ; i++) {
785 		db_offt = bnxt_re_get_nqdb_offset(rdev, i);
786 		rc = bnxt_qplib_enable_nq(rdev->en_dev->pdev, &rdev->nq[i - 1],
787 					  i - 1, rdev->en_dev->msix_entries[i].vector,
788 					  db_offt, &bnxt_re_cqn_handler,
789 					  &bnxt_re_srqn_handler);
790 		if (rc) {
791 			ibdev_err(&rdev->ibdev,
792 				  "Failed to enable NQ with rc = 0x%x", rc);
793 			goto fail;
794 		}
795 		num_vec_enabled++;
796 	}
797 	return 0;
798 fail:
799 	for (i = num_vec_enabled; i >= 0; i--)
800 		bnxt_qplib_disable_nq(&rdev->nq[i]);
801 	return rc;
802 }
803 
804 static void bnxt_re_free_nq_res(struct bnxt_re_dev *rdev)
805 {
806 	u8 type;
807 	int i;
808 
809 	for (i = 0; i < rdev->num_msix - 1; i++) {
810 		type = bnxt_qplib_get_ring_type(rdev->chip_ctx);
811 		bnxt_re_net_ring_free(rdev, rdev->nq[i].ring_id, type);
812 		bnxt_qplib_free_nq(&rdev->nq[i]);
813 		rdev->nq[i].res = NULL;
814 	}
815 }
816 
817 static void bnxt_re_free_res(struct bnxt_re_dev *rdev)
818 {
819 	bnxt_re_free_nq_res(rdev);
820 
821 	if (rdev->qplib_res.dpi_tbl.max) {
822 		bnxt_qplib_dealloc_dpi(&rdev->qplib_res,
823 				       &rdev->qplib_res.dpi_tbl,
824 				       &rdev->dpi_privileged);
825 	}
826 	if (rdev->qplib_res.rcfw) {
827 		bnxt_qplib_free_res(&rdev->qplib_res);
828 		rdev->qplib_res.rcfw = NULL;
829 	}
830 }
831 
832 static int bnxt_re_alloc_res(struct bnxt_re_dev *rdev)
833 {
834 	struct bnxt_re_ring_attr rattr = {};
835 	int num_vec_created = 0;
836 	int rc = 0, i;
837 	u8 type;
838 
839 	/* Configure and allocate resources for qplib */
840 	rdev->qplib_res.rcfw = &rdev->rcfw;
841 	rc = bnxt_qplib_get_dev_attr(&rdev->rcfw, &rdev->dev_attr,
842 				     rdev->is_virtfn);
843 	if (rc)
844 		goto fail;
845 
846 	rc = bnxt_qplib_alloc_res(&rdev->qplib_res, rdev->en_dev->pdev,
847 				  rdev->netdev, &rdev->dev_attr);
848 	if (rc)
849 		goto fail;
850 
851 	rc = bnxt_qplib_alloc_dpi(&rdev->qplib_res.dpi_tbl,
852 				  &rdev->dpi_privileged,
853 				  rdev);
854 	if (rc)
855 		goto dealloc_res;
856 
857 	for (i = 0; i < rdev->num_msix - 1; i++) {
858 		struct bnxt_qplib_nq *nq;
859 
860 		nq = &rdev->nq[i];
861 		nq->hwq.max_elements = BNXT_QPLIB_NQE_MAX_CNT;
862 		rc = bnxt_qplib_alloc_nq(&rdev->qplib_res, &rdev->nq[i]);
863 		if (rc) {
864 			ibdev_err(&rdev->ibdev, "Alloc Failed NQ%d rc:%#x",
865 				  i, rc);
866 			goto free_nq;
867 		}
868 		type = bnxt_qplib_get_ring_type(rdev->chip_ctx);
869 		rattr.dma_arr = nq->hwq.pbl[PBL_LVL_0].pg_map_arr;
870 		rattr.pages = nq->hwq.pbl[rdev->nq[i].hwq.level].pg_count;
871 		rattr.type = type;
872 		rattr.mode = RING_ALLOC_REQ_INT_MODE_MSIX;
873 		rattr.depth = BNXT_QPLIB_NQE_MAX_CNT - 1;
874 		rattr.lrid = rdev->en_dev->msix_entries[i + 1].ring_idx;
875 		rc = bnxt_re_net_ring_alloc(rdev, &rattr, &nq->ring_id);
876 		if (rc) {
877 			ibdev_err(&rdev->ibdev,
878 				  "Failed to allocate NQ fw id with rc = 0x%x",
879 				  rc);
880 			bnxt_qplib_free_nq(&rdev->nq[i]);
881 			goto free_nq;
882 		}
883 		num_vec_created++;
884 	}
885 	return 0;
886 free_nq:
887 	for (i = num_vec_created - 1; i >= 0; i--) {
888 		type = bnxt_qplib_get_ring_type(rdev->chip_ctx);
889 		bnxt_re_net_ring_free(rdev, rdev->nq[i].ring_id, type);
890 		bnxt_qplib_free_nq(&rdev->nq[i]);
891 	}
892 	bnxt_qplib_dealloc_dpi(&rdev->qplib_res,
893 			       &rdev->qplib_res.dpi_tbl,
894 			       &rdev->dpi_privileged);
895 dealloc_res:
896 	bnxt_qplib_free_res(&rdev->qplib_res);
897 
898 fail:
899 	rdev->qplib_res.rcfw = NULL;
900 	return rc;
901 }
902 
903 static void bnxt_re_dispatch_event(struct ib_device *ibdev, struct ib_qp *qp,
904 				   u8 port_num, enum ib_event_type event)
905 {
906 	struct ib_event ib_event;
907 
908 	ib_event.device = ibdev;
909 	if (qp) {
910 		ib_event.element.qp = qp;
911 		ib_event.event = event;
912 		if (qp->event_handler)
913 			qp->event_handler(&ib_event, qp->qp_context);
914 
915 	} else {
916 		ib_event.element.port_num = port_num;
917 		ib_event.event = event;
918 		ib_dispatch_event(&ib_event);
919 	}
920 }
921 
922 #define HWRM_QUEUE_PRI2COS_QCFG_INPUT_FLAGS_IVLAN      0x02
923 static int bnxt_re_query_hwrm_pri2cos(struct bnxt_re_dev *rdev, u8 dir,
924 				      u64 *cid_map)
925 {
926 	struct hwrm_queue_pri2cos_qcfg_input req = {0};
927 	struct hwrm_queue_pri2cos_qcfg_output resp;
928 	struct bnxt_en_dev *en_dev = rdev->en_dev;
929 	struct bnxt_fw_msg fw_msg;
930 	u32 flags = 0;
931 	u8 *qcfgmap, *tmp_map;
932 	int rc = 0, i;
933 
934 	if (!cid_map)
935 		return -EINVAL;
936 
937 	memset(&fw_msg, 0, sizeof(fw_msg));
938 	bnxt_re_init_hwrm_hdr(rdev, (void *)&req,
939 			      HWRM_QUEUE_PRI2COS_QCFG, -1, -1);
940 	flags |= (dir & 0x01);
941 	flags |= HWRM_QUEUE_PRI2COS_QCFG_INPUT_FLAGS_IVLAN;
942 	req.flags = cpu_to_le32(flags);
943 	req.port_id = en_dev->pf_port_id;
944 
945 	bnxt_re_fill_fw_msg(&fw_msg, (void *)&req, sizeof(req), (void *)&resp,
946 			    sizeof(resp), DFLT_HWRM_CMD_TIMEOUT);
947 	rc = bnxt_send_msg(en_dev, &fw_msg);
948 	if (rc)
949 		return rc;
950 
951 	if (resp.queue_cfg_info) {
952 		ibdev_warn(&rdev->ibdev,
953 			   "Asymmetric cos queue configuration detected");
954 		ibdev_warn(&rdev->ibdev,
955 			   " on device, QoS may not be fully functional\n");
956 	}
957 	qcfgmap = &resp.pri0_cos_queue_id;
958 	tmp_map = (u8 *)cid_map;
959 	for (i = 0; i < IEEE_8021QAZ_MAX_TCS; i++)
960 		tmp_map[i] = qcfgmap[i];
961 
962 	return rc;
963 }
964 
965 static bool bnxt_re_is_qp1_or_shadow_qp(struct bnxt_re_dev *rdev,
966 					struct bnxt_re_qp *qp)
967 {
968 	return (qp->ib_qp.qp_type == IB_QPT_GSI) ||
969 	       (qp == rdev->gsi_ctx.gsi_sqp);
970 }
971 
972 static void bnxt_re_dev_stop(struct bnxt_re_dev *rdev)
973 {
974 	int mask = IB_QP_STATE;
975 	struct ib_qp_attr qp_attr;
976 	struct bnxt_re_qp *qp;
977 
978 	qp_attr.qp_state = IB_QPS_ERR;
979 	mutex_lock(&rdev->qp_lock);
980 	list_for_each_entry(qp, &rdev->qp_list, list) {
981 		/* Modify the state of all QPs except QP1/Shadow QP */
982 		if (!bnxt_re_is_qp1_or_shadow_qp(rdev, qp)) {
983 			if (qp->qplib_qp.state !=
984 			    CMDQ_MODIFY_QP_NEW_STATE_RESET &&
985 			    qp->qplib_qp.state !=
986 			    CMDQ_MODIFY_QP_NEW_STATE_ERR) {
987 				bnxt_re_dispatch_event(&rdev->ibdev, &qp->ib_qp,
988 						       1, IB_EVENT_QP_FATAL);
989 				bnxt_re_modify_qp(&qp->ib_qp, &qp_attr, mask,
990 						  NULL);
991 			}
992 		}
993 	}
994 	mutex_unlock(&rdev->qp_lock);
995 }
996 
997 static int bnxt_re_update_gid(struct bnxt_re_dev *rdev)
998 {
999 	struct bnxt_qplib_sgid_tbl *sgid_tbl = &rdev->qplib_res.sgid_tbl;
1000 	struct bnxt_qplib_gid gid;
1001 	u16 gid_idx, index;
1002 	int rc = 0;
1003 
1004 	if (!ib_device_try_get(&rdev->ibdev))
1005 		return 0;
1006 
1007 	if (!sgid_tbl) {
1008 		ibdev_err(&rdev->ibdev, "QPLIB: SGID table not allocated");
1009 		rc = -EINVAL;
1010 		goto out;
1011 	}
1012 
1013 	for (index = 0; index < sgid_tbl->active; index++) {
1014 		gid_idx = sgid_tbl->hw_id[index];
1015 
1016 		if (!memcmp(&sgid_tbl->tbl[index], &bnxt_qplib_gid_zero,
1017 			    sizeof(bnxt_qplib_gid_zero)))
1018 			continue;
1019 		/* need to modify the VLAN enable setting of non VLAN GID only
1020 		 * as setting is done for VLAN GID while adding GID
1021 		 */
1022 		if (sgid_tbl->vlan[index])
1023 			continue;
1024 
1025 		memcpy(&gid, &sgid_tbl->tbl[index], sizeof(gid));
1026 
1027 		rc = bnxt_qplib_update_sgid(sgid_tbl, &gid, gid_idx,
1028 					    rdev->qplib_res.netdev->dev_addr);
1029 	}
1030 out:
1031 	ib_device_put(&rdev->ibdev);
1032 	return rc;
1033 }
1034 
1035 static u32 bnxt_re_get_priority_mask(struct bnxt_re_dev *rdev)
1036 {
1037 	u32 prio_map = 0, tmp_map = 0;
1038 	struct net_device *netdev;
1039 	struct dcb_app app;
1040 
1041 	netdev = rdev->netdev;
1042 
1043 	memset(&app, 0, sizeof(app));
1044 	app.selector = IEEE_8021QAZ_APP_SEL_ETHERTYPE;
1045 	app.protocol = ETH_P_IBOE;
1046 	tmp_map = dcb_ieee_getapp_mask(netdev, &app);
1047 	prio_map = tmp_map;
1048 
1049 	app.selector = IEEE_8021QAZ_APP_SEL_DGRAM;
1050 	app.protocol = ROCE_V2_UDP_DPORT;
1051 	tmp_map = dcb_ieee_getapp_mask(netdev, &app);
1052 	prio_map |= tmp_map;
1053 
1054 	return prio_map;
1055 }
1056 
1057 static void bnxt_re_parse_cid_map(u8 prio_map, u8 *cid_map, u16 *cosq)
1058 {
1059 	u16 prio;
1060 	u8 id;
1061 
1062 	for (prio = 0, id = 0; prio < 8; prio++) {
1063 		if (prio_map & (1 << prio)) {
1064 			cosq[id] = cid_map[prio];
1065 			id++;
1066 			if (id == 2) /* Max 2 tcs supported */
1067 				break;
1068 		}
1069 	}
1070 }
1071 
1072 static int bnxt_re_setup_qos(struct bnxt_re_dev *rdev)
1073 {
1074 	u8 prio_map = 0;
1075 	u64 cid_map;
1076 	int rc;
1077 
1078 	/* Get priority for roce */
1079 	prio_map = bnxt_re_get_priority_mask(rdev);
1080 
1081 	if (prio_map == rdev->cur_prio_map)
1082 		return 0;
1083 	rdev->cur_prio_map = prio_map;
1084 	/* Get cosq id for this priority */
1085 	rc = bnxt_re_query_hwrm_pri2cos(rdev, 0, &cid_map);
1086 	if (rc) {
1087 		ibdev_warn(&rdev->ibdev, "no cos for p_mask %x\n", prio_map);
1088 		return rc;
1089 	}
1090 	/* Parse CoS IDs for app priority */
1091 	bnxt_re_parse_cid_map(prio_map, (u8 *)&cid_map, rdev->cosq);
1092 
1093 	/* Config BONO. */
1094 	rc = bnxt_qplib_map_tc2cos(&rdev->qplib_res, rdev->cosq);
1095 	if (rc) {
1096 		ibdev_warn(&rdev->ibdev, "no tc for cos{%x, %x}\n",
1097 			   rdev->cosq[0], rdev->cosq[1]);
1098 		return rc;
1099 	}
1100 
1101 	/* Actual priorities are not programmed as they are already
1102 	 * done by L2 driver; just enable or disable priority vlan tagging
1103 	 */
1104 	if ((prio_map == 0 && rdev->qplib_res.prio) ||
1105 	    (prio_map != 0 && !rdev->qplib_res.prio)) {
1106 		rdev->qplib_res.prio = prio_map ? true : false;
1107 
1108 		bnxt_re_update_gid(rdev);
1109 	}
1110 
1111 	return 0;
1112 }
1113 
1114 static void bnxt_re_query_hwrm_intf_version(struct bnxt_re_dev *rdev)
1115 {
1116 	struct bnxt_en_dev *en_dev = rdev->en_dev;
1117 	struct hwrm_ver_get_output resp = {0};
1118 	struct hwrm_ver_get_input req = {0};
1119 	struct bnxt_fw_msg fw_msg;
1120 	int rc = 0;
1121 
1122 	memset(&fw_msg, 0, sizeof(fw_msg));
1123 	bnxt_re_init_hwrm_hdr(rdev, (void *)&req,
1124 			      HWRM_VER_GET, -1, -1);
1125 	req.hwrm_intf_maj = HWRM_VERSION_MAJOR;
1126 	req.hwrm_intf_min = HWRM_VERSION_MINOR;
1127 	req.hwrm_intf_upd = HWRM_VERSION_UPDATE;
1128 	bnxt_re_fill_fw_msg(&fw_msg, (void *)&req, sizeof(req), (void *)&resp,
1129 			    sizeof(resp), DFLT_HWRM_CMD_TIMEOUT);
1130 	rc = bnxt_send_msg(en_dev, &fw_msg);
1131 	if (rc) {
1132 		ibdev_err(&rdev->ibdev, "Failed to query HW version, rc = 0x%x",
1133 			  rc);
1134 		return;
1135 	}
1136 	rdev->qplib_ctx.hwrm_intf_ver =
1137 		(u64)le16_to_cpu(resp.hwrm_intf_major) << 48 |
1138 		(u64)le16_to_cpu(resp.hwrm_intf_minor) << 32 |
1139 		(u64)le16_to_cpu(resp.hwrm_intf_build) << 16 |
1140 		le16_to_cpu(resp.hwrm_intf_patch);
1141 }
1142 
1143 static int bnxt_re_ib_init(struct bnxt_re_dev *rdev)
1144 {
1145 	int rc = 0;
1146 	u32 event;
1147 
1148 	/* Register ib dev */
1149 	rc = bnxt_re_register_ib(rdev);
1150 	if (rc) {
1151 		pr_err("Failed to register with IB: %#x\n", rc);
1152 		return rc;
1153 	}
1154 	dev_info(rdev_to_dev(rdev), "Device registered with IB successfully");
1155 	ib_get_eth_speed(&rdev->ibdev, 1, &rdev->active_speed,
1156 			 &rdev->active_width);
1157 	set_bit(BNXT_RE_FLAG_ISSUE_ROCE_STATS, &rdev->flags);
1158 
1159 	event = netif_running(rdev->netdev) && netif_carrier_ok(rdev->netdev) ?
1160 		IB_EVENT_PORT_ACTIVE : IB_EVENT_PORT_ERR;
1161 
1162 	bnxt_re_dispatch_event(&rdev->ibdev, NULL, 1, event);
1163 
1164 	return rc;
1165 }
1166 
1167 static void bnxt_re_dev_uninit(struct bnxt_re_dev *rdev)
1168 {
1169 	u8 type;
1170 	int rc;
1171 
1172 	if (test_and_clear_bit(BNXT_RE_FLAG_QOS_WORK_REG, &rdev->flags))
1173 		cancel_delayed_work_sync(&rdev->worker);
1174 
1175 	if (test_and_clear_bit(BNXT_RE_FLAG_RESOURCES_INITIALIZED,
1176 			       &rdev->flags))
1177 		bnxt_re_cleanup_res(rdev);
1178 	if (test_and_clear_bit(BNXT_RE_FLAG_RESOURCES_ALLOCATED, &rdev->flags))
1179 		bnxt_re_free_res(rdev);
1180 
1181 	if (test_and_clear_bit(BNXT_RE_FLAG_RCFW_CHANNEL_EN, &rdev->flags)) {
1182 		rc = bnxt_qplib_deinit_rcfw(&rdev->rcfw);
1183 		if (rc)
1184 			ibdev_warn(&rdev->ibdev,
1185 				   "Failed to deinitialize RCFW: %#x", rc);
1186 		bnxt_re_net_stats_ctx_free(rdev, rdev->qplib_ctx.stats.fw_id);
1187 		bnxt_qplib_free_ctx(&rdev->qplib_res, &rdev->qplib_ctx);
1188 		bnxt_qplib_disable_rcfw_channel(&rdev->rcfw);
1189 		type = bnxt_qplib_get_ring_type(rdev->chip_ctx);
1190 		bnxt_re_net_ring_free(rdev, rdev->rcfw.creq.ring_id, type);
1191 		bnxt_qplib_free_rcfw_channel(&rdev->rcfw);
1192 	}
1193 	if (test_and_clear_bit(BNXT_RE_FLAG_GOT_MSIX, &rdev->flags))
1194 		rdev->num_msix = 0;
1195 
1196 	bnxt_re_destroy_chip_ctx(rdev);
1197 	if (test_and_clear_bit(BNXT_RE_FLAG_NETDEV_REGISTERED, &rdev->flags))
1198 		bnxt_unregister_dev(rdev->en_dev);
1199 }
1200 
1201 /* worker thread for polling periodic events. Now used for QoS programming*/
1202 static void bnxt_re_worker(struct work_struct *work)
1203 {
1204 	struct bnxt_re_dev *rdev = container_of(work, struct bnxt_re_dev,
1205 						worker.work);
1206 
1207 	bnxt_re_setup_qos(rdev);
1208 	schedule_delayed_work(&rdev->worker, msecs_to_jiffies(30000));
1209 }
1210 
1211 static int bnxt_re_dev_init(struct bnxt_re_dev *rdev, u8 wqe_mode)
1212 {
1213 	struct bnxt_qplib_creq_ctx *creq;
1214 	struct bnxt_re_ring_attr rattr;
1215 	u32 db_offt;
1216 	int vid;
1217 	u8 type;
1218 	int rc;
1219 
1220 	/* Registered a new RoCE device instance to netdev */
1221 	memset(&rattr, 0, sizeof(rattr));
1222 	rc = bnxt_re_register_netdev(rdev);
1223 	if (rc) {
1224 		ibdev_err(&rdev->ibdev,
1225 			  "Failed to register with netedev: %#x\n", rc);
1226 		return -EINVAL;
1227 	}
1228 	set_bit(BNXT_RE_FLAG_NETDEV_REGISTERED, &rdev->flags);
1229 
1230 	rc = bnxt_re_setup_chip_ctx(rdev, wqe_mode);
1231 	if (rc) {
1232 		ibdev_err(&rdev->ibdev, "Failed to get chip context\n");
1233 		return -EINVAL;
1234 	}
1235 
1236 	/* Check whether VF or PF */
1237 	bnxt_re_get_sriov_func_type(rdev);
1238 
1239 	if (!rdev->en_dev->ulp_tbl->msix_requested) {
1240 		ibdev_err(&rdev->ibdev,
1241 			  "Failed to get MSI-X vectors: %#x\n", rc);
1242 		rc = -EINVAL;
1243 		goto fail;
1244 	}
1245 	ibdev_dbg(&rdev->ibdev, "Got %d MSI-X vectors\n",
1246 		  rdev->en_dev->ulp_tbl->msix_requested);
1247 	rdev->num_msix = rdev->en_dev->ulp_tbl->msix_requested;
1248 	set_bit(BNXT_RE_FLAG_GOT_MSIX, &rdev->flags);
1249 
1250 	bnxt_re_query_hwrm_intf_version(rdev);
1251 
1252 	/* Establish RCFW Communication Channel to initialize the context
1253 	 * memory for the function and all child VFs
1254 	 */
1255 	rc = bnxt_qplib_alloc_rcfw_channel(&rdev->qplib_res, &rdev->rcfw,
1256 					   &rdev->qplib_ctx,
1257 					   BNXT_RE_MAX_QPC_COUNT);
1258 	if (rc) {
1259 		ibdev_err(&rdev->ibdev,
1260 			  "Failed to allocate RCFW Channel: %#x\n", rc);
1261 		goto fail;
1262 	}
1263 
1264 	type = bnxt_qplib_get_ring_type(rdev->chip_ctx);
1265 	creq = &rdev->rcfw.creq;
1266 	rattr.dma_arr = creq->hwq.pbl[PBL_LVL_0].pg_map_arr;
1267 	rattr.pages = creq->hwq.pbl[creq->hwq.level].pg_count;
1268 	rattr.type = type;
1269 	rattr.mode = RING_ALLOC_REQ_INT_MODE_MSIX;
1270 	rattr.depth = BNXT_QPLIB_CREQE_MAX_CNT - 1;
1271 	rattr.lrid = rdev->en_dev->msix_entries[BNXT_RE_AEQ_IDX].ring_idx;
1272 	rc = bnxt_re_net_ring_alloc(rdev, &rattr, &creq->ring_id);
1273 	if (rc) {
1274 		ibdev_err(&rdev->ibdev, "Failed to allocate CREQ: %#x\n", rc);
1275 		goto free_rcfw;
1276 	}
1277 	db_offt = bnxt_re_get_nqdb_offset(rdev, BNXT_RE_AEQ_IDX);
1278 	vid = rdev->en_dev->msix_entries[BNXT_RE_AEQ_IDX].vector;
1279 	rc = bnxt_qplib_enable_rcfw_channel(&rdev->rcfw,
1280 					    vid, db_offt, rdev->is_virtfn,
1281 					    &bnxt_re_aeq_handler);
1282 	if (rc) {
1283 		ibdev_err(&rdev->ibdev, "Failed to enable RCFW channel: %#x\n",
1284 			  rc);
1285 		goto free_ring;
1286 	}
1287 
1288 	rc = bnxt_qplib_get_dev_attr(&rdev->rcfw, &rdev->dev_attr,
1289 				     rdev->is_virtfn);
1290 	if (rc)
1291 		goto disable_rcfw;
1292 
1293 	bnxt_re_set_resource_limits(rdev);
1294 
1295 	rc = bnxt_qplib_alloc_ctx(&rdev->qplib_res, &rdev->qplib_ctx, 0,
1296 				  bnxt_qplib_is_chip_gen_p5(rdev->chip_ctx));
1297 	if (rc) {
1298 		ibdev_err(&rdev->ibdev,
1299 			  "Failed to allocate QPLIB context: %#x\n", rc);
1300 		goto disable_rcfw;
1301 	}
1302 	rc = bnxt_re_net_stats_ctx_alloc(rdev,
1303 					 rdev->qplib_ctx.stats.dma_map,
1304 					 &rdev->qplib_ctx.stats.fw_id);
1305 	if (rc) {
1306 		ibdev_err(&rdev->ibdev,
1307 			  "Failed to allocate stats context: %#x\n", rc);
1308 		goto free_ctx;
1309 	}
1310 
1311 	rc = bnxt_qplib_init_rcfw(&rdev->rcfw, &rdev->qplib_ctx,
1312 				  rdev->is_virtfn);
1313 	if (rc) {
1314 		ibdev_err(&rdev->ibdev,
1315 			  "Failed to initialize RCFW: %#x\n", rc);
1316 		goto free_sctx;
1317 	}
1318 	set_bit(BNXT_RE_FLAG_RCFW_CHANNEL_EN, &rdev->flags);
1319 
1320 	/* Resources based on the 'new' device caps */
1321 	rc = bnxt_re_alloc_res(rdev);
1322 	if (rc) {
1323 		ibdev_err(&rdev->ibdev,
1324 			  "Failed to allocate resources: %#x\n", rc);
1325 		goto fail;
1326 	}
1327 	set_bit(BNXT_RE_FLAG_RESOURCES_ALLOCATED, &rdev->flags);
1328 	rc = bnxt_re_init_res(rdev);
1329 	if (rc) {
1330 		ibdev_err(&rdev->ibdev,
1331 			  "Failed to initialize resources: %#x\n", rc);
1332 		goto fail;
1333 	}
1334 
1335 	set_bit(BNXT_RE_FLAG_RESOURCES_INITIALIZED, &rdev->flags);
1336 
1337 	if (!rdev->is_virtfn) {
1338 		rc = bnxt_re_setup_qos(rdev);
1339 		if (rc)
1340 			ibdev_info(&rdev->ibdev,
1341 				   "RoCE priority not yet configured\n");
1342 
1343 		INIT_DELAYED_WORK(&rdev->worker, bnxt_re_worker);
1344 		set_bit(BNXT_RE_FLAG_QOS_WORK_REG, &rdev->flags);
1345 		schedule_delayed_work(&rdev->worker, msecs_to_jiffies(30000));
1346 		/*
1347 		 * Use the total VF count since the actual VF count may not be
1348 		 * available at this point.
1349 		 */
1350 		bnxt_re_vf_res_config(rdev);
1351 	}
1352 
1353 	return 0;
1354 free_sctx:
1355 	bnxt_re_net_stats_ctx_free(rdev, rdev->qplib_ctx.stats.fw_id);
1356 free_ctx:
1357 	bnxt_qplib_free_ctx(&rdev->qplib_res, &rdev->qplib_ctx);
1358 disable_rcfw:
1359 	bnxt_qplib_disable_rcfw_channel(&rdev->rcfw);
1360 free_ring:
1361 	type = bnxt_qplib_get_ring_type(rdev->chip_ctx);
1362 	bnxt_re_net_ring_free(rdev, rdev->rcfw.creq.ring_id, type);
1363 free_rcfw:
1364 	bnxt_qplib_free_rcfw_channel(&rdev->rcfw);
1365 fail:
1366 	bnxt_re_dev_uninit(rdev);
1367 
1368 	return rc;
1369 }
1370 
1371 static int bnxt_re_add_device(struct auxiliary_device *adev, u8 wqe_mode)
1372 {
1373 	struct bnxt_aux_priv *aux_priv =
1374 		container_of(adev, struct bnxt_aux_priv, aux_dev);
1375 	struct bnxt_en_dev *en_dev;
1376 	struct bnxt_re_dev *rdev;
1377 	int rc = 0;
1378 
1379 	/* en_dev should never be NULL as long as adev and aux_dev are valid. */
1380 	en_dev = aux_priv->edev;
1381 
1382 	rdev = bnxt_re_dev_add(aux_priv, en_dev);
1383 	if (!rdev || !rdev_to_dev(rdev)) {
1384 		rc = -ENOMEM;
1385 		goto exit;
1386 	}
1387 
1388 	rc = bnxt_re_dev_init(rdev, wqe_mode);
1389 	if (rc)
1390 		goto re_dev_dealloc;
1391 
1392 	rc = bnxt_re_ib_init(rdev);
1393 	if (rc) {
1394 		pr_err("Failed to register with IB: %s",
1395 			aux_priv->aux_dev.name);
1396 		goto re_dev_uninit;
1397 	}
1398 	auxiliary_set_drvdata(adev, rdev);
1399 
1400 	return 0;
1401 
1402 re_dev_uninit:
1403 	bnxt_re_dev_uninit(rdev);
1404 re_dev_dealloc:
1405 	ib_dealloc_device(&rdev->ibdev);
1406 exit:
1407 	return rc;
1408 }
1409 
1410 /*
1411  * "Notifier chain callback can be invoked for the same chain from
1412  * different CPUs at the same time".
1413  *
1414  * For cases when the netdev is already present, our call to the
1415  * register_netdevice_notifier() will actually get the rtnl_lock()
1416  * before sending NETDEV_REGISTER and (if up) NETDEV_UP
1417  * events.
1418  *
1419  * But for cases when the netdev is not already present, the notifier
1420  * chain is subjected to be invoked from different CPUs simultaneously.
1421  *
1422  * This is protected by the netdev_mutex.
1423  */
1424 static int bnxt_re_netdev_event(struct notifier_block *notifier,
1425 				unsigned long event, void *ptr)
1426 {
1427 	struct net_device *real_dev, *netdev = netdev_notifier_info_to_dev(ptr);
1428 	struct bnxt_re_dev *rdev;
1429 
1430 	real_dev = rdma_vlan_dev_real_dev(netdev);
1431 	if (!real_dev)
1432 		real_dev = netdev;
1433 
1434 	if (real_dev != netdev)
1435 		goto exit;
1436 
1437 	rdev = bnxt_re_from_netdev(real_dev);
1438 	if (!rdev)
1439 		return NOTIFY_DONE;
1440 
1441 
1442 	switch (event) {
1443 	case NETDEV_UP:
1444 	case NETDEV_DOWN:
1445 	case NETDEV_CHANGE:
1446 		bnxt_re_dispatch_event(&rdev->ibdev, NULL, 1,
1447 					netif_carrier_ok(real_dev) ?
1448 					IB_EVENT_PORT_ACTIVE :
1449 					IB_EVENT_PORT_ERR);
1450 		break;
1451 	default:
1452 		break;
1453 	}
1454 	ib_device_put(&rdev->ibdev);
1455 exit:
1456 	return NOTIFY_DONE;
1457 }
1458 
1459 #define BNXT_ADEV_NAME "bnxt_en"
1460 
1461 static void bnxt_re_remove(struct auxiliary_device *adev)
1462 {
1463 	struct bnxt_re_dev *rdev = auxiliary_get_drvdata(adev);
1464 
1465 	if (!rdev)
1466 		return;
1467 
1468 	mutex_lock(&bnxt_re_mutex);
1469 	if (rdev->nb.notifier_call) {
1470 		unregister_netdevice_notifier(&rdev->nb);
1471 		rdev->nb.notifier_call = NULL;
1472 	} else {
1473 		/* If notifier is null, we should have already done a
1474 		 * clean up before coming here.
1475 		 */
1476 		goto skip_remove;
1477 	}
1478 
1479 	ib_unregister_device(&rdev->ibdev);
1480 	ib_dealloc_device(&rdev->ibdev);
1481 	bnxt_re_dev_uninit(rdev);
1482 skip_remove:
1483 	mutex_unlock(&bnxt_re_mutex);
1484 }
1485 
1486 static int bnxt_re_probe(struct auxiliary_device *adev,
1487 			 const struct auxiliary_device_id *id)
1488 {
1489 	struct bnxt_re_dev *rdev;
1490 	int rc;
1491 
1492 	mutex_lock(&bnxt_re_mutex);
1493 	rc = bnxt_re_add_device(adev, BNXT_QPLIB_WQE_MODE_STATIC);
1494 	if (rc) {
1495 		mutex_unlock(&bnxt_re_mutex);
1496 		return rc;
1497 	}
1498 
1499 	rdev = auxiliary_get_drvdata(adev);
1500 
1501 	rdev->nb.notifier_call = bnxt_re_netdev_event;
1502 	rc = register_netdevice_notifier(&rdev->nb);
1503 	if (rc) {
1504 		rdev->nb.notifier_call = NULL;
1505 		pr_err("%s: Cannot register to netdevice_notifier",
1506 		       ROCE_DRV_MODULE_NAME);
1507 		goto err;
1508 	}
1509 
1510 	mutex_unlock(&bnxt_re_mutex);
1511 	return 0;
1512 
1513 err:
1514 	mutex_unlock(&bnxt_re_mutex);
1515 	bnxt_re_remove(adev);
1516 
1517 	return rc;
1518 }
1519 
1520 static int bnxt_re_suspend(struct auxiliary_device *adev, pm_message_t state)
1521 {
1522 	struct bnxt_re_dev *rdev = auxiliary_get_drvdata(adev);
1523 
1524 	if (!rdev)
1525 		return 0;
1526 
1527 	mutex_lock(&bnxt_re_mutex);
1528 	/* L2 driver may invoke this callback during device error/crash or device
1529 	 * reset. Current RoCE driver doesn't recover the device in case of
1530 	 * error. Handle the error by dispatching fatal events to all qps
1531 	 * ie. by calling bnxt_re_dev_stop and release the MSIx vectors as
1532 	 * L2 driver want to modify the MSIx table.
1533 	 */
1534 
1535 	ibdev_info(&rdev->ibdev, "Handle device suspend call");
1536 	/* Check the current device state from bnxt_en_dev and move the
1537 	 * device to detached state if FW_FATAL_COND is set.
1538 	 * This prevents more commands to HW during clean-up,
1539 	 * in case the device is already in error.
1540 	 */
1541 	if (test_bit(BNXT_STATE_FW_FATAL_COND, &rdev->en_dev->en_state))
1542 		set_bit(ERR_DEVICE_DETACHED, &rdev->rcfw.cmdq.flags);
1543 
1544 	bnxt_re_dev_stop(rdev);
1545 	bnxt_re_stop_irq(rdev);
1546 	/* Move the device states to detached and  avoid sending any more
1547 	 * commands to HW
1548 	 */
1549 	set_bit(BNXT_RE_FLAG_ERR_DEVICE_DETACHED, &rdev->flags);
1550 	set_bit(ERR_DEVICE_DETACHED, &rdev->rcfw.cmdq.flags);
1551 	mutex_unlock(&bnxt_re_mutex);
1552 
1553 	return 0;
1554 }
1555 
1556 static int bnxt_re_resume(struct auxiliary_device *adev)
1557 {
1558 	struct bnxt_re_dev *rdev = auxiliary_get_drvdata(adev);
1559 
1560 	if (!rdev)
1561 		return 0;
1562 
1563 	mutex_lock(&bnxt_re_mutex);
1564 	/* L2 driver may invoke this callback during device recovery, resume.
1565 	 * reset. Current RoCE driver doesn't recover the device in case of
1566 	 * error. Handle the error by dispatching fatal events to all qps
1567 	 * ie. by calling bnxt_re_dev_stop and release the MSIx vectors as
1568 	 * L2 driver want to modify the MSIx table.
1569 	 */
1570 
1571 	ibdev_info(&rdev->ibdev, "Handle device resume call");
1572 	mutex_unlock(&bnxt_re_mutex);
1573 
1574 	return 0;
1575 }
1576 
1577 static const struct auxiliary_device_id bnxt_re_id_table[] = {
1578 	{ .name = BNXT_ADEV_NAME ".rdma", },
1579 	{},
1580 };
1581 
1582 MODULE_DEVICE_TABLE(auxiliary, bnxt_re_id_table);
1583 
1584 static struct auxiliary_driver bnxt_re_driver = {
1585 	.name = "rdma",
1586 	.probe = bnxt_re_probe,
1587 	.remove = bnxt_re_remove,
1588 	.shutdown = bnxt_re_shutdown,
1589 	.suspend = bnxt_re_suspend,
1590 	.resume = bnxt_re_resume,
1591 	.id_table = bnxt_re_id_table,
1592 };
1593 
1594 static int __init bnxt_re_mod_init(void)
1595 {
1596 	int rc = 0;
1597 
1598 	pr_info("%s: %s", ROCE_DRV_MODULE_NAME, version);
1599 	rc = auxiliary_driver_register(&bnxt_re_driver);
1600 	if (rc) {
1601 		pr_err("%s: Failed to register auxiliary driver\n",
1602 			ROCE_DRV_MODULE_NAME);
1603 		return rc;
1604 	}
1605 	return 0;
1606 }
1607 
1608 static void __exit bnxt_re_mod_exit(void)
1609 {
1610 	auxiliary_driver_unregister(&bnxt_re_driver);
1611 }
1612 
1613 module_init(bnxt_re_mod_init);
1614 module_exit(bnxt_re_mod_exit);
1615