1 /* 2 * Broadcom NetXtreme-E RoCE driver. 3 * 4 * Copyright (c) 2016 - 2017, Broadcom. All rights reserved. The term 5 * Broadcom refers to Broadcom Limited and/or its subsidiaries. 6 * 7 * This software is available to you under a choice of one of two 8 * licenses. You may choose to be licensed under the terms of the GNU 9 * General Public License (GPL) Version 2, available from the file 10 * COPYING in the main directory of this source tree, or the 11 * BSD license below: 12 * 13 * Redistribution and use in source and binary forms, with or without 14 * modification, are permitted provided that the following conditions 15 * are met: 16 * 17 * 1. Redistributions of source code must retain the above copyright 18 * notice, this list of conditions and the following disclaimer. 19 * 2. Redistributions in binary form must reproduce the above copyright 20 * notice, this list of conditions and the following disclaimer in 21 * the documentation and/or other materials provided with the 22 * distribution. 23 * 24 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' 25 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, 26 * THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR 27 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS 28 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 29 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 30 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR 31 * BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, 32 * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE 33 * OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN 34 * IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 35 * 36 * Description: IB Verbs interpreter 37 */ 38 39 #include <linux/interrupt.h> 40 #include <linux/types.h> 41 #include <linux/pci.h> 42 #include <linux/netdevice.h> 43 #include <linux/if_ether.h> 44 #include <net/addrconf.h> 45 46 #include <rdma/ib_verbs.h> 47 #include <rdma/ib_user_verbs.h> 48 #include <rdma/ib_umem.h> 49 #include <rdma/ib_addr.h> 50 #include <rdma/ib_mad.h> 51 #include <rdma/ib_cache.h> 52 #include <rdma/uverbs_ioctl.h> 53 54 #include "bnxt_ulp.h" 55 56 #include "roce_hsi.h" 57 #include "qplib_res.h" 58 #include "qplib_sp.h" 59 #include "qplib_fp.h" 60 #include "qplib_rcfw.h" 61 62 #include "bnxt_re.h" 63 #include "ib_verbs.h" 64 65 #include <rdma/uverbs_types.h> 66 #include <rdma/uverbs_std_types.h> 67 68 #include <rdma/ib_user_ioctl_cmds.h> 69 70 #define UVERBS_MODULE_NAME bnxt_re 71 #include <rdma/uverbs_named_ioctl.h> 72 73 #include <rdma/bnxt_re-abi.h> 74 75 static int __from_ib_access_flags(int iflags) 76 { 77 int qflags = 0; 78 79 if (iflags & IB_ACCESS_LOCAL_WRITE) 80 qflags |= BNXT_QPLIB_ACCESS_LOCAL_WRITE; 81 if (iflags & IB_ACCESS_REMOTE_READ) 82 qflags |= BNXT_QPLIB_ACCESS_REMOTE_READ; 83 if (iflags & IB_ACCESS_REMOTE_WRITE) 84 qflags |= BNXT_QPLIB_ACCESS_REMOTE_WRITE; 85 if (iflags & IB_ACCESS_REMOTE_ATOMIC) 86 qflags |= BNXT_QPLIB_ACCESS_REMOTE_ATOMIC; 87 if (iflags & IB_ACCESS_MW_BIND) 88 qflags |= BNXT_QPLIB_ACCESS_MW_BIND; 89 if (iflags & IB_ZERO_BASED) 90 qflags |= BNXT_QPLIB_ACCESS_ZERO_BASED; 91 if (iflags & IB_ACCESS_ON_DEMAND) 92 qflags |= BNXT_QPLIB_ACCESS_ON_DEMAND; 93 return qflags; 94 }; 95 96 static enum ib_access_flags __to_ib_access_flags(int qflags) 97 { 98 enum ib_access_flags iflags = 0; 99 100 if (qflags & BNXT_QPLIB_ACCESS_LOCAL_WRITE) 101 iflags |= IB_ACCESS_LOCAL_WRITE; 102 if (qflags & BNXT_QPLIB_ACCESS_REMOTE_WRITE) 103 iflags |= IB_ACCESS_REMOTE_WRITE; 104 if (qflags & BNXT_QPLIB_ACCESS_REMOTE_READ) 105 iflags |= IB_ACCESS_REMOTE_READ; 106 if (qflags & BNXT_QPLIB_ACCESS_REMOTE_ATOMIC) 107 iflags |= IB_ACCESS_REMOTE_ATOMIC; 108 if (qflags & BNXT_QPLIB_ACCESS_MW_BIND) 109 iflags |= IB_ACCESS_MW_BIND; 110 if (qflags & BNXT_QPLIB_ACCESS_ZERO_BASED) 111 iflags |= IB_ZERO_BASED; 112 if (qflags & BNXT_QPLIB_ACCESS_ON_DEMAND) 113 iflags |= IB_ACCESS_ON_DEMAND; 114 return iflags; 115 }; 116 117 static int bnxt_re_build_sgl(struct ib_sge *ib_sg_list, 118 struct bnxt_qplib_sge *sg_list, int num) 119 { 120 int i, total = 0; 121 122 for (i = 0; i < num; i++) { 123 sg_list[i].addr = ib_sg_list[i].addr; 124 sg_list[i].lkey = ib_sg_list[i].lkey; 125 sg_list[i].size = ib_sg_list[i].length; 126 total += sg_list[i].size; 127 } 128 return total; 129 } 130 131 /* Device */ 132 int bnxt_re_query_device(struct ib_device *ibdev, 133 struct ib_device_attr *ib_attr, 134 struct ib_udata *udata) 135 { 136 struct bnxt_re_dev *rdev = to_bnxt_re_dev(ibdev, ibdev); 137 struct bnxt_qplib_dev_attr *dev_attr = &rdev->dev_attr; 138 139 memset(ib_attr, 0, sizeof(*ib_attr)); 140 memcpy(&ib_attr->fw_ver, dev_attr->fw_ver, 141 min(sizeof(dev_attr->fw_ver), 142 sizeof(ib_attr->fw_ver))); 143 addrconf_addr_eui48((u8 *)&ib_attr->sys_image_guid, 144 rdev->netdev->dev_addr); 145 ib_attr->max_mr_size = BNXT_RE_MAX_MR_SIZE; 146 ib_attr->page_size_cap = BNXT_RE_PAGE_SIZE_SUPPORTED; 147 148 ib_attr->vendor_id = rdev->en_dev->pdev->vendor; 149 ib_attr->vendor_part_id = rdev->en_dev->pdev->device; 150 ib_attr->hw_ver = rdev->en_dev->pdev->revision; 151 ib_attr->max_qp = dev_attr->max_qp; 152 ib_attr->max_qp_wr = dev_attr->max_qp_wqes; 153 ib_attr->device_cap_flags = 154 IB_DEVICE_CURR_QP_STATE_MOD 155 | IB_DEVICE_RC_RNR_NAK_GEN 156 | IB_DEVICE_SHUTDOWN_PORT 157 | IB_DEVICE_SYS_IMAGE_GUID 158 | IB_DEVICE_RESIZE_MAX_WR 159 | IB_DEVICE_PORT_ACTIVE_EVENT 160 | IB_DEVICE_N_NOTIFY_CQ 161 | IB_DEVICE_MEM_WINDOW 162 | IB_DEVICE_MEM_WINDOW_TYPE_2B 163 | IB_DEVICE_MEM_MGT_EXTENSIONS; 164 ib_attr->kernel_cap_flags = IBK_LOCAL_DMA_LKEY; 165 ib_attr->max_send_sge = dev_attr->max_qp_sges; 166 ib_attr->max_recv_sge = dev_attr->max_qp_sges; 167 ib_attr->max_sge_rd = dev_attr->max_qp_sges; 168 ib_attr->max_cq = dev_attr->max_cq; 169 ib_attr->max_cqe = dev_attr->max_cq_wqes; 170 ib_attr->max_mr = dev_attr->max_mr; 171 ib_attr->max_pd = dev_attr->max_pd; 172 ib_attr->max_qp_rd_atom = dev_attr->max_qp_rd_atom; 173 ib_attr->max_qp_init_rd_atom = dev_attr->max_qp_init_rd_atom; 174 ib_attr->atomic_cap = IB_ATOMIC_NONE; 175 ib_attr->masked_atomic_cap = IB_ATOMIC_NONE; 176 if (dev_attr->is_atomic) { 177 ib_attr->atomic_cap = IB_ATOMIC_GLOB; 178 ib_attr->masked_atomic_cap = IB_ATOMIC_GLOB; 179 } 180 181 ib_attr->max_ee_rd_atom = 0; 182 ib_attr->max_res_rd_atom = 0; 183 ib_attr->max_ee_init_rd_atom = 0; 184 ib_attr->max_ee = 0; 185 ib_attr->max_rdd = 0; 186 ib_attr->max_mw = dev_attr->max_mw; 187 ib_attr->max_raw_ipv6_qp = 0; 188 ib_attr->max_raw_ethy_qp = dev_attr->max_raw_ethy_qp; 189 ib_attr->max_mcast_grp = 0; 190 ib_attr->max_mcast_qp_attach = 0; 191 ib_attr->max_total_mcast_qp_attach = 0; 192 ib_attr->max_ah = dev_attr->max_ah; 193 194 ib_attr->max_srq = dev_attr->max_srq; 195 ib_attr->max_srq_wr = dev_attr->max_srq_wqes; 196 ib_attr->max_srq_sge = dev_attr->max_srq_sges; 197 198 ib_attr->max_fast_reg_page_list_len = MAX_PBL_LVL_1_PGS; 199 200 ib_attr->max_pkeys = 1; 201 ib_attr->local_ca_ack_delay = BNXT_RE_DEFAULT_ACK_DELAY; 202 return 0; 203 } 204 205 /* Port */ 206 int bnxt_re_query_port(struct ib_device *ibdev, u32 port_num, 207 struct ib_port_attr *port_attr) 208 { 209 struct bnxt_re_dev *rdev = to_bnxt_re_dev(ibdev, ibdev); 210 struct bnxt_qplib_dev_attr *dev_attr = &rdev->dev_attr; 211 int rc; 212 213 memset(port_attr, 0, sizeof(*port_attr)); 214 215 if (netif_running(rdev->netdev) && netif_carrier_ok(rdev->netdev)) { 216 port_attr->state = IB_PORT_ACTIVE; 217 port_attr->phys_state = IB_PORT_PHYS_STATE_LINK_UP; 218 } else { 219 port_attr->state = IB_PORT_DOWN; 220 port_attr->phys_state = IB_PORT_PHYS_STATE_DISABLED; 221 } 222 port_attr->max_mtu = IB_MTU_4096; 223 port_attr->active_mtu = iboe_get_mtu(rdev->netdev->mtu); 224 port_attr->gid_tbl_len = dev_attr->max_sgid; 225 port_attr->port_cap_flags = IB_PORT_CM_SUP | IB_PORT_REINIT_SUP | 226 IB_PORT_DEVICE_MGMT_SUP | 227 IB_PORT_VENDOR_CLASS_SUP; 228 port_attr->ip_gids = true; 229 230 port_attr->max_msg_sz = (u32)BNXT_RE_MAX_MR_SIZE_LOW; 231 port_attr->bad_pkey_cntr = 0; 232 port_attr->qkey_viol_cntr = 0; 233 port_attr->pkey_tbl_len = dev_attr->max_pkey; 234 port_attr->lid = 0; 235 port_attr->sm_lid = 0; 236 port_attr->lmc = 0; 237 port_attr->max_vl_num = 4; 238 port_attr->sm_sl = 0; 239 port_attr->subnet_timeout = 0; 240 port_attr->init_type_reply = 0; 241 rc = ib_get_eth_speed(&rdev->ibdev, port_num, &port_attr->active_speed, 242 &port_attr->active_width); 243 244 return rc; 245 } 246 247 int bnxt_re_get_port_immutable(struct ib_device *ibdev, u32 port_num, 248 struct ib_port_immutable *immutable) 249 { 250 struct ib_port_attr port_attr; 251 252 if (bnxt_re_query_port(ibdev, port_num, &port_attr)) 253 return -EINVAL; 254 255 immutable->pkey_tbl_len = port_attr.pkey_tbl_len; 256 immutable->gid_tbl_len = port_attr.gid_tbl_len; 257 immutable->core_cap_flags = RDMA_CORE_PORT_IBA_ROCE; 258 immutable->core_cap_flags |= RDMA_CORE_CAP_PROT_ROCE_UDP_ENCAP; 259 immutable->max_mad_size = IB_MGMT_MAD_SIZE; 260 return 0; 261 } 262 263 void bnxt_re_query_fw_str(struct ib_device *ibdev, char *str) 264 { 265 struct bnxt_re_dev *rdev = to_bnxt_re_dev(ibdev, ibdev); 266 267 snprintf(str, IB_FW_VERSION_NAME_MAX, "%d.%d.%d.%d", 268 rdev->dev_attr.fw_ver[0], rdev->dev_attr.fw_ver[1], 269 rdev->dev_attr.fw_ver[2], rdev->dev_attr.fw_ver[3]); 270 } 271 272 int bnxt_re_query_pkey(struct ib_device *ibdev, u32 port_num, 273 u16 index, u16 *pkey) 274 { 275 if (index > 0) 276 return -EINVAL; 277 278 *pkey = IB_DEFAULT_PKEY_FULL; 279 280 return 0; 281 } 282 283 int bnxt_re_query_gid(struct ib_device *ibdev, u32 port_num, 284 int index, union ib_gid *gid) 285 { 286 struct bnxt_re_dev *rdev = to_bnxt_re_dev(ibdev, ibdev); 287 int rc; 288 289 /* Ignore port_num */ 290 memset(gid, 0, sizeof(*gid)); 291 rc = bnxt_qplib_get_sgid(&rdev->qplib_res, 292 &rdev->qplib_res.sgid_tbl, index, 293 (struct bnxt_qplib_gid *)gid); 294 return rc; 295 } 296 297 int bnxt_re_del_gid(const struct ib_gid_attr *attr, void **context) 298 { 299 int rc = 0; 300 struct bnxt_re_gid_ctx *ctx, **ctx_tbl; 301 struct bnxt_re_dev *rdev = to_bnxt_re_dev(attr->device, ibdev); 302 struct bnxt_qplib_sgid_tbl *sgid_tbl = &rdev->qplib_res.sgid_tbl; 303 struct bnxt_qplib_gid *gid_to_del; 304 u16 vlan_id = 0xFFFF; 305 306 /* Delete the entry from the hardware */ 307 ctx = *context; 308 if (!ctx) 309 return -EINVAL; 310 311 if (sgid_tbl && sgid_tbl->active) { 312 if (ctx->idx >= sgid_tbl->max) 313 return -EINVAL; 314 gid_to_del = &sgid_tbl->tbl[ctx->idx].gid; 315 vlan_id = sgid_tbl->tbl[ctx->idx].vlan_id; 316 /* DEL_GID is called in WQ context(netdevice_event_work_handler) 317 * or via the ib_unregister_device path. In the former case QP1 318 * may not be destroyed yet, in which case just return as FW 319 * needs that entry to be present and will fail it's deletion. 320 * We could get invoked again after QP1 is destroyed OR get an 321 * ADD_GID call with a different GID value for the same index 322 * where we issue MODIFY_GID cmd to update the GID entry -- TBD 323 */ 324 if (ctx->idx == 0 && 325 rdma_link_local_addr((struct in6_addr *)gid_to_del) && 326 ctx->refcnt == 1 && rdev->gsi_ctx.gsi_sqp) { 327 ibdev_dbg(&rdev->ibdev, 328 "Trying to delete GID0 while QP1 is alive\n"); 329 return -EFAULT; 330 } 331 ctx->refcnt--; 332 if (!ctx->refcnt) { 333 rc = bnxt_qplib_del_sgid(sgid_tbl, gid_to_del, 334 vlan_id, true); 335 if (rc) { 336 ibdev_err(&rdev->ibdev, 337 "Failed to remove GID: %#x", rc); 338 } else { 339 ctx_tbl = sgid_tbl->ctx; 340 ctx_tbl[ctx->idx] = NULL; 341 kfree(ctx); 342 } 343 } 344 } else { 345 return -EINVAL; 346 } 347 return rc; 348 } 349 350 int bnxt_re_add_gid(const struct ib_gid_attr *attr, void **context) 351 { 352 int rc; 353 u32 tbl_idx = 0; 354 u16 vlan_id = 0xFFFF; 355 struct bnxt_re_gid_ctx *ctx, **ctx_tbl; 356 struct bnxt_re_dev *rdev = to_bnxt_re_dev(attr->device, ibdev); 357 struct bnxt_qplib_sgid_tbl *sgid_tbl = &rdev->qplib_res.sgid_tbl; 358 359 rc = rdma_read_gid_l2_fields(attr, &vlan_id, NULL); 360 if (rc) 361 return rc; 362 363 rc = bnxt_qplib_add_sgid(sgid_tbl, (struct bnxt_qplib_gid *)&attr->gid, 364 rdev->qplib_res.netdev->dev_addr, 365 vlan_id, true, &tbl_idx); 366 if (rc == -EALREADY) { 367 ctx_tbl = sgid_tbl->ctx; 368 ctx_tbl[tbl_idx]->refcnt++; 369 *context = ctx_tbl[tbl_idx]; 370 return 0; 371 } 372 373 if (rc < 0) { 374 ibdev_err(&rdev->ibdev, "Failed to add GID: %#x", rc); 375 return rc; 376 } 377 378 ctx = kmalloc(sizeof(*ctx), GFP_KERNEL); 379 if (!ctx) 380 return -ENOMEM; 381 ctx_tbl = sgid_tbl->ctx; 382 ctx->idx = tbl_idx; 383 ctx->refcnt = 1; 384 ctx_tbl[tbl_idx] = ctx; 385 *context = ctx; 386 387 return rc; 388 } 389 390 enum rdma_link_layer bnxt_re_get_link_layer(struct ib_device *ibdev, 391 u32 port_num) 392 { 393 return IB_LINK_LAYER_ETHERNET; 394 } 395 396 #define BNXT_RE_FENCE_PBL_SIZE DIV_ROUND_UP(BNXT_RE_FENCE_BYTES, PAGE_SIZE) 397 398 static void bnxt_re_create_fence_wqe(struct bnxt_re_pd *pd) 399 { 400 struct bnxt_re_fence_data *fence = &pd->fence; 401 struct ib_mr *ib_mr = &fence->mr->ib_mr; 402 struct bnxt_qplib_swqe *wqe = &fence->bind_wqe; 403 struct bnxt_re_dev *rdev = pd->rdev; 404 405 if (bnxt_qplib_is_chip_gen_p5_p7(rdev->chip_ctx)) 406 return; 407 408 memset(wqe, 0, sizeof(*wqe)); 409 wqe->type = BNXT_QPLIB_SWQE_TYPE_BIND_MW; 410 wqe->wr_id = BNXT_QPLIB_FENCE_WRID; 411 wqe->flags |= BNXT_QPLIB_SWQE_FLAGS_SIGNAL_COMP; 412 wqe->flags |= BNXT_QPLIB_SWQE_FLAGS_UC_FENCE; 413 wqe->bind.zero_based = false; 414 wqe->bind.parent_l_key = ib_mr->lkey; 415 wqe->bind.va = (u64)(unsigned long)fence->va; 416 wqe->bind.length = fence->size; 417 wqe->bind.access_cntl = __from_ib_access_flags(IB_ACCESS_REMOTE_READ); 418 wqe->bind.mw_type = SQ_BIND_MW_TYPE_TYPE1; 419 420 /* Save the initial rkey in fence structure for now; 421 * wqe->bind.r_key will be set at (re)bind time. 422 */ 423 fence->bind_rkey = ib_inc_rkey(fence->mw->rkey); 424 } 425 426 static int bnxt_re_bind_fence_mw(struct bnxt_qplib_qp *qplib_qp) 427 { 428 struct bnxt_re_qp *qp = container_of(qplib_qp, struct bnxt_re_qp, 429 qplib_qp); 430 struct ib_pd *ib_pd = qp->ib_qp.pd; 431 struct bnxt_re_pd *pd = container_of(ib_pd, struct bnxt_re_pd, ib_pd); 432 struct bnxt_re_fence_data *fence = &pd->fence; 433 struct bnxt_qplib_swqe *fence_wqe = &fence->bind_wqe; 434 struct bnxt_qplib_swqe wqe; 435 int rc; 436 437 memcpy(&wqe, fence_wqe, sizeof(wqe)); 438 wqe.bind.r_key = fence->bind_rkey; 439 fence->bind_rkey = ib_inc_rkey(fence->bind_rkey); 440 441 ibdev_dbg(&qp->rdev->ibdev, 442 "Posting bind fence-WQE: rkey: %#x QP: %d PD: %p\n", 443 wqe.bind.r_key, qp->qplib_qp.id, pd); 444 rc = bnxt_qplib_post_send(&qp->qplib_qp, &wqe); 445 if (rc) { 446 ibdev_err(&qp->rdev->ibdev, "Failed to bind fence-WQE\n"); 447 return rc; 448 } 449 bnxt_qplib_post_send_db(&qp->qplib_qp); 450 451 return rc; 452 } 453 454 static void bnxt_re_destroy_fence_mr(struct bnxt_re_pd *pd) 455 { 456 struct bnxt_re_fence_data *fence = &pd->fence; 457 struct bnxt_re_dev *rdev = pd->rdev; 458 struct device *dev = &rdev->en_dev->pdev->dev; 459 struct bnxt_re_mr *mr = fence->mr; 460 461 if (bnxt_qplib_is_chip_gen_p5_p7(rdev->chip_ctx)) 462 return; 463 464 if (fence->mw) { 465 bnxt_re_dealloc_mw(fence->mw); 466 fence->mw = NULL; 467 } 468 if (mr) { 469 if (mr->ib_mr.rkey) 470 bnxt_qplib_dereg_mrw(&rdev->qplib_res, &mr->qplib_mr, 471 true); 472 if (mr->ib_mr.lkey) 473 bnxt_qplib_free_mrw(&rdev->qplib_res, &mr->qplib_mr); 474 kfree(mr); 475 fence->mr = NULL; 476 } 477 if (fence->dma_addr) { 478 dma_unmap_single(dev, fence->dma_addr, BNXT_RE_FENCE_BYTES, 479 DMA_BIDIRECTIONAL); 480 fence->dma_addr = 0; 481 } 482 } 483 484 static int bnxt_re_create_fence_mr(struct bnxt_re_pd *pd) 485 { 486 int mr_access_flags = IB_ACCESS_LOCAL_WRITE | IB_ACCESS_MW_BIND; 487 struct bnxt_re_fence_data *fence = &pd->fence; 488 struct bnxt_re_dev *rdev = pd->rdev; 489 struct device *dev = &rdev->en_dev->pdev->dev; 490 struct bnxt_re_mr *mr = NULL; 491 dma_addr_t dma_addr = 0; 492 struct ib_mw *mw; 493 int rc; 494 495 if (bnxt_qplib_is_chip_gen_p5_p7(rdev->chip_ctx)) 496 return 0; 497 498 dma_addr = dma_map_single(dev, fence->va, BNXT_RE_FENCE_BYTES, 499 DMA_BIDIRECTIONAL); 500 rc = dma_mapping_error(dev, dma_addr); 501 if (rc) { 502 ibdev_err(&rdev->ibdev, "Failed to dma-map fence-MR-mem\n"); 503 rc = -EIO; 504 fence->dma_addr = 0; 505 goto fail; 506 } 507 fence->dma_addr = dma_addr; 508 509 /* Allocate a MR */ 510 mr = kzalloc(sizeof(*mr), GFP_KERNEL); 511 if (!mr) { 512 rc = -ENOMEM; 513 goto fail; 514 } 515 fence->mr = mr; 516 mr->rdev = rdev; 517 mr->qplib_mr.pd = &pd->qplib_pd; 518 mr->qplib_mr.type = CMDQ_ALLOCATE_MRW_MRW_FLAGS_PMR; 519 mr->qplib_mr.flags = __from_ib_access_flags(mr_access_flags); 520 rc = bnxt_qplib_alloc_mrw(&rdev->qplib_res, &mr->qplib_mr); 521 if (rc) { 522 ibdev_err(&rdev->ibdev, "Failed to alloc fence-HW-MR\n"); 523 goto fail; 524 } 525 526 /* Register MR */ 527 mr->ib_mr.lkey = mr->qplib_mr.lkey; 528 mr->qplib_mr.va = (u64)(unsigned long)fence->va; 529 mr->qplib_mr.total_size = BNXT_RE_FENCE_BYTES; 530 rc = bnxt_qplib_reg_mr(&rdev->qplib_res, &mr->qplib_mr, NULL, 531 BNXT_RE_FENCE_PBL_SIZE, PAGE_SIZE); 532 if (rc) { 533 ibdev_err(&rdev->ibdev, "Failed to register fence-MR\n"); 534 goto fail; 535 } 536 mr->ib_mr.rkey = mr->qplib_mr.rkey; 537 538 /* Create a fence MW only for kernel consumers */ 539 mw = bnxt_re_alloc_mw(&pd->ib_pd, IB_MW_TYPE_1, NULL); 540 if (IS_ERR(mw)) { 541 ibdev_err(&rdev->ibdev, 542 "Failed to create fence-MW for PD: %p\n", pd); 543 rc = PTR_ERR(mw); 544 goto fail; 545 } 546 fence->mw = mw; 547 548 bnxt_re_create_fence_wqe(pd); 549 return 0; 550 551 fail: 552 bnxt_re_destroy_fence_mr(pd); 553 return rc; 554 } 555 556 static struct bnxt_re_user_mmap_entry* 557 bnxt_re_mmap_entry_insert(struct bnxt_re_ucontext *uctx, u64 mem_offset, 558 enum bnxt_re_mmap_flag mmap_flag, u64 *offset) 559 { 560 struct bnxt_re_user_mmap_entry *entry; 561 int ret; 562 563 entry = kzalloc(sizeof(*entry), GFP_KERNEL); 564 if (!entry) 565 return NULL; 566 567 entry->mem_offset = mem_offset; 568 entry->mmap_flag = mmap_flag; 569 entry->uctx = uctx; 570 571 switch (mmap_flag) { 572 case BNXT_RE_MMAP_SH_PAGE: 573 ret = rdma_user_mmap_entry_insert_exact(&uctx->ib_uctx, 574 &entry->rdma_entry, PAGE_SIZE, 0); 575 break; 576 case BNXT_RE_MMAP_UC_DB: 577 case BNXT_RE_MMAP_WC_DB: 578 case BNXT_RE_MMAP_DBR_BAR: 579 case BNXT_RE_MMAP_DBR_PAGE: 580 ret = rdma_user_mmap_entry_insert(&uctx->ib_uctx, 581 &entry->rdma_entry, PAGE_SIZE); 582 break; 583 default: 584 ret = -EINVAL; 585 break; 586 } 587 588 if (ret) { 589 kfree(entry); 590 return NULL; 591 } 592 if (offset) 593 *offset = rdma_user_mmap_get_offset(&entry->rdma_entry); 594 595 return entry; 596 } 597 598 /* Protection Domains */ 599 int bnxt_re_dealloc_pd(struct ib_pd *ib_pd, struct ib_udata *udata) 600 { 601 struct bnxt_re_pd *pd = container_of(ib_pd, struct bnxt_re_pd, ib_pd); 602 struct bnxt_re_dev *rdev = pd->rdev; 603 604 if (udata) { 605 rdma_user_mmap_entry_remove(pd->pd_db_mmap); 606 pd->pd_db_mmap = NULL; 607 } 608 609 bnxt_re_destroy_fence_mr(pd); 610 611 if (pd->qplib_pd.id) { 612 if (!bnxt_qplib_dealloc_pd(&rdev->qplib_res, 613 &rdev->qplib_res.pd_tbl, 614 &pd->qplib_pd)) 615 atomic_dec(&rdev->stats.res.pd_count); 616 } 617 return 0; 618 } 619 620 int bnxt_re_alloc_pd(struct ib_pd *ibpd, struct ib_udata *udata) 621 { 622 struct ib_device *ibdev = ibpd->device; 623 struct bnxt_re_dev *rdev = to_bnxt_re_dev(ibdev, ibdev); 624 struct bnxt_re_ucontext *ucntx = rdma_udata_to_drv_context( 625 udata, struct bnxt_re_ucontext, ib_uctx); 626 struct bnxt_re_pd *pd = container_of(ibpd, struct bnxt_re_pd, ib_pd); 627 struct bnxt_re_user_mmap_entry *entry = NULL; 628 u32 active_pds; 629 int rc = 0; 630 631 pd->rdev = rdev; 632 if (bnxt_qplib_alloc_pd(&rdev->qplib_res, &pd->qplib_pd)) { 633 ibdev_err(&rdev->ibdev, "Failed to allocate HW PD"); 634 rc = -ENOMEM; 635 goto fail; 636 } 637 638 if (udata) { 639 struct bnxt_re_pd_resp resp = {}; 640 641 if (!ucntx->dpi.dbr) { 642 /* Allocate DPI in alloc_pd to avoid failing of 643 * ibv_devinfo and family of application when DPIs 644 * are depleted. 645 */ 646 if (bnxt_qplib_alloc_dpi(&rdev->qplib_res, 647 &ucntx->dpi, ucntx, BNXT_QPLIB_DPI_TYPE_UC)) { 648 rc = -ENOMEM; 649 goto dbfail; 650 } 651 } 652 653 resp.pdid = pd->qplib_pd.id; 654 /* Still allow mapping this DBR to the new user PD. */ 655 resp.dpi = ucntx->dpi.dpi; 656 657 entry = bnxt_re_mmap_entry_insert(ucntx, (u64)ucntx->dpi.umdbr, 658 BNXT_RE_MMAP_UC_DB, &resp.dbr); 659 660 if (!entry) { 661 rc = -ENOMEM; 662 goto dbfail; 663 } 664 665 pd->pd_db_mmap = &entry->rdma_entry; 666 667 rc = ib_copy_to_udata(udata, &resp, min(sizeof(resp), udata->outlen)); 668 if (rc) { 669 rdma_user_mmap_entry_remove(pd->pd_db_mmap); 670 rc = -EFAULT; 671 goto dbfail; 672 } 673 } 674 675 if (!udata) 676 if (bnxt_re_create_fence_mr(pd)) 677 ibdev_warn(&rdev->ibdev, 678 "Failed to create Fence-MR\n"); 679 active_pds = atomic_inc_return(&rdev->stats.res.pd_count); 680 if (active_pds > rdev->stats.res.pd_watermark) 681 rdev->stats.res.pd_watermark = active_pds; 682 683 return 0; 684 dbfail: 685 bnxt_qplib_dealloc_pd(&rdev->qplib_res, &rdev->qplib_res.pd_tbl, 686 &pd->qplib_pd); 687 fail: 688 return rc; 689 } 690 691 /* Address Handles */ 692 int bnxt_re_destroy_ah(struct ib_ah *ib_ah, u32 flags) 693 { 694 struct bnxt_re_ah *ah = container_of(ib_ah, struct bnxt_re_ah, ib_ah); 695 struct bnxt_re_dev *rdev = ah->rdev; 696 bool block = true; 697 int rc; 698 699 block = !(flags & RDMA_DESTROY_AH_SLEEPABLE); 700 rc = bnxt_qplib_destroy_ah(&rdev->qplib_res, &ah->qplib_ah, block); 701 if (BNXT_RE_CHECK_RC(rc)) { 702 if (rc == -ETIMEDOUT) 703 rc = 0; 704 else 705 goto fail; 706 } 707 atomic_dec(&rdev->stats.res.ah_count); 708 fail: 709 return rc; 710 } 711 712 static u8 bnxt_re_stack_to_dev_nw_type(enum rdma_network_type ntype) 713 { 714 u8 nw_type; 715 716 switch (ntype) { 717 case RDMA_NETWORK_IPV4: 718 nw_type = CMDQ_CREATE_AH_TYPE_V2IPV4; 719 break; 720 case RDMA_NETWORK_IPV6: 721 nw_type = CMDQ_CREATE_AH_TYPE_V2IPV6; 722 break; 723 default: 724 nw_type = CMDQ_CREATE_AH_TYPE_V1; 725 break; 726 } 727 return nw_type; 728 } 729 730 int bnxt_re_create_ah(struct ib_ah *ib_ah, struct rdma_ah_init_attr *init_attr, 731 struct ib_udata *udata) 732 { 733 struct ib_pd *ib_pd = ib_ah->pd; 734 struct bnxt_re_pd *pd = container_of(ib_pd, struct bnxt_re_pd, ib_pd); 735 struct rdma_ah_attr *ah_attr = init_attr->ah_attr; 736 const struct ib_global_route *grh = rdma_ah_read_grh(ah_attr); 737 struct bnxt_re_dev *rdev = pd->rdev; 738 const struct ib_gid_attr *sgid_attr; 739 struct bnxt_re_gid_ctx *ctx; 740 struct bnxt_re_ah *ah = container_of(ib_ah, struct bnxt_re_ah, ib_ah); 741 u32 active_ahs; 742 u8 nw_type; 743 int rc; 744 745 if (!(rdma_ah_get_ah_flags(ah_attr) & IB_AH_GRH)) { 746 ibdev_err(&rdev->ibdev, "Failed to alloc AH: GRH not set"); 747 return -EINVAL; 748 } 749 750 ah->rdev = rdev; 751 ah->qplib_ah.pd = &pd->qplib_pd; 752 753 /* Supply the configuration for the HW */ 754 memcpy(ah->qplib_ah.dgid.data, grh->dgid.raw, 755 sizeof(union ib_gid)); 756 sgid_attr = grh->sgid_attr; 757 /* Get the HW context of the GID. The reference 758 * of GID table entry is already taken by the caller. 759 */ 760 ctx = rdma_read_gid_hw_context(sgid_attr); 761 ah->qplib_ah.sgid_index = ctx->idx; 762 ah->qplib_ah.host_sgid_index = grh->sgid_index; 763 ah->qplib_ah.traffic_class = grh->traffic_class; 764 ah->qplib_ah.flow_label = grh->flow_label; 765 ah->qplib_ah.hop_limit = grh->hop_limit; 766 ah->qplib_ah.sl = rdma_ah_get_sl(ah_attr); 767 768 /* Get network header type for this GID */ 769 nw_type = rdma_gid_attr_network_type(sgid_attr); 770 ah->qplib_ah.nw_type = bnxt_re_stack_to_dev_nw_type(nw_type); 771 772 memcpy(ah->qplib_ah.dmac, ah_attr->roce.dmac, ETH_ALEN); 773 rc = bnxt_qplib_create_ah(&rdev->qplib_res, &ah->qplib_ah, 774 !(init_attr->flags & 775 RDMA_CREATE_AH_SLEEPABLE)); 776 if (rc) { 777 ibdev_err(&rdev->ibdev, "Failed to allocate HW AH"); 778 return rc; 779 } 780 781 /* Write AVID to shared page. */ 782 if (udata) { 783 struct bnxt_re_ucontext *uctx = rdma_udata_to_drv_context( 784 udata, struct bnxt_re_ucontext, ib_uctx); 785 unsigned long flag; 786 u32 *wrptr; 787 788 spin_lock_irqsave(&uctx->sh_lock, flag); 789 wrptr = (u32 *)(uctx->shpg + BNXT_RE_AVID_OFFT); 790 *wrptr = ah->qplib_ah.id; 791 wmb(); /* make sure cache is updated. */ 792 spin_unlock_irqrestore(&uctx->sh_lock, flag); 793 } 794 active_ahs = atomic_inc_return(&rdev->stats.res.ah_count); 795 if (active_ahs > rdev->stats.res.ah_watermark) 796 rdev->stats.res.ah_watermark = active_ahs; 797 798 return 0; 799 } 800 801 int bnxt_re_query_ah(struct ib_ah *ib_ah, struct rdma_ah_attr *ah_attr) 802 { 803 struct bnxt_re_ah *ah = container_of(ib_ah, struct bnxt_re_ah, ib_ah); 804 805 ah_attr->type = ib_ah->type; 806 rdma_ah_set_sl(ah_attr, ah->qplib_ah.sl); 807 memcpy(ah_attr->roce.dmac, ah->qplib_ah.dmac, ETH_ALEN); 808 rdma_ah_set_grh(ah_attr, NULL, 0, 809 ah->qplib_ah.host_sgid_index, 810 0, ah->qplib_ah.traffic_class); 811 rdma_ah_set_dgid_raw(ah_attr, ah->qplib_ah.dgid.data); 812 rdma_ah_set_port_num(ah_attr, 1); 813 rdma_ah_set_static_rate(ah_attr, 0); 814 return 0; 815 } 816 817 unsigned long bnxt_re_lock_cqs(struct bnxt_re_qp *qp) 818 __acquires(&qp->scq->cq_lock) __acquires(&qp->rcq->cq_lock) 819 { 820 unsigned long flags; 821 822 spin_lock_irqsave(&qp->scq->cq_lock, flags); 823 if (qp->rcq != qp->scq) 824 spin_lock(&qp->rcq->cq_lock); 825 else 826 __acquire(&qp->rcq->cq_lock); 827 828 return flags; 829 } 830 831 void bnxt_re_unlock_cqs(struct bnxt_re_qp *qp, 832 unsigned long flags) 833 __releases(&qp->scq->cq_lock) __releases(&qp->rcq->cq_lock) 834 { 835 if (qp->rcq != qp->scq) 836 spin_unlock(&qp->rcq->cq_lock); 837 else 838 __release(&qp->rcq->cq_lock); 839 spin_unlock_irqrestore(&qp->scq->cq_lock, flags); 840 } 841 842 static int bnxt_re_destroy_gsi_sqp(struct bnxt_re_qp *qp) 843 { 844 struct bnxt_re_qp *gsi_sqp; 845 struct bnxt_re_ah *gsi_sah; 846 struct bnxt_re_dev *rdev; 847 int rc; 848 849 rdev = qp->rdev; 850 gsi_sqp = rdev->gsi_ctx.gsi_sqp; 851 gsi_sah = rdev->gsi_ctx.gsi_sah; 852 853 ibdev_dbg(&rdev->ibdev, "Destroy the shadow AH\n"); 854 bnxt_qplib_destroy_ah(&rdev->qplib_res, 855 &gsi_sah->qplib_ah, 856 true); 857 atomic_dec(&rdev->stats.res.ah_count); 858 bnxt_qplib_clean_qp(&qp->qplib_qp); 859 860 ibdev_dbg(&rdev->ibdev, "Destroy the shadow QP\n"); 861 rc = bnxt_qplib_destroy_qp(&rdev->qplib_res, &gsi_sqp->qplib_qp); 862 if (rc) { 863 ibdev_err(&rdev->ibdev, "Destroy Shadow QP failed"); 864 goto fail; 865 } 866 bnxt_qplib_free_qp_res(&rdev->qplib_res, &gsi_sqp->qplib_qp); 867 868 /* remove from active qp list */ 869 mutex_lock(&rdev->qp_lock); 870 list_del(&gsi_sqp->list); 871 mutex_unlock(&rdev->qp_lock); 872 atomic_dec(&rdev->stats.res.qp_count); 873 874 kfree(rdev->gsi_ctx.sqp_tbl); 875 kfree(gsi_sah); 876 kfree(gsi_sqp); 877 rdev->gsi_ctx.gsi_sqp = NULL; 878 rdev->gsi_ctx.gsi_sah = NULL; 879 rdev->gsi_ctx.sqp_tbl = NULL; 880 881 return 0; 882 fail: 883 return rc; 884 } 885 886 /* Queue Pairs */ 887 int bnxt_re_destroy_qp(struct ib_qp *ib_qp, struct ib_udata *udata) 888 { 889 struct bnxt_re_qp *qp = container_of(ib_qp, struct bnxt_re_qp, ib_qp); 890 struct bnxt_qplib_qp *qplib_qp = &qp->qplib_qp; 891 struct bnxt_re_dev *rdev = qp->rdev; 892 struct bnxt_qplib_nq *scq_nq = NULL; 893 struct bnxt_qplib_nq *rcq_nq = NULL; 894 unsigned int flags; 895 int rc; 896 897 bnxt_qplib_flush_cqn_wq(&qp->qplib_qp); 898 899 rc = bnxt_qplib_destroy_qp(&rdev->qplib_res, &qp->qplib_qp); 900 if (rc) { 901 ibdev_err(&rdev->ibdev, "Failed to destroy HW QP"); 902 return rc; 903 } 904 905 if (rdma_is_kernel_res(&qp->ib_qp.res)) { 906 flags = bnxt_re_lock_cqs(qp); 907 bnxt_qplib_clean_qp(&qp->qplib_qp); 908 bnxt_re_unlock_cqs(qp, flags); 909 } 910 911 bnxt_qplib_free_qp_res(&rdev->qplib_res, &qp->qplib_qp); 912 913 if (ib_qp->qp_type == IB_QPT_GSI && rdev->gsi_ctx.gsi_sqp) { 914 rc = bnxt_re_destroy_gsi_sqp(qp); 915 if (rc) 916 return rc; 917 } 918 919 mutex_lock(&rdev->qp_lock); 920 list_del(&qp->list); 921 mutex_unlock(&rdev->qp_lock); 922 atomic_dec(&rdev->stats.res.qp_count); 923 if (qp->qplib_qp.type == CMDQ_CREATE_QP_TYPE_RC) 924 atomic_dec(&rdev->stats.res.rc_qp_count); 925 else if (qp->qplib_qp.type == CMDQ_CREATE_QP_TYPE_UD) 926 atomic_dec(&rdev->stats.res.ud_qp_count); 927 928 ib_umem_release(qp->rumem); 929 ib_umem_release(qp->sumem); 930 931 /* Flush all the entries of notification queue associated with 932 * given qp. 933 */ 934 scq_nq = qplib_qp->scq->nq; 935 rcq_nq = qplib_qp->rcq->nq; 936 bnxt_re_synchronize_nq(scq_nq); 937 if (scq_nq != rcq_nq) 938 bnxt_re_synchronize_nq(rcq_nq); 939 940 return 0; 941 } 942 943 static u8 __from_ib_qp_type(enum ib_qp_type type) 944 { 945 switch (type) { 946 case IB_QPT_GSI: 947 return CMDQ_CREATE_QP1_TYPE_GSI; 948 case IB_QPT_RC: 949 return CMDQ_CREATE_QP_TYPE_RC; 950 case IB_QPT_UD: 951 return CMDQ_CREATE_QP_TYPE_UD; 952 default: 953 return IB_QPT_MAX; 954 } 955 } 956 957 static u16 bnxt_re_setup_rwqe_size(struct bnxt_qplib_qp *qplqp, 958 int rsge, int max) 959 { 960 if (qplqp->wqe_mode == BNXT_QPLIB_WQE_MODE_STATIC) 961 rsge = max; 962 return bnxt_re_get_rwqe_size(rsge); 963 } 964 965 static u16 bnxt_re_get_wqe_size(int ilsize, int nsge) 966 { 967 u16 wqe_size, calc_ils; 968 969 wqe_size = bnxt_re_get_swqe_size(nsge); 970 if (ilsize) { 971 calc_ils = sizeof(struct sq_send_hdr) + ilsize; 972 wqe_size = max_t(u16, calc_ils, wqe_size); 973 wqe_size = ALIGN(wqe_size, sizeof(struct sq_send_hdr)); 974 } 975 return wqe_size; 976 } 977 978 static int bnxt_re_setup_swqe_size(struct bnxt_re_qp *qp, 979 struct ib_qp_init_attr *init_attr) 980 { 981 struct bnxt_qplib_dev_attr *dev_attr; 982 struct bnxt_qplib_qp *qplqp; 983 struct bnxt_re_dev *rdev; 984 struct bnxt_qplib_q *sq; 985 int align, ilsize; 986 987 rdev = qp->rdev; 988 qplqp = &qp->qplib_qp; 989 sq = &qplqp->sq; 990 dev_attr = &rdev->dev_attr; 991 992 align = sizeof(struct sq_send_hdr); 993 ilsize = ALIGN(init_attr->cap.max_inline_data, align); 994 995 /* For gen p4 and gen p5 fixed wqe compatibility mode 996 * wqe size is fixed to 128 bytes - ie 6 SGEs 997 */ 998 if (qplqp->wqe_mode == BNXT_QPLIB_WQE_MODE_STATIC) { 999 sq->wqe_size = bnxt_re_get_swqe_size(BNXT_STATIC_MAX_SGE); 1000 sq->max_sge = BNXT_STATIC_MAX_SGE; 1001 } else { 1002 sq->wqe_size = bnxt_re_get_wqe_size(ilsize, sq->max_sge); 1003 if (sq->wqe_size > bnxt_re_get_swqe_size(dev_attr->max_qp_sges)) 1004 return -EINVAL; 1005 } 1006 1007 if (init_attr->cap.max_inline_data) { 1008 qplqp->max_inline_data = sq->wqe_size - 1009 sizeof(struct sq_send_hdr); 1010 init_attr->cap.max_inline_data = qplqp->max_inline_data; 1011 } 1012 1013 return 0; 1014 } 1015 1016 static int bnxt_re_init_user_qp(struct bnxt_re_dev *rdev, struct bnxt_re_pd *pd, 1017 struct bnxt_re_qp *qp, struct ib_udata *udata) 1018 { 1019 struct bnxt_qplib_qp *qplib_qp; 1020 struct bnxt_re_ucontext *cntx; 1021 struct bnxt_re_qp_req ureq; 1022 int bytes = 0, psn_sz; 1023 struct ib_umem *umem; 1024 int psn_nume; 1025 1026 qplib_qp = &qp->qplib_qp; 1027 cntx = rdma_udata_to_drv_context(udata, struct bnxt_re_ucontext, 1028 ib_uctx); 1029 if (ib_copy_from_udata(&ureq, udata, sizeof(ureq))) 1030 return -EFAULT; 1031 1032 bytes = (qplib_qp->sq.max_wqe * qplib_qp->sq.wqe_size); 1033 /* Consider mapping PSN search memory only for RC QPs. */ 1034 if (qplib_qp->type == CMDQ_CREATE_QP_TYPE_RC) { 1035 psn_sz = bnxt_qplib_is_chip_gen_p5_p7(rdev->chip_ctx) ? 1036 sizeof(struct sq_psn_search_ext) : 1037 sizeof(struct sq_psn_search); 1038 psn_nume = (qplib_qp->wqe_mode == BNXT_QPLIB_WQE_MODE_STATIC) ? 1039 qplib_qp->sq.max_wqe : 1040 ((qplib_qp->sq.max_wqe * qplib_qp->sq.wqe_size) / 1041 sizeof(struct bnxt_qplib_sge)); 1042 bytes += (psn_nume * psn_sz); 1043 } 1044 1045 bytes = PAGE_ALIGN(bytes); 1046 umem = ib_umem_get(&rdev->ibdev, ureq.qpsva, bytes, 1047 IB_ACCESS_LOCAL_WRITE); 1048 if (IS_ERR(umem)) 1049 return PTR_ERR(umem); 1050 1051 qp->sumem = umem; 1052 qplib_qp->sq.sg_info.umem = umem; 1053 qplib_qp->sq.sg_info.pgsize = PAGE_SIZE; 1054 qplib_qp->sq.sg_info.pgshft = PAGE_SHIFT; 1055 qplib_qp->qp_handle = ureq.qp_handle; 1056 1057 if (!qp->qplib_qp.srq) { 1058 bytes = (qplib_qp->rq.max_wqe * qplib_qp->rq.wqe_size); 1059 bytes = PAGE_ALIGN(bytes); 1060 umem = ib_umem_get(&rdev->ibdev, ureq.qprva, bytes, 1061 IB_ACCESS_LOCAL_WRITE); 1062 if (IS_ERR(umem)) 1063 goto rqfail; 1064 qp->rumem = umem; 1065 qplib_qp->rq.sg_info.umem = umem; 1066 qplib_qp->rq.sg_info.pgsize = PAGE_SIZE; 1067 qplib_qp->rq.sg_info.pgshft = PAGE_SHIFT; 1068 } 1069 1070 qplib_qp->dpi = &cntx->dpi; 1071 return 0; 1072 rqfail: 1073 ib_umem_release(qp->sumem); 1074 qp->sumem = NULL; 1075 memset(&qplib_qp->sq.sg_info, 0, sizeof(qplib_qp->sq.sg_info)); 1076 1077 return PTR_ERR(umem); 1078 } 1079 1080 static struct bnxt_re_ah *bnxt_re_create_shadow_qp_ah 1081 (struct bnxt_re_pd *pd, 1082 struct bnxt_qplib_res *qp1_res, 1083 struct bnxt_qplib_qp *qp1_qp) 1084 { 1085 struct bnxt_re_dev *rdev = pd->rdev; 1086 struct bnxt_re_ah *ah; 1087 union ib_gid sgid; 1088 int rc; 1089 1090 ah = kzalloc(sizeof(*ah), GFP_KERNEL); 1091 if (!ah) 1092 return NULL; 1093 1094 ah->rdev = rdev; 1095 ah->qplib_ah.pd = &pd->qplib_pd; 1096 1097 rc = bnxt_re_query_gid(&rdev->ibdev, 1, 0, &sgid); 1098 if (rc) 1099 goto fail; 1100 1101 /* supply the dgid data same as sgid */ 1102 memcpy(ah->qplib_ah.dgid.data, &sgid.raw, 1103 sizeof(union ib_gid)); 1104 ah->qplib_ah.sgid_index = 0; 1105 1106 ah->qplib_ah.traffic_class = 0; 1107 ah->qplib_ah.flow_label = 0; 1108 ah->qplib_ah.hop_limit = 1; 1109 ah->qplib_ah.sl = 0; 1110 /* Have DMAC same as SMAC */ 1111 ether_addr_copy(ah->qplib_ah.dmac, rdev->netdev->dev_addr); 1112 1113 rc = bnxt_qplib_create_ah(&rdev->qplib_res, &ah->qplib_ah, false); 1114 if (rc) { 1115 ibdev_err(&rdev->ibdev, 1116 "Failed to allocate HW AH for Shadow QP"); 1117 goto fail; 1118 } 1119 atomic_inc(&rdev->stats.res.ah_count); 1120 1121 return ah; 1122 1123 fail: 1124 kfree(ah); 1125 return NULL; 1126 } 1127 1128 static struct bnxt_re_qp *bnxt_re_create_shadow_qp 1129 (struct bnxt_re_pd *pd, 1130 struct bnxt_qplib_res *qp1_res, 1131 struct bnxt_qplib_qp *qp1_qp) 1132 { 1133 struct bnxt_re_dev *rdev = pd->rdev; 1134 struct bnxt_re_qp *qp; 1135 int rc; 1136 1137 qp = kzalloc(sizeof(*qp), GFP_KERNEL); 1138 if (!qp) 1139 return NULL; 1140 1141 qp->rdev = rdev; 1142 1143 /* Initialize the shadow QP structure from the QP1 values */ 1144 ether_addr_copy(qp->qplib_qp.smac, rdev->netdev->dev_addr); 1145 1146 qp->qplib_qp.pd = &pd->qplib_pd; 1147 qp->qplib_qp.qp_handle = (u64)(unsigned long)(&qp->qplib_qp); 1148 qp->qplib_qp.type = IB_QPT_UD; 1149 1150 qp->qplib_qp.max_inline_data = 0; 1151 qp->qplib_qp.sig_type = true; 1152 1153 /* Shadow QP SQ depth should be same as QP1 RQ depth */ 1154 qp->qplib_qp.sq.wqe_size = bnxt_re_get_wqe_size(0, 6); 1155 qp->qplib_qp.sq.max_wqe = qp1_qp->rq.max_wqe; 1156 qp->qplib_qp.sq.max_sw_wqe = qp1_qp->rq.max_wqe; 1157 qp->qplib_qp.sq.max_sge = 2; 1158 /* Q full delta can be 1 since it is internal QP */ 1159 qp->qplib_qp.sq.q_full_delta = 1; 1160 qp->qplib_qp.sq.sg_info.pgsize = PAGE_SIZE; 1161 qp->qplib_qp.sq.sg_info.pgshft = PAGE_SHIFT; 1162 1163 qp->qplib_qp.scq = qp1_qp->scq; 1164 qp->qplib_qp.rcq = qp1_qp->rcq; 1165 1166 qp->qplib_qp.rq.wqe_size = bnxt_re_get_rwqe_size(6); 1167 qp->qplib_qp.rq.max_wqe = qp1_qp->rq.max_wqe; 1168 qp->qplib_qp.rq.max_sw_wqe = qp1_qp->rq.max_wqe; 1169 qp->qplib_qp.rq.max_sge = qp1_qp->rq.max_sge; 1170 /* Q full delta can be 1 since it is internal QP */ 1171 qp->qplib_qp.rq.q_full_delta = 1; 1172 qp->qplib_qp.rq.sg_info.pgsize = PAGE_SIZE; 1173 qp->qplib_qp.rq.sg_info.pgshft = PAGE_SHIFT; 1174 1175 qp->qplib_qp.mtu = qp1_qp->mtu; 1176 1177 qp->qplib_qp.sq_hdr_buf_size = 0; 1178 qp->qplib_qp.rq_hdr_buf_size = BNXT_QPLIB_MAX_GRH_HDR_SIZE_IPV6; 1179 qp->qplib_qp.dpi = &rdev->dpi_privileged; 1180 1181 rc = bnxt_qplib_create_qp(qp1_res, &qp->qplib_qp); 1182 if (rc) 1183 goto fail; 1184 1185 spin_lock_init(&qp->sq_lock); 1186 INIT_LIST_HEAD(&qp->list); 1187 mutex_lock(&rdev->qp_lock); 1188 list_add_tail(&qp->list, &rdev->qp_list); 1189 atomic_inc(&rdev->stats.res.qp_count); 1190 mutex_unlock(&rdev->qp_lock); 1191 return qp; 1192 fail: 1193 kfree(qp); 1194 return NULL; 1195 } 1196 1197 static int bnxt_re_init_rq_attr(struct bnxt_re_qp *qp, 1198 struct ib_qp_init_attr *init_attr, 1199 struct bnxt_re_ucontext *uctx) 1200 { 1201 struct bnxt_qplib_dev_attr *dev_attr; 1202 struct bnxt_qplib_qp *qplqp; 1203 struct bnxt_re_dev *rdev; 1204 struct bnxt_qplib_q *rq; 1205 int entries; 1206 1207 rdev = qp->rdev; 1208 qplqp = &qp->qplib_qp; 1209 rq = &qplqp->rq; 1210 dev_attr = &rdev->dev_attr; 1211 1212 if (init_attr->srq) { 1213 struct bnxt_re_srq *srq; 1214 1215 srq = container_of(init_attr->srq, struct bnxt_re_srq, ib_srq); 1216 qplqp->srq = &srq->qplib_srq; 1217 rq->max_wqe = 0; 1218 } else { 1219 rq->max_sge = init_attr->cap.max_recv_sge; 1220 if (rq->max_sge > dev_attr->max_qp_sges) 1221 rq->max_sge = dev_attr->max_qp_sges; 1222 init_attr->cap.max_recv_sge = rq->max_sge; 1223 rq->wqe_size = bnxt_re_setup_rwqe_size(qplqp, rq->max_sge, 1224 dev_attr->max_qp_sges); 1225 /* Allocate 1 more than what's provided so posting max doesn't 1226 * mean empty. 1227 */ 1228 entries = bnxt_re_init_depth(init_attr->cap.max_recv_wr + 1, uctx); 1229 rq->max_wqe = min_t(u32, entries, dev_attr->max_qp_wqes + 1); 1230 rq->max_sw_wqe = rq->max_wqe; 1231 rq->q_full_delta = 0; 1232 rq->sg_info.pgsize = PAGE_SIZE; 1233 rq->sg_info.pgshft = PAGE_SHIFT; 1234 } 1235 1236 return 0; 1237 } 1238 1239 static void bnxt_re_adjust_gsi_rq_attr(struct bnxt_re_qp *qp) 1240 { 1241 struct bnxt_qplib_dev_attr *dev_attr; 1242 struct bnxt_qplib_qp *qplqp; 1243 struct bnxt_re_dev *rdev; 1244 1245 rdev = qp->rdev; 1246 qplqp = &qp->qplib_qp; 1247 dev_attr = &rdev->dev_attr; 1248 1249 if (!bnxt_qplib_is_chip_gen_p5_p7(rdev->chip_ctx)) { 1250 qplqp->rq.max_sge = dev_attr->max_qp_sges; 1251 if (qplqp->rq.max_sge > dev_attr->max_qp_sges) 1252 qplqp->rq.max_sge = dev_attr->max_qp_sges; 1253 qplqp->rq.max_sge = 6; 1254 } 1255 } 1256 1257 static int bnxt_re_init_sq_attr(struct bnxt_re_qp *qp, 1258 struct ib_qp_init_attr *init_attr, 1259 struct bnxt_re_ucontext *uctx) 1260 { 1261 struct bnxt_qplib_dev_attr *dev_attr; 1262 struct bnxt_qplib_qp *qplqp; 1263 struct bnxt_re_dev *rdev; 1264 struct bnxt_qplib_q *sq; 1265 int entries; 1266 int diff; 1267 int rc; 1268 1269 rdev = qp->rdev; 1270 qplqp = &qp->qplib_qp; 1271 sq = &qplqp->sq; 1272 dev_attr = &rdev->dev_attr; 1273 1274 sq->max_sge = init_attr->cap.max_send_sge; 1275 if (sq->max_sge > dev_attr->max_qp_sges) { 1276 sq->max_sge = dev_attr->max_qp_sges; 1277 init_attr->cap.max_send_sge = sq->max_sge; 1278 } 1279 1280 rc = bnxt_re_setup_swqe_size(qp, init_attr); 1281 if (rc) 1282 return rc; 1283 1284 entries = init_attr->cap.max_send_wr; 1285 /* Allocate 128 + 1 more than what's provided */ 1286 diff = (qplqp->wqe_mode == BNXT_QPLIB_WQE_MODE_VARIABLE) ? 1287 0 : BNXT_QPLIB_RESERVED_QP_WRS; 1288 entries = bnxt_re_init_depth(entries + diff + 1, uctx); 1289 sq->max_wqe = min_t(u32, entries, dev_attr->max_qp_wqes + diff + 1); 1290 sq->max_sw_wqe = bnxt_qplib_get_depth(sq, qplqp->wqe_mode, true); 1291 sq->q_full_delta = diff + 1; 1292 /* 1293 * Reserving one slot for Phantom WQE. Application can 1294 * post one extra entry in this case. But allowing this to avoid 1295 * unexpected Queue full condition 1296 */ 1297 qplqp->sq.q_full_delta -= 1; 1298 qplqp->sq.sg_info.pgsize = PAGE_SIZE; 1299 qplqp->sq.sg_info.pgshft = PAGE_SHIFT; 1300 1301 return 0; 1302 } 1303 1304 static void bnxt_re_adjust_gsi_sq_attr(struct bnxt_re_qp *qp, 1305 struct ib_qp_init_attr *init_attr, 1306 struct bnxt_re_ucontext *uctx) 1307 { 1308 struct bnxt_qplib_dev_attr *dev_attr; 1309 struct bnxt_qplib_qp *qplqp; 1310 struct bnxt_re_dev *rdev; 1311 int entries; 1312 1313 rdev = qp->rdev; 1314 qplqp = &qp->qplib_qp; 1315 dev_attr = &rdev->dev_attr; 1316 1317 if (!bnxt_qplib_is_chip_gen_p5_p7(rdev->chip_ctx)) { 1318 entries = bnxt_re_init_depth(init_attr->cap.max_send_wr + 1, uctx); 1319 qplqp->sq.max_wqe = min_t(u32, entries, 1320 dev_attr->max_qp_wqes + 1); 1321 qplqp->sq.q_full_delta = qplqp->sq.max_wqe - 1322 init_attr->cap.max_send_wr; 1323 qplqp->sq.max_sge++; /* Need one extra sge to put UD header */ 1324 if (qplqp->sq.max_sge > dev_attr->max_qp_sges) 1325 qplqp->sq.max_sge = dev_attr->max_qp_sges; 1326 } 1327 } 1328 1329 static int bnxt_re_init_qp_type(struct bnxt_re_dev *rdev, 1330 struct ib_qp_init_attr *init_attr) 1331 { 1332 struct bnxt_qplib_chip_ctx *chip_ctx; 1333 int qptype; 1334 1335 chip_ctx = rdev->chip_ctx; 1336 1337 qptype = __from_ib_qp_type(init_attr->qp_type); 1338 if (qptype == IB_QPT_MAX) { 1339 ibdev_err(&rdev->ibdev, "QP type 0x%x not supported", qptype); 1340 qptype = -EOPNOTSUPP; 1341 goto out; 1342 } 1343 1344 if (bnxt_qplib_is_chip_gen_p5_p7(chip_ctx) && 1345 init_attr->qp_type == IB_QPT_GSI) 1346 qptype = CMDQ_CREATE_QP_TYPE_GSI; 1347 out: 1348 return qptype; 1349 } 1350 1351 static int bnxt_re_init_qp_attr(struct bnxt_re_qp *qp, struct bnxt_re_pd *pd, 1352 struct ib_qp_init_attr *init_attr, 1353 struct ib_udata *udata) 1354 { 1355 struct bnxt_qplib_dev_attr *dev_attr; 1356 struct bnxt_re_ucontext *uctx; 1357 struct bnxt_qplib_qp *qplqp; 1358 struct bnxt_re_dev *rdev; 1359 struct bnxt_re_cq *cq; 1360 int rc = 0, qptype; 1361 1362 rdev = qp->rdev; 1363 qplqp = &qp->qplib_qp; 1364 dev_attr = &rdev->dev_attr; 1365 1366 uctx = rdma_udata_to_drv_context(udata, struct bnxt_re_ucontext, ib_uctx); 1367 /* Setup misc params */ 1368 ether_addr_copy(qplqp->smac, rdev->netdev->dev_addr); 1369 qplqp->pd = &pd->qplib_pd; 1370 qplqp->qp_handle = (u64)qplqp; 1371 qplqp->max_inline_data = init_attr->cap.max_inline_data; 1372 qplqp->sig_type = init_attr->sq_sig_type == IB_SIGNAL_ALL_WR; 1373 qptype = bnxt_re_init_qp_type(rdev, init_attr); 1374 if (qptype < 0) { 1375 rc = qptype; 1376 goto out; 1377 } 1378 qplqp->type = (u8)qptype; 1379 qplqp->wqe_mode = rdev->chip_ctx->modes.wqe_mode; 1380 1381 if (init_attr->qp_type == IB_QPT_RC) { 1382 qplqp->max_rd_atomic = dev_attr->max_qp_rd_atom; 1383 qplqp->max_dest_rd_atomic = dev_attr->max_qp_init_rd_atom; 1384 } 1385 qplqp->mtu = ib_mtu_enum_to_int(iboe_get_mtu(rdev->netdev->mtu)); 1386 qplqp->dpi = &rdev->dpi_privileged; /* Doorbell page */ 1387 if (init_attr->create_flags) { 1388 ibdev_dbg(&rdev->ibdev, 1389 "QP create flags 0x%x not supported", 1390 init_attr->create_flags); 1391 return -EOPNOTSUPP; 1392 } 1393 1394 /* Setup CQs */ 1395 if (init_attr->send_cq) { 1396 cq = container_of(init_attr->send_cq, struct bnxt_re_cq, ib_cq); 1397 qplqp->scq = &cq->qplib_cq; 1398 qp->scq = cq; 1399 } 1400 1401 if (init_attr->recv_cq) { 1402 cq = container_of(init_attr->recv_cq, struct bnxt_re_cq, ib_cq); 1403 qplqp->rcq = &cq->qplib_cq; 1404 qp->rcq = cq; 1405 } 1406 1407 /* Setup RQ/SRQ */ 1408 rc = bnxt_re_init_rq_attr(qp, init_attr, uctx); 1409 if (rc) 1410 goto out; 1411 if (init_attr->qp_type == IB_QPT_GSI) 1412 bnxt_re_adjust_gsi_rq_attr(qp); 1413 1414 /* Setup SQ */ 1415 rc = bnxt_re_init_sq_attr(qp, init_attr, uctx); 1416 if (rc) 1417 goto out; 1418 if (init_attr->qp_type == IB_QPT_GSI) 1419 bnxt_re_adjust_gsi_sq_attr(qp, init_attr, uctx); 1420 1421 if (udata) /* This will update DPI and qp_handle */ 1422 rc = bnxt_re_init_user_qp(rdev, pd, qp, udata); 1423 out: 1424 return rc; 1425 } 1426 1427 static int bnxt_re_create_shadow_gsi(struct bnxt_re_qp *qp, 1428 struct bnxt_re_pd *pd) 1429 { 1430 struct bnxt_re_sqp_entries *sqp_tbl; 1431 struct bnxt_re_dev *rdev; 1432 struct bnxt_re_qp *sqp; 1433 struct bnxt_re_ah *sah; 1434 int rc = 0; 1435 1436 rdev = qp->rdev; 1437 /* Create a shadow QP to handle the QP1 traffic */ 1438 sqp_tbl = kcalloc(BNXT_RE_MAX_GSI_SQP_ENTRIES, sizeof(*sqp_tbl), 1439 GFP_KERNEL); 1440 if (!sqp_tbl) 1441 return -ENOMEM; 1442 rdev->gsi_ctx.sqp_tbl = sqp_tbl; 1443 1444 sqp = bnxt_re_create_shadow_qp(pd, &rdev->qplib_res, &qp->qplib_qp); 1445 if (!sqp) { 1446 rc = -ENODEV; 1447 ibdev_err(&rdev->ibdev, "Failed to create Shadow QP for QP1"); 1448 goto out; 1449 } 1450 rdev->gsi_ctx.gsi_sqp = sqp; 1451 1452 sqp->rcq = qp->rcq; 1453 sqp->scq = qp->scq; 1454 sah = bnxt_re_create_shadow_qp_ah(pd, &rdev->qplib_res, 1455 &qp->qplib_qp); 1456 if (!sah) { 1457 bnxt_qplib_destroy_qp(&rdev->qplib_res, 1458 &sqp->qplib_qp); 1459 rc = -ENODEV; 1460 ibdev_err(&rdev->ibdev, 1461 "Failed to create AH entry for ShadowQP"); 1462 goto out; 1463 } 1464 rdev->gsi_ctx.gsi_sah = sah; 1465 1466 return 0; 1467 out: 1468 kfree(sqp_tbl); 1469 return rc; 1470 } 1471 1472 static int bnxt_re_create_gsi_qp(struct bnxt_re_qp *qp, struct bnxt_re_pd *pd, 1473 struct ib_qp_init_attr *init_attr) 1474 { 1475 struct bnxt_re_dev *rdev; 1476 struct bnxt_qplib_qp *qplqp; 1477 int rc; 1478 1479 rdev = qp->rdev; 1480 qplqp = &qp->qplib_qp; 1481 1482 qplqp->rq_hdr_buf_size = BNXT_QPLIB_MAX_QP1_RQ_HDR_SIZE_V2; 1483 qplqp->sq_hdr_buf_size = BNXT_QPLIB_MAX_QP1_SQ_HDR_SIZE_V2; 1484 1485 rc = bnxt_qplib_create_qp1(&rdev->qplib_res, qplqp); 1486 if (rc) { 1487 ibdev_err(&rdev->ibdev, "create HW QP1 failed!"); 1488 goto out; 1489 } 1490 1491 rc = bnxt_re_create_shadow_gsi(qp, pd); 1492 out: 1493 return rc; 1494 } 1495 1496 static bool bnxt_re_test_qp_limits(struct bnxt_re_dev *rdev, 1497 struct ib_qp_init_attr *init_attr, 1498 struct bnxt_qplib_dev_attr *dev_attr) 1499 { 1500 bool rc = true; 1501 1502 if (init_attr->cap.max_send_wr > dev_attr->max_qp_wqes || 1503 init_attr->cap.max_recv_wr > dev_attr->max_qp_wqes || 1504 init_attr->cap.max_send_sge > dev_attr->max_qp_sges || 1505 init_attr->cap.max_recv_sge > dev_attr->max_qp_sges || 1506 init_attr->cap.max_inline_data > dev_attr->max_inline_data) { 1507 ibdev_err(&rdev->ibdev, 1508 "Create QP failed - max exceeded! 0x%x/0x%x 0x%x/0x%x 0x%x/0x%x 0x%x/0x%x 0x%x/0x%x", 1509 init_attr->cap.max_send_wr, dev_attr->max_qp_wqes, 1510 init_attr->cap.max_recv_wr, dev_attr->max_qp_wqes, 1511 init_attr->cap.max_send_sge, dev_attr->max_qp_sges, 1512 init_attr->cap.max_recv_sge, dev_attr->max_qp_sges, 1513 init_attr->cap.max_inline_data, 1514 dev_attr->max_inline_data); 1515 rc = false; 1516 } 1517 return rc; 1518 } 1519 1520 int bnxt_re_create_qp(struct ib_qp *ib_qp, struct ib_qp_init_attr *qp_init_attr, 1521 struct ib_udata *udata) 1522 { 1523 struct ib_pd *ib_pd = ib_qp->pd; 1524 struct bnxt_re_pd *pd = container_of(ib_pd, struct bnxt_re_pd, ib_pd); 1525 struct bnxt_re_dev *rdev = pd->rdev; 1526 struct bnxt_qplib_dev_attr *dev_attr = &rdev->dev_attr; 1527 struct bnxt_re_qp *qp = container_of(ib_qp, struct bnxt_re_qp, ib_qp); 1528 u32 active_qps; 1529 int rc; 1530 1531 rc = bnxt_re_test_qp_limits(rdev, qp_init_attr, dev_attr); 1532 if (!rc) { 1533 rc = -EINVAL; 1534 goto fail; 1535 } 1536 1537 qp->rdev = rdev; 1538 rc = bnxt_re_init_qp_attr(qp, pd, qp_init_attr, udata); 1539 if (rc) 1540 goto fail; 1541 1542 if (qp_init_attr->qp_type == IB_QPT_GSI && 1543 !(bnxt_qplib_is_chip_gen_p5_p7(rdev->chip_ctx))) { 1544 rc = bnxt_re_create_gsi_qp(qp, pd, qp_init_attr); 1545 if (rc == -ENODEV) 1546 goto qp_destroy; 1547 if (rc) 1548 goto fail; 1549 } else { 1550 rc = bnxt_qplib_create_qp(&rdev->qplib_res, &qp->qplib_qp); 1551 if (rc) { 1552 ibdev_err(&rdev->ibdev, "Failed to create HW QP"); 1553 goto free_umem; 1554 } 1555 if (udata) { 1556 struct bnxt_re_qp_resp resp; 1557 1558 resp.qpid = qp->qplib_qp.id; 1559 resp.rsvd = 0; 1560 rc = ib_copy_to_udata(udata, &resp, sizeof(resp)); 1561 if (rc) { 1562 ibdev_err(&rdev->ibdev, "Failed to copy QP udata"); 1563 goto qp_destroy; 1564 } 1565 } 1566 } 1567 1568 qp->ib_qp.qp_num = qp->qplib_qp.id; 1569 if (qp_init_attr->qp_type == IB_QPT_GSI) 1570 rdev->gsi_ctx.gsi_qp = qp; 1571 spin_lock_init(&qp->sq_lock); 1572 spin_lock_init(&qp->rq_lock); 1573 INIT_LIST_HEAD(&qp->list); 1574 mutex_lock(&rdev->qp_lock); 1575 list_add_tail(&qp->list, &rdev->qp_list); 1576 mutex_unlock(&rdev->qp_lock); 1577 active_qps = atomic_inc_return(&rdev->stats.res.qp_count); 1578 if (active_qps > rdev->stats.res.qp_watermark) 1579 rdev->stats.res.qp_watermark = active_qps; 1580 if (qp_init_attr->qp_type == IB_QPT_RC) { 1581 active_qps = atomic_inc_return(&rdev->stats.res.rc_qp_count); 1582 if (active_qps > rdev->stats.res.rc_qp_watermark) 1583 rdev->stats.res.rc_qp_watermark = active_qps; 1584 } else if (qp_init_attr->qp_type == IB_QPT_UD) { 1585 active_qps = atomic_inc_return(&rdev->stats.res.ud_qp_count); 1586 if (active_qps > rdev->stats.res.ud_qp_watermark) 1587 rdev->stats.res.ud_qp_watermark = active_qps; 1588 } 1589 1590 return 0; 1591 qp_destroy: 1592 bnxt_qplib_destroy_qp(&rdev->qplib_res, &qp->qplib_qp); 1593 free_umem: 1594 ib_umem_release(qp->rumem); 1595 ib_umem_release(qp->sumem); 1596 fail: 1597 return rc; 1598 } 1599 1600 static u8 __from_ib_qp_state(enum ib_qp_state state) 1601 { 1602 switch (state) { 1603 case IB_QPS_RESET: 1604 return CMDQ_MODIFY_QP_NEW_STATE_RESET; 1605 case IB_QPS_INIT: 1606 return CMDQ_MODIFY_QP_NEW_STATE_INIT; 1607 case IB_QPS_RTR: 1608 return CMDQ_MODIFY_QP_NEW_STATE_RTR; 1609 case IB_QPS_RTS: 1610 return CMDQ_MODIFY_QP_NEW_STATE_RTS; 1611 case IB_QPS_SQD: 1612 return CMDQ_MODIFY_QP_NEW_STATE_SQD; 1613 case IB_QPS_SQE: 1614 return CMDQ_MODIFY_QP_NEW_STATE_SQE; 1615 case IB_QPS_ERR: 1616 default: 1617 return CMDQ_MODIFY_QP_NEW_STATE_ERR; 1618 } 1619 } 1620 1621 static enum ib_qp_state __to_ib_qp_state(u8 state) 1622 { 1623 switch (state) { 1624 case CMDQ_MODIFY_QP_NEW_STATE_RESET: 1625 return IB_QPS_RESET; 1626 case CMDQ_MODIFY_QP_NEW_STATE_INIT: 1627 return IB_QPS_INIT; 1628 case CMDQ_MODIFY_QP_NEW_STATE_RTR: 1629 return IB_QPS_RTR; 1630 case CMDQ_MODIFY_QP_NEW_STATE_RTS: 1631 return IB_QPS_RTS; 1632 case CMDQ_MODIFY_QP_NEW_STATE_SQD: 1633 return IB_QPS_SQD; 1634 case CMDQ_MODIFY_QP_NEW_STATE_SQE: 1635 return IB_QPS_SQE; 1636 case CMDQ_MODIFY_QP_NEW_STATE_ERR: 1637 default: 1638 return IB_QPS_ERR; 1639 } 1640 } 1641 1642 static u32 __from_ib_mtu(enum ib_mtu mtu) 1643 { 1644 switch (mtu) { 1645 case IB_MTU_256: 1646 return CMDQ_MODIFY_QP_PATH_MTU_MTU_256; 1647 case IB_MTU_512: 1648 return CMDQ_MODIFY_QP_PATH_MTU_MTU_512; 1649 case IB_MTU_1024: 1650 return CMDQ_MODIFY_QP_PATH_MTU_MTU_1024; 1651 case IB_MTU_2048: 1652 return CMDQ_MODIFY_QP_PATH_MTU_MTU_2048; 1653 case IB_MTU_4096: 1654 return CMDQ_MODIFY_QP_PATH_MTU_MTU_4096; 1655 default: 1656 return CMDQ_MODIFY_QP_PATH_MTU_MTU_2048; 1657 } 1658 } 1659 1660 static enum ib_mtu __to_ib_mtu(u32 mtu) 1661 { 1662 switch (mtu & CREQ_QUERY_QP_RESP_SB_PATH_MTU_MASK) { 1663 case CMDQ_MODIFY_QP_PATH_MTU_MTU_256: 1664 return IB_MTU_256; 1665 case CMDQ_MODIFY_QP_PATH_MTU_MTU_512: 1666 return IB_MTU_512; 1667 case CMDQ_MODIFY_QP_PATH_MTU_MTU_1024: 1668 return IB_MTU_1024; 1669 case CMDQ_MODIFY_QP_PATH_MTU_MTU_2048: 1670 return IB_MTU_2048; 1671 case CMDQ_MODIFY_QP_PATH_MTU_MTU_4096: 1672 return IB_MTU_4096; 1673 default: 1674 return IB_MTU_2048; 1675 } 1676 } 1677 1678 /* Shared Receive Queues */ 1679 int bnxt_re_destroy_srq(struct ib_srq *ib_srq, struct ib_udata *udata) 1680 { 1681 struct bnxt_re_srq *srq = container_of(ib_srq, struct bnxt_re_srq, 1682 ib_srq); 1683 struct bnxt_re_dev *rdev = srq->rdev; 1684 struct bnxt_qplib_srq *qplib_srq = &srq->qplib_srq; 1685 struct bnxt_qplib_nq *nq = NULL; 1686 1687 if (qplib_srq->cq) 1688 nq = qplib_srq->cq->nq; 1689 bnxt_qplib_destroy_srq(&rdev->qplib_res, qplib_srq); 1690 ib_umem_release(srq->umem); 1691 atomic_dec(&rdev->stats.res.srq_count); 1692 if (nq) 1693 nq->budget--; 1694 return 0; 1695 } 1696 1697 static int bnxt_re_init_user_srq(struct bnxt_re_dev *rdev, 1698 struct bnxt_re_pd *pd, 1699 struct bnxt_re_srq *srq, 1700 struct ib_udata *udata) 1701 { 1702 struct bnxt_re_srq_req ureq; 1703 struct bnxt_qplib_srq *qplib_srq = &srq->qplib_srq; 1704 struct ib_umem *umem; 1705 int bytes = 0; 1706 struct bnxt_re_ucontext *cntx = rdma_udata_to_drv_context( 1707 udata, struct bnxt_re_ucontext, ib_uctx); 1708 1709 if (ib_copy_from_udata(&ureq, udata, sizeof(ureq))) 1710 return -EFAULT; 1711 1712 bytes = (qplib_srq->max_wqe * qplib_srq->wqe_size); 1713 bytes = PAGE_ALIGN(bytes); 1714 umem = ib_umem_get(&rdev->ibdev, ureq.srqva, bytes, 1715 IB_ACCESS_LOCAL_WRITE); 1716 if (IS_ERR(umem)) 1717 return PTR_ERR(umem); 1718 1719 srq->umem = umem; 1720 qplib_srq->sg_info.umem = umem; 1721 qplib_srq->sg_info.pgsize = PAGE_SIZE; 1722 qplib_srq->sg_info.pgshft = PAGE_SHIFT; 1723 qplib_srq->srq_handle = ureq.srq_handle; 1724 qplib_srq->dpi = &cntx->dpi; 1725 1726 return 0; 1727 } 1728 1729 int bnxt_re_create_srq(struct ib_srq *ib_srq, 1730 struct ib_srq_init_attr *srq_init_attr, 1731 struct ib_udata *udata) 1732 { 1733 struct bnxt_qplib_dev_attr *dev_attr; 1734 struct bnxt_qplib_nq *nq = NULL; 1735 struct bnxt_re_ucontext *uctx; 1736 struct bnxt_re_dev *rdev; 1737 struct bnxt_re_srq *srq; 1738 struct bnxt_re_pd *pd; 1739 struct ib_pd *ib_pd; 1740 u32 active_srqs; 1741 int rc, entries; 1742 1743 ib_pd = ib_srq->pd; 1744 pd = container_of(ib_pd, struct bnxt_re_pd, ib_pd); 1745 rdev = pd->rdev; 1746 dev_attr = &rdev->dev_attr; 1747 srq = container_of(ib_srq, struct bnxt_re_srq, ib_srq); 1748 1749 if (srq_init_attr->attr.max_wr >= dev_attr->max_srq_wqes) { 1750 ibdev_err(&rdev->ibdev, "Create CQ failed - max exceeded"); 1751 rc = -EINVAL; 1752 goto exit; 1753 } 1754 1755 if (srq_init_attr->srq_type != IB_SRQT_BASIC) { 1756 rc = -EOPNOTSUPP; 1757 goto exit; 1758 } 1759 1760 uctx = rdma_udata_to_drv_context(udata, struct bnxt_re_ucontext, ib_uctx); 1761 srq->rdev = rdev; 1762 srq->qplib_srq.pd = &pd->qplib_pd; 1763 srq->qplib_srq.dpi = &rdev->dpi_privileged; 1764 /* Allocate 1 more than what's provided so posting max doesn't 1765 * mean empty 1766 */ 1767 entries = bnxt_re_init_depth(srq_init_attr->attr.max_wr + 1, uctx); 1768 if (entries > dev_attr->max_srq_wqes + 1) 1769 entries = dev_attr->max_srq_wqes + 1; 1770 srq->qplib_srq.max_wqe = entries; 1771 1772 srq->qplib_srq.max_sge = srq_init_attr->attr.max_sge; 1773 /* 128 byte wqe size for SRQ . So use max sges */ 1774 srq->qplib_srq.wqe_size = bnxt_re_get_rwqe_size(dev_attr->max_srq_sges); 1775 srq->qplib_srq.threshold = srq_init_attr->attr.srq_limit; 1776 srq->srq_limit = srq_init_attr->attr.srq_limit; 1777 srq->qplib_srq.eventq_hw_ring_id = rdev->nq[0].ring_id; 1778 nq = &rdev->nq[0]; 1779 1780 if (udata) { 1781 rc = bnxt_re_init_user_srq(rdev, pd, srq, udata); 1782 if (rc) 1783 goto fail; 1784 } 1785 1786 rc = bnxt_qplib_create_srq(&rdev->qplib_res, &srq->qplib_srq); 1787 if (rc) { 1788 ibdev_err(&rdev->ibdev, "Create HW SRQ failed!"); 1789 goto fail; 1790 } 1791 1792 if (udata) { 1793 struct bnxt_re_srq_resp resp; 1794 1795 resp.srqid = srq->qplib_srq.id; 1796 rc = ib_copy_to_udata(udata, &resp, sizeof(resp)); 1797 if (rc) { 1798 ibdev_err(&rdev->ibdev, "SRQ copy to udata failed!"); 1799 bnxt_qplib_destroy_srq(&rdev->qplib_res, 1800 &srq->qplib_srq); 1801 goto fail; 1802 } 1803 } 1804 if (nq) 1805 nq->budget++; 1806 active_srqs = atomic_inc_return(&rdev->stats.res.srq_count); 1807 if (active_srqs > rdev->stats.res.srq_watermark) 1808 rdev->stats.res.srq_watermark = active_srqs; 1809 spin_lock_init(&srq->lock); 1810 1811 return 0; 1812 1813 fail: 1814 ib_umem_release(srq->umem); 1815 exit: 1816 return rc; 1817 } 1818 1819 int bnxt_re_modify_srq(struct ib_srq *ib_srq, struct ib_srq_attr *srq_attr, 1820 enum ib_srq_attr_mask srq_attr_mask, 1821 struct ib_udata *udata) 1822 { 1823 struct bnxt_re_srq *srq = container_of(ib_srq, struct bnxt_re_srq, 1824 ib_srq); 1825 struct bnxt_re_dev *rdev = srq->rdev; 1826 int rc; 1827 1828 switch (srq_attr_mask) { 1829 case IB_SRQ_MAX_WR: 1830 /* SRQ resize is not supported */ 1831 return -EINVAL; 1832 case IB_SRQ_LIMIT: 1833 /* Change the SRQ threshold */ 1834 if (srq_attr->srq_limit > srq->qplib_srq.max_wqe) 1835 return -EINVAL; 1836 1837 srq->qplib_srq.threshold = srq_attr->srq_limit; 1838 rc = bnxt_qplib_modify_srq(&rdev->qplib_res, &srq->qplib_srq); 1839 if (rc) { 1840 ibdev_err(&rdev->ibdev, "Modify HW SRQ failed!"); 1841 return rc; 1842 } 1843 /* On success, update the shadow */ 1844 srq->srq_limit = srq_attr->srq_limit; 1845 /* No need to Build and send response back to udata */ 1846 return 0; 1847 default: 1848 ibdev_err(&rdev->ibdev, 1849 "Unsupported srq_attr_mask 0x%x", srq_attr_mask); 1850 return -EINVAL; 1851 } 1852 } 1853 1854 int bnxt_re_query_srq(struct ib_srq *ib_srq, struct ib_srq_attr *srq_attr) 1855 { 1856 struct bnxt_re_srq *srq = container_of(ib_srq, struct bnxt_re_srq, 1857 ib_srq); 1858 struct bnxt_re_srq tsrq; 1859 struct bnxt_re_dev *rdev = srq->rdev; 1860 int rc; 1861 1862 /* Get live SRQ attr */ 1863 tsrq.qplib_srq.id = srq->qplib_srq.id; 1864 rc = bnxt_qplib_query_srq(&rdev->qplib_res, &tsrq.qplib_srq); 1865 if (rc) { 1866 ibdev_err(&rdev->ibdev, "Query HW SRQ failed!"); 1867 return rc; 1868 } 1869 srq_attr->max_wr = srq->qplib_srq.max_wqe; 1870 srq_attr->max_sge = srq->qplib_srq.max_sge; 1871 srq_attr->srq_limit = tsrq.qplib_srq.threshold; 1872 1873 return 0; 1874 } 1875 1876 int bnxt_re_post_srq_recv(struct ib_srq *ib_srq, const struct ib_recv_wr *wr, 1877 const struct ib_recv_wr **bad_wr) 1878 { 1879 struct bnxt_re_srq *srq = container_of(ib_srq, struct bnxt_re_srq, 1880 ib_srq); 1881 struct bnxt_qplib_swqe wqe; 1882 unsigned long flags; 1883 int rc = 0; 1884 1885 spin_lock_irqsave(&srq->lock, flags); 1886 while (wr) { 1887 /* Transcribe each ib_recv_wr to qplib_swqe */ 1888 wqe.num_sge = wr->num_sge; 1889 bnxt_re_build_sgl(wr->sg_list, wqe.sg_list, wr->num_sge); 1890 wqe.wr_id = wr->wr_id; 1891 wqe.type = BNXT_QPLIB_SWQE_TYPE_RECV; 1892 1893 rc = bnxt_qplib_post_srq_recv(&srq->qplib_srq, &wqe); 1894 if (rc) { 1895 *bad_wr = wr; 1896 break; 1897 } 1898 wr = wr->next; 1899 } 1900 spin_unlock_irqrestore(&srq->lock, flags); 1901 1902 return rc; 1903 } 1904 static int bnxt_re_modify_shadow_qp(struct bnxt_re_dev *rdev, 1905 struct bnxt_re_qp *qp1_qp, 1906 int qp_attr_mask) 1907 { 1908 struct bnxt_re_qp *qp = rdev->gsi_ctx.gsi_sqp; 1909 int rc; 1910 1911 if (qp_attr_mask & IB_QP_STATE) { 1912 qp->qplib_qp.modify_flags |= CMDQ_MODIFY_QP_MODIFY_MASK_STATE; 1913 qp->qplib_qp.state = qp1_qp->qplib_qp.state; 1914 } 1915 if (qp_attr_mask & IB_QP_PKEY_INDEX) { 1916 qp->qplib_qp.modify_flags |= CMDQ_MODIFY_QP_MODIFY_MASK_PKEY; 1917 qp->qplib_qp.pkey_index = qp1_qp->qplib_qp.pkey_index; 1918 } 1919 1920 if (qp_attr_mask & IB_QP_QKEY) { 1921 qp->qplib_qp.modify_flags |= CMDQ_MODIFY_QP_MODIFY_MASK_QKEY; 1922 /* Using a Random QKEY */ 1923 qp->qplib_qp.qkey = 0x81818181; 1924 } 1925 if (qp_attr_mask & IB_QP_SQ_PSN) { 1926 qp->qplib_qp.modify_flags |= CMDQ_MODIFY_QP_MODIFY_MASK_SQ_PSN; 1927 qp->qplib_qp.sq.psn = qp1_qp->qplib_qp.sq.psn; 1928 } 1929 1930 rc = bnxt_qplib_modify_qp(&rdev->qplib_res, &qp->qplib_qp); 1931 if (rc) 1932 ibdev_err(&rdev->ibdev, "Failed to modify Shadow QP for QP1"); 1933 return rc; 1934 } 1935 1936 int bnxt_re_modify_qp(struct ib_qp *ib_qp, struct ib_qp_attr *qp_attr, 1937 int qp_attr_mask, struct ib_udata *udata) 1938 { 1939 struct bnxt_re_qp *qp = container_of(ib_qp, struct bnxt_re_qp, ib_qp); 1940 struct bnxt_re_dev *rdev = qp->rdev; 1941 struct bnxt_qplib_dev_attr *dev_attr = &rdev->dev_attr; 1942 enum ib_qp_state curr_qp_state, new_qp_state; 1943 int rc, entries; 1944 unsigned int flags; 1945 u8 nw_type; 1946 1947 if (qp_attr_mask & ~IB_QP_ATTR_STANDARD_BITS) 1948 return -EOPNOTSUPP; 1949 1950 qp->qplib_qp.modify_flags = 0; 1951 if (qp_attr_mask & IB_QP_STATE) { 1952 curr_qp_state = __to_ib_qp_state(qp->qplib_qp.cur_qp_state); 1953 new_qp_state = qp_attr->qp_state; 1954 if (!ib_modify_qp_is_ok(curr_qp_state, new_qp_state, 1955 ib_qp->qp_type, qp_attr_mask)) { 1956 ibdev_err(&rdev->ibdev, 1957 "Invalid attribute mask: %#x specified ", 1958 qp_attr_mask); 1959 ibdev_err(&rdev->ibdev, 1960 "for qpn: %#x type: %#x", 1961 ib_qp->qp_num, ib_qp->qp_type); 1962 ibdev_err(&rdev->ibdev, 1963 "curr_qp_state=0x%x, new_qp_state=0x%x\n", 1964 curr_qp_state, new_qp_state); 1965 return -EINVAL; 1966 } 1967 qp->qplib_qp.modify_flags |= CMDQ_MODIFY_QP_MODIFY_MASK_STATE; 1968 qp->qplib_qp.state = __from_ib_qp_state(qp_attr->qp_state); 1969 1970 if (!qp->sumem && 1971 qp->qplib_qp.state == CMDQ_MODIFY_QP_NEW_STATE_ERR) { 1972 ibdev_dbg(&rdev->ibdev, 1973 "Move QP = %p to flush list\n", qp); 1974 flags = bnxt_re_lock_cqs(qp); 1975 bnxt_qplib_add_flush_qp(&qp->qplib_qp); 1976 bnxt_re_unlock_cqs(qp, flags); 1977 } 1978 if (!qp->sumem && 1979 qp->qplib_qp.state == CMDQ_MODIFY_QP_NEW_STATE_RESET) { 1980 ibdev_dbg(&rdev->ibdev, 1981 "Move QP = %p out of flush list\n", qp); 1982 flags = bnxt_re_lock_cqs(qp); 1983 bnxt_qplib_clean_qp(&qp->qplib_qp); 1984 bnxt_re_unlock_cqs(qp, flags); 1985 } 1986 } 1987 if (qp_attr_mask & IB_QP_EN_SQD_ASYNC_NOTIFY) { 1988 qp->qplib_qp.modify_flags |= 1989 CMDQ_MODIFY_QP_MODIFY_MASK_EN_SQD_ASYNC_NOTIFY; 1990 qp->qplib_qp.en_sqd_async_notify = true; 1991 } 1992 if (qp_attr_mask & IB_QP_ACCESS_FLAGS) { 1993 qp->qplib_qp.modify_flags |= CMDQ_MODIFY_QP_MODIFY_MASK_ACCESS; 1994 qp->qplib_qp.access = 1995 __from_ib_access_flags(qp_attr->qp_access_flags); 1996 /* LOCAL_WRITE access must be set to allow RC receive */ 1997 qp->qplib_qp.access |= BNXT_QPLIB_ACCESS_LOCAL_WRITE; 1998 /* Temp: Set all params on QP as of now */ 1999 qp->qplib_qp.access |= CMDQ_MODIFY_QP_ACCESS_REMOTE_WRITE; 2000 qp->qplib_qp.access |= CMDQ_MODIFY_QP_ACCESS_REMOTE_READ; 2001 } 2002 if (qp_attr_mask & IB_QP_PKEY_INDEX) { 2003 qp->qplib_qp.modify_flags |= CMDQ_MODIFY_QP_MODIFY_MASK_PKEY; 2004 qp->qplib_qp.pkey_index = qp_attr->pkey_index; 2005 } 2006 if (qp_attr_mask & IB_QP_QKEY) { 2007 qp->qplib_qp.modify_flags |= CMDQ_MODIFY_QP_MODIFY_MASK_QKEY; 2008 qp->qplib_qp.qkey = qp_attr->qkey; 2009 } 2010 if (qp_attr_mask & IB_QP_AV) { 2011 const struct ib_global_route *grh = 2012 rdma_ah_read_grh(&qp_attr->ah_attr); 2013 const struct ib_gid_attr *sgid_attr; 2014 struct bnxt_re_gid_ctx *ctx; 2015 2016 qp->qplib_qp.modify_flags |= CMDQ_MODIFY_QP_MODIFY_MASK_DGID | 2017 CMDQ_MODIFY_QP_MODIFY_MASK_FLOW_LABEL | 2018 CMDQ_MODIFY_QP_MODIFY_MASK_SGID_INDEX | 2019 CMDQ_MODIFY_QP_MODIFY_MASK_HOP_LIMIT | 2020 CMDQ_MODIFY_QP_MODIFY_MASK_TRAFFIC_CLASS | 2021 CMDQ_MODIFY_QP_MODIFY_MASK_DEST_MAC | 2022 CMDQ_MODIFY_QP_MODIFY_MASK_VLAN_ID; 2023 memcpy(qp->qplib_qp.ah.dgid.data, grh->dgid.raw, 2024 sizeof(qp->qplib_qp.ah.dgid.data)); 2025 qp->qplib_qp.ah.flow_label = grh->flow_label; 2026 sgid_attr = grh->sgid_attr; 2027 /* Get the HW context of the GID. The reference 2028 * of GID table entry is already taken by the caller. 2029 */ 2030 ctx = rdma_read_gid_hw_context(sgid_attr); 2031 qp->qplib_qp.ah.sgid_index = ctx->idx; 2032 qp->qplib_qp.ah.host_sgid_index = grh->sgid_index; 2033 qp->qplib_qp.ah.hop_limit = grh->hop_limit; 2034 qp->qplib_qp.ah.traffic_class = grh->traffic_class; 2035 qp->qplib_qp.ah.sl = rdma_ah_get_sl(&qp_attr->ah_attr); 2036 ether_addr_copy(qp->qplib_qp.ah.dmac, 2037 qp_attr->ah_attr.roce.dmac); 2038 2039 rc = rdma_read_gid_l2_fields(sgid_attr, NULL, 2040 &qp->qplib_qp.smac[0]); 2041 if (rc) 2042 return rc; 2043 2044 nw_type = rdma_gid_attr_network_type(sgid_attr); 2045 switch (nw_type) { 2046 case RDMA_NETWORK_IPV4: 2047 qp->qplib_qp.nw_type = 2048 CMDQ_MODIFY_QP_NETWORK_TYPE_ROCEV2_IPV4; 2049 break; 2050 case RDMA_NETWORK_IPV6: 2051 qp->qplib_qp.nw_type = 2052 CMDQ_MODIFY_QP_NETWORK_TYPE_ROCEV2_IPV6; 2053 break; 2054 default: 2055 qp->qplib_qp.nw_type = 2056 CMDQ_MODIFY_QP_NETWORK_TYPE_ROCEV1; 2057 break; 2058 } 2059 } 2060 2061 if (qp_attr->qp_state == IB_QPS_RTR) { 2062 enum ib_mtu qpmtu; 2063 2064 qpmtu = iboe_get_mtu(rdev->netdev->mtu); 2065 if (qp_attr_mask & IB_QP_PATH_MTU) { 2066 if (ib_mtu_enum_to_int(qp_attr->path_mtu) > 2067 ib_mtu_enum_to_int(qpmtu)) 2068 return -EINVAL; 2069 qpmtu = qp_attr->path_mtu; 2070 } 2071 2072 qp->qplib_qp.modify_flags |= CMDQ_MODIFY_QP_MODIFY_MASK_PATH_MTU; 2073 qp->qplib_qp.path_mtu = __from_ib_mtu(qpmtu); 2074 qp->qplib_qp.mtu = ib_mtu_enum_to_int(qpmtu); 2075 } 2076 2077 if (qp_attr_mask & IB_QP_TIMEOUT) { 2078 qp->qplib_qp.modify_flags |= CMDQ_MODIFY_QP_MODIFY_MASK_TIMEOUT; 2079 qp->qplib_qp.timeout = qp_attr->timeout; 2080 } 2081 if (qp_attr_mask & IB_QP_RETRY_CNT) { 2082 qp->qplib_qp.modify_flags |= 2083 CMDQ_MODIFY_QP_MODIFY_MASK_RETRY_CNT; 2084 qp->qplib_qp.retry_cnt = qp_attr->retry_cnt; 2085 } 2086 if (qp_attr_mask & IB_QP_RNR_RETRY) { 2087 qp->qplib_qp.modify_flags |= 2088 CMDQ_MODIFY_QP_MODIFY_MASK_RNR_RETRY; 2089 qp->qplib_qp.rnr_retry = qp_attr->rnr_retry; 2090 } 2091 if (qp_attr_mask & IB_QP_MIN_RNR_TIMER) { 2092 qp->qplib_qp.modify_flags |= 2093 CMDQ_MODIFY_QP_MODIFY_MASK_MIN_RNR_TIMER; 2094 qp->qplib_qp.min_rnr_timer = qp_attr->min_rnr_timer; 2095 } 2096 if (qp_attr_mask & IB_QP_RQ_PSN) { 2097 qp->qplib_qp.modify_flags |= CMDQ_MODIFY_QP_MODIFY_MASK_RQ_PSN; 2098 qp->qplib_qp.rq.psn = qp_attr->rq_psn; 2099 } 2100 if (qp_attr_mask & IB_QP_MAX_QP_RD_ATOMIC) { 2101 qp->qplib_qp.modify_flags |= 2102 CMDQ_MODIFY_QP_MODIFY_MASK_MAX_RD_ATOMIC; 2103 /* Cap the max_rd_atomic to device max */ 2104 qp->qplib_qp.max_rd_atomic = min_t(u32, qp_attr->max_rd_atomic, 2105 dev_attr->max_qp_rd_atom); 2106 } 2107 if (qp_attr_mask & IB_QP_SQ_PSN) { 2108 qp->qplib_qp.modify_flags |= CMDQ_MODIFY_QP_MODIFY_MASK_SQ_PSN; 2109 qp->qplib_qp.sq.psn = qp_attr->sq_psn; 2110 } 2111 if (qp_attr_mask & IB_QP_MAX_DEST_RD_ATOMIC) { 2112 if (qp_attr->max_dest_rd_atomic > 2113 dev_attr->max_qp_init_rd_atom) { 2114 ibdev_err(&rdev->ibdev, 2115 "max_dest_rd_atomic requested%d is > dev_max%d", 2116 qp_attr->max_dest_rd_atomic, 2117 dev_attr->max_qp_init_rd_atom); 2118 return -EINVAL; 2119 } 2120 2121 qp->qplib_qp.modify_flags |= 2122 CMDQ_MODIFY_QP_MODIFY_MASK_MAX_DEST_RD_ATOMIC; 2123 qp->qplib_qp.max_dest_rd_atomic = qp_attr->max_dest_rd_atomic; 2124 } 2125 if (qp_attr_mask & IB_QP_CAP) { 2126 struct bnxt_re_ucontext *uctx = 2127 rdma_udata_to_drv_context(udata, struct bnxt_re_ucontext, ib_uctx); 2128 2129 qp->qplib_qp.modify_flags |= 2130 CMDQ_MODIFY_QP_MODIFY_MASK_SQ_SIZE | 2131 CMDQ_MODIFY_QP_MODIFY_MASK_RQ_SIZE | 2132 CMDQ_MODIFY_QP_MODIFY_MASK_SQ_SGE | 2133 CMDQ_MODIFY_QP_MODIFY_MASK_RQ_SGE | 2134 CMDQ_MODIFY_QP_MODIFY_MASK_MAX_INLINE_DATA; 2135 if ((qp_attr->cap.max_send_wr >= dev_attr->max_qp_wqes) || 2136 (qp_attr->cap.max_recv_wr >= dev_attr->max_qp_wqes) || 2137 (qp_attr->cap.max_send_sge >= dev_attr->max_qp_sges) || 2138 (qp_attr->cap.max_recv_sge >= dev_attr->max_qp_sges) || 2139 (qp_attr->cap.max_inline_data >= 2140 dev_attr->max_inline_data)) { 2141 ibdev_err(&rdev->ibdev, 2142 "Create QP failed - max exceeded"); 2143 return -EINVAL; 2144 } 2145 entries = bnxt_re_init_depth(qp_attr->cap.max_send_wr, uctx); 2146 qp->qplib_qp.sq.max_wqe = min_t(u32, entries, 2147 dev_attr->max_qp_wqes + 1); 2148 qp->qplib_qp.sq.q_full_delta = qp->qplib_qp.sq.max_wqe - 2149 qp_attr->cap.max_send_wr; 2150 /* 2151 * Reserving one slot for Phantom WQE. Some application can 2152 * post one extra entry in this case. Allowing this to avoid 2153 * unexpected Queue full condition 2154 */ 2155 qp->qplib_qp.sq.q_full_delta -= 1; 2156 qp->qplib_qp.sq.max_sge = qp_attr->cap.max_send_sge; 2157 if (qp->qplib_qp.rq.max_wqe) { 2158 entries = bnxt_re_init_depth(qp_attr->cap.max_recv_wr, uctx); 2159 qp->qplib_qp.rq.max_wqe = 2160 min_t(u32, entries, dev_attr->max_qp_wqes + 1); 2161 qp->qplib_qp.rq.max_sw_wqe = qp->qplib_qp.rq.max_wqe; 2162 qp->qplib_qp.rq.q_full_delta = qp->qplib_qp.rq.max_wqe - 2163 qp_attr->cap.max_recv_wr; 2164 qp->qplib_qp.rq.max_sge = qp_attr->cap.max_recv_sge; 2165 } else { 2166 /* SRQ was used prior, just ignore the RQ caps */ 2167 } 2168 } 2169 if (qp_attr_mask & IB_QP_DEST_QPN) { 2170 qp->qplib_qp.modify_flags |= 2171 CMDQ_MODIFY_QP_MODIFY_MASK_DEST_QP_ID; 2172 qp->qplib_qp.dest_qpn = qp_attr->dest_qp_num; 2173 } 2174 rc = bnxt_qplib_modify_qp(&rdev->qplib_res, &qp->qplib_qp); 2175 if (rc) { 2176 ibdev_err(&rdev->ibdev, "Failed to modify HW QP"); 2177 return rc; 2178 } 2179 if (ib_qp->qp_type == IB_QPT_GSI && rdev->gsi_ctx.gsi_sqp) 2180 rc = bnxt_re_modify_shadow_qp(rdev, qp, qp_attr_mask); 2181 return rc; 2182 } 2183 2184 int bnxt_re_query_qp(struct ib_qp *ib_qp, struct ib_qp_attr *qp_attr, 2185 int qp_attr_mask, struct ib_qp_init_attr *qp_init_attr) 2186 { 2187 struct bnxt_re_qp *qp = container_of(ib_qp, struct bnxt_re_qp, ib_qp); 2188 struct bnxt_re_dev *rdev = qp->rdev; 2189 struct bnxt_qplib_qp *qplib_qp; 2190 int rc; 2191 2192 qplib_qp = kzalloc(sizeof(*qplib_qp), GFP_KERNEL); 2193 if (!qplib_qp) 2194 return -ENOMEM; 2195 2196 qplib_qp->id = qp->qplib_qp.id; 2197 qplib_qp->ah.host_sgid_index = qp->qplib_qp.ah.host_sgid_index; 2198 2199 rc = bnxt_qplib_query_qp(&rdev->qplib_res, qplib_qp); 2200 if (rc) { 2201 ibdev_err(&rdev->ibdev, "Failed to query HW QP"); 2202 goto out; 2203 } 2204 qp_attr->qp_state = __to_ib_qp_state(qplib_qp->state); 2205 qp_attr->cur_qp_state = __to_ib_qp_state(qplib_qp->cur_qp_state); 2206 qp_attr->en_sqd_async_notify = qplib_qp->en_sqd_async_notify ? 1 : 0; 2207 qp_attr->qp_access_flags = __to_ib_access_flags(qplib_qp->access); 2208 qp_attr->pkey_index = qplib_qp->pkey_index; 2209 qp_attr->qkey = qplib_qp->qkey; 2210 qp_attr->ah_attr.type = RDMA_AH_ATTR_TYPE_ROCE; 2211 rdma_ah_set_grh(&qp_attr->ah_attr, NULL, qplib_qp->ah.flow_label, 2212 qplib_qp->ah.host_sgid_index, 2213 qplib_qp->ah.hop_limit, 2214 qplib_qp->ah.traffic_class); 2215 rdma_ah_set_dgid_raw(&qp_attr->ah_attr, qplib_qp->ah.dgid.data); 2216 rdma_ah_set_sl(&qp_attr->ah_attr, qplib_qp->ah.sl); 2217 ether_addr_copy(qp_attr->ah_attr.roce.dmac, qplib_qp->ah.dmac); 2218 qp_attr->path_mtu = __to_ib_mtu(qplib_qp->path_mtu); 2219 qp_attr->timeout = qplib_qp->timeout; 2220 qp_attr->retry_cnt = qplib_qp->retry_cnt; 2221 qp_attr->rnr_retry = qplib_qp->rnr_retry; 2222 qp_attr->min_rnr_timer = qplib_qp->min_rnr_timer; 2223 qp_attr->port_num = __to_ib_port_num(qplib_qp->port_id); 2224 qp_attr->rq_psn = qplib_qp->rq.psn; 2225 qp_attr->max_rd_atomic = qplib_qp->max_rd_atomic; 2226 qp_attr->sq_psn = qplib_qp->sq.psn; 2227 qp_attr->max_dest_rd_atomic = qplib_qp->max_dest_rd_atomic; 2228 qp_init_attr->sq_sig_type = qplib_qp->sig_type ? IB_SIGNAL_ALL_WR : 2229 IB_SIGNAL_REQ_WR; 2230 qp_attr->dest_qp_num = qplib_qp->dest_qpn; 2231 2232 qp_attr->cap.max_send_wr = qp->qplib_qp.sq.max_wqe; 2233 qp_attr->cap.max_send_sge = qp->qplib_qp.sq.max_sge; 2234 qp_attr->cap.max_recv_wr = qp->qplib_qp.rq.max_wqe; 2235 qp_attr->cap.max_recv_sge = qp->qplib_qp.rq.max_sge; 2236 qp_attr->cap.max_inline_data = qp->qplib_qp.max_inline_data; 2237 qp_init_attr->cap = qp_attr->cap; 2238 2239 out: 2240 kfree(qplib_qp); 2241 return rc; 2242 } 2243 2244 /* Routine for sending QP1 packets for RoCE V1 an V2 2245 */ 2246 static int bnxt_re_build_qp1_send_v2(struct bnxt_re_qp *qp, 2247 const struct ib_send_wr *wr, 2248 struct bnxt_qplib_swqe *wqe, 2249 int payload_size) 2250 { 2251 struct bnxt_re_ah *ah = container_of(ud_wr(wr)->ah, struct bnxt_re_ah, 2252 ib_ah); 2253 struct bnxt_qplib_ah *qplib_ah = &ah->qplib_ah; 2254 const struct ib_gid_attr *sgid_attr = ah->ib_ah.sgid_attr; 2255 struct bnxt_qplib_sge sge; 2256 u8 nw_type; 2257 u16 ether_type; 2258 union ib_gid dgid; 2259 bool is_eth = false; 2260 bool is_vlan = false; 2261 bool is_grh = false; 2262 bool is_udp = false; 2263 u8 ip_version = 0; 2264 u16 vlan_id = 0xFFFF; 2265 void *buf; 2266 int i, rc; 2267 2268 memset(&qp->qp1_hdr, 0, sizeof(qp->qp1_hdr)); 2269 2270 rc = rdma_read_gid_l2_fields(sgid_attr, &vlan_id, NULL); 2271 if (rc) 2272 return rc; 2273 2274 /* Get network header type for this GID */ 2275 nw_type = rdma_gid_attr_network_type(sgid_attr); 2276 switch (nw_type) { 2277 case RDMA_NETWORK_IPV4: 2278 nw_type = BNXT_RE_ROCEV2_IPV4_PACKET; 2279 break; 2280 case RDMA_NETWORK_IPV6: 2281 nw_type = BNXT_RE_ROCEV2_IPV6_PACKET; 2282 break; 2283 default: 2284 nw_type = BNXT_RE_ROCE_V1_PACKET; 2285 break; 2286 } 2287 memcpy(&dgid.raw, &qplib_ah->dgid, 16); 2288 is_udp = sgid_attr->gid_type == IB_GID_TYPE_ROCE_UDP_ENCAP; 2289 if (is_udp) { 2290 if (ipv6_addr_v4mapped((struct in6_addr *)&sgid_attr->gid)) { 2291 ip_version = 4; 2292 ether_type = ETH_P_IP; 2293 } else { 2294 ip_version = 6; 2295 ether_type = ETH_P_IPV6; 2296 } 2297 is_grh = false; 2298 } else { 2299 ether_type = ETH_P_IBOE; 2300 is_grh = true; 2301 } 2302 2303 is_eth = true; 2304 is_vlan = vlan_id && (vlan_id < 0x1000); 2305 2306 ib_ud_header_init(payload_size, !is_eth, is_eth, is_vlan, is_grh, 2307 ip_version, is_udp, 0, &qp->qp1_hdr); 2308 2309 /* ETH */ 2310 ether_addr_copy(qp->qp1_hdr.eth.dmac_h, ah->qplib_ah.dmac); 2311 ether_addr_copy(qp->qp1_hdr.eth.smac_h, qp->qplib_qp.smac); 2312 2313 /* For vlan, check the sgid for vlan existence */ 2314 2315 if (!is_vlan) { 2316 qp->qp1_hdr.eth.type = cpu_to_be16(ether_type); 2317 } else { 2318 qp->qp1_hdr.vlan.type = cpu_to_be16(ether_type); 2319 qp->qp1_hdr.vlan.tag = cpu_to_be16(vlan_id); 2320 } 2321 2322 if (is_grh || (ip_version == 6)) { 2323 memcpy(qp->qp1_hdr.grh.source_gid.raw, sgid_attr->gid.raw, 2324 sizeof(sgid_attr->gid)); 2325 memcpy(qp->qp1_hdr.grh.destination_gid.raw, qplib_ah->dgid.data, 2326 sizeof(sgid_attr->gid)); 2327 qp->qp1_hdr.grh.hop_limit = qplib_ah->hop_limit; 2328 } 2329 2330 if (ip_version == 4) { 2331 qp->qp1_hdr.ip4.tos = 0; 2332 qp->qp1_hdr.ip4.id = 0; 2333 qp->qp1_hdr.ip4.frag_off = htons(IP_DF); 2334 qp->qp1_hdr.ip4.ttl = qplib_ah->hop_limit; 2335 2336 memcpy(&qp->qp1_hdr.ip4.saddr, sgid_attr->gid.raw + 12, 4); 2337 memcpy(&qp->qp1_hdr.ip4.daddr, qplib_ah->dgid.data + 12, 4); 2338 qp->qp1_hdr.ip4.check = ib_ud_ip4_csum(&qp->qp1_hdr); 2339 } 2340 2341 if (is_udp) { 2342 qp->qp1_hdr.udp.dport = htons(ROCE_V2_UDP_DPORT); 2343 qp->qp1_hdr.udp.sport = htons(0x8CD1); 2344 qp->qp1_hdr.udp.csum = 0; 2345 } 2346 2347 /* BTH */ 2348 if (wr->opcode == IB_WR_SEND_WITH_IMM) { 2349 qp->qp1_hdr.bth.opcode = IB_OPCODE_UD_SEND_ONLY_WITH_IMMEDIATE; 2350 qp->qp1_hdr.immediate_present = 1; 2351 } else { 2352 qp->qp1_hdr.bth.opcode = IB_OPCODE_UD_SEND_ONLY; 2353 } 2354 if (wr->send_flags & IB_SEND_SOLICITED) 2355 qp->qp1_hdr.bth.solicited_event = 1; 2356 /* pad_count */ 2357 qp->qp1_hdr.bth.pad_count = (4 - payload_size) & 3; 2358 2359 /* P_key for QP1 is for all members */ 2360 qp->qp1_hdr.bth.pkey = cpu_to_be16(0xFFFF); 2361 qp->qp1_hdr.bth.destination_qpn = IB_QP1; 2362 qp->qp1_hdr.bth.ack_req = 0; 2363 qp->send_psn++; 2364 qp->send_psn &= BTH_PSN_MASK; 2365 qp->qp1_hdr.bth.psn = cpu_to_be32(qp->send_psn); 2366 /* DETH */ 2367 /* Use the priviledged Q_Key for QP1 */ 2368 qp->qp1_hdr.deth.qkey = cpu_to_be32(IB_QP1_QKEY); 2369 qp->qp1_hdr.deth.source_qpn = IB_QP1; 2370 2371 /* Pack the QP1 to the transmit buffer */ 2372 buf = bnxt_qplib_get_qp1_sq_buf(&qp->qplib_qp, &sge); 2373 if (buf) { 2374 ib_ud_header_pack(&qp->qp1_hdr, buf); 2375 for (i = wqe->num_sge; i; i--) { 2376 wqe->sg_list[i].addr = wqe->sg_list[i - 1].addr; 2377 wqe->sg_list[i].lkey = wqe->sg_list[i - 1].lkey; 2378 wqe->sg_list[i].size = wqe->sg_list[i - 1].size; 2379 } 2380 2381 /* 2382 * Max Header buf size for IPV6 RoCE V2 is 86, 2383 * which is same as the QP1 SQ header buffer. 2384 * Header buf size for IPV4 RoCE V2 can be 66. 2385 * ETH(14) + VLAN(4)+ IP(20) + UDP (8) + BTH(20). 2386 * Subtract 20 bytes from QP1 SQ header buf size 2387 */ 2388 if (is_udp && ip_version == 4) 2389 sge.size -= 20; 2390 /* 2391 * Max Header buf size for RoCE V1 is 78. 2392 * ETH(14) + VLAN(4) + GRH(40) + BTH(20). 2393 * Subtract 8 bytes from QP1 SQ header buf size 2394 */ 2395 if (!is_udp) 2396 sge.size -= 8; 2397 2398 /* Subtract 4 bytes for non vlan packets */ 2399 if (!is_vlan) 2400 sge.size -= 4; 2401 2402 wqe->sg_list[0].addr = sge.addr; 2403 wqe->sg_list[0].lkey = sge.lkey; 2404 wqe->sg_list[0].size = sge.size; 2405 wqe->num_sge++; 2406 2407 } else { 2408 ibdev_err(&qp->rdev->ibdev, "QP1 buffer is empty!"); 2409 rc = -ENOMEM; 2410 } 2411 return rc; 2412 } 2413 2414 /* For the MAD layer, it only provides the recv SGE the size of 2415 * ib_grh + MAD datagram. No Ethernet headers, Ethertype, BTH, DETH, 2416 * nor RoCE iCRC. The Cu+ solution must provide buffer for the entire 2417 * receive packet (334 bytes) with no VLAN and then copy the GRH 2418 * and the MAD datagram out to the provided SGE. 2419 */ 2420 static int bnxt_re_build_qp1_shadow_qp_recv(struct bnxt_re_qp *qp, 2421 const struct ib_recv_wr *wr, 2422 struct bnxt_qplib_swqe *wqe, 2423 int payload_size) 2424 { 2425 struct bnxt_re_sqp_entries *sqp_entry; 2426 struct bnxt_qplib_sge ref, sge; 2427 struct bnxt_re_dev *rdev; 2428 u32 rq_prod_index; 2429 2430 rdev = qp->rdev; 2431 2432 rq_prod_index = bnxt_qplib_get_rq_prod_index(&qp->qplib_qp); 2433 2434 if (!bnxt_qplib_get_qp1_rq_buf(&qp->qplib_qp, &sge)) 2435 return -ENOMEM; 2436 2437 /* Create 1 SGE to receive the entire 2438 * ethernet packet 2439 */ 2440 /* Save the reference from ULP */ 2441 ref.addr = wqe->sg_list[0].addr; 2442 ref.lkey = wqe->sg_list[0].lkey; 2443 ref.size = wqe->sg_list[0].size; 2444 2445 sqp_entry = &rdev->gsi_ctx.sqp_tbl[rq_prod_index]; 2446 2447 /* SGE 1 */ 2448 wqe->sg_list[0].addr = sge.addr; 2449 wqe->sg_list[0].lkey = sge.lkey; 2450 wqe->sg_list[0].size = BNXT_QPLIB_MAX_QP1_RQ_HDR_SIZE_V2; 2451 sge.size -= wqe->sg_list[0].size; 2452 2453 sqp_entry->sge.addr = ref.addr; 2454 sqp_entry->sge.lkey = ref.lkey; 2455 sqp_entry->sge.size = ref.size; 2456 /* Store the wrid for reporting completion */ 2457 sqp_entry->wrid = wqe->wr_id; 2458 /* change the wqe->wrid to table index */ 2459 wqe->wr_id = rq_prod_index; 2460 return 0; 2461 } 2462 2463 static int is_ud_qp(struct bnxt_re_qp *qp) 2464 { 2465 return (qp->qplib_qp.type == CMDQ_CREATE_QP_TYPE_UD || 2466 qp->qplib_qp.type == CMDQ_CREATE_QP_TYPE_GSI); 2467 } 2468 2469 static int bnxt_re_build_send_wqe(struct bnxt_re_qp *qp, 2470 const struct ib_send_wr *wr, 2471 struct bnxt_qplib_swqe *wqe) 2472 { 2473 struct bnxt_re_ah *ah = NULL; 2474 2475 if (is_ud_qp(qp)) { 2476 ah = container_of(ud_wr(wr)->ah, struct bnxt_re_ah, ib_ah); 2477 wqe->send.q_key = ud_wr(wr)->remote_qkey; 2478 wqe->send.dst_qp = ud_wr(wr)->remote_qpn; 2479 wqe->send.avid = ah->qplib_ah.id; 2480 } 2481 switch (wr->opcode) { 2482 case IB_WR_SEND: 2483 wqe->type = BNXT_QPLIB_SWQE_TYPE_SEND; 2484 break; 2485 case IB_WR_SEND_WITH_IMM: 2486 wqe->type = BNXT_QPLIB_SWQE_TYPE_SEND_WITH_IMM; 2487 wqe->send.imm_data = be32_to_cpu(wr->ex.imm_data); 2488 break; 2489 case IB_WR_SEND_WITH_INV: 2490 wqe->type = BNXT_QPLIB_SWQE_TYPE_SEND_WITH_INV; 2491 wqe->send.inv_key = wr->ex.invalidate_rkey; 2492 break; 2493 default: 2494 return -EINVAL; 2495 } 2496 if (wr->send_flags & IB_SEND_SIGNALED) 2497 wqe->flags |= BNXT_QPLIB_SWQE_FLAGS_SIGNAL_COMP; 2498 if (wr->send_flags & IB_SEND_FENCE) 2499 wqe->flags |= BNXT_QPLIB_SWQE_FLAGS_UC_FENCE; 2500 if (wr->send_flags & IB_SEND_SOLICITED) 2501 wqe->flags |= BNXT_QPLIB_SWQE_FLAGS_SOLICIT_EVENT; 2502 if (wr->send_flags & IB_SEND_INLINE) 2503 wqe->flags |= BNXT_QPLIB_SWQE_FLAGS_INLINE; 2504 2505 return 0; 2506 } 2507 2508 static int bnxt_re_build_rdma_wqe(const struct ib_send_wr *wr, 2509 struct bnxt_qplib_swqe *wqe) 2510 { 2511 switch (wr->opcode) { 2512 case IB_WR_RDMA_WRITE: 2513 wqe->type = BNXT_QPLIB_SWQE_TYPE_RDMA_WRITE; 2514 break; 2515 case IB_WR_RDMA_WRITE_WITH_IMM: 2516 wqe->type = BNXT_QPLIB_SWQE_TYPE_RDMA_WRITE_WITH_IMM; 2517 wqe->rdma.imm_data = be32_to_cpu(wr->ex.imm_data); 2518 break; 2519 case IB_WR_RDMA_READ: 2520 wqe->type = BNXT_QPLIB_SWQE_TYPE_RDMA_READ; 2521 wqe->rdma.inv_key = wr->ex.invalidate_rkey; 2522 break; 2523 default: 2524 return -EINVAL; 2525 } 2526 wqe->rdma.remote_va = rdma_wr(wr)->remote_addr; 2527 wqe->rdma.r_key = rdma_wr(wr)->rkey; 2528 if (wr->send_flags & IB_SEND_SIGNALED) 2529 wqe->flags |= BNXT_QPLIB_SWQE_FLAGS_SIGNAL_COMP; 2530 if (wr->send_flags & IB_SEND_FENCE) 2531 wqe->flags |= BNXT_QPLIB_SWQE_FLAGS_UC_FENCE; 2532 if (wr->send_flags & IB_SEND_SOLICITED) 2533 wqe->flags |= BNXT_QPLIB_SWQE_FLAGS_SOLICIT_EVENT; 2534 if (wr->send_flags & IB_SEND_INLINE) 2535 wqe->flags |= BNXT_QPLIB_SWQE_FLAGS_INLINE; 2536 2537 return 0; 2538 } 2539 2540 static int bnxt_re_build_atomic_wqe(const struct ib_send_wr *wr, 2541 struct bnxt_qplib_swqe *wqe) 2542 { 2543 switch (wr->opcode) { 2544 case IB_WR_ATOMIC_CMP_AND_SWP: 2545 wqe->type = BNXT_QPLIB_SWQE_TYPE_ATOMIC_CMP_AND_SWP; 2546 wqe->atomic.cmp_data = atomic_wr(wr)->compare_add; 2547 wqe->atomic.swap_data = atomic_wr(wr)->swap; 2548 break; 2549 case IB_WR_ATOMIC_FETCH_AND_ADD: 2550 wqe->type = BNXT_QPLIB_SWQE_TYPE_ATOMIC_FETCH_AND_ADD; 2551 wqe->atomic.cmp_data = atomic_wr(wr)->compare_add; 2552 break; 2553 default: 2554 return -EINVAL; 2555 } 2556 wqe->atomic.remote_va = atomic_wr(wr)->remote_addr; 2557 wqe->atomic.r_key = atomic_wr(wr)->rkey; 2558 if (wr->send_flags & IB_SEND_SIGNALED) 2559 wqe->flags |= BNXT_QPLIB_SWQE_FLAGS_SIGNAL_COMP; 2560 if (wr->send_flags & IB_SEND_FENCE) 2561 wqe->flags |= BNXT_QPLIB_SWQE_FLAGS_UC_FENCE; 2562 if (wr->send_flags & IB_SEND_SOLICITED) 2563 wqe->flags |= BNXT_QPLIB_SWQE_FLAGS_SOLICIT_EVENT; 2564 return 0; 2565 } 2566 2567 static int bnxt_re_build_inv_wqe(const struct ib_send_wr *wr, 2568 struct bnxt_qplib_swqe *wqe) 2569 { 2570 wqe->type = BNXT_QPLIB_SWQE_TYPE_LOCAL_INV; 2571 wqe->local_inv.inv_l_key = wr->ex.invalidate_rkey; 2572 2573 if (wr->send_flags & IB_SEND_SIGNALED) 2574 wqe->flags |= BNXT_QPLIB_SWQE_FLAGS_SIGNAL_COMP; 2575 if (wr->send_flags & IB_SEND_SOLICITED) 2576 wqe->flags |= BNXT_QPLIB_SWQE_FLAGS_SOLICIT_EVENT; 2577 2578 return 0; 2579 } 2580 2581 static int bnxt_re_build_reg_wqe(const struct ib_reg_wr *wr, 2582 struct bnxt_qplib_swqe *wqe) 2583 { 2584 struct bnxt_re_mr *mr = container_of(wr->mr, struct bnxt_re_mr, ib_mr); 2585 struct bnxt_qplib_frpl *qplib_frpl = &mr->qplib_frpl; 2586 int access = wr->access; 2587 2588 wqe->frmr.pbl_ptr = (__le64 *)qplib_frpl->hwq.pbl_ptr[0]; 2589 wqe->frmr.pbl_dma_ptr = qplib_frpl->hwq.pbl_dma_ptr[0]; 2590 wqe->frmr.page_list = mr->pages; 2591 wqe->frmr.page_list_len = mr->npages; 2592 wqe->frmr.levels = qplib_frpl->hwq.level; 2593 wqe->type = BNXT_QPLIB_SWQE_TYPE_REG_MR; 2594 2595 if (wr->wr.send_flags & IB_SEND_SIGNALED) 2596 wqe->flags |= BNXT_QPLIB_SWQE_FLAGS_SIGNAL_COMP; 2597 2598 if (access & IB_ACCESS_LOCAL_WRITE) 2599 wqe->frmr.access_cntl |= SQ_FR_PMR_ACCESS_CNTL_LOCAL_WRITE; 2600 if (access & IB_ACCESS_REMOTE_READ) 2601 wqe->frmr.access_cntl |= SQ_FR_PMR_ACCESS_CNTL_REMOTE_READ; 2602 if (access & IB_ACCESS_REMOTE_WRITE) 2603 wqe->frmr.access_cntl |= SQ_FR_PMR_ACCESS_CNTL_REMOTE_WRITE; 2604 if (access & IB_ACCESS_REMOTE_ATOMIC) 2605 wqe->frmr.access_cntl |= SQ_FR_PMR_ACCESS_CNTL_REMOTE_ATOMIC; 2606 if (access & IB_ACCESS_MW_BIND) 2607 wqe->frmr.access_cntl |= SQ_FR_PMR_ACCESS_CNTL_WINDOW_BIND; 2608 2609 wqe->frmr.l_key = wr->key; 2610 wqe->frmr.length = wr->mr->length; 2611 wqe->frmr.pbl_pg_sz_log = ilog2(PAGE_SIZE >> PAGE_SHIFT_4K); 2612 wqe->frmr.pg_sz_log = ilog2(wr->mr->page_size >> PAGE_SHIFT_4K); 2613 wqe->frmr.va = wr->mr->iova; 2614 return 0; 2615 } 2616 2617 static int bnxt_re_copy_inline_data(struct bnxt_re_dev *rdev, 2618 const struct ib_send_wr *wr, 2619 struct bnxt_qplib_swqe *wqe) 2620 { 2621 /* Copy the inline data to the data field */ 2622 u8 *in_data; 2623 u32 i, sge_len; 2624 void *sge_addr; 2625 2626 in_data = wqe->inline_data; 2627 for (i = 0; i < wr->num_sge; i++) { 2628 sge_addr = (void *)(unsigned long) 2629 wr->sg_list[i].addr; 2630 sge_len = wr->sg_list[i].length; 2631 2632 if ((sge_len + wqe->inline_len) > 2633 BNXT_QPLIB_SWQE_MAX_INLINE_LENGTH) { 2634 ibdev_err(&rdev->ibdev, 2635 "Inline data size requested > supported value"); 2636 return -EINVAL; 2637 } 2638 sge_len = wr->sg_list[i].length; 2639 2640 memcpy(in_data, sge_addr, sge_len); 2641 in_data += wr->sg_list[i].length; 2642 wqe->inline_len += wr->sg_list[i].length; 2643 } 2644 return wqe->inline_len; 2645 } 2646 2647 static int bnxt_re_copy_wr_payload(struct bnxt_re_dev *rdev, 2648 const struct ib_send_wr *wr, 2649 struct bnxt_qplib_swqe *wqe) 2650 { 2651 int payload_sz = 0; 2652 2653 if (wr->send_flags & IB_SEND_INLINE) 2654 payload_sz = bnxt_re_copy_inline_data(rdev, wr, wqe); 2655 else 2656 payload_sz = bnxt_re_build_sgl(wr->sg_list, wqe->sg_list, 2657 wqe->num_sge); 2658 2659 return payload_sz; 2660 } 2661 2662 static void bnxt_ud_qp_hw_stall_workaround(struct bnxt_re_qp *qp) 2663 { 2664 if ((qp->ib_qp.qp_type == IB_QPT_UD || 2665 qp->ib_qp.qp_type == IB_QPT_GSI || 2666 qp->ib_qp.qp_type == IB_QPT_RAW_ETHERTYPE) && 2667 qp->qplib_qp.wqe_cnt == BNXT_RE_UD_QP_HW_STALL) { 2668 int qp_attr_mask; 2669 struct ib_qp_attr qp_attr; 2670 2671 qp_attr_mask = IB_QP_STATE; 2672 qp_attr.qp_state = IB_QPS_RTS; 2673 bnxt_re_modify_qp(&qp->ib_qp, &qp_attr, qp_attr_mask, NULL); 2674 qp->qplib_qp.wqe_cnt = 0; 2675 } 2676 } 2677 2678 static int bnxt_re_post_send_shadow_qp(struct bnxt_re_dev *rdev, 2679 struct bnxt_re_qp *qp, 2680 const struct ib_send_wr *wr) 2681 { 2682 int rc = 0, payload_sz = 0; 2683 unsigned long flags; 2684 2685 spin_lock_irqsave(&qp->sq_lock, flags); 2686 while (wr) { 2687 struct bnxt_qplib_swqe wqe = {}; 2688 2689 /* Common */ 2690 wqe.num_sge = wr->num_sge; 2691 if (wr->num_sge > qp->qplib_qp.sq.max_sge) { 2692 ibdev_err(&rdev->ibdev, 2693 "Limit exceeded for Send SGEs"); 2694 rc = -EINVAL; 2695 goto bad; 2696 } 2697 2698 payload_sz = bnxt_re_copy_wr_payload(qp->rdev, wr, &wqe); 2699 if (payload_sz < 0) { 2700 rc = -EINVAL; 2701 goto bad; 2702 } 2703 wqe.wr_id = wr->wr_id; 2704 2705 wqe.type = BNXT_QPLIB_SWQE_TYPE_SEND; 2706 2707 rc = bnxt_re_build_send_wqe(qp, wr, &wqe); 2708 if (!rc) 2709 rc = bnxt_qplib_post_send(&qp->qplib_qp, &wqe); 2710 bad: 2711 if (rc) { 2712 ibdev_err(&rdev->ibdev, 2713 "Post send failed opcode = %#x rc = %d", 2714 wr->opcode, rc); 2715 break; 2716 } 2717 wr = wr->next; 2718 } 2719 bnxt_qplib_post_send_db(&qp->qplib_qp); 2720 if (!bnxt_qplib_is_chip_gen_p5_p7(qp->rdev->chip_ctx)) 2721 bnxt_ud_qp_hw_stall_workaround(qp); 2722 spin_unlock_irqrestore(&qp->sq_lock, flags); 2723 return rc; 2724 } 2725 2726 static void bnxt_re_legacy_set_uc_fence(struct bnxt_qplib_swqe *wqe) 2727 { 2728 /* Need unconditional fence for non-wire memory opcode 2729 * to work as expected. 2730 */ 2731 if (wqe->type == BNXT_QPLIB_SWQE_TYPE_LOCAL_INV || 2732 wqe->type == BNXT_QPLIB_SWQE_TYPE_FAST_REG_MR || 2733 wqe->type == BNXT_QPLIB_SWQE_TYPE_REG_MR || 2734 wqe->type == BNXT_QPLIB_SWQE_TYPE_BIND_MW) 2735 wqe->flags |= BNXT_QPLIB_SWQE_FLAGS_UC_FENCE; 2736 } 2737 2738 int bnxt_re_post_send(struct ib_qp *ib_qp, const struct ib_send_wr *wr, 2739 const struct ib_send_wr **bad_wr) 2740 { 2741 struct bnxt_re_qp *qp = container_of(ib_qp, struct bnxt_re_qp, ib_qp); 2742 struct bnxt_qplib_swqe wqe; 2743 int rc = 0, payload_sz = 0; 2744 unsigned long flags; 2745 2746 spin_lock_irqsave(&qp->sq_lock, flags); 2747 while (wr) { 2748 /* House keeping */ 2749 memset(&wqe, 0, sizeof(wqe)); 2750 2751 /* Common */ 2752 wqe.num_sge = wr->num_sge; 2753 if (wr->num_sge > qp->qplib_qp.sq.max_sge) { 2754 ibdev_err(&qp->rdev->ibdev, 2755 "Limit exceeded for Send SGEs"); 2756 rc = -EINVAL; 2757 goto bad; 2758 } 2759 2760 payload_sz = bnxt_re_copy_wr_payload(qp->rdev, wr, &wqe); 2761 if (payload_sz < 0) { 2762 rc = -EINVAL; 2763 goto bad; 2764 } 2765 wqe.wr_id = wr->wr_id; 2766 2767 switch (wr->opcode) { 2768 case IB_WR_SEND: 2769 case IB_WR_SEND_WITH_IMM: 2770 if (qp->qplib_qp.type == CMDQ_CREATE_QP1_TYPE_GSI) { 2771 rc = bnxt_re_build_qp1_send_v2(qp, wr, &wqe, 2772 payload_sz); 2773 if (rc) 2774 goto bad; 2775 wqe.rawqp1.lflags |= 2776 SQ_SEND_RAWETH_QP1_LFLAGS_ROCE_CRC; 2777 } 2778 switch (wr->send_flags) { 2779 case IB_SEND_IP_CSUM: 2780 wqe.rawqp1.lflags |= 2781 SQ_SEND_RAWETH_QP1_LFLAGS_IP_CHKSUM; 2782 break; 2783 default: 2784 break; 2785 } 2786 fallthrough; 2787 case IB_WR_SEND_WITH_INV: 2788 rc = bnxt_re_build_send_wqe(qp, wr, &wqe); 2789 break; 2790 case IB_WR_RDMA_WRITE: 2791 case IB_WR_RDMA_WRITE_WITH_IMM: 2792 case IB_WR_RDMA_READ: 2793 rc = bnxt_re_build_rdma_wqe(wr, &wqe); 2794 break; 2795 case IB_WR_ATOMIC_CMP_AND_SWP: 2796 case IB_WR_ATOMIC_FETCH_AND_ADD: 2797 rc = bnxt_re_build_atomic_wqe(wr, &wqe); 2798 break; 2799 case IB_WR_RDMA_READ_WITH_INV: 2800 ibdev_err(&qp->rdev->ibdev, 2801 "RDMA Read with Invalidate is not supported"); 2802 rc = -EINVAL; 2803 goto bad; 2804 case IB_WR_LOCAL_INV: 2805 rc = bnxt_re_build_inv_wqe(wr, &wqe); 2806 break; 2807 case IB_WR_REG_MR: 2808 rc = bnxt_re_build_reg_wqe(reg_wr(wr), &wqe); 2809 break; 2810 default: 2811 /* Unsupported WRs */ 2812 ibdev_err(&qp->rdev->ibdev, 2813 "WR (%#x) is not supported", wr->opcode); 2814 rc = -EINVAL; 2815 goto bad; 2816 } 2817 if (!rc) { 2818 if (!bnxt_qplib_is_chip_gen_p5_p7(qp->rdev->chip_ctx)) 2819 bnxt_re_legacy_set_uc_fence(&wqe); 2820 rc = bnxt_qplib_post_send(&qp->qplib_qp, &wqe); 2821 } 2822 bad: 2823 if (rc) { 2824 ibdev_err(&qp->rdev->ibdev, 2825 "post_send failed op:%#x qps = %#x rc = %d\n", 2826 wr->opcode, qp->qplib_qp.state, rc); 2827 *bad_wr = wr; 2828 break; 2829 } 2830 wr = wr->next; 2831 } 2832 bnxt_qplib_post_send_db(&qp->qplib_qp); 2833 if (!bnxt_qplib_is_chip_gen_p5_p7(qp->rdev->chip_ctx)) 2834 bnxt_ud_qp_hw_stall_workaround(qp); 2835 spin_unlock_irqrestore(&qp->sq_lock, flags); 2836 2837 return rc; 2838 } 2839 2840 static int bnxt_re_post_recv_shadow_qp(struct bnxt_re_dev *rdev, 2841 struct bnxt_re_qp *qp, 2842 const struct ib_recv_wr *wr) 2843 { 2844 struct bnxt_qplib_swqe wqe; 2845 int rc = 0; 2846 2847 while (wr) { 2848 /* House keeping */ 2849 memset(&wqe, 0, sizeof(wqe)); 2850 2851 /* Common */ 2852 wqe.num_sge = wr->num_sge; 2853 if (wr->num_sge > qp->qplib_qp.rq.max_sge) { 2854 ibdev_err(&rdev->ibdev, 2855 "Limit exceeded for Receive SGEs"); 2856 rc = -EINVAL; 2857 break; 2858 } 2859 bnxt_re_build_sgl(wr->sg_list, wqe.sg_list, wr->num_sge); 2860 wqe.wr_id = wr->wr_id; 2861 wqe.type = BNXT_QPLIB_SWQE_TYPE_RECV; 2862 2863 rc = bnxt_qplib_post_recv(&qp->qplib_qp, &wqe); 2864 if (rc) 2865 break; 2866 2867 wr = wr->next; 2868 } 2869 if (!rc) 2870 bnxt_qplib_post_recv_db(&qp->qplib_qp); 2871 return rc; 2872 } 2873 2874 int bnxt_re_post_recv(struct ib_qp *ib_qp, const struct ib_recv_wr *wr, 2875 const struct ib_recv_wr **bad_wr) 2876 { 2877 struct bnxt_re_qp *qp = container_of(ib_qp, struct bnxt_re_qp, ib_qp); 2878 struct bnxt_qplib_swqe wqe; 2879 int rc = 0, payload_sz = 0; 2880 unsigned long flags; 2881 u32 count = 0; 2882 2883 spin_lock_irqsave(&qp->rq_lock, flags); 2884 while (wr) { 2885 /* House keeping */ 2886 memset(&wqe, 0, sizeof(wqe)); 2887 2888 /* Common */ 2889 wqe.num_sge = wr->num_sge; 2890 if (wr->num_sge > qp->qplib_qp.rq.max_sge) { 2891 ibdev_err(&qp->rdev->ibdev, 2892 "Limit exceeded for Receive SGEs"); 2893 rc = -EINVAL; 2894 *bad_wr = wr; 2895 break; 2896 } 2897 2898 payload_sz = bnxt_re_build_sgl(wr->sg_list, wqe.sg_list, 2899 wr->num_sge); 2900 wqe.wr_id = wr->wr_id; 2901 wqe.type = BNXT_QPLIB_SWQE_TYPE_RECV; 2902 2903 if (ib_qp->qp_type == IB_QPT_GSI && 2904 qp->qplib_qp.type != CMDQ_CREATE_QP_TYPE_GSI) 2905 rc = bnxt_re_build_qp1_shadow_qp_recv(qp, wr, &wqe, 2906 payload_sz); 2907 if (!rc) 2908 rc = bnxt_qplib_post_recv(&qp->qplib_qp, &wqe); 2909 if (rc) { 2910 *bad_wr = wr; 2911 break; 2912 } 2913 2914 /* Ring DB if the RQEs posted reaches a threshold value */ 2915 if (++count >= BNXT_RE_RQ_WQE_THRESHOLD) { 2916 bnxt_qplib_post_recv_db(&qp->qplib_qp); 2917 count = 0; 2918 } 2919 2920 wr = wr->next; 2921 } 2922 2923 if (count) 2924 bnxt_qplib_post_recv_db(&qp->qplib_qp); 2925 2926 spin_unlock_irqrestore(&qp->rq_lock, flags); 2927 2928 return rc; 2929 } 2930 2931 /* Completion Queues */ 2932 int bnxt_re_destroy_cq(struct ib_cq *ib_cq, struct ib_udata *udata) 2933 { 2934 struct bnxt_re_cq *cq; 2935 struct bnxt_qplib_nq *nq; 2936 struct bnxt_re_dev *rdev; 2937 2938 cq = container_of(ib_cq, struct bnxt_re_cq, ib_cq); 2939 rdev = cq->rdev; 2940 nq = cq->qplib_cq.nq; 2941 2942 bnxt_qplib_destroy_cq(&rdev->qplib_res, &cq->qplib_cq); 2943 ib_umem_release(cq->umem); 2944 2945 atomic_dec(&rdev->stats.res.cq_count); 2946 nq->budget--; 2947 kfree(cq->cql); 2948 return 0; 2949 } 2950 2951 int bnxt_re_create_cq(struct ib_cq *ibcq, const struct ib_cq_init_attr *attr, 2952 struct ib_udata *udata) 2953 { 2954 struct bnxt_re_cq *cq = container_of(ibcq, struct bnxt_re_cq, ib_cq); 2955 struct bnxt_re_dev *rdev = to_bnxt_re_dev(ibcq->device, ibdev); 2956 struct bnxt_re_ucontext *uctx = 2957 rdma_udata_to_drv_context(udata, struct bnxt_re_ucontext, ib_uctx); 2958 struct bnxt_qplib_dev_attr *dev_attr = &rdev->dev_attr; 2959 int rc, entries; 2960 int cqe = attr->cqe; 2961 struct bnxt_qplib_nq *nq = NULL; 2962 unsigned int nq_alloc_cnt; 2963 u32 active_cqs; 2964 2965 if (attr->flags) 2966 return -EOPNOTSUPP; 2967 2968 /* Validate CQ fields */ 2969 if (cqe < 1 || cqe > dev_attr->max_cq_wqes) { 2970 ibdev_err(&rdev->ibdev, "Failed to create CQ -max exceeded"); 2971 return -EINVAL; 2972 } 2973 2974 cq->rdev = rdev; 2975 cq->qplib_cq.cq_handle = (u64)(unsigned long)(&cq->qplib_cq); 2976 2977 entries = bnxt_re_init_depth(cqe + 1, uctx); 2978 if (entries > dev_attr->max_cq_wqes + 1) 2979 entries = dev_attr->max_cq_wqes + 1; 2980 2981 cq->qplib_cq.sg_info.pgsize = PAGE_SIZE; 2982 cq->qplib_cq.sg_info.pgshft = PAGE_SHIFT; 2983 if (udata) { 2984 struct bnxt_re_cq_req req; 2985 if (ib_copy_from_udata(&req, udata, sizeof(req))) { 2986 rc = -EFAULT; 2987 goto fail; 2988 } 2989 2990 cq->umem = ib_umem_get(&rdev->ibdev, req.cq_va, 2991 entries * sizeof(struct cq_base), 2992 IB_ACCESS_LOCAL_WRITE); 2993 if (IS_ERR(cq->umem)) { 2994 rc = PTR_ERR(cq->umem); 2995 goto fail; 2996 } 2997 cq->qplib_cq.sg_info.umem = cq->umem; 2998 cq->qplib_cq.dpi = &uctx->dpi; 2999 } else { 3000 cq->max_cql = min_t(u32, entries, MAX_CQL_PER_POLL); 3001 cq->cql = kcalloc(cq->max_cql, sizeof(struct bnxt_qplib_cqe), 3002 GFP_KERNEL); 3003 if (!cq->cql) { 3004 rc = -ENOMEM; 3005 goto fail; 3006 } 3007 3008 cq->qplib_cq.dpi = &rdev->dpi_privileged; 3009 } 3010 /* 3011 * Allocating the NQ in a round robin fashion. nq_alloc_cnt is a 3012 * used for getting the NQ index. 3013 */ 3014 nq_alloc_cnt = atomic_inc_return(&rdev->nq_alloc_cnt); 3015 nq = &rdev->nq[nq_alloc_cnt % (rdev->num_msix - 1)]; 3016 cq->qplib_cq.max_wqe = entries; 3017 cq->qplib_cq.cnq_hw_ring_id = nq->ring_id; 3018 cq->qplib_cq.nq = nq; 3019 3020 rc = bnxt_qplib_create_cq(&rdev->qplib_res, &cq->qplib_cq); 3021 if (rc) { 3022 ibdev_err(&rdev->ibdev, "Failed to create HW CQ"); 3023 goto fail; 3024 } 3025 3026 cq->ib_cq.cqe = entries; 3027 cq->cq_period = cq->qplib_cq.period; 3028 nq->budget++; 3029 3030 active_cqs = atomic_inc_return(&rdev->stats.res.cq_count); 3031 if (active_cqs > rdev->stats.res.cq_watermark) 3032 rdev->stats.res.cq_watermark = active_cqs; 3033 spin_lock_init(&cq->cq_lock); 3034 3035 if (udata) { 3036 struct bnxt_re_cq_resp resp; 3037 3038 resp.cqid = cq->qplib_cq.id; 3039 resp.tail = cq->qplib_cq.hwq.cons; 3040 resp.phase = cq->qplib_cq.period; 3041 resp.rsvd = 0; 3042 rc = ib_copy_to_udata(udata, &resp, sizeof(resp)); 3043 if (rc) { 3044 ibdev_err(&rdev->ibdev, "Failed to copy CQ udata"); 3045 bnxt_qplib_destroy_cq(&rdev->qplib_res, &cq->qplib_cq); 3046 goto c2fail; 3047 } 3048 } 3049 3050 return 0; 3051 3052 c2fail: 3053 ib_umem_release(cq->umem); 3054 fail: 3055 kfree(cq->cql); 3056 return rc; 3057 } 3058 3059 static void bnxt_re_resize_cq_complete(struct bnxt_re_cq *cq) 3060 { 3061 struct bnxt_re_dev *rdev = cq->rdev; 3062 3063 bnxt_qplib_resize_cq_complete(&rdev->qplib_res, &cq->qplib_cq); 3064 3065 cq->qplib_cq.max_wqe = cq->resize_cqe; 3066 if (cq->resize_umem) { 3067 ib_umem_release(cq->umem); 3068 cq->umem = cq->resize_umem; 3069 cq->resize_umem = NULL; 3070 cq->resize_cqe = 0; 3071 } 3072 } 3073 3074 int bnxt_re_resize_cq(struct ib_cq *ibcq, int cqe, struct ib_udata *udata) 3075 { 3076 struct bnxt_qplib_sg_info sg_info = {}; 3077 struct bnxt_qplib_dpi *orig_dpi = NULL; 3078 struct bnxt_qplib_dev_attr *dev_attr; 3079 struct bnxt_re_ucontext *uctx = NULL; 3080 struct bnxt_re_resize_cq_req req; 3081 struct bnxt_re_dev *rdev; 3082 struct bnxt_re_cq *cq; 3083 int rc, entries; 3084 3085 cq = container_of(ibcq, struct bnxt_re_cq, ib_cq); 3086 rdev = cq->rdev; 3087 dev_attr = &rdev->dev_attr; 3088 if (!ibcq->uobject) { 3089 ibdev_err(&rdev->ibdev, "Kernel CQ Resize not supported"); 3090 return -EOPNOTSUPP; 3091 } 3092 3093 if (cq->resize_umem) { 3094 ibdev_err(&rdev->ibdev, "Resize CQ %#x failed - Busy", 3095 cq->qplib_cq.id); 3096 return -EBUSY; 3097 } 3098 3099 /* Check the requested cq depth out of supported depth */ 3100 if (cqe < 1 || cqe > dev_attr->max_cq_wqes) { 3101 ibdev_err(&rdev->ibdev, "Resize CQ %#x failed - out of range cqe %d", 3102 cq->qplib_cq.id, cqe); 3103 return -EINVAL; 3104 } 3105 3106 uctx = rdma_udata_to_drv_context(udata, struct bnxt_re_ucontext, ib_uctx); 3107 entries = bnxt_re_init_depth(cqe + 1, uctx); 3108 if (entries > dev_attr->max_cq_wqes + 1) 3109 entries = dev_attr->max_cq_wqes + 1; 3110 3111 /* uverbs consumer */ 3112 if (ib_copy_from_udata(&req, udata, sizeof(req))) { 3113 rc = -EFAULT; 3114 goto fail; 3115 } 3116 3117 cq->resize_umem = ib_umem_get(&rdev->ibdev, req.cq_va, 3118 entries * sizeof(struct cq_base), 3119 IB_ACCESS_LOCAL_WRITE); 3120 if (IS_ERR(cq->resize_umem)) { 3121 rc = PTR_ERR(cq->resize_umem); 3122 cq->resize_umem = NULL; 3123 ibdev_err(&rdev->ibdev, "%s: ib_umem_get failed! rc = %d\n", 3124 __func__, rc); 3125 goto fail; 3126 } 3127 cq->resize_cqe = entries; 3128 memcpy(&sg_info, &cq->qplib_cq.sg_info, sizeof(sg_info)); 3129 orig_dpi = cq->qplib_cq.dpi; 3130 3131 cq->qplib_cq.sg_info.umem = cq->resize_umem; 3132 cq->qplib_cq.sg_info.pgsize = PAGE_SIZE; 3133 cq->qplib_cq.sg_info.pgshft = PAGE_SHIFT; 3134 cq->qplib_cq.dpi = &uctx->dpi; 3135 3136 rc = bnxt_qplib_resize_cq(&rdev->qplib_res, &cq->qplib_cq, entries); 3137 if (rc) { 3138 ibdev_err(&rdev->ibdev, "Resize HW CQ %#x failed!", 3139 cq->qplib_cq.id); 3140 goto fail; 3141 } 3142 3143 cq->ib_cq.cqe = cq->resize_cqe; 3144 atomic_inc(&rdev->stats.res.resize_count); 3145 3146 return 0; 3147 3148 fail: 3149 if (cq->resize_umem) { 3150 ib_umem_release(cq->resize_umem); 3151 cq->resize_umem = NULL; 3152 cq->resize_cqe = 0; 3153 memcpy(&cq->qplib_cq.sg_info, &sg_info, sizeof(sg_info)); 3154 cq->qplib_cq.dpi = orig_dpi; 3155 } 3156 return rc; 3157 } 3158 3159 static u8 __req_to_ib_wc_status(u8 qstatus) 3160 { 3161 switch (qstatus) { 3162 case CQ_REQ_STATUS_OK: 3163 return IB_WC_SUCCESS; 3164 case CQ_REQ_STATUS_BAD_RESPONSE_ERR: 3165 return IB_WC_BAD_RESP_ERR; 3166 case CQ_REQ_STATUS_LOCAL_LENGTH_ERR: 3167 return IB_WC_LOC_LEN_ERR; 3168 case CQ_REQ_STATUS_LOCAL_QP_OPERATION_ERR: 3169 return IB_WC_LOC_QP_OP_ERR; 3170 case CQ_REQ_STATUS_LOCAL_PROTECTION_ERR: 3171 return IB_WC_LOC_PROT_ERR; 3172 case CQ_REQ_STATUS_MEMORY_MGT_OPERATION_ERR: 3173 return IB_WC_GENERAL_ERR; 3174 case CQ_REQ_STATUS_REMOTE_INVALID_REQUEST_ERR: 3175 return IB_WC_REM_INV_REQ_ERR; 3176 case CQ_REQ_STATUS_REMOTE_ACCESS_ERR: 3177 return IB_WC_REM_ACCESS_ERR; 3178 case CQ_REQ_STATUS_REMOTE_OPERATION_ERR: 3179 return IB_WC_REM_OP_ERR; 3180 case CQ_REQ_STATUS_RNR_NAK_RETRY_CNT_ERR: 3181 return IB_WC_RNR_RETRY_EXC_ERR; 3182 case CQ_REQ_STATUS_TRANSPORT_RETRY_CNT_ERR: 3183 return IB_WC_RETRY_EXC_ERR; 3184 case CQ_REQ_STATUS_WORK_REQUEST_FLUSHED_ERR: 3185 return IB_WC_WR_FLUSH_ERR; 3186 default: 3187 return IB_WC_GENERAL_ERR; 3188 } 3189 return 0; 3190 } 3191 3192 static u8 __rawqp1_to_ib_wc_status(u8 qstatus) 3193 { 3194 switch (qstatus) { 3195 case CQ_RES_RAWETH_QP1_STATUS_OK: 3196 return IB_WC_SUCCESS; 3197 case CQ_RES_RAWETH_QP1_STATUS_LOCAL_ACCESS_ERROR: 3198 return IB_WC_LOC_ACCESS_ERR; 3199 case CQ_RES_RAWETH_QP1_STATUS_HW_LOCAL_LENGTH_ERR: 3200 return IB_WC_LOC_LEN_ERR; 3201 case CQ_RES_RAWETH_QP1_STATUS_LOCAL_PROTECTION_ERR: 3202 return IB_WC_LOC_PROT_ERR; 3203 case CQ_RES_RAWETH_QP1_STATUS_LOCAL_QP_OPERATION_ERR: 3204 return IB_WC_LOC_QP_OP_ERR; 3205 case CQ_RES_RAWETH_QP1_STATUS_MEMORY_MGT_OPERATION_ERR: 3206 return IB_WC_GENERAL_ERR; 3207 case CQ_RES_RAWETH_QP1_STATUS_WORK_REQUEST_FLUSHED_ERR: 3208 return IB_WC_WR_FLUSH_ERR; 3209 case CQ_RES_RAWETH_QP1_STATUS_HW_FLUSH_ERR: 3210 return IB_WC_WR_FLUSH_ERR; 3211 default: 3212 return IB_WC_GENERAL_ERR; 3213 } 3214 } 3215 3216 static u8 __rc_to_ib_wc_status(u8 qstatus) 3217 { 3218 switch (qstatus) { 3219 case CQ_RES_RC_STATUS_OK: 3220 return IB_WC_SUCCESS; 3221 case CQ_RES_RC_STATUS_LOCAL_ACCESS_ERROR: 3222 return IB_WC_LOC_ACCESS_ERR; 3223 case CQ_RES_RC_STATUS_LOCAL_LENGTH_ERR: 3224 return IB_WC_LOC_LEN_ERR; 3225 case CQ_RES_RC_STATUS_LOCAL_PROTECTION_ERR: 3226 return IB_WC_LOC_PROT_ERR; 3227 case CQ_RES_RC_STATUS_LOCAL_QP_OPERATION_ERR: 3228 return IB_WC_LOC_QP_OP_ERR; 3229 case CQ_RES_RC_STATUS_MEMORY_MGT_OPERATION_ERR: 3230 return IB_WC_GENERAL_ERR; 3231 case CQ_RES_RC_STATUS_REMOTE_INVALID_REQUEST_ERR: 3232 return IB_WC_REM_INV_REQ_ERR; 3233 case CQ_RES_RC_STATUS_WORK_REQUEST_FLUSHED_ERR: 3234 return IB_WC_WR_FLUSH_ERR; 3235 case CQ_RES_RC_STATUS_HW_FLUSH_ERR: 3236 return IB_WC_WR_FLUSH_ERR; 3237 default: 3238 return IB_WC_GENERAL_ERR; 3239 } 3240 } 3241 3242 static void bnxt_re_process_req_wc(struct ib_wc *wc, struct bnxt_qplib_cqe *cqe) 3243 { 3244 switch (cqe->type) { 3245 case BNXT_QPLIB_SWQE_TYPE_SEND: 3246 wc->opcode = IB_WC_SEND; 3247 break; 3248 case BNXT_QPLIB_SWQE_TYPE_SEND_WITH_IMM: 3249 wc->opcode = IB_WC_SEND; 3250 wc->wc_flags |= IB_WC_WITH_IMM; 3251 break; 3252 case BNXT_QPLIB_SWQE_TYPE_SEND_WITH_INV: 3253 wc->opcode = IB_WC_SEND; 3254 wc->wc_flags |= IB_WC_WITH_INVALIDATE; 3255 break; 3256 case BNXT_QPLIB_SWQE_TYPE_RDMA_WRITE: 3257 wc->opcode = IB_WC_RDMA_WRITE; 3258 break; 3259 case BNXT_QPLIB_SWQE_TYPE_RDMA_WRITE_WITH_IMM: 3260 wc->opcode = IB_WC_RDMA_WRITE; 3261 wc->wc_flags |= IB_WC_WITH_IMM; 3262 break; 3263 case BNXT_QPLIB_SWQE_TYPE_RDMA_READ: 3264 wc->opcode = IB_WC_RDMA_READ; 3265 break; 3266 case BNXT_QPLIB_SWQE_TYPE_ATOMIC_CMP_AND_SWP: 3267 wc->opcode = IB_WC_COMP_SWAP; 3268 break; 3269 case BNXT_QPLIB_SWQE_TYPE_ATOMIC_FETCH_AND_ADD: 3270 wc->opcode = IB_WC_FETCH_ADD; 3271 break; 3272 case BNXT_QPLIB_SWQE_TYPE_LOCAL_INV: 3273 wc->opcode = IB_WC_LOCAL_INV; 3274 break; 3275 case BNXT_QPLIB_SWQE_TYPE_REG_MR: 3276 wc->opcode = IB_WC_REG_MR; 3277 break; 3278 default: 3279 wc->opcode = IB_WC_SEND; 3280 break; 3281 } 3282 3283 wc->status = __req_to_ib_wc_status(cqe->status); 3284 } 3285 3286 static int bnxt_re_check_packet_type(u16 raweth_qp1_flags, 3287 u16 raweth_qp1_flags2) 3288 { 3289 bool is_ipv6 = false, is_ipv4 = false; 3290 3291 /* raweth_qp1_flags Bit 9-6 indicates itype */ 3292 if ((raweth_qp1_flags & CQ_RES_RAWETH_QP1_RAWETH_QP1_FLAGS_ITYPE_ROCE) 3293 != CQ_RES_RAWETH_QP1_RAWETH_QP1_FLAGS_ITYPE_ROCE) 3294 return -1; 3295 3296 if (raweth_qp1_flags2 & 3297 CQ_RES_RAWETH_QP1_RAWETH_QP1_FLAGS2_IP_CS_CALC && 3298 raweth_qp1_flags2 & 3299 CQ_RES_RAWETH_QP1_RAWETH_QP1_FLAGS2_L4_CS_CALC) { 3300 /* raweth_qp1_flags2 Bit 8 indicates ip_type. 0-v4 1 - v6 */ 3301 (raweth_qp1_flags2 & 3302 CQ_RES_RAWETH_QP1_RAWETH_QP1_FLAGS2_IP_TYPE) ? 3303 (is_ipv6 = true) : (is_ipv4 = true); 3304 return ((is_ipv6) ? 3305 BNXT_RE_ROCEV2_IPV6_PACKET : 3306 BNXT_RE_ROCEV2_IPV4_PACKET); 3307 } else { 3308 return BNXT_RE_ROCE_V1_PACKET; 3309 } 3310 } 3311 3312 static int bnxt_re_to_ib_nw_type(int nw_type) 3313 { 3314 u8 nw_hdr_type = 0xFF; 3315 3316 switch (nw_type) { 3317 case BNXT_RE_ROCE_V1_PACKET: 3318 nw_hdr_type = RDMA_NETWORK_ROCE_V1; 3319 break; 3320 case BNXT_RE_ROCEV2_IPV4_PACKET: 3321 nw_hdr_type = RDMA_NETWORK_IPV4; 3322 break; 3323 case BNXT_RE_ROCEV2_IPV6_PACKET: 3324 nw_hdr_type = RDMA_NETWORK_IPV6; 3325 break; 3326 } 3327 return nw_hdr_type; 3328 } 3329 3330 static bool bnxt_re_is_loopback_packet(struct bnxt_re_dev *rdev, 3331 void *rq_hdr_buf) 3332 { 3333 u8 *tmp_buf = NULL; 3334 struct ethhdr *eth_hdr; 3335 u16 eth_type; 3336 bool rc = false; 3337 3338 tmp_buf = (u8 *)rq_hdr_buf; 3339 /* 3340 * If dest mac is not same as I/F mac, this could be a 3341 * loopback address or multicast address, check whether 3342 * it is a loopback packet 3343 */ 3344 if (!ether_addr_equal(tmp_buf, rdev->netdev->dev_addr)) { 3345 tmp_buf += 4; 3346 /* Check the ether type */ 3347 eth_hdr = (struct ethhdr *)tmp_buf; 3348 eth_type = ntohs(eth_hdr->h_proto); 3349 switch (eth_type) { 3350 case ETH_P_IBOE: 3351 rc = true; 3352 break; 3353 case ETH_P_IP: 3354 case ETH_P_IPV6: { 3355 u32 len; 3356 struct udphdr *udp_hdr; 3357 3358 len = (eth_type == ETH_P_IP ? sizeof(struct iphdr) : 3359 sizeof(struct ipv6hdr)); 3360 tmp_buf += sizeof(struct ethhdr) + len; 3361 udp_hdr = (struct udphdr *)tmp_buf; 3362 if (ntohs(udp_hdr->dest) == 3363 ROCE_V2_UDP_DPORT) 3364 rc = true; 3365 break; 3366 } 3367 default: 3368 break; 3369 } 3370 } 3371 3372 return rc; 3373 } 3374 3375 static int bnxt_re_process_raw_qp_pkt_rx(struct bnxt_re_qp *gsi_qp, 3376 struct bnxt_qplib_cqe *cqe) 3377 { 3378 struct bnxt_re_dev *rdev = gsi_qp->rdev; 3379 struct bnxt_re_sqp_entries *sqp_entry = NULL; 3380 struct bnxt_re_qp *gsi_sqp = rdev->gsi_ctx.gsi_sqp; 3381 dma_addr_t shrq_hdr_buf_map; 3382 struct ib_sge s_sge[2] = {}; 3383 struct ib_sge r_sge[2] = {}; 3384 struct bnxt_re_ah *gsi_sah; 3385 struct ib_recv_wr rwr = {}; 3386 dma_addr_t rq_hdr_buf_map; 3387 struct ib_ud_wr udwr = {}; 3388 struct ib_send_wr *swr; 3389 u32 skip_bytes = 0; 3390 int pkt_type = 0; 3391 void *rq_hdr_buf; 3392 u32 offset = 0; 3393 u32 tbl_idx; 3394 int rc; 3395 3396 swr = &udwr.wr; 3397 tbl_idx = cqe->wr_id; 3398 3399 rq_hdr_buf = gsi_qp->qplib_qp.rq_hdr_buf + 3400 (tbl_idx * gsi_qp->qplib_qp.rq_hdr_buf_size); 3401 rq_hdr_buf_map = bnxt_qplib_get_qp_buf_from_index(&gsi_qp->qplib_qp, 3402 tbl_idx); 3403 3404 /* Shadow QP header buffer */ 3405 shrq_hdr_buf_map = bnxt_qplib_get_qp_buf_from_index(&gsi_qp->qplib_qp, 3406 tbl_idx); 3407 sqp_entry = &rdev->gsi_ctx.sqp_tbl[tbl_idx]; 3408 3409 /* Store this cqe */ 3410 memcpy(&sqp_entry->cqe, cqe, sizeof(struct bnxt_qplib_cqe)); 3411 sqp_entry->qp1_qp = gsi_qp; 3412 3413 /* Find packet type from the cqe */ 3414 3415 pkt_type = bnxt_re_check_packet_type(cqe->raweth_qp1_flags, 3416 cqe->raweth_qp1_flags2); 3417 if (pkt_type < 0) { 3418 ibdev_err(&rdev->ibdev, "Invalid packet\n"); 3419 return -EINVAL; 3420 } 3421 3422 /* Adjust the offset for the user buffer and post in the rq */ 3423 3424 if (pkt_type == BNXT_RE_ROCEV2_IPV4_PACKET) 3425 offset = 20; 3426 3427 /* 3428 * QP1 loopback packet has 4 bytes of internal header before 3429 * ether header. Skip these four bytes. 3430 */ 3431 if (bnxt_re_is_loopback_packet(rdev, rq_hdr_buf)) 3432 skip_bytes = 4; 3433 3434 /* First send SGE . Skip the ether header*/ 3435 s_sge[0].addr = rq_hdr_buf_map + BNXT_QPLIB_MAX_QP1_RQ_ETH_HDR_SIZE 3436 + skip_bytes; 3437 s_sge[0].lkey = 0xFFFFFFFF; 3438 s_sge[0].length = offset ? BNXT_QPLIB_MAX_GRH_HDR_SIZE_IPV4 : 3439 BNXT_QPLIB_MAX_GRH_HDR_SIZE_IPV6; 3440 3441 /* Second Send SGE */ 3442 s_sge[1].addr = s_sge[0].addr + s_sge[0].length + 3443 BNXT_QPLIB_MAX_QP1_RQ_BDETH_HDR_SIZE; 3444 if (pkt_type != BNXT_RE_ROCE_V1_PACKET) 3445 s_sge[1].addr += 8; 3446 s_sge[1].lkey = 0xFFFFFFFF; 3447 s_sge[1].length = 256; 3448 3449 /* First recv SGE */ 3450 3451 r_sge[0].addr = shrq_hdr_buf_map; 3452 r_sge[0].lkey = 0xFFFFFFFF; 3453 r_sge[0].length = 40; 3454 3455 r_sge[1].addr = sqp_entry->sge.addr + offset; 3456 r_sge[1].lkey = sqp_entry->sge.lkey; 3457 r_sge[1].length = BNXT_QPLIB_MAX_GRH_HDR_SIZE_IPV6 + 256 - offset; 3458 3459 /* Create receive work request */ 3460 rwr.num_sge = 2; 3461 rwr.sg_list = r_sge; 3462 rwr.wr_id = tbl_idx; 3463 rwr.next = NULL; 3464 3465 rc = bnxt_re_post_recv_shadow_qp(rdev, gsi_sqp, &rwr); 3466 if (rc) { 3467 ibdev_err(&rdev->ibdev, 3468 "Failed to post Rx buffers to shadow QP"); 3469 return -ENOMEM; 3470 } 3471 3472 swr->num_sge = 2; 3473 swr->sg_list = s_sge; 3474 swr->wr_id = tbl_idx; 3475 swr->opcode = IB_WR_SEND; 3476 swr->next = NULL; 3477 gsi_sah = rdev->gsi_ctx.gsi_sah; 3478 udwr.ah = &gsi_sah->ib_ah; 3479 udwr.remote_qpn = gsi_sqp->qplib_qp.id; 3480 udwr.remote_qkey = gsi_sqp->qplib_qp.qkey; 3481 3482 /* post data received in the send queue */ 3483 return bnxt_re_post_send_shadow_qp(rdev, gsi_sqp, swr); 3484 } 3485 3486 static void bnxt_re_process_res_rawqp1_wc(struct ib_wc *wc, 3487 struct bnxt_qplib_cqe *cqe) 3488 { 3489 wc->opcode = IB_WC_RECV; 3490 wc->status = __rawqp1_to_ib_wc_status(cqe->status); 3491 wc->wc_flags |= IB_WC_GRH; 3492 } 3493 3494 static bool bnxt_re_check_if_vlan_valid(struct bnxt_re_dev *rdev, 3495 u16 vlan_id) 3496 { 3497 /* 3498 * Check if the vlan is configured in the host. If not configured, it 3499 * can be a transparent VLAN. So dont report the vlan id. 3500 */ 3501 if (!__vlan_find_dev_deep_rcu(rdev->netdev, 3502 htons(ETH_P_8021Q), vlan_id)) 3503 return false; 3504 return true; 3505 } 3506 3507 static bool bnxt_re_is_vlan_pkt(struct bnxt_qplib_cqe *orig_cqe, 3508 u16 *vid, u8 *sl) 3509 { 3510 bool ret = false; 3511 u32 metadata; 3512 u16 tpid; 3513 3514 metadata = orig_cqe->raweth_qp1_metadata; 3515 if (orig_cqe->raweth_qp1_flags2 & 3516 CQ_RES_RAWETH_QP1_RAWETH_QP1_FLAGS2_META_FORMAT_VLAN) { 3517 tpid = ((metadata & 3518 CQ_RES_RAWETH_QP1_RAWETH_QP1_METADATA_TPID_MASK) >> 3519 CQ_RES_RAWETH_QP1_RAWETH_QP1_METADATA_TPID_SFT); 3520 if (tpid == ETH_P_8021Q) { 3521 *vid = metadata & 3522 CQ_RES_RAWETH_QP1_RAWETH_QP1_METADATA_VID_MASK; 3523 *sl = (metadata & 3524 CQ_RES_RAWETH_QP1_RAWETH_QP1_METADATA_PRI_MASK) >> 3525 CQ_RES_RAWETH_QP1_RAWETH_QP1_METADATA_PRI_SFT; 3526 ret = true; 3527 } 3528 } 3529 3530 return ret; 3531 } 3532 3533 static void bnxt_re_process_res_rc_wc(struct ib_wc *wc, 3534 struct bnxt_qplib_cqe *cqe) 3535 { 3536 wc->opcode = IB_WC_RECV; 3537 wc->status = __rc_to_ib_wc_status(cqe->status); 3538 3539 if (cqe->flags & CQ_RES_RC_FLAGS_IMM) 3540 wc->wc_flags |= IB_WC_WITH_IMM; 3541 if (cqe->flags & CQ_RES_RC_FLAGS_INV) 3542 wc->wc_flags |= IB_WC_WITH_INVALIDATE; 3543 if ((cqe->flags & (CQ_RES_RC_FLAGS_RDMA | CQ_RES_RC_FLAGS_IMM)) == 3544 (CQ_RES_RC_FLAGS_RDMA | CQ_RES_RC_FLAGS_IMM)) 3545 wc->opcode = IB_WC_RECV_RDMA_WITH_IMM; 3546 } 3547 3548 static void bnxt_re_process_res_shadow_qp_wc(struct bnxt_re_qp *gsi_sqp, 3549 struct ib_wc *wc, 3550 struct bnxt_qplib_cqe *cqe) 3551 { 3552 struct bnxt_re_dev *rdev = gsi_sqp->rdev; 3553 struct bnxt_re_qp *gsi_qp = NULL; 3554 struct bnxt_qplib_cqe *orig_cqe = NULL; 3555 struct bnxt_re_sqp_entries *sqp_entry = NULL; 3556 int nw_type; 3557 u32 tbl_idx; 3558 u16 vlan_id; 3559 u8 sl; 3560 3561 tbl_idx = cqe->wr_id; 3562 3563 sqp_entry = &rdev->gsi_ctx.sqp_tbl[tbl_idx]; 3564 gsi_qp = sqp_entry->qp1_qp; 3565 orig_cqe = &sqp_entry->cqe; 3566 3567 wc->wr_id = sqp_entry->wrid; 3568 wc->byte_len = orig_cqe->length; 3569 wc->qp = &gsi_qp->ib_qp; 3570 3571 wc->ex.imm_data = cpu_to_be32(orig_cqe->immdata); 3572 wc->src_qp = orig_cqe->src_qp; 3573 memcpy(wc->smac, orig_cqe->smac, ETH_ALEN); 3574 if (bnxt_re_is_vlan_pkt(orig_cqe, &vlan_id, &sl)) { 3575 if (bnxt_re_check_if_vlan_valid(rdev, vlan_id)) { 3576 wc->vlan_id = vlan_id; 3577 wc->sl = sl; 3578 wc->wc_flags |= IB_WC_WITH_VLAN; 3579 } 3580 } 3581 wc->port_num = 1; 3582 wc->vendor_err = orig_cqe->status; 3583 3584 wc->opcode = IB_WC_RECV; 3585 wc->status = __rawqp1_to_ib_wc_status(orig_cqe->status); 3586 wc->wc_flags |= IB_WC_GRH; 3587 3588 nw_type = bnxt_re_check_packet_type(orig_cqe->raweth_qp1_flags, 3589 orig_cqe->raweth_qp1_flags2); 3590 if (nw_type >= 0) { 3591 wc->network_hdr_type = bnxt_re_to_ib_nw_type(nw_type); 3592 wc->wc_flags |= IB_WC_WITH_NETWORK_HDR_TYPE; 3593 } 3594 } 3595 3596 static void bnxt_re_process_res_ud_wc(struct bnxt_re_qp *qp, 3597 struct ib_wc *wc, 3598 struct bnxt_qplib_cqe *cqe) 3599 { 3600 struct bnxt_re_dev *rdev; 3601 u16 vlan_id = 0; 3602 u8 nw_type; 3603 3604 rdev = qp->rdev; 3605 wc->opcode = IB_WC_RECV; 3606 wc->status = __rc_to_ib_wc_status(cqe->status); 3607 3608 if (cqe->flags & CQ_RES_UD_FLAGS_IMM) 3609 wc->wc_flags |= IB_WC_WITH_IMM; 3610 /* report only on GSI QP for Thor */ 3611 if (qp->qplib_qp.type == CMDQ_CREATE_QP_TYPE_GSI) { 3612 wc->wc_flags |= IB_WC_GRH; 3613 memcpy(wc->smac, cqe->smac, ETH_ALEN); 3614 wc->wc_flags |= IB_WC_WITH_SMAC; 3615 if (cqe->flags & CQ_RES_UD_FLAGS_META_FORMAT_VLAN) { 3616 vlan_id = (cqe->cfa_meta & 0xFFF); 3617 } 3618 /* Mark only if vlan_id is non zero */ 3619 if (vlan_id && bnxt_re_check_if_vlan_valid(rdev, vlan_id)) { 3620 wc->vlan_id = vlan_id; 3621 wc->wc_flags |= IB_WC_WITH_VLAN; 3622 } 3623 nw_type = (cqe->flags & CQ_RES_UD_FLAGS_ROCE_IP_VER_MASK) >> 3624 CQ_RES_UD_FLAGS_ROCE_IP_VER_SFT; 3625 wc->network_hdr_type = bnxt_re_to_ib_nw_type(nw_type); 3626 wc->wc_flags |= IB_WC_WITH_NETWORK_HDR_TYPE; 3627 } 3628 3629 } 3630 3631 static int send_phantom_wqe(struct bnxt_re_qp *qp) 3632 { 3633 struct bnxt_qplib_qp *lib_qp = &qp->qplib_qp; 3634 unsigned long flags; 3635 int rc; 3636 3637 spin_lock_irqsave(&qp->sq_lock, flags); 3638 3639 rc = bnxt_re_bind_fence_mw(lib_qp); 3640 if (!rc) { 3641 lib_qp->sq.phantom_wqe_cnt++; 3642 ibdev_dbg(&qp->rdev->ibdev, 3643 "qp %#x sq->prod %#x sw_prod %#x phantom_wqe_cnt %d\n", 3644 lib_qp->id, lib_qp->sq.hwq.prod, 3645 HWQ_CMP(lib_qp->sq.hwq.prod, &lib_qp->sq.hwq), 3646 lib_qp->sq.phantom_wqe_cnt); 3647 } 3648 3649 spin_unlock_irqrestore(&qp->sq_lock, flags); 3650 return rc; 3651 } 3652 3653 int bnxt_re_poll_cq(struct ib_cq *ib_cq, int num_entries, struct ib_wc *wc) 3654 { 3655 struct bnxt_re_cq *cq = container_of(ib_cq, struct bnxt_re_cq, ib_cq); 3656 struct bnxt_re_qp *qp, *sh_qp; 3657 struct bnxt_qplib_cqe *cqe; 3658 int i, ncqe, budget; 3659 struct bnxt_qplib_q *sq; 3660 struct bnxt_qplib_qp *lib_qp; 3661 u32 tbl_idx; 3662 struct bnxt_re_sqp_entries *sqp_entry = NULL; 3663 unsigned long flags; 3664 3665 /* User CQ; the only processing we do is to 3666 * complete any pending CQ resize operation. 3667 */ 3668 if (cq->umem) { 3669 if (cq->resize_umem) 3670 bnxt_re_resize_cq_complete(cq); 3671 return 0; 3672 } 3673 3674 spin_lock_irqsave(&cq->cq_lock, flags); 3675 budget = min_t(u32, num_entries, cq->max_cql); 3676 num_entries = budget; 3677 if (!cq->cql) { 3678 ibdev_err(&cq->rdev->ibdev, "POLL CQ : no CQL to use"); 3679 goto exit; 3680 } 3681 cqe = &cq->cql[0]; 3682 while (budget) { 3683 lib_qp = NULL; 3684 ncqe = bnxt_qplib_poll_cq(&cq->qplib_cq, cqe, budget, &lib_qp); 3685 if (lib_qp) { 3686 sq = &lib_qp->sq; 3687 if (sq->send_phantom) { 3688 qp = container_of(lib_qp, 3689 struct bnxt_re_qp, qplib_qp); 3690 if (send_phantom_wqe(qp) == -ENOMEM) 3691 ibdev_err(&cq->rdev->ibdev, 3692 "Phantom failed! Scheduled to send again\n"); 3693 else 3694 sq->send_phantom = false; 3695 } 3696 } 3697 if (ncqe < budget) 3698 ncqe += bnxt_qplib_process_flush_list(&cq->qplib_cq, 3699 cqe + ncqe, 3700 budget - ncqe); 3701 3702 if (!ncqe) 3703 break; 3704 3705 for (i = 0; i < ncqe; i++, cqe++) { 3706 /* Transcribe each qplib_wqe back to ib_wc */ 3707 memset(wc, 0, sizeof(*wc)); 3708 3709 wc->wr_id = cqe->wr_id; 3710 wc->byte_len = cqe->length; 3711 qp = container_of 3712 ((struct bnxt_qplib_qp *) 3713 (unsigned long)(cqe->qp_handle), 3714 struct bnxt_re_qp, qplib_qp); 3715 wc->qp = &qp->ib_qp; 3716 if (cqe->flags & CQ_RES_RC_FLAGS_IMM) 3717 wc->ex.imm_data = cpu_to_be32(cqe->immdata); 3718 else 3719 wc->ex.invalidate_rkey = cqe->invrkey; 3720 wc->src_qp = cqe->src_qp; 3721 memcpy(wc->smac, cqe->smac, ETH_ALEN); 3722 wc->port_num = 1; 3723 wc->vendor_err = cqe->status; 3724 3725 switch (cqe->opcode) { 3726 case CQ_BASE_CQE_TYPE_REQ: 3727 sh_qp = qp->rdev->gsi_ctx.gsi_sqp; 3728 if (sh_qp && 3729 qp->qplib_qp.id == sh_qp->qplib_qp.id) { 3730 /* Handle this completion with 3731 * the stored completion 3732 */ 3733 memset(wc, 0, sizeof(*wc)); 3734 continue; 3735 } 3736 bnxt_re_process_req_wc(wc, cqe); 3737 break; 3738 case CQ_BASE_CQE_TYPE_RES_RAWETH_QP1: 3739 if (!cqe->status) { 3740 int rc = 0; 3741 3742 rc = bnxt_re_process_raw_qp_pkt_rx 3743 (qp, cqe); 3744 if (!rc) { 3745 memset(wc, 0, sizeof(*wc)); 3746 continue; 3747 } 3748 cqe->status = -1; 3749 } 3750 /* Errors need not be looped back. 3751 * But change the wr_id to the one 3752 * stored in the table 3753 */ 3754 tbl_idx = cqe->wr_id; 3755 sqp_entry = &cq->rdev->gsi_ctx.sqp_tbl[tbl_idx]; 3756 wc->wr_id = sqp_entry->wrid; 3757 bnxt_re_process_res_rawqp1_wc(wc, cqe); 3758 break; 3759 case CQ_BASE_CQE_TYPE_RES_RC: 3760 bnxt_re_process_res_rc_wc(wc, cqe); 3761 break; 3762 case CQ_BASE_CQE_TYPE_RES_UD: 3763 sh_qp = qp->rdev->gsi_ctx.gsi_sqp; 3764 if (sh_qp && 3765 qp->qplib_qp.id == sh_qp->qplib_qp.id) { 3766 /* Handle this completion with 3767 * the stored completion 3768 */ 3769 if (cqe->status) { 3770 continue; 3771 } else { 3772 bnxt_re_process_res_shadow_qp_wc 3773 (qp, wc, cqe); 3774 break; 3775 } 3776 } 3777 bnxt_re_process_res_ud_wc(qp, wc, cqe); 3778 break; 3779 default: 3780 ibdev_err(&cq->rdev->ibdev, 3781 "POLL CQ : type 0x%x not handled", 3782 cqe->opcode); 3783 continue; 3784 } 3785 wc++; 3786 budget--; 3787 } 3788 } 3789 exit: 3790 spin_unlock_irqrestore(&cq->cq_lock, flags); 3791 return num_entries - budget; 3792 } 3793 3794 int bnxt_re_req_notify_cq(struct ib_cq *ib_cq, 3795 enum ib_cq_notify_flags ib_cqn_flags) 3796 { 3797 struct bnxt_re_cq *cq = container_of(ib_cq, struct bnxt_re_cq, ib_cq); 3798 int type = 0, rc = 0; 3799 unsigned long flags; 3800 3801 spin_lock_irqsave(&cq->cq_lock, flags); 3802 /* Trigger on the very next completion */ 3803 if (ib_cqn_flags & IB_CQ_NEXT_COMP) 3804 type = DBC_DBC_TYPE_CQ_ARMALL; 3805 /* Trigger on the next solicited completion */ 3806 else if (ib_cqn_flags & IB_CQ_SOLICITED) 3807 type = DBC_DBC_TYPE_CQ_ARMSE; 3808 3809 /* Poll to see if there are missed events */ 3810 if ((ib_cqn_flags & IB_CQ_REPORT_MISSED_EVENTS) && 3811 !(bnxt_qplib_is_cq_empty(&cq->qplib_cq))) { 3812 rc = 1; 3813 goto exit; 3814 } 3815 bnxt_qplib_req_notify_cq(&cq->qplib_cq, type); 3816 3817 exit: 3818 spin_unlock_irqrestore(&cq->cq_lock, flags); 3819 return rc; 3820 } 3821 3822 /* Memory Regions */ 3823 struct ib_mr *bnxt_re_get_dma_mr(struct ib_pd *ib_pd, int mr_access_flags) 3824 { 3825 struct bnxt_re_pd *pd = container_of(ib_pd, struct bnxt_re_pd, ib_pd); 3826 struct bnxt_re_dev *rdev = pd->rdev; 3827 struct bnxt_re_mr *mr; 3828 u32 active_mrs; 3829 int rc; 3830 3831 mr = kzalloc(sizeof(*mr), GFP_KERNEL); 3832 if (!mr) 3833 return ERR_PTR(-ENOMEM); 3834 3835 mr->rdev = rdev; 3836 mr->qplib_mr.pd = &pd->qplib_pd; 3837 mr->qplib_mr.flags = __from_ib_access_flags(mr_access_flags); 3838 mr->qplib_mr.type = CMDQ_ALLOCATE_MRW_MRW_FLAGS_PMR; 3839 3840 /* Allocate and register 0 as the address */ 3841 rc = bnxt_qplib_alloc_mrw(&rdev->qplib_res, &mr->qplib_mr); 3842 if (rc) 3843 goto fail; 3844 3845 mr->qplib_mr.hwq.level = PBL_LVL_MAX; 3846 mr->qplib_mr.total_size = -1; /* Infinte length */ 3847 rc = bnxt_qplib_reg_mr(&rdev->qplib_res, &mr->qplib_mr, NULL, 0, 3848 PAGE_SIZE); 3849 if (rc) 3850 goto fail_mr; 3851 3852 mr->ib_mr.lkey = mr->qplib_mr.lkey; 3853 if (mr_access_flags & (IB_ACCESS_REMOTE_WRITE | IB_ACCESS_REMOTE_READ | 3854 IB_ACCESS_REMOTE_ATOMIC)) 3855 mr->ib_mr.rkey = mr->ib_mr.lkey; 3856 active_mrs = atomic_inc_return(&rdev->stats.res.mr_count); 3857 if (active_mrs > rdev->stats.res.mr_watermark) 3858 rdev->stats.res.mr_watermark = active_mrs; 3859 3860 return &mr->ib_mr; 3861 3862 fail_mr: 3863 bnxt_qplib_free_mrw(&rdev->qplib_res, &mr->qplib_mr); 3864 fail: 3865 kfree(mr); 3866 return ERR_PTR(rc); 3867 } 3868 3869 int bnxt_re_dereg_mr(struct ib_mr *ib_mr, struct ib_udata *udata) 3870 { 3871 struct bnxt_re_mr *mr = container_of(ib_mr, struct bnxt_re_mr, ib_mr); 3872 struct bnxt_re_dev *rdev = mr->rdev; 3873 int rc; 3874 3875 rc = bnxt_qplib_free_mrw(&rdev->qplib_res, &mr->qplib_mr); 3876 if (rc) { 3877 ibdev_err(&rdev->ibdev, "Dereg MR failed: %#x\n", rc); 3878 return rc; 3879 } 3880 3881 if (mr->pages) { 3882 rc = bnxt_qplib_free_fast_reg_page_list(&rdev->qplib_res, 3883 &mr->qplib_frpl); 3884 kfree(mr->pages); 3885 mr->npages = 0; 3886 mr->pages = NULL; 3887 } 3888 ib_umem_release(mr->ib_umem); 3889 3890 kfree(mr); 3891 atomic_dec(&rdev->stats.res.mr_count); 3892 return rc; 3893 } 3894 3895 static int bnxt_re_set_page(struct ib_mr *ib_mr, u64 addr) 3896 { 3897 struct bnxt_re_mr *mr = container_of(ib_mr, struct bnxt_re_mr, ib_mr); 3898 3899 if (unlikely(mr->npages == mr->qplib_frpl.max_pg_ptrs)) 3900 return -ENOMEM; 3901 3902 mr->pages[mr->npages++] = addr; 3903 return 0; 3904 } 3905 3906 int bnxt_re_map_mr_sg(struct ib_mr *ib_mr, struct scatterlist *sg, int sg_nents, 3907 unsigned int *sg_offset) 3908 { 3909 struct bnxt_re_mr *mr = container_of(ib_mr, struct bnxt_re_mr, ib_mr); 3910 3911 mr->npages = 0; 3912 return ib_sg_to_pages(ib_mr, sg, sg_nents, sg_offset, bnxt_re_set_page); 3913 } 3914 3915 struct ib_mr *bnxt_re_alloc_mr(struct ib_pd *ib_pd, enum ib_mr_type type, 3916 u32 max_num_sg) 3917 { 3918 struct bnxt_re_pd *pd = container_of(ib_pd, struct bnxt_re_pd, ib_pd); 3919 struct bnxt_re_dev *rdev = pd->rdev; 3920 struct bnxt_re_mr *mr = NULL; 3921 u32 active_mrs; 3922 int rc; 3923 3924 if (type != IB_MR_TYPE_MEM_REG) { 3925 ibdev_dbg(&rdev->ibdev, "MR type 0x%x not supported", type); 3926 return ERR_PTR(-EINVAL); 3927 } 3928 if (max_num_sg > MAX_PBL_LVL_1_PGS) 3929 return ERR_PTR(-EINVAL); 3930 3931 mr = kzalloc(sizeof(*mr), GFP_KERNEL); 3932 if (!mr) 3933 return ERR_PTR(-ENOMEM); 3934 3935 mr->rdev = rdev; 3936 mr->qplib_mr.pd = &pd->qplib_pd; 3937 mr->qplib_mr.flags = BNXT_QPLIB_FR_PMR; 3938 mr->qplib_mr.type = CMDQ_ALLOCATE_MRW_MRW_FLAGS_PMR; 3939 3940 rc = bnxt_qplib_alloc_mrw(&rdev->qplib_res, &mr->qplib_mr); 3941 if (rc) 3942 goto bail; 3943 3944 mr->ib_mr.lkey = mr->qplib_mr.lkey; 3945 mr->ib_mr.rkey = mr->ib_mr.lkey; 3946 3947 mr->pages = kcalloc(max_num_sg, sizeof(u64), GFP_KERNEL); 3948 if (!mr->pages) { 3949 rc = -ENOMEM; 3950 goto fail; 3951 } 3952 rc = bnxt_qplib_alloc_fast_reg_page_list(&rdev->qplib_res, 3953 &mr->qplib_frpl, max_num_sg); 3954 if (rc) { 3955 ibdev_err(&rdev->ibdev, 3956 "Failed to allocate HW FR page list"); 3957 goto fail_mr; 3958 } 3959 3960 active_mrs = atomic_inc_return(&rdev->stats.res.mr_count); 3961 if (active_mrs > rdev->stats.res.mr_watermark) 3962 rdev->stats.res.mr_watermark = active_mrs; 3963 return &mr->ib_mr; 3964 3965 fail_mr: 3966 kfree(mr->pages); 3967 fail: 3968 bnxt_qplib_free_mrw(&rdev->qplib_res, &mr->qplib_mr); 3969 bail: 3970 kfree(mr); 3971 return ERR_PTR(rc); 3972 } 3973 3974 struct ib_mw *bnxt_re_alloc_mw(struct ib_pd *ib_pd, enum ib_mw_type type, 3975 struct ib_udata *udata) 3976 { 3977 struct bnxt_re_pd *pd = container_of(ib_pd, struct bnxt_re_pd, ib_pd); 3978 struct bnxt_re_dev *rdev = pd->rdev; 3979 struct bnxt_re_mw *mw; 3980 u32 active_mws; 3981 int rc; 3982 3983 mw = kzalloc(sizeof(*mw), GFP_KERNEL); 3984 if (!mw) 3985 return ERR_PTR(-ENOMEM); 3986 mw->rdev = rdev; 3987 mw->qplib_mw.pd = &pd->qplib_pd; 3988 3989 mw->qplib_mw.type = (type == IB_MW_TYPE_1 ? 3990 CMDQ_ALLOCATE_MRW_MRW_FLAGS_MW_TYPE1 : 3991 CMDQ_ALLOCATE_MRW_MRW_FLAGS_MW_TYPE2B); 3992 rc = bnxt_qplib_alloc_mrw(&rdev->qplib_res, &mw->qplib_mw); 3993 if (rc) { 3994 ibdev_err(&rdev->ibdev, "Allocate MW failed!"); 3995 goto fail; 3996 } 3997 mw->ib_mw.rkey = mw->qplib_mw.rkey; 3998 3999 active_mws = atomic_inc_return(&rdev->stats.res.mw_count); 4000 if (active_mws > rdev->stats.res.mw_watermark) 4001 rdev->stats.res.mw_watermark = active_mws; 4002 return &mw->ib_mw; 4003 4004 fail: 4005 kfree(mw); 4006 return ERR_PTR(rc); 4007 } 4008 4009 int bnxt_re_dealloc_mw(struct ib_mw *ib_mw) 4010 { 4011 struct bnxt_re_mw *mw = container_of(ib_mw, struct bnxt_re_mw, ib_mw); 4012 struct bnxt_re_dev *rdev = mw->rdev; 4013 int rc; 4014 4015 rc = bnxt_qplib_free_mrw(&rdev->qplib_res, &mw->qplib_mw); 4016 if (rc) { 4017 ibdev_err(&rdev->ibdev, "Free MW failed: %#x\n", rc); 4018 return rc; 4019 } 4020 4021 kfree(mw); 4022 atomic_dec(&rdev->stats.res.mw_count); 4023 return rc; 4024 } 4025 4026 static struct ib_mr *__bnxt_re_user_reg_mr(struct ib_pd *ib_pd, u64 length, u64 virt_addr, 4027 int mr_access_flags, struct ib_umem *umem) 4028 { 4029 struct bnxt_re_pd *pd = container_of(ib_pd, struct bnxt_re_pd, ib_pd); 4030 struct bnxt_re_dev *rdev = pd->rdev; 4031 unsigned long page_size; 4032 struct bnxt_re_mr *mr; 4033 int umem_pgs, rc; 4034 u32 active_mrs; 4035 4036 if (length > BNXT_RE_MAX_MR_SIZE) { 4037 ibdev_err(&rdev->ibdev, "MR Size: %lld > Max supported:%lld\n", 4038 length, BNXT_RE_MAX_MR_SIZE); 4039 return ERR_PTR(-ENOMEM); 4040 } 4041 4042 page_size = ib_umem_find_best_pgsz(umem, BNXT_RE_PAGE_SIZE_SUPPORTED, virt_addr); 4043 if (!page_size) { 4044 ibdev_err(&rdev->ibdev, "umem page size unsupported!"); 4045 return ERR_PTR(-EINVAL); 4046 } 4047 4048 mr = kzalloc(sizeof(*mr), GFP_KERNEL); 4049 if (!mr) 4050 return ERR_PTR(-ENOMEM); 4051 4052 mr->rdev = rdev; 4053 mr->qplib_mr.pd = &pd->qplib_pd; 4054 mr->qplib_mr.flags = __from_ib_access_flags(mr_access_flags); 4055 mr->qplib_mr.type = CMDQ_ALLOCATE_MRW_MRW_FLAGS_MR; 4056 4057 rc = bnxt_qplib_alloc_mrw(&rdev->qplib_res, &mr->qplib_mr); 4058 if (rc) { 4059 ibdev_err(&rdev->ibdev, "Failed to allocate MR rc = %d", rc); 4060 rc = -EIO; 4061 goto free_mr; 4062 } 4063 /* The fixed portion of the rkey is the same as the lkey */ 4064 mr->ib_mr.rkey = mr->qplib_mr.rkey; 4065 mr->ib_umem = umem; 4066 mr->qplib_mr.va = virt_addr; 4067 mr->qplib_mr.total_size = length; 4068 4069 umem_pgs = ib_umem_num_dma_blocks(umem, page_size); 4070 rc = bnxt_qplib_reg_mr(&rdev->qplib_res, &mr->qplib_mr, umem, 4071 umem_pgs, page_size); 4072 if (rc) { 4073 ibdev_err(&rdev->ibdev, "Failed to register user MR - rc = %d\n", rc); 4074 rc = -EIO; 4075 goto free_mrw; 4076 } 4077 4078 mr->ib_mr.lkey = mr->qplib_mr.lkey; 4079 mr->ib_mr.rkey = mr->qplib_mr.lkey; 4080 active_mrs = atomic_inc_return(&rdev->stats.res.mr_count); 4081 if (active_mrs > rdev->stats.res.mr_watermark) 4082 rdev->stats.res.mr_watermark = active_mrs; 4083 4084 return &mr->ib_mr; 4085 4086 free_mrw: 4087 bnxt_qplib_free_mrw(&rdev->qplib_res, &mr->qplib_mr); 4088 free_mr: 4089 kfree(mr); 4090 return ERR_PTR(rc); 4091 } 4092 4093 struct ib_mr *bnxt_re_reg_user_mr(struct ib_pd *ib_pd, u64 start, u64 length, 4094 u64 virt_addr, int mr_access_flags, 4095 struct ib_udata *udata) 4096 { 4097 struct bnxt_re_pd *pd = container_of(ib_pd, struct bnxt_re_pd, ib_pd); 4098 struct bnxt_re_dev *rdev = pd->rdev; 4099 struct ib_umem *umem; 4100 struct ib_mr *ib_mr; 4101 4102 umem = ib_umem_get(&rdev->ibdev, start, length, mr_access_flags); 4103 if (IS_ERR(umem)) 4104 return ERR_CAST(umem); 4105 4106 ib_mr = __bnxt_re_user_reg_mr(ib_pd, length, virt_addr, mr_access_flags, umem); 4107 if (IS_ERR(ib_mr)) 4108 ib_umem_release(umem); 4109 return ib_mr; 4110 } 4111 4112 struct ib_mr *bnxt_re_reg_user_mr_dmabuf(struct ib_pd *ib_pd, u64 start, 4113 u64 length, u64 virt_addr, int fd, 4114 int mr_access_flags, struct ib_udata *udata) 4115 { 4116 struct bnxt_re_pd *pd = container_of(ib_pd, struct bnxt_re_pd, ib_pd); 4117 struct bnxt_re_dev *rdev = pd->rdev; 4118 struct ib_umem_dmabuf *umem_dmabuf; 4119 struct ib_umem *umem; 4120 struct ib_mr *ib_mr; 4121 4122 umem_dmabuf = ib_umem_dmabuf_get_pinned(&rdev->ibdev, start, length, 4123 fd, mr_access_flags); 4124 if (IS_ERR(umem_dmabuf)) 4125 return ERR_CAST(umem_dmabuf); 4126 4127 umem = &umem_dmabuf->umem; 4128 4129 ib_mr = __bnxt_re_user_reg_mr(ib_pd, length, virt_addr, mr_access_flags, umem); 4130 if (IS_ERR(ib_mr)) 4131 ib_umem_release(umem); 4132 return ib_mr; 4133 } 4134 4135 int bnxt_re_alloc_ucontext(struct ib_ucontext *ctx, struct ib_udata *udata) 4136 { 4137 struct ib_device *ibdev = ctx->device; 4138 struct bnxt_re_ucontext *uctx = 4139 container_of(ctx, struct bnxt_re_ucontext, ib_uctx); 4140 struct bnxt_re_dev *rdev = to_bnxt_re_dev(ibdev, ibdev); 4141 struct bnxt_qplib_dev_attr *dev_attr = &rdev->dev_attr; 4142 struct bnxt_re_user_mmap_entry *entry; 4143 struct bnxt_re_uctx_resp resp = {}; 4144 struct bnxt_re_uctx_req ureq = {}; 4145 u32 chip_met_rev_num = 0; 4146 int rc; 4147 4148 ibdev_dbg(ibdev, "ABI version requested %u", ibdev->ops.uverbs_abi_ver); 4149 4150 if (ibdev->ops.uverbs_abi_ver != BNXT_RE_ABI_VERSION) { 4151 ibdev_dbg(ibdev, " is different from the device %d ", 4152 BNXT_RE_ABI_VERSION); 4153 return -EPERM; 4154 } 4155 4156 uctx->rdev = rdev; 4157 4158 uctx->shpg = (void *)__get_free_page(GFP_KERNEL); 4159 if (!uctx->shpg) { 4160 rc = -ENOMEM; 4161 goto fail; 4162 } 4163 spin_lock_init(&uctx->sh_lock); 4164 4165 resp.comp_mask = BNXT_RE_UCNTX_CMASK_HAVE_CCTX; 4166 chip_met_rev_num = rdev->chip_ctx->chip_num; 4167 chip_met_rev_num |= ((u32)rdev->chip_ctx->chip_rev & 0xFF) << 4168 BNXT_RE_CHIP_ID0_CHIP_REV_SFT; 4169 chip_met_rev_num |= ((u32)rdev->chip_ctx->chip_metal & 0xFF) << 4170 BNXT_RE_CHIP_ID0_CHIP_MET_SFT; 4171 resp.chip_id0 = chip_met_rev_num; 4172 /*Temp, Use xa_alloc instead */ 4173 resp.dev_id = rdev->en_dev->pdev->devfn; 4174 resp.max_qp = rdev->qplib_ctx.qpc_count; 4175 resp.pg_size = PAGE_SIZE; 4176 resp.cqe_sz = sizeof(struct cq_base); 4177 resp.max_cqd = dev_attr->max_cq_wqes; 4178 4179 if (rdev->chip_ctx->modes.db_push) 4180 resp.comp_mask |= BNXT_RE_UCNTX_CMASK_WC_DPI_ENABLED; 4181 4182 entry = bnxt_re_mmap_entry_insert(uctx, 0, BNXT_RE_MMAP_SH_PAGE, NULL); 4183 if (!entry) { 4184 rc = -ENOMEM; 4185 goto cfail; 4186 } 4187 uctx->shpage_mmap = &entry->rdma_entry; 4188 if (rdev->pacing.dbr_pacing) 4189 resp.comp_mask |= BNXT_RE_UCNTX_CMASK_DBR_PACING_ENABLED; 4190 4191 if (udata->inlen >= sizeof(ureq)) { 4192 rc = ib_copy_from_udata(&ureq, udata, min(udata->inlen, sizeof(ureq))); 4193 if (rc) 4194 goto cfail; 4195 if (ureq.comp_mask & BNXT_RE_COMP_MASK_REQ_UCNTX_POW2_SUPPORT) { 4196 resp.comp_mask |= BNXT_RE_UCNTX_CMASK_POW2_DISABLED; 4197 uctx->cmask |= BNXT_RE_UCNTX_CMASK_POW2_DISABLED; 4198 } 4199 } 4200 4201 rc = ib_copy_to_udata(udata, &resp, min(udata->outlen, sizeof(resp))); 4202 if (rc) { 4203 ibdev_err(ibdev, "Failed to copy user context"); 4204 rc = -EFAULT; 4205 goto cfail; 4206 } 4207 4208 return 0; 4209 cfail: 4210 free_page((unsigned long)uctx->shpg); 4211 uctx->shpg = NULL; 4212 fail: 4213 return rc; 4214 } 4215 4216 void bnxt_re_dealloc_ucontext(struct ib_ucontext *ib_uctx) 4217 { 4218 struct bnxt_re_ucontext *uctx = container_of(ib_uctx, 4219 struct bnxt_re_ucontext, 4220 ib_uctx); 4221 4222 struct bnxt_re_dev *rdev = uctx->rdev; 4223 4224 rdma_user_mmap_entry_remove(uctx->shpage_mmap); 4225 uctx->shpage_mmap = NULL; 4226 if (uctx->shpg) 4227 free_page((unsigned long)uctx->shpg); 4228 4229 if (uctx->dpi.dbr) { 4230 /* Free DPI only if this is the first PD allocated by the 4231 * application and mark the context dpi as NULL 4232 */ 4233 bnxt_qplib_dealloc_dpi(&rdev->qplib_res, &uctx->dpi); 4234 uctx->dpi.dbr = NULL; 4235 } 4236 } 4237 4238 /* Helper function to mmap the virtual memory from user app */ 4239 int bnxt_re_mmap(struct ib_ucontext *ib_uctx, struct vm_area_struct *vma) 4240 { 4241 struct bnxt_re_ucontext *uctx = container_of(ib_uctx, 4242 struct bnxt_re_ucontext, 4243 ib_uctx); 4244 struct bnxt_re_user_mmap_entry *bnxt_entry; 4245 struct rdma_user_mmap_entry *rdma_entry; 4246 int ret = 0; 4247 u64 pfn; 4248 4249 rdma_entry = rdma_user_mmap_entry_get(&uctx->ib_uctx, vma); 4250 if (!rdma_entry) 4251 return -EINVAL; 4252 4253 bnxt_entry = container_of(rdma_entry, struct bnxt_re_user_mmap_entry, 4254 rdma_entry); 4255 4256 switch (bnxt_entry->mmap_flag) { 4257 case BNXT_RE_MMAP_WC_DB: 4258 pfn = bnxt_entry->mem_offset >> PAGE_SHIFT; 4259 ret = rdma_user_mmap_io(ib_uctx, vma, pfn, PAGE_SIZE, 4260 pgprot_writecombine(vma->vm_page_prot), 4261 rdma_entry); 4262 break; 4263 case BNXT_RE_MMAP_UC_DB: 4264 pfn = bnxt_entry->mem_offset >> PAGE_SHIFT; 4265 ret = rdma_user_mmap_io(ib_uctx, vma, pfn, PAGE_SIZE, 4266 pgprot_noncached(vma->vm_page_prot), 4267 rdma_entry); 4268 break; 4269 case BNXT_RE_MMAP_SH_PAGE: 4270 ret = vm_insert_page(vma, vma->vm_start, virt_to_page(uctx->shpg)); 4271 break; 4272 case BNXT_RE_MMAP_DBR_BAR: 4273 pfn = bnxt_entry->mem_offset >> PAGE_SHIFT; 4274 ret = rdma_user_mmap_io(ib_uctx, vma, pfn, PAGE_SIZE, 4275 pgprot_noncached(vma->vm_page_prot), 4276 rdma_entry); 4277 break; 4278 case BNXT_RE_MMAP_DBR_PAGE: 4279 /* Driver doesn't expect write access for user space */ 4280 if (vma->vm_flags & VM_WRITE) 4281 ret = -EFAULT; 4282 else 4283 ret = vm_insert_page(vma, vma->vm_start, 4284 virt_to_page((void *)bnxt_entry->mem_offset)); 4285 break; 4286 default: 4287 ret = -EINVAL; 4288 break; 4289 } 4290 4291 rdma_user_mmap_entry_put(rdma_entry); 4292 return ret; 4293 } 4294 4295 void bnxt_re_mmap_free(struct rdma_user_mmap_entry *rdma_entry) 4296 { 4297 struct bnxt_re_user_mmap_entry *bnxt_entry; 4298 4299 bnxt_entry = container_of(rdma_entry, struct bnxt_re_user_mmap_entry, 4300 rdma_entry); 4301 4302 kfree(bnxt_entry); 4303 } 4304 4305 static int UVERBS_HANDLER(BNXT_RE_METHOD_NOTIFY_DRV)(struct uverbs_attr_bundle *attrs) 4306 { 4307 struct bnxt_re_ucontext *uctx; 4308 4309 uctx = container_of(ib_uverbs_get_ucontext(attrs), struct bnxt_re_ucontext, ib_uctx); 4310 bnxt_re_pacing_alert(uctx->rdev); 4311 return 0; 4312 } 4313 4314 static int UVERBS_HANDLER(BNXT_RE_METHOD_ALLOC_PAGE)(struct uverbs_attr_bundle *attrs) 4315 { 4316 struct ib_uobject *uobj = uverbs_attr_get_uobject(attrs, BNXT_RE_ALLOC_PAGE_HANDLE); 4317 enum bnxt_re_alloc_page_type alloc_type; 4318 struct bnxt_re_user_mmap_entry *entry; 4319 enum bnxt_re_mmap_flag mmap_flag; 4320 struct bnxt_qplib_chip_ctx *cctx; 4321 struct bnxt_re_ucontext *uctx; 4322 struct bnxt_re_dev *rdev; 4323 u64 mmap_offset; 4324 u32 length; 4325 u32 dpi; 4326 u64 addr; 4327 int err; 4328 4329 uctx = container_of(ib_uverbs_get_ucontext(attrs), struct bnxt_re_ucontext, ib_uctx); 4330 if (IS_ERR(uctx)) 4331 return PTR_ERR(uctx); 4332 4333 err = uverbs_get_const(&alloc_type, attrs, BNXT_RE_ALLOC_PAGE_TYPE); 4334 if (err) 4335 return err; 4336 4337 rdev = uctx->rdev; 4338 cctx = rdev->chip_ctx; 4339 4340 switch (alloc_type) { 4341 case BNXT_RE_ALLOC_WC_PAGE: 4342 if (cctx->modes.db_push) { 4343 if (bnxt_qplib_alloc_dpi(&rdev->qplib_res, &uctx->wcdpi, 4344 uctx, BNXT_QPLIB_DPI_TYPE_WC)) 4345 return -ENOMEM; 4346 length = PAGE_SIZE; 4347 dpi = uctx->wcdpi.dpi; 4348 addr = (u64)uctx->wcdpi.umdbr; 4349 mmap_flag = BNXT_RE_MMAP_WC_DB; 4350 } else { 4351 return -EINVAL; 4352 } 4353 4354 break; 4355 case BNXT_RE_ALLOC_DBR_BAR_PAGE: 4356 length = PAGE_SIZE; 4357 addr = (u64)rdev->pacing.dbr_bar_addr; 4358 mmap_flag = BNXT_RE_MMAP_DBR_BAR; 4359 break; 4360 4361 case BNXT_RE_ALLOC_DBR_PAGE: 4362 length = PAGE_SIZE; 4363 addr = (u64)rdev->pacing.dbr_page; 4364 mmap_flag = BNXT_RE_MMAP_DBR_PAGE; 4365 break; 4366 4367 default: 4368 return -EOPNOTSUPP; 4369 } 4370 4371 entry = bnxt_re_mmap_entry_insert(uctx, addr, mmap_flag, &mmap_offset); 4372 if (!entry) 4373 return -ENOMEM; 4374 4375 uobj->object = entry; 4376 uverbs_finalize_uobj_create(attrs, BNXT_RE_ALLOC_PAGE_HANDLE); 4377 err = uverbs_copy_to(attrs, BNXT_RE_ALLOC_PAGE_MMAP_OFFSET, 4378 &mmap_offset, sizeof(mmap_offset)); 4379 if (err) 4380 return err; 4381 4382 err = uverbs_copy_to(attrs, BNXT_RE_ALLOC_PAGE_MMAP_LENGTH, 4383 &length, sizeof(length)); 4384 if (err) 4385 return err; 4386 4387 err = uverbs_copy_to(attrs, BNXT_RE_ALLOC_PAGE_DPI, 4388 &dpi, sizeof(length)); 4389 if (err) 4390 return err; 4391 4392 return 0; 4393 } 4394 4395 static int alloc_page_obj_cleanup(struct ib_uobject *uobject, 4396 enum rdma_remove_reason why, 4397 struct uverbs_attr_bundle *attrs) 4398 { 4399 struct bnxt_re_user_mmap_entry *entry = uobject->object; 4400 struct bnxt_re_ucontext *uctx = entry->uctx; 4401 4402 switch (entry->mmap_flag) { 4403 case BNXT_RE_MMAP_WC_DB: 4404 if (uctx && uctx->wcdpi.dbr) { 4405 struct bnxt_re_dev *rdev = uctx->rdev; 4406 4407 bnxt_qplib_dealloc_dpi(&rdev->qplib_res, &uctx->wcdpi); 4408 uctx->wcdpi.dbr = NULL; 4409 } 4410 break; 4411 case BNXT_RE_MMAP_DBR_BAR: 4412 case BNXT_RE_MMAP_DBR_PAGE: 4413 break; 4414 default: 4415 goto exit; 4416 } 4417 rdma_user_mmap_entry_remove(&entry->rdma_entry); 4418 exit: 4419 return 0; 4420 } 4421 4422 DECLARE_UVERBS_NAMED_METHOD(BNXT_RE_METHOD_ALLOC_PAGE, 4423 UVERBS_ATTR_IDR(BNXT_RE_ALLOC_PAGE_HANDLE, 4424 BNXT_RE_OBJECT_ALLOC_PAGE, 4425 UVERBS_ACCESS_NEW, 4426 UA_MANDATORY), 4427 UVERBS_ATTR_CONST_IN(BNXT_RE_ALLOC_PAGE_TYPE, 4428 enum bnxt_re_alloc_page_type, 4429 UA_MANDATORY), 4430 UVERBS_ATTR_PTR_OUT(BNXT_RE_ALLOC_PAGE_MMAP_OFFSET, 4431 UVERBS_ATTR_TYPE(u64), 4432 UA_MANDATORY), 4433 UVERBS_ATTR_PTR_OUT(BNXT_RE_ALLOC_PAGE_MMAP_LENGTH, 4434 UVERBS_ATTR_TYPE(u32), 4435 UA_MANDATORY), 4436 UVERBS_ATTR_PTR_OUT(BNXT_RE_ALLOC_PAGE_DPI, 4437 UVERBS_ATTR_TYPE(u32), 4438 UA_MANDATORY)); 4439 4440 DECLARE_UVERBS_NAMED_METHOD_DESTROY(BNXT_RE_METHOD_DESTROY_PAGE, 4441 UVERBS_ATTR_IDR(BNXT_RE_DESTROY_PAGE_HANDLE, 4442 BNXT_RE_OBJECT_ALLOC_PAGE, 4443 UVERBS_ACCESS_DESTROY, 4444 UA_MANDATORY)); 4445 4446 DECLARE_UVERBS_NAMED_OBJECT(BNXT_RE_OBJECT_ALLOC_PAGE, 4447 UVERBS_TYPE_ALLOC_IDR(alloc_page_obj_cleanup), 4448 &UVERBS_METHOD(BNXT_RE_METHOD_ALLOC_PAGE), 4449 &UVERBS_METHOD(BNXT_RE_METHOD_DESTROY_PAGE)); 4450 4451 DECLARE_UVERBS_NAMED_METHOD(BNXT_RE_METHOD_NOTIFY_DRV); 4452 4453 DECLARE_UVERBS_GLOBAL_METHODS(BNXT_RE_OBJECT_NOTIFY_DRV, 4454 &UVERBS_METHOD(BNXT_RE_METHOD_NOTIFY_DRV)); 4455 4456 const struct uapi_definition bnxt_re_uapi_defs[] = { 4457 UAPI_DEF_CHAIN_OBJ_TREE_NAMED(BNXT_RE_OBJECT_ALLOC_PAGE), 4458 UAPI_DEF_CHAIN_OBJ_TREE_NAMED(BNXT_RE_OBJECT_NOTIFY_DRV), 4459 {} 4460 }; 4461