1 /* 2 * Broadcom NetXtreme-E RoCE driver. 3 * 4 * Copyright (c) 2016 - 2017, Broadcom. All rights reserved. The term 5 * Broadcom refers to Broadcom Limited and/or its subsidiaries. 6 * 7 * This software is available to you under a choice of one of two 8 * licenses. You may choose to be licensed under the terms of the GNU 9 * General Public License (GPL) Version 2, available from the file 10 * COPYING in the main directory of this source tree, or the 11 * BSD license below: 12 * 13 * Redistribution and use in source and binary forms, with or without 14 * modification, are permitted provided that the following conditions 15 * are met: 16 * 17 * 1. Redistributions of source code must retain the above copyright 18 * notice, this list of conditions and the following disclaimer. 19 * 2. Redistributions in binary form must reproduce the above copyright 20 * notice, this list of conditions and the following disclaimer in 21 * the documentation and/or other materials provided with the 22 * distribution. 23 * 24 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' 25 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, 26 * THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR 27 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS 28 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 29 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 30 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR 31 * BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, 32 * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE 33 * OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN 34 * IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 35 * 36 * Description: IB Verbs interpreter 37 */ 38 39 #include <linux/interrupt.h> 40 #include <linux/types.h> 41 #include <linux/pci.h> 42 #include <linux/netdevice.h> 43 #include <linux/if_ether.h> 44 #include <net/addrconf.h> 45 46 #include <rdma/ib_verbs.h> 47 #include <rdma/ib_user_verbs.h> 48 #include <rdma/ib_umem.h> 49 #include <rdma/ib_addr.h> 50 #include <rdma/ib_mad.h> 51 #include <rdma/ib_cache.h> 52 #include <rdma/uverbs_ioctl.h> 53 54 #include "bnxt_ulp.h" 55 56 #include "roce_hsi.h" 57 #include "qplib_res.h" 58 #include "qplib_sp.h" 59 #include "qplib_fp.h" 60 #include "qplib_rcfw.h" 61 62 #include "bnxt_re.h" 63 #include "ib_verbs.h" 64 65 #include <rdma/uverbs_types.h> 66 #include <rdma/uverbs_std_types.h> 67 68 #include <rdma/ib_user_ioctl_cmds.h> 69 70 #define UVERBS_MODULE_NAME bnxt_re 71 #include <rdma/uverbs_named_ioctl.h> 72 73 #include <rdma/bnxt_re-abi.h> 74 75 static int __from_ib_access_flags(int iflags) 76 { 77 int qflags = 0; 78 79 if (iflags & IB_ACCESS_LOCAL_WRITE) 80 qflags |= BNXT_QPLIB_ACCESS_LOCAL_WRITE; 81 if (iflags & IB_ACCESS_REMOTE_READ) 82 qflags |= BNXT_QPLIB_ACCESS_REMOTE_READ; 83 if (iflags & IB_ACCESS_REMOTE_WRITE) 84 qflags |= BNXT_QPLIB_ACCESS_REMOTE_WRITE; 85 if (iflags & IB_ACCESS_REMOTE_ATOMIC) 86 qflags |= BNXT_QPLIB_ACCESS_REMOTE_ATOMIC; 87 if (iflags & IB_ACCESS_MW_BIND) 88 qflags |= BNXT_QPLIB_ACCESS_MW_BIND; 89 if (iflags & IB_ZERO_BASED) 90 qflags |= BNXT_QPLIB_ACCESS_ZERO_BASED; 91 if (iflags & IB_ACCESS_ON_DEMAND) 92 qflags |= BNXT_QPLIB_ACCESS_ON_DEMAND; 93 return qflags; 94 }; 95 96 static enum ib_access_flags __to_ib_access_flags(int qflags) 97 { 98 enum ib_access_flags iflags = 0; 99 100 if (qflags & BNXT_QPLIB_ACCESS_LOCAL_WRITE) 101 iflags |= IB_ACCESS_LOCAL_WRITE; 102 if (qflags & BNXT_QPLIB_ACCESS_REMOTE_WRITE) 103 iflags |= IB_ACCESS_REMOTE_WRITE; 104 if (qflags & BNXT_QPLIB_ACCESS_REMOTE_READ) 105 iflags |= IB_ACCESS_REMOTE_READ; 106 if (qflags & BNXT_QPLIB_ACCESS_REMOTE_ATOMIC) 107 iflags |= IB_ACCESS_REMOTE_ATOMIC; 108 if (qflags & BNXT_QPLIB_ACCESS_MW_BIND) 109 iflags |= IB_ACCESS_MW_BIND; 110 if (qflags & BNXT_QPLIB_ACCESS_ZERO_BASED) 111 iflags |= IB_ZERO_BASED; 112 if (qflags & BNXT_QPLIB_ACCESS_ON_DEMAND) 113 iflags |= IB_ACCESS_ON_DEMAND; 114 return iflags; 115 }; 116 117 static int bnxt_re_build_sgl(struct ib_sge *ib_sg_list, 118 struct bnxt_qplib_sge *sg_list, int num) 119 { 120 int i, total = 0; 121 122 for (i = 0; i < num; i++) { 123 sg_list[i].addr = ib_sg_list[i].addr; 124 sg_list[i].lkey = ib_sg_list[i].lkey; 125 sg_list[i].size = ib_sg_list[i].length; 126 total += sg_list[i].size; 127 } 128 return total; 129 } 130 131 /* Device */ 132 int bnxt_re_query_device(struct ib_device *ibdev, 133 struct ib_device_attr *ib_attr, 134 struct ib_udata *udata) 135 { 136 struct bnxt_re_dev *rdev = to_bnxt_re_dev(ibdev, ibdev); 137 struct bnxt_qplib_dev_attr *dev_attr = &rdev->dev_attr; 138 139 memset(ib_attr, 0, sizeof(*ib_attr)); 140 memcpy(&ib_attr->fw_ver, dev_attr->fw_ver, 141 min(sizeof(dev_attr->fw_ver), 142 sizeof(ib_attr->fw_ver))); 143 addrconf_addr_eui48((u8 *)&ib_attr->sys_image_guid, 144 rdev->netdev->dev_addr); 145 ib_attr->max_mr_size = BNXT_RE_MAX_MR_SIZE; 146 ib_attr->page_size_cap = BNXT_RE_PAGE_SIZE_SUPPORTED; 147 148 ib_attr->vendor_id = rdev->en_dev->pdev->vendor; 149 ib_attr->vendor_part_id = rdev->en_dev->pdev->device; 150 ib_attr->hw_ver = rdev->en_dev->pdev->subsystem_device; 151 ib_attr->max_qp = dev_attr->max_qp; 152 ib_attr->max_qp_wr = dev_attr->max_qp_wqes; 153 ib_attr->device_cap_flags = 154 IB_DEVICE_CURR_QP_STATE_MOD 155 | IB_DEVICE_RC_RNR_NAK_GEN 156 | IB_DEVICE_SHUTDOWN_PORT 157 | IB_DEVICE_SYS_IMAGE_GUID 158 | IB_DEVICE_RESIZE_MAX_WR 159 | IB_DEVICE_PORT_ACTIVE_EVENT 160 | IB_DEVICE_N_NOTIFY_CQ 161 | IB_DEVICE_MEM_WINDOW 162 | IB_DEVICE_MEM_WINDOW_TYPE_2B 163 | IB_DEVICE_MEM_MGT_EXTENSIONS; 164 ib_attr->kernel_cap_flags = IBK_LOCAL_DMA_LKEY; 165 ib_attr->max_send_sge = dev_attr->max_qp_sges; 166 ib_attr->max_recv_sge = dev_attr->max_qp_sges; 167 ib_attr->max_sge_rd = dev_attr->max_qp_sges; 168 ib_attr->max_cq = dev_attr->max_cq; 169 ib_attr->max_cqe = dev_attr->max_cq_wqes; 170 ib_attr->max_mr = dev_attr->max_mr; 171 ib_attr->max_pd = dev_attr->max_pd; 172 ib_attr->max_qp_rd_atom = dev_attr->max_qp_rd_atom; 173 ib_attr->max_qp_init_rd_atom = dev_attr->max_qp_init_rd_atom; 174 ib_attr->atomic_cap = IB_ATOMIC_NONE; 175 ib_attr->masked_atomic_cap = IB_ATOMIC_NONE; 176 if (dev_attr->is_atomic) { 177 ib_attr->atomic_cap = IB_ATOMIC_GLOB; 178 ib_attr->masked_atomic_cap = IB_ATOMIC_GLOB; 179 } 180 181 ib_attr->max_ee_rd_atom = 0; 182 ib_attr->max_res_rd_atom = 0; 183 ib_attr->max_ee_init_rd_atom = 0; 184 ib_attr->max_ee = 0; 185 ib_attr->max_rdd = 0; 186 ib_attr->max_mw = dev_attr->max_mw; 187 ib_attr->max_raw_ipv6_qp = 0; 188 ib_attr->max_raw_ethy_qp = dev_attr->max_raw_ethy_qp; 189 ib_attr->max_mcast_grp = 0; 190 ib_attr->max_mcast_qp_attach = 0; 191 ib_attr->max_total_mcast_qp_attach = 0; 192 ib_attr->max_ah = dev_attr->max_ah; 193 194 ib_attr->max_srq = dev_attr->max_srq; 195 ib_attr->max_srq_wr = dev_attr->max_srq_wqes; 196 ib_attr->max_srq_sge = dev_attr->max_srq_sges; 197 198 ib_attr->max_fast_reg_page_list_len = MAX_PBL_LVL_1_PGS; 199 200 ib_attr->max_pkeys = 1; 201 ib_attr->local_ca_ack_delay = BNXT_RE_DEFAULT_ACK_DELAY; 202 return 0; 203 } 204 205 /* Port */ 206 int bnxt_re_query_port(struct ib_device *ibdev, u32 port_num, 207 struct ib_port_attr *port_attr) 208 { 209 struct bnxt_re_dev *rdev = to_bnxt_re_dev(ibdev, ibdev); 210 struct bnxt_qplib_dev_attr *dev_attr = &rdev->dev_attr; 211 int rc; 212 213 memset(port_attr, 0, sizeof(*port_attr)); 214 215 if (netif_running(rdev->netdev) && netif_carrier_ok(rdev->netdev)) { 216 port_attr->state = IB_PORT_ACTIVE; 217 port_attr->phys_state = IB_PORT_PHYS_STATE_LINK_UP; 218 } else { 219 port_attr->state = IB_PORT_DOWN; 220 port_attr->phys_state = IB_PORT_PHYS_STATE_DISABLED; 221 } 222 port_attr->max_mtu = IB_MTU_4096; 223 port_attr->active_mtu = iboe_get_mtu(rdev->netdev->mtu); 224 port_attr->gid_tbl_len = dev_attr->max_sgid; 225 port_attr->port_cap_flags = IB_PORT_CM_SUP | IB_PORT_REINIT_SUP | 226 IB_PORT_DEVICE_MGMT_SUP | 227 IB_PORT_VENDOR_CLASS_SUP; 228 port_attr->ip_gids = true; 229 230 port_attr->max_msg_sz = (u32)BNXT_RE_MAX_MR_SIZE_LOW; 231 port_attr->bad_pkey_cntr = 0; 232 port_attr->qkey_viol_cntr = 0; 233 port_attr->pkey_tbl_len = dev_attr->max_pkey; 234 port_attr->lid = 0; 235 port_attr->sm_lid = 0; 236 port_attr->lmc = 0; 237 port_attr->max_vl_num = 4; 238 port_attr->sm_sl = 0; 239 port_attr->subnet_timeout = 0; 240 port_attr->init_type_reply = 0; 241 rc = ib_get_eth_speed(&rdev->ibdev, port_num, &port_attr->active_speed, 242 &port_attr->active_width); 243 244 return rc; 245 } 246 247 int bnxt_re_get_port_immutable(struct ib_device *ibdev, u32 port_num, 248 struct ib_port_immutable *immutable) 249 { 250 struct ib_port_attr port_attr; 251 252 if (bnxt_re_query_port(ibdev, port_num, &port_attr)) 253 return -EINVAL; 254 255 immutable->pkey_tbl_len = port_attr.pkey_tbl_len; 256 immutable->gid_tbl_len = port_attr.gid_tbl_len; 257 immutable->core_cap_flags = RDMA_CORE_PORT_IBA_ROCE; 258 immutable->core_cap_flags |= RDMA_CORE_CAP_PROT_ROCE_UDP_ENCAP; 259 immutable->max_mad_size = IB_MGMT_MAD_SIZE; 260 return 0; 261 } 262 263 void bnxt_re_query_fw_str(struct ib_device *ibdev, char *str) 264 { 265 struct bnxt_re_dev *rdev = to_bnxt_re_dev(ibdev, ibdev); 266 267 snprintf(str, IB_FW_VERSION_NAME_MAX, "%d.%d.%d.%d", 268 rdev->dev_attr.fw_ver[0], rdev->dev_attr.fw_ver[1], 269 rdev->dev_attr.fw_ver[2], rdev->dev_attr.fw_ver[3]); 270 } 271 272 int bnxt_re_query_pkey(struct ib_device *ibdev, u32 port_num, 273 u16 index, u16 *pkey) 274 { 275 if (index > 0) 276 return -EINVAL; 277 278 *pkey = IB_DEFAULT_PKEY_FULL; 279 280 return 0; 281 } 282 283 int bnxt_re_query_gid(struct ib_device *ibdev, u32 port_num, 284 int index, union ib_gid *gid) 285 { 286 struct bnxt_re_dev *rdev = to_bnxt_re_dev(ibdev, ibdev); 287 int rc = 0; 288 289 /* Ignore port_num */ 290 memset(gid, 0, sizeof(*gid)); 291 rc = bnxt_qplib_get_sgid(&rdev->qplib_res, 292 &rdev->qplib_res.sgid_tbl, index, 293 (struct bnxt_qplib_gid *)gid); 294 return rc; 295 } 296 297 int bnxt_re_del_gid(const struct ib_gid_attr *attr, void **context) 298 { 299 int rc = 0; 300 struct bnxt_re_gid_ctx *ctx, **ctx_tbl; 301 struct bnxt_re_dev *rdev = to_bnxt_re_dev(attr->device, ibdev); 302 struct bnxt_qplib_sgid_tbl *sgid_tbl = &rdev->qplib_res.sgid_tbl; 303 struct bnxt_qplib_gid *gid_to_del; 304 u16 vlan_id = 0xFFFF; 305 306 /* Delete the entry from the hardware */ 307 ctx = *context; 308 if (!ctx) 309 return -EINVAL; 310 311 if (sgid_tbl && sgid_tbl->active) { 312 if (ctx->idx >= sgid_tbl->max) 313 return -EINVAL; 314 gid_to_del = &sgid_tbl->tbl[ctx->idx].gid; 315 vlan_id = sgid_tbl->tbl[ctx->idx].vlan_id; 316 /* DEL_GID is called in WQ context(netdevice_event_work_handler) 317 * or via the ib_unregister_device path. In the former case QP1 318 * may not be destroyed yet, in which case just return as FW 319 * needs that entry to be present and will fail it's deletion. 320 * We could get invoked again after QP1 is destroyed OR get an 321 * ADD_GID call with a different GID value for the same index 322 * where we issue MODIFY_GID cmd to update the GID entry -- TBD 323 */ 324 if (ctx->idx == 0 && 325 rdma_link_local_addr((struct in6_addr *)gid_to_del) && 326 ctx->refcnt == 1 && rdev->gsi_ctx.gsi_sqp) { 327 ibdev_dbg(&rdev->ibdev, 328 "Trying to delete GID0 while QP1 is alive\n"); 329 return -EFAULT; 330 } 331 ctx->refcnt--; 332 if (!ctx->refcnt) { 333 rc = bnxt_qplib_del_sgid(sgid_tbl, gid_to_del, 334 vlan_id, true); 335 if (rc) { 336 ibdev_err(&rdev->ibdev, 337 "Failed to remove GID: %#x", rc); 338 } else { 339 ctx_tbl = sgid_tbl->ctx; 340 ctx_tbl[ctx->idx] = NULL; 341 kfree(ctx); 342 } 343 } 344 } else { 345 return -EINVAL; 346 } 347 return rc; 348 } 349 350 int bnxt_re_add_gid(const struct ib_gid_attr *attr, void **context) 351 { 352 int rc; 353 u32 tbl_idx = 0; 354 u16 vlan_id = 0xFFFF; 355 struct bnxt_re_gid_ctx *ctx, **ctx_tbl; 356 struct bnxt_re_dev *rdev = to_bnxt_re_dev(attr->device, ibdev); 357 struct bnxt_qplib_sgid_tbl *sgid_tbl = &rdev->qplib_res.sgid_tbl; 358 359 rc = rdma_read_gid_l2_fields(attr, &vlan_id, NULL); 360 if (rc) 361 return rc; 362 363 rc = bnxt_qplib_add_sgid(sgid_tbl, (struct bnxt_qplib_gid *)&attr->gid, 364 rdev->qplib_res.netdev->dev_addr, 365 vlan_id, true, &tbl_idx); 366 if (rc == -EALREADY) { 367 ctx_tbl = sgid_tbl->ctx; 368 ctx_tbl[tbl_idx]->refcnt++; 369 *context = ctx_tbl[tbl_idx]; 370 return 0; 371 } 372 373 if (rc < 0) { 374 ibdev_err(&rdev->ibdev, "Failed to add GID: %#x", rc); 375 return rc; 376 } 377 378 ctx = kmalloc(sizeof(*ctx), GFP_KERNEL); 379 if (!ctx) 380 return -ENOMEM; 381 ctx_tbl = sgid_tbl->ctx; 382 ctx->idx = tbl_idx; 383 ctx->refcnt = 1; 384 ctx_tbl[tbl_idx] = ctx; 385 *context = ctx; 386 387 return rc; 388 } 389 390 enum rdma_link_layer bnxt_re_get_link_layer(struct ib_device *ibdev, 391 u32 port_num) 392 { 393 return IB_LINK_LAYER_ETHERNET; 394 } 395 396 #define BNXT_RE_FENCE_PBL_SIZE DIV_ROUND_UP(BNXT_RE_FENCE_BYTES, PAGE_SIZE) 397 398 static void bnxt_re_create_fence_wqe(struct bnxt_re_pd *pd) 399 { 400 struct bnxt_re_fence_data *fence = &pd->fence; 401 struct ib_mr *ib_mr = &fence->mr->ib_mr; 402 struct bnxt_qplib_swqe *wqe = &fence->bind_wqe; 403 404 memset(wqe, 0, sizeof(*wqe)); 405 wqe->type = BNXT_QPLIB_SWQE_TYPE_BIND_MW; 406 wqe->wr_id = BNXT_QPLIB_FENCE_WRID; 407 wqe->flags |= BNXT_QPLIB_SWQE_FLAGS_SIGNAL_COMP; 408 wqe->flags |= BNXT_QPLIB_SWQE_FLAGS_UC_FENCE; 409 wqe->bind.zero_based = false; 410 wqe->bind.parent_l_key = ib_mr->lkey; 411 wqe->bind.va = (u64)(unsigned long)fence->va; 412 wqe->bind.length = fence->size; 413 wqe->bind.access_cntl = __from_ib_access_flags(IB_ACCESS_REMOTE_READ); 414 wqe->bind.mw_type = SQ_BIND_MW_TYPE_TYPE1; 415 416 /* Save the initial rkey in fence structure for now; 417 * wqe->bind.r_key will be set at (re)bind time. 418 */ 419 fence->bind_rkey = ib_inc_rkey(fence->mw->rkey); 420 } 421 422 static int bnxt_re_bind_fence_mw(struct bnxt_qplib_qp *qplib_qp) 423 { 424 struct bnxt_re_qp *qp = container_of(qplib_qp, struct bnxt_re_qp, 425 qplib_qp); 426 struct ib_pd *ib_pd = qp->ib_qp.pd; 427 struct bnxt_re_pd *pd = container_of(ib_pd, struct bnxt_re_pd, ib_pd); 428 struct bnxt_re_fence_data *fence = &pd->fence; 429 struct bnxt_qplib_swqe *fence_wqe = &fence->bind_wqe; 430 struct bnxt_qplib_swqe wqe; 431 int rc; 432 433 memcpy(&wqe, fence_wqe, sizeof(wqe)); 434 wqe.bind.r_key = fence->bind_rkey; 435 fence->bind_rkey = ib_inc_rkey(fence->bind_rkey); 436 437 ibdev_dbg(&qp->rdev->ibdev, 438 "Posting bind fence-WQE: rkey: %#x QP: %d PD: %p\n", 439 wqe.bind.r_key, qp->qplib_qp.id, pd); 440 rc = bnxt_qplib_post_send(&qp->qplib_qp, &wqe); 441 if (rc) { 442 ibdev_err(&qp->rdev->ibdev, "Failed to bind fence-WQE\n"); 443 return rc; 444 } 445 bnxt_qplib_post_send_db(&qp->qplib_qp); 446 447 return rc; 448 } 449 450 static void bnxt_re_destroy_fence_mr(struct bnxt_re_pd *pd) 451 { 452 struct bnxt_re_fence_data *fence = &pd->fence; 453 struct bnxt_re_dev *rdev = pd->rdev; 454 struct device *dev = &rdev->en_dev->pdev->dev; 455 struct bnxt_re_mr *mr = fence->mr; 456 457 if (fence->mw) { 458 bnxt_re_dealloc_mw(fence->mw); 459 fence->mw = NULL; 460 } 461 if (mr) { 462 if (mr->ib_mr.rkey) 463 bnxt_qplib_dereg_mrw(&rdev->qplib_res, &mr->qplib_mr, 464 true); 465 if (mr->ib_mr.lkey) 466 bnxt_qplib_free_mrw(&rdev->qplib_res, &mr->qplib_mr); 467 kfree(mr); 468 fence->mr = NULL; 469 } 470 if (fence->dma_addr) { 471 dma_unmap_single(dev, fence->dma_addr, BNXT_RE_FENCE_BYTES, 472 DMA_BIDIRECTIONAL); 473 fence->dma_addr = 0; 474 } 475 } 476 477 static int bnxt_re_create_fence_mr(struct bnxt_re_pd *pd) 478 { 479 int mr_access_flags = IB_ACCESS_LOCAL_WRITE | IB_ACCESS_MW_BIND; 480 struct bnxt_re_fence_data *fence = &pd->fence; 481 struct bnxt_re_dev *rdev = pd->rdev; 482 struct device *dev = &rdev->en_dev->pdev->dev; 483 struct bnxt_re_mr *mr = NULL; 484 dma_addr_t dma_addr = 0; 485 struct ib_mw *mw; 486 int rc; 487 488 dma_addr = dma_map_single(dev, fence->va, BNXT_RE_FENCE_BYTES, 489 DMA_BIDIRECTIONAL); 490 rc = dma_mapping_error(dev, dma_addr); 491 if (rc) { 492 ibdev_err(&rdev->ibdev, "Failed to dma-map fence-MR-mem\n"); 493 rc = -EIO; 494 fence->dma_addr = 0; 495 goto fail; 496 } 497 fence->dma_addr = dma_addr; 498 499 /* Allocate a MR */ 500 mr = kzalloc(sizeof(*mr), GFP_KERNEL); 501 if (!mr) { 502 rc = -ENOMEM; 503 goto fail; 504 } 505 fence->mr = mr; 506 mr->rdev = rdev; 507 mr->qplib_mr.pd = &pd->qplib_pd; 508 mr->qplib_mr.type = CMDQ_ALLOCATE_MRW_MRW_FLAGS_PMR; 509 mr->qplib_mr.flags = __from_ib_access_flags(mr_access_flags); 510 rc = bnxt_qplib_alloc_mrw(&rdev->qplib_res, &mr->qplib_mr); 511 if (rc) { 512 ibdev_err(&rdev->ibdev, "Failed to alloc fence-HW-MR\n"); 513 goto fail; 514 } 515 516 /* Register MR */ 517 mr->ib_mr.lkey = mr->qplib_mr.lkey; 518 mr->qplib_mr.va = (u64)(unsigned long)fence->va; 519 mr->qplib_mr.total_size = BNXT_RE_FENCE_BYTES; 520 rc = bnxt_qplib_reg_mr(&rdev->qplib_res, &mr->qplib_mr, NULL, 521 BNXT_RE_FENCE_PBL_SIZE, PAGE_SIZE); 522 if (rc) { 523 ibdev_err(&rdev->ibdev, "Failed to register fence-MR\n"); 524 goto fail; 525 } 526 mr->ib_mr.rkey = mr->qplib_mr.rkey; 527 528 /* Create a fence MW only for kernel consumers */ 529 mw = bnxt_re_alloc_mw(&pd->ib_pd, IB_MW_TYPE_1, NULL); 530 if (IS_ERR(mw)) { 531 ibdev_err(&rdev->ibdev, 532 "Failed to create fence-MW for PD: %p\n", pd); 533 rc = PTR_ERR(mw); 534 goto fail; 535 } 536 fence->mw = mw; 537 538 bnxt_re_create_fence_wqe(pd); 539 return 0; 540 541 fail: 542 bnxt_re_destroy_fence_mr(pd); 543 return rc; 544 } 545 546 static struct bnxt_re_user_mmap_entry* 547 bnxt_re_mmap_entry_insert(struct bnxt_re_ucontext *uctx, u64 mem_offset, 548 enum bnxt_re_mmap_flag mmap_flag, u64 *offset) 549 { 550 struct bnxt_re_user_mmap_entry *entry; 551 int ret; 552 553 entry = kzalloc(sizeof(*entry), GFP_KERNEL); 554 if (!entry) 555 return NULL; 556 557 entry->mem_offset = mem_offset; 558 entry->mmap_flag = mmap_flag; 559 entry->uctx = uctx; 560 561 switch (mmap_flag) { 562 case BNXT_RE_MMAP_SH_PAGE: 563 ret = rdma_user_mmap_entry_insert_exact(&uctx->ib_uctx, 564 &entry->rdma_entry, PAGE_SIZE, 0); 565 break; 566 case BNXT_RE_MMAP_UC_DB: 567 case BNXT_RE_MMAP_WC_DB: 568 ret = rdma_user_mmap_entry_insert(&uctx->ib_uctx, 569 &entry->rdma_entry, PAGE_SIZE); 570 break; 571 default: 572 ret = -EINVAL; 573 break; 574 } 575 576 if (ret) { 577 kfree(entry); 578 return NULL; 579 } 580 if (offset) 581 *offset = rdma_user_mmap_get_offset(&entry->rdma_entry); 582 583 return entry; 584 } 585 586 /* Protection Domains */ 587 int bnxt_re_dealloc_pd(struct ib_pd *ib_pd, struct ib_udata *udata) 588 { 589 struct bnxt_re_pd *pd = container_of(ib_pd, struct bnxt_re_pd, ib_pd); 590 struct bnxt_re_dev *rdev = pd->rdev; 591 592 if (udata) { 593 rdma_user_mmap_entry_remove(pd->pd_db_mmap); 594 pd->pd_db_mmap = NULL; 595 } 596 597 bnxt_re_destroy_fence_mr(pd); 598 599 if (pd->qplib_pd.id) { 600 if (!bnxt_qplib_dealloc_pd(&rdev->qplib_res, 601 &rdev->qplib_res.pd_tbl, 602 &pd->qplib_pd)) 603 atomic_dec(&rdev->pd_count); 604 } 605 return 0; 606 } 607 608 int bnxt_re_alloc_pd(struct ib_pd *ibpd, struct ib_udata *udata) 609 { 610 struct ib_device *ibdev = ibpd->device; 611 struct bnxt_re_dev *rdev = to_bnxt_re_dev(ibdev, ibdev); 612 struct bnxt_re_ucontext *ucntx = rdma_udata_to_drv_context( 613 udata, struct bnxt_re_ucontext, ib_uctx); 614 struct bnxt_re_pd *pd = container_of(ibpd, struct bnxt_re_pd, ib_pd); 615 struct bnxt_re_user_mmap_entry *entry = NULL; 616 int rc = 0; 617 618 pd->rdev = rdev; 619 if (bnxt_qplib_alloc_pd(&rdev->qplib_res.pd_tbl, &pd->qplib_pd)) { 620 ibdev_err(&rdev->ibdev, "Failed to allocate HW PD"); 621 rc = -ENOMEM; 622 goto fail; 623 } 624 625 if (udata) { 626 struct bnxt_re_pd_resp resp = {}; 627 628 if (!ucntx->dpi.dbr) { 629 /* Allocate DPI in alloc_pd to avoid failing of 630 * ibv_devinfo and family of application when DPIs 631 * are depleted. 632 */ 633 if (bnxt_qplib_alloc_dpi(&rdev->qplib_res, 634 &ucntx->dpi, ucntx, BNXT_QPLIB_DPI_TYPE_UC)) { 635 rc = -ENOMEM; 636 goto dbfail; 637 } 638 } 639 640 resp.pdid = pd->qplib_pd.id; 641 /* Still allow mapping this DBR to the new user PD. */ 642 resp.dpi = ucntx->dpi.dpi; 643 644 entry = bnxt_re_mmap_entry_insert(ucntx, (u64)ucntx->dpi.umdbr, 645 BNXT_RE_MMAP_UC_DB, &resp.dbr); 646 647 if (!entry) { 648 rc = -ENOMEM; 649 goto dbfail; 650 } 651 652 pd->pd_db_mmap = &entry->rdma_entry; 653 654 rc = ib_copy_to_udata(udata, &resp, min(sizeof(resp), udata->outlen)); 655 if (rc) { 656 rdma_user_mmap_entry_remove(pd->pd_db_mmap); 657 rc = -EFAULT; 658 goto dbfail; 659 } 660 } 661 662 if (!udata) 663 if (bnxt_re_create_fence_mr(pd)) 664 ibdev_warn(&rdev->ibdev, 665 "Failed to create Fence-MR\n"); 666 atomic_inc(&rdev->pd_count); 667 668 return 0; 669 dbfail: 670 bnxt_qplib_dealloc_pd(&rdev->qplib_res, &rdev->qplib_res.pd_tbl, 671 &pd->qplib_pd); 672 fail: 673 return rc; 674 } 675 676 /* Address Handles */ 677 int bnxt_re_destroy_ah(struct ib_ah *ib_ah, u32 flags) 678 { 679 struct bnxt_re_ah *ah = container_of(ib_ah, struct bnxt_re_ah, ib_ah); 680 struct bnxt_re_dev *rdev = ah->rdev; 681 bool block = true; 682 int rc = 0; 683 684 block = !(flags & RDMA_DESTROY_AH_SLEEPABLE); 685 rc = bnxt_qplib_destroy_ah(&rdev->qplib_res, &ah->qplib_ah, block); 686 if (BNXT_RE_CHECK_RC(rc)) { 687 if (rc == -ETIMEDOUT) 688 rc = 0; 689 else 690 goto fail; 691 } 692 atomic_dec(&rdev->ah_count); 693 fail: 694 return rc; 695 } 696 697 static u8 bnxt_re_stack_to_dev_nw_type(enum rdma_network_type ntype) 698 { 699 u8 nw_type; 700 701 switch (ntype) { 702 case RDMA_NETWORK_IPV4: 703 nw_type = CMDQ_CREATE_AH_TYPE_V2IPV4; 704 break; 705 case RDMA_NETWORK_IPV6: 706 nw_type = CMDQ_CREATE_AH_TYPE_V2IPV6; 707 break; 708 default: 709 nw_type = CMDQ_CREATE_AH_TYPE_V1; 710 break; 711 } 712 return nw_type; 713 } 714 715 int bnxt_re_create_ah(struct ib_ah *ib_ah, struct rdma_ah_init_attr *init_attr, 716 struct ib_udata *udata) 717 { 718 struct ib_pd *ib_pd = ib_ah->pd; 719 struct bnxt_re_pd *pd = container_of(ib_pd, struct bnxt_re_pd, ib_pd); 720 struct rdma_ah_attr *ah_attr = init_attr->ah_attr; 721 const struct ib_global_route *grh = rdma_ah_read_grh(ah_attr); 722 struct bnxt_re_dev *rdev = pd->rdev; 723 const struct ib_gid_attr *sgid_attr; 724 struct bnxt_re_gid_ctx *ctx; 725 struct bnxt_re_ah *ah = container_of(ib_ah, struct bnxt_re_ah, ib_ah); 726 u8 nw_type; 727 int rc; 728 729 if (!(rdma_ah_get_ah_flags(ah_attr) & IB_AH_GRH)) { 730 ibdev_err(&rdev->ibdev, "Failed to alloc AH: GRH not set"); 731 return -EINVAL; 732 } 733 734 ah->rdev = rdev; 735 ah->qplib_ah.pd = &pd->qplib_pd; 736 737 /* Supply the configuration for the HW */ 738 memcpy(ah->qplib_ah.dgid.data, grh->dgid.raw, 739 sizeof(union ib_gid)); 740 sgid_attr = grh->sgid_attr; 741 /* Get the HW context of the GID. The reference 742 * of GID table entry is already taken by the caller. 743 */ 744 ctx = rdma_read_gid_hw_context(sgid_attr); 745 ah->qplib_ah.sgid_index = ctx->idx; 746 ah->qplib_ah.host_sgid_index = grh->sgid_index; 747 ah->qplib_ah.traffic_class = grh->traffic_class; 748 ah->qplib_ah.flow_label = grh->flow_label; 749 ah->qplib_ah.hop_limit = grh->hop_limit; 750 ah->qplib_ah.sl = rdma_ah_get_sl(ah_attr); 751 752 /* Get network header type for this GID */ 753 nw_type = rdma_gid_attr_network_type(sgid_attr); 754 ah->qplib_ah.nw_type = bnxt_re_stack_to_dev_nw_type(nw_type); 755 756 memcpy(ah->qplib_ah.dmac, ah_attr->roce.dmac, ETH_ALEN); 757 rc = bnxt_qplib_create_ah(&rdev->qplib_res, &ah->qplib_ah, 758 !(init_attr->flags & 759 RDMA_CREATE_AH_SLEEPABLE)); 760 if (rc) { 761 ibdev_err(&rdev->ibdev, "Failed to allocate HW AH"); 762 return rc; 763 } 764 765 /* Write AVID to shared page. */ 766 if (udata) { 767 struct bnxt_re_ucontext *uctx = rdma_udata_to_drv_context( 768 udata, struct bnxt_re_ucontext, ib_uctx); 769 unsigned long flag; 770 u32 *wrptr; 771 772 spin_lock_irqsave(&uctx->sh_lock, flag); 773 wrptr = (u32 *)(uctx->shpg + BNXT_RE_AVID_OFFT); 774 *wrptr = ah->qplib_ah.id; 775 wmb(); /* make sure cache is updated. */ 776 spin_unlock_irqrestore(&uctx->sh_lock, flag); 777 } 778 atomic_inc(&rdev->ah_count); 779 780 return 0; 781 } 782 783 int bnxt_re_query_ah(struct ib_ah *ib_ah, struct rdma_ah_attr *ah_attr) 784 { 785 struct bnxt_re_ah *ah = container_of(ib_ah, struct bnxt_re_ah, ib_ah); 786 787 ah_attr->type = ib_ah->type; 788 rdma_ah_set_sl(ah_attr, ah->qplib_ah.sl); 789 memcpy(ah_attr->roce.dmac, ah->qplib_ah.dmac, ETH_ALEN); 790 rdma_ah_set_grh(ah_attr, NULL, 0, 791 ah->qplib_ah.host_sgid_index, 792 0, ah->qplib_ah.traffic_class); 793 rdma_ah_set_dgid_raw(ah_attr, ah->qplib_ah.dgid.data); 794 rdma_ah_set_port_num(ah_attr, 1); 795 rdma_ah_set_static_rate(ah_attr, 0); 796 return 0; 797 } 798 799 unsigned long bnxt_re_lock_cqs(struct bnxt_re_qp *qp) 800 __acquires(&qp->scq->cq_lock) __acquires(&qp->rcq->cq_lock) 801 { 802 unsigned long flags; 803 804 spin_lock_irqsave(&qp->scq->cq_lock, flags); 805 if (qp->rcq != qp->scq) 806 spin_lock(&qp->rcq->cq_lock); 807 else 808 __acquire(&qp->rcq->cq_lock); 809 810 return flags; 811 } 812 813 void bnxt_re_unlock_cqs(struct bnxt_re_qp *qp, 814 unsigned long flags) 815 __releases(&qp->scq->cq_lock) __releases(&qp->rcq->cq_lock) 816 { 817 if (qp->rcq != qp->scq) 818 spin_unlock(&qp->rcq->cq_lock); 819 else 820 __release(&qp->rcq->cq_lock); 821 spin_unlock_irqrestore(&qp->scq->cq_lock, flags); 822 } 823 824 static int bnxt_re_destroy_gsi_sqp(struct bnxt_re_qp *qp) 825 { 826 struct bnxt_re_qp *gsi_sqp; 827 struct bnxt_re_ah *gsi_sah; 828 struct bnxt_re_dev *rdev; 829 int rc = 0; 830 831 rdev = qp->rdev; 832 gsi_sqp = rdev->gsi_ctx.gsi_sqp; 833 gsi_sah = rdev->gsi_ctx.gsi_sah; 834 835 ibdev_dbg(&rdev->ibdev, "Destroy the shadow AH\n"); 836 bnxt_qplib_destroy_ah(&rdev->qplib_res, 837 &gsi_sah->qplib_ah, 838 true); 839 atomic_dec(&rdev->ah_count); 840 bnxt_qplib_clean_qp(&qp->qplib_qp); 841 842 ibdev_dbg(&rdev->ibdev, "Destroy the shadow QP\n"); 843 rc = bnxt_qplib_destroy_qp(&rdev->qplib_res, &gsi_sqp->qplib_qp); 844 if (rc) { 845 ibdev_err(&rdev->ibdev, "Destroy Shadow QP failed"); 846 goto fail; 847 } 848 bnxt_qplib_free_qp_res(&rdev->qplib_res, &gsi_sqp->qplib_qp); 849 850 /* remove from active qp list */ 851 mutex_lock(&rdev->qp_lock); 852 list_del(&gsi_sqp->list); 853 mutex_unlock(&rdev->qp_lock); 854 atomic_dec(&rdev->qp_count); 855 856 kfree(rdev->gsi_ctx.sqp_tbl); 857 kfree(gsi_sah); 858 kfree(gsi_sqp); 859 rdev->gsi_ctx.gsi_sqp = NULL; 860 rdev->gsi_ctx.gsi_sah = NULL; 861 rdev->gsi_ctx.sqp_tbl = NULL; 862 863 return 0; 864 fail: 865 return rc; 866 } 867 868 /* Queue Pairs */ 869 int bnxt_re_destroy_qp(struct ib_qp *ib_qp, struct ib_udata *udata) 870 { 871 struct bnxt_re_qp *qp = container_of(ib_qp, struct bnxt_re_qp, ib_qp); 872 struct bnxt_qplib_qp *qplib_qp = &qp->qplib_qp; 873 struct bnxt_re_dev *rdev = qp->rdev; 874 struct bnxt_qplib_nq *scq_nq = NULL; 875 struct bnxt_qplib_nq *rcq_nq = NULL; 876 unsigned int flags; 877 int rc; 878 879 bnxt_qplib_flush_cqn_wq(&qp->qplib_qp); 880 881 rc = bnxt_qplib_destroy_qp(&rdev->qplib_res, &qp->qplib_qp); 882 if (rc) { 883 ibdev_err(&rdev->ibdev, "Failed to destroy HW QP"); 884 return rc; 885 } 886 887 if (rdma_is_kernel_res(&qp->ib_qp.res)) { 888 flags = bnxt_re_lock_cqs(qp); 889 bnxt_qplib_clean_qp(&qp->qplib_qp); 890 bnxt_re_unlock_cqs(qp, flags); 891 } 892 893 bnxt_qplib_free_qp_res(&rdev->qplib_res, &qp->qplib_qp); 894 895 if (ib_qp->qp_type == IB_QPT_GSI && rdev->gsi_ctx.gsi_sqp) { 896 rc = bnxt_re_destroy_gsi_sqp(qp); 897 if (rc) 898 return rc; 899 } 900 901 mutex_lock(&rdev->qp_lock); 902 list_del(&qp->list); 903 mutex_unlock(&rdev->qp_lock); 904 atomic_dec(&rdev->qp_count); 905 906 ib_umem_release(qp->rumem); 907 ib_umem_release(qp->sumem); 908 909 /* Flush all the entries of notification queue associated with 910 * given qp. 911 */ 912 scq_nq = qplib_qp->scq->nq; 913 rcq_nq = qplib_qp->rcq->nq; 914 bnxt_re_synchronize_nq(scq_nq); 915 if (scq_nq != rcq_nq) 916 bnxt_re_synchronize_nq(rcq_nq); 917 918 return 0; 919 } 920 921 static u8 __from_ib_qp_type(enum ib_qp_type type) 922 { 923 switch (type) { 924 case IB_QPT_GSI: 925 return CMDQ_CREATE_QP1_TYPE_GSI; 926 case IB_QPT_RC: 927 return CMDQ_CREATE_QP_TYPE_RC; 928 case IB_QPT_UD: 929 return CMDQ_CREATE_QP_TYPE_UD; 930 default: 931 return IB_QPT_MAX; 932 } 933 } 934 935 static u16 bnxt_re_setup_rwqe_size(struct bnxt_qplib_qp *qplqp, 936 int rsge, int max) 937 { 938 if (qplqp->wqe_mode == BNXT_QPLIB_WQE_MODE_STATIC) 939 rsge = max; 940 return bnxt_re_get_rwqe_size(rsge); 941 } 942 943 static u16 bnxt_re_get_wqe_size(int ilsize, int nsge) 944 { 945 u16 wqe_size, calc_ils; 946 947 wqe_size = bnxt_re_get_swqe_size(nsge); 948 if (ilsize) { 949 calc_ils = sizeof(struct sq_send_hdr) + ilsize; 950 wqe_size = max_t(u16, calc_ils, wqe_size); 951 wqe_size = ALIGN(wqe_size, sizeof(struct sq_send_hdr)); 952 } 953 return wqe_size; 954 } 955 956 static int bnxt_re_setup_swqe_size(struct bnxt_re_qp *qp, 957 struct ib_qp_init_attr *init_attr) 958 { 959 struct bnxt_qplib_dev_attr *dev_attr; 960 struct bnxt_qplib_qp *qplqp; 961 struct bnxt_re_dev *rdev; 962 struct bnxt_qplib_q *sq; 963 int align, ilsize; 964 965 rdev = qp->rdev; 966 qplqp = &qp->qplib_qp; 967 sq = &qplqp->sq; 968 dev_attr = &rdev->dev_attr; 969 970 align = sizeof(struct sq_send_hdr); 971 ilsize = ALIGN(init_attr->cap.max_inline_data, align); 972 973 sq->wqe_size = bnxt_re_get_wqe_size(ilsize, sq->max_sge); 974 if (sq->wqe_size > bnxt_re_get_swqe_size(dev_attr->max_qp_sges)) 975 return -EINVAL; 976 /* For gen p4 and gen p5 backward compatibility mode 977 * wqe size is fixed to 128 bytes 978 */ 979 if (sq->wqe_size < bnxt_re_get_swqe_size(dev_attr->max_qp_sges) && 980 qplqp->wqe_mode == BNXT_QPLIB_WQE_MODE_STATIC) 981 sq->wqe_size = bnxt_re_get_swqe_size(dev_attr->max_qp_sges); 982 983 if (init_attr->cap.max_inline_data) { 984 qplqp->max_inline_data = sq->wqe_size - 985 sizeof(struct sq_send_hdr); 986 init_attr->cap.max_inline_data = qplqp->max_inline_data; 987 if (qplqp->wqe_mode == BNXT_QPLIB_WQE_MODE_STATIC) 988 sq->max_sge = qplqp->max_inline_data / 989 sizeof(struct sq_sge); 990 } 991 992 return 0; 993 } 994 995 static int bnxt_re_init_user_qp(struct bnxt_re_dev *rdev, struct bnxt_re_pd *pd, 996 struct bnxt_re_qp *qp, struct ib_udata *udata) 997 { 998 struct bnxt_qplib_qp *qplib_qp; 999 struct bnxt_re_ucontext *cntx; 1000 struct bnxt_re_qp_req ureq; 1001 int bytes = 0, psn_sz; 1002 struct ib_umem *umem; 1003 int psn_nume; 1004 1005 qplib_qp = &qp->qplib_qp; 1006 cntx = rdma_udata_to_drv_context(udata, struct bnxt_re_ucontext, 1007 ib_uctx); 1008 if (ib_copy_from_udata(&ureq, udata, sizeof(ureq))) 1009 return -EFAULT; 1010 1011 bytes = (qplib_qp->sq.max_wqe * qplib_qp->sq.wqe_size); 1012 /* Consider mapping PSN search memory only for RC QPs. */ 1013 if (qplib_qp->type == CMDQ_CREATE_QP_TYPE_RC) { 1014 psn_sz = bnxt_qplib_is_chip_gen_p5(rdev->chip_ctx) ? 1015 sizeof(struct sq_psn_search_ext) : 1016 sizeof(struct sq_psn_search); 1017 psn_nume = (qplib_qp->wqe_mode == BNXT_QPLIB_WQE_MODE_STATIC) ? 1018 qplib_qp->sq.max_wqe : 1019 ((qplib_qp->sq.max_wqe * qplib_qp->sq.wqe_size) / 1020 sizeof(struct bnxt_qplib_sge)); 1021 bytes += (psn_nume * psn_sz); 1022 } 1023 1024 bytes = PAGE_ALIGN(bytes); 1025 umem = ib_umem_get(&rdev->ibdev, ureq.qpsva, bytes, 1026 IB_ACCESS_LOCAL_WRITE); 1027 if (IS_ERR(umem)) 1028 return PTR_ERR(umem); 1029 1030 qp->sumem = umem; 1031 qplib_qp->sq.sg_info.umem = umem; 1032 qplib_qp->sq.sg_info.pgsize = PAGE_SIZE; 1033 qplib_qp->sq.sg_info.pgshft = PAGE_SHIFT; 1034 qplib_qp->qp_handle = ureq.qp_handle; 1035 1036 if (!qp->qplib_qp.srq) { 1037 bytes = (qplib_qp->rq.max_wqe * qplib_qp->rq.wqe_size); 1038 bytes = PAGE_ALIGN(bytes); 1039 umem = ib_umem_get(&rdev->ibdev, ureq.qprva, bytes, 1040 IB_ACCESS_LOCAL_WRITE); 1041 if (IS_ERR(umem)) 1042 goto rqfail; 1043 qp->rumem = umem; 1044 qplib_qp->rq.sg_info.umem = umem; 1045 qplib_qp->rq.sg_info.pgsize = PAGE_SIZE; 1046 qplib_qp->rq.sg_info.pgshft = PAGE_SHIFT; 1047 } 1048 1049 qplib_qp->dpi = &cntx->dpi; 1050 return 0; 1051 rqfail: 1052 ib_umem_release(qp->sumem); 1053 qp->sumem = NULL; 1054 memset(&qplib_qp->sq.sg_info, 0, sizeof(qplib_qp->sq.sg_info)); 1055 1056 return PTR_ERR(umem); 1057 } 1058 1059 static struct bnxt_re_ah *bnxt_re_create_shadow_qp_ah 1060 (struct bnxt_re_pd *pd, 1061 struct bnxt_qplib_res *qp1_res, 1062 struct bnxt_qplib_qp *qp1_qp) 1063 { 1064 struct bnxt_re_dev *rdev = pd->rdev; 1065 struct bnxt_re_ah *ah; 1066 union ib_gid sgid; 1067 int rc; 1068 1069 ah = kzalloc(sizeof(*ah), GFP_KERNEL); 1070 if (!ah) 1071 return NULL; 1072 1073 ah->rdev = rdev; 1074 ah->qplib_ah.pd = &pd->qplib_pd; 1075 1076 rc = bnxt_re_query_gid(&rdev->ibdev, 1, 0, &sgid); 1077 if (rc) 1078 goto fail; 1079 1080 /* supply the dgid data same as sgid */ 1081 memcpy(ah->qplib_ah.dgid.data, &sgid.raw, 1082 sizeof(union ib_gid)); 1083 ah->qplib_ah.sgid_index = 0; 1084 1085 ah->qplib_ah.traffic_class = 0; 1086 ah->qplib_ah.flow_label = 0; 1087 ah->qplib_ah.hop_limit = 1; 1088 ah->qplib_ah.sl = 0; 1089 /* Have DMAC same as SMAC */ 1090 ether_addr_copy(ah->qplib_ah.dmac, rdev->netdev->dev_addr); 1091 1092 rc = bnxt_qplib_create_ah(&rdev->qplib_res, &ah->qplib_ah, false); 1093 if (rc) { 1094 ibdev_err(&rdev->ibdev, 1095 "Failed to allocate HW AH for Shadow QP"); 1096 goto fail; 1097 } 1098 atomic_inc(&rdev->ah_count); 1099 1100 return ah; 1101 1102 fail: 1103 kfree(ah); 1104 return NULL; 1105 } 1106 1107 static struct bnxt_re_qp *bnxt_re_create_shadow_qp 1108 (struct bnxt_re_pd *pd, 1109 struct bnxt_qplib_res *qp1_res, 1110 struct bnxt_qplib_qp *qp1_qp) 1111 { 1112 struct bnxt_re_dev *rdev = pd->rdev; 1113 struct bnxt_re_qp *qp; 1114 int rc; 1115 1116 qp = kzalloc(sizeof(*qp), GFP_KERNEL); 1117 if (!qp) 1118 return NULL; 1119 1120 qp->rdev = rdev; 1121 1122 /* Initialize the shadow QP structure from the QP1 values */ 1123 ether_addr_copy(qp->qplib_qp.smac, rdev->netdev->dev_addr); 1124 1125 qp->qplib_qp.pd = &pd->qplib_pd; 1126 qp->qplib_qp.qp_handle = (u64)(unsigned long)(&qp->qplib_qp); 1127 qp->qplib_qp.type = IB_QPT_UD; 1128 1129 qp->qplib_qp.max_inline_data = 0; 1130 qp->qplib_qp.sig_type = true; 1131 1132 /* Shadow QP SQ depth should be same as QP1 RQ depth */ 1133 qp->qplib_qp.sq.wqe_size = bnxt_re_get_wqe_size(0, 6); 1134 qp->qplib_qp.sq.max_wqe = qp1_qp->rq.max_wqe; 1135 qp->qplib_qp.sq.max_sge = 2; 1136 /* Q full delta can be 1 since it is internal QP */ 1137 qp->qplib_qp.sq.q_full_delta = 1; 1138 qp->qplib_qp.sq.sg_info.pgsize = PAGE_SIZE; 1139 qp->qplib_qp.sq.sg_info.pgshft = PAGE_SHIFT; 1140 1141 qp->qplib_qp.scq = qp1_qp->scq; 1142 qp->qplib_qp.rcq = qp1_qp->rcq; 1143 1144 qp->qplib_qp.rq.wqe_size = bnxt_re_get_rwqe_size(6); 1145 qp->qplib_qp.rq.max_wqe = qp1_qp->rq.max_wqe; 1146 qp->qplib_qp.rq.max_sge = qp1_qp->rq.max_sge; 1147 /* Q full delta can be 1 since it is internal QP */ 1148 qp->qplib_qp.rq.q_full_delta = 1; 1149 qp->qplib_qp.rq.sg_info.pgsize = PAGE_SIZE; 1150 qp->qplib_qp.rq.sg_info.pgshft = PAGE_SHIFT; 1151 1152 qp->qplib_qp.mtu = qp1_qp->mtu; 1153 1154 qp->qplib_qp.sq_hdr_buf_size = 0; 1155 qp->qplib_qp.rq_hdr_buf_size = BNXT_QPLIB_MAX_GRH_HDR_SIZE_IPV6; 1156 qp->qplib_qp.dpi = &rdev->dpi_privileged; 1157 1158 rc = bnxt_qplib_create_qp(qp1_res, &qp->qplib_qp); 1159 if (rc) 1160 goto fail; 1161 1162 spin_lock_init(&qp->sq_lock); 1163 INIT_LIST_HEAD(&qp->list); 1164 mutex_lock(&rdev->qp_lock); 1165 list_add_tail(&qp->list, &rdev->qp_list); 1166 atomic_inc(&rdev->qp_count); 1167 mutex_unlock(&rdev->qp_lock); 1168 return qp; 1169 fail: 1170 kfree(qp); 1171 return NULL; 1172 } 1173 1174 static int bnxt_re_init_rq_attr(struct bnxt_re_qp *qp, 1175 struct ib_qp_init_attr *init_attr) 1176 { 1177 struct bnxt_qplib_dev_attr *dev_attr; 1178 struct bnxt_qplib_qp *qplqp; 1179 struct bnxt_re_dev *rdev; 1180 struct bnxt_qplib_q *rq; 1181 int entries; 1182 1183 rdev = qp->rdev; 1184 qplqp = &qp->qplib_qp; 1185 rq = &qplqp->rq; 1186 dev_attr = &rdev->dev_attr; 1187 1188 if (init_attr->srq) { 1189 struct bnxt_re_srq *srq; 1190 1191 srq = container_of(init_attr->srq, struct bnxt_re_srq, ib_srq); 1192 qplqp->srq = &srq->qplib_srq; 1193 rq->max_wqe = 0; 1194 } else { 1195 rq->max_sge = init_attr->cap.max_recv_sge; 1196 if (rq->max_sge > dev_attr->max_qp_sges) 1197 rq->max_sge = dev_attr->max_qp_sges; 1198 init_attr->cap.max_recv_sge = rq->max_sge; 1199 rq->wqe_size = bnxt_re_setup_rwqe_size(qplqp, rq->max_sge, 1200 dev_attr->max_qp_sges); 1201 /* Allocate 1 more than what's provided so posting max doesn't 1202 * mean empty. 1203 */ 1204 entries = roundup_pow_of_two(init_attr->cap.max_recv_wr + 1); 1205 rq->max_wqe = min_t(u32, entries, dev_attr->max_qp_wqes + 1); 1206 rq->q_full_delta = 0; 1207 rq->sg_info.pgsize = PAGE_SIZE; 1208 rq->sg_info.pgshft = PAGE_SHIFT; 1209 } 1210 1211 return 0; 1212 } 1213 1214 static void bnxt_re_adjust_gsi_rq_attr(struct bnxt_re_qp *qp) 1215 { 1216 struct bnxt_qplib_dev_attr *dev_attr; 1217 struct bnxt_qplib_qp *qplqp; 1218 struct bnxt_re_dev *rdev; 1219 1220 rdev = qp->rdev; 1221 qplqp = &qp->qplib_qp; 1222 dev_attr = &rdev->dev_attr; 1223 1224 if (!bnxt_qplib_is_chip_gen_p5(rdev->chip_ctx)) { 1225 qplqp->rq.max_sge = dev_attr->max_qp_sges; 1226 if (qplqp->rq.max_sge > dev_attr->max_qp_sges) 1227 qplqp->rq.max_sge = dev_attr->max_qp_sges; 1228 qplqp->rq.max_sge = 6; 1229 } 1230 } 1231 1232 static int bnxt_re_init_sq_attr(struct bnxt_re_qp *qp, 1233 struct ib_qp_init_attr *init_attr, 1234 struct ib_udata *udata) 1235 { 1236 struct bnxt_qplib_dev_attr *dev_attr; 1237 struct bnxt_qplib_qp *qplqp; 1238 struct bnxt_re_dev *rdev; 1239 struct bnxt_qplib_q *sq; 1240 int entries; 1241 int diff; 1242 int rc; 1243 1244 rdev = qp->rdev; 1245 qplqp = &qp->qplib_qp; 1246 sq = &qplqp->sq; 1247 dev_attr = &rdev->dev_attr; 1248 1249 sq->max_sge = init_attr->cap.max_send_sge; 1250 if (sq->max_sge > dev_attr->max_qp_sges) { 1251 sq->max_sge = dev_attr->max_qp_sges; 1252 init_attr->cap.max_send_sge = sq->max_sge; 1253 } 1254 1255 rc = bnxt_re_setup_swqe_size(qp, init_attr); 1256 if (rc) 1257 return rc; 1258 1259 entries = init_attr->cap.max_send_wr; 1260 /* Allocate 128 + 1 more than what's provided */ 1261 diff = (qplqp->wqe_mode == BNXT_QPLIB_WQE_MODE_VARIABLE) ? 1262 0 : BNXT_QPLIB_RESERVED_QP_WRS; 1263 entries = roundup_pow_of_two(entries + diff + 1); 1264 sq->max_wqe = min_t(u32, entries, dev_attr->max_qp_wqes + diff + 1); 1265 sq->q_full_delta = diff + 1; 1266 /* 1267 * Reserving one slot for Phantom WQE. Application can 1268 * post one extra entry in this case. But allowing this to avoid 1269 * unexpected Queue full condition 1270 */ 1271 qplqp->sq.q_full_delta -= 1; 1272 qplqp->sq.sg_info.pgsize = PAGE_SIZE; 1273 qplqp->sq.sg_info.pgshft = PAGE_SHIFT; 1274 1275 return 0; 1276 } 1277 1278 static void bnxt_re_adjust_gsi_sq_attr(struct bnxt_re_qp *qp, 1279 struct ib_qp_init_attr *init_attr) 1280 { 1281 struct bnxt_qplib_dev_attr *dev_attr; 1282 struct bnxt_qplib_qp *qplqp; 1283 struct bnxt_re_dev *rdev; 1284 int entries; 1285 1286 rdev = qp->rdev; 1287 qplqp = &qp->qplib_qp; 1288 dev_attr = &rdev->dev_attr; 1289 1290 if (!bnxt_qplib_is_chip_gen_p5(rdev->chip_ctx)) { 1291 entries = roundup_pow_of_two(init_attr->cap.max_send_wr + 1); 1292 qplqp->sq.max_wqe = min_t(u32, entries, 1293 dev_attr->max_qp_wqes + 1); 1294 qplqp->sq.q_full_delta = qplqp->sq.max_wqe - 1295 init_attr->cap.max_send_wr; 1296 qplqp->sq.max_sge++; /* Need one extra sge to put UD header */ 1297 if (qplqp->sq.max_sge > dev_attr->max_qp_sges) 1298 qplqp->sq.max_sge = dev_attr->max_qp_sges; 1299 } 1300 } 1301 1302 static int bnxt_re_init_qp_type(struct bnxt_re_dev *rdev, 1303 struct ib_qp_init_attr *init_attr) 1304 { 1305 struct bnxt_qplib_chip_ctx *chip_ctx; 1306 int qptype; 1307 1308 chip_ctx = rdev->chip_ctx; 1309 1310 qptype = __from_ib_qp_type(init_attr->qp_type); 1311 if (qptype == IB_QPT_MAX) { 1312 ibdev_err(&rdev->ibdev, "QP type 0x%x not supported", qptype); 1313 qptype = -EOPNOTSUPP; 1314 goto out; 1315 } 1316 1317 if (bnxt_qplib_is_chip_gen_p5(chip_ctx) && 1318 init_attr->qp_type == IB_QPT_GSI) 1319 qptype = CMDQ_CREATE_QP_TYPE_GSI; 1320 out: 1321 return qptype; 1322 } 1323 1324 static int bnxt_re_init_qp_attr(struct bnxt_re_qp *qp, struct bnxt_re_pd *pd, 1325 struct ib_qp_init_attr *init_attr, 1326 struct ib_udata *udata) 1327 { 1328 struct bnxt_qplib_dev_attr *dev_attr; 1329 struct bnxt_qplib_qp *qplqp; 1330 struct bnxt_re_dev *rdev; 1331 struct bnxt_re_cq *cq; 1332 int rc = 0, qptype; 1333 1334 rdev = qp->rdev; 1335 qplqp = &qp->qplib_qp; 1336 dev_attr = &rdev->dev_attr; 1337 1338 /* Setup misc params */ 1339 ether_addr_copy(qplqp->smac, rdev->netdev->dev_addr); 1340 qplqp->pd = &pd->qplib_pd; 1341 qplqp->qp_handle = (u64)qplqp; 1342 qplqp->max_inline_data = init_attr->cap.max_inline_data; 1343 qplqp->sig_type = ((init_attr->sq_sig_type == IB_SIGNAL_ALL_WR) ? 1344 true : false); 1345 qptype = bnxt_re_init_qp_type(rdev, init_attr); 1346 if (qptype < 0) { 1347 rc = qptype; 1348 goto out; 1349 } 1350 qplqp->type = (u8)qptype; 1351 qplqp->wqe_mode = rdev->chip_ctx->modes.wqe_mode; 1352 1353 if (init_attr->qp_type == IB_QPT_RC) { 1354 qplqp->max_rd_atomic = dev_attr->max_qp_rd_atom; 1355 qplqp->max_dest_rd_atomic = dev_attr->max_qp_init_rd_atom; 1356 } 1357 qplqp->mtu = ib_mtu_enum_to_int(iboe_get_mtu(rdev->netdev->mtu)); 1358 qplqp->dpi = &rdev->dpi_privileged; /* Doorbell page */ 1359 if (init_attr->create_flags) { 1360 ibdev_dbg(&rdev->ibdev, 1361 "QP create flags 0x%x not supported", 1362 init_attr->create_flags); 1363 return -EOPNOTSUPP; 1364 } 1365 1366 /* Setup CQs */ 1367 if (init_attr->send_cq) { 1368 cq = container_of(init_attr->send_cq, struct bnxt_re_cq, ib_cq); 1369 qplqp->scq = &cq->qplib_cq; 1370 qp->scq = cq; 1371 } 1372 1373 if (init_attr->recv_cq) { 1374 cq = container_of(init_attr->recv_cq, struct bnxt_re_cq, ib_cq); 1375 qplqp->rcq = &cq->qplib_cq; 1376 qp->rcq = cq; 1377 } 1378 1379 /* Setup RQ/SRQ */ 1380 rc = bnxt_re_init_rq_attr(qp, init_attr); 1381 if (rc) 1382 goto out; 1383 if (init_attr->qp_type == IB_QPT_GSI) 1384 bnxt_re_adjust_gsi_rq_attr(qp); 1385 1386 /* Setup SQ */ 1387 rc = bnxt_re_init_sq_attr(qp, init_attr, udata); 1388 if (rc) 1389 goto out; 1390 if (init_attr->qp_type == IB_QPT_GSI) 1391 bnxt_re_adjust_gsi_sq_attr(qp, init_attr); 1392 1393 if (udata) /* This will update DPI and qp_handle */ 1394 rc = bnxt_re_init_user_qp(rdev, pd, qp, udata); 1395 out: 1396 return rc; 1397 } 1398 1399 static int bnxt_re_create_shadow_gsi(struct bnxt_re_qp *qp, 1400 struct bnxt_re_pd *pd) 1401 { 1402 struct bnxt_re_sqp_entries *sqp_tbl; 1403 struct bnxt_re_dev *rdev; 1404 struct bnxt_re_qp *sqp; 1405 struct bnxt_re_ah *sah; 1406 int rc = 0; 1407 1408 rdev = qp->rdev; 1409 /* Create a shadow QP to handle the QP1 traffic */ 1410 sqp_tbl = kcalloc(BNXT_RE_MAX_GSI_SQP_ENTRIES, sizeof(*sqp_tbl), 1411 GFP_KERNEL); 1412 if (!sqp_tbl) 1413 return -ENOMEM; 1414 rdev->gsi_ctx.sqp_tbl = sqp_tbl; 1415 1416 sqp = bnxt_re_create_shadow_qp(pd, &rdev->qplib_res, &qp->qplib_qp); 1417 if (!sqp) { 1418 rc = -ENODEV; 1419 ibdev_err(&rdev->ibdev, "Failed to create Shadow QP for QP1"); 1420 goto out; 1421 } 1422 rdev->gsi_ctx.gsi_sqp = sqp; 1423 1424 sqp->rcq = qp->rcq; 1425 sqp->scq = qp->scq; 1426 sah = bnxt_re_create_shadow_qp_ah(pd, &rdev->qplib_res, 1427 &qp->qplib_qp); 1428 if (!sah) { 1429 bnxt_qplib_destroy_qp(&rdev->qplib_res, 1430 &sqp->qplib_qp); 1431 rc = -ENODEV; 1432 ibdev_err(&rdev->ibdev, 1433 "Failed to create AH entry for ShadowQP"); 1434 goto out; 1435 } 1436 rdev->gsi_ctx.gsi_sah = sah; 1437 1438 return 0; 1439 out: 1440 kfree(sqp_tbl); 1441 return rc; 1442 } 1443 1444 static int bnxt_re_create_gsi_qp(struct bnxt_re_qp *qp, struct bnxt_re_pd *pd, 1445 struct ib_qp_init_attr *init_attr) 1446 { 1447 struct bnxt_re_dev *rdev; 1448 struct bnxt_qplib_qp *qplqp; 1449 int rc = 0; 1450 1451 rdev = qp->rdev; 1452 qplqp = &qp->qplib_qp; 1453 1454 qplqp->rq_hdr_buf_size = BNXT_QPLIB_MAX_QP1_RQ_HDR_SIZE_V2; 1455 qplqp->sq_hdr_buf_size = BNXT_QPLIB_MAX_QP1_SQ_HDR_SIZE_V2; 1456 1457 rc = bnxt_qplib_create_qp1(&rdev->qplib_res, qplqp); 1458 if (rc) { 1459 ibdev_err(&rdev->ibdev, "create HW QP1 failed!"); 1460 goto out; 1461 } 1462 1463 rc = bnxt_re_create_shadow_gsi(qp, pd); 1464 out: 1465 return rc; 1466 } 1467 1468 static bool bnxt_re_test_qp_limits(struct bnxt_re_dev *rdev, 1469 struct ib_qp_init_attr *init_attr, 1470 struct bnxt_qplib_dev_attr *dev_attr) 1471 { 1472 bool rc = true; 1473 1474 if (init_attr->cap.max_send_wr > dev_attr->max_qp_wqes || 1475 init_attr->cap.max_recv_wr > dev_attr->max_qp_wqes || 1476 init_attr->cap.max_send_sge > dev_attr->max_qp_sges || 1477 init_attr->cap.max_recv_sge > dev_attr->max_qp_sges || 1478 init_attr->cap.max_inline_data > dev_attr->max_inline_data) { 1479 ibdev_err(&rdev->ibdev, 1480 "Create QP failed - max exceeded! 0x%x/0x%x 0x%x/0x%x 0x%x/0x%x 0x%x/0x%x 0x%x/0x%x", 1481 init_attr->cap.max_send_wr, dev_attr->max_qp_wqes, 1482 init_attr->cap.max_recv_wr, dev_attr->max_qp_wqes, 1483 init_attr->cap.max_send_sge, dev_attr->max_qp_sges, 1484 init_attr->cap.max_recv_sge, dev_attr->max_qp_sges, 1485 init_attr->cap.max_inline_data, 1486 dev_attr->max_inline_data); 1487 rc = false; 1488 } 1489 return rc; 1490 } 1491 1492 int bnxt_re_create_qp(struct ib_qp *ib_qp, struct ib_qp_init_attr *qp_init_attr, 1493 struct ib_udata *udata) 1494 { 1495 struct ib_pd *ib_pd = ib_qp->pd; 1496 struct bnxt_re_pd *pd = container_of(ib_pd, struct bnxt_re_pd, ib_pd); 1497 struct bnxt_re_dev *rdev = pd->rdev; 1498 struct bnxt_qplib_dev_attr *dev_attr = &rdev->dev_attr; 1499 struct bnxt_re_qp *qp = container_of(ib_qp, struct bnxt_re_qp, ib_qp); 1500 int rc; 1501 1502 rc = bnxt_re_test_qp_limits(rdev, qp_init_attr, dev_attr); 1503 if (!rc) { 1504 rc = -EINVAL; 1505 goto fail; 1506 } 1507 1508 qp->rdev = rdev; 1509 rc = bnxt_re_init_qp_attr(qp, pd, qp_init_attr, udata); 1510 if (rc) 1511 goto fail; 1512 1513 if (qp_init_attr->qp_type == IB_QPT_GSI && 1514 !(bnxt_qplib_is_chip_gen_p5(rdev->chip_ctx))) { 1515 rc = bnxt_re_create_gsi_qp(qp, pd, qp_init_attr); 1516 if (rc == -ENODEV) 1517 goto qp_destroy; 1518 if (rc) 1519 goto fail; 1520 } else { 1521 rc = bnxt_qplib_create_qp(&rdev->qplib_res, &qp->qplib_qp); 1522 if (rc) { 1523 ibdev_err(&rdev->ibdev, "Failed to create HW QP"); 1524 goto free_umem; 1525 } 1526 if (udata) { 1527 struct bnxt_re_qp_resp resp; 1528 1529 resp.qpid = qp->qplib_qp.id; 1530 resp.rsvd = 0; 1531 rc = ib_copy_to_udata(udata, &resp, sizeof(resp)); 1532 if (rc) { 1533 ibdev_err(&rdev->ibdev, "Failed to copy QP udata"); 1534 goto qp_destroy; 1535 } 1536 } 1537 } 1538 1539 qp->ib_qp.qp_num = qp->qplib_qp.id; 1540 if (qp_init_attr->qp_type == IB_QPT_GSI) 1541 rdev->gsi_ctx.gsi_qp = qp; 1542 spin_lock_init(&qp->sq_lock); 1543 spin_lock_init(&qp->rq_lock); 1544 INIT_LIST_HEAD(&qp->list); 1545 mutex_lock(&rdev->qp_lock); 1546 list_add_tail(&qp->list, &rdev->qp_list); 1547 mutex_unlock(&rdev->qp_lock); 1548 atomic_inc(&rdev->qp_count); 1549 1550 return 0; 1551 qp_destroy: 1552 bnxt_qplib_destroy_qp(&rdev->qplib_res, &qp->qplib_qp); 1553 free_umem: 1554 ib_umem_release(qp->rumem); 1555 ib_umem_release(qp->sumem); 1556 fail: 1557 return rc; 1558 } 1559 1560 static u8 __from_ib_qp_state(enum ib_qp_state state) 1561 { 1562 switch (state) { 1563 case IB_QPS_RESET: 1564 return CMDQ_MODIFY_QP_NEW_STATE_RESET; 1565 case IB_QPS_INIT: 1566 return CMDQ_MODIFY_QP_NEW_STATE_INIT; 1567 case IB_QPS_RTR: 1568 return CMDQ_MODIFY_QP_NEW_STATE_RTR; 1569 case IB_QPS_RTS: 1570 return CMDQ_MODIFY_QP_NEW_STATE_RTS; 1571 case IB_QPS_SQD: 1572 return CMDQ_MODIFY_QP_NEW_STATE_SQD; 1573 case IB_QPS_SQE: 1574 return CMDQ_MODIFY_QP_NEW_STATE_SQE; 1575 case IB_QPS_ERR: 1576 default: 1577 return CMDQ_MODIFY_QP_NEW_STATE_ERR; 1578 } 1579 } 1580 1581 static enum ib_qp_state __to_ib_qp_state(u8 state) 1582 { 1583 switch (state) { 1584 case CMDQ_MODIFY_QP_NEW_STATE_RESET: 1585 return IB_QPS_RESET; 1586 case CMDQ_MODIFY_QP_NEW_STATE_INIT: 1587 return IB_QPS_INIT; 1588 case CMDQ_MODIFY_QP_NEW_STATE_RTR: 1589 return IB_QPS_RTR; 1590 case CMDQ_MODIFY_QP_NEW_STATE_RTS: 1591 return IB_QPS_RTS; 1592 case CMDQ_MODIFY_QP_NEW_STATE_SQD: 1593 return IB_QPS_SQD; 1594 case CMDQ_MODIFY_QP_NEW_STATE_SQE: 1595 return IB_QPS_SQE; 1596 case CMDQ_MODIFY_QP_NEW_STATE_ERR: 1597 default: 1598 return IB_QPS_ERR; 1599 } 1600 } 1601 1602 static u32 __from_ib_mtu(enum ib_mtu mtu) 1603 { 1604 switch (mtu) { 1605 case IB_MTU_256: 1606 return CMDQ_MODIFY_QP_PATH_MTU_MTU_256; 1607 case IB_MTU_512: 1608 return CMDQ_MODIFY_QP_PATH_MTU_MTU_512; 1609 case IB_MTU_1024: 1610 return CMDQ_MODIFY_QP_PATH_MTU_MTU_1024; 1611 case IB_MTU_2048: 1612 return CMDQ_MODIFY_QP_PATH_MTU_MTU_2048; 1613 case IB_MTU_4096: 1614 return CMDQ_MODIFY_QP_PATH_MTU_MTU_4096; 1615 default: 1616 return CMDQ_MODIFY_QP_PATH_MTU_MTU_2048; 1617 } 1618 } 1619 1620 static enum ib_mtu __to_ib_mtu(u32 mtu) 1621 { 1622 switch (mtu & CREQ_QUERY_QP_RESP_SB_PATH_MTU_MASK) { 1623 case CMDQ_MODIFY_QP_PATH_MTU_MTU_256: 1624 return IB_MTU_256; 1625 case CMDQ_MODIFY_QP_PATH_MTU_MTU_512: 1626 return IB_MTU_512; 1627 case CMDQ_MODIFY_QP_PATH_MTU_MTU_1024: 1628 return IB_MTU_1024; 1629 case CMDQ_MODIFY_QP_PATH_MTU_MTU_2048: 1630 return IB_MTU_2048; 1631 case CMDQ_MODIFY_QP_PATH_MTU_MTU_4096: 1632 return IB_MTU_4096; 1633 default: 1634 return IB_MTU_2048; 1635 } 1636 } 1637 1638 /* Shared Receive Queues */ 1639 int bnxt_re_destroy_srq(struct ib_srq *ib_srq, struct ib_udata *udata) 1640 { 1641 struct bnxt_re_srq *srq = container_of(ib_srq, struct bnxt_re_srq, 1642 ib_srq); 1643 struct bnxt_re_dev *rdev = srq->rdev; 1644 struct bnxt_qplib_srq *qplib_srq = &srq->qplib_srq; 1645 struct bnxt_qplib_nq *nq = NULL; 1646 1647 if (qplib_srq->cq) 1648 nq = qplib_srq->cq->nq; 1649 bnxt_qplib_destroy_srq(&rdev->qplib_res, qplib_srq); 1650 ib_umem_release(srq->umem); 1651 atomic_dec(&rdev->srq_count); 1652 if (nq) 1653 nq->budget--; 1654 return 0; 1655 } 1656 1657 static int bnxt_re_init_user_srq(struct bnxt_re_dev *rdev, 1658 struct bnxt_re_pd *pd, 1659 struct bnxt_re_srq *srq, 1660 struct ib_udata *udata) 1661 { 1662 struct bnxt_re_srq_req ureq; 1663 struct bnxt_qplib_srq *qplib_srq = &srq->qplib_srq; 1664 struct ib_umem *umem; 1665 int bytes = 0; 1666 struct bnxt_re_ucontext *cntx = rdma_udata_to_drv_context( 1667 udata, struct bnxt_re_ucontext, ib_uctx); 1668 1669 if (ib_copy_from_udata(&ureq, udata, sizeof(ureq))) 1670 return -EFAULT; 1671 1672 bytes = (qplib_srq->max_wqe * qplib_srq->wqe_size); 1673 bytes = PAGE_ALIGN(bytes); 1674 umem = ib_umem_get(&rdev->ibdev, ureq.srqva, bytes, 1675 IB_ACCESS_LOCAL_WRITE); 1676 if (IS_ERR(umem)) 1677 return PTR_ERR(umem); 1678 1679 srq->umem = umem; 1680 qplib_srq->sg_info.umem = umem; 1681 qplib_srq->sg_info.pgsize = PAGE_SIZE; 1682 qplib_srq->sg_info.pgshft = PAGE_SHIFT; 1683 qplib_srq->srq_handle = ureq.srq_handle; 1684 qplib_srq->dpi = &cntx->dpi; 1685 1686 return 0; 1687 } 1688 1689 int bnxt_re_create_srq(struct ib_srq *ib_srq, 1690 struct ib_srq_init_attr *srq_init_attr, 1691 struct ib_udata *udata) 1692 { 1693 struct bnxt_qplib_dev_attr *dev_attr; 1694 struct bnxt_qplib_nq *nq = NULL; 1695 struct bnxt_re_dev *rdev; 1696 struct bnxt_re_srq *srq; 1697 struct bnxt_re_pd *pd; 1698 struct ib_pd *ib_pd; 1699 int rc, entries; 1700 1701 ib_pd = ib_srq->pd; 1702 pd = container_of(ib_pd, struct bnxt_re_pd, ib_pd); 1703 rdev = pd->rdev; 1704 dev_attr = &rdev->dev_attr; 1705 srq = container_of(ib_srq, struct bnxt_re_srq, ib_srq); 1706 1707 if (srq_init_attr->attr.max_wr >= dev_attr->max_srq_wqes) { 1708 ibdev_err(&rdev->ibdev, "Create CQ failed - max exceeded"); 1709 rc = -EINVAL; 1710 goto exit; 1711 } 1712 1713 if (srq_init_attr->srq_type != IB_SRQT_BASIC) { 1714 rc = -EOPNOTSUPP; 1715 goto exit; 1716 } 1717 1718 srq->rdev = rdev; 1719 srq->qplib_srq.pd = &pd->qplib_pd; 1720 srq->qplib_srq.dpi = &rdev->dpi_privileged; 1721 /* Allocate 1 more than what's provided so posting max doesn't 1722 * mean empty 1723 */ 1724 entries = roundup_pow_of_two(srq_init_attr->attr.max_wr + 1); 1725 if (entries > dev_attr->max_srq_wqes + 1) 1726 entries = dev_attr->max_srq_wqes + 1; 1727 srq->qplib_srq.max_wqe = entries; 1728 1729 srq->qplib_srq.max_sge = srq_init_attr->attr.max_sge; 1730 /* 128 byte wqe size for SRQ . So use max sges */ 1731 srq->qplib_srq.wqe_size = bnxt_re_get_rwqe_size(dev_attr->max_srq_sges); 1732 srq->qplib_srq.threshold = srq_init_attr->attr.srq_limit; 1733 srq->srq_limit = srq_init_attr->attr.srq_limit; 1734 srq->qplib_srq.eventq_hw_ring_id = rdev->nq[0].ring_id; 1735 nq = &rdev->nq[0]; 1736 1737 if (udata) { 1738 rc = bnxt_re_init_user_srq(rdev, pd, srq, udata); 1739 if (rc) 1740 goto fail; 1741 } 1742 1743 rc = bnxt_qplib_create_srq(&rdev->qplib_res, &srq->qplib_srq); 1744 if (rc) { 1745 ibdev_err(&rdev->ibdev, "Create HW SRQ failed!"); 1746 goto fail; 1747 } 1748 1749 if (udata) { 1750 struct bnxt_re_srq_resp resp; 1751 1752 resp.srqid = srq->qplib_srq.id; 1753 rc = ib_copy_to_udata(udata, &resp, sizeof(resp)); 1754 if (rc) { 1755 ibdev_err(&rdev->ibdev, "SRQ copy to udata failed!"); 1756 bnxt_qplib_destroy_srq(&rdev->qplib_res, 1757 &srq->qplib_srq); 1758 goto fail; 1759 } 1760 } 1761 if (nq) 1762 nq->budget++; 1763 atomic_inc(&rdev->srq_count); 1764 spin_lock_init(&srq->lock); 1765 1766 return 0; 1767 1768 fail: 1769 ib_umem_release(srq->umem); 1770 exit: 1771 return rc; 1772 } 1773 1774 int bnxt_re_modify_srq(struct ib_srq *ib_srq, struct ib_srq_attr *srq_attr, 1775 enum ib_srq_attr_mask srq_attr_mask, 1776 struct ib_udata *udata) 1777 { 1778 struct bnxt_re_srq *srq = container_of(ib_srq, struct bnxt_re_srq, 1779 ib_srq); 1780 struct bnxt_re_dev *rdev = srq->rdev; 1781 int rc; 1782 1783 switch (srq_attr_mask) { 1784 case IB_SRQ_MAX_WR: 1785 /* SRQ resize is not supported */ 1786 break; 1787 case IB_SRQ_LIMIT: 1788 /* Change the SRQ threshold */ 1789 if (srq_attr->srq_limit > srq->qplib_srq.max_wqe) 1790 return -EINVAL; 1791 1792 srq->qplib_srq.threshold = srq_attr->srq_limit; 1793 rc = bnxt_qplib_modify_srq(&rdev->qplib_res, &srq->qplib_srq); 1794 if (rc) { 1795 ibdev_err(&rdev->ibdev, "Modify HW SRQ failed!"); 1796 return rc; 1797 } 1798 /* On success, update the shadow */ 1799 srq->srq_limit = srq_attr->srq_limit; 1800 /* No need to Build and send response back to udata */ 1801 break; 1802 default: 1803 ibdev_err(&rdev->ibdev, 1804 "Unsupported srq_attr_mask 0x%x", srq_attr_mask); 1805 return -EINVAL; 1806 } 1807 return 0; 1808 } 1809 1810 int bnxt_re_query_srq(struct ib_srq *ib_srq, struct ib_srq_attr *srq_attr) 1811 { 1812 struct bnxt_re_srq *srq = container_of(ib_srq, struct bnxt_re_srq, 1813 ib_srq); 1814 struct bnxt_re_srq tsrq; 1815 struct bnxt_re_dev *rdev = srq->rdev; 1816 int rc; 1817 1818 /* Get live SRQ attr */ 1819 tsrq.qplib_srq.id = srq->qplib_srq.id; 1820 rc = bnxt_qplib_query_srq(&rdev->qplib_res, &tsrq.qplib_srq); 1821 if (rc) { 1822 ibdev_err(&rdev->ibdev, "Query HW SRQ failed!"); 1823 return rc; 1824 } 1825 srq_attr->max_wr = srq->qplib_srq.max_wqe; 1826 srq_attr->max_sge = srq->qplib_srq.max_sge; 1827 srq_attr->srq_limit = tsrq.qplib_srq.threshold; 1828 1829 return 0; 1830 } 1831 1832 int bnxt_re_post_srq_recv(struct ib_srq *ib_srq, const struct ib_recv_wr *wr, 1833 const struct ib_recv_wr **bad_wr) 1834 { 1835 struct bnxt_re_srq *srq = container_of(ib_srq, struct bnxt_re_srq, 1836 ib_srq); 1837 struct bnxt_qplib_swqe wqe; 1838 unsigned long flags; 1839 int rc = 0; 1840 1841 spin_lock_irqsave(&srq->lock, flags); 1842 while (wr) { 1843 /* Transcribe each ib_recv_wr to qplib_swqe */ 1844 wqe.num_sge = wr->num_sge; 1845 bnxt_re_build_sgl(wr->sg_list, wqe.sg_list, wr->num_sge); 1846 wqe.wr_id = wr->wr_id; 1847 wqe.type = BNXT_QPLIB_SWQE_TYPE_RECV; 1848 1849 rc = bnxt_qplib_post_srq_recv(&srq->qplib_srq, &wqe); 1850 if (rc) { 1851 *bad_wr = wr; 1852 break; 1853 } 1854 wr = wr->next; 1855 } 1856 spin_unlock_irqrestore(&srq->lock, flags); 1857 1858 return rc; 1859 } 1860 static int bnxt_re_modify_shadow_qp(struct bnxt_re_dev *rdev, 1861 struct bnxt_re_qp *qp1_qp, 1862 int qp_attr_mask) 1863 { 1864 struct bnxt_re_qp *qp = rdev->gsi_ctx.gsi_sqp; 1865 int rc = 0; 1866 1867 if (qp_attr_mask & IB_QP_STATE) { 1868 qp->qplib_qp.modify_flags |= CMDQ_MODIFY_QP_MODIFY_MASK_STATE; 1869 qp->qplib_qp.state = qp1_qp->qplib_qp.state; 1870 } 1871 if (qp_attr_mask & IB_QP_PKEY_INDEX) { 1872 qp->qplib_qp.modify_flags |= CMDQ_MODIFY_QP_MODIFY_MASK_PKEY; 1873 qp->qplib_qp.pkey_index = qp1_qp->qplib_qp.pkey_index; 1874 } 1875 1876 if (qp_attr_mask & IB_QP_QKEY) { 1877 qp->qplib_qp.modify_flags |= CMDQ_MODIFY_QP_MODIFY_MASK_QKEY; 1878 /* Using a Random QKEY */ 1879 qp->qplib_qp.qkey = 0x81818181; 1880 } 1881 if (qp_attr_mask & IB_QP_SQ_PSN) { 1882 qp->qplib_qp.modify_flags |= CMDQ_MODIFY_QP_MODIFY_MASK_SQ_PSN; 1883 qp->qplib_qp.sq.psn = qp1_qp->qplib_qp.sq.psn; 1884 } 1885 1886 rc = bnxt_qplib_modify_qp(&rdev->qplib_res, &qp->qplib_qp); 1887 if (rc) 1888 ibdev_err(&rdev->ibdev, "Failed to modify Shadow QP for QP1"); 1889 return rc; 1890 } 1891 1892 int bnxt_re_modify_qp(struct ib_qp *ib_qp, struct ib_qp_attr *qp_attr, 1893 int qp_attr_mask, struct ib_udata *udata) 1894 { 1895 struct bnxt_re_qp *qp = container_of(ib_qp, struct bnxt_re_qp, ib_qp); 1896 struct bnxt_re_dev *rdev = qp->rdev; 1897 struct bnxt_qplib_dev_attr *dev_attr = &rdev->dev_attr; 1898 enum ib_qp_state curr_qp_state, new_qp_state; 1899 int rc, entries; 1900 unsigned int flags; 1901 u8 nw_type; 1902 1903 if (qp_attr_mask & ~IB_QP_ATTR_STANDARD_BITS) 1904 return -EOPNOTSUPP; 1905 1906 qp->qplib_qp.modify_flags = 0; 1907 if (qp_attr_mask & IB_QP_STATE) { 1908 curr_qp_state = __to_ib_qp_state(qp->qplib_qp.cur_qp_state); 1909 new_qp_state = qp_attr->qp_state; 1910 if (!ib_modify_qp_is_ok(curr_qp_state, new_qp_state, 1911 ib_qp->qp_type, qp_attr_mask)) { 1912 ibdev_err(&rdev->ibdev, 1913 "Invalid attribute mask: %#x specified ", 1914 qp_attr_mask); 1915 ibdev_err(&rdev->ibdev, 1916 "for qpn: %#x type: %#x", 1917 ib_qp->qp_num, ib_qp->qp_type); 1918 ibdev_err(&rdev->ibdev, 1919 "curr_qp_state=0x%x, new_qp_state=0x%x\n", 1920 curr_qp_state, new_qp_state); 1921 return -EINVAL; 1922 } 1923 qp->qplib_qp.modify_flags |= CMDQ_MODIFY_QP_MODIFY_MASK_STATE; 1924 qp->qplib_qp.state = __from_ib_qp_state(qp_attr->qp_state); 1925 1926 if (!qp->sumem && 1927 qp->qplib_qp.state == CMDQ_MODIFY_QP_NEW_STATE_ERR) { 1928 ibdev_dbg(&rdev->ibdev, 1929 "Move QP = %p to flush list\n", qp); 1930 flags = bnxt_re_lock_cqs(qp); 1931 bnxt_qplib_add_flush_qp(&qp->qplib_qp); 1932 bnxt_re_unlock_cqs(qp, flags); 1933 } 1934 if (!qp->sumem && 1935 qp->qplib_qp.state == CMDQ_MODIFY_QP_NEW_STATE_RESET) { 1936 ibdev_dbg(&rdev->ibdev, 1937 "Move QP = %p out of flush list\n", qp); 1938 flags = bnxt_re_lock_cqs(qp); 1939 bnxt_qplib_clean_qp(&qp->qplib_qp); 1940 bnxt_re_unlock_cqs(qp, flags); 1941 } 1942 } 1943 if (qp_attr_mask & IB_QP_EN_SQD_ASYNC_NOTIFY) { 1944 qp->qplib_qp.modify_flags |= 1945 CMDQ_MODIFY_QP_MODIFY_MASK_EN_SQD_ASYNC_NOTIFY; 1946 qp->qplib_qp.en_sqd_async_notify = true; 1947 } 1948 if (qp_attr_mask & IB_QP_ACCESS_FLAGS) { 1949 qp->qplib_qp.modify_flags |= CMDQ_MODIFY_QP_MODIFY_MASK_ACCESS; 1950 qp->qplib_qp.access = 1951 __from_ib_access_flags(qp_attr->qp_access_flags); 1952 /* LOCAL_WRITE access must be set to allow RC receive */ 1953 qp->qplib_qp.access |= BNXT_QPLIB_ACCESS_LOCAL_WRITE; 1954 /* Temp: Set all params on QP as of now */ 1955 qp->qplib_qp.access |= CMDQ_MODIFY_QP_ACCESS_REMOTE_WRITE; 1956 qp->qplib_qp.access |= CMDQ_MODIFY_QP_ACCESS_REMOTE_READ; 1957 } 1958 if (qp_attr_mask & IB_QP_PKEY_INDEX) { 1959 qp->qplib_qp.modify_flags |= CMDQ_MODIFY_QP_MODIFY_MASK_PKEY; 1960 qp->qplib_qp.pkey_index = qp_attr->pkey_index; 1961 } 1962 if (qp_attr_mask & IB_QP_QKEY) { 1963 qp->qplib_qp.modify_flags |= CMDQ_MODIFY_QP_MODIFY_MASK_QKEY; 1964 qp->qplib_qp.qkey = qp_attr->qkey; 1965 } 1966 if (qp_attr_mask & IB_QP_AV) { 1967 const struct ib_global_route *grh = 1968 rdma_ah_read_grh(&qp_attr->ah_attr); 1969 const struct ib_gid_attr *sgid_attr; 1970 struct bnxt_re_gid_ctx *ctx; 1971 1972 qp->qplib_qp.modify_flags |= CMDQ_MODIFY_QP_MODIFY_MASK_DGID | 1973 CMDQ_MODIFY_QP_MODIFY_MASK_FLOW_LABEL | 1974 CMDQ_MODIFY_QP_MODIFY_MASK_SGID_INDEX | 1975 CMDQ_MODIFY_QP_MODIFY_MASK_HOP_LIMIT | 1976 CMDQ_MODIFY_QP_MODIFY_MASK_TRAFFIC_CLASS | 1977 CMDQ_MODIFY_QP_MODIFY_MASK_DEST_MAC | 1978 CMDQ_MODIFY_QP_MODIFY_MASK_VLAN_ID; 1979 memcpy(qp->qplib_qp.ah.dgid.data, grh->dgid.raw, 1980 sizeof(qp->qplib_qp.ah.dgid.data)); 1981 qp->qplib_qp.ah.flow_label = grh->flow_label; 1982 sgid_attr = grh->sgid_attr; 1983 /* Get the HW context of the GID. The reference 1984 * of GID table entry is already taken by the caller. 1985 */ 1986 ctx = rdma_read_gid_hw_context(sgid_attr); 1987 qp->qplib_qp.ah.sgid_index = ctx->idx; 1988 qp->qplib_qp.ah.host_sgid_index = grh->sgid_index; 1989 qp->qplib_qp.ah.hop_limit = grh->hop_limit; 1990 qp->qplib_qp.ah.traffic_class = grh->traffic_class; 1991 qp->qplib_qp.ah.sl = rdma_ah_get_sl(&qp_attr->ah_attr); 1992 ether_addr_copy(qp->qplib_qp.ah.dmac, 1993 qp_attr->ah_attr.roce.dmac); 1994 1995 rc = rdma_read_gid_l2_fields(sgid_attr, NULL, 1996 &qp->qplib_qp.smac[0]); 1997 if (rc) 1998 return rc; 1999 2000 nw_type = rdma_gid_attr_network_type(sgid_attr); 2001 switch (nw_type) { 2002 case RDMA_NETWORK_IPV4: 2003 qp->qplib_qp.nw_type = 2004 CMDQ_MODIFY_QP_NETWORK_TYPE_ROCEV2_IPV4; 2005 break; 2006 case RDMA_NETWORK_IPV6: 2007 qp->qplib_qp.nw_type = 2008 CMDQ_MODIFY_QP_NETWORK_TYPE_ROCEV2_IPV6; 2009 break; 2010 default: 2011 qp->qplib_qp.nw_type = 2012 CMDQ_MODIFY_QP_NETWORK_TYPE_ROCEV1; 2013 break; 2014 } 2015 } 2016 2017 if (qp_attr_mask & IB_QP_PATH_MTU) { 2018 qp->qplib_qp.modify_flags |= 2019 CMDQ_MODIFY_QP_MODIFY_MASK_PATH_MTU; 2020 qp->qplib_qp.path_mtu = __from_ib_mtu(qp_attr->path_mtu); 2021 qp->qplib_qp.mtu = ib_mtu_enum_to_int(qp_attr->path_mtu); 2022 } else if (qp_attr->qp_state == IB_QPS_RTR) { 2023 qp->qplib_qp.modify_flags |= 2024 CMDQ_MODIFY_QP_MODIFY_MASK_PATH_MTU; 2025 qp->qplib_qp.path_mtu = 2026 __from_ib_mtu(iboe_get_mtu(rdev->netdev->mtu)); 2027 qp->qplib_qp.mtu = 2028 ib_mtu_enum_to_int(iboe_get_mtu(rdev->netdev->mtu)); 2029 } 2030 2031 if (qp_attr_mask & IB_QP_TIMEOUT) { 2032 qp->qplib_qp.modify_flags |= CMDQ_MODIFY_QP_MODIFY_MASK_TIMEOUT; 2033 qp->qplib_qp.timeout = qp_attr->timeout; 2034 } 2035 if (qp_attr_mask & IB_QP_RETRY_CNT) { 2036 qp->qplib_qp.modify_flags |= 2037 CMDQ_MODIFY_QP_MODIFY_MASK_RETRY_CNT; 2038 qp->qplib_qp.retry_cnt = qp_attr->retry_cnt; 2039 } 2040 if (qp_attr_mask & IB_QP_RNR_RETRY) { 2041 qp->qplib_qp.modify_flags |= 2042 CMDQ_MODIFY_QP_MODIFY_MASK_RNR_RETRY; 2043 qp->qplib_qp.rnr_retry = qp_attr->rnr_retry; 2044 } 2045 if (qp_attr_mask & IB_QP_MIN_RNR_TIMER) { 2046 qp->qplib_qp.modify_flags |= 2047 CMDQ_MODIFY_QP_MODIFY_MASK_MIN_RNR_TIMER; 2048 qp->qplib_qp.min_rnr_timer = qp_attr->min_rnr_timer; 2049 } 2050 if (qp_attr_mask & IB_QP_RQ_PSN) { 2051 qp->qplib_qp.modify_flags |= CMDQ_MODIFY_QP_MODIFY_MASK_RQ_PSN; 2052 qp->qplib_qp.rq.psn = qp_attr->rq_psn; 2053 } 2054 if (qp_attr_mask & IB_QP_MAX_QP_RD_ATOMIC) { 2055 qp->qplib_qp.modify_flags |= 2056 CMDQ_MODIFY_QP_MODIFY_MASK_MAX_RD_ATOMIC; 2057 /* Cap the max_rd_atomic to device max */ 2058 qp->qplib_qp.max_rd_atomic = min_t(u32, qp_attr->max_rd_atomic, 2059 dev_attr->max_qp_rd_atom); 2060 } 2061 if (qp_attr_mask & IB_QP_SQ_PSN) { 2062 qp->qplib_qp.modify_flags |= CMDQ_MODIFY_QP_MODIFY_MASK_SQ_PSN; 2063 qp->qplib_qp.sq.psn = qp_attr->sq_psn; 2064 } 2065 if (qp_attr_mask & IB_QP_MAX_DEST_RD_ATOMIC) { 2066 if (qp_attr->max_dest_rd_atomic > 2067 dev_attr->max_qp_init_rd_atom) { 2068 ibdev_err(&rdev->ibdev, 2069 "max_dest_rd_atomic requested%d is > dev_max%d", 2070 qp_attr->max_dest_rd_atomic, 2071 dev_attr->max_qp_init_rd_atom); 2072 return -EINVAL; 2073 } 2074 2075 qp->qplib_qp.modify_flags |= 2076 CMDQ_MODIFY_QP_MODIFY_MASK_MAX_DEST_RD_ATOMIC; 2077 qp->qplib_qp.max_dest_rd_atomic = qp_attr->max_dest_rd_atomic; 2078 } 2079 if (qp_attr_mask & IB_QP_CAP) { 2080 qp->qplib_qp.modify_flags |= 2081 CMDQ_MODIFY_QP_MODIFY_MASK_SQ_SIZE | 2082 CMDQ_MODIFY_QP_MODIFY_MASK_RQ_SIZE | 2083 CMDQ_MODIFY_QP_MODIFY_MASK_SQ_SGE | 2084 CMDQ_MODIFY_QP_MODIFY_MASK_RQ_SGE | 2085 CMDQ_MODIFY_QP_MODIFY_MASK_MAX_INLINE_DATA; 2086 if ((qp_attr->cap.max_send_wr >= dev_attr->max_qp_wqes) || 2087 (qp_attr->cap.max_recv_wr >= dev_attr->max_qp_wqes) || 2088 (qp_attr->cap.max_send_sge >= dev_attr->max_qp_sges) || 2089 (qp_attr->cap.max_recv_sge >= dev_attr->max_qp_sges) || 2090 (qp_attr->cap.max_inline_data >= 2091 dev_attr->max_inline_data)) { 2092 ibdev_err(&rdev->ibdev, 2093 "Create QP failed - max exceeded"); 2094 return -EINVAL; 2095 } 2096 entries = roundup_pow_of_two(qp_attr->cap.max_send_wr); 2097 qp->qplib_qp.sq.max_wqe = min_t(u32, entries, 2098 dev_attr->max_qp_wqes + 1); 2099 qp->qplib_qp.sq.q_full_delta = qp->qplib_qp.sq.max_wqe - 2100 qp_attr->cap.max_send_wr; 2101 /* 2102 * Reserving one slot for Phantom WQE. Some application can 2103 * post one extra entry in this case. Allowing this to avoid 2104 * unexpected Queue full condition 2105 */ 2106 qp->qplib_qp.sq.q_full_delta -= 1; 2107 qp->qplib_qp.sq.max_sge = qp_attr->cap.max_send_sge; 2108 if (qp->qplib_qp.rq.max_wqe) { 2109 entries = roundup_pow_of_two(qp_attr->cap.max_recv_wr); 2110 qp->qplib_qp.rq.max_wqe = 2111 min_t(u32, entries, dev_attr->max_qp_wqes + 1); 2112 qp->qplib_qp.rq.q_full_delta = qp->qplib_qp.rq.max_wqe - 2113 qp_attr->cap.max_recv_wr; 2114 qp->qplib_qp.rq.max_sge = qp_attr->cap.max_recv_sge; 2115 } else { 2116 /* SRQ was used prior, just ignore the RQ caps */ 2117 } 2118 } 2119 if (qp_attr_mask & IB_QP_DEST_QPN) { 2120 qp->qplib_qp.modify_flags |= 2121 CMDQ_MODIFY_QP_MODIFY_MASK_DEST_QP_ID; 2122 qp->qplib_qp.dest_qpn = qp_attr->dest_qp_num; 2123 } 2124 rc = bnxt_qplib_modify_qp(&rdev->qplib_res, &qp->qplib_qp); 2125 if (rc) { 2126 ibdev_err(&rdev->ibdev, "Failed to modify HW QP"); 2127 return rc; 2128 } 2129 if (ib_qp->qp_type == IB_QPT_GSI && rdev->gsi_ctx.gsi_sqp) 2130 rc = bnxt_re_modify_shadow_qp(rdev, qp, qp_attr_mask); 2131 return rc; 2132 } 2133 2134 int bnxt_re_query_qp(struct ib_qp *ib_qp, struct ib_qp_attr *qp_attr, 2135 int qp_attr_mask, struct ib_qp_init_attr *qp_init_attr) 2136 { 2137 struct bnxt_re_qp *qp = container_of(ib_qp, struct bnxt_re_qp, ib_qp); 2138 struct bnxt_re_dev *rdev = qp->rdev; 2139 struct bnxt_qplib_qp *qplib_qp; 2140 int rc; 2141 2142 qplib_qp = kzalloc(sizeof(*qplib_qp), GFP_KERNEL); 2143 if (!qplib_qp) 2144 return -ENOMEM; 2145 2146 qplib_qp->id = qp->qplib_qp.id; 2147 qplib_qp->ah.host_sgid_index = qp->qplib_qp.ah.host_sgid_index; 2148 2149 rc = bnxt_qplib_query_qp(&rdev->qplib_res, qplib_qp); 2150 if (rc) { 2151 ibdev_err(&rdev->ibdev, "Failed to query HW QP"); 2152 goto out; 2153 } 2154 qp_attr->qp_state = __to_ib_qp_state(qplib_qp->state); 2155 qp_attr->cur_qp_state = __to_ib_qp_state(qplib_qp->cur_qp_state); 2156 qp_attr->en_sqd_async_notify = qplib_qp->en_sqd_async_notify ? 1 : 0; 2157 qp_attr->qp_access_flags = __to_ib_access_flags(qplib_qp->access); 2158 qp_attr->pkey_index = qplib_qp->pkey_index; 2159 qp_attr->qkey = qplib_qp->qkey; 2160 qp_attr->ah_attr.type = RDMA_AH_ATTR_TYPE_ROCE; 2161 rdma_ah_set_grh(&qp_attr->ah_attr, NULL, qplib_qp->ah.flow_label, 2162 qplib_qp->ah.host_sgid_index, 2163 qplib_qp->ah.hop_limit, 2164 qplib_qp->ah.traffic_class); 2165 rdma_ah_set_dgid_raw(&qp_attr->ah_attr, qplib_qp->ah.dgid.data); 2166 rdma_ah_set_sl(&qp_attr->ah_attr, qplib_qp->ah.sl); 2167 ether_addr_copy(qp_attr->ah_attr.roce.dmac, qplib_qp->ah.dmac); 2168 qp_attr->path_mtu = __to_ib_mtu(qplib_qp->path_mtu); 2169 qp_attr->timeout = qplib_qp->timeout; 2170 qp_attr->retry_cnt = qplib_qp->retry_cnt; 2171 qp_attr->rnr_retry = qplib_qp->rnr_retry; 2172 qp_attr->min_rnr_timer = qplib_qp->min_rnr_timer; 2173 qp_attr->rq_psn = qplib_qp->rq.psn; 2174 qp_attr->max_rd_atomic = qplib_qp->max_rd_atomic; 2175 qp_attr->sq_psn = qplib_qp->sq.psn; 2176 qp_attr->max_dest_rd_atomic = qplib_qp->max_dest_rd_atomic; 2177 qp_init_attr->sq_sig_type = qplib_qp->sig_type ? IB_SIGNAL_ALL_WR : 2178 IB_SIGNAL_REQ_WR; 2179 qp_attr->dest_qp_num = qplib_qp->dest_qpn; 2180 2181 qp_attr->cap.max_send_wr = qp->qplib_qp.sq.max_wqe; 2182 qp_attr->cap.max_send_sge = qp->qplib_qp.sq.max_sge; 2183 qp_attr->cap.max_recv_wr = qp->qplib_qp.rq.max_wqe; 2184 qp_attr->cap.max_recv_sge = qp->qplib_qp.rq.max_sge; 2185 qp_attr->cap.max_inline_data = qp->qplib_qp.max_inline_data; 2186 qp_init_attr->cap = qp_attr->cap; 2187 2188 out: 2189 kfree(qplib_qp); 2190 return rc; 2191 } 2192 2193 /* Routine for sending QP1 packets for RoCE V1 an V2 2194 */ 2195 static int bnxt_re_build_qp1_send_v2(struct bnxt_re_qp *qp, 2196 const struct ib_send_wr *wr, 2197 struct bnxt_qplib_swqe *wqe, 2198 int payload_size) 2199 { 2200 struct bnxt_re_ah *ah = container_of(ud_wr(wr)->ah, struct bnxt_re_ah, 2201 ib_ah); 2202 struct bnxt_qplib_ah *qplib_ah = &ah->qplib_ah; 2203 const struct ib_gid_attr *sgid_attr = ah->ib_ah.sgid_attr; 2204 struct bnxt_qplib_sge sge; 2205 u8 nw_type; 2206 u16 ether_type; 2207 union ib_gid dgid; 2208 bool is_eth = false; 2209 bool is_vlan = false; 2210 bool is_grh = false; 2211 bool is_udp = false; 2212 u8 ip_version = 0; 2213 u16 vlan_id = 0xFFFF; 2214 void *buf; 2215 int i, rc = 0; 2216 2217 memset(&qp->qp1_hdr, 0, sizeof(qp->qp1_hdr)); 2218 2219 rc = rdma_read_gid_l2_fields(sgid_attr, &vlan_id, NULL); 2220 if (rc) 2221 return rc; 2222 2223 /* Get network header type for this GID */ 2224 nw_type = rdma_gid_attr_network_type(sgid_attr); 2225 switch (nw_type) { 2226 case RDMA_NETWORK_IPV4: 2227 nw_type = BNXT_RE_ROCEV2_IPV4_PACKET; 2228 break; 2229 case RDMA_NETWORK_IPV6: 2230 nw_type = BNXT_RE_ROCEV2_IPV6_PACKET; 2231 break; 2232 default: 2233 nw_type = BNXT_RE_ROCE_V1_PACKET; 2234 break; 2235 } 2236 memcpy(&dgid.raw, &qplib_ah->dgid, 16); 2237 is_udp = sgid_attr->gid_type == IB_GID_TYPE_ROCE_UDP_ENCAP; 2238 if (is_udp) { 2239 if (ipv6_addr_v4mapped((struct in6_addr *)&sgid_attr->gid)) { 2240 ip_version = 4; 2241 ether_type = ETH_P_IP; 2242 } else { 2243 ip_version = 6; 2244 ether_type = ETH_P_IPV6; 2245 } 2246 is_grh = false; 2247 } else { 2248 ether_type = ETH_P_IBOE; 2249 is_grh = true; 2250 } 2251 2252 is_eth = true; 2253 is_vlan = (vlan_id && (vlan_id < 0x1000)) ? true : false; 2254 2255 ib_ud_header_init(payload_size, !is_eth, is_eth, is_vlan, is_grh, 2256 ip_version, is_udp, 0, &qp->qp1_hdr); 2257 2258 /* ETH */ 2259 ether_addr_copy(qp->qp1_hdr.eth.dmac_h, ah->qplib_ah.dmac); 2260 ether_addr_copy(qp->qp1_hdr.eth.smac_h, qp->qplib_qp.smac); 2261 2262 /* For vlan, check the sgid for vlan existence */ 2263 2264 if (!is_vlan) { 2265 qp->qp1_hdr.eth.type = cpu_to_be16(ether_type); 2266 } else { 2267 qp->qp1_hdr.vlan.type = cpu_to_be16(ether_type); 2268 qp->qp1_hdr.vlan.tag = cpu_to_be16(vlan_id); 2269 } 2270 2271 if (is_grh || (ip_version == 6)) { 2272 memcpy(qp->qp1_hdr.grh.source_gid.raw, sgid_attr->gid.raw, 2273 sizeof(sgid_attr->gid)); 2274 memcpy(qp->qp1_hdr.grh.destination_gid.raw, qplib_ah->dgid.data, 2275 sizeof(sgid_attr->gid)); 2276 qp->qp1_hdr.grh.hop_limit = qplib_ah->hop_limit; 2277 } 2278 2279 if (ip_version == 4) { 2280 qp->qp1_hdr.ip4.tos = 0; 2281 qp->qp1_hdr.ip4.id = 0; 2282 qp->qp1_hdr.ip4.frag_off = htons(IP_DF); 2283 qp->qp1_hdr.ip4.ttl = qplib_ah->hop_limit; 2284 2285 memcpy(&qp->qp1_hdr.ip4.saddr, sgid_attr->gid.raw + 12, 4); 2286 memcpy(&qp->qp1_hdr.ip4.daddr, qplib_ah->dgid.data + 12, 4); 2287 qp->qp1_hdr.ip4.check = ib_ud_ip4_csum(&qp->qp1_hdr); 2288 } 2289 2290 if (is_udp) { 2291 qp->qp1_hdr.udp.dport = htons(ROCE_V2_UDP_DPORT); 2292 qp->qp1_hdr.udp.sport = htons(0x8CD1); 2293 qp->qp1_hdr.udp.csum = 0; 2294 } 2295 2296 /* BTH */ 2297 if (wr->opcode == IB_WR_SEND_WITH_IMM) { 2298 qp->qp1_hdr.bth.opcode = IB_OPCODE_UD_SEND_ONLY_WITH_IMMEDIATE; 2299 qp->qp1_hdr.immediate_present = 1; 2300 } else { 2301 qp->qp1_hdr.bth.opcode = IB_OPCODE_UD_SEND_ONLY; 2302 } 2303 if (wr->send_flags & IB_SEND_SOLICITED) 2304 qp->qp1_hdr.bth.solicited_event = 1; 2305 /* pad_count */ 2306 qp->qp1_hdr.bth.pad_count = (4 - payload_size) & 3; 2307 2308 /* P_key for QP1 is for all members */ 2309 qp->qp1_hdr.bth.pkey = cpu_to_be16(0xFFFF); 2310 qp->qp1_hdr.bth.destination_qpn = IB_QP1; 2311 qp->qp1_hdr.bth.ack_req = 0; 2312 qp->send_psn++; 2313 qp->send_psn &= BTH_PSN_MASK; 2314 qp->qp1_hdr.bth.psn = cpu_to_be32(qp->send_psn); 2315 /* DETH */ 2316 /* Use the priviledged Q_Key for QP1 */ 2317 qp->qp1_hdr.deth.qkey = cpu_to_be32(IB_QP1_QKEY); 2318 qp->qp1_hdr.deth.source_qpn = IB_QP1; 2319 2320 /* Pack the QP1 to the transmit buffer */ 2321 buf = bnxt_qplib_get_qp1_sq_buf(&qp->qplib_qp, &sge); 2322 if (buf) { 2323 ib_ud_header_pack(&qp->qp1_hdr, buf); 2324 for (i = wqe->num_sge; i; i--) { 2325 wqe->sg_list[i].addr = wqe->sg_list[i - 1].addr; 2326 wqe->sg_list[i].lkey = wqe->sg_list[i - 1].lkey; 2327 wqe->sg_list[i].size = wqe->sg_list[i - 1].size; 2328 } 2329 2330 /* 2331 * Max Header buf size for IPV6 RoCE V2 is 86, 2332 * which is same as the QP1 SQ header buffer. 2333 * Header buf size for IPV4 RoCE V2 can be 66. 2334 * ETH(14) + VLAN(4)+ IP(20) + UDP (8) + BTH(20). 2335 * Subtract 20 bytes from QP1 SQ header buf size 2336 */ 2337 if (is_udp && ip_version == 4) 2338 sge.size -= 20; 2339 /* 2340 * Max Header buf size for RoCE V1 is 78. 2341 * ETH(14) + VLAN(4) + GRH(40) + BTH(20). 2342 * Subtract 8 bytes from QP1 SQ header buf size 2343 */ 2344 if (!is_udp) 2345 sge.size -= 8; 2346 2347 /* Subtract 4 bytes for non vlan packets */ 2348 if (!is_vlan) 2349 sge.size -= 4; 2350 2351 wqe->sg_list[0].addr = sge.addr; 2352 wqe->sg_list[0].lkey = sge.lkey; 2353 wqe->sg_list[0].size = sge.size; 2354 wqe->num_sge++; 2355 2356 } else { 2357 ibdev_err(&qp->rdev->ibdev, "QP1 buffer is empty!"); 2358 rc = -ENOMEM; 2359 } 2360 return rc; 2361 } 2362 2363 /* For the MAD layer, it only provides the recv SGE the size of 2364 * ib_grh + MAD datagram. No Ethernet headers, Ethertype, BTH, DETH, 2365 * nor RoCE iCRC. The Cu+ solution must provide buffer for the entire 2366 * receive packet (334 bytes) with no VLAN and then copy the GRH 2367 * and the MAD datagram out to the provided SGE. 2368 */ 2369 static int bnxt_re_build_qp1_shadow_qp_recv(struct bnxt_re_qp *qp, 2370 const struct ib_recv_wr *wr, 2371 struct bnxt_qplib_swqe *wqe, 2372 int payload_size) 2373 { 2374 struct bnxt_re_sqp_entries *sqp_entry; 2375 struct bnxt_qplib_sge ref, sge; 2376 struct bnxt_re_dev *rdev; 2377 u32 rq_prod_index; 2378 2379 rdev = qp->rdev; 2380 2381 rq_prod_index = bnxt_qplib_get_rq_prod_index(&qp->qplib_qp); 2382 2383 if (!bnxt_qplib_get_qp1_rq_buf(&qp->qplib_qp, &sge)) 2384 return -ENOMEM; 2385 2386 /* Create 1 SGE to receive the entire 2387 * ethernet packet 2388 */ 2389 /* Save the reference from ULP */ 2390 ref.addr = wqe->sg_list[0].addr; 2391 ref.lkey = wqe->sg_list[0].lkey; 2392 ref.size = wqe->sg_list[0].size; 2393 2394 sqp_entry = &rdev->gsi_ctx.sqp_tbl[rq_prod_index]; 2395 2396 /* SGE 1 */ 2397 wqe->sg_list[0].addr = sge.addr; 2398 wqe->sg_list[0].lkey = sge.lkey; 2399 wqe->sg_list[0].size = BNXT_QPLIB_MAX_QP1_RQ_HDR_SIZE_V2; 2400 sge.size -= wqe->sg_list[0].size; 2401 2402 sqp_entry->sge.addr = ref.addr; 2403 sqp_entry->sge.lkey = ref.lkey; 2404 sqp_entry->sge.size = ref.size; 2405 /* Store the wrid for reporting completion */ 2406 sqp_entry->wrid = wqe->wr_id; 2407 /* change the wqe->wrid to table index */ 2408 wqe->wr_id = rq_prod_index; 2409 return 0; 2410 } 2411 2412 static int is_ud_qp(struct bnxt_re_qp *qp) 2413 { 2414 return (qp->qplib_qp.type == CMDQ_CREATE_QP_TYPE_UD || 2415 qp->qplib_qp.type == CMDQ_CREATE_QP_TYPE_GSI); 2416 } 2417 2418 static int bnxt_re_build_send_wqe(struct bnxt_re_qp *qp, 2419 const struct ib_send_wr *wr, 2420 struct bnxt_qplib_swqe *wqe) 2421 { 2422 struct bnxt_re_ah *ah = NULL; 2423 2424 if (is_ud_qp(qp)) { 2425 ah = container_of(ud_wr(wr)->ah, struct bnxt_re_ah, ib_ah); 2426 wqe->send.q_key = ud_wr(wr)->remote_qkey; 2427 wqe->send.dst_qp = ud_wr(wr)->remote_qpn; 2428 wqe->send.avid = ah->qplib_ah.id; 2429 } 2430 switch (wr->opcode) { 2431 case IB_WR_SEND: 2432 wqe->type = BNXT_QPLIB_SWQE_TYPE_SEND; 2433 break; 2434 case IB_WR_SEND_WITH_IMM: 2435 wqe->type = BNXT_QPLIB_SWQE_TYPE_SEND_WITH_IMM; 2436 wqe->send.imm_data = wr->ex.imm_data; 2437 break; 2438 case IB_WR_SEND_WITH_INV: 2439 wqe->type = BNXT_QPLIB_SWQE_TYPE_SEND_WITH_INV; 2440 wqe->send.inv_key = wr->ex.invalidate_rkey; 2441 break; 2442 default: 2443 return -EINVAL; 2444 } 2445 if (wr->send_flags & IB_SEND_SIGNALED) 2446 wqe->flags |= BNXT_QPLIB_SWQE_FLAGS_SIGNAL_COMP; 2447 if (wr->send_flags & IB_SEND_FENCE) 2448 wqe->flags |= BNXT_QPLIB_SWQE_FLAGS_UC_FENCE; 2449 if (wr->send_flags & IB_SEND_SOLICITED) 2450 wqe->flags |= BNXT_QPLIB_SWQE_FLAGS_SOLICIT_EVENT; 2451 if (wr->send_flags & IB_SEND_INLINE) 2452 wqe->flags |= BNXT_QPLIB_SWQE_FLAGS_INLINE; 2453 2454 return 0; 2455 } 2456 2457 static int bnxt_re_build_rdma_wqe(const struct ib_send_wr *wr, 2458 struct bnxt_qplib_swqe *wqe) 2459 { 2460 switch (wr->opcode) { 2461 case IB_WR_RDMA_WRITE: 2462 wqe->type = BNXT_QPLIB_SWQE_TYPE_RDMA_WRITE; 2463 break; 2464 case IB_WR_RDMA_WRITE_WITH_IMM: 2465 wqe->type = BNXT_QPLIB_SWQE_TYPE_RDMA_WRITE_WITH_IMM; 2466 wqe->rdma.imm_data = wr->ex.imm_data; 2467 break; 2468 case IB_WR_RDMA_READ: 2469 wqe->type = BNXT_QPLIB_SWQE_TYPE_RDMA_READ; 2470 wqe->rdma.inv_key = wr->ex.invalidate_rkey; 2471 break; 2472 default: 2473 return -EINVAL; 2474 } 2475 wqe->rdma.remote_va = rdma_wr(wr)->remote_addr; 2476 wqe->rdma.r_key = rdma_wr(wr)->rkey; 2477 if (wr->send_flags & IB_SEND_SIGNALED) 2478 wqe->flags |= BNXT_QPLIB_SWQE_FLAGS_SIGNAL_COMP; 2479 if (wr->send_flags & IB_SEND_FENCE) 2480 wqe->flags |= BNXT_QPLIB_SWQE_FLAGS_UC_FENCE; 2481 if (wr->send_flags & IB_SEND_SOLICITED) 2482 wqe->flags |= BNXT_QPLIB_SWQE_FLAGS_SOLICIT_EVENT; 2483 if (wr->send_flags & IB_SEND_INLINE) 2484 wqe->flags |= BNXT_QPLIB_SWQE_FLAGS_INLINE; 2485 2486 return 0; 2487 } 2488 2489 static int bnxt_re_build_atomic_wqe(const struct ib_send_wr *wr, 2490 struct bnxt_qplib_swqe *wqe) 2491 { 2492 switch (wr->opcode) { 2493 case IB_WR_ATOMIC_CMP_AND_SWP: 2494 wqe->type = BNXT_QPLIB_SWQE_TYPE_ATOMIC_CMP_AND_SWP; 2495 wqe->atomic.cmp_data = atomic_wr(wr)->compare_add; 2496 wqe->atomic.swap_data = atomic_wr(wr)->swap; 2497 break; 2498 case IB_WR_ATOMIC_FETCH_AND_ADD: 2499 wqe->type = BNXT_QPLIB_SWQE_TYPE_ATOMIC_FETCH_AND_ADD; 2500 wqe->atomic.cmp_data = atomic_wr(wr)->compare_add; 2501 break; 2502 default: 2503 return -EINVAL; 2504 } 2505 wqe->atomic.remote_va = atomic_wr(wr)->remote_addr; 2506 wqe->atomic.r_key = atomic_wr(wr)->rkey; 2507 if (wr->send_flags & IB_SEND_SIGNALED) 2508 wqe->flags |= BNXT_QPLIB_SWQE_FLAGS_SIGNAL_COMP; 2509 if (wr->send_flags & IB_SEND_FENCE) 2510 wqe->flags |= BNXT_QPLIB_SWQE_FLAGS_UC_FENCE; 2511 if (wr->send_flags & IB_SEND_SOLICITED) 2512 wqe->flags |= BNXT_QPLIB_SWQE_FLAGS_SOLICIT_EVENT; 2513 return 0; 2514 } 2515 2516 static int bnxt_re_build_inv_wqe(const struct ib_send_wr *wr, 2517 struct bnxt_qplib_swqe *wqe) 2518 { 2519 wqe->type = BNXT_QPLIB_SWQE_TYPE_LOCAL_INV; 2520 wqe->local_inv.inv_l_key = wr->ex.invalidate_rkey; 2521 2522 /* Need unconditional fence for local invalidate 2523 * opcode to work as expected. 2524 */ 2525 wqe->flags |= BNXT_QPLIB_SWQE_FLAGS_UC_FENCE; 2526 2527 if (wr->send_flags & IB_SEND_SIGNALED) 2528 wqe->flags |= BNXT_QPLIB_SWQE_FLAGS_SIGNAL_COMP; 2529 if (wr->send_flags & IB_SEND_SOLICITED) 2530 wqe->flags |= BNXT_QPLIB_SWQE_FLAGS_SOLICIT_EVENT; 2531 2532 return 0; 2533 } 2534 2535 static int bnxt_re_build_reg_wqe(const struct ib_reg_wr *wr, 2536 struct bnxt_qplib_swqe *wqe) 2537 { 2538 struct bnxt_re_mr *mr = container_of(wr->mr, struct bnxt_re_mr, ib_mr); 2539 struct bnxt_qplib_frpl *qplib_frpl = &mr->qplib_frpl; 2540 int access = wr->access; 2541 2542 wqe->frmr.pbl_ptr = (__le64 *)qplib_frpl->hwq.pbl_ptr[0]; 2543 wqe->frmr.pbl_dma_ptr = qplib_frpl->hwq.pbl_dma_ptr[0]; 2544 wqe->frmr.page_list = mr->pages; 2545 wqe->frmr.page_list_len = mr->npages; 2546 wqe->frmr.levels = qplib_frpl->hwq.level; 2547 wqe->type = BNXT_QPLIB_SWQE_TYPE_REG_MR; 2548 2549 /* Need unconditional fence for reg_mr 2550 * opcode to function as expected. 2551 */ 2552 2553 wqe->flags |= BNXT_QPLIB_SWQE_FLAGS_UC_FENCE; 2554 2555 if (wr->wr.send_flags & IB_SEND_SIGNALED) 2556 wqe->flags |= BNXT_QPLIB_SWQE_FLAGS_SIGNAL_COMP; 2557 2558 if (access & IB_ACCESS_LOCAL_WRITE) 2559 wqe->frmr.access_cntl |= SQ_FR_PMR_ACCESS_CNTL_LOCAL_WRITE; 2560 if (access & IB_ACCESS_REMOTE_READ) 2561 wqe->frmr.access_cntl |= SQ_FR_PMR_ACCESS_CNTL_REMOTE_READ; 2562 if (access & IB_ACCESS_REMOTE_WRITE) 2563 wqe->frmr.access_cntl |= SQ_FR_PMR_ACCESS_CNTL_REMOTE_WRITE; 2564 if (access & IB_ACCESS_REMOTE_ATOMIC) 2565 wqe->frmr.access_cntl |= SQ_FR_PMR_ACCESS_CNTL_REMOTE_ATOMIC; 2566 if (access & IB_ACCESS_MW_BIND) 2567 wqe->frmr.access_cntl |= SQ_FR_PMR_ACCESS_CNTL_WINDOW_BIND; 2568 2569 wqe->frmr.l_key = wr->key; 2570 wqe->frmr.length = wr->mr->length; 2571 wqe->frmr.pbl_pg_sz_log = ilog2(PAGE_SIZE >> PAGE_SHIFT_4K); 2572 wqe->frmr.pg_sz_log = ilog2(wr->mr->page_size >> PAGE_SHIFT_4K); 2573 wqe->frmr.va = wr->mr->iova; 2574 return 0; 2575 } 2576 2577 static int bnxt_re_copy_inline_data(struct bnxt_re_dev *rdev, 2578 const struct ib_send_wr *wr, 2579 struct bnxt_qplib_swqe *wqe) 2580 { 2581 /* Copy the inline data to the data field */ 2582 u8 *in_data; 2583 u32 i, sge_len; 2584 void *sge_addr; 2585 2586 in_data = wqe->inline_data; 2587 for (i = 0; i < wr->num_sge; i++) { 2588 sge_addr = (void *)(unsigned long) 2589 wr->sg_list[i].addr; 2590 sge_len = wr->sg_list[i].length; 2591 2592 if ((sge_len + wqe->inline_len) > 2593 BNXT_QPLIB_SWQE_MAX_INLINE_LENGTH) { 2594 ibdev_err(&rdev->ibdev, 2595 "Inline data size requested > supported value"); 2596 return -EINVAL; 2597 } 2598 sge_len = wr->sg_list[i].length; 2599 2600 memcpy(in_data, sge_addr, sge_len); 2601 in_data += wr->sg_list[i].length; 2602 wqe->inline_len += wr->sg_list[i].length; 2603 } 2604 return wqe->inline_len; 2605 } 2606 2607 static int bnxt_re_copy_wr_payload(struct bnxt_re_dev *rdev, 2608 const struct ib_send_wr *wr, 2609 struct bnxt_qplib_swqe *wqe) 2610 { 2611 int payload_sz = 0; 2612 2613 if (wr->send_flags & IB_SEND_INLINE) 2614 payload_sz = bnxt_re_copy_inline_data(rdev, wr, wqe); 2615 else 2616 payload_sz = bnxt_re_build_sgl(wr->sg_list, wqe->sg_list, 2617 wqe->num_sge); 2618 2619 return payload_sz; 2620 } 2621 2622 static void bnxt_ud_qp_hw_stall_workaround(struct bnxt_re_qp *qp) 2623 { 2624 if ((qp->ib_qp.qp_type == IB_QPT_UD || 2625 qp->ib_qp.qp_type == IB_QPT_GSI || 2626 qp->ib_qp.qp_type == IB_QPT_RAW_ETHERTYPE) && 2627 qp->qplib_qp.wqe_cnt == BNXT_RE_UD_QP_HW_STALL) { 2628 int qp_attr_mask; 2629 struct ib_qp_attr qp_attr; 2630 2631 qp_attr_mask = IB_QP_STATE; 2632 qp_attr.qp_state = IB_QPS_RTS; 2633 bnxt_re_modify_qp(&qp->ib_qp, &qp_attr, qp_attr_mask, NULL); 2634 qp->qplib_qp.wqe_cnt = 0; 2635 } 2636 } 2637 2638 static int bnxt_re_post_send_shadow_qp(struct bnxt_re_dev *rdev, 2639 struct bnxt_re_qp *qp, 2640 const struct ib_send_wr *wr) 2641 { 2642 int rc = 0, payload_sz = 0; 2643 unsigned long flags; 2644 2645 spin_lock_irqsave(&qp->sq_lock, flags); 2646 while (wr) { 2647 struct bnxt_qplib_swqe wqe = {}; 2648 2649 /* Common */ 2650 wqe.num_sge = wr->num_sge; 2651 if (wr->num_sge > qp->qplib_qp.sq.max_sge) { 2652 ibdev_err(&rdev->ibdev, 2653 "Limit exceeded for Send SGEs"); 2654 rc = -EINVAL; 2655 goto bad; 2656 } 2657 2658 payload_sz = bnxt_re_copy_wr_payload(qp->rdev, wr, &wqe); 2659 if (payload_sz < 0) { 2660 rc = -EINVAL; 2661 goto bad; 2662 } 2663 wqe.wr_id = wr->wr_id; 2664 2665 wqe.type = BNXT_QPLIB_SWQE_TYPE_SEND; 2666 2667 rc = bnxt_re_build_send_wqe(qp, wr, &wqe); 2668 if (!rc) 2669 rc = bnxt_qplib_post_send(&qp->qplib_qp, &wqe); 2670 bad: 2671 if (rc) { 2672 ibdev_err(&rdev->ibdev, 2673 "Post send failed opcode = %#x rc = %d", 2674 wr->opcode, rc); 2675 break; 2676 } 2677 wr = wr->next; 2678 } 2679 bnxt_qplib_post_send_db(&qp->qplib_qp); 2680 bnxt_ud_qp_hw_stall_workaround(qp); 2681 spin_unlock_irqrestore(&qp->sq_lock, flags); 2682 return rc; 2683 } 2684 2685 int bnxt_re_post_send(struct ib_qp *ib_qp, const struct ib_send_wr *wr, 2686 const struct ib_send_wr **bad_wr) 2687 { 2688 struct bnxt_re_qp *qp = container_of(ib_qp, struct bnxt_re_qp, ib_qp); 2689 struct bnxt_qplib_swqe wqe; 2690 int rc = 0, payload_sz = 0; 2691 unsigned long flags; 2692 2693 spin_lock_irqsave(&qp->sq_lock, flags); 2694 while (wr) { 2695 /* House keeping */ 2696 memset(&wqe, 0, sizeof(wqe)); 2697 2698 /* Common */ 2699 wqe.num_sge = wr->num_sge; 2700 if (wr->num_sge > qp->qplib_qp.sq.max_sge) { 2701 ibdev_err(&qp->rdev->ibdev, 2702 "Limit exceeded for Send SGEs"); 2703 rc = -EINVAL; 2704 goto bad; 2705 } 2706 2707 payload_sz = bnxt_re_copy_wr_payload(qp->rdev, wr, &wqe); 2708 if (payload_sz < 0) { 2709 rc = -EINVAL; 2710 goto bad; 2711 } 2712 wqe.wr_id = wr->wr_id; 2713 2714 switch (wr->opcode) { 2715 case IB_WR_SEND: 2716 case IB_WR_SEND_WITH_IMM: 2717 if (qp->qplib_qp.type == CMDQ_CREATE_QP1_TYPE_GSI) { 2718 rc = bnxt_re_build_qp1_send_v2(qp, wr, &wqe, 2719 payload_sz); 2720 if (rc) 2721 goto bad; 2722 wqe.rawqp1.lflags |= 2723 SQ_SEND_RAWETH_QP1_LFLAGS_ROCE_CRC; 2724 } 2725 switch (wr->send_flags) { 2726 case IB_SEND_IP_CSUM: 2727 wqe.rawqp1.lflags |= 2728 SQ_SEND_RAWETH_QP1_LFLAGS_IP_CHKSUM; 2729 break; 2730 default: 2731 break; 2732 } 2733 fallthrough; 2734 case IB_WR_SEND_WITH_INV: 2735 rc = bnxt_re_build_send_wqe(qp, wr, &wqe); 2736 break; 2737 case IB_WR_RDMA_WRITE: 2738 case IB_WR_RDMA_WRITE_WITH_IMM: 2739 case IB_WR_RDMA_READ: 2740 rc = bnxt_re_build_rdma_wqe(wr, &wqe); 2741 break; 2742 case IB_WR_ATOMIC_CMP_AND_SWP: 2743 case IB_WR_ATOMIC_FETCH_AND_ADD: 2744 rc = bnxt_re_build_atomic_wqe(wr, &wqe); 2745 break; 2746 case IB_WR_RDMA_READ_WITH_INV: 2747 ibdev_err(&qp->rdev->ibdev, 2748 "RDMA Read with Invalidate is not supported"); 2749 rc = -EINVAL; 2750 goto bad; 2751 case IB_WR_LOCAL_INV: 2752 rc = bnxt_re_build_inv_wqe(wr, &wqe); 2753 break; 2754 case IB_WR_REG_MR: 2755 rc = bnxt_re_build_reg_wqe(reg_wr(wr), &wqe); 2756 break; 2757 default: 2758 /* Unsupported WRs */ 2759 ibdev_err(&qp->rdev->ibdev, 2760 "WR (%#x) is not supported", wr->opcode); 2761 rc = -EINVAL; 2762 goto bad; 2763 } 2764 if (!rc) 2765 rc = bnxt_qplib_post_send(&qp->qplib_qp, &wqe); 2766 bad: 2767 if (rc) { 2768 ibdev_err(&qp->rdev->ibdev, 2769 "post_send failed op:%#x qps = %#x rc = %d\n", 2770 wr->opcode, qp->qplib_qp.state, rc); 2771 *bad_wr = wr; 2772 break; 2773 } 2774 wr = wr->next; 2775 } 2776 bnxt_qplib_post_send_db(&qp->qplib_qp); 2777 bnxt_ud_qp_hw_stall_workaround(qp); 2778 spin_unlock_irqrestore(&qp->sq_lock, flags); 2779 2780 return rc; 2781 } 2782 2783 static int bnxt_re_post_recv_shadow_qp(struct bnxt_re_dev *rdev, 2784 struct bnxt_re_qp *qp, 2785 const struct ib_recv_wr *wr) 2786 { 2787 struct bnxt_qplib_swqe wqe; 2788 int rc = 0; 2789 2790 memset(&wqe, 0, sizeof(wqe)); 2791 while (wr) { 2792 /* House keeping */ 2793 memset(&wqe, 0, sizeof(wqe)); 2794 2795 /* Common */ 2796 wqe.num_sge = wr->num_sge; 2797 if (wr->num_sge > qp->qplib_qp.rq.max_sge) { 2798 ibdev_err(&rdev->ibdev, 2799 "Limit exceeded for Receive SGEs"); 2800 rc = -EINVAL; 2801 break; 2802 } 2803 bnxt_re_build_sgl(wr->sg_list, wqe.sg_list, wr->num_sge); 2804 wqe.wr_id = wr->wr_id; 2805 wqe.type = BNXT_QPLIB_SWQE_TYPE_RECV; 2806 2807 rc = bnxt_qplib_post_recv(&qp->qplib_qp, &wqe); 2808 if (rc) 2809 break; 2810 2811 wr = wr->next; 2812 } 2813 if (!rc) 2814 bnxt_qplib_post_recv_db(&qp->qplib_qp); 2815 return rc; 2816 } 2817 2818 int bnxt_re_post_recv(struct ib_qp *ib_qp, const struct ib_recv_wr *wr, 2819 const struct ib_recv_wr **bad_wr) 2820 { 2821 struct bnxt_re_qp *qp = container_of(ib_qp, struct bnxt_re_qp, ib_qp); 2822 struct bnxt_qplib_swqe wqe; 2823 int rc = 0, payload_sz = 0; 2824 unsigned long flags; 2825 u32 count = 0; 2826 2827 spin_lock_irqsave(&qp->rq_lock, flags); 2828 while (wr) { 2829 /* House keeping */ 2830 memset(&wqe, 0, sizeof(wqe)); 2831 2832 /* Common */ 2833 wqe.num_sge = wr->num_sge; 2834 if (wr->num_sge > qp->qplib_qp.rq.max_sge) { 2835 ibdev_err(&qp->rdev->ibdev, 2836 "Limit exceeded for Receive SGEs"); 2837 rc = -EINVAL; 2838 *bad_wr = wr; 2839 break; 2840 } 2841 2842 payload_sz = bnxt_re_build_sgl(wr->sg_list, wqe.sg_list, 2843 wr->num_sge); 2844 wqe.wr_id = wr->wr_id; 2845 wqe.type = BNXT_QPLIB_SWQE_TYPE_RECV; 2846 2847 if (ib_qp->qp_type == IB_QPT_GSI && 2848 qp->qplib_qp.type != CMDQ_CREATE_QP_TYPE_GSI) 2849 rc = bnxt_re_build_qp1_shadow_qp_recv(qp, wr, &wqe, 2850 payload_sz); 2851 if (!rc) 2852 rc = bnxt_qplib_post_recv(&qp->qplib_qp, &wqe); 2853 if (rc) { 2854 *bad_wr = wr; 2855 break; 2856 } 2857 2858 /* Ring DB if the RQEs posted reaches a threshold value */ 2859 if (++count >= BNXT_RE_RQ_WQE_THRESHOLD) { 2860 bnxt_qplib_post_recv_db(&qp->qplib_qp); 2861 count = 0; 2862 } 2863 2864 wr = wr->next; 2865 } 2866 2867 if (count) 2868 bnxt_qplib_post_recv_db(&qp->qplib_qp); 2869 2870 spin_unlock_irqrestore(&qp->rq_lock, flags); 2871 2872 return rc; 2873 } 2874 2875 /* Completion Queues */ 2876 int bnxt_re_destroy_cq(struct ib_cq *ib_cq, struct ib_udata *udata) 2877 { 2878 struct bnxt_re_cq *cq; 2879 struct bnxt_qplib_nq *nq; 2880 struct bnxt_re_dev *rdev; 2881 2882 cq = container_of(ib_cq, struct bnxt_re_cq, ib_cq); 2883 rdev = cq->rdev; 2884 nq = cq->qplib_cq.nq; 2885 2886 bnxt_qplib_destroy_cq(&rdev->qplib_res, &cq->qplib_cq); 2887 ib_umem_release(cq->umem); 2888 2889 atomic_dec(&rdev->cq_count); 2890 nq->budget--; 2891 kfree(cq->cql); 2892 return 0; 2893 } 2894 2895 int bnxt_re_create_cq(struct ib_cq *ibcq, const struct ib_cq_init_attr *attr, 2896 struct ib_udata *udata) 2897 { 2898 struct bnxt_re_dev *rdev = to_bnxt_re_dev(ibcq->device, ibdev); 2899 struct bnxt_qplib_dev_attr *dev_attr = &rdev->dev_attr; 2900 struct bnxt_re_cq *cq = container_of(ibcq, struct bnxt_re_cq, ib_cq); 2901 int rc, entries; 2902 int cqe = attr->cqe; 2903 struct bnxt_qplib_nq *nq = NULL; 2904 unsigned int nq_alloc_cnt; 2905 2906 if (attr->flags) 2907 return -EOPNOTSUPP; 2908 2909 /* Validate CQ fields */ 2910 if (cqe < 1 || cqe > dev_attr->max_cq_wqes) { 2911 ibdev_err(&rdev->ibdev, "Failed to create CQ -max exceeded"); 2912 return -EINVAL; 2913 } 2914 2915 cq->rdev = rdev; 2916 cq->qplib_cq.cq_handle = (u64)(unsigned long)(&cq->qplib_cq); 2917 2918 entries = roundup_pow_of_two(cqe + 1); 2919 if (entries > dev_attr->max_cq_wqes + 1) 2920 entries = dev_attr->max_cq_wqes + 1; 2921 2922 cq->qplib_cq.sg_info.pgsize = PAGE_SIZE; 2923 cq->qplib_cq.sg_info.pgshft = PAGE_SHIFT; 2924 if (udata) { 2925 struct bnxt_re_cq_req req; 2926 struct bnxt_re_ucontext *uctx = rdma_udata_to_drv_context( 2927 udata, struct bnxt_re_ucontext, ib_uctx); 2928 if (ib_copy_from_udata(&req, udata, sizeof(req))) { 2929 rc = -EFAULT; 2930 goto fail; 2931 } 2932 2933 cq->umem = ib_umem_get(&rdev->ibdev, req.cq_va, 2934 entries * sizeof(struct cq_base), 2935 IB_ACCESS_LOCAL_WRITE); 2936 if (IS_ERR(cq->umem)) { 2937 rc = PTR_ERR(cq->umem); 2938 goto fail; 2939 } 2940 cq->qplib_cq.sg_info.umem = cq->umem; 2941 cq->qplib_cq.dpi = &uctx->dpi; 2942 } else { 2943 cq->max_cql = min_t(u32, entries, MAX_CQL_PER_POLL); 2944 cq->cql = kcalloc(cq->max_cql, sizeof(struct bnxt_qplib_cqe), 2945 GFP_KERNEL); 2946 if (!cq->cql) { 2947 rc = -ENOMEM; 2948 goto fail; 2949 } 2950 2951 cq->qplib_cq.dpi = &rdev->dpi_privileged; 2952 } 2953 /* 2954 * Allocating the NQ in a round robin fashion. nq_alloc_cnt is a 2955 * used for getting the NQ index. 2956 */ 2957 nq_alloc_cnt = atomic_inc_return(&rdev->nq_alloc_cnt); 2958 nq = &rdev->nq[nq_alloc_cnt % (rdev->num_msix - 1)]; 2959 cq->qplib_cq.max_wqe = entries; 2960 cq->qplib_cq.cnq_hw_ring_id = nq->ring_id; 2961 cq->qplib_cq.nq = nq; 2962 2963 rc = bnxt_qplib_create_cq(&rdev->qplib_res, &cq->qplib_cq); 2964 if (rc) { 2965 ibdev_err(&rdev->ibdev, "Failed to create HW CQ"); 2966 goto fail; 2967 } 2968 2969 cq->ib_cq.cqe = entries; 2970 cq->cq_period = cq->qplib_cq.period; 2971 nq->budget++; 2972 2973 atomic_inc(&rdev->cq_count); 2974 spin_lock_init(&cq->cq_lock); 2975 2976 if (udata) { 2977 struct bnxt_re_cq_resp resp; 2978 2979 resp.cqid = cq->qplib_cq.id; 2980 resp.tail = cq->qplib_cq.hwq.cons; 2981 resp.phase = cq->qplib_cq.period; 2982 resp.rsvd = 0; 2983 rc = ib_copy_to_udata(udata, &resp, sizeof(resp)); 2984 if (rc) { 2985 ibdev_err(&rdev->ibdev, "Failed to copy CQ udata"); 2986 bnxt_qplib_destroy_cq(&rdev->qplib_res, &cq->qplib_cq); 2987 goto c2fail; 2988 } 2989 } 2990 2991 return 0; 2992 2993 c2fail: 2994 ib_umem_release(cq->umem); 2995 fail: 2996 kfree(cq->cql); 2997 return rc; 2998 } 2999 3000 static void bnxt_re_resize_cq_complete(struct bnxt_re_cq *cq) 3001 { 3002 struct bnxt_re_dev *rdev = cq->rdev; 3003 3004 bnxt_qplib_resize_cq_complete(&rdev->qplib_res, &cq->qplib_cq); 3005 3006 cq->qplib_cq.max_wqe = cq->resize_cqe; 3007 if (cq->resize_umem) { 3008 ib_umem_release(cq->umem); 3009 cq->umem = cq->resize_umem; 3010 cq->resize_umem = NULL; 3011 cq->resize_cqe = 0; 3012 } 3013 } 3014 3015 int bnxt_re_resize_cq(struct ib_cq *ibcq, int cqe, struct ib_udata *udata) 3016 { 3017 struct bnxt_qplib_sg_info sg_info = {}; 3018 struct bnxt_qplib_dpi *orig_dpi = NULL; 3019 struct bnxt_qplib_dev_attr *dev_attr; 3020 struct bnxt_re_ucontext *uctx = NULL; 3021 struct bnxt_re_resize_cq_req req; 3022 struct bnxt_re_dev *rdev; 3023 struct bnxt_re_cq *cq; 3024 int rc, entries; 3025 3026 cq = container_of(ibcq, struct bnxt_re_cq, ib_cq); 3027 rdev = cq->rdev; 3028 dev_attr = &rdev->dev_attr; 3029 if (!ibcq->uobject) { 3030 ibdev_err(&rdev->ibdev, "Kernel CQ Resize not supported"); 3031 return -EOPNOTSUPP; 3032 } 3033 3034 if (cq->resize_umem) { 3035 ibdev_err(&rdev->ibdev, "Resize CQ %#x failed - Busy", 3036 cq->qplib_cq.id); 3037 return -EBUSY; 3038 } 3039 3040 /* Check the requested cq depth out of supported depth */ 3041 if (cqe < 1 || cqe > dev_attr->max_cq_wqes) { 3042 ibdev_err(&rdev->ibdev, "Resize CQ %#x failed - out of range cqe %d", 3043 cq->qplib_cq.id, cqe); 3044 return -EINVAL; 3045 } 3046 3047 entries = roundup_pow_of_two(cqe + 1); 3048 if (entries > dev_attr->max_cq_wqes + 1) 3049 entries = dev_attr->max_cq_wqes + 1; 3050 3051 uctx = rdma_udata_to_drv_context(udata, struct bnxt_re_ucontext, 3052 ib_uctx); 3053 /* uverbs consumer */ 3054 if (ib_copy_from_udata(&req, udata, sizeof(req))) { 3055 rc = -EFAULT; 3056 goto fail; 3057 } 3058 3059 cq->resize_umem = ib_umem_get(&rdev->ibdev, req.cq_va, 3060 entries * sizeof(struct cq_base), 3061 IB_ACCESS_LOCAL_WRITE); 3062 if (IS_ERR(cq->resize_umem)) { 3063 rc = PTR_ERR(cq->resize_umem); 3064 cq->resize_umem = NULL; 3065 ibdev_err(&rdev->ibdev, "%s: ib_umem_get failed! rc = %d\n", 3066 __func__, rc); 3067 goto fail; 3068 } 3069 cq->resize_cqe = entries; 3070 memcpy(&sg_info, &cq->qplib_cq.sg_info, sizeof(sg_info)); 3071 orig_dpi = cq->qplib_cq.dpi; 3072 3073 cq->qplib_cq.sg_info.umem = cq->resize_umem; 3074 cq->qplib_cq.sg_info.pgsize = PAGE_SIZE; 3075 cq->qplib_cq.sg_info.pgshft = PAGE_SHIFT; 3076 cq->qplib_cq.dpi = &uctx->dpi; 3077 3078 rc = bnxt_qplib_resize_cq(&rdev->qplib_res, &cq->qplib_cq, entries); 3079 if (rc) { 3080 ibdev_err(&rdev->ibdev, "Resize HW CQ %#x failed!", 3081 cq->qplib_cq.id); 3082 goto fail; 3083 } 3084 3085 cq->ib_cq.cqe = cq->resize_cqe; 3086 3087 return 0; 3088 3089 fail: 3090 if (cq->resize_umem) { 3091 ib_umem_release(cq->resize_umem); 3092 cq->resize_umem = NULL; 3093 cq->resize_cqe = 0; 3094 memcpy(&cq->qplib_cq.sg_info, &sg_info, sizeof(sg_info)); 3095 cq->qplib_cq.dpi = orig_dpi; 3096 } 3097 return rc; 3098 } 3099 3100 static u8 __req_to_ib_wc_status(u8 qstatus) 3101 { 3102 switch (qstatus) { 3103 case CQ_REQ_STATUS_OK: 3104 return IB_WC_SUCCESS; 3105 case CQ_REQ_STATUS_BAD_RESPONSE_ERR: 3106 return IB_WC_BAD_RESP_ERR; 3107 case CQ_REQ_STATUS_LOCAL_LENGTH_ERR: 3108 return IB_WC_LOC_LEN_ERR; 3109 case CQ_REQ_STATUS_LOCAL_QP_OPERATION_ERR: 3110 return IB_WC_LOC_QP_OP_ERR; 3111 case CQ_REQ_STATUS_LOCAL_PROTECTION_ERR: 3112 return IB_WC_LOC_PROT_ERR; 3113 case CQ_REQ_STATUS_MEMORY_MGT_OPERATION_ERR: 3114 return IB_WC_GENERAL_ERR; 3115 case CQ_REQ_STATUS_REMOTE_INVALID_REQUEST_ERR: 3116 return IB_WC_REM_INV_REQ_ERR; 3117 case CQ_REQ_STATUS_REMOTE_ACCESS_ERR: 3118 return IB_WC_REM_ACCESS_ERR; 3119 case CQ_REQ_STATUS_REMOTE_OPERATION_ERR: 3120 return IB_WC_REM_OP_ERR; 3121 case CQ_REQ_STATUS_RNR_NAK_RETRY_CNT_ERR: 3122 return IB_WC_RNR_RETRY_EXC_ERR; 3123 case CQ_REQ_STATUS_TRANSPORT_RETRY_CNT_ERR: 3124 return IB_WC_RETRY_EXC_ERR; 3125 case CQ_REQ_STATUS_WORK_REQUEST_FLUSHED_ERR: 3126 return IB_WC_WR_FLUSH_ERR; 3127 default: 3128 return IB_WC_GENERAL_ERR; 3129 } 3130 return 0; 3131 } 3132 3133 static u8 __rawqp1_to_ib_wc_status(u8 qstatus) 3134 { 3135 switch (qstatus) { 3136 case CQ_RES_RAWETH_QP1_STATUS_OK: 3137 return IB_WC_SUCCESS; 3138 case CQ_RES_RAWETH_QP1_STATUS_LOCAL_ACCESS_ERROR: 3139 return IB_WC_LOC_ACCESS_ERR; 3140 case CQ_RES_RAWETH_QP1_STATUS_HW_LOCAL_LENGTH_ERR: 3141 return IB_WC_LOC_LEN_ERR; 3142 case CQ_RES_RAWETH_QP1_STATUS_LOCAL_PROTECTION_ERR: 3143 return IB_WC_LOC_PROT_ERR; 3144 case CQ_RES_RAWETH_QP1_STATUS_LOCAL_QP_OPERATION_ERR: 3145 return IB_WC_LOC_QP_OP_ERR; 3146 case CQ_RES_RAWETH_QP1_STATUS_MEMORY_MGT_OPERATION_ERR: 3147 return IB_WC_GENERAL_ERR; 3148 case CQ_RES_RAWETH_QP1_STATUS_WORK_REQUEST_FLUSHED_ERR: 3149 return IB_WC_WR_FLUSH_ERR; 3150 case CQ_RES_RAWETH_QP1_STATUS_HW_FLUSH_ERR: 3151 return IB_WC_WR_FLUSH_ERR; 3152 default: 3153 return IB_WC_GENERAL_ERR; 3154 } 3155 } 3156 3157 static u8 __rc_to_ib_wc_status(u8 qstatus) 3158 { 3159 switch (qstatus) { 3160 case CQ_RES_RC_STATUS_OK: 3161 return IB_WC_SUCCESS; 3162 case CQ_RES_RC_STATUS_LOCAL_ACCESS_ERROR: 3163 return IB_WC_LOC_ACCESS_ERR; 3164 case CQ_RES_RC_STATUS_LOCAL_LENGTH_ERR: 3165 return IB_WC_LOC_LEN_ERR; 3166 case CQ_RES_RC_STATUS_LOCAL_PROTECTION_ERR: 3167 return IB_WC_LOC_PROT_ERR; 3168 case CQ_RES_RC_STATUS_LOCAL_QP_OPERATION_ERR: 3169 return IB_WC_LOC_QP_OP_ERR; 3170 case CQ_RES_RC_STATUS_MEMORY_MGT_OPERATION_ERR: 3171 return IB_WC_GENERAL_ERR; 3172 case CQ_RES_RC_STATUS_REMOTE_INVALID_REQUEST_ERR: 3173 return IB_WC_REM_INV_REQ_ERR; 3174 case CQ_RES_RC_STATUS_WORK_REQUEST_FLUSHED_ERR: 3175 return IB_WC_WR_FLUSH_ERR; 3176 case CQ_RES_RC_STATUS_HW_FLUSH_ERR: 3177 return IB_WC_WR_FLUSH_ERR; 3178 default: 3179 return IB_WC_GENERAL_ERR; 3180 } 3181 } 3182 3183 static void bnxt_re_process_req_wc(struct ib_wc *wc, struct bnxt_qplib_cqe *cqe) 3184 { 3185 switch (cqe->type) { 3186 case BNXT_QPLIB_SWQE_TYPE_SEND: 3187 wc->opcode = IB_WC_SEND; 3188 break; 3189 case BNXT_QPLIB_SWQE_TYPE_SEND_WITH_IMM: 3190 wc->opcode = IB_WC_SEND; 3191 wc->wc_flags |= IB_WC_WITH_IMM; 3192 break; 3193 case BNXT_QPLIB_SWQE_TYPE_SEND_WITH_INV: 3194 wc->opcode = IB_WC_SEND; 3195 wc->wc_flags |= IB_WC_WITH_INVALIDATE; 3196 break; 3197 case BNXT_QPLIB_SWQE_TYPE_RDMA_WRITE: 3198 wc->opcode = IB_WC_RDMA_WRITE; 3199 break; 3200 case BNXT_QPLIB_SWQE_TYPE_RDMA_WRITE_WITH_IMM: 3201 wc->opcode = IB_WC_RDMA_WRITE; 3202 wc->wc_flags |= IB_WC_WITH_IMM; 3203 break; 3204 case BNXT_QPLIB_SWQE_TYPE_RDMA_READ: 3205 wc->opcode = IB_WC_RDMA_READ; 3206 break; 3207 case BNXT_QPLIB_SWQE_TYPE_ATOMIC_CMP_AND_SWP: 3208 wc->opcode = IB_WC_COMP_SWAP; 3209 break; 3210 case BNXT_QPLIB_SWQE_TYPE_ATOMIC_FETCH_AND_ADD: 3211 wc->opcode = IB_WC_FETCH_ADD; 3212 break; 3213 case BNXT_QPLIB_SWQE_TYPE_LOCAL_INV: 3214 wc->opcode = IB_WC_LOCAL_INV; 3215 break; 3216 case BNXT_QPLIB_SWQE_TYPE_REG_MR: 3217 wc->opcode = IB_WC_REG_MR; 3218 break; 3219 default: 3220 wc->opcode = IB_WC_SEND; 3221 break; 3222 } 3223 3224 wc->status = __req_to_ib_wc_status(cqe->status); 3225 } 3226 3227 static int bnxt_re_check_packet_type(u16 raweth_qp1_flags, 3228 u16 raweth_qp1_flags2) 3229 { 3230 bool is_ipv6 = false, is_ipv4 = false; 3231 3232 /* raweth_qp1_flags Bit 9-6 indicates itype */ 3233 if ((raweth_qp1_flags & CQ_RES_RAWETH_QP1_RAWETH_QP1_FLAGS_ITYPE_ROCE) 3234 != CQ_RES_RAWETH_QP1_RAWETH_QP1_FLAGS_ITYPE_ROCE) 3235 return -1; 3236 3237 if (raweth_qp1_flags2 & 3238 CQ_RES_RAWETH_QP1_RAWETH_QP1_FLAGS2_IP_CS_CALC && 3239 raweth_qp1_flags2 & 3240 CQ_RES_RAWETH_QP1_RAWETH_QP1_FLAGS2_L4_CS_CALC) { 3241 /* raweth_qp1_flags2 Bit 8 indicates ip_type. 0-v4 1 - v6 */ 3242 (raweth_qp1_flags2 & 3243 CQ_RES_RAWETH_QP1_RAWETH_QP1_FLAGS2_IP_TYPE) ? 3244 (is_ipv6 = true) : (is_ipv4 = true); 3245 return ((is_ipv6) ? 3246 BNXT_RE_ROCEV2_IPV6_PACKET : 3247 BNXT_RE_ROCEV2_IPV4_PACKET); 3248 } else { 3249 return BNXT_RE_ROCE_V1_PACKET; 3250 } 3251 } 3252 3253 static int bnxt_re_to_ib_nw_type(int nw_type) 3254 { 3255 u8 nw_hdr_type = 0xFF; 3256 3257 switch (nw_type) { 3258 case BNXT_RE_ROCE_V1_PACKET: 3259 nw_hdr_type = RDMA_NETWORK_ROCE_V1; 3260 break; 3261 case BNXT_RE_ROCEV2_IPV4_PACKET: 3262 nw_hdr_type = RDMA_NETWORK_IPV4; 3263 break; 3264 case BNXT_RE_ROCEV2_IPV6_PACKET: 3265 nw_hdr_type = RDMA_NETWORK_IPV6; 3266 break; 3267 } 3268 return nw_hdr_type; 3269 } 3270 3271 static bool bnxt_re_is_loopback_packet(struct bnxt_re_dev *rdev, 3272 void *rq_hdr_buf) 3273 { 3274 u8 *tmp_buf = NULL; 3275 struct ethhdr *eth_hdr; 3276 u16 eth_type; 3277 bool rc = false; 3278 3279 tmp_buf = (u8 *)rq_hdr_buf; 3280 /* 3281 * If dest mac is not same as I/F mac, this could be a 3282 * loopback address or multicast address, check whether 3283 * it is a loopback packet 3284 */ 3285 if (!ether_addr_equal(tmp_buf, rdev->netdev->dev_addr)) { 3286 tmp_buf += 4; 3287 /* Check the ether type */ 3288 eth_hdr = (struct ethhdr *)tmp_buf; 3289 eth_type = ntohs(eth_hdr->h_proto); 3290 switch (eth_type) { 3291 case ETH_P_IBOE: 3292 rc = true; 3293 break; 3294 case ETH_P_IP: 3295 case ETH_P_IPV6: { 3296 u32 len; 3297 struct udphdr *udp_hdr; 3298 3299 len = (eth_type == ETH_P_IP ? sizeof(struct iphdr) : 3300 sizeof(struct ipv6hdr)); 3301 tmp_buf += sizeof(struct ethhdr) + len; 3302 udp_hdr = (struct udphdr *)tmp_buf; 3303 if (ntohs(udp_hdr->dest) == 3304 ROCE_V2_UDP_DPORT) 3305 rc = true; 3306 break; 3307 } 3308 default: 3309 break; 3310 } 3311 } 3312 3313 return rc; 3314 } 3315 3316 static int bnxt_re_process_raw_qp_pkt_rx(struct bnxt_re_qp *gsi_qp, 3317 struct bnxt_qplib_cqe *cqe) 3318 { 3319 struct bnxt_re_dev *rdev = gsi_qp->rdev; 3320 struct bnxt_re_sqp_entries *sqp_entry = NULL; 3321 struct bnxt_re_qp *gsi_sqp = rdev->gsi_ctx.gsi_sqp; 3322 struct bnxt_re_ah *gsi_sah; 3323 struct ib_send_wr *swr; 3324 struct ib_ud_wr udwr; 3325 struct ib_recv_wr rwr; 3326 int pkt_type = 0; 3327 u32 tbl_idx; 3328 void *rq_hdr_buf; 3329 dma_addr_t rq_hdr_buf_map; 3330 dma_addr_t shrq_hdr_buf_map; 3331 u32 offset = 0; 3332 u32 skip_bytes = 0; 3333 struct ib_sge s_sge[2]; 3334 struct ib_sge r_sge[2]; 3335 int rc; 3336 3337 memset(&udwr, 0, sizeof(udwr)); 3338 memset(&rwr, 0, sizeof(rwr)); 3339 memset(&s_sge, 0, sizeof(s_sge)); 3340 memset(&r_sge, 0, sizeof(r_sge)); 3341 3342 swr = &udwr.wr; 3343 tbl_idx = cqe->wr_id; 3344 3345 rq_hdr_buf = gsi_qp->qplib_qp.rq_hdr_buf + 3346 (tbl_idx * gsi_qp->qplib_qp.rq_hdr_buf_size); 3347 rq_hdr_buf_map = bnxt_qplib_get_qp_buf_from_index(&gsi_qp->qplib_qp, 3348 tbl_idx); 3349 3350 /* Shadow QP header buffer */ 3351 shrq_hdr_buf_map = bnxt_qplib_get_qp_buf_from_index(&gsi_qp->qplib_qp, 3352 tbl_idx); 3353 sqp_entry = &rdev->gsi_ctx.sqp_tbl[tbl_idx]; 3354 3355 /* Store this cqe */ 3356 memcpy(&sqp_entry->cqe, cqe, sizeof(struct bnxt_qplib_cqe)); 3357 sqp_entry->qp1_qp = gsi_qp; 3358 3359 /* Find packet type from the cqe */ 3360 3361 pkt_type = bnxt_re_check_packet_type(cqe->raweth_qp1_flags, 3362 cqe->raweth_qp1_flags2); 3363 if (pkt_type < 0) { 3364 ibdev_err(&rdev->ibdev, "Invalid packet\n"); 3365 return -EINVAL; 3366 } 3367 3368 /* Adjust the offset for the user buffer and post in the rq */ 3369 3370 if (pkt_type == BNXT_RE_ROCEV2_IPV4_PACKET) 3371 offset = 20; 3372 3373 /* 3374 * QP1 loopback packet has 4 bytes of internal header before 3375 * ether header. Skip these four bytes. 3376 */ 3377 if (bnxt_re_is_loopback_packet(rdev, rq_hdr_buf)) 3378 skip_bytes = 4; 3379 3380 /* First send SGE . Skip the ether header*/ 3381 s_sge[0].addr = rq_hdr_buf_map + BNXT_QPLIB_MAX_QP1_RQ_ETH_HDR_SIZE 3382 + skip_bytes; 3383 s_sge[0].lkey = 0xFFFFFFFF; 3384 s_sge[0].length = offset ? BNXT_QPLIB_MAX_GRH_HDR_SIZE_IPV4 : 3385 BNXT_QPLIB_MAX_GRH_HDR_SIZE_IPV6; 3386 3387 /* Second Send SGE */ 3388 s_sge[1].addr = s_sge[0].addr + s_sge[0].length + 3389 BNXT_QPLIB_MAX_QP1_RQ_BDETH_HDR_SIZE; 3390 if (pkt_type != BNXT_RE_ROCE_V1_PACKET) 3391 s_sge[1].addr += 8; 3392 s_sge[1].lkey = 0xFFFFFFFF; 3393 s_sge[1].length = 256; 3394 3395 /* First recv SGE */ 3396 3397 r_sge[0].addr = shrq_hdr_buf_map; 3398 r_sge[0].lkey = 0xFFFFFFFF; 3399 r_sge[0].length = 40; 3400 3401 r_sge[1].addr = sqp_entry->sge.addr + offset; 3402 r_sge[1].lkey = sqp_entry->sge.lkey; 3403 r_sge[1].length = BNXT_QPLIB_MAX_GRH_HDR_SIZE_IPV6 + 256 - offset; 3404 3405 /* Create receive work request */ 3406 rwr.num_sge = 2; 3407 rwr.sg_list = r_sge; 3408 rwr.wr_id = tbl_idx; 3409 rwr.next = NULL; 3410 3411 rc = bnxt_re_post_recv_shadow_qp(rdev, gsi_sqp, &rwr); 3412 if (rc) { 3413 ibdev_err(&rdev->ibdev, 3414 "Failed to post Rx buffers to shadow QP"); 3415 return -ENOMEM; 3416 } 3417 3418 swr->num_sge = 2; 3419 swr->sg_list = s_sge; 3420 swr->wr_id = tbl_idx; 3421 swr->opcode = IB_WR_SEND; 3422 swr->next = NULL; 3423 gsi_sah = rdev->gsi_ctx.gsi_sah; 3424 udwr.ah = &gsi_sah->ib_ah; 3425 udwr.remote_qpn = gsi_sqp->qplib_qp.id; 3426 udwr.remote_qkey = gsi_sqp->qplib_qp.qkey; 3427 3428 /* post data received in the send queue */ 3429 return bnxt_re_post_send_shadow_qp(rdev, gsi_sqp, swr); 3430 } 3431 3432 static void bnxt_re_process_res_rawqp1_wc(struct ib_wc *wc, 3433 struct bnxt_qplib_cqe *cqe) 3434 { 3435 wc->opcode = IB_WC_RECV; 3436 wc->status = __rawqp1_to_ib_wc_status(cqe->status); 3437 wc->wc_flags |= IB_WC_GRH; 3438 } 3439 3440 static bool bnxt_re_check_if_vlan_valid(struct bnxt_re_dev *rdev, 3441 u16 vlan_id) 3442 { 3443 /* 3444 * Check if the vlan is configured in the host. If not configured, it 3445 * can be a transparent VLAN. So dont report the vlan id. 3446 */ 3447 if (!__vlan_find_dev_deep_rcu(rdev->netdev, 3448 htons(ETH_P_8021Q), vlan_id)) 3449 return false; 3450 return true; 3451 } 3452 3453 static bool bnxt_re_is_vlan_pkt(struct bnxt_qplib_cqe *orig_cqe, 3454 u16 *vid, u8 *sl) 3455 { 3456 bool ret = false; 3457 u32 metadata; 3458 u16 tpid; 3459 3460 metadata = orig_cqe->raweth_qp1_metadata; 3461 if (orig_cqe->raweth_qp1_flags2 & 3462 CQ_RES_RAWETH_QP1_RAWETH_QP1_FLAGS2_META_FORMAT_VLAN) { 3463 tpid = ((metadata & 3464 CQ_RES_RAWETH_QP1_RAWETH_QP1_METADATA_TPID_MASK) >> 3465 CQ_RES_RAWETH_QP1_RAWETH_QP1_METADATA_TPID_SFT); 3466 if (tpid == ETH_P_8021Q) { 3467 *vid = metadata & 3468 CQ_RES_RAWETH_QP1_RAWETH_QP1_METADATA_VID_MASK; 3469 *sl = (metadata & 3470 CQ_RES_RAWETH_QP1_RAWETH_QP1_METADATA_PRI_MASK) >> 3471 CQ_RES_RAWETH_QP1_RAWETH_QP1_METADATA_PRI_SFT; 3472 ret = true; 3473 } 3474 } 3475 3476 return ret; 3477 } 3478 3479 static void bnxt_re_process_res_rc_wc(struct ib_wc *wc, 3480 struct bnxt_qplib_cqe *cqe) 3481 { 3482 wc->opcode = IB_WC_RECV; 3483 wc->status = __rc_to_ib_wc_status(cqe->status); 3484 3485 if (cqe->flags & CQ_RES_RC_FLAGS_IMM) 3486 wc->wc_flags |= IB_WC_WITH_IMM; 3487 if (cqe->flags & CQ_RES_RC_FLAGS_INV) 3488 wc->wc_flags |= IB_WC_WITH_INVALIDATE; 3489 if ((cqe->flags & (CQ_RES_RC_FLAGS_RDMA | CQ_RES_RC_FLAGS_IMM)) == 3490 (CQ_RES_RC_FLAGS_RDMA | CQ_RES_RC_FLAGS_IMM)) 3491 wc->opcode = IB_WC_RECV_RDMA_WITH_IMM; 3492 } 3493 3494 static void bnxt_re_process_res_shadow_qp_wc(struct bnxt_re_qp *gsi_sqp, 3495 struct ib_wc *wc, 3496 struct bnxt_qplib_cqe *cqe) 3497 { 3498 struct bnxt_re_dev *rdev = gsi_sqp->rdev; 3499 struct bnxt_re_qp *gsi_qp = NULL; 3500 struct bnxt_qplib_cqe *orig_cqe = NULL; 3501 struct bnxt_re_sqp_entries *sqp_entry = NULL; 3502 int nw_type; 3503 u32 tbl_idx; 3504 u16 vlan_id; 3505 u8 sl; 3506 3507 tbl_idx = cqe->wr_id; 3508 3509 sqp_entry = &rdev->gsi_ctx.sqp_tbl[tbl_idx]; 3510 gsi_qp = sqp_entry->qp1_qp; 3511 orig_cqe = &sqp_entry->cqe; 3512 3513 wc->wr_id = sqp_entry->wrid; 3514 wc->byte_len = orig_cqe->length; 3515 wc->qp = &gsi_qp->ib_qp; 3516 3517 wc->ex.imm_data = orig_cqe->immdata; 3518 wc->src_qp = orig_cqe->src_qp; 3519 memcpy(wc->smac, orig_cqe->smac, ETH_ALEN); 3520 if (bnxt_re_is_vlan_pkt(orig_cqe, &vlan_id, &sl)) { 3521 if (bnxt_re_check_if_vlan_valid(rdev, vlan_id)) { 3522 wc->vlan_id = vlan_id; 3523 wc->sl = sl; 3524 wc->wc_flags |= IB_WC_WITH_VLAN; 3525 } 3526 } 3527 wc->port_num = 1; 3528 wc->vendor_err = orig_cqe->status; 3529 3530 wc->opcode = IB_WC_RECV; 3531 wc->status = __rawqp1_to_ib_wc_status(orig_cqe->status); 3532 wc->wc_flags |= IB_WC_GRH; 3533 3534 nw_type = bnxt_re_check_packet_type(orig_cqe->raweth_qp1_flags, 3535 orig_cqe->raweth_qp1_flags2); 3536 if (nw_type >= 0) { 3537 wc->network_hdr_type = bnxt_re_to_ib_nw_type(nw_type); 3538 wc->wc_flags |= IB_WC_WITH_NETWORK_HDR_TYPE; 3539 } 3540 } 3541 3542 static void bnxt_re_process_res_ud_wc(struct bnxt_re_qp *qp, 3543 struct ib_wc *wc, 3544 struct bnxt_qplib_cqe *cqe) 3545 { 3546 struct bnxt_re_dev *rdev; 3547 u16 vlan_id = 0; 3548 u8 nw_type; 3549 3550 rdev = qp->rdev; 3551 wc->opcode = IB_WC_RECV; 3552 wc->status = __rc_to_ib_wc_status(cqe->status); 3553 3554 if (cqe->flags & CQ_RES_UD_FLAGS_IMM) 3555 wc->wc_flags |= IB_WC_WITH_IMM; 3556 /* report only on GSI QP for Thor */ 3557 if (qp->qplib_qp.type == CMDQ_CREATE_QP_TYPE_GSI) { 3558 wc->wc_flags |= IB_WC_GRH; 3559 memcpy(wc->smac, cqe->smac, ETH_ALEN); 3560 wc->wc_flags |= IB_WC_WITH_SMAC; 3561 if (cqe->flags & CQ_RES_UD_FLAGS_META_FORMAT_VLAN) { 3562 vlan_id = (cqe->cfa_meta & 0xFFF); 3563 } 3564 /* Mark only if vlan_id is non zero */ 3565 if (vlan_id && bnxt_re_check_if_vlan_valid(rdev, vlan_id)) { 3566 wc->vlan_id = vlan_id; 3567 wc->wc_flags |= IB_WC_WITH_VLAN; 3568 } 3569 nw_type = (cqe->flags & CQ_RES_UD_FLAGS_ROCE_IP_VER_MASK) >> 3570 CQ_RES_UD_FLAGS_ROCE_IP_VER_SFT; 3571 wc->network_hdr_type = bnxt_re_to_ib_nw_type(nw_type); 3572 wc->wc_flags |= IB_WC_WITH_NETWORK_HDR_TYPE; 3573 } 3574 3575 } 3576 3577 static int send_phantom_wqe(struct bnxt_re_qp *qp) 3578 { 3579 struct bnxt_qplib_qp *lib_qp = &qp->qplib_qp; 3580 unsigned long flags; 3581 int rc = 0; 3582 3583 spin_lock_irqsave(&qp->sq_lock, flags); 3584 3585 rc = bnxt_re_bind_fence_mw(lib_qp); 3586 if (!rc) { 3587 lib_qp->sq.phantom_wqe_cnt++; 3588 ibdev_dbg(&qp->rdev->ibdev, 3589 "qp %#x sq->prod %#x sw_prod %#x phantom_wqe_cnt %d\n", 3590 lib_qp->id, lib_qp->sq.hwq.prod, 3591 HWQ_CMP(lib_qp->sq.hwq.prod, &lib_qp->sq.hwq), 3592 lib_qp->sq.phantom_wqe_cnt); 3593 } 3594 3595 spin_unlock_irqrestore(&qp->sq_lock, flags); 3596 return rc; 3597 } 3598 3599 int bnxt_re_poll_cq(struct ib_cq *ib_cq, int num_entries, struct ib_wc *wc) 3600 { 3601 struct bnxt_re_cq *cq = container_of(ib_cq, struct bnxt_re_cq, ib_cq); 3602 struct bnxt_re_qp *qp, *sh_qp; 3603 struct bnxt_qplib_cqe *cqe; 3604 int i, ncqe, budget; 3605 struct bnxt_qplib_q *sq; 3606 struct bnxt_qplib_qp *lib_qp; 3607 u32 tbl_idx; 3608 struct bnxt_re_sqp_entries *sqp_entry = NULL; 3609 unsigned long flags; 3610 3611 /* User CQ; the only processing we do is to 3612 * complete any pending CQ resize operation. 3613 */ 3614 if (cq->umem) { 3615 if (cq->resize_umem) 3616 bnxt_re_resize_cq_complete(cq); 3617 return 0; 3618 } 3619 3620 spin_lock_irqsave(&cq->cq_lock, flags); 3621 budget = min_t(u32, num_entries, cq->max_cql); 3622 num_entries = budget; 3623 if (!cq->cql) { 3624 ibdev_err(&cq->rdev->ibdev, "POLL CQ : no CQL to use"); 3625 goto exit; 3626 } 3627 cqe = &cq->cql[0]; 3628 while (budget) { 3629 lib_qp = NULL; 3630 ncqe = bnxt_qplib_poll_cq(&cq->qplib_cq, cqe, budget, &lib_qp); 3631 if (lib_qp) { 3632 sq = &lib_qp->sq; 3633 if (sq->send_phantom) { 3634 qp = container_of(lib_qp, 3635 struct bnxt_re_qp, qplib_qp); 3636 if (send_phantom_wqe(qp) == -ENOMEM) 3637 ibdev_err(&cq->rdev->ibdev, 3638 "Phantom failed! Scheduled to send again\n"); 3639 else 3640 sq->send_phantom = false; 3641 } 3642 } 3643 if (ncqe < budget) 3644 ncqe += bnxt_qplib_process_flush_list(&cq->qplib_cq, 3645 cqe + ncqe, 3646 budget - ncqe); 3647 3648 if (!ncqe) 3649 break; 3650 3651 for (i = 0; i < ncqe; i++, cqe++) { 3652 /* Transcribe each qplib_wqe back to ib_wc */ 3653 memset(wc, 0, sizeof(*wc)); 3654 3655 wc->wr_id = cqe->wr_id; 3656 wc->byte_len = cqe->length; 3657 qp = container_of 3658 ((struct bnxt_qplib_qp *) 3659 (unsigned long)(cqe->qp_handle), 3660 struct bnxt_re_qp, qplib_qp); 3661 wc->qp = &qp->ib_qp; 3662 wc->ex.imm_data = cqe->immdata; 3663 wc->src_qp = cqe->src_qp; 3664 memcpy(wc->smac, cqe->smac, ETH_ALEN); 3665 wc->port_num = 1; 3666 wc->vendor_err = cqe->status; 3667 3668 switch (cqe->opcode) { 3669 case CQ_BASE_CQE_TYPE_REQ: 3670 sh_qp = qp->rdev->gsi_ctx.gsi_sqp; 3671 if (sh_qp && 3672 qp->qplib_qp.id == sh_qp->qplib_qp.id) { 3673 /* Handle this completion with 3674 * the stored completion 3675 */ 3676 memset(wc, 0, sizeof(*wc)); 3677 continue; 3678 } 3679 bnxt_re_process_req_wc(wc, cqe); 3680 break; 3681 case CQ_BASE_CQE_TYPE_RES_RAWETH_QP1: 3682 if (!cqe->status) { 3683 int rc = 0; 3684 3685 rc = bnxt_re_process_raw_qp_pkt_rx 3686 (qp, cqe); 3687 if (!rc) { 3688 memset(wc, 0, sizeof(*wc)); 3689 continue; 3690 } 3691 cqe->status = -1; 3692 } 3693 /* Errors need not be looped back. 3694 * But change the wr_id to the one 3695 * stored in the table 3696 */ 3697 tbl_idx = cqe->wr_id; 3698 sqp_entry = &cq->rdev->gsi_ctx.sqp_tbl[tbl_idx]; 3699 wc->wr_id = sqp_entry->wrid; 3700 bnxt_re_process_res_rawqp1_wc(wc, cqe); 3701 break; 3702 case CQ_BASE_CQE_TYPE_RES_RC: 3703 bnxt_re_process_res_rc_wc(wc, cqe); 3704 break; 3705 case CQ_BASE_CQE_TYPE_RES_UD: 3706 sh_qp = qp->rdev->gsi_ctx.gsi_sqp; 3707 if (sh_qp && 3708 qp->qplib_qp.id == sh_qp->qplib_qp.id) { 3709 /* Handle this completion with 3710 * the stored completion 3711 */ 3712 if (cqe->status) { 3713 continue; 3714 } else { 3715 bnxt_re_process_res_shadow_qp_wc 3716 (qp, wc, cqe); 3717 break; 3718 } 3719 } 3720 bnxt_re_process_res_ud_wc(qp, wc, cqe); 3721 break; 3722 default: 3723 ibdev_err(&cq->rdev->ibdev, 3724 "POLL CQ : type 0x%x not handled", 3725 cqe->opcode); 3726 continue; 3727 } 3728 wc++; 3729 budget--; 3730 } 3731 } 3732 exit: 3733 spin_unlock_irqrestore(&cq->cq_lock, flags); 3734 return num_entries - budget; 3735 } 3736 3737 int bnxt_re_req_notify_cq(struct ib_cq *ib_cq, 3738 enum ib_cq_notify_flags ib_cqn_flags) 3739 { 3740 struct bnxt_re_cq *cq = container_of(ib_cq, struct bnxt_re_cq, ib_cq); 3741 int type = 0, rc = 0; 3742 unsigned long flags; 3743 3744 spin_lock_irqsave(&cq->cq_lock, flags); 3745 /* Trigger on the very next completion */ 3746 if (ib_cqn_flags & IB_CQ_NEXT_COMP) 3747 type = DBC_DBC_TYPE_CQ_ARMALL; 3748 /* Trigger on the next solicited completion */ 3749 else if (ib_cqn_flags & IB_CQ_SOLICITED) 3750 type = DBC_DBC_TYPE_CQ_ARMSE; 3751 3752 /* Poll to see if there are missed events */ 3753 if ((ib_cqn_flags & IB_CQ_REPORT_MISSED_EVENTS) && 3754 !(bnxt_qplib_is_cq_empty(&cq->qplib_cq))) { 3755 rc = 1; 3756 goto exit; 3757 } 3758 bnxt_qplib_req_notify_cq(&cq->qplib_cq, type); 3759 3760 exit: 3761 spin_unlock_irqrestore(&cq->cq_lock, flags); 3762 return rc; 3763 } 3764 3765 /* Memory Regions */ 3766 struct ib_mr *bnxt_re_get_dma_mr(struct ib_pd *ib_pd, int mr_access_flags) 3767 { 3768 struct bnxt_re_pd *pd = container_of(ib_pd, struct bnxt_re_pd, ib_pd); 3769 struct bnxt_re_dev *rdev = pd->rdev; 3770 struct bnxt_re_mr *mr; 3771 int rc; 3772 3773 mr = kzalloc(sizeof(*mr), GFP_KERNEL); 3774 if (!mr) 3775 return ERR_PTR(-ENOMEM); 3776 3777 mr->rdev = rdev; 3778 mr->qplib_mr.pd = &pd->qplib_pd; 3779 mr->qplib_mr.flags = __from_ib_access_flags(mr_access_flags); 3780 mr->qplib_mr.type = CMDQ_ALLOCATE_MRW_MRW_FLAGS_PMR; 3781 3782 /* Allocate and register 0 as the address */ 3783 rc = bnxt_qplib_alloc_mrw(&rdev->qplib_res, &mr->qplib_mr); 3784 if (rc) 3785 goto fail; 3786 3787 mr->qplib_mr.hwq.level = PBL_LVL_MAX; 3788 mr->qplib_mr.total_size = -1; /* Infinte length */ 3789 rc = bnxt_qplib_reg_mr(&rdev->qplib_res, &mr->qplib_mr, NULL, 0, 3790 PAGE_SIZE); 3791 if (rc) 3792 goto fail_mr; 3793 3794 mr->ib_mr.lkey = mr->qplib_mr.lkey; 3795 if (mr_access_flags & (IB_ACCESS_REMOTE_WRITE | IB_ACCESS_REMOTE_READ | 3796 IB_ACCESS_REMOTE_ATOMIC)) 3797 mr->ib_mr.rkey = mr->ib_mr.lkey; 3798 atomic_inc(&rdev->mr_count); 3799 3800 return &mr->ib_mr; 3801 3802 fail_mr: 3803 bnxt_qplib_free_mrw(&rdev->qplib_res, &mr->qplib_mr); 3804 fail: 3805 kfree(mr); 3806 return ERR_PTR(rc); 3807 } 3808 3809 int bnxt_re_dereg_mr(struct ib_mr *ib_mr, struct ib_udata *udata) 3810 { 3811 struct bnxt_re_mr *mr = container_of(ib_mr, struct bnxt_re_mr, ib_mr); 3812 struct bnxt_re_dev *rdev = mr->rdev; 3813 int rc; 3814 3815 rc = bnxt_qplib_free_mrw(&rdev->qplib_res, &mr->qplib_mr); 3816 if (rc) { 3817 ibdev_err(&rdev->ibdev, "Dereg MR failed: %#x\n", rc); 3818 return rc; 3819 } 3820 3821 if (mr->pages) { 3822 rc = bnxt_qplib_free_fast_reg_page_list(&rdev->qplib_res, 3823 &mr->qplib_frpl); 3824 kfree(mr->pages); 3825 mr->npages = 0; 3826 mr->pages = NULL; 3827 } 3828 ib_umem_release(mr->ib_umem); 3829 3830 kfree(mr); 3831 atomic_dec(&rdev->mr_count); 3832 return rc; 3833 } 3834 3835 static int bnxt_re_set_page(struct ib_mr *ib_mr, u64 addr) 3836 { 3837 struct bnxt_re_mr *mr = container_of(ib_mr, struct bnxt_re_mr, ib_mr); 3838 3839 if (unlikely(mr->npages == mr->qplib_frpl.max_pg_ptrs)) 3840 return -ENOMEM; 3841 3842 mr->pages[mr->npages++] = addr; 3843 return 0; 3844 } 3845 3846 int bnxt_re_map_mr_sg(struct ib_mr *ib_mr, struct scatterlist *sg, int sg_nents, 3847 unsigned int *sg_offset) 3848 { 3849 struct bnxt_re_mr *mr = container_of(ib_mr, struct bnxt_re_mr, ib_mr); 3850 3851 mr->npages = 0; 3852 return ib_sg_to_pages(ib_mr, sg, sg_nents, sg_offset, bnxt_re_set_page); 3853 } 3854 3855 struct ib_mr *bnxt_re_alloc_mr(struct ib_pd *ib_pd, enum ib_mr_type type, 3856 u32 max_num_sg) 3857 { 3858 struct bnxt_re_pd *pd = container_of(ib_pd, struct bnxt_re_pd, ib_pd); 3859 struct bnxt_re_dev *rdev = pd->rdev; 3860 struct bnxt_re_mr *mr = NULL; 3861 int rc; 3862 3863 if (type != IB_MR_TYPE_MEM_REG) { 3864 ibdev_dbg(&rdev->ibdev, "MR type 0x%x not supported", type); 3865 return ERR_PTR(-EINVAL); 3866 } 3867 if (max_num_sg > MAX_PBL_LVL_1_PGS) 3868 return ERR_PTR(-EINVAL); 3869 3870 mr = kzalloc(sizeof(*mr), GFP_KERNEL); 3871 if (!mr) 3872 return ERR_PTR(-ENOMEM); 3873 3874 mr->rdev = rdev; 3875 mr->qplib_mr.pd = &pd->qplib_pd; 3876 mr->qplib_mr.flags = BNXT_QPLIB_FR_PMR; 3877 mr->qplib_mr.type = CMDQ_ALLOCATE_MRW_MRW_FLAGS_PMR; 3878 3879 rc = bnxt_qplib_alloc_mrw(&rdev->qplib_res, &mr->qplib_mr); 3880 if (rc) 3881 goto bail; 3882 3883 mr->ib_mr.lkey = mr->qplib_mr.lkey; 3884 mr->ib_mr.rkey = mr->ib_mr.lkey; 3885 3886 mr->pages = kcalloc(max_num_sg, sizeof(u64), GFP_KERNEL); 3887 if (!mr->pages) { 3888 rc = -ENOMEM; 3889 goto fail; 3890 } 3891 rc = bnxt_qplib_alloc_fast_reg_page_list(&rdev->qplib_res, 3892 &mr->qplib_frpl, max_num_sg); 3893 if (rc) { 3894 ibdev_err(&rdev->ibdev, 3895 "Failed to allocate HW FR page list"); 3896 goto fail_mr; 3897 } 3898 3899 atomic_inc(&rdev->mr_count); 3900 return &mr->ib_mr; 3901 3902 fail_mr: 3903 kfree(mr->pages); 3904 fail: 3905 bnxt_qplib_free_mrw(&rdev->qplib_res, &mr->qplib_mr); 3906 bail: 3907 kfree(mr); 3908 return ERR_PTR(rc); 3909 } 3910 3911 struct ib_mw *bnxt_re_alloc_mw(struct ib_pd *ib_pd, enum ib_mw_type type, 3912 struct ib_udata *udata) 3913 { 3914 struct bnxt_re_pd *pd = container_of(ib_pd, struct bnxt_re_pd, ib_pd); 3915 struct bnxt_re_dev *rdev = pd->rdev; 3916 struct bnxt_re_mw *mw; 3917 int rc; 3918 3919 mw = kzalloc(sizeof(*mw), GFP_KERNEL); 3920 if (!mw) 3921 return ERR_PTR(-ENOMEM); 3922 mw->rdev = rdev; 3923 mw->qplib_mw.pd = &pd->qplib_pd; 3924 3925 mw->qplib_mw.type = (type == IB_MW_TYPE_1 ? 3926 CMDQ_ALLOCATE_MRW_MRW_FLAGS_MW_TYPE1 : 3927 CMDQ_ALLOCATE_MRW_MRW_FLAGS_MW_TYPE2B); 3928 rc = bnxt_qplib_alloc_mrw(&rdev->qplib_res, &mw->qplib_mw); 3929 if (rc) { 3930 ibdev_err(&rdev->ibdev, "Allocate MW failed!"); 3931 goto fail; 3932 } 3933 mw->ib_mw.rkey = mw->qplib_mw.rkey; 3934 3935 atomic_inc(&rdev->mw_count); 3936 return &mw->ib_mw; 3937 3938 fail: 3939 kfree(mw); 3940 return ERR_PTR(rc); 3941 } 3942 3943 int bnxt_re_dealloc_mw(struct ib_mw *ib_mw) 3944 { 3945 struct bnxt_re_mw *mw = container_of(ib_mw, struct bnxt_re_mw, ib_mw); 3946 struct bnxt_re_dev *rdev = mw->rdev; 3947 int rc; 3948 3949 rc = bnxt_qplib_free_mrw(&rdev->qplib_res, &mw->qplib_mw); 3950 if (rc) { 3951 ibdev_err(&rdev->ibdev, "Free MW failed: %#x\n", rc); 3952 return rc; 3953 } 3954 3955 kfree(mw); 3956 atomic_dec(&rdev->mw_count); 3957 return rc; 3958 } 3959 3960 /* uverbs */ 3961 struct ib_mr *bnxt_re_reg_user_mr(struct ib_pd *ib_pd, u64 start, u64 length, 3962 u64 virt_addr, int mr_access_flags, 3963 struct ib_udata *udata) 3964 { 3965 struct bnxt_re_pd *pd = container_of(ib_pd, struct bnxt_re_pd, ib_pd); 3966 struct bnxt_re_dev *rdev = pd->rdev; 3967 struct bnxt_re_mr *mr; 3968 struct ib_umem *umem; 3969 unsigned long page_size; 3970 int umem_pgs, rc; 3971 3972 if (length > BNXT_RE_MAX_MR_SIZE) { 3973 ibdev_err(&rdev->ibdev, "MR Size: %lld > Max supported:%lld\n", 3974 length, BNXT_RE_MAX_MR_SIZE); 3975 return ERR_PTR(-ENOMEM); 3976 } 3977 3978 mr = kzalloc(sizeof(*mr), GFP_KERNEL); 3979 if (!mr) 3980 return ERR_PTR(-ENOMEM); 3981 3982 mr->rdev = rdev; 3983 mr->qplib_mr.pd = &pd->qplib_pd; 3984 mr->qplib_mr.flags = __from_ib_access_flags(mr_access_flags); 3985 mr->qplib_mr.type = CMDQ_ALLOCATE_MRW_MRW_FLAGS_MR; 3986 3987 rc = bnxt_qplib_alloc_mrw(&rdev->qplib_res, &mr->qplib_mr); 3988 if (rc) { 3989 ibdev_err(&rdev->ibdev, "Failed to allocate MR"); 3990 goto free_mr; 3991 } 3992 /* The fixed portion of the rkey is the same as the lkey */ 3993 mr->ib_mr.rkey = mr->qplib_mr.rkey; 3994 3995 umem = ib_umem_get(&rdev->ibdev, start, length, mr_access_flags); 3996 if (IS_ERR(umem)) { 3997 ibdev_err(&rdev->ibdev, "Failed to get umem"); 3998 rc = -EFAULT; 3999 goto free_mrw; 4000 } 4001 mr->ib_umem = umem; 4002 4003 mr->qplib_mr.va = virt_addr; 4004 page_size = ib_umem_find_best_pgsz( 4005 umem, BNXT_RE_PAGE_SIZE_SUPPORTED, virt_addr); 4006 if (!page_size) { 4007 ibdev_err(&rdev->ibdev, "umem page size unsupported!"); 4008 rc = -EFAULT; 4009 goto free_umem; 4010 } 4011 mr->qplib_mr.total_size = length; 4012 4013 umem_pgs = ib_umem_num_dma_blocks(umem, page_size); 4014 rc = bnxt_qplib_reg_mr(&rdev->qplib_res, &mr->qplib_mr, umem, 4015 umem_pgs, page_size); 4016 if (rc) { 4017 ibdev_err(&rdev->ibdev, "Failed to register user MR"); 4018 goto free_umem; 4019 } 4020 4021 mr->ib_mr.lkey = mr->qplib_mr.lkey; 4022 mr->ib_mr.rkey = mr->qplib_mr.lkey; 4023 atomic_inc(&rdev->mr_count); 4024 4025 return &mr->ib_mr; 4026 free_umem: 4027 ib_umem_release(umem); 4028 free_mrw: 4029 bnxt_qplib_free_mrw(&rdev->qplib_res, &mr->qplib_mr); 4030 free_mr: 4031 kfree(mr); 4032 return ERR_PTR(rc); 4033 } 4034 4035 int bnxt_re_alloc_ucontext(struct ib_ucontext *ctx, struct ib_udata *udata) 4036 { 4037 struct ib_device *ibdev = ctx->device; 4038 struct bnxt_re_ucontext *uctx = 4039 container_of(ctx, struct bnxt_re_ucontext, ib_uctx); 4040 struct bnxt_re_dev *rdev = to_bnxt_re_dev(ibdev, ibdev); 4041 struct bnxt_qplib_dev_attr *dev_attr = &rdev->dev_attr; 4042 struct bnxt_re_user_mmap_entry *entry; 4043 struct bnxt_re_uctx_resp resp = {}; 4044 u32 chip_met_rev_num = 0; 4045 int rc; 4046 4047 ibdev_dbg(ibdev, "ABI version requested %u", ibdev->ops.uverbs_abi_ver); 4048 4049 if (ibdev->ops.uverbs_abi_ver != BNXT_RE_ABI_VERSION) { 4050 ibdev_dbg(ibdev, " is different from the device %d ", 4051 BNXT_RE_ABI_VERSION); 4052 return -EPERM; 4053 } 4054 4055 uctx->rdev = rdev; 4056 4057 uctx->shpg = (void *)__get_free_page(GFP_KERNEL); 4058 if (!uctx->shpg) { 4059 rc = -ENOMEM; 4060 goto fail; 4061 } 4062 spin_lock_init(&uctx->sh_lock); 4063 4064 resp.comp_mask = BNXT_RE_UCNTX_CMASK_HAVE_CCTX; 4065 chip_met_rev_num = rdev->chip_ctx->chip_num; 4066 chip_met_rev_num |= ((u32)rdev->chip_ctx->chip_rev & 0xFF) << 4067 BNXT_RE_CHIP_ID0_CHIP_REV_SFT; 4068 chip_met_rev_num |= ((u32)rdev->chip_ctx->chip_metal & 0xFF) << 4069 BNXT_RE_CHIP_ID0_CHIP_MET_SFT; 4070 resp.chip_id0 = chip_met_rev_num; 4071 /*Temp, Use xa_alloc instead */ 4072 resp.dev_id = rdev->en_dev->pdev->devfn; 4073 resp.max_qp = rdev->qplib_ctx.qpc_count; 4074 resp.pg_size = PAGE_SIZE; 4075 resp.cqe_sz = sizeof(struct cq_base); 4076 resp.max_cqd = dev_attr->max_cq_wqes; 4077 4078 resp.comp_mask |= BNXT_RE_UCNTX_CMASK_HAVE_MODE; 4079 resp.mode = rdev->chip_ctx->modes.wqe_mode; 4080 4081 if (rdev->chip_ctx->modes.db_push) 4082 resp.comp_mask |= BNXT_RE_UCNTX_CMASK_WC_DPI_ENABLED; 4083 4084 entry = bnxt_re_mmap_entry_insert(uctx, 0, BNXT_RE_MMAP_SH_PAGE, NULL); 4085 if (!entry) { 4086 rc = -ENOMEM; 4087 goto cfail; 4088 } 4089 uctx->shpage_mmap = &entry->rdma_entry; 4090 4091 rc = ib_copy_to_udata(udata, &resp, min(udata->outlen, sizeof(resp))); 4092 if (rc) { 4093 ibdev_err(ibdev, "Failed to copy user context"); 4094 rc = -EFAULT; 4095 goto cfail; 4096 } 4097 4098 return 0; 4099 cfail: 4100 free_page((unsigned long)uctx->shpg); 4101 uctx->shpg = NULL; 4102 fail: 4103 return rc; 4104 } 4105 4106 void bnxt_re_dealloc_ucontext(struct ib_ucontext *ib_uctx) 4107 { 4108 struct bnxt_re_ucontext *uctx = container_of(ib_uctx, 4109 struct bnxt_re_ucontext, 4110 ib_uctx); 4111 4112 struct bnxt_re_dev *rdev = uctx->rdev; 4113 4114 rdma_user_mmap_entry_remove(uctx->shpage_mmap); 4115 uctx->shpage_mmap = NULL; 4116 if (uctx->shpg) 4117 free_page((unsigned long)uctx->shpg); 4118 4119 if (uctx->dpi.dbr) { 4120 /* Free DPI only if this is the first PD allocated by the 4121 * application and mark the context dpi as NULL 4122 */ 4123 bnxt_qplib_dealloc_dpi(&rdev->qplib_res, &uctx->dpi); 4124 uctx->dpi.dbr = NULL; 4125 } 4126 } 4127 4128 /* Helper function to mmap the virtual memory from user app */ 4129 int bnxt_re_mmap(struct ib_ucontext *ib_uctx, struct vm_area_struct *vma) 4130 { 4131 struct bnxt_re_ucontext *uctx = container_of(ib_uctx, 4132 struct bnxt_re_ucontext, 4133 ib_uctx); 4134 struct bnxt_re_user_mmap_entry *bnxt_entry; 4135 struct rdma_user_mmap_entry *rdma_entry; 4136 int ret = 0; 4137 u64 pfn; 4138 4139 rdma_entry = rdma_user_mmap_entry_get(&uctx->ib_uctx, vma); 4140 if (!rdma_entry) 4141 return -EINVAL; 4142 4143 bnxt_entry = container_of(rdma_entry, struct bnxt_re_user_mmap_entry, 4144 rdma_entry); 4145 4146 switch (bnxt_entry->mmap_flag) { 4147 case BNXT_RE_MMAP_WC_DB: 4148 pfn = bnxt_entry->mem_offset >> PAGE_SHIFT; 4149 ret = rdma_user_mmap_io(ib_uctx, vma, pfn, PAGE_SIZE, 4150 pgprot_writecombine(vma->vm_page_prot), 4151 rdma_entry); 4152 break; 4153 case BNXT_RE_MMAP_UC_DB: 4154 pfn = bnxt_entry->mem_offset >> PAGE_SHIFT; 4155 ret = rdma_user_mmap_io(ib_uctx, vma, pfn, PAGE_SIZE, 4156 pgprot_noncached(vma->vm_page_prot), 4157 rdma_entry); 4158 break; 4159 case BNXT_RE_MMAP_SH_PAGE: 4160 ret = vm_insert_page(vma, vma->vm_start, virt_to_page(uctx->shpg)); 4161 break; 4162 default: 4163 ret = -EINVAL; 4164 break; 4165 } 4166 4167 rdma_user_mmap_entry_put(rdma_entry); 4168 return ret; 4169 } 4170 4171 void bnxt_re_mmap_free(struct rdma_user_mmap_entry *rdma_entry) 4172 { 4173 struct bnxt_re_user_mmap_entry *bnxt_entry; 4174 4175 bnxt_entry = container_of(rdma_entry, struct bnxt_re_user_mmap_entry, 4176 rdma_entry); 4177 4178 kfree(bnxt_entry); 4179 } 4180 4181 static int UVERBS_HANDLER(BNXT_RE_METHOD_ALLOC_PAGE)(struct uverbs_attr_bundle *attrs) 4182 { 4183 struct ib_uobject *uobj = uverbs_attr_get_uobject(attrs, BNXT_RE_ALLOC_PAGE_HANDLE); 4184 enum bnxt_re_alloc_page_type alloc_type; 4185 struct bnxt_re_user_mmap_entry *entry; 4186 enum bnxt_re_mmap_flag mmap_flag; 4187 struct bnxt_qplib_chip_ctx *cctx; 4188 struct bnxt_re_ucontext *uctx; 4189 struct bnxt_re_dev *rdev; 4190 u64 mmap_offset; 4191 u32 length; 4192 u32 dpi; 4193 u64 dbr; 4194 int err; 4195 4196 uctx = container_of(ib_uverbs_get_ucontext(attrs), struct bnxt_re_ucontext, ib_uctx); 4197 if (IS_ERR(uctx)) 4198 return PTR_ERR(uctx); 4199 4200 err = uverbs_get_const(&alloc_type, attrs, BNXT_RE_ALLOC_PAGE_TYPE); 4201 if (err) 4202 return err; 4203 4204 rdev = uctx->rdev; 4205 cctx = rdev->chip_ctx; 4206 4207 switch (alloc_type) { 4208 case BNXT_RE_ALLOC_WC_PAGE: 4209 if (cctx->modes.db_push) { 4210 if (bnxt_qplib_alloc_dpi(&rdev->qplib_res, &uctx->wcdpi, 4211 uctx, BNXT_QPLIB_DPI_TYPE_WC)) 4212 return -ENOMEM; 4213 length = PAGE_SIZE; 4214 dpi = uctx->wcdpi.dpi; 4215 dbr = (u64)uctx->wcdpi.umdbr; 4216 mmap_flag = BNXT_RE_MMAP_WC_DB; 4217 } else { 4218 return -EINVAL; 4219 } 4220 4221 break; 4222 4223 default: 4224 return -EOPNOTSUPP; 4225 } 4226 4227 entry = bnxt_re_mmap_entry_insert(uctx, dbr, mmap_flag, &mmap_offset); 4228 if (!entry) 4229 return -ENOMEM; 4230 4231 uobj->object = entry; 4232 uverbs_finalize_uobj_create(attrs, BNXT_RE_ALLOC_PAGE_HANDLE); 4233 err = uverbs_copy_to(attrs, BNXT_RE_ALLOC_PAGE_MMAP_OFFSET, 4234 &mmap_offset, sizeof(mmap_offset)); 4235 if (err) 4236 return err; 4237 4238 err = uverbs_copy_to(attrs, BNXT_RE_ALLOC_PAGE_MMAP_LENGTH, 4239 &length, sizeof(length)); 4240 if (err) 4241 return err; 4242 4243 err = uverbs_copy_to(attrs, BNXT_RE_ALLOC_PAGE_DPI, 4244 &dpi, sizeof(length)); 4245 if (err) 4246 return err; 4247 4248 return 0; 4249 } 4250 4251 static int alloc_page_obj_cleanup(struct ib_uobject *uobject, 4252 enum rdma_remove_reason why, 4253 struct uverbs_attr_bundle *attrs) 4254 { 4255 struct bnxt_re_user_mmap_entry *entry = uobject->object; 4256 struct bnxt_re_ucontext *uctx = entry->uctx; 4257 4258 switch (entry->mmap_flag) { 4259 case BNXT_RE_MMAP_WC_DB: 4260 if (uctx && uctx->wcdpi.dbr) { 4261 struct bnxt_re_dev *rdev = uctx->rdev; 4262 4263 bnxt_qplib_dealloc_dpi(&rdev->qplib_res, &uctx->wcdpi); 4264 uctx->wcdpi.dbr = NULL; 4265 } 4266 break; 4267 default: 4268 goto exit; 4269 } 4270 rdma_user_mmap_entry_remove(&entry->rdma_entry); 4271 exit: 4272 return 0; 4273 } 4274 4275 DECLARE_UVERBS_NAMED_METHOD(BNXT_RE_METHOD_ALLOC_PAGE, 4276 UVERBS_ATTR_IDR(BNXT_RE_ALLOC_PAGE_HANDLE, 4277 BNXT_RE_OBJECT_ALLOC_PAGE, 4278 UVERBS_ACCESS_NEW, 4279 UA_MANDATORY), 4280 UVERBS_ATTR_CONST_IN(BNXT_RE_ALLOC_PAGE_TYPE, 4281 enum bnxt_re_alloc_page_type, 4282 UA_MANDATORY), 4283 UVERBS_ATTR_PTR_OUT(BNXT_RE_ALLOC_PAGE_MMAP_OFFSET, 4284 UVERBS_ATTR_TYPE(u64), 4285 UA_MANDATORY), 4286 UVERBS_ATTR_PTR_OUT(BNXT_RE_ALLOC_PAGE_MMAP_LENGTH, 4287 UVERBS_ATTR_TYPE(u32), 4288 UA_MANDATORY), 4289 UVERBS_ATTR_PTR_OUT(BNXT_RE_ALLOC_PAGE_DPI, 4290 UVERBS_ATTR_TYPE(u32), 4291 UA_MANDATORY)); 4292 4293 DECLARE_UVERBS_NAMED_METHOD_DESTROY(BNXT_RE_METHOD_DESTROY_PAGE, 4294 UVERBS_ATTR_IDR(BNXT_RE_DESTROY_PAGE_HANDLE, 4295 BNXT_RE_OBJECT_ALLOC_PAGE, 4296 UVERBS_ACCESS_DESTROY, 4297 UA_MANDATORY)); 4298 4299 DECLARE_UVERBS_NAMED_OBJECT(BNXT_RE_OBJECT_ALLOC_PAGE, 4300 UVERBS_TYPE_ALLOC_IDR(alloc_page_obj_cleanup), 4301 &UVERBS_METHOD(BNXT_RE_METHOD_ALLOC_PAGE), 4302 &UVERBS_METHOD(BNXT_RE_METHOD_DESTROY_PAGE)); 4303 4304 const struct uapi_definition bnxt_re_uapi_defs[] = { 4305 UAPI_DEF_CHAIN_OBJ_TREE_NAMED(BNXT_RE_OBJECT_ALLOC_PAGE), 4306 {} 4307 }; 4308