1 /* 2 * Broadcom NetXtreme-E RoCE driver. 3 * 4 * Copyright (c) 2016 - 2017, Broadcom. All rights reserved. The term 5 * Broadcom refers to Broadcom Limited and/or its subsidiaries. 6 * 7 * This software is available to you under a choice of one of two 8 * licenses. You may choose to be licensed under the terms of the GNU 9 * General Public License (GPL) Version 2, available from the file 10 * COPYING in the main directory of this source tree, or the 11 * BSD license below: 12 * 13 * Redistribution and use in source and binary forms, with or without 14 * modification, are permitted provided that the following conditions 15 * are met: 16 * 17 * 1. Redistributions of source code must retain the above copyright 18 * notice, this list of conditions and the following disclaimer. 19 * 2. Redistributions in binary form must reproduce the above copyright 20 * notice, this list of conditions and the following disclaimer in 21 * the documentation and/or other materials provided with the 22 * distribution. 23 * 24 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' 25 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, 26 * THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR 27 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS 28 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 29 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 30 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR 31 * BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, 32 * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE 33 * OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN 34 * IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 35 * 36 * Description: IB Verbs interpreter 37 */ 38 39 #include <linux/interrupt.h> 40 #include <linux/types.h> 41 #include <linux/pci.h> 42 #include <linux/netdevice.h> 43 #include <linux/if_ether.h> 44 45 #include <rdma/ib_verbs.h> 46 #include <rdma/ib_user_verbs.h> 47 #include <rdma/ib_umem.h> 48 #include <rdma/ib_addr.h> 49 #include <rdma/ib_mad.h> 50 #include <rdma/ib_cache.h> 51 #include <rdma/uverbs_ioctl.h> 52 53 #include "bnxt_ulp.h" 54 55 #include "roce_hsi.h" 56 #include "qplib_res.h" 57 #include "qplib_sp.h" 58 #include "qplib_fp.h" 59 #include "qplib_rcfw.h" 60 61 #include "bnxt_re.h" 62 #include "ib_verbs.h" 63 #include <rdma/bnxt_re-abi.h> 64 65 static int __from_ib_access_flags(int iflags) 66 { 67 int qflags = 0; 68 69 if (iflags & IB_ACCESS_LOCAL_WRITE) 70 qflags |= BNXT_QPLIB_ACCESS_LOCAL_WRITE; 71 if (iflags & IB_ACCESS_REMOTE_READ) 72 qflags |= BNXT_QPLIB_ACCESS_REMOTE_READ; 73 if (iflags & IB_ACCESS_REMOTE_WRITE) 74 qflags |= BNXT_QPLIB_ACCESS_REMOTE_WRITE; 75 if (iflags & IB_ACCESS_REMOTE_ATOMIC) 76 qflags |= BNXT_QPLIB_ACCESS_REMOTE_ATOMIC; 77 if (iflags & IB_ACCESS_MW_BIND) 78 qflags |= BNXT_QPLIB_ACCESS_MW_BIND; 79 if (iflags & IB_ZERO_BASED) 80 qflags |= BNXT_QPLIB_ACCESS_ZERO_BASED; 81 if (iflags & IB_ACCESS_ON_DEMAND) 82 qflags |= BNXT_QPLIB_ACCESS_ON_DEMAND; 83 return qflags; 84 }; 85 86 static enum ib_access_flags __to_ib_access_flags(int qflags) 87 { 88 enum ib_access_flags iflags = 0; 89 90 if (qflags & BNXT_QPLIB_ACCESS_LOCAL_WRITE) 91 iflags |= IB_ACCESS_LOCAL_WRITE; 92 if (qflags & BNXT_QPLIB_ACCESS_REMOTE_WRITE) 93 iflags |= IB_ACCESS_REMOTE_WRITE; 94 if (qflags & BNXT_QPLIB_ACCESS_REMOTE_READ) 95 iflags |= IB_ACCESS_REMOTE_READ; 96 if (qflags & BNXT_QPLIB_ACCESS_REMOTE_ATOMIC) 97 iflags |= IB_ACCESS_REMOTE_ATOMIC; 98 if (qflags & BNXT_QPLIB_ACCESS_MW_BIND) 99 iflags |= IB_ACCESS_MW_BIND; 100 if (qflags & BNXT_QPLIB_ACCESS_ZERO_BASED) 101 iflags |= IB_ZERO_BASED; 102 if (qflags & BNXT_QPLIB_ACCESS_ON_DEMAND) 103 iflags |= IB_ACCESS_ON_DEMAND; 104 return iflags; 105 }; 106 107 static int bnxt_re_build_sgl(struct ib_sge *ib_sg_list, 108 struct bnxt_qplib_sge *sg_list, int num) 109 { 110 int i, total = 0; 111 112 for (i = 0; i < num; i++) { 113 sg_list[i].addr = ib_sg_list[i].addr; 114 sg_list[i].lkey = ib_sg_list[i].lkey; 115 sg_list[i].size = ib_sg_list[i].length; 116 total += sg_list[i].size; 117 } 118 return total; 119 } 120 121 /* Device */ 122 int bnxt_re_query_device(struct ib_device *ibdev, 123 struct ib_device_attr *ib_attr, 124 struct ib_udata *udata) 125 { 126 struct bnxt_re_dev *rdev = to_bnxt_re_dev(ibdev, ibdev); 127 struct bnxt_qplib_dev_attr *dev_attr = &rdev->dev_attr; 128 129 memset(ib_attr, 0, sizeof(*ib_attr)); 130 memcpy(&ib_attr->fw_ver, dev_attr->fw_ver, 131 min(sizeof(dev_attr->fw_ver), 132 sizeof(ib_attr->fw_ver))); 133 bnxt_qplib_get_guid(rdev->netdev->dev_addr, 134 (u8 *)&ib_attr->sys_image_guid); 135 ib_attr->max_mr_size = BNXT_RE_MAX_MR_SIZE; 136 ib_attr->page_size_cap = BNXT_RE_PAGE_SIZE_4K | BNXT_RE_PAGE_SIZE_2M; 137 138 ib_attr->vendor_id = rdev->en_dev->pdev->vendor; 139 ib_attr->vendor_part_id = rdev->en_dev->pdev->device; 140 ib_attr->hw_ver = rdev->en_dev->pdev->subsystem_device; 141 ib_attr->max_qp = dev_attr->max_qp; 142 ib_attr->max_qp_wr = dev_attr->max_qp_wqes; 143 ib_attr->device_cap_flags = 144 IB_DEVICE_CURR_QP_STATE_MOD 145 | IB_DEVICE_RC_RNR_NAK_GEN 146 | IB_DEVICE_SHUTDOWN_PORT 147 | IB_DEVICE_SYS_IMAGE_GUID 148 | IB_DEVICE_LOCAL_DMA_LKEY 149 | IB_DEVICE_RESIZE_MAX_WR 150 | IB_DEVICE_PORT_ACTIVE_EVENT 151 | IB_DEVICE_N_NOTIFY_CQ 152 | IB_DEVICE_MEM_WINDOW 153 | IB_DEVICE_MEM_WINDOW_TYPE_2B 154 | IB_DEVICE_MEM_MGT_EXTENSIONS; 155 ib_attr->max_send_sge = dev_attr->max_qp_sges; 156 ib_attr->max_recv_sge = dev_attr->max_qp_sges; 157 ib_attr->max_sge_rd = dev_attr->max_qp_sges; 158 ib_attr->max_cq = dev_attr->max_cq; 159 ib_attr->max_cqe = dev_attr->max_cq_wqes; 160 ib_attr->max_mr = dev_attr->max_mr; 161 ib_attr->max_pd = dev_attr->max_pd; 162 ib_attr->max_qp_rd_atom = dev_attr->max_qp_rd_atom; 163 ib_attr->max_qp_init_rd_atom = dev_attr->max_qp_init_rd_atom; 164 ib_attr->atomic_cap = IB_ATOMIC_NONE; 165 ib_attr->masked_atomic_cap = IB_ATOMIC_NONE; 166 167 ib_attr->max_ee_rd_atom = 0; 168 ib_attr->max_res_rd_atom = 0; 169 ib_attr->max_ee_init_rd_atom = 0; 170 ib_attr->max_ee = 0; 171 ib_attr->max_rdd = 0; 172 ib_attr->max_mw = dev_attr->max_mw; 173 ib_attr->max_raw_ipv6_qp = 0; 174 ib_attr->max_raw_ethy_qp = dev_attr->max_raw_ethy_qp; 175 ib_attr->max_mcast_grp = 0; 176 ib_attr->max_mcast_qp_attach = 0; 177 ib_attr->max_total_mcast_qp_attach = 0; 178 ib_attr->max_ah = dev_attr->max_ah; 179 180 ib_attr->max_fmr = 0; 181 ib_attr->max_map_per_fmr = 0; 182 183 ib_attr->max_srq = dev_attr->max_srq; 184 ib_attr->max_srq_wr = dev_attr->max_srq_wqes; 185 ib_attr->max_srq_sge = dev_attr->max_srq_sges; 186 187 ib_attr->max_fast_reg_page_list_len = MAX_PBL_LVL_1_PGS; 188 189 ib_attr->max_pkeys = 1; 190 ib_attr->local_ca_ack_delay = BNXT_RE_DEFAULT_ACK_DELAY; 191 return 0; 192 } 193 194 /* Port */ 195 int bnxt_re_query_port(struct ib_device *ibdev, u8 port_num, 196 struct ib_port_attr *port_attr) 197 { 198 struct bnxt_re_dev *rdev = to_bnxt_re_dev(ibdev, ibdev); 199 struct bnxt_qplib_dev_attr *dev_attr = &rdev->dev_attr; 200 201 memset(port_attr, 0, sizeof(*port_attr)); 202 203 if (netif_running(rdev->netdev) && netif_carrier_ok(rdev->netdev)) { 204 port_attr->state = IB_PORT_ACTIVE; 205 port_attr->phys_state = IB_PORT_PHYS_STATE_LINK_UP; 206 } else { 207 port_attr->state = IB_PORT_DOWN; 208 port_attr->phys_state = IB_PORT_PHYS_STATE_DISABLED; 209 } 210 port_attr->max_mtu = IB_MTU_4096; 211 port_attr->active_mtu = iboe_get_mtu(rdev->netdev->mtu); 212 port_attr->gid_tbl_len = dev_attr->max_sgid; 213 port_attr->port_cap_flags = IB_PORT_CM_SUP | IB_PORT_REINIT_SUP | 214 IB_PORT_DEVICE_MGMT_SUP | 215 IB_PORT_VENDOR_CLASS_SUP; 216 port_attr->ip_gids = true; 217 218 port_attr->max_msg_sz = (u32)BNXT_RE_MAX_MR_SIZE_LOW; 219 port_attr->bad_pkey_cntr = 0; 220 port_attr->qkey_viol_cntr = 0; 221 port_attr->pkey_tbl_len = dev_attr->max_pkey; 222 port_attr->lid = 0; 223 port_attr->sm_lid = 0; 224 port_attr->lmc = 0; 225 port_attr->max_vl_num = 4; 226 port_attr->sm_sl = 0; 227 port_attr->subnet_timeout = 0; 228 port_attr->init_type_reply = 0; 229 port_attr->active_speed = rdev->active_speed; 230 port_attr->active_width = rdev->active_width; 231 232 return 0; 233 } 234 235 int bnxt_re_get_port_immutable(struct ib_device *ibdev, u8 port_num, 236 struct ib_port_immutable *immutable) 237 { 238 struct ib_port_attr port_attr; 239 240 if (bnxt_re_query_port(ibdev, port_num, &port_attr)) 241 return -EINVAL; 242 243 immutable->pkey_tbl_len = port_attr.pkey_tbl_len; 244 immutable->gid_tbl_len = port_attr.gid_tbl_len; 245 immutable->core_cap_flags = RDMA_CORE_PORT_IBA_ROCE; 246 immutable->core_cap_flags |= RDMA_CORE_CAP_PROT_ROCE_UDP_ENCAP; 247 immutable->max_mad_size = IB_MGMT_MAD_SIZE; 248 return 0; 249 } 250 251 void bnxt_re_query_fw_str(struct ib_device *ibdev, char *str) 252 { 253 struct bnxt_re_dev *rdev = to_bnxt_re_dev(ibdev, ibdev); 254 255 snprintf(str, IB_FW_VERSION_NAME_MAX, "%d.%d.%d.%d", 256 rdev->dev_attr.fw_ver[0], rdev->dev_attr.fw_ver[1], 257 rdev->dev_attr.fw_ver[2], rdev->dev_attr.fw_ver[3]); 258 } 259 260 int bnxt_re_query_pkey(struct ib_device *ibdev, u8 port_num, 261 u16 index, u16 *pkey) 262 { 263 struct bnxt_re_dev *rdev = to_bnxt_re_dev(ibdev, ibdev); 264 265 /* Ignore port_num */ 266 267 memset(pkey, 0, sizeof(*pkey)); 268 return bnxt_qplib_get_pkey(&rdev->qplib_res, 269 &rdev->qplib_res.pkey_tbl, index, pkey); 270 } 271 272 int bnxt_re_query_gid(struct ib_device *ibdev, u8 port_num, 273 int index, union ib_gid *gid) 274 { 275 struct bnxt_re_dev *rdev = to_bnxt_re_dev(ibdev, ibdev); 276 int rc = 0; 277 278 /* Ignore port_num */ 279 memset(gid, 0, sizeof(*gid)); 280 rc = bnxt_qplib_get_sgid(&rdev->qplib_res, 281 &rdev->qplib_res.sgid_tbl, index, 282 (struct bnxt_qplib_gid *)gid); 283 return rc; 284 } 285 286 int bnxt_re_del_gid(const struct ib_gid_attr *attr, void **context) 287 { 288 int rc = 0; 289 struct bnxt_re_gid_ctx *ctx, **ctx_tbl; 290 struct bnxt_re_dev *rdev = to_bnxt_re_dev(attr->device, ibdev); 291 struct bnxt_qplib_sgid_tbl *sgid_tbl = &rdev->qplib_res.sgid_tbl; 292 struct bnxt_qplib_gid *gid_to_del; 293 u16 vlan_id = 0xFFFF; 294 295 /* Delete the entry from the hardware */ 296 ctx = *context; 297 if (!ctx) 298 return -EINVAL; 299 300 if (sgid_tbl && sgid_tbl->active) { 301 if (ctx->idx >= sgid_tbl->max) 302 return -EINVAL; 303 gid_to_del = &sgid_tbl->tbl[ctx->idx].gid; 304 vlan_id = sgid_tbl->tbl[ctx->idx].vlan_id; 305 /* DEL_GID is called in WQ context(netdevice_event_work_handler) 306 * or via the ib_unregister_device path. In the former case QP1 307 * may not be destroyed yet, in which case just return as FW 308 * needs that entry to be present and will fail it's deletion. 309 * We could get invoked again after QP1 is destroyed OR get an 310 * ADD_GID call with a different GID value for the same index 311 * where we issue MODIFY_GID cmd to update the GID entry -- TBD 312 */ 313 if (ctx->idx == 0 && 314 rdma_link_local_addr((struct in6_addr *)gid_to_del) && 315 ctx->refcnt == 1 && rdev->qp1_sqp) { 316 dev_dbg(rdev_to_dev(rdev), 317 "Trying to delete GID0 while QP1 is alive\n"); 318 return -EFAULT; 319 } 320 ctx->refcnt--; 321 if (!ctx->refcnt) { 322 rc = bnxt_qplib_del_sgid(sgid_tbl, gid_to_del, 323 vlan_id, true); 324 if (rc) { 325 dev_err(rdev_to_dev(rdev), 326 "Failed to remove GID: %#x", rc); 327 } else { 328 ctx_tbl = sgid_tbl->ctx; 329 ctx_tbl[ctx->idx] = NULL; 330 kfree(ctx); 331 } 332 } 333 } else { 334 return -EINVAL; 335 } 336 return rc; 337 } 338 339 int bnxt_re_add_gid(const struct ib_gid_attr *attr, void **context) 340 { 341 int rc; 342 u32 tbl_idx = 0; 343 u16 vlan_id = 0xFFFF; 344 struct bnxt_re_gid_ctx *ctx, **ctx_tbl; 345 struct bnxt_re_dev *rdev = to_bnxt_re_dev(attr->device, ibdev); 346 struct bnxt_qplib_sgid_tbl *sgid_tbl = &rdev->qplib_res.sgid_tbl; 347 348 rc = rdma_read_gid_l2_fields(attr, &vlan_id, NULL); 349 if (rc) 350 return rc; 351 352 rc = bnxt_qplib_add_sgid(sgid_tbl, (struct bnxt_qplib_gid *)&attr->gid, 353 rdev->qplib_res.netdev->dev_addr, 354 vlan_id, true, &tbl_idx); 355 if (rc == -EALREADY) { 356 ctx_tbl = sgid_tbl->ctx; 357 ctx_tbl[tbl_idx]->refcnt++; 358 *context = ctx_tbl[tbl_idx]; 359 return 0; 360 } 361 362 if (rc < 0) { 363 dev_err(rdev_to_dev(rdev), "Failed to add GID: %#x", rc); 364 return rc; 365 } 366 367 ctx = kmalloc(sizeof(*ctx), GFP_KERNEL); 368 if (!ctx) 369 return -ENOMEM; 370 ctx_tbl = sgid_tbl->ctx; 371 ctx->idx = tbl_idx; 372 ctx->refcnt = 1; 373 ctx_tbl[tbl_idx] = ctx; 374 *context = ctx; 375 376 return rc; 377 } 378 379 enum rdma_link_layer bnxt_re_get_link_layer(struct ib_device *ibdev, 380 u8 port_num) 381 { 382 return IB_LINK_LAYER_ETHERNET; 383 } 384 385 #define BNXT_RE_FENCE_PBL_SIZE DIV_ROUND_UP(BNXT_RE_FENCE_BYTES, PAGE_SIZE) 386 387 static void bnxt_re_create_fence_wqe(struct bnxt_re_pd *pd) 388 { 389 struct bnxt_re_fence_data *fence = &pd->fence; 390 struct ib_mr *ib_mr = &fence->mr->ib_mr; 391 struct bnxt_qplib_swqe *wqe = &fence->bind_wqe; 392 393 memset(wqe, 0, sizeof(*wqe)); 394 wqe->type = BNXT_QPLIB_SWQE_TYPE_BIND_MW; 395 wqe->wr_id = BNXT_QPLIB_FENCE_WRID; 396 wqe->flags |= BNXT_QPLIB_SWQE_FLAGS_SIGNAL_COMP; 397 wqe->flags |= BNXT_QPLIB_SWQE_FLAGS_UC_FENCE; 398 wqe->bind.zero_based = false; 399 wqe->bind.parent_l_key = ib_mr->lkey; 400 wqe->bind.va = (u64)(unsigned long)fence->va; 401 wqe->bind.length = fence->size; 402 wqe->bind.access_cntl = __from_ib_access_flags(IB_ACCESS_REMOTE_READ); 403 wqe->bind.mw_type = SQ_BIND_MW_TYPE_TYPE1; 404 405 /* Save the initial rkey in fence structure for now; 406 * wqe->bind.r_key will be set at (re)bind time. 407 */ 408 fence->bind_rkey = ib_inc_rkey(fence->mw->rkey); 409 } 410 411 static int bnxt_re_bind_fence_mw(struct bnxt_qplib_qp *qplib_qp) 412 { 413 struct bnxt_re_qp *qp = container_of(qplib_qp, struct bnxt_re_qp, 414 qplib_qp); 415 struct ib_pd *ib_pd = qp->ib_qp.pd; 416 struct bnxt_re_pd *pd = container_of(ib_pd, struct bnxt_re_pd, ib_pd); 417 struct bnxt_re_fence_data *fence = &pd->fence; 418 struct bnxt_qplib_swqe *fence_wqe = &fence->bind_wqe; 419 struct bnxt_qplib_swqe wqe; 420 int rc; 421 422 memcpy(&wqe, fence_wqe, sizeof(wqe)); 423 wqe.bind.r_key = fence->bind_rkey; 424 fence->bind_rkey = ib_inc_rkey(fence->bind_rkey); 425 426 dev_dbg(rdev_to_dev(qp->rdev), 427 "Posting bind fence-WQE: rkey: %#x QP: %d PD: %p\n", 428 wqe.bind.r_key, qp->qplib_qp.id, pd); 429 rc = bnxt_qplib_post_send(&qp->qplib_qp, &wqe); 430 if (rc) { 431 dev_err(rdev_to_dev(qp->rdev), "Failed to bind fence-WQE\n"); 432 return rc; 433 } 434 bnxt_qplib_post_send_db(&qp->qplib_qp); 435 436 return rc; 437 } 438 439 static void bnxt_re_destroy_fence_mr(struct bnxt_re_pd *pd) 440 { 441 struct bnxt_re_fence_data *fence = &pd->fence; 442 struct bnxt_re_dev *rdev = pd->rdev; 443 struct device *dev = &rdev->en_dev->pdev->dev; 444 struct bnxt_re_mr *mr = fence->mr; 445 446 if (fence->mw) { 447 bnxt_re_dealloc_mw(fence->mw); 448 fence->mw = NULL; 449 } 450 if (mr) { 451 if (mr->ib_mr.rkey) 452 bnxt_qplib_dereg_mrw(&rdev->qplib_res, &mr->qplib_mr, 453 true); 454 if (mr->ib_mr.lkey) 455 bnxt_qplib_free_mrw(&rdev->qplib_res, &mr->qplib_mr); 456 kfree(mr); 457 fence->mr = NULL; 458 } 459 if (fence->dma_addr) { 460 dma_unmap_single(dev, fence->dma_addr, BNXT_RE_FENCE_BYTES, 461 DMA_BIDIRECTIONAL); 462 fence->dma_addr = 0; 463 } 464 } 465 466 static int bnxt_re_create_fence_mr(struct bnxt_re_pd *pd) 467 { 468 int mr_access_flags = IB_ACCESS_LOCAL_WRITE | IB_ACCESS_MW_BIND; 469 struct bnxt_re_fence_data *fence = &pd->fence; 470 struct bnxt_re_dev *rdev = pd->rdev; 471 struct device *dev = &rdev->en_dev->pdev->dev; 472 struct bnxt_re_mr *mr = NULL; 473 dma_addr_t dma_addr = 0; 474 struct ib_mw *mw; 475 u64 pbl_tbl; 476 int rc; 477 478 dma_addr = dma_map_single(dev, fence->va, BNXT_RE_FENCE_BYTES, 479 DMA_BIDIRECTIONAL); 480 rc = dma_mapping_error(dev, dma_addr); 481 if (rc) { 482 dev_err(rdev_to_dev(rdev), "Failed to dma-map fence-MR-mem\n"); 483 rc = -EIO; 484 fence->dma_addr = 0; 485 goto fail; 486 } 487 fence->dma_addr = dma_addr; 488 489 /* Allocate a MR */ 490 mr = kzalloc(sizeof(*mr), GFP_KERNEL); 491 if (!mr) { 492 rc = -ENOMEM; 493 goto fail; 494 } 495 fence->mr = mr; 496 mr->rdev = rdev; 497 mr->qplib_mr.pd = &pd->qplib_pd; 498 mr->qplib_mr.type = CMDQ_ALLOCATE_MRW_MRW_FLAGS_PMR; 499 mr->qplib_mr.flags = __from_ib_access_flags(mr_access_flags); 500 rc = bnxt_qplib_alloc_mrw(&rdev->qplib_res, &mr->qplib_mr); 501 if (rc) { 502 dev_err(rdev_to_dev(rdev), "Failed to alloc fence-HW-MR\n"); 503 goto fail; 504 } 505 506 /* Register MR */ 507 mr->ib_mr.lkey = mr->qplib_mr.lkey; 508 mr->qplib_mr.va = (u64)(unsigned long)fence->va; 509 mr->qplib_mr.total_size = BNXT_RE_FENCE_BYTES; 510 pbl_tbl = dma_addr; 511 rc = bnxt_qplib_reg_mr(&rdev->qplib_res, &mr->qplib_mr, &pbl_tbl, 512 BNXT_RE_FENCE_PBL_SIZE, false, PAGE_SIZE); 513 if (rc) { 514 dev_err(rdev_to_dev(rdev), "Failed to register fence-MR\n"); 515 goto fail; 516 } 517 mr->ib_mr.rkey = mr->qplib_mr.rkey; 518 519 /* Create a fence MW only for kernel consumers */ 520 mw = bnxt_re_alloc_mw(&pd->ib_pd, IB_MW_TYPE_1, NULL); 521 if (IS_ERR(mw)) { 522 dev_err(rdev_to_dev(rdev), 523 "Failed to create fence-MW for PD: %p\n", pd); 524 rc = PTR_ERR(mw); 525 goto fail; 526 } 527 fence->mw = mw; 528 529 bnxt_re_create_fence_wqe(pd); 530 return 0; 531 532 fail: 533 bnxt_re_destroy_fence_mr(pd); 534 return rc; 535 } 536 537 /* Protection Domains */ 538 void bnxt_re_dealloc_pd(struct ib_pd *ib_pd, struct ib_udata *udata) 539 { 540 struct bnxt_re_pd *pd = container_of(ib_pd, struct bnxt_re_pd, ib_pd); 541 struct bnxt_re_dev *rdev = pd->rdev; 542 543 bnxt_re_destroy_fence_mr(pd); 544 545 if (pd->qplib_pd.id) 546 bnxt_qplib_dealloc_pd(&rdev->qplib_res, &rdev->qplib_res.pd_tbl, 547 &pd->qplib_pd); 548 } 549 550 int bnxt_re_alloc_pd(struct ib_pd *ibpd, struct ib_udata *udata) 551 { 552 struct ib_device *ibdev = ibpd->device; 553 struct bnxt_re_dev *rdev = to_bnxt_re_dev(ibdev, ibdev); 554 struct bnxt_re_ucontext *ucntx = rdma_udata_to_drv_context( 555 udata, struct bnxt_re_ucontext, ib_uctx); 556 struct bnxt_re_pd *pd = container_of(ibpd, struct bnxt_re_pd, ib_pd); 557 int rc; 558 559 pd->rdev = rdev; 560 if (bnxt_qplib_alloc_pd(&rdev->qplib_res.pd_tbl, &pd->qplib_pd)) { 561 dev_err(rdev_to_dev(rdev), "Failed to allocate HW PD"); 562 rc = -ENOMEM; 563 goto fail; 564 } 565 566 if (udata) { 567 struct bnxt_re_pd_resp resp; 568 569 if (!ucntx->dpi.dbr) { 570 /* Allocate DPI in alloc_pd to avoid failing of 571 * ibv_devinfo and family of application when DPIs 572 * are depleted. 573 */ 574 if (bnxt_qplib_alloc_dpi(&rdev->qplib_res.dpi_tbl, 575 &ucntx->dpi, ucntx)) { 576 rc = -ENOMEM; 577 goto dbfail; 578 } 579 } 580 581 resp.pdid = pd->qplib_pd.id; 582 /* Still allow mapping this DBR to the new user PD. */ 583 resp.dpi = ucntx->dpi.dpi; 584 resp.dbr = (u64)ucntx->dpi.umdbr; 585 586 rc = ib_copy_to_udata(udata, &resp, sizeof(resp)); 587 if (rc) { 588 dev_err(rdev_to_dev(rdev), 589 "Failed to copy user response\n"); 590 goto dbfail; 591 } 592 } 593 594 if (!udata) 595 if (bnxt_re_create_fence_mr(pd)) 596 dev_warn(rdev_to_dev(rdev), 597 "Failed to create Fence-MR\n"); 598 return 0; 599 dbfail: 600 bnxt_qplib_dealloc_pd(&rdev->qplib_res, &rdev->qplib_res.pd_tbl, 601 &pd->qplib_pd); 602 fail: 603 return rc; 604 } 605 606 /* Address Handles */ 607 void bnxt_re_destroy_ah(struct ib_ah *ib_ah, u32 flags) 608 { 609 struct bnxt_re_ah *ah = container_of(ib_ah, struct bnxt_re_ah, ib_ah); 610 struct bnxt_re_dev *rdev = ah->rdev; 611 612 bnxt_qplib_destroy_ah(&rdev->qplib_res, &ah->qplib_ah, 613 !(flags & RDMA_DESTROY_AH_SLEEPABLE)); 614 } 615 616 static u8 bnxt_re_stack_to_dev_nw_type(enum rdma_network_type ntype) 617 { 618 u8 nw_type; 619 620 switch (ntype) { 621 case RDMA_NETWORK_IPV4: 622 nw_type = CMDQ_CREATE_AH_TYPE_V2IPV4; 623 break; 624 case RDMA_NETWORK_IPV6: 625 nw_type = CMDQ_CREATE_AH_TYPE_V2IPV6; 626 break; 627 default: 628 nw_type = CMDQ_CREATE_AH_TYPE_V1; 629 break; 630 } 631 return nw_type; 632 } 633 634 int bnxt_re_create_ah(struct ib_ah *ib_ah, struct rdma_ah_attr *ah_attr, 635 u32 flags, struct ib_udata *udata) 636 { 637 struct ib_pd *ib_pd = ib_ah->pd; 638 struct bnxt_re_pd *pd = container_of(ib_pd, struct bnxt_re_pd, ib_pd); 639 const struct ib_global_route *grh = rdma_ah_read_grh(ah_attr); 640 struct bnxt_re_dev *rdev = pd->rdev; 641 const struct ib_gid_attr *sgid_attr; 642 struct bnxt_re_ah *ah = container_of(ib_ah, struct bnxt_re_ah, ib_ah); 643 u8 nw_type; 644 int rc; 645 646 if (!(rdma_ah_get_ah_flags(ah_attr) & IB_AH_GRH)) { 647 dev_err(rdev_to_dev(rdev), "Failed to alloc AH: GRH not set"); 648 return -EINVAL; 649 } 650 651 ah->rdev = rdev; 652 ah->qplib_ah.pd = &pd->qplib_pd; 653 654 /* Supply the configuration for the HW */ 655 memcpy(ah->qplib_ah.dgid.data, grh->dgid.raw, 656 sizeof(union ib_gid)); 657 /* 658 * If RoCE V2 is enabled, stack will have two entries for 659 * each GID entry. Avoiding this duplicte entry in HW. Dividing 660 * the GID index by 2 for RoCE V2 661 */ 662 ah->qplib_ah.sgid_index = grh->sgid_index / 2; 663 ah->qplib_ah.host_sgid_index = grh->sgid_index; 664 ah->qplib_ah.traffic_class = grh->traffic_class; 665 ah->qplib_ah.flow_label = grh->flow_label; 666 ah->qplib_ah.hop_limit = grh->hop_limit; 667 ah->qplib_ah.sl = rdma_ah_get_sl(ah_attr); 668 669 sgid_attr = grh->sgid_attr; 670 /* Get network header type for this GID */ 671 nw_type = rdma_gid_attr_network_type(sgid_attr); 672 ah->qplib_ah.nw_type = bnxt_re_stack_to_dev_nw_type(nw_type); 673 674 memcpy(ah->qplib_ah.dmac, ah_attr->roce.dmac, ETH_ALEN); 675 rc = bnxt_qplib_create_ah(&rdev->qplib_res, &ah->qplib_ah, 676 !(flags & RDMA_CREATE_AH_SLEEPABLE)); 677 if (rc) { 678 dev_err(rdev_to_dev(rdev), "Failed to allocate HW AH"); 679 return rc; 680 } 681 682 /* Write AVID to shared page. */ 683 if (udata) { 684 struct bnxt_re_ucontext *uctx = rdma_udata_to_drv_context( 685 udata, struct bnxt_re_ucontext, ib_uctx); 686 unsigned long flag; 687 u32 *wrptr; 688 689 spin_lock_irqsave(&uctx->sh_lock, flag); 690 wrptr = (u32 *)(uctx->shpg + BNXT_RE_AVID_OFFT); 691 *wrptr = ah->qplib_ah.id; 692 wmb(); /* make sure cache is updated. */ 693 spin_unlock_irqrestore(&uctx->sh_lock, flag); 694 } 695 696 return 0; 697 } 698 699 int bnxt_re_modify_ah(struct ib_ah *ib_ah, struct rdma_ah_attr *ah_attr) 700 { 701 return 0; 702 } 703 704 int bnxt_re_query_ah(struct ib_ah *ib_ah, struct rdma_ah_attr *ah_attr) 705 { 706 struct bnxt_re_ah *ah = container_of(ib_ah, struct bnxt_re_ah, ib_ah); 707 708 ah_attr->type = ib_ah->type; 709 rdma_ah_set_sl(ah_attr, ah->qplib_ah.sl); 710 memcpy(ah_attr->roce.dmac, ah->qplib_ah.dmac, ETH_ALEN); 711 rdma_ah_set_grh(ah_attr, NULL, 0, 712 ah->qplib_ah.host_sgid_index, 713 0, ah->qplib_ah.traffic_class); 714 rdma_ah_set_dgid_raw(ah_attr, ah->qplib_ah.dgid.data); 715 rdma_ah_set_port_num(ah_attr, 1); 716 rdma_ah_set_static_rate(ah_attr, 0); 717 return 0; 718 } 719 720 unsigned long bnxt_re_lock_cqs(struct bnxt_re_qp *qp) 721 __acquires(&qp->scq->cq_lock) __acquires(&qp->rcq->cq_lock) 722 { 723 unsigned long flags; 724 725 spin_lock_irqsave(&qp->scq->cq_lock, flags); 726 if (qp->rcq != qp->scq) 727 spin_lock(&qp->rcq->cq_lock); 728 else 729 __acquire(&qp->rcq->cq_lock); 730 731 return flags; 732 } 733 734 void bnxt_re_unlock_cqs(struct bnxt_re_qp *qp, 735 unsigned long flags) 736 __releases(&qp->scq->cq_lock) __releases(&qp->rcq->cq_lock) 737 { 738 if (qp->rcq != qp->scq) 739 spin_unlock(&qp->rcq->cq_lock); 740 else 741 __release(&qp->rcq->cq_lock); 742 spin_unlock_irqrestore(&qp->scq->cq_lock, flags); 743 } 744 745 /* Queue Pairs */ 746 int bnxt_re_destroy_qp(struct ib_qp *ib_qp, struct ib_udata *udata) 747 { 748 struct bnxt_re_qp *qp = container_of(ib_qp, struct bnxt_re_qp, ib_qp); 749 struct bnxt_re_dev *rdev = qp->rdev; 750 unsigned int flags; 751 int rc; 752 753 bnxt_qplib_flush_cqn_wq(&qp->qplib_qp); 754 rc = bnxt_qplib_destroy_qp(&rdev->qplib_res, &qp->qplib_qp); 755 if (rc) { 756 dev_err(rdev_to_dev(rdev), "Failed to destroy HW QP"); 757 return rc; 758 } 759 760 if (rdma_is_kernel_res(&qp->ib_qp.res)) { 761 flags = bnxt_re_lock_cqs(qp); 762 bnxt_qplib_clean_qp(&qp->qplib_qp); 763 bnxt_re_unlock_cqs(qp, flags); 764 } 765 766 bnxt_qplib_free_qp_res(&rdev->qplib_res, &qp->qplib_qp); 767 768 if (ib_qp->qp_type == IB_QPT_GSI && rdev->qp1_sqp) { 769 bnxt_qplib_destroy_ah(&rdev->qplib_res, &rdev->sqp_ah->qplib_ah, 770 false); 771 772 bnxt_qplib_clean_qp(&qp->qplib_qp); 773 rc = bnxt_qplib_destroy_qp(&rdev->qplib_res, 774 &rdev->qp1_sqp->qplib_qp); 775 if (rc) { 776 dev_err(rdev_to_dev(rdev), 777 "Failed to destroy Shadow QP"); 778 return rc; 779 } 780 bnxt_qplib_free_qp_res(&rdev->qplib_res, 781 &rdev->qp1_sqp->qplib_qp); 782 mutex_lock(&rdev->qp_lock); 783 list_del(&rdev->qp1_sqp->list); 784 atomic_dec(&rdev->qp_count); 785 mutex_unlock(&rdev->qp_lock); 786 787 kfree(rdev->sqp_ah); 788 kfree(rdev->qp1_sqp); 789 rdev->qp1_sqp = NULL; 790 rdev->sqp_ah = NULL; 791 } 792 793 ib_umem_release(qp->rumem); 794 ib_umem_release(qp->sumem); 795 796 mutex_lock(&rdev->qp_lock); 797 list_del(&qp->list); 798 atomic_dec(&rdev->qp_count); 799 mutex_unlock(&rdev->qp_lock); 800 kfree(qp); 801 return 0; 802 } 803 804 static u8 __from_ib_qp_type(enum ib_qp_type type) 805 { 806 switch (type) { 807 case IB_QPT_GSI: 808 return CMDQ_CREATE_QP1_TYPE_GSI; 809 case IB_QPT_RC: 810 return CMDQ_CREATE_QP_TYPE_RC; 811 case IB_QPT_UD: 812 return CMDQ_CREATE_QP_TYPE_UD; 813 default: 814 return IB_QPT_MAX; 815 } 816 } 817 818 static int bnxt_re_init_user_qp(struct bnxt_re_dev *rdev, struct bnxt_re_pd *pd, 819 struct bnxt_re_qp *qp, struct ib_udata *udata) 820 { 821 struct bnxt_re_qp_req ureq; 822 struct bnxt_qplib_qp *qplib_qp = &qp->qplib_qp; 823 struct ib_umem *umem; 824 int bytes = 0, psn_sz; 825 struct bnxt_re_ucontext *cntx = rdma_udata_to_drv_context( 826 udata, struct bnxt_re_ucontext, ib_uctx); 827 828 if (ib_copy_from_udata(&ureq, udata, sizeof(ureq))) 829 return -EFAULT; 830 831 bytes = (qplib_qp->sq.max_wqe * BNXT_QPLIB_MAX_SQE_ENTRY_SIZE); 832 /* Consider mapping PSN search memory only for RC QPs. */ 833 if (qplib_qp->type == CMDQ_CREATE_QP_TYPE_RC) { 834 psn_sz = bnxt_qplib_is_chip_gen_p5(&rdev->chip_ctx) ? 835 sizeof(struct sq_psn_search_ext) : 836 sizeof(struct sq_psn_search); 837 bytes += (qplib_qp->sq.max_wqe * psn_sz); 838 } 839 bytes = PAGE_ALIGN(bytes); 840 umem = ib_umem_get(udata, ureq.qpsva, bytes, IB_ACCESS_LOCAL_WRITE); 841 if (IS_ERR(umem)) 842 return PTR_ERR(umem); 843 844 qp->sumem = umem; 845 qplib_qp->sq.sg_info.sglist = umem->sg_head.sgl; 846 qplib_qp->sq.sg_info.npages = ib_umem_num_pages(umem); 847 qplib_qp->sq.sg_info.nmap = umem->nmap; 848 qplib_qp->qp_handle = ureq.qp_handle; 849 850 if (!qp->qplib_qp.srq) { 851 bytes = (qplib_qp->rq.max_wqe * BNXT_QPLIB_MAX_RQE_ENTRY_SIZE); 852 bytes = PAGE_ALIGN(bytes); 853 umem = ib_umem_get(udata, ureq.qprva, bytes, 854 IB_ACCESS_LOCAL_WRITE); 855 if (IS_ERR(umem)) 856 goto rqfail; 857 qp->rumem = umem; 858 qplib_qp->rq.sg_info.sglist = umem->sg_head.sgl; 859 qplib_qp->rq.sg_info.npages = ib_umem_num_pages(umem); 860 qplib_qp->rq.sg_info.nmap = umem->nmap; 861 } 862 863 qplib_qp->dpi = &cntx->dpi; 864 return 0; 865 rqfail: 866 ib_umem_release(qp->sumem); 867 qp->sumem = NULL; 868 memset(&qplib_qp->sq.sg_info, 0, sizeof(qplib_qp->sq.sg_info)); 869 870 return PTR_ERR(umem); 871 } 872 873 static struct bnxt_re_ah *bnxt_re_create_shadow_qp_ah 874 (struct bnxt_re_pd *pd, 875 struct bnxt_qplib_res *qp1_res, 876 struct bnxt_qplib_qp *qp1_qp) 877 { 878 struct bnxt_re_dev *rdev = pd->rdev; 879 struct bnxt_re_ah *ah; 880 union ib_gid sgid; 881 int rc; 882 883 ah = kzalloc(sizeof(*ah), GFP_KERNEL); 884 if (!ah) 885 return NULL; 886 887 ah->rdev = rdev; 888 ah->qplib_ah.pd = &pd->qplib_pd; 889 890 rc = bnxt_re_query_gid(&rdev->ibdev, 1, 0, &sgid); 891 if (rc) 892 goto fail; 893 894 /* supply the dgid data same as sgid */ 895 memcpy(ah->qplib_ah.dgid.data, &sgid.raw, 896 sizeof(union ib_gid)); 897 ah->qplib_ah.sgid_index = 0; 898 899 ah->qplib_ah.traffic_class = 0; 900 ah->qplib_ah.flow_label = 0; 901 ah->qplib_ah.hop_limit = 1; 902 ah->qplib_ah.sl = 0; 903 /* Have DMAC same as SMAC */ 904 ether_addr_copy(ah->qplib_ah.dmac, rdev->netdev->dev_addr); 905 906 rc = bnxt_qplib_create_ah(&rdev->qplib_res, &ah->qplib_ah, false); 907 if (rc) { 908 dev_err(rdev_to_dev(rdev), 909 "Failed to allocate HW AH for Shadow QP"); 910 goto fail; 911 } 912 913 return ah; 914 915 fail: 916 kfree(ah); 917 return NULL; 918 } 919 920 static struct bnxt_re_qp *bnxt_re_create_shadow_qp 921 (struct bnxt_re_pd *pd, 922 struct bnxt_qplib_res *qp1_res, 923 struct bnxt_qplib_qp *qp1_qp) 924 { 925 struct bnxt_re_dev *rdev = pd->rdev; 926 struct bnxt_re_qp *qp; 927 int rc; 928 929 qp = kzalloc(sizeof(*qp), GFP_KERNEL); 930 if (!qp) 931 return NULL; 932 933 qp->rdev = rdev; 934 935 /* Initialize the shadow QP structure from the QP1 values */ 936 ether_addr_copy(qp->qplib_qp.smac, rdev->netdev->dev_addr); 937 938 qp->qplib_qp.pd = &pd->qplib_pd; 939 qp->qplib_qp.qp_handle = (u64)(unsigned long)(&qp->qplib_qp); 940 qp->qplib_qp.type = IB_QPT_UD; 941 942 qp->qplib_qp.max_inline_data = 0; 943 qp->qplib_qp.sig_type = true; 944 945 /* Shadow QP SQ depth should be same as QP1 RQ depth */ 946 qp->qplib_qp.sq.max_wqe = qp1_qp->rq.max_wqe; 947 qp->qplib_qp.sq.max_sge = 2; 948 /* Q full delta can be 1 since it is internal QP */ 949 qp->qplib_qp.sq.q_full_delta = 1; 950 951 qp->qplib_qp.scq = qp1_qp->scq; 952 qp->qplib_qp.rcq = qp1_qp->rcq; 953 954 qp->qplib_qp.rq.max_wqe = qp1_qp->rq.max_wqe; 955 qp->qplib_qp.rq.max_sge = qp1_qp->rq.max_sge; 956 /* Q full delta can be 1 since it is internal QP */ 957 qp->qplib_qp.rq.q_full_delta = 1; 958 959 qp->qplib_qp.mtu = qp1_qp->mtu; 960 961 qp->qplib_qp.sq_hdr_buf_size = 0; 962 qp->qplib_qp.rq_hdr_buf_size = BNXT_QPLIB_MAX_GRH_HDR_SIZE_IPV6; 963 qp->qplib_qp.dpi = &rdev->dpi_privileged; 964 965 rc = bnxt_qplib_create_qp(qp1_res, &qp->qplib_qp); 966 if (rc) 967 goto fail; 968 969 rdev->sqp_id = qp->qplib_qp.id; 970 971 spin_lock_init(&qp->sq_lock); 972 INIT_LIST_HEAD(&qp->list); 973 mutex_lock(&rdev->qp_lock); 974 list_add_tail(&qp->list, &rdev->qp_list); 975 atomic_inc(&rdev->qp_count); 976 mutex_unlock(&rdev->qp_lock); 977 return qp; 978 fail: 979 kfree(qp); 980 return NULL; 981 } 982 983 struct ib_qp *bnxt_re_create_qp(struct ib_pd *ib_pd, 984 struct ib_qp_init_attr *qp_init_attr, 985 struct ib_udata *udata) 986 { 987 struct bnxt_re_pd *pd = container_of(ib_pd, struct bnxt_re_pd, ib_pd); 988 struct bnxt_re_dev *rdev = pd->rdev; 989 struct bnxt_qplib_dev_attr *dev_attr = &rdev->dev_attr; 990 struct bnxt_re_qp *qp; 991 struct bnxt_re_cq *cq; 992 struct bnxt_re_srq *srq; 993 int rc, entries; 994 995 if ((qp_init_attr->cap.max_send_wr > dev_attr->max_qp_wqes) || 996 (qp_init_attr->cap.max_recv_wr > dev_attr->max_qp_wqes) || 997 (qp_init_attr->cap.max_send_sge > dev_attr->max_qp_sges) || 998 (qp_init_attr->cap.max_recv_sge > dev_attr->max_qp_sges) || 999 (qp_init_attr->cap.max_inline_data > dev_attr->max_inline_data)) 1000 return ERR_PTR(-EINVAL); 1001 1002 qp = kzalloc(sizeof(*qp), GFP_KERNEL); 1003 if (!qp) 1004 return ERR_PTR(-ENOMEM); 1005 1006 qp->rdev = rdev; 1007 ether_addr_copy(qp->qplib_qp.smac, rdev->netdev->dev_addr); 1008 qp->qplib_qp.pd = &pd->qplib_pd; 1009 qp->qplib_qp.qp_handle = (u64)(unsigned long)(&qp->qplib_qp); 1010 qp->qplib_qp.type = __from_ib_qp_type(qp_init_attr->qp_type); 1011 1012 if (qp_init_attr->qp_type == IB_QPT_GSI && 1013 bnxt_qplib_is_chip_gen_p5(&rdev->chip_ctx)) 1014 qp->qplib_qp.type = CMDQ_CREATE_QP_TYPE_GSI; 1015 if (qp->qplib_qp.type == IB_QPT_MAX) { 1016 dev_err(rdev_to_dev(rdev), "QP type 0x%x not supported", 1017 qp->qplib_qp.type); 1018 rc = -EINVAL; 1019 goto fail; 1020 } 1021 1022 qp->qplib_qp.max_inline_data = qp_init_attr->cap.max_inline_data; 1023 qp->qplib_qp.sig_type = ((qp_init_attr->sq_sig_type == 1024 IB_SIGNAL_ALL_WR) ? true : false); 1025 1026 qp->qplib_qp.sq.max_sge = qp_init_attr->cap.max_send_sge; 1027 if (qp->qplib_qp.sq.max_sge > dev_attr->max_qp_sges) 1028 qp->qplib_qp.sq.max_sge = dev_attr->max_qp_sges; 1029 1030 if (qp_init_attr->send_cq) { 1031 cq = container_of(qp_init_attr->send_cq, struct bnxt_re_cq, 1032 ib_cq); 1033 if (!cq) { 1034 dev_err(rdev_to_dev(rdev), "Send CQ not found"); 1035 rc = -EINVAL; 1036 goto fail; 1037 } 1038 qp->qplib_qp.scq = &cq->qplib_cq; 1039 qp->scq = cq; 1040 } 1041 1042 if (qp_init_attr->recv_cq) { 1043 cq = container_of(qp_init_attr->recv_cq, struct bnxt_re_cq, 1044 ib_cq); 1045 if (!cq) { 1046 dev_err(rdev_to_dev(rdev), "Receive CQ not found"); 1047 rc = -EINVAL; 1048 goto fail; 1049 } 1050 qp->qplib_qp.rcq = &cq->qplib_cq; 1051 qp->rcq = cq; 1052 } 1053 1054 if (qp_init_attr->srq) { 1055 srq = container_of(qp_init_attr->srq, struct bnxt_re_srq, 1056 ib_srq); 1057 if (!srq) { 1058 dev_err(rdev_to_dev(rdev), "SRQ not found"); 1059 rc = -EINVAL; 1060 goto fail; 1061 } 1062 qp->qplib_qp.srq = &srq->qplib_srq; 1063 qp->qplib_qp.rq.max_wqe = 0; 1064 } else { 1065 /* Allocate 1 more than what's provided so posting max doesn't 1066 * mean empty 1067 */ 1068 entries = roundup_pow_of_two(qp_init_attr->cap.max_recv_wr + 1); 1069 qp->qplib_qp.rq.max_wqe = min_t(u32, entries, 1070 dev_attr->max_qp_wqes + 1); 1071 1072 qp->qplib_qp.rq.q_full_delta = qp->qplib_qp.rq.max_wqe - 1073 qp_init_attr->cap.max_recv_wr; 1074 1075 qp->qplib_qp.rq.max_sge = qp_init_attr->cap.max_recv_sge; 1076 if (qp->qplib_qp.rq.max_sge > dev_attr->max_qp_sges) 1077 qp->qplib_qp.rq.max_sge = dev_attr->max_qp_sges; 1078 } 1079 1080 qp->qplib_qp.mtu = ib_mtu_enum_to_int(iboe_get_mtu(rdev->netdev->mtu)); 1081 1082 if (qp_init_attr->qp_type == IB_QPT_GSI && 1083 !(bnxt_qplib_is_chip_gen_p5(&rdev->chip_ctx))) { 1084 /* Allocate 1 more than what's provided */ 1085 entries = roundup_pow_of_two(qp_init_attr->cap.max_send_wr + 1); 1086 qp->qplib_qp.sq.max_wqe = min_t(u32, entries, 1087 dev_attr->max_qp_wqes + 1); 1088 qp->qplib_qp.sq.q_full_delta = qp->qplib_qp.sq.max_wqe - 1089 qp_init_attr->cap.max_send_wr; 1090 qp->qplib_qp.rq.max_sge = dev_attr->max_qp_sges; 1091 if (qp->qplib_qp.rq.max_sge > dev_attr->max_qp_sges) 1092 qp->qplib_qp.rq.max_sge = dev_attr->max_qp_sges; 1093 qp->qplib_qp.sq.max_sge++; 1094 if (qp->qplib_qp.sq.max_sge > dev_attr->max_qp_sges) 1095 qp->qplib_qp.sq.max_sge = dev_attr->max_qp_sges; 1096 1097 qp->qplib_qp.rq_hdr_buf_size = 1098 BNXT_QPLIB_MAX_QP1_RQ_HDR_SIZE_V2; 1099 1100 qp->qplib_qp.sq_hdr_buf_size = 1101 BNXT_QPLIB_MAX_QP1_SQ_HDR_SIZE_V2; 1102 qp->qplib_qp.dpi = &rdev->dpi_privileged; 1103 rc = bnxt_qplib_create_qp1(&rdev->qplib_res, &qp->qplib_qp); 1104 if (rc) { 1105 dev_err(rdev_to_dev(rdev), "Failed to create HW QP1"); 1106 goto fail; 1107 } 1108 /* Create a shadow QP to handle the QP1 traffic */ 1109 rdev->qp1_sqp = bnxt_re_create_shadow_qp(pd, &rdev->qplib_res, 1110 &qp->qplib_qp); 1111 if (!rdev->qp1_sqp) { 1112 rc = -EINVAL; 1113 dev_err(rdev_to_dev(rdev), 1114 "Failed to create Shadow QP for QP1"); 1115 goto qp_destroy; 1116 } 1117 rdev->sqp_ah = bnxt_re_create_shadow_qp_ah(pd, &rdev->qplib_res, 1118 &qp->qplib_qp); 1119 if (!rdev->sqp_ah) { 1120 bnxt_qplib_destroy_qp(&rdev->qplib_res, 1121 &rdev->qp1_sqp->qplib_qp); 1122 rc = -EINVAL; 1123 dev_err(rdev_to_dev(rdev), 1124 "Failed to create AH entry for ShadowQP"); 1125 goto qp_destroy; 1126 } 1127 1128 } else { 1129 /* Allocate 128 + 1 more than what's provided */ 1130 entries = roundup_pow_of_two(qp_init_attr->cap.max_send_wr + 1131 BNXT_QPLIB_RESERVED_QP_WRS + 1); 1132 qp->qplib_qp.sq.max_wqe = min_t(u32, entries, 1133 dev_attr->max_qp_wqes + 1134 BNXT_QPLIB_RESERVED_QP_WRS + 1); 1135 qp->qplib_qp.sq.q_full_delta = BNXT_QPLIB_RESERVED_QP_WRS + 1; 1136 1137 /* 1138 * Reserving one slot for Phantom WQE. Application can 1139 * post one extra entry in this case. But allowing this to avoid 1140 * unexpected Queue full condition 1141 */ 1142 1143 qp->qplib_qp.sq.q_full_delta -= 1; 1144 1145 qp->qplib_qp.max_rd_atomic = dev_attr->max_qp_rd_atom; 1146 qp->qplib_qp.max_dest_rd_atomic = dev_attr->max_qp_init_rd_atom; 1147 if (udata) { 1148 rc = bnxt_re_init_user_qp(rdev, pd, qp, udata); 1149 if (rc) 1150 goto fail; 1151 } else { 1152 qp->qplib_qp.dpi = &rdev->dpi_privileged; 1153 } 1154 1155 rc = bnxt_qplib_create_qp(&rdev->qplib_res, &qp->qplib_qp); 1156 if (rc) { 1157 dev_err(rdev_to_dev(rdev), "Failed to create HW QP"); 1158 goto free_umem; 1159 } 1160 } 1161 1162 qp->ib_qp.qp_num = qp->qplib_qp.id; 1163 spin_lock_init(&qp->sq_lock); 1164 spin_lock_init(&qp->rq_lock); 1165 1166 if (udata) { 1167 struct bnxt_re_qp_resp resp; 1168 1169 resp.qpid = qp->ib_qp.qp_num; 1170 resp.rsvd = 0; 1171 rc = ib_copy_to_udata(udata, &resp, sizeof(resp)); 1172 if (rc) { 1173 dev_err(rdev_to_dev(rdev), "Failed to copy QP udata"); 1174 goto qp_destroy; 1175 } 1176 } 1177 INIT_LIST_HEAD(&qp->list); 1178 mutex_lock(&rdev->qp_lock); 1179 list_add_tail(&qp->list, &rdev->qp_list); 1180 atomic_inc(&rdev->qp_count); 1181 mutex_unlock(&rdev->qp_lock); 1182 1183 return &qp->ib_qp; 1184 qp_destroy: 1185 bnxt_qplib_destroy_qp(&rdev->qplib_res, &qp->qplib_qp); 1186 free_umem: 1187 ib_umem_release(qp->rumem); 1188 ib_umem_release(qp->sumem); 1189 fail: 1190 kfree(qp); 1191 return ERR_PTR(rc); 1192 } 1193 1194 static u8 __from_ib_qp_state(enum ib_qp_state state) 1195 { 1196 switch (state) { 1197 case IB_QPS_RESET: 1198 return CMDQ_MODIFY_QP_NEW_STATE_RESET; 1199 case IB_QPS_INIT: 1200 return CMDQ_MODIFY_QP_NEW_STATE_INIT; 1201 case IB_QPS_RTR: 1202 return CMDQ_MODIFY_QP_NEW_STATE_RTR; 1203 case IB_QPS_RTS: 1204 return CMDQ_MODIFY_QP_NEW_STATE_RTS; 1205 case IB_QPS_SQD: 1206 return CMDQ_MODIFY_QP_NEW_STATE_SQD; 1207 case IB_QPS_SQE: 1208 return CMDQ_MODIFY_QP_NEW_STATE_SQE; 1209 case IB_QPS_ERR: 1210 default: 1211 return CMDQ_MODIFY_QP_NEW_STATE_ERR; 1212 } 1213 } 1214 1215 static enum ib_qp_state __to_ib_qp_state(u8 state) 1216 { 1217 switch (state) { 1218 case CMDQ_MODIFY_QP_NEW_STATE_RESET: 1219 return IB_QPS_RESET; 1220 case CMDQ_MODIFY_QP_NEW_STATE_INIT: 1221 return IB_QPS_INIT; 1222 case CMDQ_MODIFY_QP_NEW_STATE_RTR: 1223 return IB_QPS_RTR; 1224 case CMDQ_MODIFY_QP_NEW_STATE_RTS: 1225 return IB_QPS_RTS; 1226 case CMDQ_MODIFY_QP_NEW_STATE_SQD: 1227 return IB_QPS_SQD; 1228 case CMDQ_MODIFY_QP_NEW_STATE_SQE: 1229 return IB_QPS_SQE; 1230 case CMDQ_MODIFY_QP_NEW_STATE_ERR: 1231 default: 1232 return IB_QPS_ERR; 1233 } 1234 } 1235 1236 static u32 __from_ib_mtu(enum ib_mtu mtu) 1237 { 1238 switch (mtu) { 1239 case IB_MTU_256: 1240 return CMDQ_MODIFY_QP_PATH_MTU_MTU_256; 1241 case IB_MTU_512: 1242 return CMDQ_MODIFY_QP_PATH_MTU_MTU_512; 1243 case IB_MTU_1024: 1244 return CMDQ_MODIFY_QP_PATH_MTU_MTU_1024; 1245 case IB_MTU_2048: 1246 return CMDQ_MODIFY_QP_PATH_MTU_MTU_2048; 1247 case IB_MTU_4096: 1248 return CMDQ_MODIFY_QP_PATH_MTU_MTU_4096; 1249 default: 1250 return CMDQ_MODIFY_QP_PATH_MTU_MTU_2048; 1251 } 1252 } 1253 1254 static enum ib_mtu __to_ib_mtu(u32 mtu) 1255 { 1256 switch (mtu & CREQ_QUERY_QP_RESP_SB_PATH_MTU_MASK) { 1257 case CMDQ_MODIFY_QP_PATH_MTU_MTU_256: 1258 return IB_MTU_256; 1259 case CMDQ_MODIFY_QP_PATH_MTU_MTU_512: 1260 return IB_MTU_512; 1261 case CMDQ_MODIFY_QP_PATH_MTU_MTU_1024: 1262 return IB_MTU_1024; 1263 case CMDQ_MODIFY_QP_PATH_MTU_MTU_2048: 1264 return IB_MTU_2048; 1265 case CMDQ_MODIFY_QP_PATH_MTU_MTU_4096: 1266 return IB_MTU_4096; 1267 default: 1268 return IB_MTU_2048; 1269 } 1270 } 1271 1272 /* Shared Receive Queues */ 1273 void bnxt_re_destroy_srq(struct ib_srq *ib_srq, struct ib_udata *udata) 1274 { 1275 struct bnxt_re_srq *srq = container_of(ib_srq, struct bnxt_re_srq, 1276 ib_srq); 1277 struct bnxt_re_dev *rdev = srq->rdev; 1278 struct bnxt_qplib_srq *qplib_srq = &srq->qplib_srq; 1279 struct bnxt_qplib_nq *nq = NULL; 1280 1281 if (qplib_srq->cq) 1282 nq = qplib_srq->cq->nq; 1283 bnxt_qplib_destroy_srq(&rdev->qplib_res, qplib_srq); 1284 ib_umem_release(srq->umem); 1285 atomic_dec(&rdev->srq_count); 1286 if (nq) 1287 nq->budget--; 1288 } 1289 1290 static int bnxt_re_init_user_srq(struct bnxt_re_dev *rdev, 1291 struct bnxt_re_pd *pd, 1292 struct bnxt_re_srq *srq, 1293 struct ib_udata *udata) 1294 { 1295 struct bnxt_re_srq_req ureq; 1296 struct bnxt_qplib_srq *qplib_srq = &srq->qplib_srq; 1297 struct ib_umem *umem; 1298 int bytes = 0; 1299 struct bnxt_re_ucontext *cntx = rdma_udata_to_drv_context( 1300 udata, struct bnxt_re_ucontext, ib_uctx); 1301 1302 if (ib_copy_from_udata(&ureq, udata, sizeof(ureq))) 1303 return -EFAULT; 1304 1305 bytes = (qplib_srq->max_wqe * BNXT_QPLIB_MAX_RQE_ENTRY_SIZE); 1306 bytes = PAGE_ALIGN(bytes); 1307 umem = ib_umem_get(udata, ureq.srqva, bytes, IB_ACCESS_LOCAL_WRITE); 1308 if (IS_ERR(umem)) 1309 return PTR_ERR(umem); 1310 1311 srq->umem = umem; 1312 qplib_srq->sg_info.sglist = umem->sg_head.sgl; 1313 qplib_srq->sg_info.npages = ib_umem_num_pages(umem); 1314 qplib_srq->sg_info.nmap = umem->nmap; 1315 qplib_srq->srq_handle = ureq.srq_handle; 1316 qplib_srq->dpi = &cntx->dpi; 1317 1318 return 0; 1319 } 1320 1321 int bnxt_re_create_srq(struct ib_srq *ib_srq, 1322 struct ib_srq_init_attr *srq_init_attr, 1323 struct ib_udata *udata) 1324 { 1325 struct ib_pd *ib_pd = ib_srq->pd; 1326 struct bnxt_re_pd *pd = container_of(ib_pd, struct bnxt_re_pd, ib_pd); 1327 struct bnxt_re_dev *rdev = pd->rdev; 1328 struct bnxt_qplib_dev_attr *dev_attr = &rdev->dev_attr; 1329 struct bnxt_re_srq *srq = 1330 container_of(ib_srq, struct bnxt_re_srq, ib_srq); 1331 struct bnxt_qplib_nq *nq = NULL; 1332 int rc, entries; 1333 1334 if (srq_init_attr->attr.max_wr >= dev_attr->max_srq_wqes) { 1335 dev_err(rdev_to_dev(rdev), "Create CQ failed - max exceeded"); 1336 rc = -EINVAL; 1337 goto exit; 1338 } 1339 1340 if (srq_init_attr->srq_type != IB_SRQT_BASIC) { 1341 rc = -EOPNOTSUPP; 1342 goto exit; 1343 } 1344 1345 srq->rdev = rdev; 1346 srq->qplib_srq.pd = &pd->qplib_pd; 1347 srq->qplib_srq.dpi = &rdev->dpi_privileged; 1348 /* Allocate 1 more than what's provided so posting max doesn't 1349 * mean empty 1350 */ 1351 entries = roundup_pow_of_two(srq_init_attr->attr.max_wr + 1); 1352 if (entries > dev_attr->max_srq_wqes + 1) 1353 entries = dev_attr->max_srq_wqes + 1; 1354 1355 srq->qplib_srq.max_wqe = entries; 1356 srq->qplib_srq.max_sge = srq_init_attr->attr.max_sge; 1357 srq->qplib_srq.threshold = srq_init_attr->attr.srq_limit; 1358 srq->srq_limit = srq_init_attr->attr.srq_limit; 1359 srq->qplib_srq.eventq_hw_ring_id = rdev->nq[0].ring_id; 1360 nq = &rdev->nq[0]; 1361 1362 if (udata) { 1363 rc = bnxt_re_init_user_srq(rdev, pd, srq, udata); 1364 if (rc) 1365 goto fail; 1366 } 1367 1368 rc = bnxt_qplib_create_srq(&rdev->qplib_res, &srq->qplib_srq); 1369 if (rc) { 1370 dev_err(rdev_to_dev(rdev), "Create HW SRQ failed!"); 1371 goto fail; 1372 } 1373 1374 if (udata) { 1375 struct bnxt_re_srq_resp resp; 1376 1377 resp.srqid = srq->qplib_srq.id; 1378 rc = ib_copy_to_udata(udata, &resp, sizeof(resp)); 1379 if (rc) { 1380 dev_err(rdev_to_dev(rdev), "SRQ copy to udata failed!"); 1381 bnxt_qplib_destroy_srq(&rdev->qplib_res, 1382 &srq->qplib_srq); 1383 goto fail; 1384 } 1385 } 1386 if (nq) 1387 nq->budget++; 1388 atomic_inc(&rdev->srq_count); 1389 1390 return 0; 1391 1392 fail: 1393 ib_umem_release(srq->umem); 1394 exit: 1395 return rc; 1396 } 1397 1398 int bnxt_re_modify_srq(struct ib_srq *ib_srq, struct ib_srq_attr *srq_attr, 1399 enum ib_srq_attr_mask srq_attr_mask, 1400 struct ib_udata *udata) 1401 { 1402 struct bnxt_re_srq *srq = container_of(ib_srq, struct bnxt_re_srq, 1403 ib_srq); 1404 struct bnxt_re_dev *rdev = srq->rdev; 1405 int rc; 1406 1407 switch (srq_attr_mask) { 1408 case IB_SRQ_MAX_WR: 1409 /* SRQ resize is not supported */ 1410 break; 1411 case IB_SRQ_LIMIT: 1412 /* Change the SRQ threshold */ 1413 if (srq_attr->srq_limit > srq->qplib_srq.max_wqe) 1414 return -EINVAL; 1415 1416 srq->qplib_srq.threshold = srq_attr->srq_limit; 1417 rc = bnxt_qplib_modify_srq(&rdev->qplib_res, &srq->qplib_srq); 1418 if (rc) { 1419 dev_err(rdev_to_dev(rdev), "Modify HW SRQ failed!"); 1420 return rc; 1421 } 1422 /* On success, update the shadow */ 1423 srq->srq_limit = srq_attr->srq_limit; 1424 /* No need to Build and send response back to udata */ 1425 break; 1426 default: 1427 dev_err(rdev_to_dev(rdev), 1428 "Unsupported srq_attr_mask 0x%x", srq_attr_mask); 1429 return -EINVAL; 1430 } 1431 return 0; 1432 } 1433 1434 int bnxt_re_query_srq(struct ib_srq *ib_srq, struct ib_srq_attr *srq_attr) 1435 { 1436 struct bnxt_re_srq *srq = container_of(ib_srq, struct bnxt_re_srq, 1437 ib_srq); 1438 struct bnxt_re_srq tsrq; 1439 struct bnxt_re_dev *rdev = srq->rdev; 1440 int rc; 1441 1442 /* Get live SRQ attr */ 1443 tsrq.qplib_srq.id = srq->qplib_srq.id; 1444 rc = bnxt_qplib_query_srq(&rdev->qplib_res, &tsrq.qplib_srq); 1445 if (rc) { 1446 dev_err(rdev_to_dev(rdev), "Query HW SRQ failed!"); 1447 return rc; 1448 } 1449 srq_attr->max_wr = srq->qplib_srq.max_wqe; 1450 srq_attr->max_sge = srq->qplib_srq.max_sge; 1451 srq_attr->srq_limit = tsrq.qplib_srq.threshold; 1452 1453 return 0; 1454 } 1455 1456 int bnxt_re_post_srq_recv(struct ib_srq *ib_srq, const struct ib_recv_wr *wr, 1457 const struct ib_recv_wr **bad_wr) 1458 { 1459 struct bnxt_re_srq *srq = container_of(ib_srq, struct bnxt_re_srq, 1460 ib_srq); 1461 struct bnxt_qplib_swqe wqe; 1462 unsigned long flags; 1463 int rc = 0; 1464 1465 spin_lock_irqsave(&srq->lock, flags); 1466 while (wr) { 1467 /* Transcribe each ib_recv_wr to qplib_swqe */ 1468 wqe.num_sge = wr->num_sge; 1469 bnxt_re_build_sgl(wr->sg_list, wqe.sg_list, wr->num_sge); 1470 wqe.wr_id = wr->wr_id; 1471 wqe.type = BNXT_QPLIB_SWQE_TYPE_RECV; 1472 1473 rc = bnxt_qplib_post_srq_recv(&srq->qplib_srq, &wqe); 1474 if (rc) { 1475 *bad_wr = wr; 1476 break; 1477 } 1478 wr = wr->next; 1479 } 1480 spin_unlock_irqrestore(&srq->lock, flags); 1481 1482 return rc; 1483 } 1484 static int bnxt_re_modify_shadow_qp(struct bnxt_re_dev *rdev, 1485 struct bnxt_re_qp *qp1_qp, 1486 int qp_attr_mask) 1487 { 1488 struct bnxt_re_qp *qp = rdev->qp1_sqp; 1489 int rc = 0; 1490 1491 if (qp_attr_mask & IB_QP_STATE) { 1492 qp->qplib_qp.modify_flags |= CMDQ_MODIFY_QP_MODIFY_MASK_STATE; 1493 qp->qplib_qp.state = qp1_qp->qplib_qp.state; 1494 } 1495 if (qp_attr_mask & IB_QP_PKEY_INDEX) { 1496 qp->qplib_qp.modify_flags |= CMDQ_MODIFY_QP_MODIFY_MASK_PKEY; 1497 qp->qplib_qp.pkey_index = qp1_qp->qplib_qp.pkey_index; 1498 } 1499 1500 if (qp_attr_mask & IB_QP_QKEY) { 1501 qp->qplib_qp.modify_flags |= CMDQ_MODIFY_QP_MODIFY_MASK_QKEY; 1502 /* Using a Random QKEY */ 1503 qp->qplib_qp.qkey = 0x81818181; 1504 } 1505 if (qp_attr_mask & IB_QP_SQ_PSN) { 1506 qp->qplib_qp.modify_flags |= CMDQ_MODIFY_QP_MODIFY_MASK_SQ_PSN; 1507 qp->qplib_qp.sq.psn = qp1_qp->qplib_qp.sq.psn; 1508 } 1509 1510 rc = bnxt_qplib_modify_qp(&rdev->qplib_res, &qp->qplib_qp); 1511 if (rc) 1512 dev_err(rdev_to_dev(rdev), 1513 "Failed to modify Shadow QP for QP1"); 1514 return rc; 1515 } 1516 1517 int bnxt_re_modify_qp(struct ib_qp *ib_qp, struct ib_qp_attr *qp_attr, 1518 int qp_attr_mask, struct ib_udata *udata) 1519 { 1520 struct bnxt_re_qp *qp = container_of(ib_qp, struct bnxt_re_qp, ib_qp); 1521 struct bnxt_re_dev *rdev = qp->rdev; 1522 struct bnxt_qplib_dev_attr *dev_attr = &rdev->dev_attr; 1523 enum ib_qp_state curr_qp_state, new_qp_state; 1524 int rc, entries; 1525 unsigned int flags; 1526 u8 nw_type; 1527 1528 qp->qplib_qp.modify_flags = 0; 1529 if (qp_attr_mask & IB_QP_STATE) { 1530 curr_qp_state = __to_ib_qp_state(qp->qplib_qp.cur_qp_state); 1531 new_qp_state = qp_attr->qp_state; 1532 if (!ib_modify_qp_is_ok(curr_qp_state, new_qp_state, 1533 ib_qp->qp_type, qp_attr_mask)) { 1534 dev_err(rdev_to_dev(rdev), 1535 "Invalid attribute mask: %#x specified ", 1536 qp_attr_mask); 1537 dev_err(rdev_to_dev(rdev), 1538 "for qpn: %#x type: %#x", 1539 ib_qp->qp_num, ib_qp->qp_type); 1540 dev_err(rdev_to_dev(rdev), 1541 "curr_qp_state=0x%x, new_qp_state=0x%x\n", 1542 curr_qp_state, new_qp_state); 1543 return -EINVAL; 1544 } 1545 qp->qplib_qp.modify_flags |= CMDQ_MODIFY_QP_MODIFY_MASK_STATE; 1546 qp->qplib_qp.state = __from_ib_qp_state(qp_attr->qp_state); 1547 1548 if (!qp->sumem && 1549 qp->qplib_qp.state == CMDQ_MODIFY_QP_NEW_STATE_ERR) { 1550 dev_dbg(rdev_to_dev(rdev), 1551 "Move QP = %p to flush list\n", 1552 qp); 1553 flags = bnxt_re_lock_cqs(qp); 1554 bnxt_qplib_add_flush_qp(&qp->qplib_qp); 1555 bnxt_re_unlock_cqs(qp, flags); 1556 } 1557 if (!qp->sumem && 1558 qp->qplib_qp.state == CMDQ_MODIFY_QP_NEW_STATE_RESET) { 1559 dev_dbg(rdev_to_dev(rdev), 1560 "Move QP = %p out of flush list\n", 1561 qp); 1562 flags = bnxt_re_lock_cqs(qp); 1563 bnxt_qplib_clean_qp(&qp->qplib_qp); 1564 bnxt_re_unlock_cqs(qp, flags); 1565 } 1566 } 1567 if (qp_attr_mask & IB_QP_EN_SQD_ASYNC_NOTIFY) { 1568 qp->qplib_qp.modify_flags |= 1569 CMDQ_MODIFY_QP_MODIFY_MASK_EN_SQD_ASYNC_NOTIFY; 1570 qp->qplib_qp.en_sqd_async_notify = true; 1571 } 1572 if (qp_attr_mask & IB_QP_ACCESS_FLAGS) { 1573 qp->qplib_qp.modify_flags |= CMDQ_MODIFY_QP_MODIFY_MASK_ACCESS; 1574 qp->qplib_qp.access = 1575 __from_ib_access_flags(qp_attr->qp_access_flags); 1576 /* LOCAL_WRITE access must be set to allow RC receive */ 1577 qp->qplib_qp.access |= BNXT_QPLIB_ACCESS_LOCAL_WRITE; 1578 /* Temp: Set all params on QP as of now */ 1579 qp->qplib_qp.access |= CMDQ_MODIFY_QP_ACCESS_REMOTE_WRITE; 1580 qp->qplib_qp.access |= CMDQ_MODIFY_QP_ACCESS_REMOTE_READ; 1581 } 1582 if (qp_attr_mask & IB_QP_PKEY_INDEX) { 1583 qp->qplib_qp.modify_flags |= CMDQ_MODIFY_QP_MODIFY_MASK_PKEY; 1584 qp->qplib_qp.pkey_index = qp_attr->pkey_index; 1585 } 1586 if (qp_attr_mask & IB_QP_QKEY) { 1587 qp->qplib_qp.modify_flags |= CMDQ_MODIFY_QP_MODIFY_MASK_QKEY; 1588 qp->qplib_qp.qkey = qp_attr->qkey; 1589 } 1590 if (qp_attr_mask & IB_QP_AV) { 1591 const struct ib_global_route *grh = 1592 rdma_ah_read_grh(&qp_attr->ah_attr); 1593 const struct ib_gid_attr *sgid_attr; 1594 1595 qp->qplib_qp.modify_flags |= CMDQ_MODIFY_QP_MODIFY_MASK_DGID | 1596 CMDQ_MODIFY_QP_MODIFY_MASK_FLOW_LABEL | 1597 CMDQ_MODIFY_QP_MODIFY_MASK_SGID_INDEX | 1598 CMDQ_MODIFY_QP_MODIFY_MASK_HOP_LIMIT | 1599 CMDQ_MODIFY_QP_MODIFY_MASK_TRAFFIC_CLASS | 1600 CMDQ_MODIFY_QP_MODIFY_MASK_DEST_MAC | 1601 CMDQ_MODIFY_QP_MODIFY_MASK_VLAN_ID; 1602 memcpy(qp->qplib_qp.ah.dgid.data, grh->dgid.raw, 1603 sizeof(qp->qplib_qp.ah.dgid.data)); 1604 qp->qplib_qp.ah.flow_label = grh->flow_label; 1605 /* If RoCE V2 is enabled, stack will have two entries for 1606 * each GID entry. Avoiding this duplicte entry in HW. Dividing 1607 * the GID index by 2 for RoCE V2 1608 */ 1609 qp->qplib_qp.ah.sgid_index = grh->sgid_index / 2; 1610 qp->qplib_qp.ah.host_sgid_index = grh->sgid_index; 1611 qp->qplib_qp.ah.hop_limit = grh->hop_limit; 1612 qp->qplib_qp.ah.traffic_class = grh->traffic_class; 1613 qp->qplib_qp.ah.sl = rdma_ah_get_sl(&qp_attr->ah_attr); 1614 ether_addr_copy(qp->qplib_qp.ah.dmac, 1615 qp_attr->ah_attr.roce.dmac); 1616 1617 sgid_attr = qp_attr->ah_attr.grh.sgid_attr; 1618 rc = rdma_read_gid_l2_fields(sgid_attr, NULL, 1619 &qp->qplib_qp.smac[0]); 1620 if (rc) 1621 return rc; 1622 1623 nw_type = rdma_gid_attr_network_type(sgid_attr); 1624 switch (nw_type) { 1625 case RDMA_NETWORK_IPV4: 1626 qp->qplib_qp.nw_type = 1627 CMDQ_MODIFY_QP_NETWORK_TYPE_ROCEV2_IPV4; 1628 break; 1629 case RDMA_NETWORK_IPV6: 1630 qp->qplib_qp.nw_type = 1631 CMDQ_MODIFY_QP_NETWORK_TYPE_ROCEV2_IPV6; 1632 break; 1633 default: 1634 qp->qplib_qp.nw_type = 1635 CMDQ_MODIFY_QP_NETWORK_TYPE_ROCEV1; 1636 break; 1637 } 1638 } 1639 1640 if (qp_attr_mask & IB_QP_PATH_MTU) { 1641 qp->qplib_qp.modify_flags |= 1642 CMDQ_MODIFY_QP_MODIFY_MASK_PATH_MTU; 1643 qp->qplib_qp.path_mtu = __from_ib_mtu(qp_attr->path_mtu); 1644 qp->qplib_qp.mtu = ib_mtu_enum_to_int(qp_attr->path_mtu); 1645 } else if (qp_attr->qp_state == IB_QPS_RTR) { 1646 qp->qplib_qp.modify_flags |= 1647 CMDQ_MODIFY_QP_MODIFY_MASK_PATH_MTU; 1648 qp->qplib_qp.path_mtu = 1649 __from_ib_mtu(iboe_get_mtu(rdev->netdev->mtu)); 1650 qp->qplib_qp.mtu = 1651 ib_mtu_enum_to_int(iboe_get_mtu(rdev->netdev->mtu)); 1652 } 1653 1654 if (qp_attr_mask & IB_QP_TIMEOUT) { 1655 qp->qplib_qp.modify_flags |= CMDQ_MODIFY_QP_MODIFY_MASK_TIMEOUT; 1656 qp->qplib_qp.timeout = qp_attr->timeout; 1657 } 1658 if (qp_attr_mask & IB_QP_RETRY_CNT) { 1659 qp->qplib_qp.modify_flags |= 1660 CMDQ_MODIFY_QP_MODIFY_MASK_RETRY_CNT; 1661 qp->qplib_qp.retry_cnt = qp_attr->retry_cnt; 1662 } 1663 if (qp_attr_mask & IB_QP_RNR_RETRY) { 1664 qp->qplib_qp.modify_flags |= 1665 CMDQ_MODIFY_QP_MODIFY_MASK_RNR_RETRY; 1666 qp->qplib_qp.rnr_retry = qp_attr->rnr_retry; 1667 } 1668 if (qp_attr_mask & IB_QP_MIN_RNR_TIMER) { 1669 qp->qplib_qp.modify_flags |= 1670 CMDQ_MODIFY_QP_MODIFY_MASK_MIN_RNR_TIMER; 1671 qp->qplib_qp.min_rnr_timer = qp_attr->min_rnr_timer; 1672 } 1673 if (qp_attr_mask & IB_QP_RQ_PSN) { 1674 qp->qplib_qp.modify_flags |= CMDQ_MODIFY_QP_MODIFY_MASK_RQ_PSN; 1675 qp->qplib_qp.rq.psn = qp_attr->rq_psn; 1676 } 1677 if (qp_attr_mask & IB_QP_MAX_QP_RD_ATOMIC) { 1678 qp->qplib_qp.modify_flags |= 1679 CMDQ_MODIFY_QP_MODIFY_MASK_MAX_RD_ATOMIC; 1680 /* Cap the max_rd_atomic to device max */ 1681 qp->qplib_qp.max_rd_atomic = min_t(u32, qp_attr->max_rd_atomic, 1682 dev_attr->max_qp_rd_atom); 1683 } 1684 if (qp_attr_mask & IB_QP_SQ_PSN) { 1685 qp->qplib_qp.modify_flags |= CMDQ_MODIFY_QP_MODIFY_MASK_SQ_PSN; 1686 qp->qplib_qp.sq.psn = qp_attr->sq_psn; 1687 } 1688 if (qp_attr_mask & IB_QP_MAX_DEST_RD_ATOMIC) { 1689 if (qp_attr->max_dest_rd_atomic > 1690 dev_attr->max_qp_init_rd_atom) { 1691 dev_err(rdev_to_dev(rdev), 1692 "max_dest_rd_atomic requested%d is > dev_max%d", 1693 qp_attr->max_dest_rd_atomic, 1694 dev_attr->max_qp_init_rd_atom); 1695 return -EINVAL; 1696 } 1697 1698 qp->qplib_qp.modify_flags |= 1699 CMDQ_MODIFY_QP_MODIFY_MASK_MAX_DEST_RD_ATOMIC; 1700 qp->qplib_qp.max_dest_rd_atomic = qp_attr->max_dest_rd_atomic; 1701 } 1702 if (qp_attr_mask & IB_QP_CAP) { 1703 qp->qplib_qp.modify_flags |= 1704 CMDQ_MODIFY_QP_MODIFY_MASK_SQ_SIZE | 1705 CMDQ_MODIFY_QP_MODIFY_MASK_RQ_SIZE | 1706 CMDQ_MODIFY_QP_MODIFY_MASK_SQ_SGE | 1707 CMDQ_MODIFY_QP_MODIFY_MASK_RQ_SGE | 1708 CMDQ_MODIFY_QP_MODIFY_MASK_MAX_INLINE_DATA; 1709 if ((qp_attr->cap.max_send_wr >= dev_attr->max_qp_wqes) || 1710 (qp_attr->cap.max_recv_wr >= dev_attr->max_qp_wqes) || 1711 (qp_attr->cap.max_send_sge >= dev_attr->max_qp_sges) || 1712 (qp_attr->cap.max_recv_sge >= dev_attr->max_qp_sges) || 1713 (qp_attr->cap.max_inline_data >= 1714 dev_attr->max_inline_data)) { 1715 dev_err(rdev_to_dev(rdev), 1716 "Create QP failed - max exceeded"); 1717 return -EINVAL; 1718 } 1719 entries = roundup_pow_of_two(qp_attr->cap.max_send_wr); 1720 qp->qplib_qp.sq.max_wqe = min_t(u32, entries, 1721 dev_attr->max_qp_wqes + 1); 1722 qp->qplib_qp.sq.q_full_delta = qp->qplib_qp.sq.max_wqe - 1723 qp_attr->cap.max_send_wr; 1724 /* 1725 * Reserving one slot for Phantom WQE. Some application can 1726 * post one extra entry in this case. Allowing this to avoid 1727 * unexpected Queue full condition 1728 */ 1729 qp->qplib_qp.sq.q_full_delta -= 1; 1730 qp->qplib_qp.sq.max_sge = qp_attr->cap.max_send_sge; 1731 if (qp->qplib_qp.rq.max_wqe) { 1732 entries = roundup_pow_of_two(qp_attr->cap.max_recv_wr); 1733 qp->qplib_qp.rq.max_wqe = 1734 min_t(u32, entries, dev_attr->max_qp_wqes + 1); 1735 qp->qplib_qp.rq.q_full_delta = qp->qplib_qp.rq.max_wqe - 1736 qp_attr->cap.max_recv_wr; 1737 qp->qplib_qp.rq.max_sge = qp_attr->cap.max_recv_sge; 1738 } else { 1739 /* SRQ was used prior, just ignore the RQ caps */ 1740 } 1741 } 1742 if (qp_attr_mask & IB_QP_DEST_QPN) { 1743 qp->qplib_qp.modify_flags |= 1744 CMDQ_MODIFY_QP_MODIFY_MASK_DEST_QP_ID; 1745 qp->qplib_qp.dest_qpn = qp_attr->dest_qp_num; 1746 } 1747 rc = bnxt_qplib_modify_qp(&rdev->qplib_res, &qp->qplib_qp); 1748 if (rc) { 1749 dev_err(rdev_to_dev(rdev), "Failed to modify HW QP"); 1750 return rc; 1751 } 1752 if (ib_qp->qp_type == IB_QPT_GSI && rdev->qp1_sqp) 1753 rc = bnxt_re_modify_shadow_qp(rdev, qp, qp_attr_mask); 1754 return rc; 1755 } 1756 1757 int bnxt_re_query_qp(struct ib_qp *ib_qp, struct ib_qp_attr *qp_attr, 1758 int qp_attr_mask, struct ib_qp_init_attr *qp_init_attr) 1759 { 1760 struct bnxt_re_qp *qp = container_of(ib_qp, struct bnxt_re_qp, ib_qp); 1761 struct bnxt_re_dev *rdev = qp->rdev; 1762 struct bnxt_qplib_qp *qplib_qp; 1763 int rc; 1764 1765 qplib_qp = kzalloc(sizeof(*qplib_qp), GFP_KERNEL); 1766 if (!qplib_qp) 1767 return -ENOMEM; 1768 1769 qplib_qp->id = qp->qplib_qp.id; 1770 qplib_qp->ah.host_sgid_index = qp->qplib_qp.ah.host_sgid_index; 1771 1772 rc = bnxt_qplib_query_qp(&rdev->qplib_res, qplib_qp); 1773 if (rc) { 1774 dev_err(rdev_to_dev(rdev), "Failed to query HW QP"); 1775 goto out; 1776 } 1777 qp_attr->qp_state = __to_ib_qp_state(qplib_qp->state); 1778 qp_attr->en_sqd_async_notify = qplib_qp->en_sqd_async_notify ? 1 : 0; 1779 qp_attr->qp_access_flags = __to_ib_access_flags(qplib_qp->access); 1780 qp_attr->pkey_index = qplib_qp->pkey_index; 1781 qp_attr->qkey = qplib_qp->qkey; 1782 qp_attr->ah_attr.type = RDMA_AH_ATTR_TYPE_ROCE; 1783 rdma_ah_set_grh(&qp_attr->ah_attr, NULL, qplib_qp->ah.flow_label, 1784 qplib_qp->ah.host_sgid_index, 1785 qplib_qp->ah.hop_limit, 1786 qplib_qp->ah.traffic_class); 1787 rdma_ah_set_dgid_raw(&qp_attr->ah_attr, qplib_qp->ah.dgid.data); 1788 rdma_ah_set_sl(&qp_attr->ah_attr, qplib_qp->ah.sl); 1789 ether_addr_copy(qp_attr->ah_attr.roce.dmac, qplib_qp->ah.dmac); 1790 qp_attr->path_mtu = __to_ib_mtu(qplib_qp->path_mtu); 1791 qp_attr->timeout = qplib_qp->timeout; 1792 qp_attr->retry_cnt = qplib_qp->retry_cnt; 1793 qp_attr->rnr_retry = qplib_qp->rnr_retry; 1794 qp_attr->min_rnr_timer = qplib_qp->min_rnr_timer; 1795 qp_attr->rq_psn = qplib_qp->rq.psn; 1796 qp_attr->max_rd_atomic = qplib_qp->max_rd_atomic; 1797 qp_attr->sq_psn = qplib_qp->sq.psn; 1798 qp_attr->max_dest_rd_atomic = qplib_qp->max_dest_rd_atomic; 1799 qp_init_attr->sq_sig_type = qplib_qp->sig_type ? IB_SIGNAL_ALL_WR : 1800 IB_SIGNAL_REQ_WR; 1801 qp_attr->dest_qp_num = qplib_qp->dest_qpn; 1802 1803 qp_attr->cap.max_send_wr = qp->qplib_qp.sq.max_wqe; 1804 qp_attr->cap.max_send_sge = qp->qplib_qp.sq.max_sge; 1805 qp_attr->cap.max_recv_wr = qp->qplib_qp.rq.max_wqe; 1806 qp_attr->cap.max_recv_sge = qp->qplib_qp.rq.max_sge; 1807 qp_attr->cap.max_inline_data = qp->qplib_qp.max_inline_data; 1808 qp_init_attr->cap = qp_attr->cap; 1809 1810 out: 1811 kfree(qplib_qp); 1812 return rc; 1813 } 1814 1815 /* Routine for sending QP1 packets for RoCE V1 an V2 1816 */ 1817 static int bnxt_re_build_qp1_send_v2(struct bnxt_re_qp *qp, 1818 const struct ib_send_wr *wr, 1819 struct bnxt_qplib_swqe *wqe, 1820 int payload_size) 1821 { 1822 struct bnxt_re_ah *ah = container_of(ud_wr(wr)->ah, struct bnxt_re_ah, 1823 ib_ah); 1824 struct bnxt_qplib_ah *qplib_ah = &ah->qplib_ah; 1825 const struct ib_gid_attr *sgid_attr = ah->ib_ah.sgid_attr; 1826 struct bnxt_qplib_sge sge; 1827 u8 nw_type; 1828 u16 ether_type; 1829 union ib_gid dgid; 1830 bool is_eth = false; 1831 bool is_vlan = false; 1832 bool is_grh = false; 1833 bool is_udp = false; 1834 u8 ip_version = 0; 1835 u16 vlan_id = 0xFFFF; 1836 void *buf; 1837 int i, rc = 0; 1838 1839 memset(&qp->qp1_hdr, 0, sizeof(qp->qp1_hdr)); 1840 1841 rc = rdma_read_gid_l2_fields(sgid_attr, &vlan_id, NULL); 1842 if (rc) 1843 return rc; 1844 1845 /* Get network header type for this GID */ 1846 nw_type = rdma_gid_attr_network_type(sgid_attr); 1847 switch (nw_type) { 1848 case RDMA_NETWORK_IPV4: 1849 nw_type = BNXT_RE_ROCEV2_IPV4_PACKET; 1850 break; 1851 case RDMA_NETWORK_IPV6: 1852 nw_type = BNXT_RE_ROCEV2_IPV6_PACKET; 1853 break; 1854 default: 1855 nw_type = BNXT_RE_ROCE_V1_PACKET; 1856 break; 1857 } 1858 memcpy(&dgid.raw, &qplib_ah->dgid, 16); 1859 is_udp = sgid_attr->gid_type == IB_GID_TYPE_ROCE_UDP_ENCAP; 1860 if (is_udp) { 1861 if (ipv6_addr_v4mapped((struct in6_addr *)&sgid_attr->gid)) { 1862 ip_version = 4; 1863 ether_type = ETH_P_IP; 1864 } else { 1865 ip_version = 6; 1866 ether_type = ETH_P_IPV6; 1867 } 1868 is_grh = false; 1869 } else { 1870 ether_type = ETH_P_IBOE; 1871 is_grh = true; 1872 } 1873 1874 is_eth = true; 1875 is_vlan = (vlan_id && (vlan_id < 0x1000)) ? true : false; 1876 1877 ib_ud_header_init(payload_size, !is_eth, is_eth, is_vlan, is_grh, 1878 ip_version, is_udp, 0, &qp->qp1_hdr); 1879 1880 /* ETH */ 1881 ether_addr_copy(qp->qp1_hdr.eth.dmac_h, ah->qplib_ah.dmac); 1882 ether_addr_copy(qp->qp1_hdr.eth.smac_h, qp->qplib_qp.smac); 1883 1884 /* For vlan, check the sgid for vlan existence */ 1885 1886 if (!is_vlan) { 1887 qp->qp1_hdr.eth.type = cpu_to_be16(ether_type); 1888 } else { 1889 qp->qp1_hdr.vlan.type = cpu_to_be16(ether_type); 1890 qp->qp1_hdr.vlan.tag = cpu_to_be16(vlan_id); 1891 } 1892 1893 if (is_grh || (ip_version == 6)) { 1894 memcpy(qp->qp1_hdr.grh.source_gid.raw, sgid_attr->gid.raw, 1895 sizeof(sgid_attr->gid)); 1896 memcpy(qp->qp1_hdr.grh.destination_gid.raw, qplib_ah->dgid.data, 1897 sizeof(sgid_attr->gid)); 1898 qp->qp1_hdr.grh.hop_limit = qplib_ah->hop_limit; 1899 } 1900 1901 if (ip_version == 4) { 1902 qp->qp1_hdr.ip4.tos = 0; 1903 qp->qp1_hdr.ip4.id = 0; 1904 qp->qp1_hdr.ip4.frag_off = htons(IP_DF); 1905 qp->qp1_hdr.ip4.ttl = qplib_ah->hop_limit; 1906 1907 memcpy(&qp->qp1_hdr.ip4.saddr, sgid_attr->gid.raw + 12, 4); 1908 memcpy(&qp->qp1_hdr.ip4.daddr, qplib_ah->dgid.data + 12, 4); 1909 qp->qp1_hdr.ip4.check = ib_ud_ip4_csum(&qp->qp1_hdr); 1910 } 1911 1912 if (is_udp) { 1913 qp->qp1_hdr.udp.dport = htons(ROCE_V2_UDP_DPORT); 1914 qp->qp1_hdr.udp.sport = htons(0x8CD1); 1915 qp->qp1_hdr.udp.csum = 0; 1916 } 1917 1918 /* BTH */ 1919 if (wr->opcode == IB_WR_SEND_WITH_IMM) { 1920 qp->qp1_hdr.bth.opcode = IB_OPCODE_UD_SEND_ONLY_WITH_IMMEDIATE; 1921 qp->qp1_hdr.immediate_present = 1; 1922 } else { 1923 qp->qp1_hdr.bth.opcode = IB_OPCODE_UD_SEND_ONLY; 1924 } 1925 if (wr->send_flags & IB_SEND_SOLICITED) 1926 qp->qp1_hdr.bth.solicited_event = 1; 1927 /* pad_count */ 1928 qp->qp1_hdr.bth.pad_count = (4 - payload_size) & 3; 1929 1930 /* P_key for QP1 is for all members */ 1931 qp->qp1_hdr.bth.pkey = cpu_to_be16(0xFFFF); 1932 qp->qp1_hdr.bth.destination_qpn = IB_QP1; 1933 qp->qp1_hdr.bth.ack_req = 0; 1934 qp->send_psn++; 1935 qp->send_psn &= BTH_PSN_MASK; 1936 qp->qp1_hdr.bth.psn = cpu_to_be32(qp->send_psn); 1937 /* DETH */ 1938 /* Use the priviledged Q_Key for QP1 */ 1939 qp->qp1_hdr.deth.qkey = cpu_to_be32(IB_QP1_QKEY); 1940 qp->qp1_hdr.deth.source_qpn = IB_QP1; 1941 1942 /* Pack the QP1 to the transmit buffer */ 1943 buf = bnxt_qplib_get_qp1_sq_buf(&qp->qplib_qp, &sge); 1944 if (buf) { 1945 ib_ud_header_pack(&qp->qp1_hdr, buf); 1946 for (i = wqe->num_sge; i; i--) { 1947 wqe->sg_list[i].addr = wqe->sg_list[i - 1].addr; 1948 wqe->sg_list[i].lkey = wqe->sg_list[i - 1].lkey; 1949 wqe->sg_list[i].size = wqe->sg_list[i - 1].size; 1950 } 1951 1952 /* 1953 * Max Header buf size for IPV6 RoCE V2 is 86, 1954 * which is same as the QP1 SQ header buffer. 1955 * Header buf size for IPV4 RoCE V2 can be 66. 1956 * ETH(14) + VLAN(4)+ IP(20) + UDP (8) + BTH(20). 1957 * Subtract 20 bytes from QP1 SQ header buf size 1958 */ 1959 if (is_udp && ip_version == 4) 1960 sge.size -= 20; 1961 /* 1962 * Max Header buf size for RoCE V1 is 78. 1963 * ETH(14) + VLAN(4) + GRH(40) + BTH(20). 1964 * Subtract 8 bytes from QP1 SQ header buf size 1965 */ 1966 if (!is_udp) 1967 sge.size -= 8; 1968 1969 /* Subtract 4 bytes for non vlan packets */ 1970 if (!is_vlan) 1971 sge.size -= 4; 1972 1973 wqe->sg_list[0].addr = sge.addr; 1974 wqe->sg_list[0].lkey = sge.lkey; 1975 wqe->sg_list[0].size = sge.size; 1976 wqe->num_sge++; 1977 1978 } else { 1979 dev_err(rdev_to_dev(qp->rdev), "QP1 buffer is empty!"); 1980 rc = -ENOMEM; 1981 } 1982 return rc; 1983 } 1984 1985 /* For the MAD layer, it only provides the recv SGE the size of 1986 * ib_grh + MAD datagram. No Ethernet headers, Ethertype, BTH, DETH, 1987 * nor RoCE iCRC. The Cu+ solution must provide buffer for the entire 1988 * receive packet (334 bytes) with no VLAN and then copy the GRH 1989 * and the MAD datagram out to the provided SGE. 1990 */ 1991 static int bnxt_re_build_qp1_shadow_qp_recv(struct bnxt_re_qp *qp, 1992 const struct ib_recv_wr *wr, 1993 struct bnxt_qplib_swqe *wqe, 1994 int payload_size) 1995 { 1996 struct bnxt_qplib_sge ref, sge; 1997 u32 rq_prod_index; 1998 struct bnxt_re_sqp_entries *sqp_entry; 1999 2000 rq_prod_index = bnxt_qplib_get_rq_prod_index(&qp->qplib_qp); 2001 2002 if (!bnxt_qplib_get_qp1_rq_buf(&qp->qplib_qp, &sge)) 2003 return -ENOMEM; 2004 2005 /* Create 1 SGE to receive the entire 2006 * ethernet packet 2007 */ 2008 /* Save the reference from ULP */ 2009 ref.addr = wqe->sg_list[0].addr; 2010 ref.lkey = wqe->sg_list[0].lkey; 2011 ref.size = wqe->sg_list[0].size; 2012 2013 sqp_entry = &qp->rdev->sqp_tbl[rq_prod_index]; 2014 2015 /* SGE 1 */ 2016 wqe->sg_list[0].addr = sge.addr; 2017 wqe->sg_list[0].lkey = sge.lkey; 2018 wqe->sg_list[0].size = BNXT_QPLIB_MAX_QP1_RQ_HDR_SIZE_V2; 2019 sge.size -= wqe->sg_list[0].size; 2020 2021 sqp_entry->sge.addr = ref.addr; 2022 sqp_entry->sge.lkey = ref.lkey; 2023 sqp_entry->sge.size = ref.size; 2024 /* Store the wrid for reporting completion */ 2025 sqp_entry->wrid = wqe->wr_id; 2026 /* change the wqe->wrid to table index */ 2027 wqe->wr_id = rq_prod_index; 2028 return 0; 2029 } 2030 2031 static int is_ud_qp(struct bnxt_re_qp *qp) 2032 { 2033 return (qp->qplib_qp.type == CMDQ_CREATE_QP_TYPE_UD || 2034 qp->qplib_qp.type == CMDQ_CREATE_QP_TYPE_GSI); 2035 } 2036 2037 static int bnxt_re_build_send_wqe(struct bnxt_re_qp *qp, 2038 const struct ib_send_wr *wr, 2039 struct bnxt_qplib_swqe *wqe) 2040 { 2041 struct bnxt_re_ah *ah = NULL; 2042 2043 if (is_ud_qp(qp)) { 2044 ah = container_of(ud_wr(wr)->ah, struct bnxt_re_ah, ib_ah); 2045 wqe->send.q_key = ud_wr(wr)->remote_qkey; 2046 wqe->send.dst_qp = ud_wr(wr)->remote_qpn; 2047 wqe->send.avid = ah->qplib_ah.id; 2048 } 2049 switch (wr->opcode) { 2050 case IB_WR_SEND: 2051 wqe->type = BNXT_QPLIB_SWQE_TYPE_SEND; 2052 break; 2053 case IB_WR_SEND_WITH_IMM: 2054 wqe->type = BNXT_QPLIB_SWQE_TYPE_SEND_WITH_IMM; 2055 wqe->send.imm_data = wr->ex.imm_data; 2056 break; 2057 case IB_WR_SEND_WITH_INV: 2058 wqe->type = BNXT_QPLIB_SWQE_TYPE_SEND_WITH_INV; 2059 wqe->send.inv_key = wr->ex.invalidate_rkey; 2060 break; 2061 default: 2062 return -EINVAL; 2063 } 2064 if (wr->send_flags & IB_SEND_SIGNALED) 2065 wqe->flags |= BNXT_QPLIB_SWQE_FLAGS_SIGNAL_COMP; 2066 if (wr->send_flags & IB_SEND_FENCE) 2067 wqe->flags |= BNXT_QPLIB_SWQE_FLAGS_UC_FENCE; 2068 if (wr->send_flags & IB_SEND_SOLICITED) 2069 wqe->flags |= BNXT_QPLIB_SWQE_FLAGS_SOLICIT_EVENT; 2070 if (wr->send_flags & IB_SEND_INLINE) 2071 wqe->flags |= BNXT_QPLIB_SWQE_FLAGS_INLINE; 2072 2073 return 0; 2074 } 2075 2076 static int bnxt_re_build_rdma_wqe(const struct ib_send_wr *wr, 2077 struct bnxt_qplib_swqe *wqe) 2078 { 2079 switch (wr->opcode) { 2080 case IB_WR_RDMA_WRITE: 2081 wqe->type = BNXT_QPLIB_SWQE_TYPE_RDMA_WRITE; 2082 break; 2083 case IB_WR_RDMA_WRITE_WITH_IMM: 2084 wqe->type = BNXT_QPLIB_SWQE_TYPE_RDMA_WRITE_WITH_IMM; 2085 wqe->rdma.imm_data = wr->ex.imm_data; 2086 break; 2087 case IB_WR_RDMA_READ: 2088 wqe->type = BNXT_QPLIB_SWQE_TYPE_RDMA_READ; 2089 wqe->rdma.inv_key = wr->ex.invalidate_rkey; 2090 break; 2091 default: 2092 return -EINVAL; 2093 } 2094 wqe->rdma.remote_va = rdma_wr(wr)->remote_addr; 2095 wqe->rdma.r_key = rdma_wr(wr)->rkey; 2096 if (wr->send_flags & IB_SEND_SIGNALED) 2097 wqe->flags |= BNXT_QPLIB_SWQE_FLAGS_SIGNAL_COMP; 2098 if (wr->send_flags & IB_SEND_FENCE) 2099 wqe->flags |= BNXT_QPLIB_SWQE_FLAGS_UC_FENCE; 2100 if (wr->send_flags & IB_SEND_SOLICITED) 2101 wqe->flags |= BNXT_QPLIB_SWQE_FLAGS_SOLICIT_EVENT; 2102 if (wr->send_flags & IB_SEND_INLINE) 2103 wqe->flags |= BNXT_QPLIB_SWQE_FLAGS_INLINE; 2104 2105 return 0; 2106 } 2107 2108 static int bnxt_re_build_atomic_wqe(const struct ib_send_wr *wr, 2109 struct bnxt_qplib_swqe *wqe) 2110 { 2111 switch (wr->opcode) { 2112 case IB_WR_ATOMIC_CMP_AND_SWP: 2113 wqe->type = BNXT_QPLIB_SWQE_TYPE_ATOMIC_CMP_AND_SWP; 2114 wqe->atomic.cmp_data = atomic_wr(wr)->compare_add; 2115 wqe->atomic.swap_data = atomic_wr(wr)->swap; 2116 break; 2117 case IB_WR_ATOMIC_FETCH_AND_ADD: 2118 wqe->type = BNXT_QPLIB_SWQE_TYPE_ATOMIC_FETCH_AND_ADD; 2119 wqe->atomic.cmp_data = atomic_wr(wr)->compare_add; 2120 break; 2121 default: 2122 return -EINVAL; 2123 } 2124 wqe->atomic.remote_va = atomic_wr(wr)->remote_addr; 2125 wqe->atomic.r_key = atomic_wr(wr)->rkey; 2126 if (wr->send_flags & IB_SEND_SIGNALED) 2127 wqe->flags |= BNXT_QPLIB_SWQE_FLAGS_SIGNAL_COMP; 2128 if (wr->send_flags & IB_SEND_FENCE) 2129 wqe->flags |= BNXT_QPLIB_SWQE_FLAGS_UC_FENCE; 2130 if (wr->send_flags & IB_SEND_SOLICITED) 2131 wqe->flags |= BNXT_QPLIB_SWQE_FLAGS_SOLICIT_EVENT; 2132 return 0; 2133 } 2134 2135 static int bnxt_re_build_inv_wqe(const struct ib_send_wr *wr, 2136 struct bnxt_qplib_swqe *wqe) 2137 { 2138 wqe->type = BNXT_QPLIB_SWQE_TYPE_LOCAL_INV; 2139 wqe->local_inv.inv_l_key = wr->ex.invalidate_rkey; 2140 2141 /* Need unconditional fence for local invalidate 2142 * opcode to work as expected. 2143 */ 2144 wqe->flags |= BNXT_QPLIB_SWQE_FLAGS_UC_FENCE; 2145 2146 if (wr->send_flags & IB_SEND_SIGNALED) 2147 wqe->flags |= BNXT_QPLIB_SWQE_FLAGS_SIGNAL_COMP; 2148 if (wr->send_flags & IB_SEND_SOLICITED) 2149 wqe->flags |= BNXT_QPLIB_SWQE_FLAGS_SOLICIT_EVENT; 2150 2151 return 0; 2152 } 2153 2154 static int bnxt_re_build_reg_wqe(const struct ib_reg_wr *wr, 2155 struct bnxt_qplib_swqe *wqe) 2156 { 2157 struct bnxt_re_mr *mr = container_of(wr->mr, struct bnxt_re_mr, ib_mr); 2158 struct bnxt_qplib_frpl *qplib_frpl = &mr->qplib_frpl; 2159 int access = wr->access; 2160 2161 wqe->frmr.pbl_ptr = (__le64 *)qplib_frpl->hwq.pbl_ptr[0]; 2162 wqe->frmr.pbl_dma_ptr = qplib_frpl->hwq.pbl_dma_ptr[0]; 2163 wqe->frmr.page_list = mr->pages; 2164 wqe->frmr.page_list_len = mr->npages; 2165 wqe->frmr.levels = qplib_frpl->hwq.level + 1; 2166 wqe->type = BNXT_QPLIB_SWQE_TYPE_REG_MR; 2167 2168 /* Need unconditional fence for reg_mr 2169 * opcode to function as expected. 2170 */ 2171 2172 wqe->flags |= BNXT_QPLIB_SWQE_FLAGS_UC_FENCE; 2173 2174 if (wr->wr.send_flags & IB_SEND_SIGNALED) 2175 wqe->flags |= BNXT_QPLIB_SWQE_FLAGS_SIGNAL_COMP; 2176 2177 if (access & IB_ACCESS_LOCAL_WRITE) 2178 wqe->frmr.access_cntl |= SQ_FR_PMR_ACCESS_CNTL_LOCAL_WRITE; 2179 if (access & IB_ACCESS_REMOTE_READ) 2180 wqe->frmr.access_cntl |= SQ_FR_PMR_ACCESS_CNTL_REMOTE_READ; 2181 if (access & IB_ACCESS_REMOTE_WRITE) 2182 wqe->frmr.access_cntl |= SQ_FR_PMR_ACCESS_CNTL_REMOTE_WRITE; 2183 if (access & IB_ACCESS_REMOTE_ATOMIC) 2184 wqe->frmr.access_cntl |= SQ_FR_PMR_ACCESS_CNTL_REMOTE_ATOMIC; 2185 if (access & IB_ACCESS_MW_BIND) 2186 wqe->frmr.access_cntl |= SQ_FR_PMR_ACCESS_CNTL_WINDOW_BIND; 2187 2188 wqe->frmr.l_key = wr->key; 2189 wqe->frmr.length = wr->mr->length; 2190 wqe->frmr.pbl_pg_sz_log = (wr->mr->page_size >> PAGE_SHIFT_4K) - 1; 2191 wqe->frmr.va = wr->mr->iova; 2192 return 0; 2193 } 2194 2195 static int bnxt_re_copy_inline_data(struct bnxt_re_dev *rdev, 2196 const struct ib_send_wr *wr, 2197 struct bnxt_qplib_swqe *wqe) 2198 { 2199 /* Copy the inline data to the data field */ 2200 u8 *in_data; 2201 u32 i, sge_len; 2202 void *sge_addr; 2203 2204 in_data = wqe->inline_data; 2205 for (i = 0; i < wr->num_sge; i++) { 2206 sge_addr = (void *)(unsigned long) 2207 wr->sg_list[i].addr; 2208 sge_len = wr->sg_list[i].length; 2209 2210 if ((sge_len + wqe->inline_len) > 2211 BNXT_QPLIB_SWQE_MAX_INLINE_LENGTH) { 2212 dev_err(rdev_to_dev(rdev), 2213 "Inline data size requested > supported value"); 2214 return -EINVAL; 2215 } 2216 sge_len = wr->sg_list[i].length; 2217 2218 memcpy(in_data, sge_addr, sge_len); 2219 in_data += wr->sg_list[i].length; 2220 wqe->inline_len += wr->sg_list[i].length; 2221 } 2222 return wqe->inline_len; 2223 } 2224 2225 static int bnxt_re_copy_wr_payload(struct bnxt_re_dev *rdev, 2226 const struct ib_send_wr *wr, 2227 struct bnxt_qplib_swqe *wqe) 2228 { 2229 int payload_sz = 0; 2230 2231 if (wr->send_flags & IB_SEND_INLINE) 2232 payload_sz = bnxt_re_copy_inline_data(rdev, wr, wqe); 2233 else 2234 payload_sz = bnxt_re_build_sgl(wr->sg_list, wqe->sg_list, 2235 wqe->num_sge); 2236 2237 return payload_sz; 2238 } 2239 2240 static void bnxt_ud_qp_hw_stall_workaround(struct bnxt_re_qp *qp) 2241 { 2242 if ((qp->ib_qp.qp_type == IB_QPT_UD || 2243 qp->ib_qp.qp_type == IB_QPT_GSI || 2244 qp->ib_qp.qp_type == IB_QPT_RAW_ETHERTYPE) && 2245 qp->qplib_qp.wqe_cnt == BNXT_RE_UD_QP_HW_STALL) { 2246 int qp_attr_mask; 2247 struct ib_qp_attr qp_attr; 2248 2249 qp_attr_mask = IB_QP_STATE; 2250 qp_attr.qp_state = IB_QPS_RTS; 2251 bnxt_re_modify_qp(&qp->ib_qp, &qp_attr, qp_attr_mask, NULL); 2252 qp->qplib_qp.wqe_cnt = 0; 2253 } 2254 } 2255 2256 static int bnxt_re_post_send_shadow_qp(struct bnxt_re_dev *rdev, 2257 struct bnxt_re_qp *qp, 2258 const struct ib_send_wr *wr) 2259 { 2260 struct bnxt_qplib_swqe wqe; 2261 int rc = 0, payload_sz = 0; 2262 unsigned long flags; 2263 2264 spin_lock_irqsave(&qp->sq_lock, flags); 2265 memset(&wqe, 0, sizeof(wqe)); 2266 while (wr) { 2267 /* House keeping */ 2268 memset(&wqe, 0, sizeof(wqe)); 2269 2270 /* Common */ 2271 wqe.num_sge = wr->num_sge; 2272 if (wr->num_sge > qp->qplib_qp.sq.max_sge) { 2273 dev_err(rdev_to_dev(rdev), 2274 "Limit exceeded for Send SGEs"); 2275 rc = -EINVAL; 2276 goto bad; 2277 } 2278 2279 payload_sz = bnxt_re_copy_wr_payload(qp->rdev, wr, &wqe); 2280 if (payload_sz < 0) { 2281 rc = -EINVAL; 2282 goto bad; 2283 } 2284 wqe.wr_id = wr->wr_id; 2285 2286 wqe.type = BNXT_QPLIB_SWQE_TYPE_SEND; 2287 2288 rc = bnxt_re_build_send_wqe(qp, wr, &wqe); 2289 if (!rc) 2290 rc = bnxt_qplib_post_send(&qp->qplib_qp, &wqe); 2291 bad: 2292 if (rc) { 2293 dev_err(rdev_to_dev(rdev), 2294 "Post send failed opcode = %#x rc = %d", 2295 wr->opcode, rc); 2296 break; 2297 } 2298 wr = wr->next; 2299 } 2300 bnxt_qplib_post_send_db(&qp->qplib_qp); 2301 bnxt_ud_qp_hw_stall_workaround(qp); 2302 spin_unlock_irqrestore(&qp->sq_lock, flags); 2303 return rc; 2304 } 2305 2306 int bnxt_re_post_send(struct ib_qp *ib_qp, const struct ib_send_wr *wr, 2307 const struct ib_send_wr **bad_wr) 2308 { 2309 struct bnxt_re_qp *qp = container_of(ib_qp, struct bnxt_re_qp, ib_qp); 2310 struct bnxt_qplib_swqe wqe; 2311 int rc = 0, payload_sz = 0; 2312 unsigned long flags; 2313 2314 spin_lock_irqsave(&qp->sq_lock, flags); 2315 while (wr) { 2316 /* House keeping */ 2317 memset(&wqe, 0, sizeof(wqe)); 2318 2319 /* Common */ 2320 wqe.num_sge = wr->num_sge; 2321 if (wr->num_sge > qp->qplib_qp.sq.max_sge) { 2322 dev_err(rdev_to_dev(qp->rdev), 2323 "Limit exceeded for Send SGEs"); 2324 rc = -EINVAL; 2325 goto bad; 2326 } 2327 2328 payload_sz = bnxt_re_copy_wr_payload(qp->rdev, wr, &wqe); 2329 if (payload_sz < 0) { 2330 rc = -EINVAL; 2331 goto bad; 2332 } 2333 wqe.wr_id = wr->wr_id; 2334 2335 switch (wr->opcode) { 2336 case IB_WR_SEND: 2337 case IB_WR_SEND_WITH_IMM: 2338 if (qp->qplib_qp.type == CMDQ_CREATE_QP1_TYPE_GSI) { 2339 rc = bnxt_re_build_qp1_send_v2(qp, wr, &wqe, 2340 payload_sz); 2341 if (rc) 2342 goto bad; 2343 wqe.rawqp1.lflags |= 2344 SQ_SEND_RAWETH_QP1_LFLAGS_ROCE_CRC; 2345 } 2346 switch (wr->send_flags) { 2347 case IB_SEND_IP_CSUM: 2348 wqe.rawqp1.lflags |= 2349 SQ_SEND_RAWETH_QP1_LFLAGS_IP_CHKSUM; 2350 break; 2351 default: 2352 break; 2353 } 2354 /* fall through */ 2355 case IB_WR_SEND_WITH_INV: 2356 rc = bnxt_re_build_send_wqe(qp, wr, &wqe); 2357 break; 2358 case IB_WR_RDMA_WRITE: 2359 case IB_WR_RDMA_WRITE_WITH_IMM: 2360 case IB_WR_RDMA_READ: 2361 rc = bnxt_re_build_rdma_wqe(wr, &wqe); 2362 break; 2363 case IB_WR_ATOMIC_CMP_AND_SWP: 2364 case IB_WR_ATOMIC_FETCH_AND_ADD: 2365 rc = bnxt_re_build_atomic_wqe(wr, &wqe); 2366 break; 2367 case IB_WR_RDMA_READ_WITH_INV: 2368 dev_err(rdev_to_dev(qp->rdev), 2369 "RDMA Read with Invalidate is not supported"); 2370 rc = -EINVAL; 2371 goto bad; 2372 case IB_WR_LOCAL_INV: 2373 rc = bnxt_re_build_inv_wqe(wr, &wqe); 2374 break; 2375 case IB_WR_REG_MR: 2376 rc = bnxt_re_build_reg_wqe(reg_wr(wr), &wqe); 2377 break; 2378 default: 2379 /* Unsupported WRs */ 2380 dev_err(rdev_to_dev(qp->rdev), 2381 "WR (%#x) is not supported", wr->opcode); 2382 rc = -EINVAL; 2383 goto bad; 2384 } 2385 if (!rc) 2386 rc = bnxt_qplib_post_send(&qp->qplib_qp, &wqe); 2387 bad: 2388 if (rc) { 2389 dev_err(rdev_to_dev(qp->rdev), 2390 "post_send failed op:%#x qps = %#x rc = %d\n", 2391 wr->opcode, qp->qplib_qp.state, rc); 2392 *bad_wr = wr; 2393 break; 2394 } 2395 wr = wr->next; 2396 } 2397 bnxt_qplib_post_send_db(&qp->qplib_qp); 2398 bnxt_ud_qp_hw_stall_workaround(qp); 2399 spin_unlock_irqrestore(&qp->sq_lock, flags); 2400 2401 return rc; 2402 } 2403 2404 static int bnxt_re_post_recv_shadow_qp(struct bnxt_re_dev *rdev, 2405 struct bnxt_re_qp *qp, 2406 const struct ib_recv_wr *wr) 2407 { 2408 struct bnxt_qplib_swqe wqe; 2409 int rc = 0; 2410 2411 memset(&wqe, 0, sizeof(wqe)); 2412 while (wr) { 2413 /* House keeping */ 2414 memset(&wqe, 0, sizeof(wqe)); 2415 2416 /* Common */ 2417 wqe.num_sge = wr->num_sge; 2418 if (wr->num_sge > qp->qplib_qp.rq.max_sge) { 2419 dev_err(rdev_to_dev(rdev), 2420 "Limit exceeded for Receive SGEs"); 2421 rc = -EINVAL; 2422 break; 2423 } 2424 bnxt_re_build_sgl(wr->sg_list, wqe.sg_list, wr->num_sge); 2425 wqe.wr_id = wr->wr_id; 2426 wqe.type = BNXT_QPLIB_SWQE_TYPE_RECV; 2427 2428 rc = bnxt_qplib_post_recv(&qp->qplib_qp, &wqe); 2429 if (rc) 2430 break; 2431 2432 wr = wr->next; 2433 } 2434 if (!rc) 2435 bnxt_qplib_post_recv_db(&qp->qplib_qp); 2436 return rc; 2437 } 2438 2439 int bnxt_re_post_recv(struct ib_qp *ib_qp, const struct ib_recv_wr *wr, 2440 const struct ib_recv_wr **bad_wr) 2441 { 2442 struct bnxt_re_qp *qp = container_of(ib_qp, struct bnxt_re_qp, ib_qp); 2443 struct bnxt_qplib_swqe wqe; 2444 int rc = 0, payload_sz = 0; 2445 unsigned long flags; 2446 u32 count = 0; 2447 2448 spin_lock_irqsave(&qp->rq_lock, flags); 2449 while (wr) { 2450 /* House keeping */ 2451 memset(&wqe, 0, sizeof(wqe)); 2452 2453 /* Common */ 2454 wqe.num_sge = wr->num_sge; 2455 if (wr->num_sge > qp->qplib_qp.rq.max_sge) { 2456 dev_err(rdev_to_dev(qp->rdev), 2457 "Limit exceeded for Receive SGEs"); 2458 rc = -EINVAL; 2459 *bad_wr = wr; 2460 break; 2461 } 2462 2463 payload_sz = bnxt_re_build_sgl(wr->sg_list, wqe.sg_list, 2464 wr->num_sge); 2465 wqe.wr_id = wr->wr_id; 2466 wqe.type = BNXT_QPLIB_SWQE_TYPE_RECV; 2467 2468 if (ib_qp->qp_type == IB_QPT_GSI && 2469 qp->qplib_qp.type != CMDQ_CREATE_QP_TYPE_GSI) 2470 rc = bnxt_re_build_qp1_shadow_qp_recv(qp, wr, &wqe, 2471 payload_sz); 2472 if (!rc) 2473 rc = bnxt_qplib_post_recv(&qp->qplib_qp, &wqe); 2474 if (rc) { 2475 *bad_wr = wr; 2476 break; 2477 } 2478 2479 /* Ring DB if the RQEs posted reaches a threshold value */ 2480 if (++count >= BNXT_RE_RQ_WQE_THRESHOLD) { 2481 bnxt_qplib_post_recv_db(&qp->qplib_qp); 2482 count = 0; 2483 } 2484 2485 wr = wr->next; 2486 } 2487 2488 if (count) 2489 bnxt_qplib_post_recv_db(&qp->qplib_qp); 2490 2491 spin_unlock_irqrestore(&qp->rq_lock, flags); 2492 2493 return rc; 2494 } 2495 2496 /* Completion Queues */ 2497 void bnxt_re_destroy_cq(struct ib_cq *ib_cq, struct ib_udata *udata) 2498 { 2499 struct bnxt_re_cq *cq; 2500 struct bnxt_qplib_nq *nq; 2501 struct bnxt_re_dev *rdev; 2502 2503 cq = container_of(ib_cq, struct bnxt_re_cq, ib_cq); 2504 rdev = cq->rdev; 2505 nq = cq->qplib_cq.nq; 2506 2507 bnxt_qplib_destroy_cq(&rdev->qplib_res, &cq->qplib_cq); 2508 ib_umem_release(cq->umem); 2509 2510 atomic_dec(&rdev->cq_count); 2511 nq->budget--; 2512 kfree(cq->cql); 2513 } 2514 2515 int bnxt_re_create_cq(struct ib_cq *ibcq, const struct ib_cq_init_attr *attr, 2516 struct ib_udata *udata) 2517 { 2518 struct bnxt_re_dev *rdev = to_bnxt_re_dev(ibcq->device, ibdev); 2519 struct bnxt_qplib_dev_attr *dev_attr = &rdev->dev_attr; 2520 struct bnxt_re_cq *cq = container_of(ibcq, struct bnxt_re_cq, ib_cq); 2521 int rc, entries; 2522 int cqe = attr->cqe; 2523 struct bnxt_qplib_nq *nq = NULL; 2524 unsigned int nq_alloc_cnt; 2525 2526 /* Validate CQ fields */ 2527 if (cqe < 1 || cqe > dev_attr->max_cq_wqes) { 2528 dev_err(rdev_to_dev(rdev), "Failed to create CQ -max exceeded"); 2529 return -EINVAL; 2530 } 2531 2532 cq->rdev = rdev; 2533 cq->qplib_cq.cq_handle = (u64)(unsigned long)(&cq->qplib_cq); 2534 2535 entries = roundup_pow_of_two(cqe + 1); 2536 if (entries > dev_attr->max_cq_wqes + 1) 2537 entries = dev_attr->max_cq_wqes + 1; 2538 2539 if (udata) { 2540 struct bnxt_re_cq_req req; 2541 struct bnxt_re_ucontext *uctx = rdma_udata_to_drv_context( 2542 udata, struct bnxt_re_ucontext, ib_uctx); 2543 if (ib_copy_from_udata(&req, udata, sizeof(req))) { 2544 rc = -EFAULT; 2545 goto fail; 2546 } 2547 2548 cq->umem = ib_umem_get(udata, req.cq_va, 2549 entries * sizeof(struct cq_base), 2550 IB_ACCESS_LOCAL_WRITE); 2551 if (IS_ERR(cq->umem)) { 2552 rc = PTR_ERR(cq->umem); 2553 goto fail; 2554 } 2555 cq->qplib_cq.sg_info.sglist = cq->umem->sg_head.sgl; 2556 cq->qplib_cq.sg_info.npages = ib_umem_num_pages(cq->umem); 2557 cq->qplib_cq.sg_info.nmap = cq->umem->nmap; 2558 cq->qplib_cq.dpi = &uctx->dpi; 2559 } else { 2560 cq->max_cql = min_t(u32, entries, MAX_CQL_PER_POLL); 2561 cq->cql = kcalloc(cq->max_cql, sizeof(struct bnxt_qplib_cqe), 2562 GFP_KERNEL); 2563 if (!cq->cql) { 2564 rc = -ENOMEM; 2565 goto fail; 2566 } 2567 2568 cq->qplib_cq.dpi = &rdev->dpi_privileged; 2569 } 2570 /* 2571 * Allocating the NQ in a round robin fashion. nq_alloc_cnt is a 2572 * used for getting the NQ index. 2573 */ 2574 nq_alloc_cnt = atomic_inc_return(&rdev->nq_alloc_cnt); 2575 nq = &rdev->nq[nq_alloc_cnt % (rdev->num_msix - 1)]; 2576 cq->qplib_cq.max_wqe = entries; 2577 cq->qplib_cq.cnq_hw_ring_id = nq->ring_id; 2578 cq->qplib_cq.nq = nq; 2579 2580 rc = bnxt_qplib_create_cq(&rdev->qplib_res, &cq->qplib_cq); 2581 if (rc) { 2582 dev_err(rdev_to_dev(rdev), "Failed to create HW CQ"); 2583 goto fail; 2584 } 2585 2586 cq->ib_cq.cqe = entries; 2587 cq->cq_period = cq->qplib_cq.period; 2588 nq->budget++; 2589 2590 atomic_inc(&rdev->cq_count); 2591 spin_lock_init(&cq->cq_lock); 2592 2593 if (udata) { 2594 struct bnxt_re_cq_resp resp; 2595 2596 resp.cqid = cq->qplib_cq.id; 2597 resp.tail = cq->qplib_cq.hwq.cons; 2598 resp.phase = cq->qplib_cq.period; 2599 resp.rsvd = 0; 2600 rc = ib_copy_to_udata(udata, &resp, sizeof(resp)); 2601 if (rc) { 2602 dev_err(rdev_to_dev(rdev), "Failed to copy CQ udata"); 2603 bnxt_qplib_destroy_cq(&rdev->qplib_res, &cq->qplib_cq); 2604 goto c2fail; 2605 } 2606 } 2607 2608 return 0; 2609 2610 c2fail: 2611 ib_umem_release(cq->umem); 2612 fail: 2613 kfree(cq->cql); 2614 return rc; 2615 } 2616 2617 static u8 __req_to_ib_wc_status(u8 qstatus) 2618 { 2619 switch (qstatus) { 2620 case CQ_REQ_STATUS_OK: 2621 return IB_WC_SUCCESS; 2622 case CQ_REQ_STATUS_BAD_RESPONSE_ERR: 2623 return IB_WC_BAD_RESP_ERR; 2624 case CQ_REQ_STATUS_LOCAL_LENGTH_ERR: 2625 return IB_WC_LOC_LEN_ERR; 2626 case CQ_REQ_STATUS_LOCAL_QP_OPERATION_ERR: 2627 return IB_WC_LOC_QP_OP_ERR; 2628 case CQ_REQ_STATUS_LOCAL_PROTECTION_ERR: 2629 return IB_WC_LOC_PROT_ERR; 2630 case CQ_REQ_STATUS_MEMORY_MGT_OPERATION_ERR: 2631 return IB_WC_GENERAL_ERR; 2632 case CQ_REQ_STATUS_REMOTE_INVALID_REQUEST_ERR: 2633 return IB_WC_REM_INV_REQ_ERR; 2634 case CQ_REQ_STATUS_REMOTE_ACCESS_ERR: 2635 return IB_WC_REM_ACCESS_ERR; 2636 case CQ_REQ_STATUS_REMOTE_OPERATION_ERR: 2637 return IB_WC_REM_OP_ERR; 2638 case CQ_REQ_STATUS_RNR_NAK_RETRY_CNT_ERR: 2639 return IB_WC_RNR_RETRY_EXC_ERR; 2640 case CQ_REQ_STATUS_TRANSPORT_RETRY_CNT_ERR: 2641 return IB_WC_RETRY_EXC_ERR; 2642 case CQ_REQ_STATUS_WORK_REQUEST_FLUSHED_ERR: 2643 return IB_WC_WR_FLUSH_ERR; 2644 default: 2645 return IB_WC_GENERAL_ERR; 2646 } 2647 return 0; 2648 } 2649 2650 static u8 __rawqp1_to_ib_wc_status(u8 qstatus) 2651 { 2652 switch (qstatus) { 2653 case CQ_RES_RAWETH_QP1_STATUS_OK: 2654 return IB_WC_SUCCESS; 2655 case CQ_RES_RAWETH_QP1_STATUS_LOCAL_ACCESS_ERROR: 2656 return IB_WC_LOC_ACCESS_ERR; 2657 case CQ_RES_RAWETH_QP1_STATUS_HW_LOCAL_LENGTH_ERR: 2658 return IB_WC_LOC_LEN_ERR; 2659 case CQ_RES_RAWETH_QP1_STATUS_LOCAL_PROTECTION_ERR: 2660 return IB_WC_LOC_PROT_ERR; 2661 case CQ_RES_RAWETH_QP1_STATUS_LOCAL_QP_OPERATION_ERR: 2662 return IB_WC_LOC_QP_OP_ERR; 2663 case CQ_RES_RAWETH_QP1_STATUS_MEMORY_MGT_OPERATION_ERR: 2664 return IB_WC_GENERAL_ERR; 2665 case CQ_RES_RAWETH_QP1_STATUS_WORK_REQUEST_FLUSHED_ERR: 2666 return IB_WC_WR_FLUSH_ERR; 2667 case CQ_RES_RAWETH_QP1_STATUS_HW_FLUSH_ERR: 2668 return IB_WC_WR_FLUSH_ERR; 2669 default: 2670 return IB_WC_GENERAL_ERR; 2671 } 2672 } 2673 2674 static u8 __rc_to_ib_wc_status(u8 qstatus) 2675 { 2676 switch (qstatus) { 2677 case CQ_RES_RC_STATUS_OK: 2678 return IB_WC_SUCCESS; 2679 case CQ_RES_RC_STATUS_LOCAL_ACCESS_ERROR: 2680 return IB_WC_LOC_ACCESS_ERR; 2681 case CQ_RES_RC_STATUS_LOCAL_LENGTH_ERR: 2682 return IB_WC_LOC_LEN_ERR; 2683 case CQ_RES_RC_STATUS_LOCAL_PROTECTION_ERR: 2684 return IB_WC_LOC_PROT_ERR; 2685 case CQ_RES_RC_STATUS_LOCAL_QP_OPERATION_ERR: 2686 return IB_WC_LOC_QP_OP_ERR; 2687 case CQ_RES_RC_STATUS_MEMORY_MGT_OPERATION_ERR: 2688 return IB_WC_GENERAL_ERR; 2689 case CQ_RES_RC_STATUS_REMOTE_INVALID_REQUEST_ERR: 2690 return IB_WC_REM_INV_REQ_ERR; 2691 case CQ_RES_RC_STATUS_WORK_REQUEST_FLUSHED_ERR: 2692 return IB_WC_WR_FLUSH_ERR; 2693 case CQ_RES_RC_STATUS_HW_FLUSH_ERR: 2694 return IB_WC_WR_FLUSH_ERR; 2695 default: 2696 return IB_WC_GENERAL_ERR; 2697 } 2698 } 2699 2700 static void bnxt_re_process_req_wc(struct ib_wc *wc, struct bnxt_qplib_cqe *cqe) 2701 { 2702 switch (cqe->type) { 2703 case BNXT_QPLIB_SWQE_TYPE_SEND: 2704 wc->opcode = IB_WC_SEND; 2705 break; 2706 case BNXT_QPLIB_SWQE_TYPE_SEND_WITH_IMM: 2707 wc->opcode = IB_WC_SEND; 2708 wc->wc_flags |= IB_WC_WITH_IMM; 2709 break; 2710 case BNXT_QPLIB_SWQE_TYPE_SEND_WITH_INV: 2711 wc->opcode = IB_WC_SEND; 2712 wc->wc_flags |= IB_WC_WITH_INVALIDATE; 2713 break; 2714 case BNXT_QPLIB_SWQE_TYPE_RDMA_WRITE: 2715 wc->opcode = IB_WC_RDMA_WRITE; 2716 break; 2717 case BNXT_QPLIB_SWQE_TYPE_RDMA_WRITE_WITH_IMM: 2718 wc->opcode = IB_WC_RDMA_WRITE; 2719 wc->wc_flags |= IB_WC_WITH_IMM; 2720 break; 2721 case BNXT_QPLIB_SWQE_TYPE_RDMA_READ: 2722 wc->opcode = IB_WC_RDMA_READ; 2723 break; 2724 case BNXT_QPLIB_SWQE_TYPE_ATOMIC_CMP_AND_SWP: 2725 wc->opcode = IB_WC_COMP_SWAP; 2726 break; 2727 case BNXT_QPLIB_SWQE_TYPE_ATOMIC_FETCH_AND_ADD: 2728 wc->opcode = IB_WC_FETCH_ADD; 2729 break; 2730 case BNXT_QPLIB_SWQE_TYPE_LOCAL_INV: 2731 wc->opcode = IB_WC_LOCAL_INV; 2732 break; 2733 case BNXT_QPLIB_SWQE_TYPE_REG_MR: 2734 wc->opcode = IB_WC_REG_MR; 2735 break; 2736 default: 2737 wc->opcode = IB_WC_SEND; 2738 break; 2739 } 2740 2741 wc->status = __req_to_ib_wc_status(cqe->status); 2742 } 2743 2744 static int bnxt_re_check_packet_type(u16 raweth_qp1_flags, 2745 u16 raweth_qp1_flags2) 2746 { 2747 bool is_ipv6 = false, is_ipv4 = false; 2748 2749 /* raweth_qp1_flags Bit 9-6 indicates itype */ 2750 if ((raweth_qp1_flags & CQ_RES_RAWETH_QP1_RAWETH_QP1_FLAGS_ITYPE_ROCE) 2751 != CQ_RES_RAWETH_QP1_RAWETH_QP1_FLAGS_ITYPE_ROCE) 2752 return -1; 2753 2754 if (raweth_qp1_flags2 & 2755 CQ_RES_RAWETH_QP1_RAWETH_QP1_FLAGS2_IP_CS_CALC && 2756 raweth_qp1_flags2 & 2757 CQ_RES_RAWETH_QP1_RAWETH_QP1_FLAGS2_L4_CS_CALC) { 2758 /* raweth_qp1_flags2 Bit 8 indicates ip_type. 0-v4 1 - v6 */ 2759 (raweth_qp1_flags2 & 2760 CQ_RES_RAWETH_QP1_RAWETH_QP1_FLAGS2_IP_TYPE) ? 2761 (is_ipv6 = true) : (is_ipv4 = true); 2762 return ((is_ipv6) ? 2763 BNXT_RE_ROCEV2_IPV6_PACKET : 2764 BNXT_RE_ROCEV2_IPV4_PACKET); 2765 } else { 2766 return BNXT_RE_ROCE_V1_PACKET; 2767 } 2768 } 2769 2770 static int bnxt_re_to_ib_nw_type(int nw_type) 2771 { 2772 u8 nw_hdr_type = 0xFF; 2773 2774 switch (nw_type) { 2775 case BNXT_RE_ROCE_V1_PACKET: 2776 nw_hdr_type = RDMA_NETWORK_ROCE_V1; 2777 break; 2778 case BNXT_RE_ROCEV2_IPV4_PACKET: 2779 nw_hdr_type = RDMA_NETWORK_IPV4; 2780 break; 2781 case BNXT_RE_ROCEV2_IPV6_PACKET: 2782 nw_hdr_type = RDMA_NETWORK_IPV6; 2783 break; 2784 } 2785 return nw_hdr_type; 2786 } 2787 2788 static bool bnxt_re_is_loopback_packet(struct bnxt_re_dev *rdev, 2789 void *rq_hdr_buf) 2790 { 2791 u8 *tmp_buf = NULL; 2792 struct ethhdr *eth_hdr; 2793 u16 eth_type; 2794 bool rc = false; 2795 2796 tmp_buf = (u8 *)rq_hdr_buf; 2797 /* 2798 * If dest mac is not same as I/F mac, this could be a 2799 * loopback address or multicast address, check whether 2800 * it is a loopback packet 2801 */ 2802 if (!ether_addr_equal(tmp_buf, rdev->netdev->dev_addr)) { 2803 tmp_buf += 4; 2804 /* Check the ether type */ 2805 eth_hdr = (struct ethhdr *)tmp_buf; 2806 eth_type = ntohs(eth_hdr->h_proto); 2807 switch (eth_type) { 2808 case ETH_P_IBOE: 2809 rc = true; 2810 break; 2811 case ETH_P_IP: 2812 case ETH_P_IPV6: { 2813 u32 len; 2814 struct udphdr *udp_hdr; 2815 2816 len = (eth_type == ETH_P_IP ? sizeof(struct iphdr) : 2817 sizeof(struct ipv6hdr)); 2818 tmp_buf += sizeof(struct ethhdr) + len; 2819 udp_hdr = (struct udphdr *)tmp_buf; 2820 if (ntohs(udp_hdr->dest) == 2821 ROCE_V2_UDP_DPORT) 2822 rc = true; 2823 break; 2824 } 2825 default: 2826 break; 2827 } 2828 } 2829 2830 return rc; 2831 } 2832 2833 static int bnxt_re_process_raw_qp_pkt_rx(struct bnxt_re_qp *qp1_qp, 2834 struct bnxt_qplib_cqe *cqe) 2835 { 2836 struct bnxt_re_dev *rdev = qp1_qp->rdev; 2837 struct bnxt_re_sqp_entries *sqp_entry = NULL; 2838 struct bnxt_re_qp *qp = rdev->qp1_sqp; 2839 struct ib_send_wr *swr; 2840 struct ib_ud_wr udwr; 2841 struct ib_recv_wr rwr; 2842 int pkt_type = 0; 2843 u32 tbl_idx; 2844 void *rq_hdr_buf; 2845 dma_addr_t rq_hdr_buf_map; 2846 dma_addr_t shrq_hdr_buf_map; 2847 u32 offset = 0; 2848 u32 skip_bytes = 0; 2849 struct ib_sge s_sge[2]; 2850 struct ib_sge r_sge[2]; 2851 int rc; 2852 2853 memset(&udwr, 0, sizeof(udwr)); 2854 memset(&rwr, 0, sizeof(rwr)); 2855 memset(&s_sge, 0, sizeof(s_sge)); 2856 memset(&r_sge, 0, sizeof(r_sge)); 2857 2858 swr = &udwr.wr; 2859 tbl_idx = cqe->wr_id; 2860 2861 rq_hdr_buf = qp1_qp->qplib_qp.rq_hdr_buf + 2862 (tbl_idx * qp1_qp->qplib_qp.rq_hdr_buf_size); 2863 rq_hdr_buf_map = bnxt_qplib_get_qp_buf_from_index(&qp1_qp->qplib_qp, 2864 tbl_idx); 2865 2866 /* Shadow QP header buffer */ 2867 shrq_hdr_buf_map = bnxt_qplib_get_qp_buf_from_index(&qp->qplib_qp, 2868 tbl_idx); 2869 sqp_entry = &rdev->sqp_tbl[tbl_idx]; 2870 2871 /* Store this cqe */ 2872 memcpy(&sqp_entry->cqe, cqe, sizeof(struct bnxt_qplib_cqe)); 2873 sqp_entry->qp1_qp = qp1_qp; 2874 2875 /* Find packet type from the cqe */ 2876 2877 pkt_type = bnxt_re_check_packet_type(cqe->raweth_qp1_flags, 2878 cqe->raweth_qp1_flags2); 2879 if (pkt_type < 0) { 2880 dev_err(rdev_to_dev(rdev), "Invalid packet\n"); 2881 return -EINVAL; 2882 } 2883 2884 /* Adjust the offset for the user buffer and post in the rq */ 2885 2886 if (pkt_type == BNXT_RE_ROCEV2_IPV4_PACKET) 2887 offset = 20; 2888 2889 /* 2890 * QP1 loopback packet has 4 bytes of internal header before 2891 * ether header. Skip these four bytes. 2892 */ 2893 if (bnxt_re_is_loopback_packet(rdev, rq_hdr_buf)) 2894 skip_bytes = 4; 2895 2896 /* First send SGE . Skip the ether header*/ 2897 s_sge[0].addr = rq_hdr_buf_map + BNXT_QPLIB_MAX_QP1_RQ_ETH_HDR_SIZE 2898 + skip_bytes; 2899 s_sge[0].lkey = 0xFFFFFFFF; 2900 s_sge[0].length = offset ? BNXT_QPLIB_MAX_GRH_HDR_SIZE_IPV4 : 2901 BNXT_QPLIB_MAX_GRH_HDR_SIZE_IPV6; 2902 2903 /* Second Send SGE */ 2904 s_sge[1].addr = s_sge[0].addr + s_sge[0].length + 2905 BNXT_QPLIB_MAX_QP1_RQ_BDETH_HDR_SIZE; 2906 if (pkt_type != BNXT_RE_ROCE_V1_PACKET) 2907 s_sge[1].addr += 8; 2908 s_sge[1].lkey = 0xFFFFFFFF; 2909 s_sge[1].length = 256; 2910 2911 /* First recv SGE */ 2912 2913 r_sge[0].addr = shrq_hdr_buf_map; 2914 r_sge[0].lkey = 0xFFFFFFFF; 2915 r_sge[0].length = 40; 2916 2917 r_sge[1].addr = sqp_entry->sge.addr + offset; 2918 r_sge[1].lkey = sqp_entry->sge.lkey; 2919 r_sge[1].length = BNXT_QPLIB_MAX_GRH_HDR_SIZE_IPV6 + 256 - offset; 2920 2921 /* Create receive work request */ 2922 rwr.num_sge = 2; 2923 rwr.sg_list = r_sge; 2924 rwr.wr_id = tbl_idx; 2925 rwr.next = NULL; 2926 2927 rc = bnxt_re_post_recv_shadow_qp(rdev, qp, &rwr); 2928 if (rc) { 2929 dev_err(rdev_to_dev(rdev), 2930 "Failed to post Rx buffers to shadow QP"); 2931 return -ENOMEM; 2932 } 2933 2934 swr->num_sge = 2; 2935 swr->sg_list = s_sge; 2936 swr->wr_id = tbl_idx; 2937 swr->opcode = IB_WR_SEND; 2938 swr->next = NULL; 2939 2940 udwr.ah = &rdev->sqp_ah->ib_ah; 2941 udwr.remote_qpn = rdev->qp1_sqp->qplib_qp.id; 2942 udwr.remote_qkey = rdev->qp1_sqp->qplib_qp.qkey; 2943 2944 /* post data received in the send queue */ 2945 rc = bnxt_re_post_send_shadow_qp(rdev, qp, swr); 2946 2947 return 0; 2948 } 2949 2950 static void bnxt_re_process_res_rawqp1_wc(struct ib_wc *wc, 2951 struct bnxt_qplib_cqe *cqe) 2952 { 2953 wc->opcode = IB_WC_RECV; 2954 wc->status = __rawqp1_to_ib_wc_status(cqe->status); 2955 wc->wc_flags |= IB_WC_GRH; 2956 } 2957 2958 static bool bnxt_re_is_vlan_pkt(struct bnxt_qplib_cqe *orig_cqe, 2959 u16 *vid, u8 *sl) 2960 { 2961 bool ret = false; 2962 u32 metadata; 2963 u16 tpid; 2964 2965 metadata = orig_cqe->raweth_qp1_metadata; 2966 if (orig_cqe->raweth_qp1_flags2 & 2967 CQ_RES_RAWETH_QP1_RAWETH_QP1_FLAGS2_META_FORMAT_VLAN) { 2968 tpid = ((metadata & 2969 CQ_RES_RAWETH_QP1_RAWETH_QP1_METADATA_TPID_MASK) >> 2970 CQ_RES_RAWETH_QP1_RAWETH_QP1_METADATA_TPID_SFT); 2971 if (tpid == ETH_P_8021Q) { 2972 *vid = metadata & 2973 CQ_RES_RAWETH_QP1_RAWETH_QP1_METADATA_VID_MASK; 2974 *sl = (metadata & 2975 CQ_RES_RAWETH_QP1_RAWETH_QP1_METADATA_PRI_MASK) >> 2976 CQ_RES_RAWETH_QP1_RAWETH_QP1_METADATA_PRI_SFT; 2977 ret = true; 2978 } 2979 } 2980 2981 return ret; 2982 } 2983 2984 static void bnxt_re_process_res_rc_wc(struct ib_wc *wc, 2985 struct bnxt_qplib_cqe *cqe) 2986 { 2987 wc->opcode = IB_WC_RECV; 2988 wc->status = __rc_to_ib_wc_status(cqe->status); 2989 2990 if (cqe->flags & CQ_RES_RC_FLAGS_IMM) 2991 wc->wc_flags |= IB_WC_WITH_IMM; 2992 if (cqe->flags & CQ_RES_RC_FLAGS_INV) 2993 wc->wc_flags |= IB_WC_WITH_INVALIDATE; 2994 if ((cqe->flags & (CQ_RES_RC_FLAGS_RDMA | CQ_RES_RC_FLAGS_IMM)) == 2995 (CQ_RES_RC_FLAGS_RDMA | CQ_RES_RC_FLAGS_IMM)) 2996 wc->opcode = IB_WC_RECV_RDMA_WITH_IMM; 2997 } 2998 2999 static void bnxt_re_process_res_shadow_qp_wc(struct bnxt_re_qp *qp, 3000 struct ib_wc *wc, 3001 struct bnxt_qplib_cqe *cqe) 3002 { 3003 struct bnxt_re_dev *rdev = qp->rdev; 3004 struct bnxt_re_qp *qp1_qp = NULL; 3005 struct bnxt_qplib_cqe *orig_cqe = NULL; 3006 struct bnxt_re_sqp_entries *sqp_entry = NULL; 3007 int nw_type; 3008 u32 tbl_idx; 3009 u16 vlan_id; 3010 u8 sl; 3011 3012 tbl_idx = cqe->wr_id; 3013 3014 sqp_entry = &rdev->sqp_tbl[tbl_idx]; 3015 qp1_qp = sqp_entry->qp1_qp; 3016 orig_cqe = &sqp_entry->cqe; 3017 3018 wc->wr_id = sqp_entry->wrid; 3019 wc->byte_len = orig_cqe->length; 3020 wc->qp = &qp1_qp->ib_qp; 3021 3022 wc->ex.imm_data = orig_cqe->immdata; 3023 wc->src_qp = orig_cqe->src_qp; 3024 memcpy(wc->smac, orig_cqe->smac, ETH_ALEN); 3025 if (bnxt_re_is_vlan_pkt(orig_cqe, &vlan_id, &sl)) { 3026 wc->vlan_id = vlan_id; 3027 wc->sl = sl; 3028 wc->wc_flags |= IB_WC_WITH_VLAN; 3029 } 3030 wc->port_num = 1; 3031 wc->vendor_err = orig_cqe->status; 3032 3033 wc->opcode = IB_WC_RECV; 3034 wc->status = __rawqp1_to_ib_wc_status(orig_cqe->status); 3035 wc->wc_flags |= IB_WC_GRH; 3036 3037 nw_type = bnxt_re_check_packet_type(orig_cqe->raweth_qp1_flags, 3038 orig_cqe->raweth_qp1_flags2); 3039 if (nw_type >= 0) { 3040 wc->network_hdr_type = bnxt_re_to_ib_nw_type(nw_type); 3041 wc->wc_flags |= IB_WC_WITH_NETWORK_HDR_TYPE; 3042 } 3043 } 3044 3045 static void bnxt_re_process_res_ud_wc(struct bnxt_re_qp *qp, 3046 struct ib_wc *wc, 3047 struct bnxt_qplib_cqe *cqe) 3048 { 3049 u8 nw_type; 3050 3051 wc->opcode = IB_WC_RECV; 3052 wc->status = __rc_to_ib_wc_status(cqe->status); 3053 3054 if (cqe->flags & CQ_RES_UD_FLAGS_IMM) 3055 wc->wc_flags |= IB_WC_WITH_IMM; 3056 /* report only on GSI QP for Thor */ 3057 if (qp->qplib_qp.type == CMDQ_CREATE_QP_TYPE_GSI) { 3058 wc->wc_flags |= IB_WC_GRH; 3059 memcpy(wc->smac, cqe->smac, ETH_ALEN); 3060 wc->wc_flags |= IB_WC_WITH_SMAC; 3061 if (cqe->flags & CQ_RES_UD_FLAGS_META_FORMAT_VLAN) { 3062 wc->vlan_id = (cqe->cfa_meta & 0xFFF); 3063 if (wc->vlan_id < 0x1000) 3064 wc->wc_flags |= IB_WC_WITH_VLAN; 3065 } 3066 nw_type = (cqe->flags & CQ_RES_UD_FLAGS_ROCE_IP_VER_MASK) >> 3067 CQ_RES_UD_FLAGS_ROCE_IP_VER_SFT; 3068 wc->network_hdr_type = bnxt_re_to_ib_nw_type(nw_type); 3069 wc->wc_flags |= IB_WC_WITH_NETWORK_HDR_TYPE; 3070 } 3071 3072 } 3073 3074 static int send_phantom_wqe(struct bnxt_re_qp *qp) 3075 { 3076 struct bnxt_qplib_qp *lib_qp = &qp->qplib_qp; 3077 unsigned long flags; 3078 int rc = 0; 3079 3080 spin_lock_irqsave(&qp->sq_lock, flags); 3081 3082 rc = bnxt_re_bind_fence_mw(lib_qp); 3083 if (!rc) { 3084 lib_qp->sq.phantom_wqe_cnt++; 3085 dev_dbg(&lib_qp->sq.hwq.pdev->dev, 3086 "qp %#x sq->prod %#x sw_prod %#x phantom_wqe_cnt %d\n", 3087 lib_qp->id, lib_qp->sq.hwq.prod, 3088 HWQ_CMP(lib_qp->sq.hwq.prod, &lib_qp->sq.hwq), 3089 lib_qp->sq.phantom_wqe_cnt); 3090 } 3091 3092 spin_unlock_irqrestore(&qp->sq_lock, flags); 3093 return rc; 3094 } 3095 3096 int bnxt_re_poll_cq(struct ib_cq *ib_cq, int num_entries, struct ib_wc *wc) 3097 { 3098 struct bnxt_re_cq *cq = container_of(ib_cq, struct bnxt_re_cq, ib_cq); 3099 struct bnxt_re_qp *qp; 3100 struct bnxt_qplib_cqe *cqe; 3101 int i, ncqe, budget; 3102 struct bnxt_qplib_q *sq; 3103 struct bnxt_qplib_qp *lib_qp; 3104 u32 tbl_idx; 3105 struct bnxt_re_sqp_entries *sqp_entry = NULL; 3106 unsigned long flags; 3107 3108 spin_lock_irqsave(&cq->cq_lock, flags); 3109 budget = min_t(u32, num_entries, cq->max_cql); 3110 num_entries = budget; 3111 if (!cq->cql) { 3112 dev_err(rdev_to_dev(cq->rdev), "POLL CQ : no CQL to use"); 3113 goto exit; 3114 } 3115 cqe = &cq->cql[0]; 3116 while (budget) { 3117 lib_qp = NULL; 3118 ncqe = bnxt_qplib_poll_cq(&cq->qplib_cq, cqe, budget, &lib_qp); 3119 if (lib_qp) { 3120 sq = &lib_qp->sq; 3121 if (sq->send_phantom) { 3122 qp = container_of(lib_qp, 3123 struct bnxt_re_qp, qplib_qp); 3124 if (send_phantom_wqe(qp) == -ENOMEM) 3125 dev_err(rdev_to_dev(cq->rdev), 3126 "Phantom failed! Scheduled to send again\n"); 3127 else 3128 sq->send_phantom = false; 3129 } 3130 } 3131 if (ncqe < budget) 3132 ncqe += bnxt_qplib_process_flush_list(&cq->qplib_cq, 3133 cqe + ncqe, 3134 budget - ncqe); 3135 3136 if (!ncqe) 3137 break; 3138 3139 for (i = 0; i < ncqe; i++, cqe++) { 3140 /* Transcribe each qplib_wqe back to ib_wc */ 3141 memset(wc, 0, sizeof(*wc)); 3142 3143 wc->wr_id = cqe->wr_id; 3144 wc->byte_len = cqe->length; 3145 qp = container_of 3146 ((struct bnxt_qplib_qp *) 3147 (unsigned long)(cqe->qp_handle), 3148 struct bnxt_re_qp, qplib_qp); 3149 if (!qp) { 3150 dev_err(rdev_to_dev(cq->rdev), 3151 "POLL CQ : bad QP handle"); 3152 continue; 3153 } 3154 wc->qp = &qp->ib_qp; 3155 wc->ex.imm_data = cqe->immdata; 3156 wc->src_qp = cqe->src_qp; 3157 memcpy(wc->smac, cqe->smac, ETH_ALEN); 3158 wc->port_num = 1; 3159 wc->vendor_err = cqe->status; 3160 3161 switch (cqe->opcode) { 3162 case CQ_BASE_CQE_TYPE_REQ: 3163 if (qp->rdev->qp1_sqp && qp->qplib_qp.id == 3164 qp->rdev->qp1_sqp->qplib_qp.id) { 3165 /* Handle this completion with 3166 * the stored completion 3167 */ 3168 memset(wc, 0, sizeof(*wc)); 3169 continue; 3170 } 3171 bnxt_re_process_req_wc(wc, cqe); 3172 break; 3173 case CQ_BASE_CQE_TYPE_RES_RAWETH_QP1: 3174 if (!cqe->status) { 3175 int rc = 0; 3176 3177 rc = bnxt_re_process_raw_qp_pkt_rx 3178 (qp, cqe); 3179 if (!rc) { 3180 memset(wc, 0, sizeof(*wc)); 3181 continue; 3182 } 3183 cqe->status = -1; 3184 } 3185 /* Errors need not be looped back. 3186 * But change the wr_id to the one 3187 * stored in the table 3188 */ 3189 tbl_idx = cqe->wr_id; 3190 sqp_entry = &cq->rdev->sqp_tbl[tbl_idx]; 3191 wc->wr_id = sqp_entry->wrid; 3192 bnxt_re_process_res_rawqp1_wc(wc, cqe); 3193 break; 3194 case CQ_BASE_CQE_TYPE_RES_RC: 3195 bnxt_re_process_res_rc_wc(wc, cqe); 3196 break; 3197 case CQ_BASE_CQE_TYPE_RES_UD: 3198 if (qp->rdev->qp1_sqp && qp->qplib_qp.id == 3199 qp->rdev->qp1_sqp->qplib_qp.id) { 3200 /* Handle this completion with 3201 * the stored completion 3202 */ 3203 if (cqe->status) { 3204 continue; 3205 } else { 3206 bnxt_re_process_res_shadow_qp_wc 3207 (qp, wc, cqe); 3208 break; 3209 } 3210 } 3211 bnxt_re_process_res_ud_wc(qp, wc, cqe); 3212 break; 3213 default: 3214 dev_err(rdev_to_dev(cq->rdev), 3215 "POLL CQ : type 0x%x not handled", 3216 cqe->opcode); 3217 continue; 3218 } 3219 wc++; 3220 budget--; 3221 } 3222 } 3223 exit: 3224 spin_unlock_irqrestore(&cq->cq_lock, flags); 3225 return num_entries - budget; 3226 } 3227 3228 int bnxt_re_req_notify_cq(struct ib_cq *ib_cq, 3229 enum ib_cq_notify_flags ib_cqn_flags) 3230 { 3231 struct bnxt_re_cq *cq = container_of(ib_cq, struct bnxt_re_cq, ib_cq); 3232 int type = 0, rc = 0; 3233 unsigned long flags; 3234 3235 spin_lock_irqsave(&cq->cq_lock, flags); 3236 /* Trigger on the very next completion */ 3237 if (ib_cqn_flags & IB_CQ_NEXT_COMP) 3238 type = DBC_DBC_TYPE_CQ_ARMALL; 3239 /* Trigger on the next solicited completion */ 3240 else if (ib_cqn_flags & IB_CQ_SOLICITED) 3241 type = DBC_DBC_TYPE_CQ_ARMSE; 3242 3243 /* Poll to see if there are missed events */ 3244 if ((ib_cqn_flags & IB_CQ_REPORT_MISSED_EVENTS) && 3245 !(bnxt_qplib_is_cq_empty(&cq->qplib_cq))) { 3246 rc = 1; 3247 goto exit; 3248 } 3249 bnxt_qplib_req_notify_cq(&cq->qplib_cq, type); 3250 3251 exit: 3252 spin_unlock_irqrestore(&cq->cq_lock, flags); 3253 return rc; 3254 } 3255 3256 /* Memory Regions */ 3257 struct ib_mr *bnxt_re_get_dma_mr(struct ib_pd *ib_pd, int mr_access_flags) 3258 { 3259 struct bnxt_re_pd *pd = container_of(ib_pd, struct bnxt_re_pd, ib_pd); 3260 struct bnxt_re_dev *rdev = pd->rdev; 3261 struct bnxt_re_mr *mr; 3262 u64 pbl = 0; 3263 int rc; 3264 3265 mr = kzalloc(sizeof(*mr), GFP_KERNEL); 3266 if (!mr) 3267 return ERR_PTR(-ENOMEM); 3268 3269 mr->rdev = rdev; 3270 mr->qplib_mr.pd = &pd->qplib_pd; 3271 mr->qplib_mr.flags = __from_ib_access_flags(mr_access_flags); 3272 mr->qplib_mr.type = CMDQ_ALLOCATE_MRW_MRW_FLAGS_PMR; 3273 3274 /* Allocate and register 0 as the address */ 3275 rc = bnxt_qplib_alloc_mrw(&rdev->qplib_res, &mr->qplib_mr); 3276 if (rc) 3277 goto fail; 3278 3279 mr->qplib_mr.hwq.level = PBL_LVL_MAX; 3280 mr->qplib_mr.total_size = -1; /* Infinte length */ 3281 rc = bnxt_qplib_reg_mr(&rdev->qplib_res, &mr->qplib_mr, &pbl, 0, false, 3282 PAGE_SIZE); 3283 if (rc) 3284 goto fail_mr; 3285 3286 mr->ib_mr.lkey = mr->qplib_mr.lkey; 3287 if (mr_access_flags & (IB_ACCESS_REMOTE_WRITE | IB_ACCESS_REMOTE_READ | 3288 IB_ACCESS_REMOTE_ATOMIC)) 3289 mr->ib_mr.rkey = mr->ib_mr.lkey; 3290 atomic_inc(&rdev->mr_count); 3291 3292 return &mr->ib_mr; 3293 3294 fail_mr: 3295 bnxt_qplib_free_mrw(&rdev->qplib_res, &mr->qplib_mr); 3296 fail: 3297 kfree(mr); 3298 return ERR_PTR(rc); 3299 } 3300 3301 int bnxt_re_dereg_mr(struct ib_mr *ib_mr, struct ib_udata *udata) 3302 { 3303 struct bnxt_re_mr *mr = container_of(ib_mr, struct bnxt_re_mr, ib_mr); 3304 struct bnxt_re_dev *rdev = mr->rdev; 3305 int rc; 3306 3307 rc = bnxt_qplib_free_mrw(&rdev->qplib_res, &mr->qplib_mr); 3308 if (rc) 3309 dev_err(rdev_to_dev(rdev), "Dereg MR failed: %#x\n", rc); 3310 3311 if (mr->pages) { 3312 rc = bnxt_qplib_free_fast_reg_page_list(&rdev->qplib_res, 3313 &mr->qplib_frpl); 3314 kfree(mr->pages); 3315 mr->npages = 0; 3316 mr->pages = NULL; 3317 } 3318 ib_umem_release(mr->ib_umem); 3319 3320 kfree(mr); 3321 atomic_dec(&rdev->mr_count); 3322 return rc; 3323 } 3324 3325 static int bnxt_re_set_page(struct ib_mr *ib_mr, u64 addr) 3326 { 3327 struct bnxt_re_mr *mr = container_of(ib_mr, struct bnxt_re_mr, ib_mr); 3328 3329 if (unlikely(mr->npages == mr->qplib_frpl.max_pg_ptrs)) 3330 return -ENOMEM; 3331 3332 mr->pages[mr->npages++] = addr; 3333 return 0; 3334 } 3335 3336 int bnxt_re_map_mr_sg(struct ib_mr *ib_mr, struct scatterlist *sg, int sg_nents, 3337 unsigned int *sg_offset) 3338 { 3339 struct bnxt_re_mr *mr = container_of(ib_mr, struct bnxt_re_mr, ib_mr); 3340 3341 mr->npages = 0; 3342 return ib_sg_to_pages(ib_mr, sg, sg_nents, sg_offset, bnxt_re_set_page); 3343 } 3344 3345 struct ib_mr *bnxt_re_alloc_mr(struct ib_pd *ib_pd, enum ib_mr_type type, 3346 u32 max_num_sg, struct ib_udata *udata) 3347 { 3348 struct bnxt_re_pd *pd = container_of(ib_pd, struct bnxt_re_pd, ib_pd); 3349 struct bnxt_re_dev *rdev = pd->rdev; 3350 struct bnxt_re_mr *mr = NULL; 3351 int rc; 3352 3353 if (type != IB_MR_TYPE_MEM_REG) { 3354 dev_dbg(rdev_to_dev(rdev), "MR type 0x%x not supported", type); 3355 return ERR_PTR(-EINVAL); 3356 } 3357 if (max_num_sg > MAX_PBL_LVL_1_PGS) 3358 return ERR_PTR(-EINVAL); 3359 3360 mr = kzalloc(sizeof(*mr), GFP_KERNEL); 3361 if (!mr) 3362 return ERR_PTR(-ENOMEM); 3363 3364 mr->rdev = rdev; 3365 mr->qplib_mr.pd = &pd->qplib_pd; 3366 mr->qplib_mr.flags = BNXT_QPLIB_FR_PMR; 3367 mr->qplib_mr.type = CMDQ_ALLOCATE_MRW_MRW_FLAGS_PMR; 3368 3369 rc = bnxt_qplib_alloc_mrw(&rdev->qplib_res, &mr->qplib_mr); 3370 if (rc) 3371 goto bail; 3372 3373 mr->ib_mr.lkey = mr->qplib_mr.lkey; 3374 mr->ib_mr.rkey = mr->ib_mr.lkey; 3375 3376 mr->pages = kcalloc(max_num_sg, sizeof(u64), GFP_KERNEL); 3377 if (!mr->pages) { 3378 rc = -ENOMEM; 3379 goto fail; 3380 } 3381 rc = bnxt_qplib_alloc_fast_reg_page_list(&rdev->qplib_res, 3382 &mr->qplib_frpl, max_num_sg); 3383 if (rc) { 3384 dev_err(rdev_to_dev(rdev), 3385 "Failed to allocate HW FR page list"); 3386 goto fail_mr; 3387 } 3388 3389 atomic_inc(&rdev->mr_count); 3390 return &mr->ib_mr; 3391 3392 fail_mr: 3393 kfree(mr->pages); 3394 fail: 3395 bnxt_qplib_free_mrw(&rdev->qplib_res, &mr->qplib_mr); 3396 bail: 3397 kfree(mr); 3398 return ERR_PTR(rc); 3399 } 3400 3401 struct ib_mw *bnxt_re_alloc_mw(struct ib_pd *ib_pd, enum ib_mw_type type, 3402 struct ib_udata *udata) 3403 { 3404 struct bnxt_re_pd *pd = container_of(ib_pd, struct bnxt_re_pd, ib_pd); 3405 struct bnxt_re_dev *rdev = pd->rdev; 3406 struct bnxt_re_mw *mw; 3407 int rc; 3408 3409 mw = kzalloc(sizeof(*mw), GFP_KERNEL); 3410 if (!mw) 3411 return ERR_PTR(-ENOMEM); 3412 mw->rdev = rdev; 3413 mw->qplib_mw.pd = &pd->qplib_pd; 3414 3415 mw->qplib_mw.type = (type == IB_MW_TYPE_1 ? 3416 CMDQ_ALLOCATE_MRW_MRW_FLAGS_MW_TYPE1 : 3417 CMDQ_ALLOCATE_MRW_MRW_FLAGS_MW_TYPE2B); 3418 rc = bnxt_qplib_alloc_mrw(&rdev->qplib_res, &mw->qplib_mw); 3419 if (rc) { 3420 dev_err(rdev_to_dev(rdev), "Allocate MW failed!"); 3421 goto fail; 3422 } 3423 mw->ib_mw.rkey = mw->qplib_mw.rkey; 3424 3425 atomic_inc(&rdev->mw_count); 3426 return &mw->ib_mw; 3427 3428 fail: 3429 kfree(mw); 3430 return ERR_PTR(rc); 3431 } 3432 3433 int bnxt_re_dealloc_mw(struct ib_mw *ib_mw) 3434 { 3435 struct bnxt_re_mw *mw = container_of(ib_mw, struct bnxt_re_mw, ib_mw); 3436 struct bnxt_re_dev *rdev = mw->rdev; 3437 int rc; 3438 3439 rc = bnxt_qplib_free_mrw(&rdev->qplib_res, &mw->qplib_mw); 3440 if (rc) { 3441 dev_err(rdev_to_dev(rdev), "Free MW failed: %#x\n", rc); 3442 return rc; 3443 } 3444 3445 kfree(mw); 3446 atomic_dec(&rdev->mw_count); 3447 return rc; 3448 } 3449 3450 static int bnxt_re_page_size_ok(int page_shift) 3451 { 3452 switch (page_shift) { 3453 case CMDQ_REGISTER_MR_LOG2_PBL_PG_SIZE_PG_4K: 3454 case CMDQ_REGISTER_MR_LOG2_PBL_PG_SIZE_PG_8K: 3455 case CMDQ_REGISTER_MR_LOG2_PBL_PG_SIZE_PG_64K: 3456 case CMDQ_REGISTER_MR_LOG2_PBL_PG_SIZE_PG_2M: 3457 case CMDQ_REGISTER_MR_LOG2_PBL_PG_SIZE_PG_256K: 3458 case CMDQ_REGISTER_MR_LOG2_PBL_PG_SIZE_PG_1M: 3459 case CMDQ_REGISTER_MR_LOG2_PBL_PG_SIZE_PG_4M: 3460 case CMDQ_REGISTER_MR_LOG2_PBL_PG_SIZE_PG_1G: 3461 return 1; 3462 default: 3463 return 0; 3464 } 3465 } 3466 3467 static int fill_umem_pbl_tbl(struct ib_umem *umem, u64 *pbl_tbl_orig, 3468 int page_shift) 3469 { 3470 u64 *pbl_tbl = pbl_tbl_orig; 3471 u64 page_size = BIT_ULL(page_shift); 3472 struct ib_block_iter biter; 3473 3474 rdma_for_each_block(umem->sg_head.sgl, &biter, umem->nmap, page_size) 3475 *pbl_tbl++ = rdma_block_iter_dma_address(&biter); 3476 3477 return pbl_tbl - pbl_tbl_orig; 3478 } 3479 3480 /* uverbs */ 3481 struct ib_mr *bnxt_re_reg_user_mr(struct ib_pd *ib_pd, u64 start, u64 length, 3482 u64 virt_addr, int mr_access_flags, 3483 struct ib_udata *udata) 3484 { 3485 struct bnxt_re_pd *pd = container_of(ib_pd, struct bnxt_re_pd, ib_pd); 3486 struct bnxt_re_dev *rdev = pd->rdev; 3487 struct bnxt_re_mr *mr; 3488 struct ib_umem *umem; 3489 u64 *pbl_tbl = NULL; 3490 int umem_pgs, page_shift, rc; 3491 3492 if (length > BNXT_RE_MAX_MR_SIZE) { 3493 dev_err(rdev_to_dev(rdev), "MR Size: %lld > Max supported:%lld\n", 3494 length, BNXT_RE_MAX_MR_SIZE); 3495 return ERR_PTR(-ENOMEM); 3496 } 3497 3498 mr = kzalloc(sizeof(*mr), GFP_KERNEL); 3499 if (!mr) 3500 return ERR_PTR(-ENOMEM); 3501 3502 mr->rdev = rdev; 3503 mr->qplib_mr.pd = &pd->qplib_pd; 3504 mr->qplib_mr.flags = __from_ib_access_flags(mr_access_flags); 3505 mr->qplib_mr.type = CMDQ_ALLOCATE_MRW_MRW_FLAGS_MR; 3506 3507 rc = bnxt_qplib_alloc_mrw(&rdev->qplib_res, &mr->qplib_mr); 3508 if (rc) { 3509 dev_err(rdev_to_dev(rdev), "Failed to allocate MR"); 3510 goto free_mr; 3511 } 3512 /* The fixed portion of the rkey is the same as the lkey */ 3513 mr->ib_mr.rkey = mr->qplib_mr.rkey; 3514 3515 umem = ib_umem_get(udata, start, length, mr_access_flags); 3516 if (IS_ERR(umem)) { 3517 dev_err(rdev_to_dev(rdev), "Failed to get umem"); 3518 rc = -EFAULT; 3519 goto free_mrw; 3520 } 3521 mr->ib_umem = umem; 3522 3523 mr->qplib_mr.va = virt_addr; 3524 umem_pgs = ib_umem_page_count(umem); 3525 if (!umem_pgs) { 3526 dev_err(rdev_to_dev(rdev), "umem is invalid!"); 3527 rc = -EINVAL; 3528 goto free_umem; 3529 } 3530 mr->qplib_mr.total_size = length; 3531 3532 pbl_tbl = kcalloc(umem_pgs, sizeof(u64 *), GFP_KERNEL); 3533 if (!pbl_tbl) { 3534 rc = -ENOMEM; 3535 goto free_umem; 3536 } 3537 3538 page_shift = __ffs(ib_umem_find_best_pgsz(umem, 3539 BNXT_RE_PAGE_SIZE_4K | BNXT_RE_PAGE_SIZE_2M, 3540 virt_addr)); 3541 3542 if (!bnxt_re_page_size_ok(page_shift)) { 3543 dev_err(rdev_to_dev(rdev), "umem page size unsupported!"); 3544 rc = -EFAULT; 3545 goto fail; 3546 } 3547 3548 if (page_shift == BNXT_RE_PAGE_SHIFT_4K && 3549 length > BNXT_RE_MAX_MR_SIZE_LOW) { 3550 dev_err(rdev_to_dev(rdev), "Requested MR Sz:%llu Max sup:%llu", 3551 length, (u64)BNXT_RE_MAX_MR_SIZE_LOW); 3552 rc = -EINVAL; 3553 goto fail; 3554 } 3555 3556 /* Map umem buf ptrs to the PBL */ 3557 umem_pgs = fill_umem_pbl_tbl(umem, pbl_tbl, page_shift); 3558 rc = bnxt_qplib_reg_mr(&rdev->qplib_res, &mr->qplib_mr, pbl_tbl, 3559 umem_pgs, false, 1 << page_shift); 3560 if (rc) { 3561 dev_err(rdev_to_dev(rdev), "Failed to register user MR"); 3562 goto fail; 3563 } 3564 3565 kfree(pbl_tbl); 3566 3567 mr->ib_mr.lkey = mr->qplib_mr.lkey; 3568 mr->ib_mr.rkey = mr->qplib_mr.lkey; 3569 atomic_inc(&rdev->mr_count); 3570 3571 return &mr->ib_mr; 3572 fail: 3573 kfree(pbl_tbl); 3574 free_umem: 3575 ib_umem_release(umem); 3576 free_mrw: 3577 bnxt_qplib_free_mrw(&rdev->qplib_res, &mr->qplib_mr); 3578 free_mr: 3579 kfree(mr); 3580 return ERR_PTR(rc); 3581 } 3582 3583 int bnxt_re_alloc_ucontext(struct ib_ucontext *ctx, struct ib_udata *udata) 3584 { 3585 struct ib_device *ibdev = ctx->device; 3586 struct bnxt_re_ucontext *uctx = 3587 container_of(ctx, struct bnxt_re_ucontext, ib_uctx); 3588 struct bnxt_re_dev *rdev = to_bnxt_re_dev(ibdev, ibdev); 3589 struct bnxt_qplib_dev_attr *dev_attr = &rdev->dev_attr; 3590 struct bnxt_re_uctx_resp resp; 3591 u32 chip_met_rev_num = 0; 3592 int rc; 3593 3594 dev_dbg(rdev_to_dev(rdev), "ABI version requested %u", 3595 ibdev->ops.uverbs_abi_ver); 3596 3597 if (ibdev->ops.uverbs_abi_ver != BNXT_RE_ABI_VERSION) { 3598 dev_dbg(rdev_to_dev(rdev), " is different from the device %d ", 3599 BNXT_RE_ABI_VERSION); 3600 return -EPERM; 3601 } 3602 3603 uctx->rdev = rdev; 3604 3605 uctx->shpg = (void *)__get_free_page(GFP_KERNEL); 3606 if (!uctx->shpg) { 3607 rc = -ENOMEM; 3608 goto fail; 3609 } 3610 spin_lock_init(&uctx->sh_lock); 3611 3612 resp.comp_mask = BNXT_RE_UCNTX_CMASK_HAVE_CCTX; 3613 chip_met_rev_num = rdev->chip_ctx.chip_num; 3614 chip_met_rev_num |= ((u32)rdev->chip_ctx.chip_rev & 0xFF) << 3615 BNXT_RE_CHIP_ID0_CHIP_REV_SFT; 3616 chip_met_rev_num |= ((u32)rdev->chip_ctx.chip_metal & 0xFF) << 3617 BNXT_RE_CHIP_ID0_CHIP_MET_SFT; 3618 resp.chip_id0 = chip_met_rev_num; 3619 /* Future extension of chip info */ 3620 resp.chip_id1 = 0; 3621 /*Temp, Use xa_alloc instead */ 3622 resp.dev_id = rdev->en_dev->pdev->devfn; 3623 resp.max_qp = rdev->qplib_ctx.qpc_count; 3624 resp.pg_size = PAGE_SIZE; 3625 resp.cqe_sz = sizeof(struct cq_base); 3626 resp.max_cqd = dev_attr->max_cq_wqes; 3627 resp.rsvd = 0; 3628 3629 rc = ib_copy_to_udata(udata, &resp, min(udata->outlen, sizeof(resp))); 3630 if (rc) { 3631 dev_err(rdev_to_dev(rdev), "Failed to copy user context"); 3632 rc = -EFAULT; 3633 goto cfail; 3634 } 3635 3636 return 0; 3637 cfail: 3638 free_page((unsigned long)uctx->shpg); 3639 uctx->shpg = NULL; 3640 fail: 3641 return rc; 3642 } 3643 3644 void bnxt_re_dealloc_ucontext(struct ib_ucontext *ib_uctx) 3645 { 3646 struct bnxt_re_ucontext *uctx = container_of(ib_uctx, 3647 struct bnxt_re_ucontext, 3648 ib_uctx); 3649 3650 struct bnxt_re_dev *rdev = uctx->rdev; 3651 3652 if (uctx->shpg) 3653 free_page((unsigned long)uctx->shpg); 3654 3655 if (uctx->dpi.dbr) { 3656 /* Free DPI only if this is the first PD allocated by the 3657 * application and mark the context dpi as NULL 3658 */ 3659 bnxt_qplib_dealloc_dpi(&rdev->qplib_res, 3660 &rdev->qplib_res.dpi_tbl, &uctx->dpi); 3661 uctx->dpi.dbr = NULL; 3662 } 3663 } 3664 3665 /* Helper function to mmap the virtual memory from user app */ 3666 int bnxt_re_mmap(struct ib_ucontext *ib_uctx, struct vm_area_struct *vma) 3667 { 3668 struct bnxt_re_ucontext *uctx = container_of(ib_uctx, 3669 struct bnxt_re_ucontext, 3670 ib_uctx); 3671 struct bnxt_re_dev *rdev = uctx->rdev; 3672 u64 pfn; 3673 3674 if (vma->vm_end - vma->vm_start != PAGE_SIZE) 3675 return -EINVAL; 3676 3677 if (vma->vm_pgoff) { 3678 vma->vm_page_prot = pgprot_noncached(vma->vm_page_prot); 3679 if (io_remap_pfn_range(vma, vma->vm_start, vma->vm_pgoff, 3680 PAGE_SIZE, vma->vm_page_prot)) { 3681 dev_err(rdev_to_dev(rdev), "Failed to map DPI"); 3682 return -EAGAIN; 3683 } 3684 } else { 3685 pfn = virt_to_phys(uctx->shpg) >> PAGE_SHIFT; 3686 if (remap_pfn_range(vma, vma->vm_start, 3687 pfn, PAGE_SIZE, vma->vm_page_prot)) { 3688 dev_err(rdev_to_dev(rdev), 3689 "Failed to map shared page"); 3690 return -EAGAIN; 3691 } 3692 } 3693 3694 return 0; 3695 } 3696