1 /* 2 * Broadcom NetXtreme-E RoCE driver. 3 * 4 * Copyright (c) 2016 - 2017, Broadcom. All rights reserved. The term 5 * Broadcom refers to Broadcom Limited and/or its subsidiaries. 6 * 7 * This software is available to you under a choice of one of two 8 * licenses. You may choose to be licensed under the terms of the GNU 9 * General Public License (GPL) Version 2, available from the file 10 * COPYING in the main directory of this source tree, or the 11 * BSD license below: 12 * 13 * Redistribution and use in source and binary forms, with or without 14 * modification, are permitted provided that the following conditions 15 * are met: 16 * 17 * 1. Redistributions of source code must retain the above copyright 18 * notice, this list of conditions and the following disclaimer. 19 * 2. Redistributions in binary form must reproduce the above copyright 20 * notice, this list of conditions and the following disclaimer in 21 * the documentation and/or other materials provided with the 22 * distribution. 23 * 24 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' 25 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, 26 * THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR 27 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS 28 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 29 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 30 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR 31 * BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, 32 * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE 33 * OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN 34 * IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 35 * 36 * Description: IB Verbs interpreter 37 */ 38 39 #include <linux/interrupt.h> 40 #include <linux/types.h> 41 #include <linux/pci.h> 42 #include <linux/netdevice.h> 43 #include <linux/if_ether.h> 44 45 #include <rdma/ib_verbs.h> 46 #include <rdma/ib_user_verbs.h> 47 #include <rdma/ib_umem.h> 48 #include <rdma/ib_addr.h> 49 #include <rdma/ib_mad.h> 50 #include <rdma/ib_cache.h> 51 52 #include "bnxt_ulp.h" 53 54 #include "roce_hsi.h" 55 #include "qplib_res.h" 56 #include "qplib_sp.h" 57 #include "qplib_fp.h" 58 #include "qplib_rcfw.h" 59 60 #include "bnxt_re.h" 61 #include "ib_verbs.h" 62 #include <rdma/bnxt_re-abi.h> 63 64 static int __from_ib_access_flags(int iflags) 65 { 66 int qflags = 0; 67 68 if (iflags & IB_ACCESS_LOCAL_WRITE) 69 qflags |= BNXT_QPLIB_ACCESS_LOCAL_WRITE; 70 if (iflags & IB_ACCESS_REMOTE_READ) 71 qflags |= BNXT_QPLIB_ACCESS_REMOTE_READ; 72 if (iflags & IB_ACCESS_REMOTE_WRITE) 73 qflags |= BNXT_QPLIB_ACCESS_REMOTE_WRITE; 74 if (iflags & IB_ACCESS_REMOTE_ATOMIC) 75 qflags |= BNXT_QPLIB_ACCESS_REMOTE_ATOMIC; 76 if (iflags & IB_ACCESS_MW_BIND) 77 qflags |= BNXT_QPLIB_ACCESS_MW_BIND; 78 if (iflags & IB_ZERO_BASED) 79 qflags |= BNXT_QPLIB_ACCESS_ZERO_BASED; 80 if (iflags & IB_ACCESS_ON_DEMAND) 81 qflags |= BNXT_QPLIB_ACCESS_ON_DEMAND; 82 return qflags; 83 }; 84 85 static enum ib_access_flags __to_ib_access_flags(int qflags) 86 { 87 enum ib_access_flags iflags = 0; 88 89 if (qflags & BNXT_QPLIB_ACCESS_LOCAL_WRITE) 90 iflags |= IB_ACCESS_LOCAL_WRITE; 91 if (qflags & BNXT_QPLIB_ACCESS_REMOTE_WRITE) 92 iflags |= IB_ACCESS_REMOTE_WRITE; 93 if (qflags & BNXT_QPLIB_ACCESS_REMOTE_READ) 94 iflags |= IB_ACCESS_REMOTE_READ; 95 if (qflags & BNXT_QPLIB_ACCESS_REMOTE_ATOMIC) 96 iflags |= IB_ACCESS_REMOTE_ATOMIC; 97 if (qflags & BNXT_QPLIB_ACCESS_MW_BIND) 98 iflags |= IB_ACCESS_MW_BIND; 99 if (qflags & BNXT_QPLIB_ACCESS_ZERO_BASED) 100 iflags |= IB_ZERO_BASED; 101 if (qflags & BNXT_QPLIB_ACCESS_ON_DEMAND) 102 iflags |= IB_ACCESS_ON_DEMAND; 103 return iflags; 104 }; 105 106 static int bnxt_re_build_sgl(struct ib_sge *ib_sg_list, 107 struct bnxt_qplib_sge *sg_list, int num) 108 { 109 int i, total = 0; 110 111 for (i = 0; i < num; i++) { 112 sg_list[i].addr = ib_sg_list[i].addr; 113 sg_list[i].lkey = ib_sg_list[i].lkey; 114 sg_list[i].size = ib_sg_list[i].length; 115 total += sg_list[i].size; 116 } 117 return total; 118 } 119 120 /* Device */ 121 struct net_device *bnxt_re_get_netdev(struct ib_device *ibdev, u8 port_num) 122 { 123 struct bnxt_re_dev *rdev = to_bnxt_re_dev(ibdev, ibdev); 124 struct net_device *netdev = NULL; 125 126 rcu_read_lock(); 127 if (rdev) 128 netdev = rdev->netdev; 129 if (netdev) 130 dev_hold(netdev); 131 132 rcu_read_unlock(); 133 return netdev; 134 } 135 136 int bnxt_re_query_device(struct ib_device *ibdev, 137 struct ib_device_attr *ib_attr, 138 struct ib_udata *udata) 139 { 140 struct bnxt_re_dev *rdev = to_bnxt_re_dev(ibdev, ibdev); 141 struct bnxt_qplib_dev_attr *dev_attr = &rdev->dev_attr; 142 143 memset(ib_attr, 0, sizeof(*ib_attr)); 144 145 ib_attr->fw_ver = (u64)(unsigned long)(dev_attr->fw_ver); 146 bnxt_qplib_get_guid(rdev->netdev->dev_addr, 147 (u8 *)&ib_attr->sys_image_guid); 148 ib_attr->max_mr_size = BNXT_RE_MAX_MR_SIZE; 149 ib_attr->page_size_cap = BNXT_RE_PAGE_SIZE_4K; 150 151 ib_attr->vendor_id = rdev->en_dev->pdev->vendor; 152 ib_attr->vendor_part_id = rdev->en_dev->pdev->device; 153 ib_attr->hw_ver = rdev->en_dev->pdev->subsystem_device; 154 ib_attr->max_qp = dev_attr->max_qp; 155 ib_attr->max_qp_wr = dev_attr->max_qp_wqes; 156 ib_attr->device_cap_flags = 157 IB_DEVICE_CURR_QP_STATE_MOD 158 | IB_DEVICE_RC_RNR_NAK_GEN 159 | IB_DEVICE_SHUTDOWN_PORT 160 | IB_DEVICE_SYS_IMAGE_GUID 161 | IB_DEVICE_LOCAL_DMA_LKEY 162 | IB_DEVICE_RESIZE_MAX_WR 163 | IB_DEVICE_PORT_ACTIVE_EVENT 164 | IB_DEVICE_N_NOTIFY_CQ 165 | IB_DEVICE_MEM_WINDOW 166 | IB_DEVICE_MEM_WINDOW_TYPE_2B 167 | IB_DEVICE_MEM_MGT_EXTENSIONS; 168 ib_attr->max_sge = dev_attr->max_qp_sges; 169 ib_attr->max_sge_rd = dev_attr->max_qp_sges; 170 ib_attr->max_cq = dev_attr->max_cq; 171 ib_attr->max_cqe = dev_attr->max_cq_wqes; 172 ib_attr->max_mr = dev_attr->max_mr; 173 ib_attr->max_pd = dev_attr->max_pd; 174 ib_attr->max_qp_rd_atom = dev_attr->max_qp_rd_atom; 175 ib_attr->max_qp_init_rd_atom = dev_attr->max_qp_init_rd_atom; 176 if (dev_attr->is_atomic) { 177 ib_attr->atomic_cap = IB_ATOMIC_HCA; 178 ib_attr->masked_atomic_cap = IB_ATOMIC_HCA; 179 } 180 181 ib_attr->max_ee_rd_atom = 0; 182 ib_attr->max_res_rd_atom = 0; 183 ib_attr->max_ee_init_rd_atom = 0; 184 ib_attr->max_ee = 0; 185 ib_attr->max_rdd = 0; 186 ib_attr->max_mw = dev_attr->max_mw; 187 ib_attr->max_raw_ipv6_qp = 0; 188 ib_attr->max_raw_ethy_qp = dev_attr->max_raw_ethy_qp; 189 ib_attr->max_mcast_grp = 0; 190 ib_attr->max_mcast_qp_attach = 0; 191 ib_attr->max_total_mcast_qp_attach = 0; 192 ib_attr->max_ah = dev_attr->max_ah; 193 194 ib_attr->max_fmr = 0; 195 ib_attr->max_map_per_fmr = 0; 196 197 ib_attr->max_srq = dev_attr->max_srq; 198 ib_attr->max_srq_wr = dev_attr->max_srq_wqes; 199 ib_attr->max_srq_sge = dev_attr->max_srq_sges; 200 201 ib_attr->max_fast_reg_page_list_len = MAX_PBL_LVL_1_PGS; 202 203 ib_attr->max_pkeys = 1; 204 ib_attr->local_ca_ack_delay = BNXT_RE_DEFAULT_ACK_DELAY; 205 return 0; 206 } 207 208 int bnxt_re_modify_device(struct ib_device *ibdev, 209 int device_modify_mask, 210 struct ib_device_modify *device_modify) 211 { 212 switch (device_modify_mask) { 213 case IB_DEVICE_MODIFY_SYS_IMAGE_GUID: 214 /* Modify the GUID requires the modification of the GID table */ 215 /* GUID should be made as READ-ONLY */ 216 break; 217 case IB_DEVICE_MODIFY_NODE_DESC: 218 /* Node Desc should be made as READ-ONLY */ 219 break; 220 default: 221 break; 222 } 223 return 0; 224 } 225 226 /* Port */ 227 int bnxt_re_query_port(struct ib_device *ibdev, u8 port_num, 228 struct ib_port_attr *port_attr) 229 { 230 struct bnxt_re_dev *rdev = to_bnxt_re_dev(ibdev, ibdev); 231 struct bnxt_qplib_dev_attr *dev_attr = &rdev->dev_attr; 232 233 memset(port_attr, 0, sizeof(*port_attr)); 234 235 if (netif_running(rdev->netdev) && netif_carrier_ok(rdev->netdev)) { 236 port_attr->state = IB_PORT_ACTIVE; 237 port_attr->phys_state = 5; 238 } else { 239 port_attr->state = IB_PORT_DOWN; 240 port_attr->phys_state = 3; 241 } 242 port_attr->max_mtu = IB_MTU_4096; 243 port_attr->active_mtu = iboe_get_mtu(rdev->netdev->mtu); 244 port_attr->gid_tbl_len = dev_attr->max_sgid; 245 port_attr->port_cap_flags = IB_PORT_CM_SUP | IB_PORT_REINIT_SUP | 246 IB_PORT_DEVICE_MGMT_SUP | 247 IB_PORT_VENDOR_CLASS_SUP | 248 IB_PORT_IP_BASED_GIDS; 249 250 /* Max MSG size set to 2G for now */ 251 port_attr->max_msg_sz = 0x80000000; 252 port_attr->bad_pkey_cntr = 0; 253 port_attr->qkey_viol_cntr = 0; 254 port_attr->pkey_tbl_len = dev_attr->max_pkey; 255 port_attr->lid = 0; 256 port_attr->sm_lid = 0; 257 port_attr->lmc = 0; 258 port_attr->max_vl_num = 4; 259 port_attr->sm_sl = 0; 260 port_attr->subnet_timeout = 0; 261 port_attr->init_type_reply = 0; 262 port_attr->active_speed = rdev->active_speed; 263 port_attr->active_width = rdev->active_width; 264 265 return 0; 266 } 267 268 int bnxt_re_get_port_immutable(struct ib_device *ibdev, u8 port_num, 269 struct ib_port_immutable *immutable) 270 { 271 struct ib_port_attr port_attr; 272 273 if (bnxt_re_query_port(ibdev, port_num, &port_attr)) 274 return -EINVAL; 275 276 immutable->pkey_tbl_len = port_attr.pkey_tbl_len; 277 immutable->gid_tbl_len = port_attr.gid_tbl_len; 278 immutable->core_cap_flags = RDMA_CORE_PORT_IBA_ROCE; 279 immutable->core_cap_flags |= RDMA_CORE_CAP_PROT_ROCE_UDP_ENCAP; 280 immutable->max_mad_size = IB_MGMT_MAD_SIZE; 281 return 0; 282 } 283 284 int bnxt_re_query_pkey(struct ib_device *ibdev, u8 port_num, 285 u16 index, u16 *pkey) 286 { 287 struct bnxt_re_dev *rdev = to_bnxt_re_dev(ibdev, ibdev); 288 289 /* Ignore port_num */ 290 291 memset(pkey, 0, sizeof(*pkey)); 292 return bnxt_qplib_get_pkey(&rdev->qplib_res, 293 &rdev->qplib_res.pkey_tbl, index, pkey); 294 } 295 296 int bnxt_re_query_gid(struct ib_device *ibdev, u8 port_num, 297 int index, union ib_gid *gid) 298 { 299 struct bnxt_re_dev *rdev = to_bnxt_re_dev(ibdev, ibdev); 300 int rc = 0; 301 302 /* Ignore port_num */ 303 memset(gid, 0, sizeof(*gid)); 304 rc = bnxt_qplib_get_sgid(&rdev->qplib_res, 305 &rdev->qplib_res.sgid_tbl, index, 306 (struct bnxt_qplib_gid *)gid); 307 return rc; 308 } 309 310 int bnxt_re_del_gid(struct ib_device *ibdev, u8 port_num, 311 unsigned int index, void **context) 312 { 313 int rc = 0; 314 struct bnxt_re_gid_ctx *ctx, **ctx_tbl; 315 struct bnxt_re_dev *rdev = to_bnxt_re_dev(ibdev, ibdev); 316 struct bnxt_qplib_sgid_tbl *sgid_tbl = &rdev->qplib_res.sgid_tbl; 317 struct bnxt_qplib_gid *gid_to_del; 318 319 /* Delete the entry from the hardware */ 320 ctx = *context; 321 if (!ctx) 322 return -EINVAL; 323 324 if (sgid_tbl && sgid_tbl->active) { 325 if (ctx->idx >= sgid_tbl->max) 326 return -EINVAL; 327 gid_to_del = &sgid_tbl->tbl[ctx->idx]; 328 /* DEL_GID is called in WQ context(netdevice_event_work_handler) 329 * or via the ib_unregister_device path. In the former case QP1 330 * may not be destroyed yet, in which case just return as FW 331 * needs that entry to be present and will fail it's deletion. 332 * We could get invoked again after QP1 is destroyed OR get an 333 * ADD_GID call with a different GID value for the same index 334 * where we issue MODIFY_GID cmd to update the GID entry -- TBD 335 */ 336 if (ctx->idx == 0 && 337 rdma_link_local_addr((struct in6_addr *)gid_to_del) && 338 ctx->refcnt == 1 && rdev->qp1_sqp) { 339 dev_dbg(rdev_to_dev(rdev), 340 "Trying to delete GID0 while QP1 is alive\n"); 341 return -EFAULT; 342 } 343 ctx->refcnt--; 344 if (!ctx->refcnt) { 345 rc = bnxt_qplib_del_sgid(sgid_tbl, gid_to_del, true); 346 if (rc) { 347 dev_err(rdev_to_dev(rdev), 348 "Failed to remove GID: %#x", rc); 349 } else { 350 ctx_tbl = sgid_tbl->ctx; 351 ctx_tbl[ctx->idx] = NULL; 352 kfree(ctx); 353 } 354 } 355 } else { 356 return -EINVAL; 357 } 358 return rc; 359 } 360 361 int bnxt_re_add_gid(struct ib_device *ibdev, u8 port_num, 362 unsigned int index, const union ib_gid *gid, 363 const struct ib_gid_attr *attr, void **context) 364 { 365 int rc; 366 u32 tbl_idx = 0; 367 u16 vlan_id = 0xFFFF; 368 struct bnxt_re_gid_ctx *ctx, **ctx_tbl; 369 struct bnxt_re_dev *rdev = to_bnxt_re_dev(ibdev, ibdev); 370 struct bnxt_qplib_sgid_tbl *sgid_tbl = &rdev->qplib_res.sgid_tbl; 371 372 if ((attr->ndev) && is_vlan_dev(attr->ndev)) 373 vlan_id = vlan_dev_vlan_id(attr->ndev); 374 375 rc = bnxt_qplib_add_sgid(sgid_tbl, (struct bnxt_qplib_gid *)gid, 376 rdev->qplib_res.netdev->dev_addr, 377 vlan_id, true, &tbl_idx); 378 if (rc == -EALREADY) { 379 ctx_tbl = sgid_tbl->ctx; 380 ctx_tbl[tbl_idx]->refcnt++; 381 *context = ctx_tbl[tbl_idx]; 382 return 0; 383 } 384 385 if (rc < 0) { 386 dev_err(rdev_to_dev(rdev), "Failed to add GID: %#x", rc); 387 return rc; 388 } 389 390 ctx = kmalloc(sizeof(*ctx), GFP_KERNEL); 391 if (!ctx) 392 return -ENOMEM; 393 ctx_tbl = sgid_tbl->ctx; 394 ctx->idx = tbl_idx; 395 ctx->refcnt = 1; 396 ctx_tbl[tbl_idx] = ctx; 397 398 return rc; 399 } 400 401 enum rdma_link_layer bnxt_re_get_link_layer(struct ib_device *ibdev, 402 u8 port_num) 403 { 404 return IB_LINK_LAYER_ETHERNET; 405 } 406 407 #define BNXT_RE_FENCE_PBL_SIZE DIV_ROUND_UP(BNXT_RE_FENCE_BYTES, PAGE_SIZE) 408 409 static void bnxt_re_create_fence_wqe(struct bnxt_re_pd *pd) 410 { 411 struct bnxt_re_fence_data *fence = &pd->fence; 412 struct ib_mr *ib_mr = &fence->mr->ib_mr; 413 struct bnxt_qplib_swqe *wqe = &fence->bind_wqe; 414 415 memset(wqe, 0, sizeof(*wqe)); 416 wqe->type = BNXT_QPLIB_SWQE_TYPE_BIND_MW; 417 wqe->wr_id = BNXT_QPLIB_FENCE_WRID; 418 wqe->flags |= BNXT_QPLIB_SWQE_FLAGS_SIGNAL_COMP; 419 wqe->flags |= BNXT_QPLIB_SWQE_FLAGS_UC_FENCE; 420 wqe->bind.zero_based = false; 421 wqe->bind.parent_l_key = ib_mr->lkey; 422 wqe->bind.va = (u64)(unsigned long)fence->va; 423 wqe->bind.length = fence->size; 424 wqe->bind.access_cntl = __from_ib_access_flags(IB_ACCESS_REMOTE_READ); 425 wqe->bind.mw_type = SQ_BIND_MW_TYPE_TYPE1; 426 427 /* Save the initial rkey in fence structure for now; 428 * wqe->bind.r_key will be set at (re)bind time. 429 */ 430 fence->bind_rkey = ib_inc_rkey(fence->mw->rkey); 431 } 432 433 static int bnxt_re_bind_fence_mw(struct bnxt_qplib_qp *qplib_qp) 434 { 435 struct bnxt_re_qp *qp = container_of(qplib_qp, struct bnxt_re_qp, 436 qplib_qp); 437 struct ib_pd *ib_pd = qp->ib_qp.pd; 438 struct bnxt_re_pd *pd = container_of(ib_pd, struct bnxt_re_pd, ib_pd); 439 struct bnxt_re_fence_data *fence = &pd->fence; 440 struct bnxt_qplib_swqe *fence_wqe = &fence->bind_wqe; 441 struct bnxt_qplib_swqe wqe; 442 int rc; 443 444 memcpy(&wqe, fence_wqe, sizeof(wqe)); 445 wqe.bind.r_key = fence->bind_rkey; 446 fence->bind_rkey = ib_inc_rkey(fence->bind_rkey); 447 448 dev_dbg(rdev_to_dev(qp->rdev), 449 "Posting bind fence-WQE: rkey: %#x QP: %d PD: %p\n", 450 wqe.bind.r_key, qp->qplib_qp.id, pd); 451 rc = bnxt_qplib_post_send(&qp->qplib_qp, &wqe); 452 if (rc) { 453 dev_err(rdev_to_dev(qp->rdev), "Failed to bind fence-WQE\n"); 454 return rc; 455 } 456 bnxt_qplib_post_send_db(&qp->qplib_qp); 457 458 return rc; 459 } 460 461 static void bnxt_re_destroy_fence_mr(struct bnxt_re_pd *pd) 462 { 463 struct bnxt_re_fence_data *fence = &pd->fence; 464 struct bnxt_re_dev *rdev = pd->rdev; 465 struct device *dev = &rdev->en_dev->pdev->dev; 466 struct bnxt_re_mr *mr = fence->mr; 467 468 if (fence->mw) { 469 bnxt_re_dealloc_mw(fence->mw); 470 fence->mw = NULL; 471 } 472 if (mr) { 473 if (mr->ib_mr.rkey) 474 bnxt_qplib_dereg_mrw(&rdev->qplib_res, &mr->qplib_mr, 475 true); 476 if (mr->ib_mr.lkey) 477 bnxt_qplib_free_mrw(&rdev->qplib_res, &mr->qplib_mr); 478 kfree(mr); 479 fence->mr = NULL; 480 } 481 if (fence->dma_addr) { 482 dma_unmap_single(dev, fence->dma_addr, BNXT_RE_FENCE_BYTES, 483 DMA_BIDIRECTIONAL); 484 fence->dma_addr = 0; 485 } 486 } 487 488 static int bnxt_re_create_fence_mr(struct bnxt_re_pd *pd) 489 { 490 int mr_access_flags = IB_ACCESS_LOCAL_WRITE | IB_ACCESS_MW_BIND; 491 struct bnxt_re_fence_data *fence = &pd->fence; 492 struct bnxt_re_dev *rdev = pd->rdev; 493 struct device *dev = &rdev->en_dev->pdev->dev; 494 struct bnxt_re_mr *mr = NULL; 495 dma_addr_t dma_addr = 0; 496 struct ib_mw *mw; 497 u64 pbl_tbl; 498 int rc; 499 500 dma_addr = dma_map_single(dev, fence->va, BNXT_RE_FENCE_BYTES, 501 DMA_BIDIRECTIONAL); 502 rc = dma_mapping_error(dev, dma_addr); 503 if (rc) { 504 dev_err(rdev_to_dev(rdev), "Failed to dma-map fence-MR-mem\n"); 505 rc = -EIO; 506 fence->dma_addr = 0; 507 goto fail; 508 } 509 fence->dma_addr = dma_addr; 510 511 /* Allocate a MR */ 512 mr = kzalloc(sizeof(*mr), GFP_KERNEL); 513 if (!mr) { 514 rc = -ENOMEM; 515 goto fail; 516 } 517 fence->mr = mr; 518 mr->rdev = rdev; 519 mr->qplib_mr.pd = &pd->qplib_pd; 520 mr->qplib_mr.type = CMDQ_ALLOCATE_MRW_MRW_FLAGS_PMR; 521 mr->qplib_mr.flags = __from_ib_access_flags(mr_access_flags); 522 rc = bnxt_qplib_alloc_mrw(&rdev->qplib_res, &mr->qplib_mr); 523 if (rc) { 524 dev_err(rdev_to_dev(rdev), "Failed to alloc fence-HW-MR\n"); 525 goto fail; 526 } 527 528 /* Register MR */ 529 mr->ib_mr.lkey = mr->qplib_mr.lkey; 530 mr->qplib_mr.va = (u64)(unsigned long)fence->va; 531 mr->qplib_mr.total_size = BNXT_RE_FENCE_BYTES; 532 pbl_tbl = dma_addr; 533 rc = bnxt_qplib_reg_mr(&rdev->qplib_res, &mr->qplib_mr, &pbl_tbl, 534 BNXT_RE_FENCE_PBL_SIZE, false); 535 if (rc) { 536 dev_err(rdev_to_dev(rdev), "Failed to register fence-MR\n"); 537 goto fail; 538 } 539 mr->ib_mr.rkey = mr->qplib_mr.rkey; 540 541 /* Create a fence MW only for kernel consumers */ 542 mw = bnxt_re_alloc_mw(&pd->ib_pd, IB_MW_TYPE_1, NULL); 543 if (IS_ERR(mw)) { 544 dev_err(rdev_to_dev(rdev), 545 "Failed to create fence-MW for PD: %p\n", pd); 546 rc = PTR_ERR(mw); 547 goto fail; 548 } 549 fence->mw = mw; 550 551 bnxt_re_create_fence_wqe(pd); 552 return 0; 553 554 fail: 555 bnxt_re_destroy_fence_mr(pd); 556 return rc; 557 } 558 559 /* Protection Domains */ 560 int bnxt_re_dealloc_pd(struct ib_pd *ib_pd) 561 { 562 struct bnxt_re_pd *pd = container_of(ib_pd, struct bnxt_re_pd, ib_pd); 563 struct bnxt_re_dev *rdev = pd->rdev; 564 int rc; 565 566 bnxt_re_destroy_fence_mr(pd); 567 568 if (pd->qplib_pd.id) { 569 rc = bnxt_qplib_dealloc_pd(&rdev->qplib_res, 570 &rdev->qplib_res.pd_tbl, 571 &pd->qplib_pd); 572 if (rc) 573 dev_err(rdev_to_dev(rdev), "Failed to deallocate HW PD"); 574 } 575 576 kfree(pd); 577 return 0; 578 } 579 580 struct ib_pd *bnxt_re_alloc_pd(struct ib_device *ibdev, 581 struct ib_ucontext *ucontext, 582 struct ib_udata *udata) 583 { 584 struct bnxt_re_dev *rdev = to_bnxt_re_dev(ibdev, ibdev); 585 struct bnxt_re_ucontext *ucntx = container_of(ucontext, 586 struct bnxt_re_ucontext, 587 ib_uctx); 588 struct bnxt_re_pd *pd; 589 int rc; 590 591 pd = kzalloc(sizeof(*pd), GFP_KERNEL); 592 if (!pd) 593 return ERR_PTR(-ENOMEM); 594 595 pd->rdev = rdev; 596 if (bnxt_qplib_alloc_pd(&rdev->qplib_res.pd_tbl, &pd->qplib_pd)) { 597 dev_err(rdev_to_dev(rdev), "Failed to allocate HW PD"); 598 rc = -ENOMEM; 599 goto fail; 600 } 601 602 if (udata) { 603 struct bnxt_re_pd_resp resp; 604 605 if (!ucntx->dpi.dbr) { 606 /* Allocate DPI in alloc_pd to avoid failing of 607 * ibv_devinfo and family of application when DPIs 608 * are depleted. 609 */ 610 if (bnxt_qplib_alloc_dpi(&rdev->qplib_res.dpi_tbl, 611 &ucntx->dpi, ucntx)) { 612 rc = -ENOMEM; 613 goto dbfail; 614 } 615 } 616 617 resp.pdid = pd->qplib_pd.id; 618 /* Still allow mapping this DBR to the new user PD. */ 619 resp.dpi = ucntx->dpi.dpi; 620 resp.dbr = (u64)ucntx->dpi.umdbr; 621 622 rc = ib_copy_to_udata(udata, &resp, sizeof(resp)); 623 if (rc) { 624 dev_err(rdev_to_dev(rdev), 625 "Failed to copy user response\n"); 626 goto dbfail; 627 } 628 } 629 630 if (!udata) 631 if (bnxt_re_create_fence_mr(pd)) 632 dev_warn(rdev_to_dev(rdev), 633 "Failed to create Fence-MR\n"); 634 return &pd->ib_pd; 635 dbfail: 636 (void)bnxt_qplib_dealloc_pd(&rdev->qplib_res, &rdev->qplib_res.pd_tbl, 637 &pd->qplib_pd); 638 fail: 639 kfree(pd); 640 return ERR_PTR(rc); 641 } 642 643 /* Address Handles */ 644 int bnxt_re_destroy_ah(struct ib_ah *ib_ah) 645 { 646 struct bnxt_re_ah *ah = container_of(ib_ah, struct bnxt_re_ah, ib_ah); 647 struct bnxt_re_dev *rdev = ah->rdev; 648 int rc; 649 650 rc = bnxt_qplib_destroy_ah(&rdev->qplib_res, &ah->qplib_ah); 651 if (rc) { 652 dev_err(rdev_to_dev(rdev), "Failed to destroy HW AH"); 653 return rc; 654 } 655 kfree(ah); 656 return 0; 657 } 658 659 struct ib_ah *bnxt_re_create_ah(struct ib_pd *ib_pd, 660 struct rdma_ah_attr *ah_attr, 661 struct ib_udata *udata) 662 { 663 struct bnxt_re_pd *pd = container_of(ib_pd, struct bnxt_re_pd, ib_pd); 664 struct bnxt_re_dev *rdev = pd->rdev; 665 struct bnxt_re_ah *ah; 666 const struct ib_global_route *grh = rdma_ah_read_grh(ah_attr); 667 int rc; 668 u16 vlan_tag; 669 u8 nw_type; 670 671 struct ib_gid_attr sgid_attr; 672 673 if (!(rdma_ah_get_ah_flags(ah_attr) & IB_AH_GRH)) { 674 dev_err(rdev_to_dev(rdev), "Failed to alloc AH: GRH not set"); 675 return ERR_PTR(-EINVAL); 676 } 677 ah = kzalloc(sizeof(*ah), GFP_ATOMIC); 678 if (!ah) 679 return ERR_PTR(-ENOMEM); 680 681 ah->rdev = rdev; 682 ah->qplib_ah.pd = &pd->qplib_pd; 683 684 /* Supply the configuration for the HW */ 685 memcpy(ah->qplib_ah.dgid.data, grh->dgid.raw, 686 sizeof(union ib_gid)); 687 /* 688 * If RoCE V2 is enabled, stack will have two entries for 689 * each GID entry. Avoiding this duplicte entry in HW. Dividing 690 * the GID index by 2 for RoCE V2 691 */ 692 ah->qplib_ah.sgid_index = grh->sgid_index / 2; 693 ah->qplib_ah.host_sgid_index = grh->sgid_index; 694 ah->qplib_ah.traffic_class = grh->traffic_class; 695 ah->qplib_ah.flow_label = grh->flow_label; 696 ah->qplib_ah.hop_limit = grh->hop_limit; 697 ah->qplib_ah.sl = rdma_ah_get_sl(ah_attr); 698 if (ib_pd->uobject && 699 !rdma_is_multicast_addr((struct in6_addr *) 700 grh->dgid.raw) && 701 !rdma_link_local_addr((struct in6_addr *) 702 grh->dgid.raw)) { 703 union ib_gid sgid; 704 705 rc = ib_get_cached_gid(&rdev->ibdev, 1, 706 grh->sgid_index, &sgid, 707 &sgid_attr); 708 if (rc) { 709 dev_err(rdev_to_dev(rdev), 710 "Failed to query gid at index %d", 711 grh->sgid_index); 712 goto fail; 713 } 714 if (sgid_attr.ndev) { 715 if (is_vlan_dev(sgid_attr.ndev)) 716 vlan_tag = vlan_dev_vlan_id(sgid_attr.ndev); 717 dev_put(sgid_attr.ndev); 718 } 719 /* Get network header type for this GID */ 720 nw_type = ib_gid_to_network_type(sgid_attr.gid_type, &sgid); 721 switch (nw_type) { 722 case RDMA_NETWORK_IPV4: 723 ah->qplib_ah.nw_type = CMDQ_CREATE_AH_TYPE_V2IPV4; 724 break; 725 case RDMA_NETWORK_IPV6: 726 ah->qplib_ah.nw_type = CMDQ_CREATE_AH_TYPE_V2IPV6; 727 break; 728 default: 729 ah->qplib_ah.nw_type = CMDQ_CREATE_AH_TYPE_V1; 730 break; 731 } 732 rc = rdma_addr_find_l2_eth_by_grh(&sgid, &grh->dgid, 733 ah_attr->roce.dmac, &vlan_tag, 734 &sgid_attr.ndev->ifindex, 735 NULL); 736 if (rc) { 737 dev_err(rdev_to_dev(rdev), "Failed to get dmac\n"); 738 goto fail; 739 } 740 } 741 742 memcpy(ah->qplib_ah.dmac, ah_attr->roce.dmac, ETH_ALEN); 743 rc = bnxt_qplib_create_ah(&rdev->qplib_res, &ah->qplib_ah); 744 if (rc) { 745 dev_err(rdev_to_dev(rdev), "Failed to allocate HW AH"); 746 goto fail; 747 } 748 749 /* Write AVID to shared page. */ 750 if (ib_pd->uobject) { 751 struct ib_ucontext *ib_uctx = ib_pd->uobject->context; 752 struct bnxt_re_ucontext *uctx; 753 unsigned long flag; 754 u32 *wrptr; 755 756 uctx = container_of(ib_uctx, struct bnxt_re_ucontext, ib_uctx); 757 spin_lock_irqsave(&uctx->sh_lock, flag); 758 wrptr = (u32 *)(uctx->shpg + BNXT_RE_AVID_OFFT); 759 *wrptr = ah->qplib_ah.id; 760 wmb(); /* make sure cache is updated. */ 761 spin_unlock_irqrestore(&uctx->sh_lock, flag); 762 } 763 764 return &ah->ib_ah; 765 766 fail: 767 kfree(ah); 768 return ERR_PTR(rc); 769 } 770 771 int bnxt_re_modify_ah(struct ib_ah *ib_ah, struct rdma_ah_attr *ah_attr) 772 { 773 return 0; 774 } 775 776 int bnxt_re_query_ah(struct ib_ah *ib_ah, struct rdma_ah_attr *ah_attr) 777 { 778 struct bnxt_re_ah *ah = container_of(ib_ah, struct bnxt_re_ah, ib_ah); 779 780 ah_attr->type = ib_ah->type; 781 rdma_ah_set_sl(ah_attr, ah->qplib_ah.sl); 782 memcpy(ah_attr->roce.dmac, ah->qplib_ah.dmac, ETH_ALEN); 783 rdma_ah_set_grh(ah_attr, NULL, 0, 784 ah->qplib_ah.host_sgid_index, 785 0, ah->qplib_ah.traffic_class); 786 rdma_ah_set_dgid_raw(ah_attr, ah->qplib_ah.dgid.data); 787 rdma_ah_set_port_num(ah_attr, 1); 788 rdma_ah_set_static_rate(ah_attr, 0); 789 return 0; 790 } 791 792 /* Queue Pairs */ 793 int bnxt_re_destroy_qp(struct ib_qp *ib_qp) 794 { 795 struct bnxt_re_qp *qp = container_of(ib_qp, struct bnxt_re_qp, ib_qp); 796 struct bnxt_re_dev *rdev = qp->rdev; 797 int rc; 798 799 bnxt_qplib_del_flush_qp(&qp->qplib_qp); 800 rc = bnxt_qplib_destroy_qp(&rdev->qplib_res, &qp->qplib_qp); 801 if (rc) { 802 dev_err(rdev_to_dev(rdev), "Failed to destroy HW QP"); 803 return rc; 804 } 805 if (ib_qp->qp_type == IB_QPT_GSI && rdev->qp1_sqp) { 806 rc = bnxt_qplib_destroy_ah(&rdev->qplib_res, 807 &rdev->sqp_ah->qplib_ah); 808 if (rc) { 809 dev_err(rdev_to_dev(rdev), 810 "Failed to destroy HW AH for shadow QP"); 811 return rc; 812 } 813 814 bnxt_qplib_del_flush_qp(&qp->qplib_qp); 815 rc = bnxt_qplib_destroy_qp(&rdev->qplib_res, 816 &rdev->qp1_sqp->qplib_qp); 817 if (rc) { 818 dev_err(rdev_to_dev(rdev), 819 "Failed to destroy Shadow QP"); 820 return rc; 821 } 822 mutex_lock(&rdev->qp_lock); 823 list_del(&rdev->qp1_sqp->list); 824 atomic_dec(&rdev->qp_count); 825 mutex_unlock(&rdev->qp_lock); 826 827 kfree(rdev->sqp_ah); 828 kfree(rdev->qp1_sqp); 829 rdev->qp1_sqp = NULL; 830 rdev->sqp_ah = NULL; 831 } 832 833 if (!IS_ERR_OR_NULL(qp->rumem)) 834 ib_umem_release(qp->rumem); 835 if (!IS_ERR_OR_NULL(qp->sumem)) 836 ib_umem_release(qp->sumem); 837 838 mutex_lock(&rdev->qp_lock); 839 list_del(&qp->list); 840 atomic_dec(&rdev->qp_count); 841 mutex_unlock(&rdev->qp_lock); 842 kfree(qp); 843 return 0; 844 } 845 846 static u8 __from_ib_qp_type(enum ib_qp_type type) 847 { 848 switch (type) { 849 case IB_QPT_GSI: 850 return CMDQ_CREATE_QP1_TYPE_GSI; 851 case IB_QPT_RC: 852 return CMDQ_CREATE_QP_TYPE_RC; 853 case IB_QPT_UD: 854 return CMDQ_CREATE_QP_TYPE_UD; 855 default: 856 return IB_QPT_MAX; 857 } 858 } 859 860 static int bnxt_re_init_user_qp(struct bnxt_re_dev *rdev, struct bnxt_re_pd *pd, 861 struct bnxt_re_qp *qp, struct ib_udata *udata) 862 { 863 struct bnxt_re_qp_req ureq; 864 struct bnxt_qplib_qp *qplib_qp = &qp->qplib_qp; 865 struct ib_umem *umem; 866 int bytes = 0; 867 struct ib_ucontext *context = pd->ib_pd.uobject->context; 868 struct bnxt_re_ucontext *cntx = container_of(context, 869 struct bnxt_re_ucontext, 870 ib_uctx); 871 if (ib_copy_from_udata(&ureq, udata, sizeof(ureq))) 872 return -EFAULT; 873 874 bytes = (qplib_qp->sq.max_wqe * BNXT_QPLIB_MAX_SQE_ENTRY_SIZE); 875 /* Consider mapping PSN search memory only for RC QPs. */ 876 if (qplib_qp->type == CMDQ_CREATE_QP_TYPE_RC) 877 bytes += (qplib_qp->sq.max_wqe * sizeof(struct sq_psn_search)); 878 bytes = PAGE_ALIGN(bytes); 879 umem = ib_umem_get(context, ureq.qpsva, bytes, 880 IB_ACCESS_LOCAL_WRITE, 1); 881 if (IS_ERR(umem)) 882 return PTR_ERR(umem); 883 884 qp->sumem = umem; 885 qplib_qp->sq.sglist = umem->sg_head.sgl; 886 qplib_qp->sq.nmap = umem->nmap; 887 qplib_qp->qp_handle = ureq.qp_handle; 888 889 if (!qp->qplib_qp.srq) { 890 bytes = (qplib_qp->rq.max_wqe * BNXT_QPLIB_MAX_RQE_ENTRY_SIZE); 891 bytes = PAGE_ALIGN(bytes); 892 umem = ib_umem_get(context, ureq.qprva, bytes, 893 IB_ACCESS_LOCAL_WRITE, 1); 894 if (IS_ERR(umem)) 895 goto rqfail; 896 qp->rumem = umem; 897 qplib_qp->rq.sglist = umem->sg_head.sgl; 898 qplib_qp->rq.nmap = umem->nmap; 899 } 900 901 qplib_qp->dpi = &cntx->dpi; 902 return 0; 903 rqfail: 904 ib_umem_release(qp->sumem); 905 qp->sumem = NULL; 906 qplib_qp->sq.sglist = NULL; 907 qplib_qp->sq.nmap = 0; 908 909 return PTR_ERR(umem); 910 } 911 912 static struct bnxt_re_ah *bnxt_re_create_shadow_qp_ah 913 (struct bnxt_re_pd *pd, 914 struct bnxt_qplib_res *qp1_res, 915 struct bnxt_qplib_qp *qp1_qp) 916 { 917 struct bnxt_re_dev *rdev = pd->rdev; 918 struct bnxt_re_ah *ah; 919 union ib_gid sgid; 920 int rc; 921 922 ah = kzalloc(sizeof(*ah), GFP_KERNEL); 923 if (!ah) 924 return NULL; 925 926 ah->rdev = rdev; 927 ah->qplib_ah.pd = &pd->qplib_pd; 928 929 rc = bnxt_re_query_gid(&rdev->ibdev, 1, 0, &sgid); 930 if (rc) 931 goto fail; 932 933 /* supply the dgid data same as sgid */ 934 memcpy(ah->qplib_ah.dgid.data, &sgid.raw, 935 sizeof(union ib_gid)); 936 ah->qplib_ah.sgid_index = 0; 937 938 ah->qplib_ah.traffic_class = 0; 939 ah->qplib_ah.flow_label = 0; 940 ah->qplib_ah.hop_limit = 1; 941 ah->qplib_ah.sl = 0; 942 /* Have DMAC same as SMAC */ 943 ether_addr_copy(ah->qplib_ah.dmac, rdev->netdev->dev_addr); 944 945 rc = bnxt_qplib_create_ah(&rdev->qplib_res, &ah->qplib_ah); 946 if (rc) { 947 dev_err(rdev_to_dev(rdev), 948 "Failed to allocate HW AH for Shadow QP"); 949 goto fail; 950 } 951 952 return ah; 953 954 fail: 955 kfree(ah); 956 return NULL; 957 } 958 959 static struct bnxt_re_qp *bnxt_re_create_shadow_qp 960 (struct bnxt_re_pd *pd, 961 struct bnxt_qplib_res *qp1_res, 962 struct bnxt_qplib_qp *qp1_qp) 963 { 964 struct bnxt_re_dev *rdev = pd->rdev; 965 struct bnxt_re_qp *qp; 966 int rc; 967 968 qp = kzalloc(sizeof(*qp), GFP_KERNEL); 969 if (!qp) 970 return NULL; 971 972 qp->rdev = rdev; 973 974 /* Initialize the shadow QP structure from the QP1 values */ 975 ether_addr_copy(qp->qplib_qp.smac, rdev->netdev->dev_addr); 976 977 qp->qplib_qp.pd = &pd->qplib_pd; 978 qp->qplib_qp.qp_handle = (u64)(unsigned long)(&qp->qplib_qp); 979 qp->qplib_qp.type = IB_QPT_UD; 980 981 qp->qplib_qp.max_inline_data = 0; 982 qp->qplib_qp.sig_type = true; 983 984 /* Shadow QP SQ depth should be same as QP1 RQ depth */ 985 qp->qplib_qp.sq.max_wqe = qp1_qp->rq.max_wqe; 986 qp->qplib_qp.sq.max_sge = 2; 987 /* Q full delta can be 1 since it is internal QP */ 988 qp->qplib_qp.sq.q_full_delta = 1; 989 990 qp->qplib_qp.scq = qp1_qp->scq; 991 qp->qplib_qp.rcq = qp1_qp->rcq; 992 993 qp->qplib_qp.rq.max_wqe = qp1_qp->rq.max_wqe; 994 qp->qplib_qp.rq.max_sge = qp1_qp->rq.max_sge; 995 /* Q full delta can be 1 since it is internal QP */ 996 qp->qplib_qp.rq.q_full_delta = 1; 997 998 qp->qplib_qp.mtu = qp1_qp->mtu; 999 1000 qp->qplib_qp.sq_hdr_buf_size = 0; 1001 qp->qplib_qp.rq_hdr_buf_size = BNXT_QPLIB_MAX_GRH_HDR_SIZE_IPV6; 1002 qp->qplib_qp.dpi = &rdev->dpi_privileged; 1003 1004 rc = bnxt_qplib_create_qp(qp1_res, &qp->qplib_qp); 1005 if (rc) 1006 goto fail; 1007 1008 rdev->sqp_id = qp->qplib_qp.id; 1009 1010 spin_lock_init(&qp->sq_lock); 1011 INIT_LIST_HEAD(&qp->list); 1012 mutex_lock(&rdev->qp_lock); 1013 list_add_tail(&qp->list, &rdev->qp_list); 1014 atomic_inc(&rdev->qp_count); 1015 mutex_unlock(&rdev->qp_lock); 1016 return qp; 1017 fail: 1018 kfree(qp); 1019 return NULL; 1020 } 1021 1022 struct ib_qp *bnxt_re_create_qp(struct ib_pd *ib_pd, 1023 struct ib_qp_init_attr *qp_init_attr, 1024 struct ib_udata *udata) 1025 { 1026 struct bnxt_re_pd *pd = container_of(ib_pd, struct bnxt_re_pd, ib_pd); 1027 struct bnxt_re_dev *rdev = pd->rdev; 1028 struct bnxt_qplib_dev_attr *dev_attr = &rdev->dev_attr; 1029 struct bnxt_re_qp *qp; 1030 struct bnxt_re_cq *cq; 1031 int rc, entries; 1032 1033 if ((qp_init_attr->cap.max_send_wr > dev_attr->max_qp_wqes) || 1034 (qp_init_attr->cap.max_recv_wr > dev_attr->max_qp_wqes) || 1035 (qp_init_attr->cap.max_send_sge > dev_attr->max_qp_sges) || 1036 (qp_init_attr->cap.max_recv_sge > dev_attr->max_qp_sges) || 1037 (qp_init_attr->cap.max_inline_data > dev_attr->max_inline_data)) 1038 return ERR_PTR(-EINVAL); 1039 1040 qp = kzalloc(sizeof(*qp), GFP_KERNEL); 1041 if (!qp) 1042 return ERR_PTR(-ENOMEM); 1043 1044 qp->rdev = rdev; 1045 ether_addr_copy(qp->qplib_qp.smac, rdev->netdev->dev_addr); 1046 qp->qplib_qp.pd = &pd->qplib_pd; 1047 qp->qplib_qp.qp_handle = (u64)(unsigned long)(&qp->qplib_qp); 1048 qp->qplib_qp.type = __from_ib_qp_type(qp_init_attr->qp_type); 1049 if (qp->qplib_qp.type == IB_QPT_MAX) { 1050 dev_err(rdev_to_dev(rdev), "QP type 0x%x not supported", 1051 qp->qplib_qp.type); 1052 rc = -EINVAL; 1053 goto fail; 1054 } 1055 qp->qplib_qp.max_inline_data = qp_init_attr->cap.max_inline_data; 1056 qp->qplib_qp.sig_type = ((qp_init_attr->sq_sig_type == 1057 IB_SIGNAL_ALL_WR) ? true : false); 1058 1059 qp->qplib_qp.sq.max_sge = qp_init_attr->cap.max_send_sge; 1060 if (qp->qplib_qp.sq.max_sge > dev_attr->max_qp_sges) 1061 qp->qplib_qp.sq.max_sge = dev_attr->max_qp_sges; 1062 1063 if (qp_init_attr->send_cq) { 1064 cq = container_of(qp_init_attr->send_cq, struct bnxt_re_cq, 1065 ib_cq); 1066 if (!cq) { 1067 dev_err(rdev_to_dev(rdev), "Send CQ not found"); 1068 rc = -EINVAL; 1069 goto fail; 1070 } 1071 qp->qplib_qp.scq = &cq->qplib_cq; 1072 } 1073 1074 if (qp_init_attr->recv_cq) { 1075 cq = container_of(qp_init_attr->recv_cq, struct bnxt_re_cq, 1076 ib_cq); 1077 if (!cq) { 1078 dev_err(rdev_to_dev(rdev), "Receive CQ not found"); 1079 rc = -EINVAL; 1080 goto fail; 1081 } 1082 qp->qplib_qp.rcq = &cq->qplib_cq; 1083 } 1084 1085 if (qp_init_attr->srq) { 1086 dev_err(rdev_to_dev(rdev), "SRQ not supported"); 1087 rc = -ENOTSUPP; 1088 goto fail; 1089 } else { 1090 /* Allocate 1 more than what's provided so posting max doesn't 1091 * mean empty 1092 */ 1093 entries = roundup_pow_of_two(qp_init_attr->cap.max_recv_wr + 1); 1094 qp->qplib_qp.rq.max_wqe = min_t(u32, entries, 1095 dev_attr->max_qp_wqes + 1); 1096 1097 qp->qplib_qp.rq.q_full_delta = qp->qplib_qp.rq.max_wqe - 1098 qp_init_attr->cap.max_recv_wr; 1099 1100 qp->qplib_qp.rq.max_sge = qp_init_attr->cap.max_recv_sge; 1101 if (qp->qplib_qp.rq.max_sge > dev_attr->max_qp_sges) 1102 qp->qplib_qp.rq.max_sge = dev_attr->max_qp_sges; 1103 } 1104 1105 qp->qplib_qp.mtu = ib_mtu_enum_to_int(iboe_get_mtu(rdev->netdev->mtu)); 1106 1107 if (qp_init_attr->qp_type == IB_QPT_GSI) { 1108 /* Allocate 1 more than what's provided */ 1109 entries = roundup_pow_of_two(qp_init_attr->cap.max_send_wr + 1); 1110 qp->qplib_qp.sq.max_wqe = min_t(u32, entries, 1111 dev_attr->max_qp_wqes + 1); 1112 qp->qplib_qp.sq.q_full_delta = qp->qplib_qp.sq.max_wqe - 1113 qp_init_attr->cap.max_send_wr; 1114 qp->qplib_qp.rq.max_sge = dev_attr->max_qp_sges; 1115 if (qp->qplib_qp.rq.max_sge > dev_attr->max_qp_sges) 1116 qp->qplib_qp.rq.max_sge = dev_attr->max_qp_sges; 1117 qp->qplib_qp.sq.max_sge++; 1118 if (qp->qplib_qp.sq.max_sge > dev_attr->max_qp_sges) 1119 qp->qplib_qp.sq.max_sge = dev_attr->max_qp_sges; 1120 1121 qp->qplib_qp.rq_hdr_buf_size = 1122 BNXT_QPLIB_MAX_QP1_RQ_HDR_SIZE_V2; 1123 1124 qp->qplib_qp.sq_hdr_buf_size = 1125 BNXT_QPLIB_MAX_QP1_SQ_HDR_SIZE_V2; 1126 qp->qplib_qp.dpi = &rdev->dpi_privileged; 1127 rc = bnxt_qplib_create_qp1(&rdev->qplib_res, &qp->qplib_qp); 1128 if (rc) { 1129 dev_err(rdev_to_dev(rdev), "Failed to create HW QP1"); 1130 goto fail; 1131 } 1132 /* Create a shadow QP to handle the QP1 traffic */ 1133 rdev->qp1_sqp = bnxt_re_create_shadow_qp(pd, &rdev->qplib_res, 1134 &qp->qplib_qp); 1135 if (!rdev->qp1_sqp) { 1136 rc = -EINVAL; 1137 dev_err(rdev_to_dev(rdev), 1138 "Failed to create Shadow QP for QP1"); 1139 goto qp_destroy; 1140 } 1141 rdev->sqp_ah = bnxt_re_create_shadow_qp_ah(pd, &rdev->qplib_res, 1142 &qp->qplib_qp); 1143 if (!rdev->sqp_ah) { 1144 bnxt_qplib_destroy_qp(&rdev->qplib_res, 1145 &rdev->qp1_sqp->qplib_qp); 1146 rc = -EINVAL; 1147 dev_err(rdev_to_dev(rdev), 1148 "Failed to create AH entry for ShadowQP"); 1149 goto qp_destroy; 1150 } 1151 1152 } else { 1153 /* Allocate 128 + 1 more than what's provided */ 1154 entries = roundup_pow_of_two(qp_init_attr->cap.max_send_wr + 1155 BNXT_QPLIB_RESERVED_QP_WRS + 1); 1156 qp->qplib_qp.sq.max_wqe = min_t(u32, entries, 1157 dev_attr->max_qp_wqes + 1158 BNXT_QPLIB_RESERVED_QP_WRS + 1); 1159 qp->qplib_qp.sq.q_full_delta = BNXT_QPLIB_RESERVED_QP_WRS + 1; 1160 1161 /* 1162 * Reserving one slot for Phantom WQE. Application can 1163 * post one extra entry in this case. But allowing this to avoid 1164 * unexpected Queue full condition 1165 */ 1166 1167 qp->qplib_qp.sq.q_full_delta -= 1; 1168 1169 qp->qplib_qp.max_rd_atomic = dev_attr->max_qp_rd_atom; 1170 qp->qplib_qp.max_dest_rd_atomic = dev_attr->max_qp_init_rd_atom; 1171 if (udata) { 1172 rc = bnxt_re_init_user_qp(rdev, pd, qp, udata); 1173 if (rc) 1174 goto fail; 1175 } else { 1176 qp->qplib_qp.dpi = &rdev->dpi_privileged; 1177 } 1178 1179 rc = bnxt_qplib_create_qp(&rdev->qplib_res, &qp->qplib_qp); 1180 if (rc) { 1181 dev_err(rdev_to_dev(rdev), "Failed to create HW QP"); 1182 goto fail; 1183 } 1184 } 1185 1186 qp->ib_qp.qp_num = qp->qplib_qp.id; 1187 spin_lock_init(&qp->sq_lock); 1188 spin_lock_init(&qp->rq_lock); 1189 1190 if (udata) { 1191 struct bnxt_re_qp_resp resp; 1192 1193 resp.qpid = qp->ib_qp.qp_num; 1194 resp.rsvd = 0; 1195 rc = ib_copy_to_udata(udata, &resp, sizeof(resp)); 1196 if (rc) { 1197 dev_err(rdev_to_dev(rdev), "Failed to copy QP udata"); 1198 goto qp_destroy; 1199 } 1200 } 1201 INIT_LIST_HEAD(&qp->list); 1202 mutex_lock(&rdev->qp_lock); 1203 list_add_tail(&qp->list, &rdev->qp_list); 1204 atomic_inc(&rdev->qp_count); 1205 mutex_unlock(&rdev->qp_lock); 1206 1207 return &qp->ib_qp; 1208 qp_destroy: 1209 bnxt_qplib_destroy_qp(&rdev->qplib_res, &qp->qplib_qp); 1210 fail: 1211 kfree(qp); 1212 return ERR_PTR(rc); 1213 } 1214 1215 static u8 __from_ib_qp_state(enum ib_qp_state state) 1216 { 1217 switch (state) { 1218 case IB_QPS_RESET: 1219 return CMDQ_MODIFY_QP_NEW_STATE_RESET; 1220 case IB_QPS_INIT: 1221 return CMDQ_MODIFY_QP_NEW_STATE_INIT; 1222 case IB_QPS_RTR: 1223 return CMDQ_MODIFY_QP_NEW_STATE_RTR; 1224 case IB_QPS_RTS: 1225 return CMDQ_MODIFY_QP_NEW_STATE_RTS; 1226 case IB_QPS_SQD: 1227 return CMDQ_MODIFY_QP_NEW_STATE_SQD; 1228 case IB_QPS_SQE: 1229 return CMDQ_MODIFY_QP_NEW_STATE_SQE; 1230 case IB_QPS_ERR: 1231 default: 1232 return CMDQ_MODIFY_QP_NEW_STATE_ERR; 1233 } 1234 } 1235 1236 static enum ib_qp_state __to_ib_qp_state(u8 state) 1237 { 1238 switch (state) { 1239 case CMDQ_MODIFY_QP_NEW_STATE_RESET: 1240 return IB_QPS_RESET; 1241 case CMDQ_MODIFY_QP_NEW_STATE_INIT: 1242 return IB_QPS_INIT; 1243 case CMDQ_MODIFY_QP_NEW_STATE_RTR: 1244 return IB_QPS_RTR; 1245 case CMDQ_MODIFY_QP_NEW_STATE_RTS: 1246 return IB_QPS_RTS; 1247 case CMDQ_MODIFY_QP_NEW_STATE_SQD: 1248 return IB_QPS_SQD; 1249 case CMDQ_MODIFY_QP_NEW_STATE_SQE: 1250 return IB_QPS_SQE; 1251 case CMDQ_MODIFY_QP_NEW_STATE_ERR: 1252 default: 1253 return IB_QPS_ERR; 1254 } 1255 } 1256 1257 static u32 __from_ib_mtu(enum ib_mtu mtu) 1258 { 1259 switch (mtu) { 1260 case IB_MTU_256: 1261 return CMDQ_MODIFY_QP_PATH_MTU_MTU_256; 1262 case IB_MTU_512: 1263 return CMDQ_MODIFY_QP_PATH_MTU_MTU_512; 1264 case IB_MTU_1024: 1265 return CMDQ_MODIFY_QP_PATH_MTU_MTU_1024; 1266 case IB_MTU_2048: 1267 return CMDQ_MODIFY_QP_PATH_MTU_MTU_2048; 1268 case IB_MTU_4096: 1269 return CMDQ_MODIFY_QP_PATH_MTU_MTU_4096; 1270 default: 1271 return CMDQ_MODIFY_QP_PATH_MTU_MTU_2048; 1272 } 1273 } 1274 1275 static enum ib_mtu __to_ib_mtu(u32 mtu) 1276 { 1277 switch (mtu & CREQ_QUERY_QP_RESP_SB_PATH_MTU_MASK) { 1278 case CMDQ_MODIFY_QP_PATH_MTU_MTU_256: 1279 return IB_MTU_256; 1280 case CMDQ_MODIFY_QP_PATH_MTU_MTU_512: 1281 return IB_MTU_512; 1282 case CMDQ_MODIFY_QP_PATH_MTU_MTU_1024: 1283 return IB_MTU_1024; 1284 case CMDQ_MODIFY_QP_PATH_MTU_MTU_2048: 1285 return IB_MTU_2048; 1286 case CMDQ_MODIFY_QP_PATH_MTU_MTU_4096: 1287 return IB_MTU_4096; 1288 default: 1289 return IB_MTU_2048; 1290 } 1291 } 1292 1293 static int bnxt_re_modify_shadow_qp(struct bnxt_re_dev *rdev, 1294 struct bnxt_re_qp *qp1_qp, 1295 int qp_attr_mask) 1296 { 1297 struct bnxt_re_qp *qp = rdev->qp1_sqp; 1298 int rc = 0; 1299 1300 if (qp_attr_mask & IB_QP_STATE) { 1301 qp->qplib_qp.modify_flags |= CMDQ_MODIFY_QP_MODIFY_MASK_STATE; 1302 qp->qplib_qp.state = qp1_qp->qplib_qp.state; 1303 } 1304 if (qp_attr_mask & IB_QP_PKEY_INDEX) { 1305 qp->qplib_qp.modify_flags |= CMDQ_MODIFY_QP_MODIFY_MASK_PKEY; 1306 qp->qplib_qp.pkey_index = qp1_qp->qplib_qp.pkey_index; 1307 } 1308 1309 if (qp_attr_mask & IB_QP_QKEY) { 1310 qp->qplib_qp.modify_flags |= CMDQ_MODIFY_QP_MODIFY_MASK_QKEY; 1311 /* Using a Random QKEY */ 1312 qp->qplib_qp.qkey = 0x81818181; 1313 } 1314 if (qp_attr_mask & IB_QP_SQ_PSN) { 1315 qp->qplib_qp.modify_flags |= CMDQ_MODIFY_QP_MODIFY_MASK_SQ_PSN; 1316 qp->qplib_qp.sq.psn = qp1_qp->qplib_qp.sq.psn; 1317 } 1318 1319 rc = bnxt_qplib_modify_qp(&rdev->qplib_res, &qp->qplib_qp); 1320 if (rc) 1321 dev_err(rdev_to_dev(rdev), 1322 "Failed to modify Shadow QP for QP1"); 1323 return rc; 1324 } 1325 1326 int bnxt_re_modify_qp(struct ib_qp *ib_qp, struct ib_qp_attr *qp_attr, 1327 int qp_attr_mask, struct ib_udata *udata) 1328 { 1329 struct bnxt_re_qp *qp = container_of(ib_qp, struct bnxt_re_qp, ib_qp); 1330 struct bnxt_re_dev *rdev = qp->rdev; 1331 struct bnxt_qplib_dev_attr *dev_attr = &rdev->dev_attr; 1332 enum ib_qp_state curr_qp_state, new_qp_state; 1333 int rc, entries; 1334 int status; 1335 union ib_gid sgid; 1336 struct ib_gid_attr sgid_attr; 1337 u8 nw_type; 1338 1339 qp->qplib_qp.modify_flags = 0; 1340 if (qp_attr_mask & IB_QP_STATE) { 1341 curr_qp_state = __to_ib_qp_state(qp->qplib_qp.cur_qp_state); 1342 new_qp_state = qp_attr->qp_state; 1343 if (!ib_modify_qp_is_ok(curr_qp_state, new_qp_state, 1344 ib_qp->qp_type, qp_attr_mask, 1345 IB_LINK_LAYER_ETHERNET)) { 1346 dev_err(rdev_to_dev(rdev), 1347 "Invalid attribute mask: %#x specified ", 1348 qp_attr_mask); 1349 dev_err(rdev_to_dev(rdev), 1350 "for qpn: %#x type: %#x", 1351 ib_qp->qp_num, ib_qp->qp_type); 1352 dev_err(rdev_to_dev(rdev), 1353 "curr_qp_state=0x%x, new_qp_state=0x%x\n", 1354 curr_qp_state, new_qp_state); 1355 return -EINVAL; 1356 } 1357 qp->qplib_qp.modify_flags |= CMDQ_MODIFY_QP_MODIFY_MASK_STATE; 1358 qp->qplib_qp.state = __from_ib_qp_state(qp_attr->qp_state); 1359 1360 if (!qp->sumem && 1361 qp->qplib_qp.state == CMDQ_MODIFY_QP_NEW_STATE_ERR) { 1362 dev_dbg(rdev_to_dev(rdev), 1363 "Move QP = %p to flush list\n", 1364 qp); 1365 bnxt_qplib_add_flush_qp(&qp->qplib_qp); 1366 } 1367 if (!qp->sumem && 1368 qp->qplib_qp.state == CMDQ_MODIFY_QP_NEW_STATE_RESET) { 1369 dev_dbg(rdev_to_dev(rdev), 1370 "Move QP = %p out of flush list\n", 1371 qp); 1372 bnxt_qplib_del_flush_qp(&qp->qplib_qp); 1373 } 1374 } 1375 if (qp_attr_mask & IB_QP_EN_SQD_ASYNC_NOTIFY) { 1376 qp->qplib_qp.modify_flags |= 1377 CMDQ_MODIFY_QP_MODIFY_MASK_EN_SQD_ASYNC_NOTIFY; 1378 qp->qplib_qp.en_sqd_async_notify = true; 1379 } 1380 if (qp_attr_mask & IB_QP_ACCESS_FLAGS) { 1381 qp->qplib_qp.modify_flags |= CMDQ_MODIFY_QP_MODIFY_MASK_ACCESS; 1382 qp->qplib_qp.access = 1383 __from_ib_access_flags(qp_attr->qp_access_flags); 1384 /* LOCAL_WRITE access must be set to allow RC receive */ 1385 qp->qplib_qp.access |= BNXT_QPLIB_ACCESS_LOCAL_WRITE; 1386 } 1387 if (qp_attr_mask & IB_QP_PKEY_INDEX) { 1388 qp->qplib_qp.modify_flags |= CMDQ_MODIFY_QP_MODIFY_MASK_PKEY; 1389 qp->qplib_qp.pkey_index = qp_attr->pkey_index; 1390 } 1391 if (qp_attr_mask & IB_QP_QKEY) { 1392 qp->qplib_qp.modify_flags |= CMDQ_MODIFY_QP_MODIFY_MASK_QKEY; 1393 qp->qplib_qp.qkey = qp_attr->qkey; 1394 } 1395 if (qp_attr_mask & IB_QP_AV) { 1396 const struct ib_global_route *grh = 1397 rdma_ah_read_grh(&qp_attr->ah_attr); 1398 1399 qp->qplib_qp.modify_flags |= CMDQ_MODIFY_QP_MODIFY_MASK_DGID | 1400 CMDQ_MODIFY_QP_MODIFY_MASK_FLOW_LABEL | 1401 CMDQ_MODIFY_QP_MODIFY_MASK_SGID_INDEX | 1402 CMDQ_MODIFY_QP_MODIFY_MASK_HOP_LIMIT | 1403 CMDQ_MODIFY_QP_MODIFY_MASK_TRAFFIC_CLASS | 1404 CMDQ_MODIFY_QP_MODIFY_MASK_DEST_MAC | 1405 CMDQ_MODIFY_QP_MODIFY_MASK_VLAN_ID; 1406 memcpy(qp->qplib_qp.ah.dgid.data, grh->dgid.raw, 1407 sizeof(qp->qplib_qp.ah.dgid.data)); 1408 qp->qplib_qp.ah.flow_label = grh->flow_label; 1409 /* If RoCE V2 is enabled, stack will have two entries for 1410 * each GID entry. Avoiding this duplicte entry in HW. Dividing 1411 * the GID index by 2 for RoCE V2 1412 */ 1413 qp->qplib_qp.ah.sgid_index = grh->sgid_index / 2; 1414 qp->qplib_qp.ah.host_sgid_index = grh->sgid_index; 1415 qp->qplib_qp.ah.hop_limit = grh->hop_limit; 1416 qp->qplib_qp.ah.traffic_class = grh->traffic_class; 1417 qp->qplib_qp.ah.sl = rdma_ah_get_sl(&qp_attr->ah_attr); 1418 ether_addr_copy(qp->qplib_qp.ah.dmac, 1419 qp_attr->ah_attr.roce.dmac); 1420 1421 status = ib_get_cached_gid(&rdev->ibdev, 1, 1422 grh->sgid_index, 1423 &sgid, &sgid_attr); 1424 if (!status && sgid_attr.ndev) { 1425 memcpy(qp->qplib_qp.smac, sgid_attr.ndev->dev_addr, 1426 ETH_ALEN); 1427 dev_put(sgid_attr.ndev); 1428 nw_type = ib_gid_to_network_type(sgid_attr.gid_type, 1429 &sgid); 1430 switch (nw_type) { 1431 case RDMA_NETWORK_IPV4: 1432 qp->qplib_qp.nw_type = 1433 CMDQ_MODIFY_QP_NETWORK_TYPE_ROCEV2_IPV4; 1434 break; 1435 case RDMA_NETWORK_IPV6: 1436 qp->qplib_qp.nw_type = 1437 CMDQ_MODIFY_QP_NETWORK_TYPE_ROCEV2_IPV6; 1438 break; 1439 default: 1440 qp->qplib_qp.nw_type = 1441 CMDQ_MODIFY_QP_NETWORK_TYPE_ROCEV1; 1442 break; 1443 } 1444 } 1445 } 1446 1447 if (qp_attr_mask & IB_QP_PATH_MTU) { 1448 qp->qplib_qp.modify_flags |= 1449 CMDQ_MODIFY_QP_MODIFY_MASK_PATH_MTU; 1450 qp->qplib_qp.path_mtu = __from_ib_mtu(qp_attr->path_mtu); 1451 qp->qplib_qp.mtu = ib_mtu_enum_to_int(qp_attr->path_mtu); 1452 } else if (qp_attr->qp_state == IB_QPS_RTR) { 1453 qp->qplib_qp.modify_flags |= 1454 CMDQ_MODIFY_QP_MODIFY_MASK_PATH_MTU; 1455 qp->qplib_qp.path_mtu = 1456 __from_ib_mtu(iboe_get_mtu(rdev->netdev->mtu)); 1457 qp->qplib_qp.mtu = 1458 ib_mtu_enum_to_int(iboe_get_mtu(rdev->netdev->mtu)); 1459 } 1460 1461 if (qp_attr_mask & IB_QP_TIMEOUT) { 1462 qp->qplib_qp.modify_flags |= CMDQ_MODIFY_QP_MODIFY_MASK_TIMEOUT; 1463 qp->qplib_qp.timeout = qp_attr->timeout; 1464 } 1465 if (qp_attr_mask & IB_QP_RETRY_CNT) { 1466 qp->qplib_qp.modify_flags |= 1467 CMDQ_MODIFY_QP_MODIFY_MASK_RETRY_CNT; 1468 qp->qplib_qp.retry_cnt = qp_attr->retry_cnt; 1469 } 1470 if (qp_attr_mask & IB_QP_RNR_RETRY) { 1471 qp->qplib_qp.modify_flags |= 1472 CMDQ_MODIFY_QP_MODIFY_MASK_RNR_RETRY; 1473 qp->qplib_qp.rnr_retry = qp_attr->rnr_retry; 1474 } 1475 if (qp_attr_mask & IB_QP_MIN_RNR_TIMER) { 1476 qp->qplib_qp.modify_flags |= 1477 CMDQ_MODIFY_QP_MODIFY_MASK_MIN_RNR_TIMER; 1478 qp->qplib_qp.min_rnr_timer = qp_attr->min_rnr_timer; 1479 } 1480 if (qp_attr_mask & IB_QP_RQ_PSN) { 1481 qp->qplib_qp.modify_flags |= CMDQ_MODIFY_QP_MODIFY_MASK_RQ_PSN; 1482 qp->qplib_qp.rq.psn = qp_attr->rq_psn; 1483 } 1484 if (qp_attr_mask & IB_QP_MAX_QP_RD_ATOMIC) { 1485 qp->qplib_qp.modify_flags |= 1486 CMDQ_MODIFY_QP_MODIFY_MASK_MAX_RD_ATOMIC; 1487 /* Cap the max_rd_atomic to device max */ 1488 qp->qplib_qp.max_rd_atomic = min_t(u32, qp_attr->max_rd_atomic, 1489 dev_attr->max_qp_rd_atom); 1490 } 1491 if (qp_attr_mask & IB_QP_SQ_PSN) { 1492 qp->qplib_qp.modify_flags |= CMDQ_MODIFY_QP_MODIFY_MASK_SQ_PSN; 1493 qp->qplib_qp.sq.psn = qp_attr->sq_psn; 1494 } 1495 if (qp_attr_mask & IB_QP_MAX_DEST_RD_ATOMIC) { 1496 if (qp_attr->max_dest_rd_atomic > 1497 dev_attr->max_qp_init_rd_atom) { 1498 dev_err(rdev_to_dev(rdev), 1499 "max_dest_rd_atomic requested%d is > dev_max%d", 1500 qp_attr->max_dest_rd_atomic, 1501 dev_attr->max_qp_init_rd_atom); 1502 return -EINVAL; 1503 } 1504 1505 qp->qplib_qp.modify_flags |= 1506 CMDQ_MODIFY_QP_MODIFY_MASK_MAX_DEST_RD_ATOMIC; 1507 qp->qplib_qp.max_dest_rd_atomic = qp_attr->max_dest_rd_atomic; 1508 } 1509 if (qp_attr_mask & IB_QP_CAP) { 1510 qp->qplib_qp.modify_flags |= 1511 CMDQ_MODIFY_QP_MODIFY_MASK_SQ_SIZE | 1512 CMDQ_MODIFY_QP_MODIFY_MASK_RQ_SIZE | 1513 CMDQ_MODIFY_QP_MODIFY_MASK_SQ_SGE | 1514 CMDQ_MODIFY_QP_MODIFY_MASK_RQ_SGE | 1515 CMDQ_MODIFY_QP_MODIFY_MASK_MAX_INLINE_DATA; 1516 if ((qp_attr->cap.max_send_wr >= dev_attr->max_qp_wqes) || 1517 (qp_attr->cap.max_recv_wr >= dev_attr->max_qp_wqes) || 1518 (qp_attr->cap.max_send_sge >= dev_attr->max_qp_sges) || 1519 (qp_attr->cap.max_recv_sge >= dev_attr->max_qp_sges) || 1520 (qp_attr->cap.max_inline_data >= 1521 dev_attr->max_inline_data)) { 1522 dev_err(rdev_to_dev(rdev), 1523 "Create QP failed - max exceeded"); 1524 return -EINVAL; 1525 } 1526 entries = roundup_pow_of_two(qp_attr->cap.max_send_wr); 1527 qp->qplib_qp.sq.max_wqe = min_t(u32, entries, 1528 dev_attr->max_qp_wqes + 1); 1529 qp->qplib_qp.sq.q_full_delta = qp->qplib_qp.sq.max_wqe - 1530 qp_attr->cap.max_send_wr; 1531 /* 1532 * Reserving one slot for Phantom WQE. Some application can 1533 * post one extra entry in this case. Allowing this to avoid 1534 * unexpected Queue full condition 1535 */ 1536 qp->qplib_qp.sq.q_full_delta -= 1; 1537 qp->qplib_qp.sq.max_sge = qp_attr->cap.max_send_sge; 1538 if (qp->qplib_qp.rq.max_wqe) { 1539 entries = roundup_pow_of_two(qp_attr->cap.max_recv_wr); 1540 qp->qplib_qp.rq.max_wqe = 1541 min_t(u32, entries, dev_attr->max_qp_wqes + 1); 1542 qp->qplib_qp.rq.q_full_delta = qp->qplib_qp.rq.max_wqe - 1543 qp_attr->cap.max_recv_wr; 1544 qp->qplib_qp.rq.max_sge = qp_attr->cap.max_recv_sge; 1545 } else { 1546 /* SRQ was used prior, just ignore the RQ caps */ 1547 } 1548 } 1549 if (qp_attr_mask & IB_QP_DEST_QPN) { 1550 qp->qplib_qp.modify_flags |= 1551 CMDQ_MODIFY_QP_MODIFY_MASK_DEST_QP_ID; 1552 qp->qplib_qp.dest_qpn = qp_attr->dest_qp_num; 1553 } 1554 rc = bnxt_qplib_modify_qp(&rdev->qplib_res, &qp->qplib_qp); 1555 if (rc) { 1556 dev_err(rdev_to_dev(rdev), "Failed to modify HW QP"); 1557 return rc; 1558 } 1559 if (ib_qp->qp_type == IB_QPT_GSI && rdev->qp1_sqp) 1560 rc = bnxt_re_modify_shadow_qp(rdev, qp, qp_attr_mask); 1561 return rc; 1562 } 1563 1564 int bnxt_re_query_qp(struct ib_qp *ib_qp, struct ib_qp_attr *qp_attr, 1565 int qp_attr_mask, struct ib_qp_init_attr *qp_init_attr) 1566 { 1567 struct bnxt_re_qp *qp = container_of(ib_qp, struct bnxt_re_qp, ib_qp); 1568 struct bnxt_re_dev *rdev = qp->rdev; 1569 struct bnxt_qplib_qp *qplib_qp; 1570 int rc; 1571 1572 qplib_qp = kzalloc(sizeof(*qplib_qp), GFP_KERNEL); 1573 if (!qplib_qp) 1574 return -ENOMEM; 1575 1576 qplib_qp->id = qp->qplib_qp.id; 1577 qplib_qp->ah.host_sgid_index = qp->qplib_qp.ah.host_sgid_index; 1578 1579 rc = bnxt_qplib_query_qp(&rdev->qplib_res, qplib_qp); 1580 if (rc) { 1581 dev_err(rdev_to_dev(rdev), "Failed to query HW QP"); 1582 goto out; 1583 } 1584 qp_attr->qp_state = __to_ib_qp_state(qplib_qp->state); 1585 qp_attr->en_sqd_async_notify = qplib_qp->en_sqd_async_notify ? 1 : 0; 1586 qp_attr->qp_access_flags = __to_ib_access_flags(qplib_qp->access); 1587 qp_attr->pkey_index = qplib_qp->pkey_index; 1588 qp_attr->qkey = qplib_qp->qkey; 1589 qp_attr->ah_attr.type = RDMA_AH_ATTR_TYPE_ROCE; 1590 rdma_ah_set_grh(&qp_attr->ah_attr, NULL, qplib_qp->ah.flow_label, 1591 qplib_qp->ah.host_sgid_index, 1592 qplib_qp->ah.hop_limit, 1593 qplib_qp->ah.traffic_class); 1594 rdma_ah_set_dgid_raw(&qp_attr->ah_attr, qplib_qp->ah.dgid.data); 1595 rdma_ah_set_sl(&qp_attr->ah_attr, qplib_qp->ah.sl); 1596 ether_addr_copy(qp_attr->ah_attr.roce.dmac, qplib_qp->ah.dmac); 1597 qp_attr->path_mtu = __to_ib_mtu(qplib_qp->path_mtu); 1598 qp_attr->timeout = qplib_qp->timeout; 1599 qp_attr->retry_cnt = qplib_qp->retry_cnt; 1600 qp_attr->rnr_retry = qplib_qp->rnr_retry; 1601 qp_attr->min_rnr_timer = qplib_qp->min_rnr_timer; 1602 qp_attr->rq_psn = qplib_qp->rq.psn; 1603 qp_attr->max_rd_atomic = qplib_qp->max_rd_atomic; 1604 qp_attr->sq_psn = qplib_qp->sq.psn; 1605 qp_attr->max_dest_rd_atomic = qplib_qp->max_dest_rd_atomic; 1606 qp_init_attr->sq_sig_type = qplib_qp->sig_type ? IB_SIGNAL_ALL_WR : 1607 IB_SIGNAL_REQ_WR; 1608 qp_attr->dest_qp_num = qplib_qp->dest_qpn; 1609 1610 qp_attr->cap.max_send_wr = qp->qplib_qp.sq.max_wqe; 1611 qp_attr->cap.max_send_sge = qp->qplib_qp.sq.max_sge; 1612 qp_attr->cap.max_recv_wr = qp->qplib_qp.rq.max_wqe; 1613 qp_attr->cap.max_recv_sge = qp->qplib_qp.rq.max_sge; 1614 qp_attr->cap.max_inline_data = qp->qplib_qp.max_inline_data; 1615 qp_init_attr->cap = qp_attr->cap; 1616 1617 out: 1618 kfree(qplib_qp); 1619 return rc; 1620 } 1621 1622 /* Routine for sending QP1 packets for RoCE V1 an V2 1623 */ 1624 static int bnxt_re_build_qp1_send_v2(struct bnxt_re_qp *qp, 1625 struct ib_send_wr *wr, 1626 struct bnxt_qplib_swqe *wqe, 1627 int payload_size) 1628 { 1629 struct ib_device *ibdev = &qp->rdev->ibdev; 1630 struct bnxt_re_ah *ah = container_of(ud_wr(wr)->ah, struct bnxt_re_ah, 1631 ib_ah); 1632 struct bnxt_qplib_ah *qplib_ah = &ah->qplib_ah; 1633 struct bnxt_qplib_sge sge; 1634 union ib_gid sgid; 1635 u8 nw_type; 1636 u16 ether_type; 1637 struct ib_gid_attr sgid_attr; 1638 union ib_gid dgid; 1639 bool is_eth = false; 1640 bool is_vlan = false; 1641 bool is_grh = false; 1642 bool is_udp = false; 1643 u8 ip_version = 0; 1644 u16 vlan_id = 0xFFFF; 1645 void *buf; 1646 int i, rc = 0, size; 1647 1648 memset(&qp->qp1_hdr, 0, sizeof(qp->qp1_hdr)); 1649 1650 rc = ib_get_cached_gid(ibdev, 1, 1651 qplib_ah->host_sgid_index, &sgid, 1652 &sgid_attr); 1653 if (rc) { 1654 dev_err(rdev_to_dev(qp->rdev), 1655 "Failed to query gid at index %d", 1656 qplib_ah->host_sgid_index); 1657 return rc; 1658 } 1659 if (sgid_attr.ndev) { 1660 if (is_vlan_dev(sgid_attr.ndev)) 1661 vlan_id = vlan_dev_vlan_id(sgid_attr.ndev); 1662 dev_put(sgid_attr.ndev); 1663 } 1664 /* Get network header type for this GID */ 1665 nw_type = ib_gid_to_network_type(sgid_attr.gid_type, &sgid); 1666 switch (nw_type) { 1667 case RDMA_NETWORK_IPV4: 1668 nw_type = BNXT_RE_ROCEV2_IPV4_PACKET; 1669 break; 1670 case RDMA_NETWORK_IPV6: 1671 nw_type = BNXT_RE_ROCEV2_IPV6_PACKET; 1672 break; 1673 default: 1674 nw_type = BNXT_RE_ROCE_V1_PACKET; 1675 break; 1676 } 1677 memcpy(&dgid.raw, &qplib_ah->dgid, 16); 1678 is_udp = sgid_attr.gid_type == IB_GID_TYPE_ROCE_UDP_ENCAP; 1679 if (is_udp) { 1680 if (ipv6_addr_v4mapped((struct in6_addr *)&sgid)) { 1681 ip_version = 4; 1682 ether_type = ETH_P_IP; 1683 } else { 1684 ip_version = 6; 1685 ether_type = ETH_P_IPV6; 1686 } 1687 is_grh = false; 1688 } else { 1689 ether_type = ETH_P_IBOE; 1690 is_grh = true; 1691 } 1692 1693 is_eth = true; 1694 is_vlan = (vlan_id && (vlan_id < 0x1000)) ? true : false; 1695 1696 ib_ud_header_init(payload_size, !is_eth, is_eth, is_vlan, is_grh, 1697 ip_version, is_udp, 0, &qp->qp1_hdr); 1698 1699 /* ETH */ 1700 ether_addr_copy(qp->qp1_hdr.eth.dmac_h, ah->qplib_ah.dmac); 1701 ether_addr_copy(qp->qp1_hdr.eth.smac_h, qp->qplib_qp.smac); 1702 1703 /* For vlan, check the sgid for vlan existence */ 1704 1705 if (!is_vlan) { 1706 qp->qp1_hdr.eth.type = cpu_to_be16(ether_type); 1707 } else { 1708 qp->qp1_hdr.vlan.type = cpu_to_be16(ether_type); 1709 qp->qp1_hdr.vlan.tag = cpu_to_be16(vlan_id); 1710 } 1711 1712 if (is_grh || (ip_version == 6)) { 1713 memcpy(qp->qp1_hdr.grh.source_gid.raw, sgid.raw, sizeof(sgid)); 1714 memcpy(qp->qp1_hdr.grh.destination_gid.raw, qplib_ah->dgid.data, 1715 sizeof(sgid)); 1716 qp->qp1_hdr.grh.hop_limit = qplib_ah->hop_limit; 1717 } 1718 1719 if (ip_version == 4) { 1720 qp->qp1_hdr.ip4.tos = 0; 1721 qp->qp1_hdr.ip4.id = 0; 1722 qp->qp1_hdr.ip4.frag_off = htons(IP_DF); 1723 qp->qp1_hdr.ip4.ttl = qplib_ah->hop_limit; 1724 1725 memcpy(&qp->qp1_hdr.ip4.saddr, sgid.raw + 12, 4); 1726 memcpy(&qp->qp1_hdr.ip4.daddr, qplib_ah->dgid.data + 12, 4); 1727 qp->qp1_hdr.ip4.check = ib_ud_ip4_csum(&qp->qp1_hdr); 1728 } 1729 1730 if (is_udp) { 1731 qp->qp1_hdr.udp.dport = htons(ROCE_V2_UDP_DPORT); 1732 qp->qp1_hdr.udp.sport = htons(0x8CD1); 1733 qp->qp1_hdr.udp.csum = 0; 1734 } 1735 1736 /* BTH */ 1737 if (wr->opcode == IB_WR_SEND_WITH_IMM) { 1738 qp->qp1_hdr.bth.opcode = IB_OPCODE_UD_SEND_ONLY_WITH_IMMEDIATE; 1739 qp->qp1_hdr.immediate_present = 1; 1740 } else { 1741 qp->qp1_hdr.bth.opcode = IB_OPCODE_UD_SEND_ONLY; 1742 } 1743 if (wr->send_flags & IB_SEND_SOLICITED) 1744 qp->qp1_hdr.bth.solicited_event = 1; 1745 /* pad_count */ 1746 qp->qp1_hdr.bth.pad_count = (4 - payload_size) & 3; 1747 1748 /* P_key for QP1 is for all members */ 1749 qp->qp1_hdr.bth.pkey = cpu_to_be16(0xFFFF); 1750 qp->qp1_hdr.bth.destination_qpn = IB_QP1; 1751 qp->qp1_hdr.bth.ack_req = 0; 1752 qp->send_psn++; 1753 qp->send_psn &= BTH_PSN_MASK; 1754 qp->qp1_hdr.bth.psn = cpu_to_be32(qp->send_psn); 1755 /* DETH */ 1756 /* Use the priviledged Q_Key for QP1 */ 1757 qp->qp1_hdr.deth.qkey = cpu_to_be32(IB_QP1_QKEY); 1758 qp->qp1_hdr.deth.source_qpn = IB_QP1; 1759 1760 /* Pack the QP1 to the transmit buffer */ 1761 buf = bnxt_qplib_get_qp1_sq_buf(&qp->qplib_qp, &sge); 1762 if (buf) { 1763 size = ib_ud_header_pack(&qp->qp1_hdr, buf); 1764 for (i = wqe->num_sge; i; i--) { 1765 wqe->sg_list[i].addr = wqe->sg_list[i - 1].addr; 1766 wqe->sg_list[i].lkey = wqe->sg_list[i - 1].lkey; 1767 wqe->sg_list[i].size = wqe->sg_list[i - 1].size; 1768 } 1769 1770 /* 1771 * Max Header buf size for IPV6 RoCE V2 is 86, 1772 * which is same as the QP1 SQ header buffer. 1773 * Header buf size for IPV4 RoCE V2 can be 66. 1774 * ETH(14) + VLAN(4)+ IP(20) + UDP (8) + BTH(20). 1775 * Subtract 20 bytes from QP1 SQ header buf size 1776 */ 1777 if (is_udp && ip_version == 4) 1778 sge.size -= 20; 1779 /* 1780 * Max Header buf size for RoCE V1 is 78. 1781 * ETH(14) + VLAN(4) + GRH(40) + BTH(20). 1782 * Subtract 8 bytes from QP1 SQ header buf size 1783 */ 1784 if (!is_udp) 1785 sge.size -= 8; 1786 1787 /* Subtract 4 bytes for non vlan packets */ 1788 if (!is_vlan) 1789 sge.size -= 4; 1790 1791 wqe->sg_list[0].addr = sge.addr; 1792 wqe->sg_list[0].lkey = sge.lkey; 1793 wqe->sg_list[0].size = sge.size; 1794 wqe->num_sge++; 1795 1796 } else { 1797 dev_err(rdev_to_dev(qp->rdev), "QP1 buffer is empty!"); 1798 rc = -ENOMEM; 1799 } 1800 return rc; 1801 } 1802 1803 /* For the MAD layer, it only provides the recv SGE the size of 1804 * ib_grh + MAD datagram. No Ethernet headers, Ethertype, BTH, DETH, 1805 * nor RoCE iCRC. The Cu+ solution must provide buffer for the entire 1806 * receive packet (334 bytes) with no VLAN and then copy the GRH 1807 * and the MAD datagram out to the provided SGE. 1808 */ 1809 static int bnxt_re_build_qp1_shadow_qp_recv(struct bnxt_re_qp *qp, 1810 struct ib_recv_wr *wr, 1811 struct bnxt_qplib_swqe *wqe, 1812 int payload_size) 1813 { 1814 struct bnxt_qplib_sge ref, sge; 1815 u32 rq_prod_index; 1816 struct bnxt_re_sqp_entries *sqp_entry; 1817 1818 rq_prod_index = bnxt_qplib_get_rq_prod_index(&qp->qplib_qp); 1819 1820 if (!bnxt_qplib_get_qp1_rq_buf(&qp->qplib_qp, &sge)) 1821 return -ENOMEM; 1822 1823 /* Create 1 SGE to receive the entire 1824 * ethernet packet 1825 */ 1826 /* Save the reference from ULP */ 1827 ref.addr = wqe->sg_list[0].addr; 1828 ref.lkey = wqe->sg_list[0].lkey; 1829 ref.size = wqe->sg_list[0].size; 1830 1831 sqp_entry = &qp->rdev->sqp_tbl[rq_prod_index]; 1832 1833 /* SGE 1 */ 1834 wqe->sg_list[0].addr = sge.addr; 1835 wqe->sg_list[0].lkey = sge.lkey; 1836 wqe->sg_list[0].size = BNXT_QPLIB_MAX_QP1_RQ_HDR_SIZE_V2; 1837 sge.size -= wqe->sg_list[0].size; 1838 1839 sqp_entry->sge.addr = ref.addr; 1840 sqp_entry->sge.lkey = ref.lkey; 1841 sqp_entry->sge.size = ref.size; 1842 /* Store the wrid for reporting completion */ 1843 sqp_entry->wrid = wqe->wr_id; 1844 /* change the wqe->wrid to table index */ 1845 wqe->wr_id = rq_prod_index; 1846 return 0; 1847 } 1848 1849 static int is_ud_qp(struct bnxt_re_qp *qp) 1850 { 1851 return qp->qplib_qp.type == CMDQ_CREATE_QP_TYPE_UD; 1852 } 1853 1854 static int bnxt_re_build_send_wqe(struct bnxt_re_qp *qp, 1855 struct ib_send_wr *wr, 1856 struct bnxt_qplib_swqe *wqe) 1857 { 1858 struct bnxt_re_ah *ah = NULL; 1859 1860 if (is_ud_qp(qp)) { 1861 ah = container_of(ud_wr(wr)->ah, struct bnxt_re_ah, ib_ah); 1862 wqe->send.q_key = ud_wr(wr)->remote_qkey; 1863 wqe->send.dst_qp = ud_wr(wr)->remote_qpn; 1864 wqe->send.avid = ah->qplib_ah.id; 1865 } 1866 switch (wr->opcode) { 1867 case IB_WR_SEND: 1868 wqe->type = BNXT_QPLIB_SWQE_TYPE_SEND; 1869 break; 1870 case IB_WR_SEND_WITH_IMM: 1871 wqe->type = BNXT_QPLIB_SWQE_TYPE_SEND_WITH_IMM; 1872 wqe->send.imm_data = wr->ex.imm_data; 1873 break; 1874 case IB_WR_SEND_WITH_INV: 1875 wqe->type = BNXT_QPLIB_SWQE_TYPE_SEND_WITH_INV; 1876 wqe->send.inv_key = wr->ex.invalidate_rkey; 1877 break; 1878 default: 1879 return -EINVAL; 1880 } 1881 if (wr->send_flags & IB_SEND_SIGNALED) 1882 wqe->flags |= BNXT_QPLIB_SWQE_FLAGS_SIGNAL_COMP; 1883 if (wr->send_flags & IB_SEND_FENCE) 1884 wqe->flags |= BNXT_QPLIB_SWQE_FLAGS_UC_FENCE; 1885 if (wr->send_flags & IB_SEND_SOLICITED) 1886 wqe->flags |= BNXT_QPLIB_SWQE_FLAGS_SOLICIT_EVENT; 1887 if (wr->send_flags & IB_SEND_INLINE) 1888 wqe->flags |= BNXT_QPLIB_SWQE_FLAGS_INLINE; 1889 1890 return 0; 1891 } 1892 1893 static int bnxt_re_build_rdma_wqe(struct ib_send_wr *wr, 1894 struct bnxt_qplib_swqe *wqe) 1895 { 1896 switch (wr->opcode) { 1897 case IB_WR_RDMA_WRITE: 1898 wqe->type = BNXT_QPLIB_SWQE_TYPE_RDMA_WRITE; 1899 break; 1900 case IB_WR_RDMA_WRITE_WITH_IMM: 1901 wqe->type = BNXT_QPLIB_SWQE_TYPE_RDMA_WRITE_WITH_IMM; 1902 wqe->rdma.imm_data = wr->ex.imm_data; 1903 break; 1904 case IB_WR_RDMA_READ: 1905 wqe->type = BNXT_QPLIB_SWQE_TYPE_RDMA_READ; 1906 wqe->rdma.inv_key = wr->ex.invalidate_rkey; 1907 break; 1908 default: 1909 return -EINVAL; 1910 } 1911 wqe->rdma.remote_va = rdma_wr(wr)->remote_addr; 1912 wqe->rdma.r_key = rdma_wr(wr)->rkey; 1913 if (wr->send_flags & IB_SEND_SIGNALED) 1914 wqe->flags |= BNXT_QPLIB_SWQE_FLAGS_SIGNAL_COMP; 1915 if (wr->send_flags & IB_SEND_FENCE) 1916 wqe->flags |= BNXT_QPLIB_SWQE_FLAGS_UC_FENCE; 1917 if (wr->send_flags & IB_SEND_SOLICITED) 1918 wqe->flags |= BNXT_QPLIB_SWQE_FLAGS_SOLICIT_EVENT; 1919 if (wr->send_flags & IB_SEND_INLINE) 1920 wqe->flags |= BNXT_QPLIB_SWQE_FLAGS_INLINE; 1921 1922 return 0; 1923 } 1924 1925 static int bnxt_re_build_atomic_wqe(struct ib_send_wr *wr, 1926 struct bnxt_qplib_swqe *wqe) 1927 { 1928 switch (wr->opcode) { 1929 case IB_WR_ATOMIC_CMP_AND_SWP: 1930 wqe->type = BNXT_QPLIB_SWQE_TYPE_ATOMIC_CMP_AND_SWP; 1931 wqe->atomic.cmp_data = atomic_wr(wr)->compare_add; 1932 wqe->atomic.swap_data = atomic_wr(wr)->swap; 1933 break; 1934 case IB_WR_ATOMIC_FETCH_AND_ADD: 1935 wqe->type = BNXT_QPLIB_SWQE_TYPE_ATOMIC_FETCH_AND_ADD; 1936 wqe->atomic.cmp_data = atomic_wr(wr)->compare_add; 1937 break; 1938 default: 1939 return -EINVAL; 1940 } 1941 wqe->atomic.remote_va = atomic_wr(wr)->remote_addr; 1942 wqe->atomic.r_key = atomic_wr(wr)->rkey; 1943 if (wr->send_flags & IB_SEND_SIGNALED) 1944 wqe->flags |= BNXT_QPLIB_SWQE_FLAGS_SIGNAL_COMP; 1945 if (wr->send_flags & IB_SEND_FENCE) 1946 wqe->flags |= BNXT_QPLIB_SWQE_FLAGS_UC_FENCE; 1947 if (wr->send_flags & IB_SEND_SOLICITED) 1948 wqe->flags |= BNXT_QPLIB_SWQE_FLAGS_SOLICIT_EVENT; 1949 return 0; 1950 } 1951 1952 static int bnxt_re_build_inv_wqe(struct ib_send_wr *wr, 1953 struct bnxt_qplib_swqe *wqe) 1954 { 1955 wqe->type = BNXT_QPLIB_SWQE_TYPE_LOCAL_INV; 1956 wqe->local_inv.inv_l_key = wr->ex.invalidate_rkey; 1957 1958 if (wr->send_flags & IB_SEND_SIGNALED) 1959 wqe->flags |= BNXT_QPLIB_SWQE_FLAGS_SIGNAL_COMP; 1960 if (wr->send_flags & IB_SEND_FENCE) 1961 wqe->flags |= BNXT_QPLIB_SWQE_FLAGS_UC_FENCE; 1962 if (wr->send_flags & IB_SEND_SOLICITED) 1963 wqe->flags |= BNXT_QPLIB_SWQE_FLAGS_SOLICIT_EVENT; 1964 1965 return 0; 1966 } 1967 1968 static int bnxt_re_build_reg_wqe(struct ib_reg_wr *wr, 1969 struct bnxt_qplib_swqe *wqe) 1970 { 1971 struct bnxt_re_mr *mr = container_of(wr->mr, struct bnxt_re_mr, ib_mr); 1972 struct bnxt_qplib_frpl *qplib_frpl = &mr->qplib_frpl; 1973 int access = wr->access; 1974 1975 wqe->frmr.pbl_ptr = (__le64 *)qplib_frpl->hwq.pbl_ptr[0]; 1976 wqe->frmr.pbl_dma_ptr = qplib_frpl->hwq.pbl_dma_ptr[0]; 1977 wqe->frmr.page_list = mr->pages; 1978 wqe->frmr.page_list_len = mr->npages; 1979 wqe->frmr.levels = qplib_frpl->hwq.level + 1; 1980 wqe->type = BNXT_QPLIB_SWQE_TYPE_REG_MR; 1981 1982 if (wr->wr.send_flags & IB_SEND_FENCE) 1983 wqe->flags |= BNXT_QPLIB_SWQE_FLAGS_UC_FENCE; 1984 if (wr->wr.send_flags & IB_SEND_SIGNALED) 1985 wqe->flags |= BNXT_QPLIB_SWQE_FLAGS_SIGNAL_COMP; 1986 1987 if (access & IB_ACCESS_LOCAL_WRITE) 1988 wqe->frmr.access_cntl |= SQ_FR_PMR_ACCESS_CNTL_LOCAL_WRITE; 1989 if (access & IB_ACCESS_REMOTE_READ) 1990 wqe->frmr.access_cntl |= SQ_FR_PMR_ACCESS_CNTL_REMOTE_READ; 1991 if (access & IB_ACCESS_REMOTE_WRITE) 1992 wqe->frmr.access_cntl |= SQ_FR_PMR_ACCESS_CNTL_REMOTE_WRITE; 1993 if (access & IB_ACCESS_REMOTE_ATOMIC) 1994 wqe->frmr.access_cntl |= SQ_FR_PMR_ACCESS_CNTL_REMOTE_ATOMIC; 1995 if (access & IB_ACCESS_MW_BIND) 1996 wqe->frmr.access_cntl |= SQ_FR_PMR_ACCESS_CNTL_WINDOW_BIND; 1997 1998 wqe->frmr.l_key = wr->key; 1999 wqe->frmr.length = wr->mr->length; 2000 wqe->frmr.pbl_pg_sz_log = (wr->mr->page_size >> PAGE_SHIFT_4K) - 1; 2001 wqe->frmr.va = wr->mr->iova; 2002 return 0; 2003 } 2004 2005 static int bnxt_re_copy_inline_data(struct bnxt_re_dev *rdev, 2006 struct ib_send_wr *wr, 2007 struct bnxt_qplib_swqe *wqe) 2008 { 2009 /* Copy the inline data to the data field */ 2010 u8 *in_data; 2011 u32 i, sge_len; 2012 void *sge_addr; 2013 2014 in_data = wqe->inline_data; 2015 for (i = 0; i < wr->num_sge; i++) { 2016 sge_addr = (void *)(unsigned long) 2017 wr->sg_list[i].addr; 2018 sge_len = wr->sg_list[i].length; 2019 2020 if ((sge_len + wqe->inline_len) > 2021 BNXT_QPLIB_SWQE_MAX_INLINE_LENGTH) { 2022 dev_err(rdev_to_dev(rdev), 2023 "Inline data size requested > supported value"); 2024 return -EINVAL; 2025 } 2026 sge_len = wr->sg_list[i].length; 2027 2028 memcpy(in_data, sge_addr, sge_len); 2029 in_data += wr->sg_list[i].length; 2030 wqe->inline_len += wr->sg_list[i].length; 2031 } 2032 return wqe->inline_len; 2033 } 2034 2035 static int bnxt_re_copy_wr_payload(struct bnxt_re_dev *rdev, 2036 struct ib_send_wr *wr, 2037 struct bnxt_qplib_swqe *wqe) 2038 { 2039 int payload_sz = 0; 2040 2041 if (wr->send_flags & IB_SEND_INLINE) 2042 payload_sz = bnxt_re_copy_inline_data(rdev, wr, wqe); 2043 else 2044 payload_sz = bnxt_re_build_sgl(wr->sg_list, wqe->sg_list, 2045 wqe->num_sge); 2046 2047 return payload_sz; 2048 } 2049 2050 static void bnxt_ud_qp_hw_stall_workaround(struct bnxt_re_qp *qp) 2051 { 2052 if ((qp->ib_qp.qp_type == IB_QPT_UD || 2053 qp->ib_qp.qp_type == IB_QPT_GSI || 2054 qp->ib_qp.qp_type == IB_QPT_RAW_ETHERTYPE) && 2055 qp->qplib_qp.wqe_cnt == BNXT_RE_UD_QP_HW_STALL) { 2056 int qp_attr_mask; 2057 struct ib_qp_attr qp_attr; 2058 2059 qp_attr_mask = IB_QP_STATE; 2060 qp_attr.qp_state = IB_QPS_RTS; 2061 bnxt_re_modify_qp(&qp->ib_qp, &qp_attr, qp_attr_mask, NULL); 2062 qp->qplib_qp.wqe_cnt = 0; 2063 } 2064 } 2065 2066 static int bnxt_re_post_send_shadow_qp(struct bnxt_re_dev *rdev, 2067 struct bnxt_re_qp *qp, 2068 struct ib_send_wr *wr) 2069 { 2070 struct bnxt_qplib_swqe wqe; 2071 int rc = 0, payload_sz = 0; 2072 unsigned long flags; 2073 2074 spin_lock_irqsave(&qp->sq_lock, flags); 2075 memset(&wqe, 0, sizeof(wqe)); 2076 while (wr) { 2077 /* House keeping */ 2078 memset(&wqe, 0, sizeof(wqe)); 2079 2080 /* Common */ 2081 wqe.num_sge = wr->num_sge; 2082 if (wr->num_sge > qp->qplib_qp.sq.max_sge) { 2083 dev_err(rdev_to_dev(rdev), 2084 "Limit exceeded for Send SGEs"); 2085 rc = -EINVAL; 2086 goto bad; 2087 } 2088 2089 payload_sz = bnxt_re_copy_wr_payload(qp->rdev, wr, &wqe); 2090 if (payload_sz < 0) { 2091 rc = -EINVAL; 2092 goto bad; 2093 } 2094 wqe.wr_id = wr->wr_id; 2095 2096 wqe.type = BNXT_QPLIB_SWQE_TYPE_SEND; 2097 2098 rc = bnxt_re_build_send_wqe(qp, wr, &wqe); 2099 if (!rc) 2100 rc = bnxt_qplib_post_send(&qp->qplib_qp, &wqe); 2101 bad: 2102 if (rc) { 2103 dev_err(rdev_to_dev(rdev), 2104 "Post send failed opcode = %#x rc = %d", 2105 wr->opcode, rc); 2106 break; 2107 } 2108 wr = wr->next; 2109 } 2110 bnxt_qplib_post_send_db(&qp->qplib_qp); 2111 bnxt_ud_qp_hw_stall_workaround(qp); 2112 spin_unlock_irqrestore(&qp->sq_lock, flags); 2113 return rc; 2114 } 2115 2116 int bnxt_re_post_send(struct ib_qp *ib_qp, struct ib_send_wr *wr, 2117 struct ib_send_wr **bad_wr) 2118 { 2119 struct bnxt_re_qp *qp = container_of(ib_qp, struct bnxt_re_qp, ib_qp); 2120 struct bnxt_qplib_swqe wqe; 2121 int rc = 0, payload_sz = 0; 2122 unsigned long flags; 2123 2124 spin_lock_irqsave(&qp->sq_lock, flags); 2125 while (wr) { 2126 /* House keeping */ 2127 memset(&wqe, 0, sizeof(wqe)); 2128 2129 /* Common */ 2130 wqe.num_sge = wr->num_sge; 2131 if (wr->num_sge > qp->qplib_qp.sq.max_sge) { 2132 dev_err(rdev_to_dev(qp->rdev), 2133 "Limit exceeded for Send SGEs"); 2134 rc = -EINVAL; 2135 goto bad; 2136 } 2137 2138 payload_sz = bnxt_re_copy_wr_payload(qp->rdev, wr, &wqe); 2139 if (payload_sz < 0) { 2140 rc = -EINVAL; 2141 goto bad; 2142 } 2143 wqe.wr_id = wr->wr_id; 2144 2145 switch (wr->opcode) { 2146 case IB_WR_SEND: 2147 case IB_WR_SEND_WITH_IMM: 2148 if (ib_qp->qp_type == IB_QPT_GSI) { 2149 rc = bnxt_re_build_qp1_send_v2(qp, wr, &wqe, 2150 payload_sz); 2151 if (rc) 2152 goto bad; 2153 wqe.rawqp1.lflags |= 2154 SQ_SEND_RAWETH_QP1_LFLAGS_ROCE_CRC; 2155 } 2156 switch (wr->send_flags) { 2157 case IB_SEND_IP_CSUM: 2158 wqe.rawqp1.lflags |= 2159 SQ_SEND_RAWETH_QP1_LFLAGS_IP_CHKSUM; 2160 break; 2161 default: 2162 break; 2163 } 2164 /* Fall thru to build the wqe */ 2165 case IB_WR_SEND_WITH_INV: 2166 rc = bnxt_re_build_send_wqe(qp, wr, &wqe); 2167 break; 2168 case IB_WR_RDMA_WRITE: 2169 case IB_WR_RDMA_WRITE_WITH_IMM: 2170 case IB_WR_RDMA_READ: 2171 rc = bnxt_re_build_rdma_wqe(wr, &wqe); 2172 break; 2173 case IB_WR_ATOMIC_CMP_AND_SWP: 2174 case IB_WR_ATOMIC_FETCH_AND_ADD: 2175 rc = bnxt_re_build_atomic_wqe(wr, &wqe); 2176 break; 2177 case IB_WR_RDMA_READ_WITH_INV: 2178 dev_err(rdev_to_dev(qp->rdev), 2179 "RDMA Read with Invalidate is not supported"); 2180 rc = -EINVAL; 2181 goto bad; 2182 case IB_WR_LOCAL_INV: 2183 rc = bnxt_re_build_inv_wqe(wr, &wqe); 2184 break; 2185 case IB_WR_REG_MR: 2186 rc = bnxt_re_build_reg_wqe(reg_wr(wr), &wqe); 2187 break; 2188 default: 2189 /* Unsupported WRs */ 2190 dev_err(rdev_to_dev(qp->rdev), 2191 "WR (%#x) is not supported", wr->opcode); 2192 rc = -EINVAL; 2193 goto bad; 2194 } 2195 if (!rc) 2196 rc = bnxt_qplib_post_send(&qp->qplib_qp, &wqe); 2197 bad: 2198 if (rc) { 2199 dev_err(rdev_to_dev(qp->rdev), 2200 "post_send failed op:%#x qps = %#x rc = %d\n", 2201 wr->opcode, qp->qplib_qp.state, rc); 2202 *bad_wr = wr; 2203 break; 2204 } 2205 wr = wr->next; 2206 } 2207 bnxt_qplib_post_send_db(&qp->qplib_qp); 2208 bnxt_ud_qp_hw_stall_workaround(qp); 2209 spin_unlock_irqrestore(&qp->sq_lock, flags); 2210 2211 return rc; 2212 } 2213 2214 static int bnxt_re_post_recv_shadow_qp(struct bnxt_re_dev *rdev, 2215 struct bnxt_re_qp *qp, 2216 struct ib_recv_wr *wr) 2217 { 2218 struct bnxt_qplib_swqe wqe; 2219 int rc = 0, payload_sz = 0; 2220 2221 memset(&wqe, 0, sizeof(wqe)); 2222 while (wr) { 2223 /* House keeping */ 2224 memset(&wqe, 0, sizeof(wqe)); 2225 2226 /* Common */ 2227 wqe.num_sge = wr->num_sge; 2228 if (wr->num_sge > qp->qplib_qp.rq.max_sge) { 2229 dev_err(rdev_to_dev(rdev), 2230 "Limit exceeded for Receive SGEs"); 2231 rc = -EINVAL; 2232 break; 2233 } 2234 payload_sz = bnxt_re_build_sgl(wr->sg_list, wqe.sg_list, 2235 wr->num_sge); 2236 wqe.wr_id = wr->wr_id; 2237 wqe.type = BNXT_QPLIB_SWQE_TYPE_RECV; 2238 2239 rc = bnxt_qplib_post_recv(&qp->qplib_qp, &wqe); 2240 if (rc) 2241 break; 2242 2243 wr = wr->next; 2244 } 2245 if (!rc) 2246 bnxt_qplib_post_recv_db(&qp->qplib_qp); 2247 return rc; 2248 } 2249 2250 int bnxt_re_post_recv(struct ib_qp *ib_qp, struct ib_recv_wr *wr, 2251 struct ib_recv_wr **bad_wr) 2252 { 2253 struct bnxt_re_qp *qp = container_of(ib_qp, struct bnxt_re_qp, ib_qp); 2254 struct bnxt_qplib_swqe wqe; 2255 int rc = 0, payload_sz = 0; 2256 unsigned long flags; 2257 u32 count = 0; 2258 2259 spin_lock_irqsave(&qp->rq_lock, flags); 2260 while (wr) { 2261 /* House keeping */ 2262 memset(&wqe, 0, sizeof(wqe)); 2263 2264 /* Common */ 2265 wqe.num_sge = wr->num_sge; 2266 if (wr->num_sge > qp->qplib_qp.rq.max_sge) { 2267 dev_err(rdev_to_dev(qp->rdev), 2268 "Limit exceeded for Receive SGEs"); 2269 rc = -EINVAL; 2270 *bad_wr = wr; 2271 break; 2272 } 2273 2274 payload_sz = bnxt_re_build_sgl(wr->sg_list, wqe.sg_list, 2275 wr->num_sge); 2276 wqe.wr_id = wr->wr_id; 2277 wqe.type = BNXT_QPLIB_SWQE_TYPE_RECV; 2278 2279 if (ib_qp->qp_type == IB_QPT_GSI) 2280 rc = bnxt_re_build_qp1_shadow_qp_recv(qp, wr, &wqe, 2281 payload_sz); 2282 if (!rc) 2283 rc = bnxt_qplib_post_recv(&qp->qplib_qp, &wqe); 2284 if (rc) { 2285 *bad_wr = wr; 2286 break; 2287 } 2288 2289 /* Ring DB if the RQEs posted reaches a threshold value */ 2290 if (++count >= BNXT_RE_RQ_WQE_THRESHOLD) { 2291 bnxt_qplib_post_recv_db(&qp->qplib_qp); 2292 count = 0; 2293 } 2294 2295 wr = wr->next; 2296 } 2297 2298 if (count) 2299 bnxt_qplib_post_recv_db(&qp->qplib_qp); 2300 2301 spin_unlock_irqrestore(&qp->rq_lock, flags); 2302 2303 return rc; 2304 } 2305 2306 /* Completion Queues */ 2307 int bnxt_re_destroy_cq(struct ib_cq *ib_cq) 2308 { 2309 struct bnxt_re_cq *cq = container_of(ib_cq, struct bnxt_re_cq, ib_cq); 2310 struct bnxt_re_dev *rdev = cq->rdev; 2311 int rc; 2312 struct bnxt_qplib_nq *nq = cq->qplib_cq.nq; 2313 2314 rc = bnxt_qplib_destroy_cq(&rdev->qplib_res, &cq->qplib_cq); 2315 if (rc) { 2316 dev_err(rdev_to_dev(rdev), "Failed to destroy HW CQ"); 2317 return rc; 2318 } 2319 if (!IS_ERR_OR_NULL(cq->umem)) 2320 ib_umem_release(cq->umem); 2321 2322 if (cq) { 2323 kfree(cq->cql); 2324 kfree(cq); 2325 } 2326 atomic_dec(&rdev->cq_count); 2327 nq->budget--; 2328 return 0; 2329 } 2330 2331 struct ib_cq *bnxt_re_create_cq(struct ib_device *ibdev, 2332 const struct ib_cq_init_attr *attr, 2333 struct ib_ucontext *context, 2334 struct ib_udata *udata) 2335 { 2336 struct bnxt_re_dev *rdev = to_bnxt_re_dev(ibdev, ibdev); 2337 struct bnxt_qplib_dev_attr *dev_attr = &rdev->dev_attr; 2338 struct bnxt_re_cq *cq = NULL; 2339 int rc, entries; 2340 int cqe = attr->cqe; 2341 struct bnxt_qplib_nq *nq = NULL; 2342 unsigned int nq_alloc_cnt; 2343 2344 /* Validate CQ fields */ 2345 if (cqe < 1 || cqe > dev_attr->max_cq_wqes) { 2346 dev_err(rdev_to_dev(rdev), "Failed to create CQ -max exceeded"); 2347 return ERR_PTR(-EINVAL); 2348 } 2349 cq = kzalloc(sizeof(*cq), GFP_KERNEL); 2350 if (!cq) 2351 return ERR_PTR(-ENOMEM); 2352 2353 cq->rdev = rdev; 2354 cq->qplib_cq.cq_handle = (u64)(unsigned long)(&cq->qplib_cq); 2355 2356 entries = roundup_pow_of_two(cqe + 1); 2357 if (entries > dev_attr->max_cq_wqes + 1) 2358 entries = dev_attr->max_cq_wqes + 1; 2359 2360 if (context) { 2361 struct bnxt_re_cq_req req; 2362 struct bnxt_re_ucontext *uctx = container_of 2363 (context, 2364 struct bnxt_re_ucontext, 2365 ib_uctx); 2366 if (ib_copy_from_udata(&req, udata, sizeof(req))) { 2367 rc = -EFAULT; 2368 goto fail; 2369 } 2370 2371 cq->umem = ib_umem_get(context, req.cq_va, 2372 entries * sizeof(struct cq_base), 2373 IB_ACCESS_LOCAL_WRITE, 1); 2374 if (IS_ERR(cq->umem)) { 2375 rc = PTR_ERR(cq->umem); 2376 goto fail; 2377 } 2378 cq->qplib_cq.sghead = cq->umem->sg_head.sgl; 2379 cq->qplib_cq.nmap = cq->umem->nmap; 2380 cq->qplib_cq.dpi = &uctx->dpi; 2381 } else { 2382 cq->max_cql = min_t(u32, entries, MAX_CQL_PER_POLL); 2383 cq->cql = kcalloc(cq->max_cql, sizeof(struct bnxt_qplib_cqe), 2384 GFP_KERNEL); 2385 if (!cq->cql) { 2386 rc = -ENOMEM; 2387 goto fail; 2388 } 2389 2390 cq->qplib_cq.dpi = &rdev->dpi_privileged; 2391 cq->qplib_cq.sghead = NULL; 2392 cq->qplib_cq.nmap = 0; 2393 } 2394 /* 2395 * Allocating the NQ in a round robin fashion. nq_alloc_cnt is a 2396 * used for getting the NQ index. 2397 */ 2398 nq_alloc_cnt = atomic_inc_return(&rdev->nq_alloc_cnt); 2399 nq = &rdev->nq[nq_alloc_cnt % (rdev->num_msix - 1)]; 2400 cq->qplib_cq.max_wqe = entries; 2401 cq->qplib_cq.cnq_hw_ring_id = nq->ring_id; 2402 cq->qplib_cq.nq = nq; 2403 2404 rc = bnxt_qplib_create_cq(&rdev->qplib_res, &cq->qplib_cq); 2405 if (rc) { 2406 dev_err(rdev_to_dev(rdev), "Failed to create HW CQ"); 2407 goto fail; 2408 } 2409 2410 cq->ib_cq.cqe = entries; 2411 cq->cq_period = cq->qplib_cq.period; 2412 nq->budget++; 2413 2414 atomic_inc(&rdev->cq_count); 2415 2416 if (context) { 2417 struct bnxt_re_cq_resp resp; 2418 2419 resp.cqid = cq->qplib_cq.id; 2420 resp.tail = cq->qplib_cq.hwq.cons; 2421 resp.phase = cq->qplib_cq.period; 2422 resp.rsvd = 0; 2423 rc = ib_copy_to_udata(udata, &resp, sizeof(resp)); 2424 if (rc) { 2425 dev_err(rdev_to_dev(rdev), "Failed to copy CQ udata"); 2426 bnxt_qplib_destroy_cq(&rdev->qplib_res, &cq->qplib_cq); 2427 goto c2fail; 2428 } 2429 } 2430 2431 return &cq->ib_cq; 2432 2433 c2fail: 2434 if (context) 2435 ib_umem_release(cq->umem); 2436 fail: 2437 kfree(cq->cql); 2438 kfree(cq); 2439 return ERR_PTR(rc); 2440 } 2441 2442 static u8 __req_to_ib_wc_status(u8 qstatus) 2443 { 2444 switch (qstatus) { 2445 case CQ_REQ_STATUS_OK: 2446 return IB_WC_SUCCESS; 2447 case CQ_REQ_STATUS_BAD_RESPONSE_ERR: 2448 return IB_WC_BAD_RESP_ERR; 2449 case CQ_REQ_STATUS_LOCAL_LENGTH_ERR: 2450 return IB_WC_LOC_LEN_ERR; 2451 case CQ_REQ_STATUS_LOCAL_QP_OPERATION_ERR: 2452 return IB_WC_LOC_QP_OP_ERR; 2453 case CQ_REQ_STATUS_LOCAL_PROTECTION_ERR: 2454 return IB_WC_LOC_PROT_ERR; 2455 case CQ_REQ_STATUS_MEMORY_MGT_OPERATION_ERR: 2456 return IB_WC_GENERAL_ERR; 2457 case CQ_REQ_STATUS_REMOTE_INVALID_REQUEST_ERR: 2458 return IB_WC_REM_INV_REQ_ERR; 2459 case CQ_REQ_STATUS_REMOTE_ACCESS_ERR: 2460 return IB_WC_REM_ACCESS_ERR; 2461 case CQ_REQ_STATUS_REMOTE_OPERATION_ERR: 2462 return IB_WC_REM_OP_ERR; 2463 case CQ_REQ_STATUS_RNR_NAK_RETRY_CNT_ERR: 2464 return IB_WC_RNR_RETRY_EXC_ERR; 2465 case CQ_REQ_STATUS_TRANSPORT_RETRY_CNT_ERR: 2466 return IB_WC_RETRY_EXC_ERR; 2467 case CQ_REQ_STATUS_WORK_REQUEST_FLUSHED_ERR: 2468 return IB_WC_WR_FLUSH_ERR; 2469 default: 2470 return IB_WC_GENERAL_ERR; 2471 } 2472 return 0; 2473 } 2474 2475 static u8 __rawqp1_to_ib_wc_status(u8 qstatus) 2476 { 2477 switch (qstatus) { 2478 case CQ_RES_RAWETH_QP1_STATUS_OK: 2479 return IB_WC_SUCCESS; 2480 case CQ_RES_RAWETH_QP1_STATUS_LOCAL_ACCESS_ERROR: 2481 return IB_WC_LOC_ACCESS_ERR; 2482 case CQ_RES_RAWETH_QP1_STATUS_HW_LOCAL_LENGTH_ERR: 2483 return IB_WC_LOC_LEN_ERR; 2484 case CQ_RES_RAWETH_QP1_STATUS_LOCAL_PROTECTION_ERR: 2485 return IB_WC_LOC_PROT_ERR; 2486 case CQ_RES_RAWETH_QP1_STATUS_LOCAL_QP_OPERATION_ERR: 2487 return IB_WC_LOC_QP_OP_ERR; 2488 case CQ_RES_RAWETH_QP1_STATUS_MEMORY_MGT_OPERATION_ERR: 2489 return IB_WC_GENERAL_ERR; 2490 case CQ_RES_RAWETH_QP1_STATUS_WORK_REQUEST_FLUSHED_ERR: 2491 return IB_WC_WR_FLUSH_ERR; 2492 case CQ_RES_RAWETH_QP1_STATUS_HW_FLUSH_ERR: 2493 return IB_WC_WR_FLUSH_ERR; 2494 default: 2495 return IB_WC_GENERAL_ERR; 2496 } 2497 } 2498 2499 static u8 __rc_to_ib_wc_status(u8 qstatus) 2500 { 2501 switch (qstatus) { 2502 case CQ_RES_RC_STATUS_OK: 2503 return IB_WC_SUCCESS; 2504 case CQ_RES_RC_STATUS_LOCAL_ACCESS_ERROR: 2505 return IB_WC_LOC_ACCESS_ERR; 2506 case CQ_RES_RC_STATUS_LOCAL_LENGTH_ERR: 2507 return IB_WC_LOC_LEN_ERR; 2508 case CQ_RES_RC_STATUS_LOCAL_PROTECTION_ERR: 2509 return IB_WC_LOC_PROT_ERR; 2510 case CQ_RES_RC_STATUS_LOCAL_QP_OPERATION_ERR: 2511 return IB_WC_LOC_QP_OP_ERR; 2512 case CQ_RES_RC_STATUS_MEMORY_MGT_OPERATION_ERR: 2513 return IB_WC_GENERAL_ERR; 2514 case CQ_RES_RC_STATUS_REMOTE_INVALID_REQUEST_ERR: 2515 return IB_WC_REM_INV_REQ_ERR; 2516 case CQ_RES_RC_STATUS_WORK_REQUEST_FLUSHED_ERR: 2517 return IB_WC_WR_FLUSH_ERR; 2518 case CQ_RES_RC_STATUS_HW_FLUSH_ERR: 2519 return IB_WC_WR_FLUSH_ERR; 2520 default: 2521 return IB_WC_GENERAL_ERR; 2522 } 2523 } 2524 2525 static void bnxt_re_process_req_wc(struct ib_wc *wc, struct bnxt_qplib_cqe *cqe) 2526 { 2527 switch (cqe->type) { 2528 case BNXT_QPLIB_SWQE_TYPE_SEND: 2529 wc->opcode = IB_WC_SEND; 2530 break; 2531 case BNXT_QPLIB_SWQE_TYPE_SEND_WITH_IMM: 2532 wc->opcode = IB_WC_SEND; 2533 wc->wc_flags |= IB_WC_WITH_IMM; 2534 break; 2535 case BNXT_QPLIB_SWQE_TYPE_SEND_WITH_INV: 2536 wc->opcode = IB_WC_SEND; 2537 wc->wc_flags |= IB_WC_WITH_INVALIDATE; 2538 break; 2539 case BNXT_QPLIB_SWQE_TYPE_RDMA_WRITE: 2540 wc->opcode = IB_WC_RDMA_WRITE; 2541 break; 2542 case BNXT_QPLIB_SWQE_TYPE_RDMA_WRITE_WITH_IMM: 2543 wc->opcode = IB_WC_RDMA_WRITE; 2544 wc->wc_flags |= IB_WC_WITH_IMM; 2545 break; 2546 case BNXT_QPLIB_SWQE_TYPE_RDMA_READ: 2547 wc->opcode = IB_WC_RDMA_READ; 2548 break; 2549 case BNXT_QPLIB_SWQE_TYPE_ATOMIC_CMP_AND_SWP: 2550 wc->opcode = IB_WC_COMP_SWAP; 2551 break; 2552 case BNXT_QPLIB_SWQE_TYPE_ATOMIC_FETCH_AND_ADD: 2553 wc->opcode = IB_WC_FETCH_ADD; 2554 break; 2555 case BNXT_QPLIB_SWQE_TYPE_LOCAL_INV: 2556 wc->opcode = IB_WC_LOCAL_INV; 2557 break; 2558 case BNXT_QPLIB_SWQE_TYPE_REG_MR: 2559 wc->opcode = IB_WC_REG_MR; 2560 break; 2561 default: 2562 wc->opcode = IB_WC_SEND; 2563 break; 2564 } 2565 2566 wc->status = __req_to_ib_wc_status(cqe->status); 2567 } 2568 2569 static int bnxt_re_check_packet_type(u16 raweth_qp1_flags, 2570 u16 raweth_qp1_flags2) 2571 { 2572 bool is_udp = false, is_ipv6 = false, is_ipv4 = false; 2573 2574 /* raweth_qp1_flags Bit 9-6 indicates itype */ 2575 if ((raweth_qp1_flags & CQ_RES_RAWETH_QP1_RAWETH_QP1_FLAGS_ITYPE_ROCE) 2576 != CQ_RES_RAWETH_QP1_RAWETH_QP1_FLAGS_ITYPE_ROCE) 2577 return -1; 2578 2579 if (raweth_qp1_flags2 & 2580 CQ_RES_RAWETH_QP1_RAWETH_QP1_FLAGS2_IP_CS_CALC && 2581 raweth_qp1_flags2 & 2582 CQ_RES_RAWETH_QP1_RAWETH_QP1_FLAGS2_L4_CS_CALC) { 2583 is_udp = true; 2584 /* raweth_qp1_flags2 Bit 8 indicates ip_type. 0-v4 1 - v6 */ 2585 (raweth_qp1_flags2 & 2586 CQ_RES_RAWETH_QP1_RAWETH_QP1_FLAGS2_IP_TYPE) ? 2587 (is_ipv6 = true) : (is_ipv4 = true); 2588 return ((is_ipv6) ? 2589 BNXT_RE_ROCEV2_IPV6_PACKET : 2590 BNXT_RE_ROCEV2_IPV4_PACKET); 2591 } else { 2592 return BNXT_RE_ROCE_V1_PACKET; 2593 } 2594 } 2595 2596 static int bnxt_re_to_ib_nw_type(int nw_type) 2597 { 2598 u8 nw_hdr_type = 0xFF; 2599 2600 switch (nw_type) { 2601 case BNXT_RE_ROCE_V1_PACKET: 2602 nw_hdr_type = RDMA_NETWORK_ROCE_V1; 2603 break; 2604 case BNXT_RE_ROCEV2_IPV4_PACKET: 2605 nw_hdr_type = RDMA_NETWORK_IPV4; 2606 break; 2607 case BNXT_RE_ROCEV2_IPV6_PACKET: 2608 nw_hdr_type = RDMA_NETWORK_IPV6; 2609 break; 2610 } 2611 return nw_hdr_type; 2612 } 2613 2614 static bool bnxt_re_is_loopback_packet(struct bnxt_re_dev *rdev, 2615 void *rq_hdr_buf) 2616 { 2617 u8 *tmp_buf = NULL; 2618 struct ethhdr *eth_hdr; 2619 u16 eth_type; 2620 bool rc = false; 2621 2622 tmp_buf = (u8 *)rq_hdr_buf; 2623 /* 2624 * If dest mac is not same as I/F mac, this could be a 2625 * loopback address or multicast address, check whether 2626 * it is a loopback packet 2627 */ 2628 if (!ether_addr_equal(tmp_buf, rdev->netdev->dev_addr)) { 2629 tmp_buf += 4; 2630 /* Check the ether type */ 2631 eth_hdr = (struct ethhdr *)tmp_buf; 2632 eth_type = ntohs(eth_hdr->h_proto); 2633 switch (eth_type) { 2634 case ETH_P_IBOE: 2635 rc = true; 2636 break; 2637 case ETH_P_IP: 2638 case ETH_P_IPV6: { 2639 u32 len; 2640 struct udphdr *udp_hdr; 2641 2642 len = (eth_type == ETH_P_IP ? sizeof(struct iphdr) : 2643 sizeof(struct ipv6hdr)); 2644 tmp_buf += sizeof(struct ethhdr) + len; 2645 udp_hdr = (struct udphdr *)tmp_buf; 2646 if (ntohs(udp_hdr->dest) == 2647 ROCE_V2_UDP_DPORT) 2648 rc = true; 2649 break; 2650 } 2651 default: 2652 break; 2653 } 2654 } 2655 2656 return rc; 2657 } 2658 2659 static int bnxt_re_process_raw_qp_pkt_rx(struct bnxt_re_qp *qp1_qp, 2660 struct bnxt_qplib_cqe *cqe) 2661 { 2662 struct bnxt_re_dev *rdev = qp1_qp->rdev; 2663 struct bnxt_re_sqp_entries *sqp_entry = NULL; 2664 struct bnxt_re_qp *qp = rdev->qp1_sqp; 2665 struct ib_send_wr *swr; 2666 struct ib_ud_wr udwr; 2667 struct ib_recv_wr rwr; 2668 int pkt_type = 0; 2669 u32 tbl_idx; 2670 void *rq_hdr_buf; 2671 dma_addr_t rq_hdr_buf_map; 2672 dma_addr_t shrq_hdr_buf_map; 2673 u32 offset = 0; 2674 u32 skip_bytes = 0; 2675 struct ib_sge s_sge[2]; 2676 struct ib_sge r_sge[2]; 2677 int rc; 2678 2679 memset(&udwr, 0, sizeof(udwr)); 2680 memset(&rwr, 0, sizeof(rwr)); 2681 memset(&s_sge, 0, sizeof(s_sge)); 2682 memset(&r_sge, 0, sizeof(r_sge)); 2683 2684 swr = &udwr.wr; 2685 tbl_idx = cqe->wr_id; 2686 2687 rq_hdr_buf = qp1_qp->qplib_qp.rq_hdr_buf + 2688 (tbl_idx * qp1_qp->qplib_qp.rq_hdr_buf_size); 2689 rq_hdr_buf_map = bnxt_qplib_get_qp_buf_from_index(&qp1_qp->qplib_qp, 2690 tbl_idx); 2691 2692 /* Shadow QP header buffer */ 2693 shrq_hdr_buf_map = bnxt_qplib_get_qp_buf_from_index(&qp->qplib_qp, 2694 tbl_idx); 2695 sqp_entry = &rdev->sqp_tbl[tbl_idx]; 2696 2697 /* Store this cqe */ 2698 memcpy(&sqp_entry->cqe, cqe, sizeof(struct bnxt_qplib_cqe)); 2699 sqp_entry->qp1_qp = qp1_qp; 2700 2701 /* Find packet type from the cqe */ 2702 2703 pkt_type = bnxt_re_check_packet_type(cqe->raweth_qp1_flags, 2704 cqe->raweth_qp1_flags2); 2705 if (pkt_type < 0) { 2706 dev_err(rdev_to_dev(rdev), "Invalid packet\n"); 2707 return -EINVAL; 2708 } 2709 2710 /* Adjust the offset for the user buffer and post in the rq */ 2711 2712 if (pkt_type == BNXT_RE_ROCEV2_IPV4_PACKET) 2713 offset = 20; 2714 2715 /* 2716 * QP1 loopback packet has 4 bytes of internal header before 2717 * ether header. Skip these four bytes. 2718 */ 2719 if (bnxt_re_is_loopback_packet(rdev, rq_hdr_buf)) 2720 skip_bytes = 4; 2721 2722 /* First send SGE . Skip the ether header*/ 2723 s_sge[0].addr = rq_hdr_buf_map + BNXT_QPLIB_MAX_QP1_RQ_ETH_HDR_SIZE 2724 + skip_bytes; 2725 s_sge[0].lkey = 0xFFFFFFFF; 2726 s_sge[0].length = offset ? BNXT_QPLIB_MAX_GRH_HDR_SIZE_IPV4 : 2727 BNXT_QPLIB_MAX_GRH_HDR_SIZE_IPV6; 2728 2729 /* Second Send SGE */ 2730 s_sge[1].addr = s_sge[0].addr + s_sge[0].length + 2731 BNXT_QPLIB_MAX_QP1_RQ_BDETH_HDR_SIZE; 2732 if (pkt_type != BNXT_RE_ROCE_V1_PACKET) 2733 s_sge[1].addr += 8; 2734 s_sge[1].lkey = 0xFFFFFFFF; 2735 s_sge[1].length = 256; 2736 2737 /* First recv SGE */ 2738 2739 r_sge[0].addr = shrq_hdr_buf_map; 2740 r_sge[0].lkey = 0xFFFFFFFF; 2741 r_sge[0].length = 40; 2742 2743 r_sge[1].addr = sqp_entry->sge.addr + offset; 2744 r_sge[1].lkey = sqp_entry->sge.lkey; 2745 r_sge[1].length = BNXT_QPLIB_MAX_GRH_HDR_SIZE_IPV6 + 256 - offset; 2746 2747 /* Create receive work request */ 2748 rwr.num_sge = 2; 2749 rwr.sg_list = r_sge; 2750 rwr.wr_id = tbl_idx; 2751 rwr.next = NULL; 2752 2753 rc = bnxt_re_post_recv_shadow_qp(rdev, qp, &rwr); 2754 if (rc) { 2755 dev_err(rdev_to_dev(rdev), 2756 "Failed to post Rx buffers to shadow QP"); 2757 return -ENOMEM; 2758 } 2759 2760 swr->num_sge = 2; 2761 swr->sg_list = s_sge; 2762 swr->wr_id = tbl_idx; 2763 swr->opcode = IB_WR_SEND; 2764 swr->next = NULL; 2765 2766 udwr.ah = &rdev->sqp_ah->ib_ah; 2767 udwr.remote_qpn = rdev->qp1_sqp->qplib_qp.id; 2768 udwr.remote_qkey = rdev->qp1_sqp->qplib_qp.qkey; 2769 2770 /* post data received in the send queue */ 2771 rc = bnxt_re_post_send_shadow_qp(rdev, qp, swr); 2772 2773 return 0; 2774 } 2775 2776 static void bnxt_re_process_res_rawqp1_wc(struct ib_wc *wc, 2777 struct bnxt_qplib_cqe *cqe) 2778 { 2779 wc->opcode = IB_WC_RECV; 2780 wc->status = __rawqp1_to_ib_wc_status(cqe->status); 2781 wc->wc_flags |= IB_WC_GRH; 2782 } 2783 2784 static void bnxt_re_process_res_rc_wc(struct ib_wc *wc, 2785 struct bnxt_qplib_cqe *cqe) 2786 { 2787 wc->opcode = IB_WC_RECV; 2788 wc->status = __rc_to_ib_wc_status(cqe->status); 2789 2790 if (cqe->flags & CQ_RES_RC_FLAGS_IMM) 2791 wc->wc_flags |= IB_WC_WITH_IMM; 2792 if (cqe->flags & CQ_RES_RC_FLAGS_INV) 2793 wc->wc_flags |= IB_WC_WITH_INVALIDATE; 2794 if ((cqe->flags & (CQ_RES_RC_FLAGS_RDMA | CQ_RES_RC_FLAGS_IMM)) == 2795 (CQ_RES_RC_FLAGS_RDMA | CQ_RES_RC_FLAGS_IMM)) 2796 wc->opcode = IB_WC_RECV_RDMA_WITH_IMM; 2797 } 2798 2799 static void bnxt_re_process_res_shadow_qp_wc(struct bnxt_re_qp *qp, 2800 struct ib_wc *wc, 2801 struct bnxt_qplib_cqe *cqe) 2802 { 2803 u32 tbl_idx; 2804 struct bnxt_re_dev *rdev = qp->rdev; 2805 struct bnxt_re_qp *qp1_qp = NULL; 2806 struct bnxt_qplib_cqe *orig_cqe = NULL; 2807 struct bnxt_re_sqp_entries *sqp_entry = NULL; 2808 int nw_type; 2809 2810 tbl_idx = cqe->wr_id; 2811 2812 sqp_entry = &rdev->sqp_tbl[tbl_idx]; 2813 qp1_qp = sqp_entry->qp1_qp; 2814 orig_cqe = &sqp_entry->cqe; 2815 2816 wc->wr_id = sqp_entry->wrid; 2817 wc->byte_len = orig_cqe->length; 2818 wc->qp = &qp1_qp->ib_qp; 2819 2820 wc->ex.imm_data = orig_cqe->immdata; 2821 wc->src_qp = orig_cqe->src_qp; 2822 memcpy(wc->smac, orig_cqe->smac, ETH_ALEN); 2823 wc->port_num = 1; 2824 wc->vendor_err = orig_cqe->status; 2825 2826 wc->opcode = IB_WC_RECV; 2827 wc->status = __rawqp1_to_ib_wc_status(orig_cqe->status); 2828 wc->wc_flags |= IB_WC_GRH; 2829 2830 nw_type = bnxt_re_check_packet_type(orig_cqe->raweth_qp1_flags, 2831 orig_cqe->raweth_qp1_flags2); 2832 if (nw_type >= 0) { 2833 wc->network_hdr_type = bnxt_re_to_ib_nw_type(nw_type); 2834 wc->wc_flags |= IB_WC_WITH_NETWORK_HDR_TYPE; 2835 } 2836 } 2837 2838 static void bnxt_re_process_res_ud_wc(struct ib_wc *wc, 2839 struct bnxt_qplib_cqe *cqe) 2840 { 2841 wc->opcode = IB_WC_RECV; 2842 wc->status = __rc_to_ib_wc_status(cqe->status); 2843 2844 if (cqe->flags & CQ_RES_RC_FLAGS_IMM) 2845 wc->wc_flags |= IB_WC_WITH_IMM; 2846 if (cqe->flags & CQ_RES_RC_FLAGS_INV) 2847 wc->wc_flags |= IB_WC_WITH_INVALIDATE; 2848 if ((cqe->flags & (CQ_RES_RC_FLAGS_RDMA | CQ_RES_RC_FLAGS_IMM)) == 2849 (CQ_RES_RC_FLAGS_RDMA | CQ_RES_RC_FLAGS_IMM)) 2850 wc->opcode = IB_WC_RECV_RDMA_WITH_IMM; 2851 } 2852 2853 static int send_phantom_wqe(struct bnxt_re_qp *qp) 2854 { 2855 struct bnxt_qplib_qp *lib_qp = &qp->qplib_qp; 2856 unsigned long flags; 2857 int rc = 0; 2858 2859 spin_lock_irqsave(&qp->sq_lock, flags); 2860 2861 rc = bnxt_re_bind_fence_mw(lib_qp); 2862 if (!rc) { 2863 lib_qp->sq.phantom_wqe_cnt++; 2864 dev_dbg(&lib_qp->sq.hwq.pdev->dev, 2865 "qp %#x sq->prod %#x sw_prod %#x phantom_wqe_cnt %d\n", 2866 lib_qp->id, lib_qp->sq.hwq.prod, 2867 HWQ_CMP(lib_qp->sq.hwq.prod, &lib_qp->sq.hwq), 2868 lib_qp->sq.phantom_wqe_cnt); 2869 } 2870 2871 spin_unlock_irqrestore(&qp->sq_lock, flags); 2872 return rc; 2873 } 2874 2875 int bnxt_re_poll_cq(struct ib_cq *ib_cq, int num_entries, struct ib_wc *wc) 2876 { 2877 struct bnxt_re_cq *cq = container_of(ib_cq, struct bnxt_re_cq, ib_cq); 2878 struct bnxt_re_qp *qp; 2879 struct bnxt_qplib_cqe *cqe; 2880 int i, ncqe, budget; 2881 struct bnxt_qplib_q *sq; 2882 struct bnxt_qplib_qp *lib_qp; 2883 u32 tbl_idx; 2884 struct bnxt_re_sqp_entries *sqp_entry = NULL; 2885 unsigned long flags; 2886 2887 spin_lock_irqsave(&cq->cq_lock, flags); 2888 budget = min_t(u32, num_entries, cq->max_cql); 2889 num_entries = budget; 2890 if (!cq->cql) { 2891 dev_err(rdev_to_dev(cq->rdev), "POLL CQ : no CQL to use"); 2892 goto exit; 2893 } 2894 cqe = &cq->cql[0]; 2895 while (budget) { 2896 lib_qp = NULL; 2897 ncqe = bnxt_qplib_poll_cq(&cq->qplib_cq, cqe, budget, &lib_qp); 2898 if (lib_qp) { 2899 sq = &lib_qp->sq; 2900 if (sq->send_phantom) { 2901 qp = container_of(lib_qp, 2902 struct bnxt_re_qp, qplib_qp); 2903 if (send_phantom_wqe(qp) == -ENOMEM) 2904 dev_err(rdev_to_dev(cq->rdev), 2905 "Phantom failed! Scheduled to send again\n"); 2906 else 2907 sq->send_phantom = false; 2908 } 2909 } 2910 if (ncqe < budget) 2911 ncqe += bnxt_qplib_process_flush_list(&cq->qplib_cq, 2912 cqe + ncqe, 2913 budget - ncqe); 2914 2915 if (!ncqe) 2916 break; 2917 2918 for (i = 0; i < ncqe; i++, cqe++) { 2919 /* Transcribe each qplib_wqe back to ib_wc */ 2920 memset(wc, 0, sizeof(*wc)); 2921 2922 wc->wr_id = cqe->wr_id; 2923 wc->byte_len = cqe->length; 2924 qp = container_of 2925 ((struct bnxt_qplib_qp *) 2926 (unsigned long)(cqe->qp_handle), 2927 struct bnxt_re_qp, qplib_qp); 2928 if (!qp) { 2929 dev_err(rdev_to_dev(cq->rdev), 2930 "POLL CQ : bad QP handle"); 2931 continue; 2932 } 2933 wc->qp = &qp->ib_qp; 2934 wc->ex.imm_data = cqe->immdata; 2935 wc->src_qp = cqe->src_qp; 2936 memcpy(wc->smac, cqe->smac, ETH_ALEN); 2937 wc->port_num = 1; 2938 wc->vendor_err = cqe->status; 2939 2940 switch (cqe->opcode) { 2941 case CQ_BASE_CQE_TYPE_REQ: 2942 if (qp->qplib_qp.id == 2943 qp->rdev->qp1_sqp->qplib_qp.id) { 2944 /* Handle this completion with 2945 * the stored completion 2946 */ 2947 memset(wc, 0, sizeof(*wc)); 2948 continue; 2949 } 2950 bnxt_re_process_req_wc(wc, cqe); 2951 break; 2952 case CQ_BASE_CQE_TYPE_RES_RAWETH_QP1: 2953 if (!cqe->status) { 2954 int rc = 0; 2955 2956 rc = bnxt_re_process_raw_qp_pkt_rx 2957 (qp, cqe); 2958 if (!rc) { 2959 memset(wc, 0, sizeof(*wc)); 2960 continue; 2961 } 2962 cqe->status = -1; 2963 } 2964 /* Errors need not be looped back. 2965 * But change the wr_id to the one 2966 * stored in the table 2967 */ 2968 tbl_idx = cqe->wr_id; 2969 sqp_entry = &cq->rdev->sqp_tbl[tbl_idx]; 2970 wc->wr_id = sqp_entry->wrid; 2971 bnxt_re_process_res_rawqp1_wc(wc, cqe); 2972 break; 2973 case CQ_BASE_CQE_TYPE_RES_RC: 2974 bnxt_re_process_res_rc_wc(wc, cqe); 2975 break; 2976 case CQ_BASE_CQE_TYPE_RES_UD: 2977 if (qp->qplib_qp.id == 2978 qp->rdev->qp1_sqp->qplib_qp.id) { 2979 /* Handle this completion with 2980 * the stored completion 2981 */ 2982 if (cqe->status) { 2983 continue; 2984 } else { 2985 bnxt_re_process_res_shadow_qp_wc 2986 (qp, wc, cqe); 2987 break; 2988 } 2989 } 2990 bnxt_re_process_res_ud_wc(wc, cqe); 2991 break; 2992 default: 2993 dev_err(rdev_to_dev(cq->rdev), 2994 "POLL CQ : type 0x%x not handled", 2995 cqe->opcode); 2996 continue; 2997 } 2998 wc++; 2999 budget--; 3000 } 3001 } 3002 exit: 3003 spin_unlock_irqrestore(&cq->cq_lock, flags); 3004 return num_entries - budget; 3005 } 3006 3007 int bnxt_re_req_notify_cq(struct ib_cq *ib_cq, 3008 enum ib_cq_notify_flags ib_cqn_flags) 3009 { 3010 struct bnxt_re_cq *cq = container_of(ib_cq, struct bnxt_re_cq, ib_cq); 3011 int type = 0; 3012 3013 /* Trigger on the very next completion */ 3014 if (ib_cqn_flags & IB_CQ_NEXT_COMP) 3015 type = DBR_DBR_TYPE_CQ_ARMALL; 3016 /* Trigger on the next solicited completion */ 3017 else if (ib_cqn_flags & IB_CQ_SOLICITED) 3018 type = DBR_DBR_TYPE_CQ_ARMSE; 3019 3020 /* Poll to see if there are missed events */ 3021 if ((ib_cqn_flags & IB_CQ_REPORT_MISSED_EVENTS) && 3022 !(bnxt_qplib_is_cq_empty(&cq->qplib_cq))) 3023 return 1; 3024 3025 bnxt_qplib_req_notify_cq(&cq->qplib_cq, type); 3026 3027 return 0; 3028 } 3029 3030 /* Memory Regions */ 3031 struct ib_mr *bnxt_re_get_dma_mr(struct ib_pd *ib_pd, int mr_access_flags) 3032 { 3033 struct bnxt_re_pd *pd = container_of(ib_pd, struct bnxt_re_pd, ib_pd); 3034 struct bnxt_re_dev *rdev = pd->rdev; 3035 struct bnxt_re_mr *mr; 3036 u64 pbl = 0; 3037 int rc; 3038 3039 mr = kzalloc(sizeof(*mr), GFP_KERNEL); 3040 if (!mr) 3041 return ERR_PTR(-ENOMEM); 3042 3043 mr->rdev = rdev; 3044 mr->qplib_mr.pd = &pd->qplib_pd; 3045 mr->qplib_mr.flags = __from_ib_access_flags(mr_access_flags); 3046 mr->qplib_mr.type = CMDQ_ALLOCATE_MRW_MRW_FLAGS_PMR; 3047 3048 /* Allocate and register 0 as the address */ 3049 rc = bnxt_qplib_alloc_mrw(&rdev->qplib_res, &mr->qplib_mr); 3050 if (rc) 3051 goto fail; 3052 3053 mr->qplib_mr.hwq.level = PBL_LVL_MAX; 3054 mr->qplib_mr.total_size = -1; /* Infinte length */ 3055 rc = bnxt_qplib_reg_mr(&rdev->qplib_res, &mr->qplib_mr, &pbl, 0, false); 3056 if (rc) 3057 goto fail_mr; 3058 3059 mr->ib_mr.lkey = mr->qplib_mr.lkey; 3060 if (mr_access_flags & (IB_ACCESS_REMOTE_WRITE | IB_ACCESS_REMOTE_READ | 3061 IB_ACCESS_REMOTE_ATOMIC)) 3062 mr->ib_mr.rkey = mr->ib_mr.lkey; 3063 atomic_inc(&rdev->mr_count); 3064 3065 return &mr->ib_mr; 3066 3067 fail_mr: 3068 bnxt_qplib_free_mrw(&rdev->qplib_res, &mr->qplib_mr); 3069 fail: 3070 kfree(mr); 3071 return ERR_PTR(rc); 3072 } 3073 3074 int bnxt_re_dereg_mr(struct ib_mr *ib_mr) 3075 { 3076 struct bnxt_re_mr *mr = container_of(ib_mr, struct bnxt_re_mr, ib_mr); 3077 struct bnxt_re_dev *rdev = mr->rdev; 3078 int rc; 3079 3080 rc = bnxt_qplib_free_mrw(&rdev->qplib_res, &mr->qplib_mr); 3081 if (rc) { 3082 dev_err(rdev_to_dev(rdev), "Dereg MR failed: %#x\n", rc); 3083 return rc; 3084 } 3085 3086 if (mr->pages) { 3087 rc = bnxt_qplib_free_fast_reg_page_list(&rdev->qplib_res, 3088 &mr->qplib_frpl); 3089 kfree(mr->pages); 3090 mr->npages = 0; 3091 mr->pages = NULL; 3092 } 3093 if (!IS_ERR_OR_NULL(mr->ib_umem)) 3094 ib_umem_release(mr->ib_umem); 3095 3096 kfree(mr); 3097 atomic_dec(&rdev->mr_count); 3098 return rc; 3099 } 3100 3101 static int bnxt_re_set_page(struct ib_mr *ib_mr, u64 addr) 3102 { 3103 struct bnxt_re_mr *mr = container_of(ib_mr, struct bnxt_re_mr, ib_mr); 3104 3105 if (unlikely(mr->npages == mr->qplib_frpl.max_pg_ptrs)) 3106 return -ENOMEM; 3107 3108 mr->pages[mr->npages++] = addr; 3109 return 0; 3110 } 3111 3112 int bnxt_re_map_mr_sg(struct ib_mr *ib_mr, struct scatterlist *sg, int sg_nents, 3113 unsigned int *sg_offset) 3114 { 3115 struct bnxt_re_mr *mr = container_of(ib_mr, struct bnxt_re_mr, ib_mr); 3116 3117 mr->npages = 0; 3118 return ib_sg_to_pages(ib_mr, sg, sg_nents, sg_offset, bnxt_re_set_page); 3119 } 3120 3121 struct ib_mr *bnxt_re_alloc_mr(struct ib_pd *ib_pd, enum ib_mr_type type, 3122 u32 max_num_sg) 3123 { 3124 struct bnxt_re_pd *pd = container_of(ib_pd, struct bnxt_re_pd, ib_pd); 3125 struct bnxt_re_dev *rdev = pd->rdev; 3126 struct bnxt_re_mr *mr = NULL; 3127 int rc; 3128 3129 if (type != IB_MR_TYPE_MEM_REG) { 3130 dev_dbg(rdev_to_dev(rdev), "MR type 0x%x not supported", type); 3131 return ERR_PTR(-EINVAL); 3132 } 3133 if (max_num_sg > MAX_PBL_LVL_1_PGS) 3134 return ERR_PTR(-EINVAL); 3135 3136 mr = kzalloc(sizeof(*mr), GFP_KERNEL); 3137 if (!mr) 3138 return ERR_PTR(-ENOMEM); 3139 3140 mr->rdev = rdev; 3141 mr->qplib_mr.pd = &pd->qplib_pd; 3142 mr->qplib_mr.flags = BNXT_QPLIB_FR_PMR; 3143 mr->qplib_mr.type = CMDQ_ALLOCATE_MRW_MRW_FLAGS_PMR; 3144 3145 rc = bnxt_qplib_alloc_mrw(&rdev->qplib_res, &mr->qplib_mr); 3146 if (rc) 3147 goto fail; 3148 3149 mr->ib_mr.lkey = mr->qplib_mr.lkey; 3150 mr->ib_mr.rkey = mr->ib_mr.lkey; 3151 3152 mr->pages = kcalloc(max_num_sg, sizeof(u64), GFP_KERNEL); 3153 if (!mr->pages) { 3154 rc = -ENOMEM; 3155 goto fail; 3156 } 3157 rc = bnxt_qplib_alloc_fast_reg_page_list(&rdev->qplib_res, 3158 &mr->qplib_frpl, max_num_sg); 3159 if (rc) { 3160 dev_err(rdev_to_dev(rdev), 3161 "Failed to allocate HW FR page list"); 3162 goto fail_mr; 3163 } 3164 3165 atomic_inc(&rdev->mr_count); 3166 return &mr->ib_mr; 3167 3168 fail_mr: 3169 bnxt_qplib_free_mrw(&rdev->qplib_res, &mr->qplib_mr); 3170 fail: 3171 kfree(mr->pages); 3172 kfree(mr); 3173 return ERR_PTR(rc); 3174 } 3175 3176 struct ib_mw *bnxt_re_alloc_mw(struct ib_pd *ib_pd, enum ib_mw_type type, 3177 struct ib_udata *udata) 3178 { 3179 struct bnxt_re_pd *pd = container_of(ib_pd, struct bnxt_re_pd, ib_pd); 3180 struct bnxt_re_dev *rdev = pd->rdev; 3181 struct bnxt_re_mw *mw; 3182 int rc; 3183 3184 mw = kzalloc(sizeof(*mw), GFP_KERNEL); 3185 if (!mw) 3186 return ERR_PTR(-ENOMEM); 3187 mw->rdev = rdev; 3188 mw->qplib_mw.pd = &pd->qplib_pd; 3189 3190 mw->qplib_mw.type = (type == IB_MW_TYPE_1 ? 3191 CMDQ_ALLOCATE_MRW_MRW_FLAGS_MW_TYPE1 : 3192 CMDQ_ALLOCATE_MRW_MRW_FLAGS_MW_TYPE2B); 3193 rc = bnxt_qplib_alloc_mrw(&rdev->qplib_res, &mw->qplib_mw); 3194 if (rc) { 3195 dev_err(rdev_to_dev(rdev), "Allocate MW failed!"); 3196 goto fail; 3197 } 3198 mw->ib_mw.rkey = mw->qplib_mw.rkey; 3199 3200 atomic_inc(&rdev->mw_count); 3201 return &mw->ib_mw; 3202 3203 fail: 3204 kfree(mw); 3205 return ERR_PTR(rc); 3206 } 3207 3208 int bnxt_re_dealloc_mw(struct ib_mw *ib_mw) 3209 { 3210 struct bnxt_re_mw *mw = container_of(ib_mw, struct bnxt_re_mw, ib_mw); 3211 struct bnxt_re_dev *rdev = mw->rdev; 3212 int rc; 3213 3214 rc = bnxt_qplib_free_mrw(&rdev->qplib_res, &mw->qplib_mw); 3215 if (rc) { 3216 dev_err(rdev_to_dev(rdev), "Free MW failed: %#x\n", rc); 3217 return rc; 3218 } 3219 3220 kfree(mw); 3221 atomic_dec(&rdev->mw_count); 3222 return rc; 3223 } 3224 3225 /* uverbs */ 3226 struct ib_mr *bnxt_re_reg_user_mr(struct ib_pd *ib_pd, u64 start, u64 length, 3227 u64 virt_addr, int mr_access_flags, 3228 struct ib_udata *udata) 3229 { 3230 struct bnxt_re_pd *pd = container_of(ib_pd, struct bnxt_re_pd, ib_pd); 3231 struct bnxt_re_dev *rdev = pd->rdev; 3232 struct bnxt_re_mr *mr; 3233 struct ib_umem *umem; 3234 u64 *pbl_tbl, *pbl_tbl_orig; 3235 int i, umem_pgs, pages, rc; 3236 struct scatterlist *sg; 3237 int entry; 3238 3239 if (length > BNXT_RE_MAX_MR_SIZE) { 3240 dev_err(rdev_to_dev(rdev), "MR Size: %lld > Max supported:%ld\n", 3241 length, BNXT_RE_MAX_MR_SIZE); 3242 return ERR_PTR(-ENOMEM); 3243 } 3244 3245 mr = kzalloc(sizeof(*mr), GFP_KERNEL); 3246 if (!mr) 3247 return ERR_PTR(-ENOMEM); 3248 3249 mr->rdev = rdev; 3250 mr->qplib_mr.pd = &pd->qplib_pd; 3251 mr->qplib_mr.flags = __from_ib_access_flags(mr_access_flags); 3252 mr->qplib_mr.type = CMDQ_ALLOCATE_MRW_MRW_FLAGS_MR; 3253 3254 umem = ib_umem_get(ib_pd->uobject->context, start, length, 3255 mr_access_flags, 0); 3256 if (IS_ERR(umem)) { 3257 dev_err(rdev_to_dev(rdev), "Failed to get umem"); 3258 rc = -EFAULT; 3259 goto free_mr; 3260 } 3261 mr->ib_umem = umem; 3262 3263 rc = bnxt_qplib_alloc_mrw(&rdev->qplib_res, &mr->qplib_mr); 3264 if (rc) { 3265 dev_err(rdev_to_dev(rdev), "Failed to allocate MR"); 3266 goto release_umem; 3267 } 3268 /* The fixed portion of the rkey is the same as the lkey */ 3269 mr->ib_mr.rkey = mr->qplib_mr.rkey; 3270 3271 mr->qplib_mr.va = virt_addr; 3272 umem_pgs = ib_umem_page_count(umem); 3273 if (!umem_pgs) { 3274 dev_err(rdev_to_dev(rdev), "umem is invalid!"); 3275 rc = -EINVAL; 3276 goto free_mrw; 3277 } 3278 mr->qplib_mr.total_size = length; 3279 3280 pbl_tbl = kcalloc(umem_pgs, sizeof(u64 *), GFP_KERNEL); 3281 if (!pbl_tbl) { 3282 rc = -EINVAL; 3283 goto free_mrw; 3284 } 3285 pbl_tbl_orig = pbl_tbl; 3286 3287 if (umem->hugetlb) { 3288 dev_err(rdev_to_dev(rdev), "umem hugetlb not supported!"); 3289 rc = -EFAULT; 3290 goto fail; 3291 } 3292 3293 if (umem->page_shift != PAGE_SHIFT) { 3294 dev_err(rdev_to_dev(rdev), "umem page shift unsupported!"); 3295 rc = -EFAULT; 3296 goto fail; 3297 } 3298 /* Map umem buf ptrs to the PBL */ 3299 for_each_sg(umem->sg_head.sgl, sg, umem->nmap, entry) { 3300 pages = sg_dma_len(sg) >> umem->page_shift; 3301 for (i = 0; i < pages; i++, pbl_tbl++) 3302 *pbl_tbl = sg_dma_address(sg) + (i << umem->page_shift); 3303 } 3304 rc = bnxt_qplib_reg_mr(&rdev->qplib_res, &mr->qplib_mr, pbl_tbl_orig, 3305 umem_pgs, false); 3306 if (rc) { 3307 dev_err(rdev_to_dev(rdev), "Failed to register user MR"); 3308 goto fail; 3309 } 3310 3311 kfree(pbl_tbl_orig); 3312 3313 mr->ib_mr.lkey = mr->qplib_mr.lkey; 3314 mr->ib_mr.rkey = mr->qplib_mr.lkey; 3315 atomic_inc(&rdev->mr_count); 3316 3317 return &mr->ib_mr; 3318 fail: 3319 kfree(pbl_tbl_orig); 3320 free_mrw: 3321 bnxt_qplib_free_mrw(&rdev->qplib_res, &mr->qplib_mr); 3322 release_umem: 3323 ib_umem_release(umem); 3324 free_mr: 3325 kfree(mr); 3326 return ERR_PTR(rc); 3327 } 3328 3329 struct ib_ucontext *bnxt_re_alloc_ucontext(struct ib_device *ibdev, 3330 struct ib_udata *udata) 3331 { 3332 struct bnxt_re_dev *rdev = to_bnxt_re_dev(ibdev, ibdev); 3333 struct bnxt_re_uctx_resp resp; 3334 struct bnxt_re_ucontext *uctx; 3335 struct bnxt_qplib_dev_attr *dev_attr = &rdev->dev_attr; 3336 int rc; 3337 3338 dev_dbg(rdev_to_dev(rdev), "ABI version requested %d", 3339 ibdev->uverbs_abi_ver); 3340 3341 if (ibdev->uverbs_abi_ver != BNXT_RE_ABI_VERSION) { 3342 dev_dbg(rdev_to_dev(rdev), " is different from the device %d ", 3343 BNXT_RE_ABI_VERSION); 3344 return ERR_PTR(-EPERM); 3345 } 3346 3347 uctx = kzalloc(sizeof(*uctx), GFP_KERNEL); 3348 if (!uctx) 3349 return ERR_PTR(-ENOMEM); 3350 3351 uctx->rdev = rdev; 3352 3353 uctx->shpg = (void *)__get_free_page(GFP_KERNEL); 3354 if (!uctx->shpg) { 3355 rc = -ENOMEM; 3356 goto fail; 3357 } 3358 spin_lock_init(&uctx->sh_lock); 3359 3360 resp.dev_id = rdev->en_dev->pdev->devfn; /*Temp, Use idr_alloc instead*/ 3361 resp.max_qp = rdev->qplib_ctx.qpc_count; 3362 resp.pg_size = PAGE_SIZE; 3363 resp.cqe_sz = sizeof(struct cq_base); 3364 resp.max_cqd = dev_attr->max_cq_wqes; 3365 resp.rsvd = 0; 3366 3367 rc = ib_copy_to_udata(udata, &resp, sizeof(resp)); 3368 if (rc) { 3369 dev_err(rdev_to_dev(rdev), "Failed to copy user context"); 3370 rc = -EFAULT; 3371 goto cfail; 3372 } 3373 3374 return &uctx->ib_uctx; 3375 cfail: 3376 free_page((unsigned long)uctx->shpg); 3377 uctx->shpg = NULL; 3378 fail: 3379 kfree(uctx); 3380 return ERR_PTR(rc); 3381 } 3382 3383 int bnxt_re_dealloc_ucontext(struct ib_ucontext *ib_uctx) 3384 { 3385 struct bnxt_re_ucontext *uctx = container_of(ib_uctx, 3386 struct bnxt_re_ucontext, 3387 ib_uctx); 3388 3389 struct bnxt_re_dev *rdev = uctx->rdev; 3390 int rc = 0; 3391 3392 if (uctx->shpg) 3393 free_page((unsigned long)uctx->shpg); 3394 3395 if (uctx->dpi.dbr) { 3396 /* Free DPI only if this is the first PD allocated by the 3397 * application and mark the context dpi as NULL 3398 */ 3399 rc = bnxt_qplib_dealloc_dpi(&rdev->qplib_res, 3400 &rdev->qplib_res.dpi_tbl, 3401 &uctx->dpi); 3402 if (rc) 3403 dev_err(rdev_to_dev(rdev), "Deallocate HW DPI failed!"); 3404 /* Don't fail, continue*/ 3405 uctx->dpi.dbr = NULL; 3406 } 3407 3408 kfree(uctx); 3409 return 0; 3410 } 3411 3412 /* Helper function to mmap the virtual memory from user app */ 3413 int bnxt_re_mmap(struct ib_ucontext *ib_uctx, struct vm_area_struct *vma) 3414 { 3415 struct bnxt_re_ucontext *uctx = container_of(ib_uctx, 3416 struct bnxt_re_ucontext, 3417 ib_uctx); 3418 struct bnxt_re_dev *rdev = uctx->rdev; 3419 u64 pfn; 3420 3421 if (vma->vm_end - vma->vm_start != PAGE_SIZE) 3422 return -EINVAL; 3423 3424 if (vma->vm_pgoff) { 3425 vma->vm_page_prot = pgprot_noncached(vma->vm_page_prot); 3426 if (io_remap_pfn_range(vma, vma->vm_start, vma->vm_pgoff, 3427 PAGE_SIZE, vma->vm_page_prot)) { 3428 dev_err(rdev_to_dev(rdev), "Failed to map DPI"); 3429 return -EAGAIN; 3430 } 3431 } else { 3432 pfn = virt_to_phys(uctx->shpg) >> PAGE_SHIFT; 3433 if (remap_pfn_range(vma, vma->vm_start, 3434 pfn, PAGE_SIZE, vma->vm_page_prot)) { 3435 dev_err(rdev_to_dev(rdev), 3436 "Failed to map shared page"); 3437 return -EAGAIN; 3438 } 3439 } 3440 3441 return 0; 3442 } 3443