1 /* 2 * Broadcom NetXtreme-E RoCE driver. 3 * 4 * Copyright (c) 2016 - 2017, Broadcom. All rights reserved. The term 5 * Broadcom refers to Broadcom Limited and/or its subsidiaries. 6 * 7 * This software is available to you under a choice of one of two 8 * licenses. You may choose to be licensed under the terms of the GNU 9 * General Public License (GPL) Version 2, available from the file 10 * COPYING in the main directory of this source tree, or the 11 * BSD license below: 12 * 13 * Redistribution and use in source and binary forms, with or without 14 * modification, are permitted provided that the following conditions 15 * are met: 16 * 17 * 1. Redistributions of source code must retain the above copyright 18 * notice, this list of conditions and the following disclaimer. 19 * 2. Redistributions in binary form must reproduce the above copyright 20 * notice, this list of conditions and the following disclaimer in 21 * the documentation and/or other materials provided with the 22 * distribution. 23 * 24 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' 25 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, 26 * THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR 27 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS 28 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 29 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 30 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR 31 * BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, 32 * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE 33 * OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN 34 * IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 35 * 36 * Description: IB Verbs interpreter 37 */ 38 39 #include <linux/interrupt.h> 40 #include <linux/types.h> 41 #include <linux/pci.h> 42 #include <linux/netdevice.h> 43 #include <linux/if_ether.h> 44 45 #include <rdma/ib_verbs.h> 46 #include <rdma/ib_user_verbs.h> 47 #include <rdma/ib_umem.h> 48 #include <rdma/ib_addr.h> 49 #include <rdma/ib_mad.h> 50 #include <rdma/ib_cache.h> 51 52 #include "bnxt_ulp.h" 53 54 #include "roce_hsi.h" 55 #include "qplib_res.h" 56 #include "qplib_sp.h" 57 #include "qplib_fp.h" 58 #include "qplib_rcfw.h" 59 60 #include "bnxt_re.h" 61 #include "ib_verbs.h" 62 #include <rdma/bnxt_re-abi.h> 63 64 static int __from_ib_access_flags(int iflags) 65 { 66 int qflags = 0; 67 68 if (iflags & IB_ACCESS_LOCAL_WRITE) 69 qflags |= BNXT_QPLIB_ACCESS_LOCAL_WRITE; 70 if (iflags & IB_ACCESS_REMOTE_READ) 71 qflags |= BNXT_QPLIB_ACCESS_REMOTE_READ; 72 if (iflags & IB_ACCESS_REMOTE_WRITE) 73 qflags |= BNXT_QPLIB_ACCESS_REMOTE_WRITE; 74 if (iflags & IB_ACCESS_REMOTE_ATOMIC) 75 qflags |= BNXT_QPLIB_ACCESS_REMOTE_ATOMIC; 76 if (iflags & IB_ACCESS_MW_BIND) 77 qflags |= BNXT_QPLIB_ACCESS_MW_BIND; 78 if (iflags & IB_ZERO_BASED) 79 qflags |= BNXT_QPLIB_ACCESS_ZERO_BASED; 80 if (iflags & IB_ACCESS_ON_DEMAND) 81 qflags |= BNXT_QPLIB_ACCESS_ON_DEMAND; 82 return qflags; 83 }; 84 85 static enum ib_access_flags __to_ib_access_flags(int qflags) 86 { 87 enum ib_access_flags iflags = 0; 88 89 if (qflags & BNXT_QPLIB_ACCESS_LOCAL_WRITE) 90 iflags |= IB_ACCESS_LOCAL_WRITE; 91 if (qflags & BNXT_QPLIB_ACCESS_REMOTE_WRITE) 92 iflags |= IB_ACCESS_REMOTE_WRITE; 93 if (qflags & BNXT_QPLIB_ACCESS_REMOTE_READ) 94 iflags |= IB_ACCESS_REMOTE_READ; 95 if (qflags & BNXT_QPLIB_ACCESS_REMOTE_ATOMIC) 96 iflags |= IB_ACCESS_REMOTE_ATOMIC; 97 if (qflags & BNXT_QPLIB_ACCESS_MW_BIND) 98 iflags |= IB_ACCESS_MW_BIND; 99 if (qflags & BNXT_QPLIB_ACCESS_ZERO_BASED) 100 iflags |= IB_ZERO_BASED; 101 if (qflags & BNXT_QPLIB_ACCESS_ON_DEMAND) 102 iflags |= IB_ACCESS_ON_DEMAND; 103 return iflags; 104 }; 105 106 static int bnxt_re_build_sgl(struct ib_sge *ib_sg_list, 107 struct bnxt_qplib_sge *sg_list, int num) 108 { 109 int i, total = 0; 110 111 for (i = 0; i < num; i++) { 112 sg_list[i].addr = ib_sg_list[i].addr; 113 sg_list[i].lkey = ib_sg_list[i].lkey; 114 sg_list[i].size = ib_sg_list[i].length; 115 total += sg_list[i].size; 116 } 117 return total; 118 } 119 120 /* Device */ 121 struct net_device *bnxt_re_get_netdev(struct ib_device *ibdev, u8 port_num) 122 { 123 struct bnxt_re_dev *rdev = to_bnxt_re_dev(ibdev, ibdev); 124 struct net_device *netdev = NULL; 125 126 rcu_read_lock(); 127 if (rdev) 128 netdev = rdev->netdev; 129 if (netdev) 130 dev_hold(netdev); 131 132 rcu_read_unlock(); 133 return netdev; 134 } 135 136 int bnxt_re_query_device(struct ib_device *ibdev, 137 struct ib_device_attr *ib_attr, 138 struct ib_udata *udata) 139 { 140 struct bnxt_re_dev *rdev = to_bnxt_re_dev(ibdev, ibdev); 141 struct bnxt_qplib_dev_attr *dev_attr = &rdev->dev_attr; 142 143 memset(ib_attr, 0, sizeof(*ib_attr)); 144 145 ib_attr->fw_ver = (u64)(unsigned long)(dev_attr->fw_ver); 146 bnxt_qplib_get_guid(rdev->netdev->dev_addr, 147 (u8 *)&ib_attr->sys_image_guid); 148 ib_attr->max_mr_size = BNXT_RE_MAX_MR_SIZE; 149 ib_attr->page_size_cap = BNXT_RE_PAGE_SIZE_4K; 150 151 ib_attr->vendor_id = rdev->en_dev->pdev->vendor; 152 ib_attr->vendor_part_id = rdev->en_dev->pdev->device; 153 ib_attr->hw_ver = rdev->en_dev->pdev->subsystem_device; 154 ib_attr->max_qp = dev_attr->max_qp; 155 ib_attr->max_qp_wr = dev_attr->max_qp_wqes; 156 ib_attr->device_cap_flags = 157 IB_DEVICE_CURR_QP_STATE_MOD 158 | IB_DEVICE_RC_RNR_NAK_GEN 159 | IB_DEVICE_SHUTDOWN_PORT 160 | IB_DEVICE_SYS_IMAGE_GUID 161 | IB_DEVICE_LOCAL_DMA_LKEY 162 | IB_DEVICE_RESIZE_MAX_WR 163 | IB_DEVICE_PORT_ACTIVE_EVENT 164 | IB_DEVICE_N_NOTIFY_CQ 165 | IB_DEVICE_MEM_WINDOW 166 | IB_DEVICE_MEM_WINDOW_TYPE_2B 167 | IB_DEVICE_MEM_MGT_EXTENSIONS; 168 ib_attr->max_sge = dev_attr->max_qp_sges; 169 ib_attr->max_sge_rd = dev_attr->max_qp_sges; 170 ib_attr->max_cq = dev_attr->max_cq; 171 ib_attr->max_cqe = dev_attr->max_cq_wqes; 172 ib_attr->max_mr = dev_attr->max_mr; 173 ib_attr->max_pd = dev_attr->max_pd; 174 ib_attr->max_qp_rd_atom = dev_attr->max_qp_rd_atom; 175 ib_attr->max_qp_init_rd_atom = dev_attr->max_qp_init_rd_atom; 176 if (dev_attr->is_atomic) { 177 ib_attr->atomic_cap = IB_ATOMIC_HCA; 178 ib_attr->masked_atomic_cap = IB_ATOMIC_HCA; 179 } 180 181 ib_attr->max_ee_rd_atom = 0; 182 ib_attr->max_res_rd_atom = 0; 183 ib_attr->max_ee_init_rd_atom = 0; 184 ib_attr->max_ee = 0; 185 ib_attr->max_rdd = 0; 186 ib_attr->max_mw = dev_attr->max_mw; 187 ib_attr->max_raw_ipv6_qp = 0; 188 ib_attr->max_raw_ethy_qp = dev_attr->max_raw_ethy_qp; 189 ib_attr->max_mcast_grp = 0; 190 ib_attr->max_mcast_qp_attach = 0; 191 ib_attr->max_total_mcast_qp_attach = 0; 192 ib_attr->max_ah = dev_attr->max_ah; 193 194 ib_attr->max_fmr = 0; 195 ib_attr->max_map_per_fmr = 0; 196 197 ib_attr->max_srq = dev_attr->max_srq; 198 ib_attr->max_srq_wr = dev_attr->max_srq_wqes; 199 ib_attr->max_srq_sge = dev_attr->max_srq_sges; 200 201 ib_attr->max_fast_reg_page_list_len = MAX_PBL_LVL_1_PGS; 202 203 ib_attr->max_pkeys = 1; 204 ib_attr->local_ca_ack_delay = BNXT_RE_DEFAULT_ACK_DELAY; 205 return 0; 206 } 207 208 int bnxt_re_modify_device(struct ib_device *ibdev, 209 int device_modify_mask, 210 struct ib_device_modify *device_modify) 211 { 212 switch (device_modify_mask) { 213 case IB_DEVICE_MODIFY_SYS_IMAGE_GUID: 214 /* Modify the GUID requires the modification of the GID table */ 215 /* GUID should be made as READ-ONLY */ 216 break; 217 case IB_DEVICE_MODIFY_NODE_DESC: 218 /* Node Desc should be made as READ-ONLY */ 219 break; 220 default: 221 break; 222 } 223 return 0; 224 } 225 226 /* Port */ 227 int bnxt_re_query_port(struct ib_device *ibdev, u8 port_num, 228 struct ib_port_attr *port_attr) 229 { 230 struct bnxt_re_dev *rdev = to_bnxt_re_dev(ibdev, ibdev); 231 struct bnxt_qplib_dev_attr *dev_attr = &rdev->dev_attr; 232 233 memset(port_attr, 0, sizeof(*port_attr)); 234 235 if (netif_running(rdev->netdev) && netif_carrier_ok(rdev->netdev)) { 236 port_attr->state = IB_PORT_ACTIVE; 237 port_attr->phys_state = 5; 238 } else { 239 port_attr->state = IB_PORT_DOWN; 240 port_attr->phys_state = 3; 241 } 242 port_attr->max_mtu = IB_MTU_4096; 243 port_attr->active_mtu = iboe_get_mtu(rdev->netdev->mtu); 244 port_attr->gid_tbl_len = dev_attr->max_sgid; 245 port_attr->port_cap_flags = IB_PORT_CM_SUP | IB_PORT_REINIT_SUP | 246 IB_PORT_DEVICE_MGMT_SUP | 247 IB_PORT_VENDOR_CLASS_SUP | 248 IB_PORT_IP_BASED_GIDS; 249 250 /* Max MSG size set to 2G for now */ 251 port_attr->max_msg_sz = 0x80000000; 252 port_attr->bad_pkey_cntr = 0; 253 port_attr->qkey_viol_cntr = 0; 254 port_attr->pkey_tbl_len = dev_attr->max_pkey; 255 port_attr->lid = 0; 256 port_attr->sm_lid = 0; 257 port_attr->lmc = 0; 258 port_attr->max_vl_num = 4; 259 port_attr->sm_sl = 0; 260 port_attr->subnet_timeout = 0; 261 port_attr->init_type_reply = 0; 262 /* call the underlying netdev's ethtool hooks to query speed settings 263 * for which we acquire rtnl_lock _only_ if it's registered with 264 * IB stack to avoid race in the NETDEV_UNREG path 265 */ 266 if (test_bit(BNXT_RE_FLAG_IBDEV_REGISTERED, &rdev->flags)) 267 if (ib_get_eth_speed(ibdev, port_num, &port_attr->active_speed, 268 &port_attr->active_width)) 269 return -EINVAL; 270 return 0; 271 } 272 273 int bnxt_re_get_port_immutable(struct ib_device *ibdev, u8 port_num, 274 struct ib_port_immutable *immutable) 275 { 276 struct ib_port_attr port_attr; 277 278 if (bnxt_re_query_port(ibdev, port_num, &port_attr)) 279 return -EINVAL; 280 281 immutable->pkey_tbl_len = port_attr.pkey_tbl_len; 282 immutable->gid_tbl_len = port_attr.gid_tbl_len; 283 immutable->core_cap_flags = RDMA_CORE_PORT_IBA_ROCE; 284 immutable->core_cap_flags |= RDMA_CORE_CAP_PROT_ROCE_UDP_ENCAP; 285 immutable->max_mad_size = IB_MGMT_MAD_SIZE; 286 return 0; 287 } 288 289 int bnxt_re_query_pkey(struct ib_device *ibdev, u8 port_num, 290 u16 index, u16 *pkey) 291 { 292 struct bnxt_re_dev *rdev = to_bnxt_re_dev(ibdev, ibdev); 293 294 /* Ignore port_num */ 295 296 memset(pkey, 0, sizeof(*pkey)); 297 return bnxt_qplib_get_pkey(&rdev->qplib_res, 298 &rdev->qplib_res.pkey_tbl, index, pkey); 299 } 300 301 int bnxt_re_query_gid(struct ib_device *ibdev, u8 port_num, 302 int index, union ib_gid *gid) 303 { 304 struct bnxt_re_dev *rdev = to_bnxt_re_dev(ibdev, ibdev); 305 int rc = 0; 306 307 /* Ignore port_num */ 308 memset(gid, 0, sizeof(*gid)); 309 rc = bnxt_qplib_get_sgid(&rdev->qplib_res, 310 &rdev->qplib_res.sgid_tbl, index, 311 (struct bnxt_qplib_gid *)gid); 312 return rc; 313 } 314 315 int bnxt_re_del_gid(struct ib_device *ibdev, u8 port_num, 316 unsigned int index, void **context) 317 { 318 int rc = 0; 319 struct bnxt_re_gid_ctx *ctx, **ctx_tbl; 320 struct bnxt_re_dev *rdev = to_bnxt_re_dev(ibdev, ibdev); 321 struct bnxt_qplib_sgid_tbl *sgid_tbl = &rdev->qplib_res.sgid_tbl; 322 323 /* Delete the entry from the hardware */ 324 ctx = *context; 325 if (!ctx) 326 return -EINVAL; 327 328 if (sgid_tbl && sgid_tbl->active) { 329 if (ctx->idx >= sgid_tbl->max) 330 return -EINVAL; 331 ctx->refcnt--; 332 if (!ctx->refcnt) { 333 rc = bnxt_qplib_del_sgid(sgid_tbl, 334 &sgid_tbl->tbl[ctx->idx], 335 true); 336 if (rc) { 337 dev_err(rdev_to_dev(rdev), 338 "Failed to remove GID: %#x", rc); 339 } else { 340 ctx_tbl = sgid_tbl->ctx; 341 ctx_tbl[ctx->idx] = NULL; 342 kfree(ctx); 343 } 344 } 345 } else { 346 return -EINVAL; 347 } 348 return rc; 349 } 350 351 int bnxt_re_add_gid(struct ib_device *ibdev, u8 port_num, 352 unsigned int index, const union ib_gid *gid, 353 const struct ib_gid_attr *attr, void **context) 354 { 355 int rc; 356 u32 tbl_idx = 0; 357 u16 vlan_id = 0xFFFF; 358 struct bnxt_re_gid_ctx *ctx, **ctx_tbl; 359 struct bnxt_re_dev *rdev = to_bnxt_re_dev(ibdev, ibdev); 360 struct bnxt_qplib_sgid_tbl *sgid_tbl = &rdev->qplib_res.sgid_tbl; 361 362 if ((attr->ndev) && is_vlan_dev(attr->ndev)) 363 vlan_id = vlan_dev_vlan_id(attr->ndev); 364 365 rc = bnxt_qplib_add_sgid(sgid_tbl, (struct bnxt_qplib_gid *)gid, 366 rdev->qplib_res.netdev->dev_addr, 367 vlan_id, true, &tbl_idx); 368 if (rc == -EALREADY) { 369 ctx_tbl = sgid_tbl->ctx; 370 ctx_tbl[tbl_idx]->refcnt++; 371 *context = ctx_tbl[tbl_idx]; 372 return 0; 373 } 374 375 if (rc < 0) { 376 dev_err(rdev_to_dev(rdev), "Failed to add GID: %#x", rc); 377 return rc; 378 } 379 380 ctx = kmalloc(sizeof(*ctx), GFP_KERNEL); 381 if (!ctx) 382 return -ENOMEM; 383 ctx_tbl = sgid_tbl->ctx; 384 ctx->idx = tbl_idx; 385 ctx->refcnt = 1; 386 ctx_tbl[tbl_idx] = ctx; 387 388 return rc; 389 } 390 391 enum rdma_link_layer bnxt_re_get_link_layer(struct ib_device *ibdev, 392 u8 port_num) 393 { 394 return IB_LINK_LAYER_ETHERNET; 395 } 396 397 #define BNXT_RE_FENCE_PBL_SIZE DIV_ROUND_UP(BNXT_RE_FENCE_BYTES, PAGE_SIZE) 398 399 static void bnxt_re_create_fence_wqe(struct bnxt_re_pd *pd) 400 { 401 struct bnxt_re_fence_data *fence = &pd->fence; 402 struct ib_mr *ib_mr = &fence->mr->ib_mr; 403 struct bnxt_qplib_swqe *wqe = &fence->bind_wqe; 404 405 memset(wqe, 0, sizeof(*wqe)); 406 wqe->type = BNXT_QPLIB_SWQE_TYPE_BIND_MW; 407 wqe->wr_id = BNXT_QPLIB_FENCE_WRID; 408 wqe->flags |= BNXT_QPLIB_SWQE_FLAGS_SIGNAL_COMP; 409 wqe->flags |= BNXT_QPLIB_SWQE_FLAGS_UC_FENCE; 410 wqe->bind.zero_based = false; 411 wqe->bind.parent_l_key = ib_mr->lkey; 412 wqe->bind.va = (u64)(unsigned long)fence->va; 413 wqe->bind.length = fence->size; 414 wqe->bind.access_cntl = __from_ib_access_flags(IB_ACCESS_REMOTE_READ); 415 wqe->bind.mw_type = SQ_BIND_MW_TYPE_TYPE1; 416 417 /* Save the initial rkey in fence structure for now; 418 * wqe->bind.r_key will be set at (re)bind time. 419 */ 420 fence->bind_rkey = ib_inc_rkey(fence->mw->rkey); 421 } 422 423 static int bnxt_re_bind_fence_mw(struct bnxt_qplib_qp *qplib_qp) 424 { 425 struct bnxt_re_qp *qp = container_of(qplib_qp, struct bnxt_re_qp, 426 qplib_qp); 427 struct ib_pd *ib_pd = qp->ib_qp.pd; 428 struct bnxt_re_pd *pd = container_of(ib_pd, struct bnxt_re_pd, ib_pd); 429 struct bnxt_re_fence_data *fence = &pd->fence; 430 struct bnxt_qplib_swqe *fence_wqe = &fence->bind_wqe; 431 struct bnxt_qplib_swqe wqe; 432 int rc; 433 434 memcpy(&wqe, fence_wqe, sizeof(wqe)); 435 wqe.bind.r_key = fence->bind_rkey; 436 fence->bind_rkey = ib_inc_rkey(fence->bind_rkey); 437 438 dev_dbg(rdev_to_dev(qp->rdev), 439 "Posting bind fence-WQE: rkey: %#x QP: %d PD: %p\n", 440 wqe.bind.r_key, qp->qplib_qp.id, pd); 441 rc = bnxt_qplib_post_send(&qp->qplib_qp, &wqe); 442 if (rc) { 443 dev_err(rdev_to_dev(qp->rdev), "Failed to bind fence-WQE\n"); 444 return rc; 445 } 446 bnxt_qplib_post_send_db(&qp->qplib_qp); 447 448 return rc; 449 } 450 451 static void bnxt_re_destroy_fence_mr(struct bnxt_re_pd *pd) 452 { 453 struct bnxt_re_fence_data *fence = &pd->fence; 454 struct bnxt_re_dev *rdev = pd->rdev; 455 struct device *dev = &rdev->en_dev->pdev->dev; 456 struct bnxt_re_mr *mr = fence->mr; 457 458 if (fence->mw) { 459 bnxt_re_dealloc_mw(fence->mw); 460 fence->mw = NULL; 461 } 462 if (mr) { 463 if (mr->ib_mr.rkey) 464 bnxt_qplib_dereg_mrw(&rdev->qplib_res, &mr->qplib_mr, 465 true); 466 if (mr->ib_mr.lkey) 467 bnxt_qplib_free_mrw(&rdev->qplib_res, &mr->qplib_mr); 468 kfree(mr); 469 fence->mr = NULL; 470 } 471 if (fence->dma_addr) { 472 dma_unmap_single(dev, fence->dma_addr, BNXT_RE_FENCE_BYTES, 473 DMA_BIDIRECTIONAL); 474 fence->dma_addr = 0; 475 } 476 } 477 478 static int bnxt_re_create_fence_mr(struct bnxt_re_pd *pd) 479 { 480 int mr_access_flags = IB_ACCESS_LOCAL_WRITE | IB_ACCESS_MW_BIND; 481 struct bnxt_re_fence_data *fence = &pd->fence; 482 struct bnxt_re_dev *rdev = pd->rdev; 483 struct device *dev = &rdev->en_dev->pdev->dev; 484 struct bnxt_re_mr *mr = NULL; 485 dma_addr_t dma_addr = 0; 486 struct ib_mw *mw; 487 u64 pbl_tbl; 488 int rc; 489 490 dma_addr = dma_map_single(dev, fence->va, BNXT_RE_FENCE_BYTES, 491 DMA_BIDIRECTIONAL); 492 rc = dma_mapping_error(dev, dma_addr); 493 if (rc) { 494 dev_err(rdev_to_dev(rdev), "Failed to dma-map fence-MR-mem\n"); 495 rc = -EIO; 496 fence->dma_addr = 0; 497 goto fail; 498 } 499 fence->dma_addr = dma_addr; 500 501 /* Allocate a MR */ 502 mr = kzalloc(sizeof(*mr), GFP_KERNEL); 503 if (!mr) { 504 rc = -ENOMEM; 505 goto fail; 506 } 507 fence->mr = mr; 508 mr->rdev = rdev; 509 mr->qplib_mr.pd = &pd->qplib_pd; 510 mr->qplib_mr.type = CMDQ_ALLOCATE_MRW_MRW_FLAGS_PMR; 511 mr->qplib_mr.flags = __from_ib_access_flags(mr_access_flags); 512 rc = bnxt_qplib_alloc_mrw(&rdev->qplib_res, &mr->qplib_mr); 513 if (rc) { 514 dev_err(rdev_to_dev(rdev), "Failed to alloc fence-HW-MR\n"); 515 goto fail; 516 } 517 518 /* Register MR */ 519 mr->ib_mr.lkey = mr->qplib_mr.lkey; 520 mr->qplib_mr.va = (u64)(unsigned long)fence->va; 521 mr->qplib_mr.total_size = BNXT_RE_FENCE_BYTES; 522 pbl_tbl = dma_addr; 523 rc = bnxt_qplib_reg_mr(&rdev->qplib_res, &mr->qplib_mr, &pbl_tbl, 524 BNXT_RE_FENCE_PBL_SIZE, false); 525 if (rc) { 526 dev_err(rdev_to_dev(rdev), "Failed to register fence-MR\n"); 527 goto fail; 528 } 529 mr->ib_mr.rkey = mr->qplib_mr.rkey; 530 531 /* Create a fence MW only for kernel consumers */ 532 mw = bnxt_re_alloc_mw(&pd->ib_pd, IB_MW_TYPE_1, NULL); 533 if (IS_ERR(mw)) { 534 dev_err(rdev_to_dev(rdev), 535 "Failed to create fence-MW for PD: %p\n", pd); 536 rc = PTR_ERR(mw); 537 goto fail; 538 } 539 fence->mw = mw; 540 541 bnxt_re_create_fence_wqe(pd); 542 return 0; 543 544 fail: 545 bnxt_re_destroy_fence_mr(pd); 546 return rc; 547 } 548 549 /* Protection Domains */ 550 int bnxt_re_dealloc_pd(struct ib_pd *ib_pd) 551 { 552 struct bnxt_re_pd *pd = container_of(ib_pd, struct bnxt_re_pd, ib_pd); 553 struct bnxt_re_dev *rdev = pd->rdev; 554 int rc; 555 556 bnxt_re_destroy_fence_mr(pd); 557 558 if (pd->qplib_pd.id) { 559 rc = bnxt_qplib_dealloc_pd(&rdev->qplib_res, 560 &rdev->qplib_res.pd_tbl, 561 &pd->qplib_pd); 562 if (rc) 563 dev_err(rdev_to_dev(rdev), "Failed to deallocate HW PD"); 564 } 565 566 kfree(pd); 567 return 0; 568 } 569 570 struct ib_pd *bnxt_re_alloc_pd(struct ib_device *ibdev, 571 struct ib_ucontext *ucontext, 572 struct ib_udata *udata) 573 { 574 struct bnxt_re_dev *rdev = to_bnxt_re_dev(ibdev, ibdev); 575 struct bnxt_re_ucontext *ucntx = container_of(ucontext, 576 struct bnxt_re_ucontext, 577 ib_uctx); 578 struct bnxt_re_pd *pd; 579 int rc; 580 581 pd = kzalloc(sizeof(*pd), GFP_KERNEL); 582 if (!pd) 583 return ERR_PTR(-ENOMEM); 584 585 pd->rdev = rdev; 586 if (bnxt_qplib_alloc_pd(&rdev->qplib_res.pd_tbl, &pd->qplib_pd)) { 587 dev_err(rdev_to_dev(rdev), "Failed to allocate HW PD"); 588 rc = -ENOMEM; 589 goto fail; 590 } 591 592 if (udata) { 593 struct bnxt_re_pd_resp resp; 594 595 if (!ucntx->dpi.dbr) { 596 /* Allocate DPI in alloc_pd to avoid failing of 597 * ibv_devinfo and family of application when DPIs 598 * are depleted. 599 */ 600 if (bnxt_qplib_alloc_dpi(&rdev->qplib_res.dpi_tbl, 601 &ucntx->dpi, ucntx)) { 602 rc = -ENOMEM; 603 goto dbfail; 604 } 605 } 606 607 resp.pdid = pd->qplib_pd.id; 608 /* Still allow mapping this DBR to the new user PD. */ 609 resp.dpi = ucntx->dpi.dpi; 610 resp.dbr = (u64)ucntx->dpi.umdbr; 611 612 rc = ib_copy_to_udata(udata, &resp, sizeof(resp)); 613 if (rc) { 614 dev_err(rdev_to_dev(rdev), 615 "Failed to copy user response\n"); 616 goto dbfail; 617 } 618 } 619 620 if (!udata) 621 if (bnxt_re_create_fence_mr(pd)) 622 dev_warn(rdev_to_dev(rdev), 623 "Failed to create Fence-MR\n"); 624 return &pd->ib_pd; 625 dbfail: 626 (void)bnxt_qplib_dealloc_pd(&rdev->qplib_res, &rdev->qplib_res.pd_tbl, 627 &pd->qplib_pd); 628 fail: 629 kfree(pd); 630 return ERR_PTR(rc); 631 } 632 633 /* Address Handles */ 634 int bnxt_re_destroy_ah(struct ib_ah *ib_ah) 635 { 636 struct bnxt_re_ah *ah = container_of(ib_ah, struct bnxt_re_ah, ib_ah); 637 struct bnxt_re_dev *rdev = ah->rdev; 638 int rc; 639 640 rc = bnxt_qplib_destroy_ah(&rdev->qplib_res, &ah->qplib_ah); 641 if (rc) { 642 dev_err(rdev_to_dev(rdev), "Failed to destroy HW AH"); 643 return rc; 644 } 645 kfree(ah); 646 return 0; 647 } 648 649 struct ib_ah *bnxt_re_create_ah(struct ib_pd *ib_pd, 650 struct rdma_ah_attr *ah_attr, 651 struct ib_udata *udata) 652 { 653 struct bnxt_re_pd *pd = container_of(ib_pd, struct bnxt_re_pd, ib_pd); 654 struct bnxt_re_dev *rdev = pd->rdev; 655 struct bnxt_re_ah *ah; 656 const struct ib_global_route *grh = rdma_ah_read_grh(ah_attr); 657 int rc; 658 u16 vlan_tag; 659 u8 nw_type; 660 661 struct ib_gid_attr sgid_attr; 662 663 if (!(rdma_ah_get_ah_flags(ah_attr) & IB_AH_GRH)) { 664 dev_err(rdev_to_dev(rdev), "Failed to alloc AH: GRH not set"); 665 return ERR_PTR(-EINVAL); 666 } 667 ah = kzalloc(sizeof(*ah), GFP_ATOMIC); 668 if (!ah) 669 return ERR_PTR(-ENOMEM); 670 671 ah->rdev = rdev; 672 ah->qplib_ah.pd = &pd->qplib_pd; 673 674 /* Supply the configuration for the HW */ 675 memcpy(ah->qplib_ah.dgid.data, grh->dgid.raw, 676 sizeof(union ib_gid)); 677 /* 678 * If RoCE V2 is enabled, stack will have two entries for 679 * each GID entry. Avoiding this duplicte entry in HW. Dividing 680 * the GID index by 2 for RoCE V2 681 */ 682 ah->qplib_ah.sgid_index = grh->sgid_index / 2; 683 ah->qplib_ah.host_sgid_index = grh->sgid_index; 684 ah->qplib_ah.traffic_class = grh->traffic_class; 685 ah->qplib_ah.flow_label = grh->flow_label; 686 ah->qplib_ah.hop_limit = grh->hop_limit; 687 ah->qplib_ah.sl = rdma_ah_get_sl(ah_attr); 688 if (ib_pd->uobject && 689 !rdma_is_multicast_addr((struct in6_addr *) 690 grh->dgid.raw) && 691 !rdma_link_local_addr((struct in6_addr *) 692 grh->dgid.raw)) { 693 union ib_gid sgid; 694 695 rc = ib_get_cached_gid(&rdev->ibdev, 1, 696 grh->sgid_index, &sgid, 697 &sgid_attr); 698 if (rc) { 699 dev_err(rdev_to_dev(rdev), 700 "Failed to query gid at index %d", 701 grh->sgid_index); 702 goto fail; 703 } 704 if (sgid_attr.ndev) { 705 if (is_vlan_dev(sgid_attr.ndev)) 706 vlan_tag = vlan_dev_vlan_id(sgid_attr.ndev); 707 dev_put(sgid_attr.ndev); 708 } 709 /* Get network header type for this GID */ 710 nw_type = ib_gid_to_network_type(sgid_attr.gid_type, &sgid); 711 switch (nw_type) { 712 case RDMA_NETWORK_IPV4: 713 ah->qplib_ah.nw_type = CMDQ_CREATE_AH_TYPE_V2IPV4; 714 break; 715 case RDMA_NETWORK_IPV6: 716 ah->qplib_ah.nw_type = CMDQ_CREATE_AH_TYPE_V2IPV6; 717 break; 718 default: 719 ah->qplib_ah.nw_type = CMDQ_CREATE_AH_TYPE_V1; 720 break; 721 } 722 rc = rdma_addr_find_l2_eth_by_grh(&sgid, &grh->dgid, 723 ah_attr->roce.dmac, &vlan_tag, 724 &sgid_attr.ndev->ifindex, 725 NULL); 726 if (rc) { 727 dev_err(rdev_to_dev(rdev), "Failed to get dmac\n"); 728 goto fail; 729 } 730 } 731 732 memcpy(ah->qplib_ah.dmac, ah_attr->roce.dmac, ETH_ALEN); 733 rc = bnxt_qplib_create_ah(&rdev->qplib_res, &ah->qplib_ah); 734 if (rc) { 735 dev_err(rdev_to_dev(rdev), "Failed to allocate HW AH"); 736 goto fail; 737 } 738 739 /* Write AVID to shared page. */ 740 if (ib_pd->uobject) { 741 struct ib_ucontext *ib_uctx = ib_pd->uobject->context; 742 struct bnxt_re_ucontext *uctx; 743 unsigned long flag; 744 u32 *wrptr; 745 746 uctx = container_of(ib_uctx, struct bnxt_re_ucontext, ib_uctx); 747 spin_lock_irqsave(&uctx->sh_lock, flag); 748 wrptr = (u32 *)(uctx->shpg + BNXT_RE_AVID_OFFT); 749 *wrptr = ah->qplib_ah.id; 750 wmb(); /* make sure cache is updated. */ 751 spin_unlock_irqrestore(&uctx->sh_lock, flag); 752 } 753 754 return &ah->ib_ah; 755 756 fail: 757 kfree(ah); 758 return ERR_PTR(rc); 759 } 760 761 int bnxt_re_modify_ah(struct ib_ah *ib_ah, struct rdma_ah_attr *ah_attr) 762 { 763 return 0; 764 } 765 766 int bnxt_re_query_ah(struct ib_ah *ib_ah, struct rdma_ah_attr *ah_attr) 767 { 768 struct bnxt_re_ah *ah = container_of(ib_ah, struct bnxt_re_ah, ib_ah); 769 770 ah_attr->type = ib_ah->type; 771 rdma_ah_set_sl(ah_attr, ah->qplib_ah.sl); 772 memcpy(ah_attr->roce.dmac, ah->qplib_ah.dmac, ETH_ALEN); 773 rdma_ah_set_grh(ah_attr, NULL, 0, 774 ah->qplib_ah.host_sgid_index, 775 0, ah->qplib_ah.traffic_class); 776 rdma_ah_set_dgid_raw(ah_attr, ah->qplib_ah.dgid.data); 777 rdma_ah_set_port_num(ah_attr, 1); 778 rdma_ah_set_static_rate(ah_attr, 0); 779 return 0; 780 } 781 782 /* Queue Pairs */ 783 int bnxt_re_destroy_qp(struct ib_qp *ib_qp) 784 { 785 struct bnxt_re_qp *qp = container_of(ib_qp, struct bnxt_re_qp, ib_qp); 786 struct bnxt_re_dev *rdev = qp->rdev; 787 int rc; 788 789 bnxt_qplib_del_flush_qp(&qp->qplib_qp); 790 rc = bnxt_qplib_destroy_qp(&rdev->qplib_res, &qp->qplib_qp); 791 if (rc) { 792 dev_err(rdev_to_dev(rdev), "Failed to destroy HW QP"); 793 return rc; 794 } 795 if (ib_qp->qp_type == IB_QPT_GSI && rdev->qp1_sqp) { 796 rc = bnxt_qplib_destroy_ah(&rdev->qplib_res, 797 &rdev->sqp_ah->qplib_ah); 798 if (rc) { 799 dev_err(rdev_to_dev(rdev), 800 "Failed to destroy HW AH for shadow QP"); 801 return rc; 802 } 803 804 bnxt_qplib_del_flush_qp(&qp->qplib_qp); 805 rc = bnxt_qplib_destroy_qp(&rdev->qplib_res, 806 &rdev->qp1_sqp->qplib_qp); 807 if (rc) { 808 dev_err(rdev_to_dev(rdev), 809 "Failed to destroy Shadow QP"); 810 return rc; 811 } 812 mutex_lock(&rdev->qp_lock); 813 list_del(&rdev->qp1_sqp->list); 814 atomic_dec(&rdev->qp_count); 815 mutex_unlock(&rdev->qp_lock); 816 817 kfree(rdev->sqp_ah); 818 kfree(rdev->qp1_sqp); 819 } 820 821 if (!IS_ERR_OR_NULL(qp->rumem)) 822 ib_umem_release(qp->rumem); 823 if (!IS_ERR_OR_NULL(qp->sumem)) 824 ib_umem_release(qp->sumem); 825 826 mutex_lock(&rdev->qp_lock); 827 list_del(&qp->list); 828 atomic_dec(&rdev->qp_count); 829 mutex_unlock(&rdev->qp_lock); 830 kfree(qp); 831 return 0; 832 } 833 834 static u8 __from_ib_qp_type(enum ib_qp_type type) 835 { 836 switch (type) { 837 case IB_QPT_GSI: 838 return CMDQ_CREATE_QP1_TYPE_GSI; 839 case IB_QPT_RC: 840 return CMDQ_CREATE_QP_TYPE_RC; 841 case IB_QPT_UD: 842 return CMDQ_CREATE_QP_TYPE_UD; 843 default: 844 return IB_QPT_MAX; 845 } 846 } 847 848 static int bnxt_re_init_user_qp(struct bnxt_re_dev *rdev, struct bnxt_re_pd *pd, 849 struct bnxt_re_qp *qp, struct ib_udata *udata) 850 { 851 struct bnxt_re_qp_req ureq; 852 struct bnxt_qplib_qp *qplib_qp = &qp->qplib_qp; 853 struct ib_umem *umem; 854 int bytes = 0; 855 struct ib_ucontext *context = pd->ib_pd.uobject->context; 856 struct bnxt_re_ucontext *cntx = container_of(context, 857 struct bnxt_re_ucontext, 858 ib_uctx); 859 if (ib_copy_from_udata(&ureq, udata, sizeof(ureq))) 860 return -EFAULT; 861 862 bytes = (qplib_qp->sq.max_wqe * BNXT_QPLIB_MAX_SQE_ENTRY_SIZE); 863 /* Consider mapping PSN search memory only for RC QPs. */ 864 if (qplib_qp->type == CMDQ_CREATE_QP_TYPE_RC) 865 bytes += (qplib_qp->sq.max_wqe * sizeof(struct sq_psn_search)); 866 bytes = PAGE_ALIGN(bytes); 867 umem = ib_umem_get(context, ureq.qpsva, bytes, 868 IB_ACCESS_LOCAL_WRITE, 1); 869 if (IS_ERR(umem)) 870 return PTR_ERR(umem); 871 872 qp->sumem = umem; 873 qplib_qp->sq.sglist = umem->sg_head.sgl; 874 qplib_qp->sq.nmap = umem->nmap; 875 qplib_qp->qp_handle = ureq.qp_handle; 876 877 if (!qp->qplib_qp.srq) { 878 bytes = (qplib_qp->rq.max_wqe * BNXT_QPLIB_MAX_RQE_ENTRY_SIZE); 879 bytes = PAGE_ALIGN(bytes); 880 umem = ib_umem_get(context, ureq.qprva, bytes, 881 IB_ACCESS_LOCAL_WRITE, 1); 882 if (IS_ERR(umem)) 883 goto rqfail; 884 qp->rumem = umem; 885 qplib_qp->rq.sglist = umem->sg_head.sgl; 886 qplib_qp->rq.nmap = umem->nmap; 887 } 888 889 qplib_qp->dpi = &cntx->dpi; 890 return 0; 891 rqfail: 892 ib_umem_release(qp->sumem); 893 qp->sumem = NULL; 894 qplib_qp->sq.sglist = NULL; 895 qplib_qp->sq.nmap = 0; 896 897 return PTR_ERR(umem); 898 } 899 900 static struct bnxt_re_ah *bnxt_re_create_shadow_qp_ah 901 (struct bnxt_re_pd *pd, 902 struct bnxt_qplib_res *qp1_res, 903 struct bnxt_qplib_qp *qp1_qp) 904 { 905 struct bnxt_re_dev *rdev = pd->rdev; 906 struct bnxt_re_ah *ah; 907 union ib_gid sgid; 908 int rc; 909 910 ah = kzalloc(sizeof(*ah), GFP_KERNEL); 911 if (!ah) 912 return NULL; 913 914 ah->rdev = rdev; 915 ah->qplib_ah.pd = &pd->qplib_pd; 916 917 rc = bnxt_re_query_gid(&rdev->ibdev, 1, 0, &sgid); 918 if (rc) 919 goto fail; 920 921 /* supply the dgid data same as sgid */ 922 memcpy(ah->qplib_ah.dgid.data, &sgid.raw, 923 sizeof(union ib_gid)); 924 ah->qplib_ah.sgid_index = 0; 925 926 ah->qplib_ah.traffic_class = 0; 927 ah->qplib_ah.flow_label = 0; 928 ah->qplib_ah.hop_limit = 1; 929 ah->qplib_ah.sl = 0; 930 /* Have DMAC same as SMAC */ 931 ether_addr_copy(ah->qplib_ah.dmac, rdev->netdev->dev_addr); 932 933 rc = bnxt_qplib_create_ah(&rdev->qplib_res, &ah->qplib_ah); 934 if (rc) { 935 dev_err(rdev_to_dev(rdev), 936 "Failed to allocate HW AH for Shadow QP"); 937 goto fail; 938 } 939 940 return ah; 941 942 fail: 943 kfree(ah); 944 return NULL; 945 } 946 947 static struct bnxt_re_qp *bnxt_re_create_shadow_qp 948 (struct bnxt_re_pd *pd, 949 struct bnxt_qplib_res *qp1_res, 950 struct bnxt_qplib_qp *qp1_qp) 951 { 952 struct bnxt_re_dev *rdev = pd->rdev; 953 struct bnxt_re_qp *qp; 954 int rc; 955 956 qp = kzalloc(sizeof(*qp), GFP_KERNEL); 957 if (!qp) 958 return NULL; 959 960 qp->rdev = rdev; 961 962 /* Initialize the shadow QP structure from the QP1 values */ 963 ether_addr_copy(qp->qplib_qp.smac, rdev->netdev->dev_addr); 964 965 qp->qplib_qp.pd = &pd->qplib_pd; 966 qp->qplib_qp.qp_handle = (u64)(unsigned long)(&qp->qplib_qp); 967 qp->qplib_qp.type = IB_QPT_UD; 968 969 qp->qplib_qp.max_inline_data = 0; 970 qp->qplib_qp.sig_type = true; 971 972 /* Shadow QP SQ depth should be same as QP1 RQ depth */ 973 qp->qplib_qp.sq.max_wqe = qp1_qp->rq.max_wqe; 974 qp->qplib_qp.sq.max_sge = 2; 975 /* Q full delta can be 1 since it is internal QP */ 976 qp->qplib_qp.sq.q_full_delta = 1; 977 978 qp->qplib_qp.scq = qp1_qp->scq; 979 qp->qplib_qp.rcq = qp1_qp->rcq; 980 981 qp->qplib_qp.rq.max_wqe = qp1_qp->rq.max_wqe; 982 qp->qplib_qp.rq.max_sge = qp1_qp->rq.max_sge; 983 /* Q full delta can be 1 since it is internal QP */ 984 qp->qplib_qp.rq.q_full_delta = 1; 985 986 qp->qplib_qp.mtu = qp1_qp->mtu; 987 988 qp->qplib_qp.sq_hdr_buf_size = 0; 989 qp->qplib_qp.rq_hdr_buf_size = BNXT_QPLIB_MAX_GRH_HDR_SIZE_IPV6; 990 qp->qplib_qp.dpi = &rdev->dpi_privileged; 991 992 rc = bnxt_qplib_create_qp(qp1_res, &qp->qplib_qp); 993 if (rc) 994 goto fail; 995 996 rdev->sqp_id = qp->qplib_qp.id; 997 998 spin_lock_init(&qp->sq_lock); 999 INIT_LIST_HEAD(&qp->list); 1000 mutex_lock(&rdev->qp_lock); 1001 list_add_tail(&qp->list, &rdev->qp_list); 1002 atomic_inc(&rdev->qp_count); 1003 mutex_unlock(&rdev->qp_lock); 1004 return qp; 1005 fail: 1006 kfree(qp); 1007 return NULL; 1008 } 1009 1010 struct ib_qp *bnxt_re_create_qp(struct ib_pd *ib_pd, 1011 struct ib_qp_init_attr *qp_init_attr, 1012 struct ib_udata *udata) 1013 { 1014 struct bnxt_re_pd *pd = container_of(ib_pd, struct bnxt_re_pd, ib_pd); 1015 struct bnxt_re_dev *rdev = pd->rdev; 1016 struct bnxt_qplib_dev_attr *dev_attr = &rdev->dev_attr; 1017 struct bnxt_re_qp *qp; 1018 struct bnxt_re_cq *cq; 1019 int rc, entries; 1020 1021 if ((qp_init_attr->cap.max_send_wr > dev_attr->max_qp_wqes) || 1022 (qp_init_attr->cap.max_recv_wr > dev_attr->max_qp_wqes) || 1023 (qp_init_attr->cap.max_send_sge > dev_attr->max_qp_sges) || 1024 (qp_init_attr->cap.max_recv_sge > dev_attr->max_qp_sges) || 1025 (qp_init_attr->cap.max_inline_data > dev_attr->max_inline_data)) 1026 return ERR_PTR(-EINVAL); 1027 1028 qp = kzalloc(sizeof(*qp), GFP_KERNEL); 1029 if (!qp) 1030 return ERR_PTR(-ENOMEM); 1031 1032 qp->rdev = rdev; 1033 ether_addr_copy(qp->qplib_qp.smac, rdev->netdev->dev_addr); 1034 qp->qplib_qp.pd = &pd->qplib_pd; 1035 qp->qplib_qp.qp_handle = (u64)(unsigned long)(&qp->qplib_qp); 1036 qp->qplib_qp.type = __from_ib_qp_type(qp_init_attr->qp_type); 1037 if (qp->qplib_qp.type == IB_QPT_MAX) { 1038 dev_err(rdev_to_dev(rdev), "QP type 0x%x not supported", 1039 qp->qplib_qp.type); 1040 rc = -EINVAL; 1041 goto fail; 1042 } 1043 qp->qplib_qp.max_inline_data = qp_init_attr->cap.max_inline_data; 1044 qp->qplib_qp.sig_type = ((qp_init_attr->sq_sig_type == 1045 IB_SIGNAL_ALL_WR) ? true : false); 1046 1047 qp->qplib_qp.sq.max_sge = qp_init_attr->cap.max_send_sge; 1048 if (qp->qplib_qp.sq.max_sge > dev_attr->max_qp_sges) 1049 qp->qplib_qp.sq.max_sge = dev_attr->max_qp_sges; 1050 1051 if (qp_init_attr->send_cq) { 1052 cq = container_of(qp_init_attr->send_cq, struct bnxt_re_cq, 1053 ib_cq); 1054 if (!cq) { 1055 dev_err(rdev_to_dev(rdev), "Send CQ not found"); 1056 rc = -EINVAL; 1057 goto fail; 1058 } 1059 qp->qplib_qp.scq = &cq->qplib_cq; 1060 } 1061 1062 if (qp_init_attr->recv_cq) { 1063 cq = container_of(qp_init_attr->recv_cq, struct bnxt_re_cq, 1064 ib_cq); 1065 if (!cq) { 1066 dev_err(rdev_to_dev(rdev), "Receive CQ not found"); 1067 rc = -EINVAL; 1068 goto fail; 1069 } 1070 qp->qplib_qp.rcq = &cq->qplib_cq; 1071 } 1072 1073 if (qp_init_attr->srq) { 1074 dev_err(rdev_to_dev(rdev), "SRQ not supported"); 1075 rc = -ENOTSUPP; 1076 goto fail; 1077 } else { 1078 /* Allocate 1 more than what's provided so posting max doesn't 1079 * mean empty 1080 */ 1081 entries = roundup_pow_of_two(qp_init_attr->cap.max_recv_wr + 1); 1082 qp->qplib_qp.rq.max_wqe = min_t(u32, entries, 1083 dev_attr->max_qp_wqes + 1); 1084 1085 qp->qplib_qp.rq.q_full_delta = qp->qplib_qp.rq.max_wqe - 1086 qp_init_attr->cap.max_recv_wr; 1087 1088 qp->qplib_qp.rq.max_sge = qp_init_attr->cap.max_recv_sge; 1089 if (qp->qplib_qp.rq.max_sge > dev_attr->max_qp_sges) 1090 qp->qplib_qp.rq.max_sge = dev_attr->max_qp_sges; 1091 } 1092 1093 qp->qplib_qp.mtu = ib_mtu_enum_to_int(iboe_get_mtu(rdev->netdev->mtu)); 1094 1095 if (qp_init_attr->qp_type == IB_QPT_GSI) { 1096 /* Allocate 1 more than what's provided */ 1097 entries = roundup_pow_of_two(qp_init_attr->cap.max_send_wr + 1); 1098 qp->qplib_qp.sq.max_wqe = min_t(u32, entries, 1099 dev_attr->max_qp_wqes + 1); 1100 qp->qplib_qp.sq.q_full_delta = qp->qplib_qp.sq.max_wqe - 1101 qp_init_attr->cap.max_send_wr; 1102 qp->qplib_qp.rq.max_sge = dev_attr->max_qp_sges; 1103 if (qp->qplib_qp.rq.max_sge > dev_attr->max_qp_sges) 1104 qp->qplib_qp.rq.max_sge = dev_attr->max_qp_sges; 1105 qp->qplib_qp.sq.max_sge++; 1106 if (qp->qplib_qp.sq.max_sge > dev_attr->max_qp_sges) 1107 qp->qplib_qp.sq.max_sge = dev_attr->max_qp_sges; 1108 1109 qp->qplib_qp.rq_hdr_buf_size = 1110 BNXT_QPLIB_MAX_QP1_RQ_HDR_SIZE_V2; 1111 1112 qp->qplib_qp.sq_hdr_buf_size = 1113 BNXT_QPLIB_MAX_QP1_SQ_HDR_SIZE_V2; 1114 qp->qplib_qp.dpi = &rdev->dpi_privileged; 1115 rc = bnxt_qplib_create_qp1(&rdev->qplib_res, &qp->qplib_qp); 1116 if (rc) { 1117 dev_err(rdev_to_dev(rdev), "Failed to create HW QP1"); 1118 goto fail; 1119 } 1120 /* Create a shadow QP to handle the QP1 traffic */ 1121 rdev->qp1_sqp = bnxt_re_create_shadow_qp(pd, &rdev->qplib_res, 1122 &qp->qplib_qp); 1123 if (!rdev->qp1_sqp) { 1124 rc = -EINVAL; 1125 dev_err(rdev_to_dev(rdev), 1126 "Failed to create Shadow QP for QP1"); 1127 goto qp_destroy; 1128 } 1129 rdev->sqp_ah = bnxt_re_create_shadow_qp_ah(pd, &rdev->qplib_res, 1130 &qp->qplib_qp); 1131 if (!rdev->sqp_ah) { 1132 bnxt_qplib_destroy_qp(&rdev->qplib_res, 1133 &rdev->qp1_sqp->qplib_qp); 1134 rc = -EINVAL; 1135 dev_err(rdev_to_dev(rdev), 1136 "Failed to create AH entry for ShadowQP"); 1137 goto qp_destroy; 1138 } 1139 1140 } else { 1141 /* Allocate 128 + 1 more than what's provided */ 1142 entries = roundup_pow_of_two(qp_init_attr->cap.max_send_wr + 1143 BNXT_QPLIB_RESERVED_QP_WRS + 1); 1144 qp->qplib_qp.sq.max_wqe = min_t(u32, entries, 1145 dev_attr->max_qp_wqes + 1146 BNXT_QPLIB_RESERVED_QP_WRS + 1); 1147 qp->qplib_qp.sq.q_full_delta = BNXT_QPLIB_RESERVED_QP_WRS + 1; 1148 1149 /* 1150 * Reserving one slot for Phantom WQE. Application can 1151 * post one extra entry in this case. But allowing this to avoid 1152 * unexpected Queue full condition 1153 */ 1154 1155 qp->qplib_qp.sq.q_full_delta -= 1; 1156 1157 qp->qplib_qp.max_rd_atomic = dev_attr->max_qp_rd_atom; 1158 qp->qplib_qp.max_dest_rd_atomic = dev_attr->max_qp_init_rd_atom; 1159 if (udata) { 1160 rc = bnxt_re_init_user_qp(rdev, pd, qp, udata); 1161 if (rc) 1162 goto fail; 1163 } else { 1164 qp->qplib_qp.dpi = &rdev->dpi_privileged; 1165 } 1166 1167 rc = bnxt_qplib_create_qp(&rdev->qplib_res, &qp->qplib_qp); 1168 if (rc) { 1169 dev_err(rdev_to_dev(rdev), "Failed to create HW QP"); 1170 goto fail; 1171 } 1172 } 1173 1174 qp->ib_qp.qp_num = qp->qplib_qp.id; 1175 spin_lock_init(&qp->sq_lock); 1176 spin_lock_init(&qp->rq_lock); 1177 1178 if (udata) { 1179 struct bnxt_re_qp_resp resp; 1180 1181 resp.qpid = qp->ib_qp.qp_num; 1182 resp.rsvd = 0; 1183 rc = ib_copy_to_udata(udata, &resp, sizeof(resp)); 1184 if (rc) { 1185 dev_err(rdev_to_dev(rdev), "Failed to copy QP udata"); 1186 goto qp_destroy; 1187 } 1188 } 1189 INIT_LIST_HEAD(&qp->list); 1190 mutex_lock(&rdev->qp_lock); 1191 list_add_tail(&qp->list, &rdev->qp_list); 1192 atomic_inc(&rdev->qp_count); 1193 mutex_unlock(&rdev->qp_lock); 1194 1195 return &qp->ib_qp; 1196 qp_destroy: 1197 bnxt_qplib_destroy_qp(&rdev->qplib_res, &qp->qplib_qp); 1198 fail: 1199 kfree(qp); 1200 return ERR_PTR(rc); 1201 } 1202 1203 static u8 __from_ib_qp_state(enum ib_qp_state state) 1204 { 1205 switch (state) { 1206 case IB_QPS_RESET: 1207 return CMDQ_MODIFY_QP_NEW_STATE_RESET; 1208 case IB_QPS_INIT: 1209 return CMDQ_MODIFY_QP_NEW_STATE_INIT; 1210 case IB_QPS_RTR: 1211 return CMDQ_MODIFY_QP_NEW_STATE_RTR; 1212 case IB_QPS_RTS: 1213 return CMDQ_MODIFY_QP_NEW_STATE_RTS; 1214 case IB_QPS_SQD: 1215 return CMDQ_MODIFY_QP_NEW_STATE_SQD; 1216 case IB_QPS_SQE: 1217 return CMDQ_MODIFY_QP_NEW_STATE_SQE; 1218 case IB_QPS_ERR: 1219 default: 1220 return CMDQ_MODIFY_QP_NEW_STATE_ERR; 1221 } 1222 } 1223 1224 static enum ib_qp_state __to_ib_qp_state(u8 state) 1225 { 1226 switch (state) { 1227 case CMDQ_MODIFY_QP_NEW_STATE_RESET: 1228 return IB_QPS_RESET; 1229 case CMDQ_MODIFY_QP_NEW_STATE_INIT: 1230 return IB_QPS_INIT; 1231 case CMDQ_MODIFY_QP_NEW_STATE_RTR: 1232 return IB_QPS_RTR; 1233 case CMDQ_MODIFY_QP_NEW_STATE_RTS: 1234 return IB_QPS_RTS; 1235 case CMDQ_MODIFY_QP_NEW_STATE_SQD: 1236 return IB_QPS_SQD; 1237 case CMDQ_MODIFY_QP_NEW_STATE_SQE: 1238 return IB_QPS_SQE; 1239 case CMDQ_MODIFY_QP_NEW_STATE_ERR: 1240 default: 1241 return IB_QPS_ERR; 1242 } 1243 } 1244 1245 static u32 __from_ib_mtu(enum ib_mtu mtu) 1246 { 1247 switch (mtu) { 1248 case IB_MTU_256: 1249 return CMDQ_MODIFY_QP_PATH_MTU_MTU_256; 1250 case IB_MTU_512: 1251 return CMDQ_MODIFY_QP_PATH_MTU_MTU_512; 1252 case IB_MTU_1024: 1253 return CMDQ_MODIFY_QP_PATH_MTU_MTU_1024; 1254 case IB_MTU_2048: 1255 return CMDQ_MODIFY_QP_PATH_MTU_MTU_2048; 1256 case IB_MTU_4096: 1257 return CMDQ_MODIFY_QP_PATH_MTU_MTU_4096; 1258 default: 1259 return CMDQ_MODIFY_QP_PATH_MTU_MTU_2048; 1260 } 1261 } 1262 1263 static enum ib_mtu __to_ib_mtu(u32 mtu) 1264 { 1265 switch (mtu & CREQ_QUERY_QP_RESP_SB_PATH_MTU_MASK) { 1266 case CMDQ_MODIFY_QP_PATH_MTU_MTU_256: 1267 return IB_MTU_256; 1268 case CMDQ_MODIFY_QP_PATH_MTU_MTU_512: 1269 return IB_MTU_512; 1270 case CMDQ_MODIFY_QP_PATH_MTU_MTU_1024: 1271 return IB_MTU_1024; 1272 case CMDQ_MODIFY_QP_PATH_MTU_MTU_2048: 1273 return IB_MTU_2048; 1274 case CMDQ_MODIFY_QP_PATH_MTU_MTU_4096: 1275 return IB_MTU_4096; 1276 default: 1277 return IB_MTU_2048; 1278 } 1279 } 1280 1281 static int bnxt_re_modify_shadow_qp(struct bnxt_re_dev *rdev, 1282 struct bnxt_re_qp *qp1_qp, 1283 int qp_attr_mask) 1284 { 1285 struct bnxt_re_qp *qp = rdev->qp1_sqp; 1286 int rc = 0; 1287 1288 if (qp_attr_mask & IB_QP_STATE) { 1289 qp->qplib_qp.modify_flags |= CMDQ_MODIFY_QP_MODIFY_MASK_STATE; 1290 qp->qplib_qp.state = qp1_qp->qplib_qp.state; 1291 } 1292 if (qp_attr_mask & IB_QP_PKEY_INDEX) { 1293 qp->qplib_qp.modify_flags |= CMDQ_MODIFY_QP_MODIFY_MASK_PKEY; 1294 qp->qplib_qp.pkey_index = qp1_qp->qplib_qp.pkey_index; 1295 } 1296 1297 if (qp_attr_mask & IB_QP_QKEY) { 1298 qp->qplib_qp.modify_flags |= CMDQ_MODIFY_QP_MODIFY_MASK_QKEY; 1299 /* Using a Random QKEY */ 1300 qp->qplib_qp.qkey = 0x81818181; 1301 } 1302 if (qp_attr_mask & IB_QP_SQ_PSN) { 1303 qp->qplib_qp.modify_flags |= CMDQ_MODIFY_QP_MODIFY_MASK_SQ_PSN; 1304 qp->qplib_qp.sq.psn = qp1_qp->qplib_qp.sq.psn; 1305 } 1306 1307 rc = bnxt_qplib_modify_qp(&rdev->qplib_res, &qp->qplib_qp); 1308 if (rc) 1309 dev_err(rdev_to_dev(rdev), 1310 "Failed to modify Shadow QP for QP1"); 1311 return rc; 1312 } 1313 1314 int bnxt_re_modify_qp(struct ib_qp *ib_qp, struct ib_qp_attr *qp_attr, 1315 int qp_attr_mask, struct ib_udata *udata) 1316 { 1317 struct bnxt_re_qp *qp = container_of(ib_qp, struct bnxt_re_qp, ib_qp); 1318 struct bnxt_re_dev *rdev = qp->rdev; 1319 struct bnxt_qplib_dev_attr *dev_attr = &rdev->dev_attr; 1320 enum ib_qp_state curr_qp_state, new_qp_state; 1321 int rc, entries; 1322 int status; 1323 union ib_gid sgid; 1324 struct ib_gid_attr sgid_attr; 1325 u8 nw_type; 1326 1327 qp->qplib_qp.modify_flags = 0; 1328 if (qp_attr_mask & IB_QP_STATE) { 1329 curr_qp_state = __to_ib_qp_state(qp->qplib_qp.cur_qp_state); 1330 new_qp_state = qp_attr->qp_state; 1331 if (!ib_modify_qp_is_ok(curr_qp_state, new_qp_state, 1332 ib_qp->qp_type, qp_attr_mask, 1333 IB_LINK_LAYER_ETHERNET)) { 1334 dev_err(rdev_to_dev(rdev), 1335 "Invalid attribute mask: %#x specified ", 1336 qp_attr_mask); 1337 dev_err(rdev_to_dev(rdev), 1338 "for qpn: %#x type: %#x", 1339 ib_qp->qp_num, ib_qp->qp_type); 1340 dev_err(rdev_to_dev(rdev), 1341 "curr_qp_state=0x%x, new_qp_state=0x%x\n", 1342 curr_qp_state, new_qp_state); 1343 return -EINVAL; 1344 } 1345 qp->qplib_qp.modify_flags |= CMDQ_MODIFY_QP_MODIFY_MASK_STATE; 1346 qp->qplib_qp.state = __from_ib_qp_state(qp_attr->qp_state); 1347 1348 if (!qp->sumem && 1349 qp->qplib_qp.state == CMDQ_MODIFY_QP_NEW_STATE_ERR) { 1350 dev_dbg(rdev_to_dev(rdev), 1351 "Move QP = %p to flush list\n", 1352 qp); 1353 bnxt_qplib_add_flush_qp(&qp->qplib_qp); 1354 } 1355 if (!qp->sumem && 1356 qp->qplib_qp.state == CMDQ_MODIFY_QP_NEW_STATE_RESET) { 1357 dev_dbg(rdev_to_dev(rdev), 1358 "Move QP = %p out of flush list\n", 1359 qp); 1360 bnxt_qplib_del_flush_qp(&qp->qplib_qp); 1361 } 1362 } 1363 if (qp_attr_mask & IB_QP_EN_SQD_ASYNC_NOTIFY) { 1364 qp->qplib_qp.modify_flags |= 1365 CMDQ_MODIFY_QP_MODIFY_MASK_EN_SQD_ASYNC_NOTIFY; 1366 qp->qplib_qp.en_sqd_async_notify = true; 1367 } 1368 if (qp_attr_mask & IB_QP_ACCESS_FLAGS) { 1369 qp->qplib_qp.modify_flags |= CMDQ_MODIFY_QP_MODIFY_MASK_ACCESS; 1370 qp->qplib_qp.access = 1371 __from_ib_access_flags(qp_attr->qp_access_flags); 1372 /* LOCAL_WRITE access must be set to allow RC receive */ 1373 qp->qplib_qp.access |= BNXT_QPLIB_ACCESS_LOCAL_WRITE; 1374 } 1375 if (qp_attr_mask & IB_QP_PKEY_INDEX) { 1376 qp->qplib_qp.modify_flags |= CMDQ_MODIFY_QP_MODIFY_MASK_PKEY; 1377 qp->qplib_qp.pkey_index = qp_attr->pkey_index; 1378 } 1379 if (qp_attr_mask & IB_QP_QKEY) { 1380 qp->qplib_qp.modify_flags |= CMDQ_MODIFY_QP_MODIFY_MASK_QKEY; 1381 qp->qplib_qp.qkey = qp_attr->qkey; 1382 } 1383 if (qp_attr_mask & IB_QP_AV) { 1384 const struct ib_global_route *grh = 1385 rdma_ah_read_grh(&qp_attr->ah_attr); 1386 1387 qp->qplib_qp.modify_flags |= CMDQ_MODIFY_QP_MODIFY_MASK_DGID | 1388 CMDQ_MODIFY_QP_MODIFY_MASK_FLOW_LABEL | 1389 CMDQ_MODIFY_QP_MODIFY_MASK_SGID_INDEX | 1390 CMDQ_MODIFY_QP_MODIFY_MASK_HOP_LIMIT | 1391 CMDQ_MODIFY_QP_MODIFY_MASK_TRAFFIC_CLASS | 1392 CMDQ_MODIFY_QP_MODIFY_MASK_DEST_MAC | 1393 CMDQ_MODIFY_QP_MODIFY_MASK_VLAN_ID; 1394 memcpy(qp->qplib_qp.ah.dgid.data, grh->dgid.raw, 1395 sizeof(qp->qplib_qp.ah.dgid.data)); 1396 qp->qplib_qp.ah.flow_label = grh->flow_label; 1397 /* If RoCE V2 is enabled, stack will have two entries for 1398 * each GID entry. Avoiding this duplicte entry in HW. Dividing 1399 * the GID index by 2 for RoCE V2 1400 */ 1401 qp->qplib_qp.ah.sgid_index = grh->sgid_index / 2; 1402 qp->qplib_qp.ah.host_sgid_index = grh->sgid_index; 1403 qp->qplib_qp.ah.hop_limit = grh->hop_limit; 1404 qp->qplib_qp.ah.traffic_class = grh->traffic_class; 1405 qp->qplib_qp.ah.sl = rdma_ah_get_sl(&qp_attr->ah_attr); 1406 ether_addr_copy(qp->qplib_qp.ah.dmac, 1407 qp_attr->ah_attr.roce.dmac); 1408 1409 status = ib_get_cached_gid(&rdev->ibdev, 1, 1410 grh->sgid_index, 1411 &sgid, &sgid_attr); 1412 if (!status && sgid_attr.ndev) { 1413 memcpy(qp->qplib_qp.smac, sgid_attr.ndev->dev_addr, 1414 ETH_ALEN); 1415 dev_put(sgid_attr.ndev); 1416 nw_type = ib_gid_to_network_type(sgid_attr.gid_type, 1417 &sgid); 1418 switch (nw_type) { 1419 case RDMA_NETWORK_IPV4: 1420 qp->qplib_qp.nw_type = 1421 CMDQ_MODIFY_QP_NETWORK_TYPE_ROCEV2_IPV4; 1422 break; 1423 case RDMA_NETWORK_IPV6: 1424 qp->qplib_qp.nw_type = 1425 CMDQ_MODIFY_QP_NETWORK_TYPE_ROCEV2_IPV6; 1426 break; 1427 default: 1428 qp->qplib_qp.nw_type = 1429 CMDQ_MODIFY_QP_NETWORK_TYPE_ROCEV1; 1430 break; 1431 } 1432 } 1433 } 1434 1435 if (qp_attr_mask & IB_QP_PATH_MTU) { 1436 qp->qplib_qp.modify_flags |= 1437 CMDQ_MODIFY_QP_MODIFY_MASK_PATH_MTU; 1438 qp->qplib_qp.path_mtu = __from_ib_mtu(qp_attr->path_mtu); 1439 } else if (qp_attr->qp_state == IB_QPS_RTR) { 1440 qp->qplib_qp.modify_flags |= 1441 CMDQ_MODIFY_QP_MODIFY_MASK_PATH_MTU; 1442 qp->qplib_qp.path_mtu = 1443 __from_ib_mtu(iboe_get_mtu(rdev->netdev->mtu)); 1444 } 1445 1446 if (qp_attr_mask & IB_QP_TIMEOUT) { 1447 qp->qplib_qp.modify_flags |= CMDQ_MODIFY_QP_MODIFY_MASK_TIMEOUT; 1448 qp->qplib_qp.timeout = qp_attr->timeout; 1449 } 1450 if (qp_attr_mask & IB_QP_RETRY_CNT) { 1451 qp->qplib_qp.modify_flags |= 1452 CMDQ_MODIFY_QP_MODIFY_MASK_RETRY_CNT; 1453 qp->qplib_qp.retry_cnt = qp_attr->retry_cnt; 1454 } 1455 if (qp_attr_mask & IB_QP_RNR_RETRY) { 1456 qp->qplib_qp.modify_flags |= 1457 CMDQ_MODIFY_QP_MODIFY_MASK_RNR_RETRY; 1458 qp->qplib_qp.rnr_retry = qp_attr->rnr_retry; 1459 } 1460 if (qp_attr_mask & IB_QP_MIN_RNR_TIMER) { 1461 qp->qplib_qp.modify_flags |= 1462 CMDQ_MODIFY_QP_MODIFY_MASK_MIN_RNR_TIMER; 1463 qp->qplib_qp.min_rnr_timer = qp_attr->min_rnr_timer; 1464 } 1465 if (qp_attr_mask & IB_QP_RQ_PSN) { 1466 qp->qplib_qp.modify_flags |= CMDQ_MODIFY_QP_MODIFY_MASK_RQ_PSN; 1467 qp->qplib_qp.rq.psn = qp_attr->rq_psn; 1468 } 1469 if (qp_attr_mask & IB_QP_MAX_QP_RD_ATOMIC) { 1470 qp->qplib_qp.modify_flags |= 1471 CMDQ_MODIFY_QP_MODIFY_MASK_MAX_RD_ATOMIC; 1472 /* Cap the max_rd_atomic to device max */ 1473 qp->qplib_qp.max_rd_atomic = min_t(u32, qp_attr->max_rd_atomic, 1474 dev_attr->max_qp_rd_atom); 1475 } 1476 if (qp_attr_mask & IB_QP_SQ_PSN) { 1477 qp->qplib_qp.modify_flags |= CMDQ_MODIFY_QP_MODIFY_MASK_SQ_PSN; 1478 qp->qplib_qp.sq.psn = qp_attr->sq_psn; 1479 } 1480 if (qp_attr_mask & IB_QP_MAX_DEST_RD_ATOMIC) { 1481 if (qp_attr->max_dest_rd_atomic > 1482 dev_attr->max_qp_init_rd_atom) { 1483 dev_err(rdev_to_dev(rdev), 1484 "max_dest_rd_atomic requested%d is > dev_max%d", 1485 qp_attr->max_dest_rd_atomic, 1486 dev_attr->max_qp_init_rd_atom); 1487 return -EINVAL; 1488 } 1489 1490 qp->qplib_qp.modify_flags |= 1491 CMDQ_MODIFY_QP_MODIFY_MASK_MAX_DEST_RD_ATOMIC; 1492 qp->qplib_qp.max_dest_rd_atomic = qp_attr->max_dest_rd_atomic; 1493 } 1494 if (qp_attr_mask & IB_QP_CAP) { 1495 qp->qplib_qp.modify_flags |= 1496 CMDQ_MODIFY_QP_MODIFY_MASK_SQ_SIZE | 1497 CMDQ_MODIFY_QP_MODIFY_MASK_RQ_SIZE | 1498 CMDQ_MODIFY_QP_MODIFY_MASK_SQ_SGE | 1499 CMDQ_MODIFY_QP_MODIFY_MASK_RQ_SGE | 1500 CMDQ_MODIFY_QP_MODIFY_MASK_MAX_INLINE_DATA; 1501 if ((qp_attr->cap.max_send_wr >= dev_attr->max_qp_wqes) || 1502 (qp_attr->cap.max_recv_wr >= dev_attr->max_qp_wqes) || 1503 (qp_attr->cap.max_send_sge >= dev_attr->max_qp_sges) || 1504 (qp_attr->cap.max_recv_sge >= dev_attr->max_qp_sges) || 1505 (qp_attr->cap.max_inline_data >= 1506 dev_attr->max_inline_data)) { 1507 dev_err(rdev_to_dev(rdev), 1508 "Create QP failed - max exceeded"); 1509 return -EINVAL; 1510 } 1511 entries = roundup_pow_of_two(qp_attr->cap.max_send_wr); 1512 qp->qplib_qp.sq.max_wqe = min_t(u32, entries, 1513 dev_attr->max_qp_wqes + 1); 1514 qp->qplib_qp.sq.q_full_delta = qp->qplib_qp.sq.max_wqe - 1515 qp_attr->cap.max_send_wr; 1516 /* 1517 * Reserving one slot for Phantom WQE. Some application can 1518 * post one extra entry in this case. Allowing this to avoid 1519 * unexpected Queue full condition 1520 */ 1521 qp->qplib_qp.sq.q_full_delta -= 1; 1522 qp->qplib_qp.sq.max_sge = qp_attr->cap.max_send_sge; 1523 if (qp->qplib_qp.rq.max_wqe) { 1524 entries = roundup_pow_of_two(qp_attr->cap.max_recv_wr); 1525 qp->qplib_qp.rq.max_wqe = 1526 min_t(u32, entries, dev_attr->max_qp_wqes + 1); 1527 qp->qplib_qp.rq.q_full_delta = qp->qplib_qp.rq.max_wqe - 1528 qp_attr->cap.max_recv_wr; 1529 qp->qplib_qp.rq.max_sge = qp_attr->cap.max_recv_sge; 1530 } else { 1531 /* SRQ was used prior, just ignore the RQ caps */ 1532 } 1533 } 1534 if (qp_attr_mask & IB_QP_DEST_QPN) { 1535 qp->qplib_qp.modify_flags |= 1536 CMDQ_MODIFY_QP_MODIFY_MASK_DEST_QP_ID; 1537 qp->qplib_qp.dest_qpn = qp_attr->dest_qp_num; 1538 } 1539 rc = bnxt_qplib_modify_qp(&rdev->qplib_res, &qp->qplib_qp); 1540 if (rc) { 1541 dev_err(rdev_to_dev(rdev), "Failed to modify HW QP"); 1542 return rc; 1543 } 1544 if (ib_qp->qp_type == IB_QPT_GSI && rdev->qp1_sqp) 1545 rc = bnxt_re_modify_shadow_qp(rdev, qp, qp_attr_mask); 1546 return rc; 1547 } 1548 1549 int bnxt_re_query_qp(struct ib_qp *ib_qp, struct ib_qp_attr *qp_attr, 1550 int qp_attr_mask, struct ib_qp_init_attr *qp_init_attr) 1551 { 1552 struct bnxt_re_qp *qp = container_of(ib_qp, struct bnxt_re_qp, ib_qp); 1553 struct bnxt_re_dev *rdev = qp->rdev; 1554 struct bnxt_qplib_qp qplib_qp; 1555 int rc; 1556 1557 memset(&qplib_qp, 0, sizeof(struct bnxt_qplib_qp)); 1558 qplib_qp.id = qp->qplib_qp.id; 1559 qplib_qp.ah.host_sgid_index = qp->qplib_qp.ah.host_sgid_index; 1560 1561 rc = bnxt_qplib_query_qp(&rdev->qplib_res, &qplib_qp); 1562 if (rc) { 1563 dev_err(rdev_to_dev(rdev), "Failed to query HW QP"); 1564 return rc; 1565 } 1566 qp_attr->qp_state = __to_ib_qp_state(qplib_qp.state); 1567 qp_attr->en_sqd_async_notify = qplib_qp.en_sqd_async_notify ? 1 : 0; 1568 qp_attr->qp_access_flags = __to_ib_access_flags(qplib_qp.access); 1569 qp_attr->pkey_index = qplib_qp.pkey_index; 1570 qp_attr->qkey = qplib_qp.qkey; 1571 qp_attr->ah_attr.type = RDMA_AH_ATTR_TYPE_ROCE; 1572 rdma_ah_set_grh(&qp_attr->ah_attr, NULL, qplib_qp.ah.flow_label, 1573 qplib_qp.ah.host_sgid_index, 1574 qplib_qp.ah.hop_limit, 1575 qplib_qp.ah.traffic_class); 1576 rdma_ah_set_dgid_raw(&qp_attr->ah_attr, qplib_qp.ah.dgid.data); 1577 rdma_ah_set_sl(&qp_attr->ah_attr, qplib_qp.ah.sl); 1578 ether_addr_copy(qp_attr->ah_attr.roce.dmac, qplib_qp.ah.dmac); 1579 qp_attr->path_mtu = __to_ib_mtu(qplib_qp.path_mtu); 1580 qp_attr->timeout = qplib_qp.timeout; 1581 qp_attr->retry_cnt = qplib_qp.retry_cnt; 1582 qp_attr->rnr_retry = qplib_qp.rnr_retry; 1583 qp_attr->min_rnr_timer = qplib_qp.min_rnr_timer; 1584 qp_attr->rq_psn = qplib_qp.rq.psn; 1585 qp_attr->max_rd_atomic = qplib_qp.max_rd_atomic; 1586 qp_attr->sq_psn = qplib_qp.sq.psn; 1587 qp_attr->max_dest_rd_atomic = qplib_qp.max_dest_rd_atomic; 1588 qp_init_attr->sq_sig_type = qplib_qp.sig_type ? IB_SIGNAL_ALL_WR : 1589 IB_SIGNAL_REQ_WR; 1590 qp_attr->dest_qp_num = qplib_qp.dest_qpn; 1591 1592 qp_attr->cap.max_send_wr = qp->qplib_qp.sq.max_wqe; 1593 qp_attr->cap.max_send_sge = qp->qplib_qp.sq.max_sge; 1594 qp_attr->cap.max_recv_wr = qp->qplib_qp.rq.max_wqe; 1595 qp_attr->cap.max_recv_sge = qp->qplib_qp.rq.max_sge; 1596 qp_attr->cap.max_inline_data = qp->qplib_qp.max_inline_data; 1597 qp_init_attr->cap = qp_attr->cap; 1598 1599 return 0; 1600 } 1601 1602 /* Routine for sending QP1 packets for RoCE V1 an V2 1603 */ 1604 static int bnxt_re_build_qp1_send_v2(struct bnxt_re_qp *qp, 1605 struct ib_send_wr *wr, 1606 struct bnxt_qplib_swqe *wqe, 1607 int payload_size) 1608 { 1609 struct ib_device *ibdev = &qp->rdev->ibdev; 1610 struct bnxt_re_ah *ah = container_of(ud_wr(wr)->ah, struct bnxt_re_ah, 1611 ib_ah); 1612 struct bnxt_qplib_ah *qplib_ah = &ah->qplib_ah; 1613 struct bnxt_qplib_sge sge; 1614 union ib_gid sgid; 1615 u8 nw_type; 1616 u16 ether_type; 1617 struct ib_gid_attr sgid_attr; 1618 union ib_gid dgid; 1619 bool is_eth = false; 1620 bool is_vlan = false; 1621 bool is_grh = false; 1622 bool is_udp = false; 1623 u8 ip_version = 0; 1624 u16 vlan_id = 0xFFFF; 1625 void *buf; 1626 int i, rc = 0, size; 1627 1628 memset(&qp->qp1_hdr, 0, sizeof(qp->qp1_hdr)); 1629 1630 rc = ib_get_cached_gid(ibdev, 1, 1631 qplib_ah->host_sgid_index, &sgid, 1632 &sgid_attr); 1633 if (rc) { 1634 dev_err(rdev_to_dev(qp->rdev), 1635 "Failed to query gid at index %d", 1636 qplib_ah->host_sgid_index); 1637 return rc; 1638 } 1639 if (sgid_attr.ndev) { 1640 if (is_vlan_dev(sgid_attr.ndev)) 1641 vlan_id = vlan_dev_vlan_id(sgid_attr.ndev); 1642 dev_put(sgid_attr.ndev); 1643 } 1644 /* Get network header type for this GID */ 1645 nw_type = ib_gid_to_network_type(sgid_attr.gid_type, &sgid); 1646 switch (nw_type) { 1647 case RDMA_NETWORK_IPV4: 1648 nw_type = BNXT_RE_ROCEV2_IPV4_PACKET; 1649 break; 1650 case RDMA_NETWORK_IPV6: 1651 nw_type = BNXT_RE_ROCEV2_IPV6_PACKET; 1652 break; 1653 default: 1654 nw_type = BNXT_RE_ROCE_V1_PACKET; 1655 break; 1656 } 1657 memcpy(&dgid.raw, &qplib_ah->dgid, 16); 1658 is_udp = sgid_attr.gid_type == IB_GID_TYPE_ROCE_UDP_ENCAP; 1659 if (is_udp) { 1660 if (ipv6_addr_v4mapped((struct in6_addr *)&sgid)) { 1661 ip_version = 4; 1662 ether_type = ETH_P_IP; 1663 } else { 1664 ip_version = 6; 1665 ether_type = ETH_P_IPV6; 1666 } 1667 is_grh = false; 1668 } else { 1669 ether_type = ETH_P_IBOE; 1670 is_grh = true; 1671 } 1672 1673 is_eth = true; 1674 is_vlan = (vlan_id && (vlan_id < 0x1000)) ? true : false; 1675 1676 ib_ud_header_init(payload_size, !is_eth, is_eth, is_vlan, is_grh, 1677 ip_version, is_udp, 0, &qp->qp1_hdr); 1678 1679 /* ETH */ 1680 ether_addr_copy(qp->qp1_hdr.eth.dmac_h, ah->qplib_ah.dmac); 1681 ether_addr_copy(qp->qp1_hdr.eth.smac_h, qp->qplib_qp.smac); 1682 1683 /* For vlan, check the sgid for vlan existence */ 1684 1685 if (!is_vlan) { 1686 qp->qp1_hdr.eth.type = cpu_to_be16(ether_type); 1687 } else { 1688 qp->qp1_hdr.vlan.type = cpu_to_be16(ether_type); 1689 qp->qp1_hdr.vlan.tag = cpu_to_be16(vlan_id); 1690 } 1691 1692 if (is_grh || (ip_version == 6)) { 1693 memcpy(qp->qp1_hdr.grh.source_gid.raw, sgid.raw, sizeof(sgid)); 1694 memcpy(qp->qp1_hdr.grh.destination_gid.raw, qplib_ah->dgid.data, 1695 sizeof(sgid)); 1696 qp->qp1_hdr.grh.hop_limit = qplib_ah->hop_limit; 1697 } 1698 1699 if (ip_version == 4) { 1700 qp->qp1_hdr.ip4.tos = 0; 1701 qp->qp1_hdr.ip4.id = 0; 1702 qp->qp1_hdr.ip4.frag_off = htons(IP_DF); 1703 qp->qp1_hdr.ip4.ttl = qplib_ah->hop_limit; 1704 1705 memcpy(&qp->qp1_hdr.ip4.saddr, sgid.raw + 12, 4); 1706 memcpy(&qp->qp1_hdr.ip4.daddr, qplib_ah->dgid.data + 12, 4); 1707 qp->qp1_hdr.ip4.check = ib_ud_ip4_csum(&qp->qp1_hdr); 1708 } 1709 1710 if (is_udp) { 1711 qp->qp1_hdr.udp.dport = htons(ROCE_V2_UDP_DPORT); 1712 qp->qp1_hdr.udp.sport = htons(0x8CD1); 1713 qp->qp1_hdr.udp.csum = 0; 1714 } 1715 1716 /* BTH */ 1717 if (wr->opcode == IB_WR_SEND_WITH_IMM) { 1718 qp->qp1_hdr.bth.opcode = IB_OPCODE_UD_SEND_ONLY_WITH_IMMEDIATE; 1719 qp->qp1_hdr.immediate_present = 1; 1720 } else { 1721 qp->qp1_hdr.bth.opcode = IB_OPCODE_UD_SEND_ONLY; 1722 } 1723 if (wr->send_flags & IB_SEND_SOLICITED) 1724 qp->qp1_hdr.bth.solicited_event = 1; 1725 /* pad_count */ 1726 qp->qp1_hdr.bth.pad_count = (4 - payload_size) & 3; 1727 1728 /* P_key for QP1 is for all members */ 1729 qp->qp1_hdr.bth.pkey = cpu_to_be16(0xFFFF); 1730 qp->qp1_hdr.bth.destination_qpn = IB_QP1; 1731 qp->qp1_hdr.bth.ack_req = 0; 1732 qp->send_psn++; 1733 qp->send_psn &= BTH_PSN_MASK; 1734 qp->qp1_hdr.bth.psn = cpu_to_be32(qp->send_psn); 1735 /* DETH */ 1736 /* Use the priviledged Q_Key for QP1 */ 1737 qp->qp1_hdr.deth.qkey = cpu_to_be32(IB_QP1_QKEY); 1738 qp->qp1_hdr.deth.source_qpn = IB_QP1; 1739 1740 /* Pack the QP1 to the transmit buffer */ 1741 buf = bnxt_qplib_get_qp1_sq_buf(&qp->qplib_qp, &sge); 1742 if (buf) { 1743 size = ib_ud_header_pack(&qp->qp1_hdr, buf); 1744 for (i = wqe->num_sge; i; i--) { 1745 wqe->sg_list[i].addr = wqe->sg_list[i - 1].addr; 1746 wqe->sg_list[i].lkey = wqe->sg_list[i - 1].lkey; 1747 wqe->sg_list[i].size = wqe->sg_list[i - 1].size; 1748 } 1749 1750 /* 1751 * Max Header buf size for IPV6 RoCE V2 is 86, 1752 * which is same as the QP1 SQ header buffer. 1753 * Header buf size for IPV4 RoCE V2 can be 66. 1754 * ETH(14) + VLAN(4)+ IP(20) + UDP (8) + BTH(20). 1755 * Subtract 20 bytes from QP1 SQ header buf size 1756 */ 1757 if (is_udp && ip_version == 4) 1758 sge.size -= 20; 1759 /* 1760 * Max Header buf size for RoCE V1 is 78. 1761 * ETH(14) + VLAN(4) + GRH(40) + BTH(20). 1762 * Subtract 8 bytes from QP1 SQ header buf size 1763 */ 1764 if (!is_udp) 1765 sge.size -= 8; 1766 1767 /* Subtract 4 bytes for non vlan packets */ 1768 if (!is_vlan) 1769 sge.size -= 4; 1770 1771 wqe->sg_list[0].addr = sge.addr; 1772 wqe->sg_list[0].lkey = sge.lkey; 1773 wqe->sg_list[0].size = sge.size; 1774 wqe->num_sge++; 1775 1776 } else { 1777 dev_err(rdev_to_dev(qp->rdev), "QP1 buffer is empty!"); 1778 rc = -ENOMEM; 1779 } 1780 return rc; 1781 } 1782 1783 /* For the MAD layer, it only provides the recv SGE the size of 1784 * ib_grh + MAD datagram. No Ethernet headers, Ethertype, BTH, DETH, 1785 * nor RoCE iCRC. The Cu+ solution must provide buffer for the entire 1786 * receive packet (334 bytes) with no VLAN and then copy the GRH 1787 * and the MAD datagram out to the provided SGE. 1788 */ 1789 static int bnxt_re_build_qp1_shadow_qp_recv(struct bnxt_re_qp *qp, 1790 struct ib_recv_wr *wr, 1791 struct bnxt_qplib_swqe *wqe, 1792 int payload_size) 1793 { 1794 struct bnxt_qplib_sge ref, sge; 1795 u32 rq_prod_index; 1796 struct bnxt_re_sqp_entries *sqp_entry; 1797 1798 rq_prod_index = bnxt_qplib_get_rq_prod_index(&qp->qplib_qp); 1799 1800 if (!bnxt_qplib_get_qp1_rq_buf(&qp->qplib_qp, &sge)) 1801 return -ENOMEM; 1802 1803 /* Create 1 SGE to receive the entire 1804 * ethernet packet 1805 */ 1806 /* Save the reference from ULP */ 1807 ref.addr = wqe->sg_list[0].addr; 1808 ref.lkey = wqe->sg_list[0].lkey; 1809 ref.size = wqe->sg_list[0].size; 1810 1811 sqp_entry = &qp->rdev->sqp_tbl[rq_prod_index]; 1812 1813 /* SGE 1 */ 1814 wqe->sg_list[0].addr = sge.addr; 1815 wqe->sg_list[0].lkey = sge.lkey; 1816 wqe->sg_list[0].size = BNXT_QPLIB_MAX_QP1_RQ_HDR_SIZE_V2; 1817 sge.size -= wqe->sg_list[0].size; 1818 1819 sqp_entry->sge.addr = ref.addr; 1820 sqp_entry->sge.lkey = ref.lkey; 1821 sqp_entry->sge.size = ref.size; 1822 /* Store the wrid for reporting completion */ 1823 sqp_entry->wrid = wqe->wr_id; 1824 /* change the wqe->wrid to table index */ 1825 wqe->wr_id = rq_prod_index; 1826 return 0; 1827 } 1828 1829 static int is_ud_qp(struct bnxt_re_qp *qp) 1830 { 1831 return qp->qplib_qp.type == CMDQ_CREATE_QP_TYPE_UD; 1832 } 1833 1834 static int bnxt_re_build_send_wqe(struct bnxt_re_qp *qp, 1835 struct ib_send_wr *wr, 1836 struct bnxt_qplib_swqe *wqe) 1837 { 1838 struct bnxt_re_ah *ah = NULL; 1839 1840 if (is_ud_qp(qp)) { 1841 ah = container_of(ud_wr(wr)->ah, struct bnxt_re_ah, ib_ah); 1842 wqe->send.q_key = ud_wr(wr)->remote_qkey; 1843 wqe->send.dst_qp = ud_wr(wr)->remote_qpn; 1844 wqe->send.avid = ah->qplib_ah.id; 1845 } 1846 switch (wr->opcode) { 1847 case IB_WR_SEND: 1848 wqe->type = BNXT_QPLIB_SWQE_TYPE_SEND; 1849 break; 1850 case IB_WR_SEND_WITH_IMM: 1851 wqe->type = BNXT_QPLIB_SWQE_TYPE_SEND_WITH_IMM; 1852 wqe->send.imm_data = wr->ex.imm_data; 1853 break; 1854 case IB_WR_SEND_WITH_INV: 1855 wqe->type = BNXT_QPLIB_SWQE_TYPE_SEND_WITH_INV; 1856 wqe->send.inv_key = wr->ex.invalidate_rkey; 1857 break; 1858 default: 1859 return -EINVAL; 1860 } 1861 if (wr->send_flags & IB_SEND_SIGNALED) 1862 wqe->flags |= BNXT_QPLIB_SWQE_FLAGS_SIGNAL_COMP; 1863 if (wr->send_flags & IB_SEND_FENCE) 1864 wqe->flags |= BNXT_QPLIB_SWQE_FLAGS_UC_FENCE; 1865 if (wr->send_flags & IB_SEND_SOLICITED) 1866 wqe->flags |= BNXT_QPLIB_SWQE_FLAGS_SOLICIT_EVENT; 1867 if (wr->send_flags & IB_SEND_INLINE) 1868 wqe->flags |= BNXT_QPLIB_SWQE_FLAGS_INLINE; 1869 1870 return 0; 1871 } 1872 1873 static int bnxt_re_build_rdma_wqe(struct ib_send_wr *wr, 1874 struct bnxt_qplib_swqe *wqe) 1875 { 1876 switch (wr->opcode) { 1877 case IB_WR_RDMA_WRITE: 1878 wqe->type = BNXT_QPLIB_SWQE_TYPE_RDMA_WRITE; 1879 break; 1880 case IB_WR_RDMA_WRITE_WITH_IMM: 1881 wqe->type = BNXT_QPLIB_SWQE_TYPE_RDMA_WRITE_WITH_IMM; 1882 wqe->rdma.imm_data = wr->ex.imm_data; 1883 break; 1884 case IB_WR_RDMA_READ: 1885 wqe->type = BNXT_QPLIB_SWQE_TYPE_RDMA_READ; 1886 wqe->rdma.inv_key = wr->ex.invalidate_rkey; 1887 break; 1888 default: 1889 return -EINVAL; 1890 } 1891 wqe->rdma.remote_va = rdma_wr(wr)->remote_addr; 1892 wqe->rdma.r_key = rdma_wr(wr)->rkey; 1893 if (wr->send_flags & IB_SEND_SIGNALED) 1894 wqe->flags |= BNXT_QPLIB_SWQE_FLAGS_SIGNAL_COMP; 1895 if (wr->send_flags & IB_SEND_FENCE) 1896 wqe->flags |= BNXT_QPLIB_SWQE_FLAGS_UC_FENCE; 1897 if (wr->send_flags & IB_SEND_SOLICITED) 1898 wqe->flags |= BNXT_QPLIB_SWQE_FLAGS_SOLICIT_EVENT; 1899 if (wr->send_flags & IB_SEND_INLINE) 1900 wqe->flags |= BNXT_QPLIB_SWQE_FLAGS_INLINE; 1901 1902 return 0; 1903 } 1904 1905 static int bnxt_re_build_atomic_wqe(struct ib_send_wr *wr, 1906 struct bnxt_qplib_swqe *wqe) 1907 { 1908 switch (wr->opcode) { 1909 case IB_WR_ATOMIC_CMP_AND_SWP: 1910 wqe->type = BNXT_QPLIB_SWQE_TYPE_ATOMIC_CMP_AND_SWP; 1911 wqe->atomic.swap_data = atomic_wr(wr)->swap; 1912 break; 1913 case IB_WR_ATOMIC_FETCH_AND_ADD: 1914 wqe->type = BNXT_QPLIB_SWQE_TYPE_ATOMIC_FETCH_AND_ADD; 1915 wqe->atomic.cmp_data = atomic_wr(wr)->compare_add; 1916 break; 1917 default: 1918 return -EINVAL; 1919 } 1920 wqe->atomic.remote_va = atomic_wr(wr)->remote_addr; 1921 wqe->atomic.r_key = atomic_wr(wr)->rkey; 1922 if (wr->send_flags & IB_SEND_SIGNALED) 1923 wqe->flags |= BNXT_QPLIB_SWQE_FLAGS_SIGNAL_COMP; 1924 if (wr->send_flags & IB_SEND_FENCE) 1925 wqe->flags |= BNXT_QPLIB_SWQE_FLAGS_UC_FENCE; 1926 if (wr->send_flags & IB_SEND_SOLICITED) 1927 wqe->flags |= BNXT_QPLIB_SWQE_FLAGS_SOLICIT_EVENT; 1928 return 0; 1929 } 1930 1931 static int bnxt_re_build_inv_wqe(struct ib_send_wr *wr, 1932 struct bnxt_qplib_swqe *wqe) 1933 { 1934 wqe->type = BNXT_QPLIB_SWQE_TYPE_LOCAL_INV; 1935 wqe->local_inv.inv_l_key = wr->ex.invalidate_rkey; 1936 1937 if (wr->send_flags & IB_SEND_SIGNALED) 1938 wqe->flags |= BNXT_QPLIB_SWQE_FLAGS_SIGNAL_COMP; 1939 if (wr->send_flags & IB_SEND_FENCE) 1940 wqe->flags |= BNXT_QPLIB_SWQE_FLAGS_UC_FENCE; 1941 if (wr->send_flags & IB_SEND_SOLICITED) 1942 wqe->flags |= BNXT_QPLIB_SWQE_FLAGS_SOLICIT_EVENT; 1943 1944 return 0; 1945 } 1946 1947 static int bnxt_re_build_reg_wqe(struct ib_reg_wr *wr, 1948 struct bnxt_qplib_swqe *wqe) 1949 { 1950 struct bnxt_re_mr *mr = container_of(wr->mr, struct bnxt_re_mr, ib_mr); 1951 struct bnxt_qplib_frpl *qplib_frpl = &mr->qplib_frpl; 1952 int access = wr->access; 1953 1954 wqe->frmr.pbl_ptr = (__le64 *)qplib_frpl->hwq.pbl_ptr[0]; 1955 wqe->frmr.pbl_dma_ptr = qplib_frpl->hwq.pbl_dma_ptr[0]; 1956 wqe->frmr.page_list = mr->pages; 1957 wqe->frmr.page_list_len = mr->npages; 1958 wqe->frmr.levels = qplib_frpl->hwq.level + 1; 1959 wqe->type = BNXT_QPLIB_SWQE_TYPE_REG_MR; 1960 1961 if (wr->wr.send_flags & IB_SEND_FENCE) 1962 wqe->flags |= BNXT_QPLIB_SWQE_FLAGS_UC_FENCE; 1963 if (wr->wr.send_flags & IB_SEND_SIGNALED) 1964 wqe->flags |= BNXT_QPLIB_SWQE_FLAGS_SIGNAL_COMP; 1965 1966 if (access & IB_ACCESS_LOCAL_WRITE) 1967 wqe->frmr.access_cntl |= SQ_FR_PMR_ACCESS_CNTL_LOCAL_WRITE; 1968 if (access & IB_ACCESS_REMOTE_READ) 1969 wqe->frmr.access_cntl |= SQ_FR_PMR_ACCESS_CNTL_REMOTE_READ; 1970 if (access & IB_ACCESS_REMOTE_WRITE) 1971 wqe->frmr.access_cntl |= SQ_FR_PMR_ACCESS_CNTL_REMOTE_WRITE; 1972 if (access & IB_ACCESS_REMOTE_ATOMIC) 1973 wqe->frmr.access_cntl |= SQ_FR_PMR_ACCESS_CNTL_REMOTE_ATOMIC; 1974 if (access & IB_ACCESS_MW_BIND) 1975 wqe->frmr.access_cntl |= SQ_FR_PMR_ACCESS_CNTL_WINDOW_BIND; 1976 1977 wqe->frmr.l_key = wr->key; 1978 wqe->frmr.length = wr->mr->length; 1979 wqe->frmr.pbl_pg_sz_log = (wr->mr->page_size >> PAGE_SHIFT_4K) - 1; 1980 wqe->frmr.va = wr->mr->iova; 1981 return 0; 1982 } 1983 1984 static int bnxt_re_copy_inline_data(struct bnxt_re_dev *rdev, 1985 struct ib_send_wr *wr, 1986 struct bnxt_qplib_swqe *wqe) 1987 { 1988 /* Copy the inline data to the data field */ 1989 u8 *in_data; 1990 u32 i, sge_len; 1991 void *sge_addr; 1992 1993 in_data = wqe->inline_data; 1994 for (i = 0; i < wr->num_sge; i++) { 1995 sge_addr = (void *)(unsigned long) 1996 wr->sg_list[i].addr; 1997 sge_len = wr->sg_list[i].length; 1998 1999 if ((sge_len + wqe->inline_len) > 2000 BNXT_QPLIB_SWQE_MAX_INLINE_LENGTH) { 2001 dev_err(rdev_to_dev(rdev), 2002 "Inline data size requested > supported value"); 2003 return -EINVAL; 2004 } 2005 sge_len = wr->sg_list[i].length; 2006 2007 memcpy(in_data, sge_addr, sge_len); 2008 in_data += wr->sg_list[i].length; 2009 wqe->inline_len += wr->sg_list[i].length; 2010 } 2011 return wqe->inline_len; 2012 } 2013 2014 static int bnxt_re_copy_wr_payload(struct bnxt_re_dev *rdev, 2015 struct ib_send_wr *wr, 2016 struct bnxt_qplib_swqe *wqe) 2017 { 2018 int payload_sz = 0; 2019 2020 if (wr->send_flags & IB_SEND_INLINE) 2021 payload_sz = bnxt_re_copy_inline_data(rdev, wr, wqe); 2022 else 2023 payload_sz = bnxt_re_build_sgl(wr->sg_list, wqe->sg_list, 2024 wqe->num_sge); 2025 2026 return payload_sz; 2027 } 2028 2029 static void bnxt_ud_qp_hw_stall_workaround(struct bnxt_re_qp *qp) 2030 { 2031 if ((qp->ib_qp.qp_type == IB_QPT_UD || 2032 qp->ib_qp.qp_type == IB_QPT_GSI || 2033 qp->ib_qp.qp_type == IB_QPT_RAW_ETHERTYPE) && 2034 qp->qplib_qp.wqe_cnt == BNXT_RE_UD_QP_HW_STALL) { 2035 int qp_attr_mask; 2036 struct ib_qp_attr qp_attr; 2037 2038 qp_attr_mask = IB_QP_STATE; 2039 qp_attr.qp_state = IB_QPS_RTS; 2040 bnxt_re_modify_qp(&qp->ib_qp, &qp_attr, qp_attr_mask, NULL); 2041 qp->qplib_qp.wqe_cnt = 0; 2042 } 2043 } 2044 2045 static int bnxt_re_post_send_shadow_qp(struct bnxt_re_dev *rdev, 2046 struct bnxt_re_qp *qp, 2047 struct ib_send_wr *wr) 2048 { 2049 struct bnxt_qplib_swqe wqe; 2050 int rc = 0, payload_sz = 0; 2051 unsigned long flags; 2052 2053 spin_lock_irqsave(&qp->sq_lock, flags); 2054 memset(&wqe, 0, sizeof(wqe)); 2055 while (wr) { 2056 /* House keeping */ 2057 memset(&wqe, 0, sizeof(wqe)); 2058 2059 /* Common */ 2060 wqe.num_sge = wr->num_sge; 2061 if (wr->num_sge > qp->qplib_qp.sq.max_sge) { 2062 dev_err(rdev_to_dev(rdev), 2063 "Limit exceeded for Send SGEs"); 2064 rc = -EINVAL; 2065 goto bad; 2066 } 2067 2068 payload_sz = bnxt_re_copy_wr_payload(qp->rdev, wr, &wqe); 2069 if (payload_sz < 0) { 2070 rc = -EINVAL; 2071 goto bad; 2072 } 2073 wqe.wr_id = wr->wr_id; 2074 2075 wqe.type = BNXT_QPLIB_SWQE_TYPE_SEND; 2076 2077 rc = bnxt_re_build_send_wqe(qp, wr, &wqe); 2078 if (!rc) 2079 rc = bnxt_qplib_post_send(&qp->qplib_qp, &wqe); 2080 bad: 2081 if (rc) { 2082 dev_err(rdev_to_dev(rdev), 2083 "Post send failed opcode = %#x rc = %d", 2084 wr->opcode, rc); 2085 break; 2086 } 2087 wr = wr->next; 2088 } 2089 bnxt_qplib_post_send_db(&qp->qplib_qp); 2090 bnxt_ud_qp_hw_stall_workaround(qp); 2091 spin_unlock_irqrestore(&qp->sq_lock, flags); 2092 return rc; 2093 } 2094 2095 int bnxt_re_post_send(struct ib_qp *ib_qp, struct ib_send_wr *wr, 2096 struct ib_send_wr **bad_wr) 2097 { 2098 struct bnxt_re_qp *qp = container_of(ib_qp, struct bnxt_re_qp, ib_qp); 2099 struct bnxt_qplib_swqe wqe; 2100 int rc = 0, payload_sz = 0; 2101 unsigned long flags; 2102 2103 spin_lock_irqsave(&qp->sq_lock, flags); 2104 while (wr) { 2105 /* House keeping */ 2106 memset(&wqe, 0, sizeof(wqe)); 2107 2108 /* Common */ 2109 wqe.num_sge = wr->num_sge; 2110 if (wr->num_sge > qp->qplib_qp.sq.max_sge) { 2111 dev_err(rdev_to_dev(qp->rdev), 2112 "Limit exceeded for Send SGEs"); 2113 rc = -EINVAL; 2114 goto bad; 2115 } 2116 2117 payload_sz = bnxt_re_copy_wr_payload(qp->rdev, wr, &wqe); 2118 if (payload_sz < 0) { 2119 rc = -EINVAL; 2120 goto bad; 2121 } 2122 wqe.wr_id = wr->wr_id; 2123 2124 switch (wr->opcode) { 2125 case IB_WR_SEND: 2126 case IB_WR_SEND_WITH_IMM: 2127 if (ib_qp->qp_type == IB_QPT_GSI) { 2128 rc = bnxt_re_build_qp1_send_v2(qp, wr, &wqe, 2129 payload_sz); 2130 if (rc) 2131 goto bad; 2132 wqe.rawqp1.lflags |= 2133 SQ_SEND_RAWETH_QP1_LFLAGS_ROCE_CRC; 2134 } 2135 switch (wr->send_flags) { 2136 case IB_SEND_IP_CSUM: 2137 wqe.rawqp1.lflags |= 2138 SQ_SEND_RAWETH_QP1_LFLAGS_IP_CHKSUM; 2139 break; 2140 default: 2141 break; 2142 } 2143 /* Fall thru to build the wqe */ 2144 case IB_WR_SEND_WITH_INV: 2145 rc = bnxt_re_build_send_wqe(qp, wr, &wqe); 2146 break; 2147 case IB_WR_RDMA_WRITE: 2148 case IB_WR_RDMA_WRITE_WITH_IMM: 2149 case IB_WR_RDMA_READ: 2150 rc = bnxt_re_build_rdma_wqe(wr, &wqe); 2151 break; 2152 case IB_WR_ATOMIC_CMP_AND_SWP: 2153 case IB_WR_ATOMIC_FETCH_AND_ADD: 2154 rc = bnxt_re_build_atomic_wqe(wr, &wqe); 2155 break; 2156 case IB_WR_RDMA_READ_WITH_INV: 2157 dev_err(rdev_to_dev(qp->rdev), 2158 "RDMA Read with Invalidate is not supported"); 2159 rc = -EINVAL; 2160 goto bad; 2161 case IB_WR_LOCAL_INV: 2162 rc = bnxt_re_build_inv_wqe(wr, &wqe); 2163 break; 2164 case IB_WR_REG_MR: 2165 rc = bnxt_re_build_reg_wqe(reg_wr(wr), &wqe); 2166 break; 2167 default: 2168 /* Unsupported WRs */ 2169 dev_err(rdev_to_dev(qp->rdev), 2170 "WR (%#x) is not supported", wr->opcode); 2171 rc = -EINVAL; 2172 goto bad; 2173 } 2174 if (!rc) 2175 rc = bnxt_qplib_post_send(&qp->qplib_qp, &wqe); 2176 bad: 2177 if (rc) { 2178 dev_err(rdev_to_dev(qp->rdev), 2179 "post_send failed op:%#x qps = %#x rc = %d\n", 2180 wr->opcode, qp->qplib_qp.state, rc); 2181 *bad_wr = wr; 2182 break; 2183 } 2184 wr = wr->next; 2185 } 2186 bnxt_qplib_post_send_db(&qp->qplib_qp); 2187 bnxt_ud_qp_hw_stall_workaround(qp); 2188 spin_unlock_irqrestore(&qp->sq_lock, flags); 2189 2190 return rc; 2191 } 2192 2193 static int bnxt_re_post_recv_shadow_qp(struct bnxt_re_dev *rdev, 2194 struct bnxt_re_qp *qp, 2195 struct ib_recv_wr *wr) 2196 { 2197 struct bnxt_qplib_swqe wqe; 2198 int rc = 0, payload_sz = 0; 2199 2200 memset(&wqe, 0, sizeof(wqe)); 2201 while (wr) { 2202 /* House keeping */ 2203 memset(&wqe, 0, sizeof(wqe)); 2204 2205 /* Common */ 2206 wqe.num_sge = wr->num_sge; 2207 if (wr->num_sge > qp->qplib_qp.rq.max_sge) { 2208 dev_err(rdev_to_dev(rdev), 2209 "Limit exceeded for Receive SGEs"); 2210 rc = -EINVAL; 2211 break; 2212 } 2213 payload_sz = bnxt_re_build_sgl(wr->sg_list, wqe.sg_list, 2214 wr->num_sge); 2215 wqe.wr_id = wr->wr_id; 2216 wqe.type = BNXT_QPLIB_SWQE_TYPE_RECV; 2217 2218 rc = bnxt_qplib_post_recv(&qp->qplib_qp, &wqe); 2219 if (rc) 2220 break; 2221 2222 wr = wr->next; 2223 } 2224 if (!rc) 2225 bnxt_qplib_post_recv_db(&qp->qplib_qp); 2226 return rc; 2227 } 2228 2229 int bnxt_re_post_recv(struct ib_qp *ib_qp, struct ib_recv_wr *wr, 2230 struct ib_recv_wr **bad_wr) 2231 { 2232 struct bnxt_re_qp *qp = container_of(ib_qp, struct bnxt_re_qp, ib_qp); 2233 struct bnxt_qplib_swqe wqe; 2234 int rc = 0, payload_sz = 0; 2235 unsigned long flags; 2236 u32 count = 0; 2237 2238 spin_lock_irqsave(&qp->rq_lock, flags); 2239 while (wr) { 2240 /* House keeping */ 2241 memset(&wqe, 0, sizeof(wqe)); 2242 2243 /* Common */ 2244 wqe.num_sge = wr->num_sge; 2245 if (wr->num_sge > qp->qplib_qp.rq.max_sge) { 2246 dev_err(rdev_to_dev(qp->rdev), 2247 "Limit exceeded for Receive SGEs"); 2248 rc = -EINVAL; 2249 *bad_wr = wr; 2250 break; 2251 } 2252 2253 payload_sz = bnxt_re_build_sgl(wr->sg_list, wqe.sg_list, 2254 wr->num_sge); 2255 wqe.wr_id = wr->wr_id; 2256 wqe.type = BNXT_QPLIB_SWQE_TYPE_RECV; 2257 2258 if (ib_qp->qp_type == IB_QPT_GSI) 2259 rc = bnxt_re_build_qp1_shadow_qp_recv(qp, wr, &wqe, 2260 payload_sz); 2261 if (!rc) 2262 rc = bnxt_qplib_post_recv(&qp->qplib_qp, &wqe); 2263 if (rc) { 2264 *bad_wr = wr; 2265 break; 2266 } 2267 2268 /* Ring DB if the RQEs posted reaches a threshold value */ 2269 if (++count >= BNXT_RE_RQ_WQE_THRESHOLD) { 2270 bnxt_qplib_post_recv_db(&qp->qplib_qp); 2271 count = 0; 2272 } 2273 2274 wr = wr->next; 2275 } 2276 2277 if (count) 2278 bnxt_qplib_post_recv_db(&qp->qplib_qp); 2279 2280 spin_unlock_irqrestore(&qp->rq_lock, flags); 2281 2282 return rc; 2283 } 2284 2285 /* Completion Queues */ 2286 int bnxt_re_destroy_cq(struct ib_cq *ib_cq) 2287 { 2288 struct bnxt_re_cq *cq = container_of(ib_cq, struct bnxt_re_cq, ib_cq); 2289 struct bnxt_re_dev *rdev = cq->rdev; 2290 int rc; 2291 struct bnxt_qplib_nq *nq = cq->qplib_cq.nq; 2292 2293 rc = bnxt_qplib_destroy_cq(&rdev->qplib_res, &cq->qplib_cq); 2294 if (rc) { 2295 dev_err(rdev_to_dev(rdev), "Failed to destroy HW CQ"); 2296 return rc; 2297 } 2298 if (!IS_ERR_OR_NULL(cq->umem)) 2299 ib_umem_release(cq->umem); 2300 2301 if (cq) { 2302 kfree(cq->cql); 2303 kfree(cq); 2304 } 2305 atomic_dec(&rdev->cq_count); 2306 nq->budget--; 2307 return 0; 2308 } 2309 2310 struct ib_cq *bnxt_re_create_cq(struct ib_device *ibdev, 2311 const struct ib_cq_init_attr *attr, 2312 struct ib_ucontext *context, 2313 struct ib_udata *udata) 2314 { 2315 struct bnxt_re_dev *rdev = to_bnxt_re_dev(ibdev, ibdev); 2316 struct bnxt_qplib_dev_attr *dev_attr = &rdev->dev_attr; 2317 struct bnxt_re_cq *cq = NULL; 2318 int rc, entries; 2319 int cqe = attr->cqe; 2320 struct bnxt_qplib_nq *nq = NULL; 2321 unsigned int nq_alloc_cnt; 2322 2323 /* Validate CQ fields */ 2324 if (cqe < 1 || cqe > dev_attr->max_cq_wqes) { 2325 dev_err(rdev_to_dev(rdev), "Failed to create CQ -max exceeded"); 2326 return ERR_PTR(-EINVAL); 2327 } 2328 cq = kzalloc(sizeof(*cq), GFP_KERNEL); 2329 if (!cq) 2330 return ERR_PTR(-ENOMEM); 2331 2332 cq->rdev = rdev; 2333 cq->qplib_cq.cq_handle = (u64)(unsigned long)(&cq->qplib_cq); 2334 2335 entries = roundup_pow_of_two(cqe + 1); 2336 if (entries > dev_attr->max_cq_wqes + 1) 2337 entries = dev_attr->max_cq_wqes + 1; 2338 2339 if (context) { 2340 struct bnxt_re_cq_req req; 2341 struct bnxt_re_ucontext *uctx = container_of 2342 (context, 2343 struct bnxt_re_ucontext, 2344 ib_uctx); 2345 if (ib_copy_from_udata(&req, udata, sizeof(req))) { 2346 rc = -EFAULT; 2347 goto fail; 2348 } 2349 2350 cq->umem = ib_umem_get(context, req.cq_va, 2351 entries * sizeof(struct cq_base), 2352 IB_ACCESS_LOCAL_WRITE, 1); 2353 if (IS_ERR(cq->umem)) { 2354 rc = PTR_ERR(cq->umem); 2355 goto fail; 2356 } 2357 cq->qplib_cq.sghead = cq->umem->sg_head.sgl; 2358 cq->qplib_cq.nmap = cq->umem->nmap; 2359 cq->qplib_cq.dpi = &uctx->dpi; 2360 } else { 2361 cq->max_cql = min_t(u32, entries, MAX_CQL_PER_POLL); 2362 cq->cql = kcalloc(cq->max_cql, sizeof(struct bnxt_qplib_cqe), 2363 GFP_KERNEL); 2364 if (!cq->cql) { 2365 rc = -ENOMEM; 2366 goto fail; 2367 } 2368 2369 cq->qplib_cq.dpi = &rdev->dpi_privileged; 2370 cq->qplib_cq.sghead = NULL; 2371 cq->qplib_cq.nmap = 0; 2372 } 2373 /* 2374 * Allocating the NQ in a round robin fashion. nq_alloc_cnt is a 2375 * used for getting the NQ index. 2376 */ 2377 nq_alloc_cnt = atomic_inc_return(&rdev->nq_alloc_cnt); 2378 nq = &rdev->nq[nq_alloc_cnt % (rdev->num_msix - 1)]; 2379 cq->qplib_cq.max_wqe = entries; 2380 cq->qplib_cq.cnq_hw_ring_id = nq->ring_id; 2381 cq->qplib_cq.nq = nq; 2382 2383 rc = bnxt_qplib_create_cq(&rdev->qplib_res, &cq->qplib_cq); 2384 if (rc) { 2385 dev_err(rdev_to_dev(rdev), "Failed to create HW CQ"); 2386 goto fail; 2387 } 2388 2389 cq->ib_cq.cqe = entries; 2390 cq->cq_period = cq->qplib_cq.period; 2391 nq->budget++; 2392 2393 atomic_inc(&rdev->cq_count); 2394 2395 if (context) { 2396 struct bnxt_re_cq_resp resp; 2397 2398 resp.cqid = cq->qplib_cq.id; 2399 resp.tail = cq->qplib_cq.hwq.cons; 2400 resp.phase = cq->qplib_cq.period; 2401 resp.rsvd = 0; 2402 rc = ib_copy_to_udata(udata, &resp, sizeof(resp)); 2403 if (rc) { 2404 dev_err(rdev_to_dev(rdev), "Failed to copy CQ udata"); 2405 bnxt_qplib_destroy_cq(&rdev->qplib_res, &cq->qplib_cq); 2406 goto c2fail; 2407 } 2408 } 2409 2410 return &cq->ib_cq; 2411 2412 c2fail: 2413 if (context) 2414 ib_umem_release(cq->umem); 2415 fail: 2416 kfree(cq->cql); 2417 kfree(cq); 2418 return ERR_PTR(rc); 2419 } 2420 2421 static u8 __req_to_ib_wc_status(u8 qstatus) 2422 { 2423 switch (qstatus) { 2424 case CQ_REQ_STATUS_OK: 2425 return IB_WC_SUCCESS; 2426 case CQ_REQ_STATUS_BAD_RESPONSE_ERR: 2427 return IB_WC_BAD_RESP_ERR; 2428 case CQ_REQ_STATUS_LOCAL_LENGTH_ERR: 2429 return IB_WC_LOC_LEN_ERR; 2430 case CQ_REQ_STATUS_LOCAL_QP_OPERATION_ERR: 2431 return IB_WC_LOC_QP_OP_ERR; 2432 case CQ_REQ_STATUS_LOCAL_PROTECTION_ERR: 2433 return IB_WC_LOC_PROT_ERR; 2434 case CQ_REQ_STATUS_MEMORY_MGT_OPERATION_ERR: 2435 return IB_WC_GENERAL_ERR; 2436 case CQ_REQ_STATUS_REMOTE_INVALID_REQUEST_ERR: 2437 return IB_WC_REM_INV_REQ_ERR; 2438 case CQ_REQ_STATUS_REMOTE_ACCESS_ERR: 2439 return IB_WC_REM_ACCESS_ERR; 2440 case CQ_REQ_STATUS_REMOTE_OPERATION_ERR: 2441 return IB_WC_REM_OP_ERR; 2442 case CQ_REQ_STATUS_RNR_NAK_RETRY_CNT_ERR: 2443 return IB_WC_RNR_RETRY_EXC_ERR; 2444 case CQ_REQ_STATUS_TRANSPORT_RETRY_CNT_ERR: 2445 return IB_WC_RETRY_EXC_ERR; 2446 case CQ_REQ_STATUS_WORK_REQUEST_FLUSHED_ERR: 2447 return IB_WC_WR_FLUSH_ERR; 2448 default: 2449 return IB_WC_GENERAL_ERR; 2450 } 2451 return 0; 2452 } 2453 2454 static u8 __rawqp1_to_ib_wc_status(u8 qstatus) 2455 { 2456 switch (qstatus) { 2457 case CQ_RES_RAWETH_QP1_STATUS_OK: 2458 return IB_WC_SUCCESS; 2459 case CQ_RES_RAWETH_QP1_STATUS_LOCAL_ACCESS_ERROR: 2460 return IB_WC_LOC_ACCESS_ERR; 2461 case CQ_RES_RAWETH_QP1_STATUS_HW_LOCAL_LENGTH_ERR: 2462 return IB_WC_LOC_LEN_ERR; 2463 case CQ_RES_RAWETH_QP1_STATUS_LOCAL_PROTECTION_ERR: 2464 return IB_WC_LOC_PROT_ERR; 2465 case CQ_RES_RAWETH_QP1_STATUS_LOCAL_QP_OPERATION_ERR: 2466 return IB_WC_LOC_QP_OP_ERR; 2467 case CQ_RES_RAWETH_QP1_STATUS_MEMORY_MGT_OPERATION_ERR: 2468 return IB_WC_GENERAL_ERR; 2469 case CQ_RES_RAWETH_QP1_STATUS_WORK_REQUEST_FLUSHED_ERR: 2470 return IB_WC_WR_FLUSH_ERR; 2471 case CQ_RES_RAWETH_QP1_STATUS_HW_FLUSH_ERR: 2472 return IB_WC_WR_FLUSH_ERR; 2473 default: 2474 return IB_WC_GENERAL_ERR; 2475 } 2476 } 2477 2478 static u8 __rc_to_ib_wc_status(u8 qstatus) 2479 { 2480 switch (qstatus) { 2481 case CQ_RES_RC_STATUS_OK: 2482 return IB_WC_SUCCESS; 2483 case CQ_RES_RC_STATUS_LOCAL_ACCESS_ERROR: 2484 return IB_WC_LOC_ACCESS_ERR; 2485 case CQ_RES_RC_STATUS_LOCAL_LENGTH_ERR: 2486 return IB_WC_LOC_LEN_ERR; 2487 case CQ_RES_RC_STATUS_LOCAL_PROTECTION_ERR: 2488 return IB_WC_LOC_PROT_ERR; 2489 case CQ_RES_RC_STATUS_LOCAL_QP_OPERATION_ERR: 2490 return IB_WC_LOC_QP_OP_ERR; 2491 case CQ_RES_RC_STATUS_MEMORY_MGT_OPERATION_ERR: 2492 return IB_WC_GENERAL_ERR; 2493 case CQ_RES_RC_STATUS_REMOTE_INVALID_REQUEST_ERR: 2494 return IB_WC_REM_INV_REQ_ERR; 2495 case CQ_RES_RC_STATUS_WORK_REQUEST_FLUSHED_ERR: 2496 return IB_WC_WR_FLUSH_ERR; 2497 case CQ_RES_RC_STATUS_HW_FLUSH_ERR: 2498 return IB_WC_WR_FLUSH_ERR; 2499 default: 2500 return IB_WC_GENERAL_ERR; 2501 } 2502 } 2503 2504 static void bnxt_re_process_req_wc(struct ib_wc *wc, struct bnxt_qplib_cqe *cqe) 2505 { 2506 switch (cqe->type) { 2507 case BNXT_QPLIB_SWQE_TYPE_SEND: 2508 wc->opcode = IB_WC_SEND; 2509 break; 2510 case BNXT_QPLIB_SWQE_TYPE_SEND_WITH_IMM: 2511 wc->opcode = IB_WC_SEND; 2512 wc->wc_flags |= IB_WC_WITH_IMM; 2513 break; 2514 case BNXT_QPLIB_SWQE_TYPE_SEND_WITH_INV: 2515 wc->opcode = IB_WC_SEND; 2516 wc->wc_flags |= IB_WC_WITH_INVALIDATE; 2517 break; 2518 case BNXT_QPLIB_SWQE_TYPE_RDMA_WRITE: 2519 wc->opcode = IB_WC_RDMA_WRITE; 2520 break; 2521 case BNXT_QPLIB_SWQE_TYPE_RDMA_WRITE_WITH_IMM: 2522 wc->opcode = IB_WC_RDMA_WRITE; 2523 wc->wc_flags |= IB_WC_WITH_IMM; 2524 break; 2525 case BNXT_QPLIB_SWQE_TYPE_RDMA_READ: 2526 wc->opcode = IB_WC_RDMA_READ; 2527 break; 2528 case BNXT_QPLIB_SWQE_TYPE_ATOMIC_CMP_AND_SWP: 2529 wc->opcode = IB_WC_COMP_SWAP; 2530 break; 2531 case BNXT_QPLIB_SWQE_TYPE_ATOMIC_FETCH_AND_ADD: 2532 wc->opcode = IB_WC_FETCH_ADD; 2533 break; 2534 case BNXT_QPLIB_SWQE_TYPE_LOCAL_INV: 2535 wc->opcode = IB_WC_LOCAL_INV; 2536 break; 2537 case BNXT_QPLIB_SWQE_TYPE_REG_MR: 2538 wc->opcode = IB_WC_REG_MR; 2539 break; 2540 default: 2541 wc->opcode = IB_WC_SEND; 2542 break; 2543 } 2544 2545 wc->status = __req_to_ib_wc_status(cqe->status); 2546 } 2547 2548 static int bnxt_re_check_packet_type(u16 raweth_qp1_flags, 2549 u16 raweth_qp1_flags2) 2550 { 2551 bool is_udp = false, is_ipv6 = false, is_ipv4 = false; 2552 2553 /* raweth_qp1_flags Bit 9-6 indicates itype */ 2554 if ((raweth_qp1_flags & CQ_RES_RAWETH_QP1_RAWETH_QP1_FLAGS_ITYPE_ROCE) 2555 != CQ_RES_RAWETH_QP1_RAWETH_QP1_FLAGS_ITYPE_ROCE) 2556 return -1; 2557 2558 if (raweth_qp1_flags2 & 2559 CQ_RES_RAWETH_QP1_RAWETH_QP1_FLAGS2_IP_CS_CALC && 2560 raweth_qp1_flags2 & 2561 CQ_RES_RAWETH_QP1_RAWETH_QP1_FLAGS2_L4_CS_CALC) { 2562 is_udp = true; 2563 /* raweth_qp1_flags2 Bit 8 indicates ip_type. 0-v4 1 - v6 */ 2564 (raweth_qp1_flags2 & 2565 CQ_RES_RAWETH_QP1_RAWETH_QP1_FLAGS2_IP_TYPE) ? 2566 (is_ipv6 = true) : (is_ipv4 = true); 2567 return ((is_ipv6) ? 2568 BNXT_RE_ROCEV2_IPV6_PACKET : 2569 BNXT_RE_ROCEV2_IPV4_PACKET); 2570 } else { 2571 return BNXT_RE_ROCE_V1_PACKET; 2572 } 2573 } 2574 2575 static int bnxt_re_to_ib_nw_type(int nw_type) 2576 { 2577 u8 nw_hdr_type = 0xFF; 2578 2579 switch (nw_type) { 2580 case BNXT_RE_ROCE_V1_PACKET: 2581 nw_hdr_type = RDMA_NETWORK_ROCE_V1; 2582 break; 2583 case BNXT_RE_ROCEV2_IPV4_PACKET: 2584 nw_hdr_type = RDMA_NETWORK_IPV4; 2585 break; 2586 case BNXT_RE_ROCEV2_IPV6_PACKET: 2587 nw_hdr_type = RDMA_NETWORK_IPV6; 2588 break; 2589 } 2590 return nw_hdr_type; 2591 } 2592 2593 static bool bnxt_re_is_loopback_packet(struct bnxt_re_dev *rdev, 2594 void *rq_hdr_buf) 2595 { 2596 u8 *tmp_buf = NULL; 2597 struct ethhdr *eth_hdr; 2598 u16 eth_type; 2599 bool rc = false; 2600 2601 tmp_buf = (u8 *)rq_hdr_buf; 2602 /* 2603 * If dest mac is not same as I/F mac, this could be a 2604 * loopback address or multicast address, check whether 2605 * it is a loopback packet 2606 */ 2607 if (!ether_addr_equal(tmp_buf, rdev->netdev->dev_addr)) { 2608 tmp_buf += 4; 2609 /* Check the ether type */ 2610 eth_hdr = (struct ethhdr *)tmp_buf; 2611 eth_type = ntohs(eth_hdr->h_proto); 2612 switch (eth_type) { 2613 case ETH_P_IBOE: 2614 rc = true; 2615 break; 2616 case ETH_P_IP: 2617 case ETH_P_IPV6: { 2618 u32 len; 2619 struct udphdr *udp_hdr; 2620 2621 len = (eth_type == ETH_P_IP ? sizeof(struct iphdr) : 2622 sizeof(struct ipv6hdr)); 2623 tmp_buf += sizeof(struct ethhdr) + len; 2624 udp_hdr = (struct udphdr *)tmp_buf; 2625 if (ntohs(udp_hdr->dest) == 2626 ROCE_V2_UDP_DPORT) 2627 rc = true; 2628 break; 2629 } 2630 default: 2631 break; 2632 } 2633 } 2634 2635 return rc; 2636 } 2637 2638 static int bnxt_re_process_raw_qp_pkt_rx(struct bnxt_re_qp *qp1_qp, 2639 struct bnxt_qplib_cqe *cqe) 2640 { 2641 struct bnxt_re_dev *rdev = qp1_qp->rdev; 2642 struct bnxt_re_sqp_entries *sqp_entry = NULL; 2643 struct bnxt_re_qp *qp = rdev->qp1_sqp; 2644 struct ib_send_wr *swr; 2645 struct ib_ud_wr udwr; 2646 struct ib_recv_wr rwr; 2647 int pkt_type = 0; 2648 u32 tbl_idx; 2649 void *rq_hdr_buf; 2650 dma_addr_t rq_hdr_buf_map; 2651 dma_addr_t shrq_hdr_buf_map; 2652 u32 offset = 0; 2653 u32 skip_bytes = 0; 2654 struct ib_sge s_sge[2]; 2655 struct ib_sge r_sge[2]; 2656 int rc; 2657 2658 memset(&udwr, 0, sizeof(udwr)); 2659 memset(&rwr, 0, sizeof(rwr)); 2660 memset(&s_sge, 0, sizeof(s_sge)); 2661 memset(&r_sge, 0, sizeof(r_sge)); 2662 2663 swr = &udwr.wr; 2664 tbl_idx = cqe->wr_id; 2665 2666 rq_hdr_buf = qp1_qp->qplib_qp.rq_hdr_buf + 2667 (tbl_idx * qp1_qp->qplib_qp.rq_hdr_buf_size); 2668 rq_hdr_buf_map = bnxt_qplib_get_qp_buf_from_index(&qp1_qp->qplib_qp, 2669 tbl_idx); 2670 2671 /* Shadow QP header buffer */ 2672 shrq_hdr_buf_map = bnxt_qplib_get_qp_buf_from_index(&qp->qplib_qp, 2673 tbl_idx); 2674 sqp_entry = &rdev->sqp_tbl[tbl_idx]; 2675 2676 /* Store this cqe */ 2677 memcpy(&sqp_entry->cqe, cqe, sizeof(struct bnxt_qplib_cqe)); 2678 sqp_entry->qp1_qp = qp1_qp; 2679 2680 /* Find packet type from the cqe */ 2681 2682 pkt_type = bnxt_re_check_packet_type(cqe->raweth_qp1_flags, 2683 cqe->raweth_qp1_flags2); 2684 if (pkt_type < 0) { 2685 dev_err(rdev_to_dev(rdev), "Invalid packet\n"); 2686 return -EINVAL; 2687 } 2688 2689 /* Adjust the offset for the user buffer and post in the rq */ 2690 2691 if (pkt_type == BNXT_RE_ROCEV2_IPV4_PACKET) 2692 offset = 20; 2693 2694 /* 2695 * QP1 loopback packet has 4 bytes of internal header before 2696 * ether header. Skip these four bytes. 2697 */ 2698 if (bnxt_re_is_loopback_packet(rdev, rq_hdr_buf)) 2699 skip_bytes = 4; 2700 2701 /* First send SGE . Skip the ether header*/ 2702 s_sge[0].addr = rq_hdr_buf_map + BNXT_QPLIB_MAX_QP1_RQ_ETH_HDR_SIZE 2703 + skip_bytes; 2704 s_sge[0].lkey = 0xFFFFFFFF; 2705 s_sge[0].length = offset ? BNXT_QPLIB_MAX_GRH_HDR_SIZE_IPV4 : 2706 BNXT_QPLIB_MAX_GRH_HDR_SIZE_IPV6; 2707 2708 /* Second Send SGE */ 2709 s_sge[1].addr = s_sge[0].addr + s_sge[0].length + 2710 BNXT_QPLIB_MAX_QP1_RQ_BDETH_HDR_SIZE; 2711 if (pkt_type != BNXT_RE_ROCE_V1_PACKET) 2712 s_sge[1].addr += 8; 2713 s_sge[1].lkey = 0xFFFFFFFF; 2714 s_sge[1].length = 256; 2715 2716 /* First recv SGE */ 2717 2718 r_sge[0].addr = shrq_hdr_buf_map; 2719 r_sge[0].lkey = 0xFFFFFFFF; 2720 r_sge[0].length = 40; 2721 2722 r_sge[1].addr = sqp_entry->sge.addr + offset; 2723 r_sge[1].lkey = sqp_entry->sge.lkey; 2724 r_sge[1].length = BNXT_QPLIB_MAX_GRH_HDR_SIZE_IPV6 + 256 - offset; 2725 2726 /* Create receive work request */ 2727 rwr.num_sge = 2; 2728 rwr.sg_list = r_sge; 2729 rwr.wr_id = tbl_idx; 2730 rwr.next = NULL; 2731 2732 rc = bnxt_re_post_recv_shadow_qp(rdev, qp, &rwr); 2733 if (rc) { 2734 dev_err(rdev_to_dev(rdev), 2735 "Failed to post Rx buffers to shadow QP"); 2736 return -ENOMEM; 2737 } 2738 2739 swr->num_sge = 2; 2740 swr->sg_list = s_sge; 2741 swr->wr_id = tbl_idx; 2742 swr->opcode = IB_WR_SEND; 2743 swr->next = NULL; 2744 2745 udwr.ah = &rdev->sqp_ah->ib_ah; 2746 udwr.remote_qpn = rdev->qp1_sqp->qplib_qp.id; 2747 udwr.remote_qkey = rdev->qp1_sqp->qplib_qp.qkey; 2748 2749 /* post data received in the send queue */ 2750 rc = bnxt_re_post_send_shadow_qp(rdev, qp, swr); 2751 2752 return 0; 2753 } 2754 2755 static void bnxt_re_process_res_rawqp1_wc(struct ib_wc *wc, 2756 struct bnxt_qplib_cqe *cqe) 2757 { 2758 wc->opcode = IB_WC_RECV; 2759 wc->status = __rawqp1_to_ib_wc_status(cqe->status); 2760 wc->wc_flags |= IB_WC_GRH; 2761 } 2762 2763 static void bnxt_re_process_res_rc_wc(struct ib_wc *wc, 2764 struct bnxt_qplib_cqe *cqe) 2765 { 2766 wc->opcode = IB_WC_RECV; 2767 wc->status = __rc_to_ib_wc_status(cqe->status); 2768 2769 if (cqe->flags & CQ_RES_RC_FLAGS_IMM) 2770 wc->wc_flags |= IB_WC_WITH_IMM; 2771 if (cqe->flags & CQ_RES_RC_FLAGS_INV) 2772 wc->wc_flags |= IB_WC_WITH_INVALIDATE; 2773 if ((cqe->flags & (CQ_RES_RC_FLAGS_RDMA | CQ_RES_RC_FLAGS_IMM)) == 2774 (CQ_RES_RC_FLAGS_RDMA | CQ_RES_RC_FLAGS_IMM)) 2775 wc->opcode = IB_WC_RECV_RDMA_WITH_IMM; 2776 } 2777 2778 static void bnxt_re_process_res_shadow_qp_wc(struct bnxt_re_qp *qp, 2779 struct ib_wc *wc, 2780 struct bnxt_qplib_cqe *cqe) 2781 { 2782 u32 tbl_idx; 2783 struct bnxt_re_dev *rdev = qp->rdev; 2784 struct bnxt_re_qp *qp1_qp = NULL; 2785 struct bnxt_qplib_cqe *orig_cqe = NULL; 2786 struct bnxt_re_sqp_entries *sqp_entry = NULL; 2787 int nw_type; 2788 2789 tbl_idx = cqe->wr_id; 2790 2791 sqp_entry = &rdev->sqp_tbl[tbl_idx]; 2792 qp1_qp = sqp_entry->qp1_qp; 2793 orig_cqe = &sqp_entry->cqe; 2794 2795 wc->wr_id = sqp_entry->wrid; 2796 wc->byte_len = orig_cqe->length; 2797 wc->qp = &qp1_qp->ib_qp; 2798 2799 wc->ex.imm_data = orig_cqe->immdata; 2800 wc->src_qp = orig_cqe->src_qp; 2801 memcpy(wc->smac, orig_cqe->smac, ETH_ALEN); 2802 wc->port_num = 1; 2803 wc->vendor_err = orig_cqe->status; 2804 2805 wc->opcode = IB_WC_RECV; 2806 wc->status = __rawqp1_to_ib_wc_status(orig_cqe->status); 2807 wc->wc_flags |= IB_WC_GRH; 2808 2809 nw_type = bnxt_re_check_packet_type(orig_cqe->raweth_qp1_flags, 2810 orig_cqe->raweth_qp1_flags2); 2811 if (nw_type >= 0) { 2812 wc->network_hdr_type = bnxt_re_to_ib_nw_type(nw_type); 2813 wc->wc_flags |= IB_WC_WITH_NETWORK_HDR_TYPE; 2814 } 2815 } 2816 2817 static void bnxt_re_process_res_ud_wc(struct ib_wc *wc, 2818 struct bnxt_qplib_cqe *cqe) 2819 { 2820 wc->opcode = IB_WC_RECV; 2821 wc->status = __rc_to_ib_wc_status(cqe->status); 2822 2823 if (cqe->flags & CQ_RES_RC_FLAGS_IMM) 2824 wc->wc_flags |= IB_WC_WITH_IMM; 2825 if (cqe->flags & CQ_RES_RC_FLAGS_INV) 2826 wc->wc_flags |= IB_WC_WITH_INVALIDATE; 2827 if ((cqe->flags & (CQ_RES_RC_FLAGS_RDMA | CQ_RES_RC_FLAGS_IMM)) == 2828 (CQ_RES_RC_FLAGS_RDMA | CQ_RES_RC_FLAGS_IMM)) 2829 wc->opcode = IB_WC_RECV_RDMA_WITH_IMM; 2830 } 2831 2832 static int send_phantom_wqe(struct bnxt_re_qp *qp) 2833 { 2834 struct bnxt_qplib_qp *lib_qp = &qp->qplib_qp; 2835 unsigned long flags; 2836 int rc = 0; 2837 2838 spin_lock_irqsave(&qp->sq_lock, flags); 2839 2840 rc = bnxt_re_bind_fence_mw(lib_qp); 2841 if (!rc) { 2842 lib_qp->sq.phantom_wqe_cnt++; 2843 dev_dbg(&lib_qp->sq.hwq.pdev->dev, 2844 "qp %#x sq->prod %#x sw_prod %#x phantom_wqe_cnt %d\n", 2845 lib_qp->id, lib_qp->sq.hwq.prod, 2846 HWQ_CMP(lib_qp->sq.hwq.prod, &lib_qp->sq.hwq), 2847 lib_qp->sq.phantom_wqe_cnt); 2848 } 2849 2850 spin_unlock_irqrestore(&qp->sq_lock, flags); 2851 return rc; 2852 } 2853 2854 int bnxt_re_poll_cq(struct ib_cq *ib_cq, int num_entries, struct ib_wc *wc) 2855 { 2856 struct bnxt_re_cq *cq = container_of(ib_cq, struct bnxt_re_cq, ib_cq); 2857 struct bnxt_re_qp *qp; 2858 struct bnxt_qplib_cqe *cqe; 2859 int i, ncqe, budget; 2860 struct bnxt_qplib_q *sq; 2861 struct bnxt_qplib_qp *lib_qp; 2862 u32 tbl_idx; 2863 struct bnxt_re_sqp_entries *sqp_entry = NULL; 2864 unsigned long flags; 2865 2866 spin_lock_irqsave(&cq->cq_lock, flags); 2867 budget = min_t(u32, num_entries, cq->max_cql); 2868 num_entries = budget; 2869 if (!cq->cql) { 2870 dev_err(rdev_to_dev(cq->rdev), "POLL CQ : no CQL to use"); 2871 goto exit; 2872 } 2873 cqe = &cq->cql[0]; 2874 while (budget) { 2875 lib_qp = NULL; 2876 ncqe = bnxt_qplib_poll_cq(&cq->qplib_cq, cqe, budget, &lib_qp); 2877 if (lib_qp) { 2878 sq = &lib_qp->sq; 2879 if (sq->send_phantom) { 2880 qp = container_of(lib_qp, 2881 struct bnxt_re_qp, qplib_qp); 2882 if (send_phantom_wqe(qp) == -ENOMEM) 2883 dev_err(rdev_to_dev(cq->rdev), 2884 "Phantom failed! Scheduled to send again\n"); 2885 else 2886 sq->send_phantom = false; 2887 } 2888 } 2889 if (ncqe < budget) 2890 ncqe += bnxt_qplib_process_flush_list(&cq->qplib_cq, 2891 cqe + ncqe, 2892 budget - ncqe); 2893 2894 if (!ncqe) 2895 break; 2896 2897 for (i = 0; i < ncqe; i++, cqe++) { 2898 /* Transcribe each qplib_wqe back to ib_wc */ 2899 memset(wc, 0, sizeof(*wc)); 2900 2901 wc->wr_id = cqe->wr_id; 2902 wc->byte_len = cqe->length; 2903 qp = container_of 2904 ((struct bnxt_qplib_qp *) 2905 (unsigned long)(cqe->qp_handle), 2906 struct bnxt_re_qp, qplib_qp); 2907 if (!qp) { 2908 dev_err(rdev_to_dev(cq->rdev), 2909 "POLL CQ : bad QP handle"); 2910 continue; 2911 } 2912 wc->qp = &qp->ib_qp; 2913 wc->ex.imm_data = cqe->immdata; 2914 wc->src_qp = cqe->src_qp; 2915 memcpy(wc->smac, cqe->smac, ETH_ALEN); 2916 wc->port_num = 1; 2917 wc->vendor_err = cqe->status; 2918 2919 switch (cqe->opcode) { 2920 case CQ_BASE_CQE_TYPE_REQ: 2921 if (qp->qplib_qp.id == 2922 qp->rdev->qp1_sqp->qplib_qp.id) { 2923 /* Handle this completion with 2924 * the stored completion 2925 */ 2926 memset(wc, 0, sizeof(*wc)); 2927 continue; 2928 } 2929 bnxt_re_process_req_wc(wc, cqe); 2930 break; 2931 case CQ_BASE_CQE_TYPE_RES_RAWETH_QP1: 2932 if (!cqe->status) { 2933 int rc = 0; 2934 2935 rc = bnxt_re_process_raw_qp_pkt_rx 2936 (qp, cqe); 2937 if (!rc) { 2938 memset(wc, 0, sizeof(*wc)); 2939 continue; 2940 } 2941 cqe->status = -1; 2942 } 2943 /* Errors need not be looped back. 2944 * But change the wr_id to the one 2945 * stored in the table 2946 */ 2947 tbl_idx = cqe->wr_id; 2948 sqp_entry = &cq->rdev->sqp_tbl[tbl_idx]; 2949 wc->wr_id = sqp_entry->wrid; 2950 bnxt_re_process_res_rawqp1_wc(wc, cqe); 2951 break; 2952 case CQ_BASE_CQE_TYPE_RES_RC: 2953 bnxt_re_process_res_rc_wc(wc, cqe); 2954 break; 2955 case CQ_BASE_CQE_TYPE_RES_UD: 2956 if (qp->qplib_qp.id == 2957 qp->rdev->qp1_sqp->qplib_qp.id) { 2958 /* Handle this completion with 2959 * the stored completion 2960 */ 2961 if (cqe->status) { 2962 continue; 2963 } else { 2964 bnxt_re_process_res_shadow_qp_wc 2965 (qp, wc, cqe); 2966 break; 2967 } 2968 } 2969 bnxt_re_process_res_ud_wc(wc, cqe); 2970 break; 2971 default: 2972 dev_err(rdev_to_dev(cq->rdev), 2973 "POLL CQ : type 0x%x not handled", 2974 cqe->opcode); 2975 continue; 2976 } 2977 wc++; 2978 budget--; 2979 } 2980 } 2981 exit: 2982 spin_unlock_irqrestore(&cq->cq_lock, flags); 2983 return num_entries - budget; 2984 } 2985 2986 int bnxt_re_req_notify_cq(struct ib_cq *ib_cq, 2987 enum ib_cq_notify_flags ib_cqn_flags) 2988 { 2989 struct bnxt_re_cq *cq = container_of(ib_cq, struct bnxt_re_cq, ib_cq); 2990 int type = 0; 2991 2992 /* Trigger on the very next completion */ 2993 if (ib_cqn_flags & IB_CQ_NEXT_COMP) 2994 type = DBR_DBR_TYPE_CQ_ARMALL; 2995 /* Trigger on the next solicited completion */ 2996 else if (ib_cqn_flags & IB_CQ_SOLICITED) 2997 type = DBR_DBR_TYPE_CQ_ARMSE; 2998 2999 /* Poll to see if there are missed events */ 3000 if ((ib_cqn_flags & IB_CQ_REPORT_MISSED_EVENTS) && 3001 !(bnxt_qplib_is_cq_empty(&cq->qplib_cq))) 3002 return 1; 3003 3004 bnxt_qplib_req_notify_cq(&cq->qplib_cq, type); 3005 3006 return 0; 3007 } 3008 3009 /* Memory Regions */ 3010 struct ib_mr *bnxt_re_get_dma_mr(struct ib_pd *ib_pd, int mr_access_flags) 3011 { 3012 struct bnxt_re_pd *pd = container_of(ib_pd, struct bnxt_re_pd, ib_pd); 3013 struct bnxt_re_dev *rdev = pd->rdev; 3014 struct bnxt_re_mr *mr; 3015 u64 pbl = 0; 3016 int rc; 3017 3018 mr = kzalloc(sizeof(*mr), GFP_KERNEL); 3019 if (!mr) 3020 return ERR_PTR(-ENOMEM); 3021 3022 mr->rdev = rdev; 3023 mr->qplib_mr.pd = &pd->qplib_pd; 3024 mr->qplib_mr.flags = __from_ib_access_flags(mr_access_flags); 3025 mr->qplib_mr.type = CMDQ_ALLOCATE_MRW_MRW_FLAGS_PMR; 3026 3027 /* Allocate and register 0 as the address */ 3028 rc = bnxt_qplib_alloc_mrw(&rdev->qplib_res, &mr->qplib_mr); 3029 if (rc) 3030 goto fail; 3031 3032 mr->qplib_mr.hwq.level = PBL_LVL_MAX; 3033 mr->qplib_mr.total_size = -1; /* Infinte length */ 3034 rc = bnxt_qplib_reg_mr(&rdev->qplib_res, &mr->qplib_mr, &pbl, 0, false); 3035 if (rc) 3036 goto fail_mr; 3037 3038 mr->ib_mr.lkey = mr->qplib_mr.lkey; 3039 if (mr_access_flags & (IB_ACCESS_REMOTE_WRITE | IB_ACCESS_REMOTE_READ | 3040 IB_ACCESS_REMOTE_ATOMIC)) 3041 mr->ib_mr.rkey = mr->ib_mr.lkey; 3042 atomic_inc(&rdev->mr_count); 3043 3044 return &mr->ib_mr; 3045 3046 fail_mr: 3047 bnxt_qplib_free_mrw(&rdev->qplib_res, &mr->qplib_mr); 3048 fail: 3049 kfree(mr); 3050 return ERR_PTR(rc); 3051 } 3052 3053 int bnxt_re_dereg_mr(struct ib_mr *ib_mr) 3054 { 3055 struct bnxt_re_mr *mr = container_of(ib_mr, struct bnxt_re_mr, ib_mr); 3056 struct bnxt_re_dev *rdev = mr->rdev; 3057 int rc; 3058 3059 rc = bnxt_qplib_free_mrw(&rdev->qplib_res, &mr->qplib_mr); 3060 if (rc) { 3061 dev_err(rdev_to_dev(rdev), "Dereg MR failed: %#x\n", rc); 3062 return rc; 3063 } 3064 3065 if (mr->npages && mr->pages) { 3066 rc = bnxt_qplib_free_fast_reg_page_list(&rdev->qplib_res, 3067 &mr->qplib_frpl); 3068 kfree(mr->pages); 3069 mr->npages = 0; 3070 mr->pages = NULL; 3071 } 3072 if (!IS_ERR_OR_NULL(mr->ib_umem)) 3073 ib_umem_release(mr->ib_umem); 3074 3075 kfree(mr); 3076 atomic_dec(&rdev->mr_count); 3077 return rc; 3078 } 3079 3080 static int bnxt_re_set_page(struct ib_mr *ib_mr, u64 addr) 3081 { 3082 struct bnxt_re_mr *mr = container_of(ib_mr, struct bnxt_re_mr, ib_mr); 3083 3084 if (unlikely(mr->npages == mr->qplib_frpl.max_pg_ptrs)) 3085 return -ENOMEM; 3086 3087 mr->pages[mr->npages++] = addr; 3088 return 0; 3089 } 3090 3091 int bnxt_re_map_mr_sg(struct ib_mr *ib_mr, struct scatterlist *sg, int sg_nents, 3092 unsigned int *sg_offset) 3093 { 3094 struct bnxt_re_mr *mr = container_of(ib_mr, struct bnxt_re_mr, ib_mr); 3095 3096 mr->npages = 0; 3097 return ib_sg_to_pages(ib_mr, sg, sg_nents, sg_offset, bnxt_re_set_page); 3098 } 3099 3100 struct ib_mr *bnxt_re_alloc_mr(struct ib_pd *ib_pd, enum ib_mr_type type, 3101 u32 max_num_sg) 3102 { 3103 struct bnxt_re_pd *pd = container_of(ib_pd, struct bnxt_re_pd, ib_pd); 3104 struct bnxt_re_dev *rdev = pd->rdev; 3105 struct bnxt_re_mr *mr = NULL; 3106 int rc; 3107 3108 if (type != IB_MR_TYPE_MEM_REG) { 3109 dev_dbg(rdev_to_dev(rdev), "MR type 0x%x not supported", type); 3110 return ERR_PTR(-EINVAL); 3111 } 3112 if (max_num_sg > MAX_PBL_LVL_1_PGS) 3113 return ERR_PTR(-EINVAL); 3114 3115 mr = kzalloc(sizeof(*mr), GFP_KERNEL); 3116 if (!mr) 3117 return ERR_PTR(-ENOMEM); 3118 3119 mr->rdev = rdev; 3120 mr->qplib_mr.pd = &pd->qplib_pd; 3121 mr->qplib_mr.flags = BNXT_QPLIB_FR_PMR; 3122 mr->qplib_mr.type = CMDQ_ALLOCATE_MRW_MRW_FLAGS_PMR; 3123 3124 rc = bnxt_qplib_alloc_mrw(&rdev->qplib_res, &mr->qplib_mr); 3125 if (rc) 3126 goto fail; 3127 3128 mr->ib_mr.lkey = mr->qplib_mr.lkey; 3129 mr->ib_mr.rkey = mr->ib_mr.lkey; 3130 3131 mr->pages = kcalloc(max_num_sg, sizeof(u64), GFP_KERNEL); 3132 if (!mr->pages) { 3133 rc = -ENOMEM; 3134 goto fail; 3135 } 3136 rc = bnxt_qplib_alloc_fast_reg_page_list(&rdev->qplib_res, 3137 &mr->qplib_frpl, max_num_sg); 3138 if (rc) { 3139 dev_err(rdev_to_dev(rdev), 3140 "Failed to allocate HW FR page list"); 3141 goto fail_mr; 3142 } 3143 3144 atomic_inc(&rdev->mr_count); 3145 return &mr->ib_mr; 3146 3147 fail_mr: 3148 bnxt_qplib_free_mrw(&rdev->qplib_res, &mr->qplib_mr); 3149 fail: 3150 kfree(mr->pages); 3151 kfree(mr); 3152 return ERR_PTR(rc); 3153 } 3154 3155 struct ib_mw *bnxt_re_alloc_mw(struct ib_pd *ib_pd, enum ib_mw_type type, 3156 struct ib_udata *udata) 3157 { 3158 struct bnxt_re_pd *pd = container_of(ib_pd, struct bnxt_re_pd, ib_pd); 3159 struct bnxt_re_dev *rdev = pd->rdev; 3160 struct bnxt_re_mw *mw; 3161 int rc; 3162 3163 mw = kzalloc(sizeof(*mw), GFP_KERNEL); 3164 if (!mw) 3165 return ERR_PTR(-ENOMEM); 3166 mw->rdev = rdev; 3167 mw->qplib_mw.pd = &pd->qplib_pd; 3168 3169 mw->qplib_mw.type = (type == IB_MW_TYPE_1 ? 3170 CMDQ_ALLOCATE_MRW_MRW_FLAGS_MW_TYPE1 : 3171 CMDQ_ALLOCATE_MRW_MRW_FLAGS_MW_TYPE2B); 3172 rc = bnxt_qplib_alloc_mrw(&rdev->qplib_res, &mw->qplib_mw); 3173 if (rc) { 3174 dev_err(rdev_to_dev(rdev), "Allocate MW failed!"); 3175 goto fail; 3176 } 3177 mw->ib_mw.rkey = mw->qplib_mw.rkey; 3178 3179 atomic_inc(&rdev->mw_count); 3180 return &mw->ib_mw; 3181 3182 fail: 3183 kfree(mw); 3184 return ERR_PTR(rc); 3185 } 3186 3187 int bnxt_re_dealloc_mw(struct ib_mw *ib_mw) 3188 { 3189 struct bnxt_re_mw *mw = container_of(ib_mw, struct bnxt_re_mw, ib_mw); 3190 struct bnxt_re_dev *rdev = mw->rdev; 3191 int rc; 3192 3193 rc = bnxt_qplib_free_mrw(&rdev->qplib_res, &mw->qplib_mw); 3194 if (rc) { 3195 dev_err(rdev_to_dev(rdev), "Free MW failed: %#x\n", rc); 3196 return rc; 3197 } 3198 3199 kfree(mw); 3200 atomic_dec(&rdev->mw_count); 3201 return rc; 3202 } 3203 3204 /* uverbs */ 3205 struct ib_mr *bnxt_re_reg_user_mr(struct ib_pd *ib_pd, u64 start, u64 length, 3206 u64 virt_addr, int mr_access_flags, 3207 struct ib_udata *udata) 3208 { 3209 struct bnxt_re_pd *pd = container_of(ib_pd, struct bnxt_re_pd, ib_pd); 3210 struct bnxt_re_dev *rdev = pd->rdev; 3211 struct bnxt_re_mr *mr; 3212 struct ib_umem *umem; 3213 u64 *pbl_tbl, *pbl_tbl_orig; 3214 int i, umem_pgs, pages, rc; 3215 struct scatterlist *sg; 3216 int entry; 3217 3218 if (length > BNXT_RE_MAX_MR_SIZE) { 3219 dev_err(rdev_to_dev(rdev), "MR Size: %lld > Max supported:%ld\n", 3220 length, BNXT_RE_MAX_MR_SIZE); 3221 return ERR_PTR(-ENOMEM); 3222 } 3223 3224 mr = kzalloc(sizeof(*mr), GFP_KERNEL); 3225 if (!mr) 3226 return ERR_PTR(-ENOMEM); 3227 3228 mr->rdev = rdev; 3229 mr->qplib_mr.pd = &pd->qplib_pd; 3230 mr->qplib_mr.flags = __from_ib_access_flags(mr_access_flags); 3231 mr->qplib_mr.type = CMDQ_ALLOCATE_MRW_MRW_FLAGS_MR; 3232 3233 umem = ib_umem_get(ib_pd->uobject->context, start, length, 3234 mr_access_flags, 0); 3235 if (IS_ERR(umem)) { 3236 dev_err(rdev_to_dev(rdev), "Failed to get umem"); 3237 rc = -EFAULT; 3238 goto free_mr; 3239 } 3240 mr->ib_umem = umem; 3241 3242 rc = bnxt_qplib_alloc_mrw(&rdev->qplib_res, &mr->qplib_mr); 3243 if (rc) { 3244 dev_err(rdev_to_dev(rdev), "Failed to allocate MR"); 3245 goto release_umem; 3246 } 3247 /* The fixed portion of the rkey is the same as the lkey */ 3248 mr->ib_mr.rkey = mr->qplib_mr.rkey; 3249 3250 mr->qplib_mr.va = virt_addr; 3251 umem_pgs = ib_umem_page_count(umem); 3252 if (!umem_pgs) { 3253 dev_err(rdev_to_dev(rdev), "umem is invalid!"); 3254 rc = -EINVAL; 3255 goto free_mrw; 3256 } 3257 mr->qplib_mr.total_size = length; 3258 3259 pbl_tbl = kcalloc(umem_pgs, sizeof(u64 *), GFP_KERNEL); 3260 if (!pbl_tbl) { 3261 rc = -EINVAL; 3262 goto free_mrw; 3263 } 3264 pbl_tbl_orig = pbl_tbl; 3265 3266 if (umem->hugetlb) { 3267 dev_err(rdev_to_dev(rdev), "umem hugetlb not supported!"); 3268 rc = -EFAULT; 3269 goto fail; 3270 } 3271 3272 if (umem->page_shift != PAGE_SHIFT) { 3273 dev_err(rdev_to_dev(rdev), "umem page shift unsupported!"); 3274 rc = -EFAULT; 3275 goto fail; 3276 } 3277 /* Map umem buf ptrs to the PBL */ 3278 for_each_sg(umem->sg_head.sgl, sg, umem->nmap, entry) { 3279 pages = sg_dma_len(sg) >> umem->page_shift; 3280 for (i = 0; i < pages; i++, pbl_tbl++) 3281 *pbl_tbl = sg_dma_address(sg) + (i << umem->page_shift); 3282 } 3283 rc = bnxt_qplib_reg_mr(&rdev->qplib_res, &mr->qplib_mr, pbl_tbl_orig, 3284 umem_pgs, false); 3285 if (rc) { 3286 dev_err(rdev_to_dev(rdev), "Failed to register user MR"); 3287 goto fail; 3288 } 3289 3290 kfree(pbl_tbl_orig); 3291 3292 mr->ib_mr.lkey = mr->qplib_mr.lkey; 3293 mr->ib_mr.rkey = mr->qplib_mr.lkey; 3294 atomic_inc(&rdev->mr_count); 3295 3296 return &mr->ib_mr; 3297 fail: 3298 kfree(pbl_tbl_orig); 3299 free_mrw: 3300 bnxt_qplib_free_mrw(&rdev->qplib_res, &mr->qplib_mr); 3301 release_umem: 3302 ib_umem_release(umem); 3303 free_mr: 3304 kfree(mr); 3305 return ERR_PTR(rc); 3306 } 3307 3308 struct ib_ucontext *bnxt_re_alloc_ucontext(struct ib_device *ibdev, 3309 struct ib_udata *udata) 3310 { 3311 struct bnxt_re_dev *rdev = to_bnxt_re_dev(ibdev, ibdev); 3312 struct bnxt_re_uctx_resp resp; 3313 struct bnxt_re_ucontext *uctx; 3314 struct bnxt_qplib_dev_attr *dev_attr = &rdev->dev_attr; 3315 int rc; 3316 3317 dev_dbg(rdev_to_dev(rdev), "ABI version requested %d", 3318 ibdev->uverbs_abi_ver); 3319 3320 if (ibdev->uverbs_abi_ver != BNXT_RE_ABI_VERSION) { 3321 dev_dbg(rdev_to_dev(rdev), " is different from the device %d ", 3322 BNXT_RE_ABI_VERSION); 3323 return ERR_PTR(-EPERM); 3324 } 3325 3326 uctx = kzalloc(sizeof(*uctx), GFP_KERNEL); 3327 if (!uctx) 3328 return ERR_PTR(-ENOMEM); 3329 3330 uctx->rdev = rdev; 3331 3332 uctx->shpg = (void *)__get_free_page(GFP_KERNEL); 3333 if (!uctx->shpg) { 3334 rc = -ENOMEM; 3335 goto fail; 3336 } 3337 spin_lock_init(&uctx->sh_lock); 3338 3339 resp.dev_id = rdev->en_dev->pdev->devfn; /*Temp, Use idr_alloc instead*/ 3340 resp.max_qp = rdev->qplib_ctx.qpc_count; 3341 resp.pg_size = PAGE_SIZE; 3342 resp.cqe_sz = sizeof(struct cq_base); 3343 resp.max_cqd = dev_attr->max_cq_wqes; 3344 resp.rsvd = 0; 3345 3346 rc = ib_copy_to_udata(udata, &resp, sizeof(resp)); 3347 if (rc) { 3348 dev_err(rdev_to_dev(rdev), "Failed to copy user context"); 3349 rc = -EFAULT; 3350 goto cfail; 3351 } 3352 3353 return &uctx->ib_uctx; 3354 cfail: 3355 free_page((unsigned long)uctx->shpg); 3356 uctx->shpg = NULL; 3357 fail: 3358 kfree(uctx); 3359 return ERR_PTR(rc); 3360 } 3361 3362 int bnxt_re_dealloc_ucontext(struct ib_ucontext *ib_uctx) 3363 { 3364 struct bnxt_re_ucontext *uctx = container_of(ib_uctx, 3365 struct bnxt_re_ucontext, 3366 ib_uctx); 3367 3368 struct bnxt_re_dev *rdev = uctx->rdev; 3369 int rc = 0; 3370 3371 if (uctx->shpg) 3372 free_page((unsigned long)uctx->shpg); 3373 3374 if (uctx->dpi.dbr) { 3375 /* Free DPI only if this is the first PD allocated by the 3376 * application and mark the context dpi as NULL 3377 */ 3378 rc = bnxt_qplib_dealloc_dpi(&rdev->qplib_res, 3379 &rdev->qplib_res.dpi_tbl, 3380 &uctx->dpi); 3381 if (rc) 3382 dev_err(rdev_to_dev(rdev), "Deallocate HW DPI failed!"); 3383 /* Don't fail, continue*/ 3384 uctx->dpi.dbr = NULL; 3385 } 3386 3387 kfree(uctx); 3388 return 0; 3389 } 3390 3391 /* Helper function to mmap the virtual memory from user app */ 3392 int bnxt_re_mmap(struct ib_ucontext *ib_uctx, struct vm_area_struct *vma) 3393 { 3394 struct bnxt_re_ucontext *uctx = container_of(ib_uctx, 3395 struct bnxt_re_ucontext, 3396 ib_uctx); 3397 struct bnxt_re_dev *rdev = uctx->rdev; 3398 u64 pfn; 3399 3400 if (vma->vm_end - vma->vm_start != PAGE_SIZE) 3401 return -EINVAL; 3402 3403 if (vma->vm_pgoff) { 3404 vma->vm_page_prot = pgprot_noncached(vma->vm_page_prot); 3405 if (io_remap_pfn_range(vma, vma->vm_start, vma->vm_pgoff, 3406 PAGE_SIZE, vma->vm_page_prot)) { 3407 dev_err(rdev_to_dev(rdev), "Failed to map DPI"); 3408 return -EAGAIN; 3409 } 3410 } else { 3411 pfn = virt_to_phys(uctx->shpg) >> PAGE_SHIFT; 3412 if (remap_pfn_range(vma, vma->vm_start, 3413 pfn, PAGE_SIZE, vma->vm_page_prot)) { 3414 dev_err(rdev_to_dev(rdev), 3415 "Failed to map shared page"); 3416 return -EAGAIN; 3417 } 3418 } 3419 3420 return 0; 3421 } 3422