1 /* 2 * Broadcom NetXtreme-E RoCE driver. 3 * 4 * Copyright (c) 2016 - 2017, Broadcom. All rights reserved. The term 5 * Broadcom refers to Broadcom Limited and/or its subsidiaries. 6 * 7 * This software is available to you under a choice of one of two 8 * licenses. You may choose to be licensed under the terms of the GNU 9 * General Public License (GPL) Version 2, available from the file 10 * COPYING in the main directory of this source tree, or the 11 * BSD license below: 12 * 13 * Redistribution and use in source and binary forms, with or without 14 * modification, are permitted provided that the following conditions 15 * are met: 16 * 17 * 1. Redistributions of source code must retain the above copyright 18 * notice, this list of conditions and the following disclaimer. 19 * 2. Redistributions in binary form must reproduce the above copyright 20 * notice, this list of conditions and the following disclaimer in 21 * the documentation and/or other materials provided with the 22 * distribution. 23 * 24 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' 25 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, 26 * THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR 27 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS 28 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 29 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 30 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR 31 * BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, 32 * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE 33 * OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN 34 * IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 35 * 36 * Description: IB Verbs interpreter 37 */ 38 39 #include <linux/interrupt.h> 40 #include <linux/types.h> 41 #include <linux/pci.h> 42 #include <linux/netdevice.h> 43 #include <linux/if_ether.h> 44 45 #include <rdma/ib_verbs.h> 46 #include <rdma/ib_user_verbs.h> 47 #include <rdma/ib_umem.h> 48 #include <rdma/ib_addr.h> 49 #include <rdma/ib_mad.h> 50 #include <rdma/ib_cache.h> 51 #include <rdma/uverbs_ioctl.h> 52 53 #include "bnxt_ulp.h" 54 55 #include "roce_hsi.h" 56 #include "qplib_res.h" 57 #include "qplib_sp.h" 58 #include "qplib_fp.h" 59 #include "qplib_rcfw.h" 60 61 #include "bnxt_re.h" 62 #include "ib_verbs.h" 63 #include <rdma/bnxt_re-abi.h> 64 65 static int __from_ib_access_flags(int iflags) 66 { 67 int qflags = 0; 68 69 if (iflags & IB_ACCESS_LOCAL_WRITE) 70 qflags |= BNXT_QPLIB_ACCESS_LOCAL_WRITE; 71 if (iflags & IB_ACCESS_REMOTE_READ) 72 qflags |= BNXT_QPLIB_ACCESS_REMOTE_READ; 73 if (iflags & IB_ACCESS_REMOTE_WRITE) 74 qflags |= BNXT_QPLIB_ACCESS_REMOTE_WRITE; 75 if (iflags & IB_ACCESS_REMOTE_ATOMIC) 76 qflags |= BNXT_QPLIB_ACCESS_REMOTE_ATOMIC; 77 if (iflags & IB_ACCESS_MW_BIND) 78 qflags |= BNXT_QPLIB_ACCESS_MW_BIND; 79 if (iflags & IB_ZERO_BASED) 80 qflags |= BNXT_QPLIB_ACCESS_ZERO_BASED; 81 if (iflags & IB_ACCESS_ON_DEMAND) 82 qflags |= BNXT_QPLIB_ACCESS_ON_DEMAND; 83 return qflags; 84 }; 85 86 static enum ib_access_flags __to_ib_access_flags(int qflags) 87 { 88 enum ib_access_flags iflags = 0; 89 90 if (qflags & BNXT_QPLIB_ACCESS_LOCAL_WRITE) 91 iflags |= IB_ACCESS_LOCAL_WRITE; 92 if (qflags & BNXT_QPLIB_ACCESS_REMOTE_WRITE) 93 iflags |= IB_ACCESS_REMOTE_WRITE; 94 if (qflags & BNXT_QPLIB_ACCESS_REMOTE_READ) 95 iflags |= IB_ACCESS_REMOTE_READ; 96 if (qflags & BNXT_QPLIB_ACCESS_REMOTE_ATOMIC) 97 iflags |= IB_ACCESS_REMOTE_ATOMIC; 98 if (qflags & BNXT_QPLIB_ACCESS_MW_BIND) 99 iflags |= IB_ACCESS_MW_BIND; 100 if (qflags & BNXT_QPLIB_ACCESS_ZERO_BASED) 101 iflags |= IB_ZERO_BASED; 102 if (qflags & BNXT_QPLIB_ACCESS_ON_DEMAND) 103 iflags |= IB_ACCESS_ON_DEMAND; 104 return iflags; 105 }; 106 107 static int bnxt_re_build_sgl(struct ib_sge *ib_sg_list, 108 struct bnxt_qplib_sge *sg_list, int num) 109 { 110 int i, total = 0; 111 112 for (i = 0; i < num; i++) { 113 sg_list[i].addr = ib_sg_list[i].addr; 114 sg_list[i].lkey = ib_sg_list[i].lkey; 115 sg_list[i].size = ib_sg_list[i].length; 116 total += sg_list[i].size; 117 } 118 return total; 119 } 120 121 /* Device */ 122 int bnxt_re_query_device(struct ib_device *ibdev, 123 struct ib_device_attr *ib_attr, 124 struct ib_udata *udata) 125 { 126 struct bnxt_re_dev *rdev = to_bnxt_re_dev(ibdev, ibdev); 127 struct bnxt_qplib_dev_attr *dev_attr = &rdev->dev_attr; 128 129 memset(ib_attr, 0, sizeof(*ib_attr)); 130 memcpy(&ib_attr->fw_ver, dev_attr->fw_ver, 131 min(sizeof(dev_attr->fw_ver), 132 sizeof(ib_attr->fw_ver))); 133 bnxt_qplib_get_guid(rdev->netdev->dev_addr, 134 (u8 *)&ib_attr->sys_image_guid); 135 ib_attr->max_mr_size = BNXT_RE_MAX_MR_SIZE; 136 ib_attr->page_size_cap = BNXT_RE_PAGE_SIZE_4K | BNXT_RE_PAGE_SIZE_2M; 137 138 ib_attr->vendor_id = rdev->en_dev->pdev->vendor; 139 ib_attr->vendor_part_id = rdev->en_dev->pdev->device; 140 ib_attr->hw_ver = rdev->en_dev->pdev->subsystem_device; 141 ib_attr->max_qp = dev_attr->max_qp; 142 ib_attr->max_qp_wr = dev_attr->max_qp_wqes; 143 ib_attr->device_cap_flags = 144 IB_DEVICE_CURR_QP_STATE_MOD 145 | IB_DEVICE_RC_RNR_NAK_GEN 146 | IB_DEVICE_SHUTDOWN_PORT 147 | IB_DEVICE_SYS_IMAGE_GUID 148 | IB_DEVICE_LOCAL_DMA_LKEY 149 | IB_DEVICE_RESIZE_MAX_WR 150 | IB_DEVICE_PORT_ACTIVE_EVENT 151 | IB_DEVICE_N_NOTIFY_CQ 152 | IB_DEVICE_MEM_WINDOW 153 | IB_DEVICE_MEM_WINDOW_TYPE_2B 154 | IB_DEVICE_MEM_MGT_EXTENSIONS; 155 ib_attr->max_send_sge = dev_attr->max_qp_sges; 156 ib_attr->max_recv_sge = dev_attr->max_qp_sges; 157 ib_attr->max_sge_rd = dev_attr->max_qp_sges; 158 ib_attr->max_cq = dev_attr->max_cq; 159 ib_attr->max_cqe = dev_attr->max_cq_wqes; 160 ib_attr->max_mr = dev_attr->max_mr; 161 ib_attr->max_pd = dev_attr->max_pd; 162 ib_attr->max_qp_rd_atom = dev_attr->max_qp_rd_atom; 163 ib_attr->max_qp_init_rd_atom = dev_attr->max_qp_init_rd_atom; 164 ib_attr->atomic_cap = IB_ATOMIC_NONE; 165 ib_attr->masked_atomic_cap = IB_ATOMIC_NONE; 166 167 ib_attr->max_ee_rd_atom = 0; 168 ib_attr->max_res_rd_atom = 0; 169 ib_attr->max_ee_init_rd_atom = 0; 170 ib_attr->max_ee = 0; 171 ib_attr->max_rdd = 0; 172 ib_attr->max_mw = dev_attr->max_mw; 173 ib_attr->max_raw_ipv6_qp = 0; 174 ib_attr->max_raw_ethy_qp = dev_attr->max_raw_ethy_qp; 175 ib_attr->max_mcast_grp = 0; 176 ib_attr->max_mcast_qp_attach = 0; 177 ib_attr->max_total_mcast_qp_attach = 0; 178 ib_attr->max_ah = dev_attr->max_ah; 179 180 ib_attr->max_fmr = 0; 181 ib_attr->max_map_per_fmr = 0; 182 183 ib_attr->max_srq = dev_attr->max_srq; 184 ib_attr->max_srq_wr = dev_attr->max_srq_wqes; 185 ib_attr->max_srq_sge = dev_attr->max_srq_sges; 186 187 ib_attr->max_fast_reg_page_list_len = MAX_PBL_LVL_1_PGS; 188 189 ib_attr->max_pkeys = 1; 190 ib_attr->local_ca_ack_delay = BNXT_RE_DEFAULT_ACK_DELAY; 191 return 0; 192 } 193 194 int bnxt_re_modify_device(struct ib_device *ibdev, 195 int device_modify_mask, 196 struct ib_device_modify *device_modify) 197 { 198 switch (device_modify_mask) { 199 case IB_DEVICE_MODIFY_SYS_IMAGE_GUID: 200 /* Modify the GUID requires the modification of the GID table */ 201 /* GUID should be made as READ-ONLY */ 202 break; 203 case IB_DEVICE_MODIFY_NODE_DESC: 204 /* Node Desc should be made as READ-ONLY */ 205 break; 206 default: 207 break; 208 } 209 return 0; 210 } 211 212 /* Port */ 213 int bnxt_re_query_port(struct ib_device *ibdev, u8 port_num, 214 struct ib_port_attr *port_attr) 215 { 216 struct bnxt_re_dev *rdev = to_bnxt_re_dev(ibdev, ibdev); 217 struct bnxt_qplib_dev_attr *dev_attr = &rdev->dev_attr; 218 219 memset(port_attr, 0, sizeof(*port_attr)); 220 221 if (netif_running(rdev->netdev) && netif_carrier_ok(rdev->netdev)) { 222 port_attr->state = IB_PORT_ACTIVE; 223 port_attr->phys_state = 5; 224 } else { 225 port_attr->state = IB_PORT_DOWN; 226 port_attr->phys_state = 3; 227 } 228 port_attr->max_mtu = IB_MTU_4096; 229 port_attr->active_mtu = iboe_get_mtu(rdev->netdev->mtu); 230 port_attr->gid_tbl_len = dev_attr->max_sgid; 231 port_attr->port_cap_flags = IB_PORT_CM_SUP | IB_PORT_REINIT_SUP | 232 IB_PORT_DEVICE_MGMT_SUP | 233 IB_PORT_VENDOR_CLASS_SUP; 234 port_attr->ip_gids = true; 235 236 port_attr->max_msg_sz = (u32)BNXT_RE_MAX_MR_SIZE_LOW; 237 port_attr->bad_pkey_cntr = 0; 238 port_attr->qkey_viol_cntr = 0; 239 port_attr->pkey_tbl_len = dev_attr->max_pkey; 240 port_attr->lid = 0; 241 port_attr->sm_lid = 0; 242 port_attr->lmc = 0; 243 port_attr->max_vl_num = 4; 244 port_attr->sm_sl = 0; 245 port_attr->subnet_timeout = 0; 246 port_attr->init_type_reply = 0; 247 port_attr->active_speed = rdev->active_speed; 248 port_attr->active_width = rdev->active_width; 249 250 return 0; 251 } 252 253 int bnxt_re_get_port_immutable(struct ib_device *ibdev, u8 port_num, 254 struct ib_port_immutable *immutable) 255 { 256 struct ib_port_attr port_attr; 257 258 if (bnxt_re_query_port(ibdev, port_num, &port_attr)) 259 return -EINVAL; 260 261 immutable->pkey_tbl_len = port_attr.pkey_tbl_len; 262 immutable->gid_tbl_len = port_attr.gid_tbl_len; 263 immutable->core_cap_flags = RDMA_CORE_PORT_IBA_ROCE; 264 immutable->core_cap_flags |= RDMA_CORE_CAP_PROT_ROCE_UDP_ENCAP; 265 immutable->max_mad_size = IB_MGMT_MAD_SIZE; 266 return 0; 267 } 268 269 void bnxt_re_query_fw_str(struct ib_device *ibdev, char *str) 270 { 271 struct bnxt_re_dev *rdev = to_bnxt_re_dev(ibdev, ibdev); 272 273 snprintf(str, IB_FW_VERSION_NAME_MAX, "%d.%d.%d.%d", 274 rdev->dev_attr.fw_ver[0], rdev->dev_attr.fw_ver[1], 275 rdev->dev_attr.fw_ver[2], rdev->dev_attr.fw_ver[3]); 276 } 277 278 int bnxt_re_query_pkey(struct ib_device *ibdev, u8 port_num, 279 u16 index, u16 *pkey) 280 { 281 struct bnxt_re_dev *rdev = to_bnxt_re_dev(ibdev, ibdev); 282 283 /* Ignore port_num */ 284 285 memset(pkey, 0, sizeof(*pkey)); 286 return bnxt_qplib_get_pkey(&rdev->qplib_res, 287 &rdev->qplib_res.pkey_tbl, index, pkey); 288 } 289 290 int bnxt_re_query_gid(struct ib_device *ibdev, u8 port_num, 291 int index, union ib_gid *gid) 292 { 293 struct bnxt_re_dev *rdev = to_bnxt_re_dev(ibdev, ibdev); 294 int rc = 0; 295 296 /* Ignore port_num */ 297 memset(gid, 0, sizeof(*gid)); 298 rc = bnxt_qplib_get_sgid(&rdev->qplib_res, 299 &rdev->qplib_res.sgid_tbl, index, 300 (struct bnxt_qplib_gid *)gid); 301 return rc; 302 } 303 304 int bnxt_re_del_gid(const struct ib_gid_attr *attr, void **context) 305 { 306 int rc = 0; 307 struct bnxt_re_gid_ctx *ctx, **ctx_tbl; 308 struct bnxt_re_dev *rdev = to_bnxt_re_dev(attr->device, ibdev); 309 struct bnxt_qplib_sgid_tbl *sgid_tbl = &rdev->qplib_res.sgid_tbl; 310 struct bnxt_qplib_gid *gid_to_del; 311 312 /* Delete the entry from the hardware */ 313 ctx = *context; 314 if (!ctx) 315 return -EINVAL; 316 317 if (sgid_tbl && sgid_tbl->active) { 318 if (ctx->idx >= sgid_tbl->max) 319 return -EINVAL; 320 gid_to_del = &sgid_tbl->tbl[ctx->idx]; 321 /* DEL_GID is called in WQ context(netdevice_event_work_handler) 322 * or via the ib_unregister_device path. In the former case QP1 323 * may not be destroyed yet, in which case just return as FW 324 * needs that entry to be present and will fail it's deletion. 325 * We could get invoked again after QP1 is destroyed OR get an 326 * ADD_GID call with a different GID value for the same index 327 * where we issue MODIFY_GID cmd to update the GID entry -- TBD 328 */ 329 if (ctx->idx == 0 && 330 rdma_link_local_addr((struct in6_addr *)gid_to_del) && 331 ctx->refcnt == 1 && rdev->qp1_sqp) { 332 dev_dbg(rdev_to_dev(rdev), 333 "Trying to delete GID0 while QP1 is alive\n"); 334 return -EFAULT; 335 } 336 ctx->refcnt--; 337 if (!ctx->refcnt) { 338 rc = bnxt_qplib_del_sgid(sgid_tbl, gid_to_del, true); 339 if (rc) { 340 dev_err(rdev_to_dev(rdev), 341 "Failed to remove GID: %#x", rc); 342 } else { 343 ctx_tbl = sgid_tbl->ctx; 344 ctx_tbl[ctx->idx] = NULL; 345 kfree(ctx); 346 } 347 } 348 } else { 349 return -EINVAL; 350 } 351 return rc; 352 } 353 354 int bnxt_re_add_gid(const struct ib_gid_attr *attr, void **context) 355 { 356 int rc; 357 u32 tbl_idx = 0; 358 u16 vlan_id = 0xFFFF; 359 struct bnxt_re_gid_ctx *ctx, **ctx_tbl; 360 struct bnxt_re_dev *rdev = to_bnxt_re_dev(attr->device, ibdev); 361 struct bnxt_qplib_sgid_tbl *sgid_tbl = &rdev->qplib_res.sgid_tbl; 362 363 rc = rdma_read_gid_l2_fields(attr, &vlan_id, NULL); 364 if (rc) 365 return rc; 366 367 rc = bnxt_qplib_add_sgid(sgid_tbl, (struct bnxt_qplib_gid *)&attr->gid, 368 rdev->qplib_res.netdev->dev_addr, 369 vlan_id, true, &tbl_idx); 370 if (rc == -EALREADY) { 371 ctx_tbl = sgid_tbl->ctx; 372 ctx_tbl[tbl_idx]->refcnt++; 373 *context = ctx_tbl[tbl_idx]; 374 return 0; 375 } 376 377 if (rc < 0) { 378 dev_err(rdev_to_dev(rdev), "Failed to add GID: %#x", rc); 379 return rc; 380 } 381 382 ctx = kmalloc(sizeof(*ctx), GFP_KERNEL); 383 if (!ctx) 384 return -ENOMEM; 385 ctx_tbl = sgid_tbl->ctx; 386 ctx->idx = tbl_idx; 387 ctx->refcnt = 1; 388 ctx_tbl[tbl_idx] = ctx; 389 *context = ctx; 390 391 return rc; 392 } 393 394 enum rdma_link_layer bnxt_re_get_link_layer(struct ib_device *ibdev, 395 u8 port_num) 396 { 397 return IB_LINK_LAYER_ETHERNET; 398 } 399 400 #define BNXT_RE_FENCE_PBL_SIZE DIV_ROUND_UP(BNXT_RE_FENCE_BYTES, PAGE_SIZE) 401 402 static void bnxt_re_create_fence_wqe(struct bnxt_re_pd *pd) 403 { 404 struct bnxt_re_fence_data *fence = &pd->fence; 405 struct ib_mr *ib_mr = &fence->mr->ib_mr; 406 struct bnxt_qplib_swqe *wqe = &fence->bind_wqe; 407 408 memset(wqe, 0, sizeof(*wqe)); 409 wqe->type = BNXT_QPLIB_SWQE_TYPE_BIND_MW; 410 wqe->wr_id = BNXT_QPLIB_FENCE_WRID; 411 wqe->flags |= BNXT_QPLIB_SWQE_FLAGS_SIGNAL_COMP; 412 wqe->flags |= BNXT_QPLIB_SWQE_FLAGS_UC_FENCE; 413 wqe->bind.zero_based = false; 414 wqe->bind.parent_l_key = ib_mr->lkey; 415 wqe->bind.va = (u64)(unsigned long)fence->va; 416 wqe->bind.length = fence->size; 417 wqe->bind.access_cntl = __from_ib_access_flags(IB_ACCESS_REMOTE_READ); 418 wqe->bind.mw_type = SQ_BIND_MW_TYPE_TYPE1; 419 420 /* Save the initial rkey in fence structure for now; 421 * wqe->bind.r_key will be set at (re)bind time. 422 */ 423 fence->bind_rkey = ib_inc_rkey(fence->mw->rkey); 424 } 425 426 static int bnxt_re_bind_fence_mw(struct bnxt_qplib_qp *qplib_qp) 427 { 428 struct bnxt_re_qp *qp = container_of(qplib_qp, struct bnxt_re_qp, 429 qplib_qp); 430 struct ib_pd *ib_pd = qp->ib_qp.pd; 431 struct bnxt_re_pd *pd = container_of(ib_pd, struct bnxt_re_pd, ib_pd); 432 struct bnxt_re_fence_data *fence = &pd->fence; 433 struct bnxt_qplib_swqe *fence_wqe = &fence->bind_wqe; 434 struct bnxt_qplib_swqe wqe; 435 int rc; 436 437 memcpy(&wqe, fence_wqe, sizeof(wqe)); 438 wqe.bind.r_key = fence->bind_rkey; 439 fence->bind_rkey = ib_inc_rkey(fence->bind_rkey); 440 441 dev_dbg(rdev_to_dev(qp->rdev), 442 "Posting bind fence-WQE: rkey: %#x QP: %d PD: %p\n", 443 wqe.bind.r_key, qp->qplib_qp.id, pd); 444 rc = bnxt_qplib_post_send(&qp->qplib_qp, &wqe); 445 if (rc) { 446 dev_err(rdev_to_dev(qp->rdev), "Failed to bind fence-WQE\n"); 447 return rc; 448 } 449 bnxt_qplib_post_send_db(&qp->qplib_qp); 450 451 return rc; 452 } 453 454 static void bnxt_re_destroy_fence_mr(struct bnxt_re_pd *pd) 455 { 456 struct bnxt_re_fence_data *fence = &pd->fence; 457 struct bnxt_re_dev *rdev = pd->rdev; 458 struct device *dev = &rdev->en_dev->pdev->dev; 459 struct bnxt_re_mr *mr = fence->mr; 460 461 if (fence->mw) { 462 bnxt_re_dealloc_mw(fence->mw); 463 fence->mw = NULL; 464 } 465 if (mr) { 466 if (mr->ib_mr.rkey) 467 bnxt_qplib_dereg_mrw(&rdev->qplib_res, &mr->qplib_mr, 468 true); 469 if (mr->ib_mr.lkey) 470 bnxt_qplib_free_mrw(&rdev->qplib_res, &mr->qplib_mr); 471 kfree(mr); 472 fence->mr = NULL; 473 } 474 if (fence->dma_addr) { 475 dma_unmap_single(dev, fence->dma_addr, BNXT_RE_FENCE_BYTES, 476 DMA_BIDIRECTIONAL); 477 fence->dma_addr = 0; 478 } 479 } 480 481 static int bnxt_re_create_fence_mr(struct bnxt_re_pd *pd) 482 { 483 int mr_access_flags = IB_ACCESS_LOCAL_WRITE | IB_ACCESS_MW_BIND; 484 struct bnxt_re_fence_data *fence = &pd->fence; 485 struct bnxt_re_dev *rdev = pd->rdev; 486 struct device *dev = &rdev->en_dev->pdev->dev; 487 struct bnxt_re_mr *mr = NULL; 488 dma_addr_t dma_addr = 0; 489 struct ib_mw *mw; 490 u64 pbl_tbl; 491 int rc; 492 493 dma_addr = dma_map_single(dev, fence->va, BNXT_RE_FENCE_BYTES, 494 DMA_BIDIRECTIONAL); 495 rc = dma_mapping_error(dev, dma_addr); 496 if (rc) { 497 dev_err(rdev_to_dev(rdev), "Failed to dma-map fence-MR-mem\n"); 498 rc = -EIO; 499 fence->dma_addr = 0; 500 goto fail; 501 } 502 fence->dma_addr = dma_addr; 503 504 /* Allocate a MR */ 505 mr = kzalloc(sizeof(*mr), GFP_KERNEL); 506 if (!mr) { 507 rc = -ENOMEM; 508 goto fail; 509 } 510 fence->mr = mr; 511 mr->rdev = rdev; 512 mr->qplib_mr.pd = &pd->qplib_pd; 513 mr->qplib_mr.type = CMDQ_ALLOCATE_MRW_MRW_FLAGS_PMR; 514 mr->qplib_mr.flags = __from_ib_access_flags(mr_access_flags); 515 rc = bnxt_qplib_alloc_mrw(&rdev->qplib_res, &mr->qplib_mr); 516 if (rc) { 517 dev_err(rdev_to_dev(rdev), "Failed to alloc fence-HW-MR\n"); 518 goto fail; 519 } 520 521 /* Register MR */ 522 mr->ib_mr.lkey = mr->qplib_mr.lkey; 523 mr->qplib_mr.va = (u64)(unsigned long)fence->va; 524 mr->qplib_mr.total_size = BNXT_RE_FENCE_BYTES; 525 pbl_tbl = dma_addr; 526 rc = bnxt_qplib_reg_mr(&rdev->qplib_res, &mr->qplib_mr, &pbl_tbl, 527 BNXT_RE_FENCE_PBL_SIZE, false, PAGE_SIZE); 528 if (rc) { 529 dev_err(rdev_to_dev(rdev), "Failed to register fence-MR\n"); 530 goto fail; 531 } 532 mr->ib_mr.rkey = mr->qplib_mr.rkey; 533 534 /* Create a fence MW only for kernel consumers */ 535 mw = bnxt_re_alloc_mw(&pd->ib_pd, IB_MW_TYPE_1, NULL); 536 if (IS_ERR(mw)) { 537 dev_err(rdev_to_dev(rdev), 538 "Failed to create fence-MW for PD: %p\n", pd); 539 rc = PTR_ERR(mw); 540 goto fail; 541 } 542 fence->mw = mw; 543 544 bnxt_re_create_fence_wqe(pd); 545 return 0; 546 547 fail: 548 bnxt_re_destroy_fence_mr(pd); 549 return rc; 550 } 551 552 /* Protection Domains */ 553 void bnxt_re_dealloc_pd(struct ib_pd *ib_pd, struct ib_udata *udata) 554 { 555 struct bnxt_re_pd *pd = container_of(ib_pd, struct bnxt_re_pd, ib_pd); 556 struct bnxt_re_dev *rdev = pd->rdev; 557 558 bnxt_re_destroy_fence_mr(pd); 559 560 if (pd->qplib_pd.id) 561 bnxt_qplib_dealloc_pd(&rdev->qplib_res, &rdev->qplib_res.pd_tbl, 562 &pd->qplib_pd); 563 } 564 565 int bnxt_re_alloc_pd(struct ib_pd *ibpd, struct ib_udata *udata) 566 { 567 struct ib_device *ibdev = ibpd->device; 568 struct bnxt_re_dev *rdev = to_bnxt_re_dev(ibdev, ibdev); 569 struct bnxt_re_ucontext *ucntx = rdma_udata_to_drv_context( 570 udata, struct bnxt_re_ucontext, ib_uctx); 571 struct bnxt_re_pd *pd = container_of(ibpd, struct bnxt_re_pd, ib_pd); 572 int rc; 573 574 pd->rdev = rdev; 575 if (bnxt_qplib_alloc_pd(&rdev->qplib_res.pd_tbl, &pd->qplib_pd)) { 576 dev_err(rdev_to_dev(rdev), "Failed to allocate HW PD"); 577 rc = -ENOMEM; 578 goto fail; 579 } 580 581 if (udata) { 582 struct bnxt_re_pd_resp resp; 583 584 if (!ucntx->dpi.dbr) { 585 /* Allocate DPI in alloc_pd to avoid failing of 586 * ibv_devinfo and family of application when DPIs 587 * are depleted. 588 */ 589 if (bnxt_qplib_alloc_dpi(&rdev->qplib_res.dpi_tbl, 590 &ucntx->dpi, ucntx)) { 591 rc = -ENOMEM; 592 goto dbfail; 593 } 594 } 595 596 resp.pdid = pd->qplib_pd.id; 597 /* Still allow mapping this DBR to the new user PD. */ 598 resp.dpi = ucntx->dpi.dpi; 599 resp.dbr = (u64)ucntx->dpi.umdbr; 600 601 rc = ib_copy_to_udata(udata, &resp, sizeof(resp)); 602 if (rc) { 603 dev_err(rdev_to_dev(rdev), 604 "Failed to copy user response\n"); 605 goto dbfail; 606 } 607 } 608 609 if (!udata) 610 if (bnxt_re_create_fence_mr(pd)) 611 dev_warn(rdev_to_dev(rdev), 612 "Failed to create Fence-MR\n"); 613 return 0; 614 dbfail: 615 bnxt_qplib_dealloc_pd(&rdev->qplib_res, &rdev->qplib_res.pd_tbl, 616 &pd->qplib_pd); 617 fail: 618 return rc; 619 } 620 621 /* Address Handles */ 622 void bnxt_re_destroy_ah(struct ib_ah *ib_ah, u32 flags) 623 { 624 struct bnxt_re_ah *ah = container_of(ib_ah, struct bnxt_re_ah, ib_ah); 625 struct bnxt_re_dev *rdev = ah->rdev; 626 627 bnxt_qplib_destroy_ah(&rdev->qplib_res, &ah->qplib_ah, 628 !(flags & RDMA_DESTROY_AH_SLEEPABLE)); 629 } 630 631 static u8 bnxt_re_stack_to_dev_nw_type(enum rdma_network_type ntype) 632 { 633 u8 nw_type; 634 635 switch (ntype) { 636 case RDMA_NETWORK_IPV4: 637 nw_type = CMDQ_CREATE_AH_TYPE_V2IPV4; 638 break; 639 case RDMA_NETWORK_IPV6: 640 nw_type = CMDQ_CREATE_AH_TYPE_V2IPV6; 641 break; 642 default: 643 nw_type = CMDQ_CREATE_AH_TYPE_V1; 644 break; 645 } 646 return nw_type; 647 } 648 649 int bnxt_re_create_ah(struct ib_ah *ib_ah, struct rdma_ah_attr *ah_attr, 650 u32 flags, struct ib_udata *udata) 651 { 652 struct ib_pd *ib_pd = ib_ah->pd; 653 struct bnxt_re_pd *pd = container_of(ib_pd, struct bnxt_re_pd, ib_pd); 654 const struct ib_global_route *grh = rdma_ah_read_grh(ah_attr); 655 struct bnxt_re_dev *rdev = pd->rdev; 656 const struct ib_gid_attr *sgid_attr; 657 struct bnxt_re_ah *ah = container_of(ib_ah, struct bnxt_re_ah, ib_ah); 658 u8 nw_type; 659 int rc; 660 661 if (!(rdma_ah_get_ah_flags(ah_attr) & IB_AH_GRH)) { 662 dev_err(rdev_to_dev(rdev), "Failed to alloc AH: GRH not set"); 663 return -EINVAL; 664 } 665 666 ah->rdev = rdev; 667 ah->qplib_ah.pd = &pd->qplib_pd; 668 669 /* Supply the configuration for the HW */ 670 memcpy(ah->qplib_ah.dgid.data, grh->dgid.raw, 671 sizeof(union ib_gid)); 672 /* 673 * If RoCE V2 is enabled, stack will have two entries for 674 * each GID entry. Avoiding this duplicte entry in HW. Dividing 675 * the GID index by 2 for RoCE V2 676 */ 677 ah->qplib_ah.sgid_index = grh->sgid_index / 2; 678 ah->qplib_ah.host_sgid_index = grh->sgid_index; 679 ah->qplib_ah.traffic_class = grh->traffic_class; 680 ah->qplib_ah.flow_label = grh->flow_label; 681 ah->qplib_ah.hop_limit = grh->hop_limit; 682 ah->qplib_ah.sl = rdma_ah_get_sl(ah_attr); 683 684 sgid_attr = grh->sgid_attr; 685 /* Get network header type for this GID */ 686 nw_type = rdma_gid_attr_network_type(sgid_attr); 687 ah->qplib_ah.nw_type = bnxt_re_stack_to_dev_nw_type(nw_type); 688 689 memcpy(ah->qplib_ah.dmac, ah_attr->roce.dmac, ETH_ALEN); 690 rc = bnxt_qplib_create_ah(&rdev->qplib_res, &ah->qplib_ah, 691 !(flags & RDMA_CREATE_AH_SLEEPABLE)); 692 if (rc) { 693 dev_err(rdev_to_dev(rdev), "Failed to allocate HW AH"); 694 return rc; 695 } 696 697 /* Write AVID to shared page. */ 698 if (udata) { 699 struct bnxt_re_ucontext *uctx = rdma_udata_to_drv_context( 700 udata, struct bnxt_re_ucontext, ib_uctx); 701 unsigned long flag; 702 u32 *wrptr; 703 704 spin_lock_irqsave(&uctx->sh_lock, flag); 705 wrptr = (u32 *)(uctx->shpg + BNXT_RE_AVID_OFFT); 706 *wrptr = ah->qplib_ah.id; 707 wmb(); /* make sure cache is updated. */ 708 spin_unlock_irqrestore(&uctx->sh_lock, flag); 709 } 710 711 return 0; 712 } 713 714 int bnxt_re_modify_ah(struct ib_ah *ib_ah, struct rdma_ah_attr *ah_attr) 715 { 716 return 0; 717 } 718 719 int bnxt_re_query_ah(struct ib_ah *ib_ah, struct rdma_ah_attr *ah_attr) 720 { 721 struct bnxt_re_ah *ah = container_of(ib_ah, struct bnxt_re_ah, ib_ah); 722 723 ah_attr->type = ib_ah->type; 724 rdma_ah_set_sl(ah_attr, ah->qplib_ah.sl); 725 memcpy(ah_attr->roce.dmac, ah->qplib_ah.dmac, ETH_ALEN); 726 rdma_ah_set_grh(ah_attr, NULL, 0, 727 ah->qplib_ah.host_sgid_index, 728 0, ah->qplib_ah.traffic_class); 729 rdma_ah_set_dgid_raw(ah_attr, ah->qplib_ah.dgid.data); 730 rdma_ah_set_port_num(ah_attr, 1); 731 rdma_ah_set_static_rate(ah_attr, 0); 732 return 0; 733 } 734 735 unsigned long bnxt_re_lock_cqs(struct bnxt_re_qp *qp) 736 __acquires(&qp->scq->cq_lock) __acquires(&qp->rcq->cq_lock) 737 { 738 unsigned long flags; 739 740 spin_lock_irqsave(&qp->scq->cq_lock, flags); 741 if (qp->rcq != qp->scq) 742 spin_lock(&qp->rcq->cq_lock); 743 else 744 __acquire(&qp->rcq->cq_lock); 745 746 return flags; 747 } 748 749 void bnxt_re_unlock_cqs(struct bnxt_re_qp *qp, 750 unsigned long flags) 751 __releases(&qp->scq->cq_lock) __releases(&qp->rcq->cq_lock) 752 { 753 if (qp->rcq != qp->scq) 754 spin_unlock(&qp->rcq->cq_lock); 755 else 756 __release(&qp->rcq->cq_lock); 757 spin_unlock_irqrestore(&qp->scq->cq_lock, flags); 758 } 759 760 /* Queue Pairs */ 761 int bnxt_re_destroy_qp(struct ib_qp *ib_qp, struct ib_udata *udata) 762 { 763 struct bnxt_re_qp *qp = container_of(ib_qp, struct bnxt_re_qp, ib_qp); 764 struct bnxt_re_dev *rdev = qp->rdev; 765 unsigned int flags; 766 int rc; 767 768 bnxt_qplib_flush_cqn_wq(&qp->qplib_qp); 769 rc = bnxt_qplib_destroy_qp(&rdev->qplib_res, &qp->qplib_qp); 770 if (rc) { 771 dev_err(rdev_to_dev(rdev), "Failed to destroy HW QP"); 772 return rc; 773 } 774 775 if (rdma_is_kernel_res(&qp->ib_qp.res)) { 776 flags = bnxt_re_lock_cqs(qp); 777 bnxt_qplib_clean_qp(&qp->qplib_qp); 778 bnxt_re_unlock_cqs(qp, flags); 779 } 780 781 bnxt_qplib_free_qp_res(&rdev->qplib_res, &qp->qplib_qp); 782 783 if (ib_qp->qp_type == IB_QPT_GSI && rdev->qp1_sqp) { 784 bnxt_qplib_destroy_ah(&rdev->qplib_res, &rdev->sqp_ah->qplib_ah, 785 false); 786 787 bnxt_qplib_clean_qp(&qp->qplib_qp); 788 rc = bnxt_qplib_destroy_qp(&rdev->qplib_res, 789 &rdev->qp1_sqp->qplib_qp); 790 if (rc) { 791 dev_err(rdev_to_dev(rdev), 792 "Failed to destroy Shadow QP"); 793 return rc; 794 } 795 bnxt_qplib_free_qp_res(&rdev->qplib_res, 796 &rdev->qp1_sqp->qplib_qp); 797 mutex_lock(&rdev->qp_lock); 798 list_del(&rdev->qp1_sqp->list); 799 atomic_dec(&rdev->qp_count); 800 mutex_unlock(&rdev->qp_lock); 801 802 kfree(rdev->sqp_ah); 803 kfree(rdev->qp1_sqp); 804 rdev->qp1_sqp = NULL; 805 rdev->sqp_ah = NULL; 806 } 807 808 if (!IS_ERR_OR_NULL(qp->rumem)) 809 ib_umem_release(qp->rumem); 810 if (!IS_ERR_OR_NULL(qp->sumem)) 811 ib_umem_release(qp->sumem); 812 813 mutex_lock(&rdev->qp_lock); 814 list_del(&qp->list); 815 atomic_dec(&rdev->qp_count); 816 mutex_unlock(&rdev->qp_lock); 817 kfree(qp); 818 return 0; 819 } 820 821 static u8 __from_ib_qp_type(enum ib_qp_type type) 822 { 823 switch (type) { 824 case IB_QPT_GSI: 825 return CMDQ_CREATE_QP1_TYPE_GSI; 826 case IB_QPT_RC: 827 return CMDQ_CREATE_QP_TYPE_RC; 828 case IB_QPT_UD: 829 return CMDQ_CREATE_QP_TYPE_UD; 830 default: 831 return IB_QPT_MAX; 832 } 833 } 834 835 static int bnxt_re_init_user_qp(struct bnxt_re_dev *rdev, struct bnxt_re_pd *pd, 836 struct bnxt_re_qp *qp, struct ib_udata *udata) 837 { 838 struct bnxt_re_qp_req ureq; 839 struct bnxt_qplib_qp *qplib_qp = &qp->qplib_qp; 840 struct ib_umem *umem; 841 int bytes = 0, psn_sz; 842 struct bnxt_re_ucontext *cntx = rdma_udata_to_drv_context( 843 udata, struct bnxt_re_ucontext, ib_uctx); 844 845 if (ib_copy_from_udata(&ureq, udata, sizeof(ureq))) 846 return -EFAULT; 847 848 bytes = (qplib_qp->sq.max_wqe * BNXT_QPLIB_MAX_SQE_ENTRY_SIZE); 849 /* Consider mapping PSN search memory only for RC QPs. */ 850 if (qplib_qp->type == CMDQ_CREATE_QP_TYPE_RC) { 851 psn_sz = bnxt_qplib_is_chip_gen_p5(&rdev->chip_ctx) ? 852 sizeof(struct sq_psn_search_ext) : 853 sizeof(struct sq_psn_search); 854 bytes += (qplib_qp->sq.max_wqe * psn_sz); 855 } 856 bytes = PAGE_ALIGN(bytes); 857 umem = ib_umem_get(udata, ureq.qpsva, bytes, IB_ACCESS_LOCAL_WRITE, 1); 858 if (IS_ERR(umem)) 859 return PTR_ERR(umem); 860 861 qp->sumem = umem; 862 qplib_qp->sq.sg_info.sglist = umem->sg_head.sgl; 863 qplib_qp->sq.sg_info.npages = ib_umem_num_pages(umem); 864 qplib_qp->sq.sg_info.nmap = umem->nmap; 865 qplib_qp->qp_handle = ureq.qp_handle; 866 867 if (!qp->qplib_qp.srq) { 868 bytes = (qplib_qp->rq.max_wqe * BNXT_QPLIB_MAX_RQE_ENTRY_SIZE); 869 bytes = PAGE_ALIGN(bytes); 870 umem = ib_umem_get(udata, ureq.qprva, bytes, 871 IB_ACCESS_LOCAL_WRITE, 1); 872 if (IS_ERR(umem)) 873 goto rqfail; 874 qp->rumem = umem; 875 qplib_qp->rq.sg_info.sglist = umem->sg_head.sgl; 876 qplib_qp->rq.sg_info.npages = ib_umem_num_pages(umem); 877 qplib_qp->rq.sg_info.nmap = umem->nmap; 878 } 879 880 qplib_qp->dpi = &cntx->dpi; 881 return 0; 882 rqfail: 883 ib_umem_release(qp->sumem); 884 qp->sumem = NULL; 885 memset(&qplib_qp->sq.sg_info, 0, sizeof(qplib_qp->sq.sg_info)); 886 887 return PTR_ERR(umem); 888 } 889 890 static struct bnxt_re_ah *bnxt_re_create_shadow_qp_ah 891 (struct bnxt_re_pd *pd, 892 struct bnxt_qplib_res *qp1_res, 893 struct bnxt_qplib_qp *qp1_qp) 894 { 895 struct bnxt_re_dev *rdev = pd->rdev; 896 struct bnxt_re_ah *ah; 897 union ib_gid sgid; 898 int rc; 899 900 ah = kzalloc(sizeof(*ah), GFP_KERNEL); 901 if (!ah) 902 return NULL; 903 904 ah->rdev = rdev; 905 ah->qplib_ah.pd = &pd->qplib_pd; 906 907 rc = bnxt_re_query_gid(&rdev->ibdev, 1, 0, &sgid); 908 if (rc) 909 goto fail; 910 911 /* supply the dgid data same as sgid */ 912 memcpy(ah->qplib_ah.dgid.data, &sgid.raw, 913 sizeof(union ib_gid)); 914 ah->qplib_ah.sgid_index = 0; 915 916 ah->qplib_ah.traffic_class = 0; 917 ah->qplib_ah.flow_label = 0; 918 ah->qplib_ah.hop_limit = 1; 919 ah->qplib_ah.sl = 0; 920 /* Have DMAC same as SMAC */ 921 ether_addr_copy(ah->qplib_ah.dmac, rdev->netdev->dev_addr); 922 923 rc = bnxt_qplib_create_ah(&rdev->qplib_res, &ah->qplib_ah, false); 924 if (rc) { 925 dev_err(rdev_to_dev(rdev), 926 "Failed to allocate HW AH for Shadow QP"); 927 goto fail; 928 } 929 930 return ah; 931 932 fail: 933 kfree(ah); 934 return NULL; 935 } 936 937 static struct bnxt_re_qp *bnxt_re_create_shadow_qp 938 (struct bnxt_re_pd *pd, 939 struct bnxt_qplib_res *qp1_res, 940 struct bnxt_qplib_qp *qp1_qp) 941 { 942 struct bnxt_re_dev *rdev = pd->rdev; 943 struct bnxt_re_qp *qp; 944 int rc; 945 946 qp = kzalloc(sizeof(*qp), GFP_KERNEL); 947 if (!qp) 948 return NULL; 949 950 qp->rdev = rdev; 951 952 /* Initialize the shadow QP structure from the QP1 values */ 953 ether_addr_copy(qp->qplib_qp.smac, rdev->netdev->dev_addr); 954 955 qp->qplib_qp.pd = &pd->qplib_pd; 956 qp->qplib_qp.qp_handle = (u64)(unsigned long)(&qp->qplib_qp); 957 qp->qplib_qp.type = IB_QPT_UD; 958 959 qp->qplib_qp.max_inline_data = 0; 960 qp->qplib_qp.sig_type = true; 961 962 /* Shadow QP SQ depth should be same as QP1 RQ depth */ 963 qp->qplib_qp.sq.max_wqe = qp1_qp->rq.max_wqe; 964 qp->qplib_qp.sq.max_sge = 2; 965 /* Q full delta can be 1 since it is internal QP */ 966 qp->qplib_qp.sq.q_full_delta = 1; 967 968 qp->qplib_qp.scq = qp1_qp->scq; 969 qp->qplib_qp.rcq = qp1_qp->rcq; 970 971 qp->qplib_qp.rq.max_wqe = qp1_qp->rq.max_wqe; 972 qp->qplib_qp.rq.max_sge = qp1_qp->rq.max_sge; 973 /* Q full delta can be 1 since it is internal QP */ 974 qp->qplib_qp.rq.q_full_delta = 1; 975 976 qp->qplib_qp.mtu = qp1_qp->mtu; 977 978 qp->qplib_qp.sq_hdr_buf_size = 0; 979 qp->qplib_qp.rq_hdr_buf_size = BNXT_QPLIB_MAX_GRH_HDR_SIZE_IPV6; 980 qp->qplib_qp.dpi = &rdev->dpi_privileged; 981 982 rc = bnxt_qplib_create_qp(qp1_res, &qp->qplib_qp); 983 if (rc) 984 goto fail; 985 986 rdev->sqp_id = qp->qplib_qp.id; 987 988 spin_lock_init(&qp->sq_lock); 989 INIT_LIST_HEAD(&qp->list); 990 mutex_lock(&rdev->qp_lock); 991 list_add_tail(&qp->list, &rdev->qp_list); 992 atomic_inc(&rdev->qp_count); 993 mutex_unlock(&rdev->qp_lock); 994 return qp; 995 fail: 996 kfree(qp); 997 return NULL; 998 } 999 1000 struct ib_qp *bnxt_re_create_qp(struct ib_pd *ib_pd, 1001 struct ib_qp_init_attr *qp_init_attr, 1002 struct ib_udata *udata) 1003 { 1004 struct bnxt_re_pd *pd = container_of(ib_pd, struct bnxt_re_pd, ib_pd); 1005 struct bnxt_re_dev *rdev = pd->rdev; 1006 struct bnxt_qplib_dev_attr *dev_attr = &rdev->dev_attr; 1007 struct bnxt_re_qp *qp; 1008 struct bnxt_re_cq *cq; 1009 struct bnxt_re_srq *srq; 1010 int rc, entries; 1011 1012 if ((qp_init_attr->cap.max_send_wr > dev_attr->max_qp_wqes) || 1013 (qp_init_attr->cap.max_recv_wr > dev_attr->max_qp_wqes) || 1014 (qp_init_attr->cap.max_send_sge > dev_attr->max_qp_sges) || 1015 (qp_init_attr->cap.max_recv_sge > dev_attr->max_qp_sges) || 1016 (qp_init_attr->cap.max_inline_data > dev_attr->max_inline_data)) 1017 return ERR_PTR(-EINVAL); 1018 1019 qp = kzalloc(sizeof(*qp), GFP_KERNEL); 1020 if (!qp) 1021 return ERR_PTR(-ENOMEM); 1022 1023 qp->rdev = rdev; 1024 ether_addr_copy(qp->qplib_qp.smac, rdev->netdev->dev_addr); 1025 qp->qplib_qp.pd = &pd->qplib_pd; 1026 qp->qplib_qp.qp_handle = (u64)(unsigned long)(&qp->qplib_qp); 1027 qp->qplib_qp.type = __from_ib_qp_type(qp_init_attr->qp_type); 1028 1029 if (qp_init_attr->qp_type == IB_QPT_GSI && 1030 bnxt_qplib_is_chip_gen_p5(&rdev->chip_ctx)) 1031 qp->qplib_qp.type = CMDQ_CREATE_QP_TYPE_GSI; 1032 if (qp->qplib_qp.type == IB_QPT_MAX) { 1033 dev_err(rdev_to_dev(rdev), "QP type 0x%x not supported", 1034 qp->qplib_qp.type); 1035 rc = -EINVAL; 1036 goto fail; 1037 } 1038 1039 qp->qplib_qp.max_inline_data = qp_init_attr->cap.max_inline_data; 1040 qp->qplib_qp.sig_type = ((qp_init_attr->sq_sig_type == 1041 IB_SIGNAL_ALL_WR) ? true : false); 1042 1043 qp->qplib_qp.sq.max_sge = qp_init_attr->cap.max_send_sge; 1044 if (qp->qplib_qp.sq.max_sge > dev_attr->max_qp_sges) 1045 qp->qplib_qp.sq.max_sge = dev_attr->max_qp_sges; 1046 1047 if (qp_init_attr->send_cq) { 1048 cq = container_of(qp_init_attr->send_cq, struct bnxt_re_cq, 1049 ib_cq); 1050 if (!cq) { 1051 dev_err(rdev_to_dev(rdev), "Send CQ not found"); 1052 rc = -EINVAL; 1053 goto fail; 1054 } 1055 qp->qplib_qp.scq = &cq->qplib_cq; 1056 qp->scq = cq; 1057 } 1058 1059 if (qp_init_attr->recv_cq) { 1060 cq = container_of(qp_init_attr->recv_cq, struct bnxt_re_cq, 1061 ib_cq); 1062 if (!cq) { 1063 dev_err(rdev_to_dev(rdev), "Receive CQ not found"); 1064 rc = -EINVAL; 1065 goto fail; 1066 } 1067 qp->qplib_qp.rcq = &cq->qplib_cq; 1068 qp->rcq = cq; 1069 } 1070 1071 if (qp_init_attr->srq) { 1072 srq = container_of(qp_init_attr->srq, struct bnxt_re_srq, 1073 ib_srq); 1074 if (!srq) { 1075 dev_err(rdev_to_dev(rdev), "SRQ not found"); 1076 rc = -EINVAL; 1077 goto fail; 1078 } 1079 qp->qplib_qp.srq = &srq->qplib_srq; 1080 qp->qplib_qp.rq.max_wqe = 0; 1081 } else { 1082 /* Allocate 1 more than what's provided so posting max doesn't 1083 * mean empty 1084 */ 1085 entries = roundup_pow_of_two(qp_init_attr->cap.max_recv_wr + 1); 1086 qp->qplib_qp.rq.max_wqe = min_t(u32, entries, 1087 dev_attr->max_qp_wqes + 1); 1088 1089 qp->qplib_qp.rq.q_full_delta = qp->qplib_qp.rq.max_wqe - 1090 qp_init_attr->cap.max_recv_wr; 1091 1092 qp->qplib_qp.rq.max_sge = qp_init_attr->cap.max_recv_sge; 1093 if (qp->qplib_qp.rq.max_sge > dev_attr->max_qp_sges) 1094 qp->qplib_qp.rq.max_sge = dev_attr->max_qp_sges; 1095 } 1096 1097 qp->qplib_qp.mtu = ib_mtu_enum_to_int(iboe_get_mtu(rdev->netdev->mtu)); 1098 1099 if (qp_init_attr->qp_type == IB_QPT_GSI && 1100 !(bnxt_qplib_is_chip_gen_p5(&rdev->chip_ctx))) { 1101 /* Allocate 1 more than what's provided */ 1102 entries = roundup_pow_of_two(qp_init_attr->cap.max_send_wr + 1); 1103 qp->qplib_qp.sq.max_wqe = min_t(u32, entries, 1104 dev_attr->max_qp_wqes + 1); 1105 qp->qplib_qp.sq.q_full_delta = qp->qplib_qp.sq.max_wqe - 1106 qp_init_attr->cap.max_send_wr; 1107 qp->qplib_qp.rq.max_sge = dev_attr->max_qp_sges; 1108 if (qp->qplib_qp.rq.max_sge > dev_attr->max_qp_sges) 1109 qp->qplib_qp.rq.max_sge = dev_attr->max_qp_sges; 1110 qp->qplib_qp.sq.max_sge++; 1111 if (qp->qplib_qp.sq.max_sge > dev_attr->max_qp_sges) 1112 qp->qplib_qp.sq.max_sge = dev_attr->max_qp_sges; 1113 1114 qp->qplib_qp.rq_hdr_buf_size = 1115 BNXT_QPLIB_MAX_QP1_RQ_HDR_SIZE_V2; 1116 1117 qp->qplib_qp.sq_hdr_buf_size = 1118 BNXT_QPLIB_MAX_QP1_SQ_HDR_SIZE_V2; 1119 qp->qplib_qp.dpi = &rdev->dpi_privileged; 1120 rc = bnxt_qplib_create_qp1(&rdev->qplib_res, &qp->qplib_qp); 1121 if (rc) { 1122 dev_err(rdev_to_dev(rdev), "Failed to create HW QP1"); 1123 goto fail; 1124 } 1125 /* Create a shadow QP to handle the QP1 traffic */ 1126 rdev->qp1_sqp = bnxt_re_create_shadow_qp(pd, &rdev->qplib_res, 1127 &qp->qplib_qp); 1128 if (!rdev->qp1_sqp) { 1129 rc = -EINVAL; 1130 dev_err(rdev_to_dev(rdev), 1131 "Failed to create Shadow QP for QP1"); 1132 goto qp_destroy; 1133 } 1134 rdev->sqp_ah = bnxt_re_create_shadow_qp_ah(pd, &rdev->qplib_res, 1135 &qp->qplib_qp); 1136 if (!rdev->sqp_ah) { 1137 bnxt_qplib_destroy_qp(&rdev->qplib_res, 1138 &rdev->qp1_sqp->qplib_qp); 1139 rc = -EINVAL; 1140 dev_err(rdev_to_dev(rdev), 1141 "Failed to create AH entry for ShadowQP"); 1142 goto qp_destroy; 1143 } 1144 1145 } else { 1146 /* Allocate 128 + 1 more than what's provided */ 1147 entries = roundup_pow_of_two(qp_init_attr->cap.max_send_wr + 1148 BNXT_QPLIB_RESERVED_QP_WRS + 1); 1149 qp->qplib_qp.sq.max_wqe = min_t(u32, entries, 1150 dev_attr->max_qp_wqes + 1151 BNXT_QPLIB_RESERVED_QP_WRS + 1); 1152 qp->qplib_qp.sq.q_full_delta = BNXT_QPLIB_RESERVED_QP_WRS + 1; 1153 1154 /* 1155 * Reserving one slot for Phantom WQE. Application can 1156 * post one extra entry in this case. But allowing this to avoid 1157 * unexpected Queue full condition 1158 */ 1159 1160 qp->qplib_qp.sq.q_full_delta -= 1; 1161 1162 qp->qplib_qp.max_rd_atomic = dev_attr->max_qp_rd_atom; 1163 qp->qplib_qp.max_dest_rd_atomic = dev_attr->max_qp_init_rd_atom; 1164 if (udata) { 1165 rc = bnxt_re_init_user_qp(rdev, pd, qp, udata); 1166 if (rc) 1167 goto fail; 1168 } else { 1169 qp->qplib_qp.dpi = &rdev->dpi_privileged; 1170 } 1171 1172 rc = bnxt_qplib_create_qp(&rdev->qplib_res, &qp->qplib_qp); 1173 if (rc) { 1174 dev_err(rdev_to_dev(rdev), "Failed to create HW QP"); 1175 goto free_umem; 1176 } 1177 } 1178 1179 qp->ib_qp.qp_num = qp->qplib_qp.id; 1180 spin_lock_init(&qp->sq_lock); 1181 spin_lock_init(&qp->rq_lock); 1182 1183 if (udata) { 1184 struct bnxt_re_qp_resp resp; 1185 1186 resp.qpid = qp->ib_qp.qp_num; 1187 resp.rsvd = 0; 1188 rc = ib_copy_to_udata(udata, &resp, sizeof(resp)); 1189 if (rc) { 1190 dev_err(rdev_to_dev(rdev), "Failed to copy QP udata"); 1191 goto qp_destroy; 1192 } 1193 } 1194 INIT_LIST_HEAD(&qp->list); 1195 mutex_lock(&rdev->qp_lock); 1196 list_add_tail(&qp->list, &rdev->qp_list); 1197 atomic_inc(&rdev->qp_count); 1198 mutex_unlock(&rdev->qp_lock); 1199 1200 return &qp->ib_qp; 1201 qp_destroy: 1202 bnxt_qplib_destroy_qp(&rdev->qplib_res, &qp->qplib_qp); 1203 free_umem: 1204 if (udata) { 1205 if (qp->rumem) 1206 ib_umem_release(qp->rumem); 1207 if (qp->sumem) 1208 ib_umem_release(qp->sumem); 1209 } 1210 fail: 1211 kfree(qp); 1212 return ERR_PTR(rc); 1213 } 1214 1215 static u8 __from_ib_qp_state(enum ib_qp_state state) 1216 { 1217 switch (state) { 1218 case IB_QPS_RESET: 1219 return CMDQ_MODIFY_QP_NEW_STATE_RESET; 1220 case IB_QPS_INIT: 1221 return CMDQ_MODIFY_QP_NEW_STATE_INIT; 1222 case IB_QPS_RTR: 1223 return CMDQ_MODIFY_QP_NEW_STATE_RTR; 1224 case IB_QPS_RTS: 1225 return CMDQ_MODIFY_QP_NEW_STATE_RTS; 1226 case IB_QPS_SQD: 1227 return CMDQ_MODIFY_QP_NEW_STATE_SQD; 1228 case IB_QPS_SQE: 1229 return CMDQ_MODIFY_QP_NEW_STATE_SQE; 1230 case IB_QPS_ERR: 1231 default: 1232 return CMDQ_MODIFY_QP_NEW_STATE_ERR; 1233 } 1234 } 1235 1236 static enum ib_qp_state __to_ib_qp_state(u8 state) 1237 { 1238 switch (state) { 1239 case CMDQ_MODIFY_QP_NEW_STATE_RESET: 1240 return IB_QPS_RESET; 1241 case CMDQ_MODIFY_QP_NEW_STATE_INIT: 1242 return IB_QPS_INIT; 1243 case CMDQ_MODIFY_QP_NEW_STATE_RTR: 1244 return IB_QPS_RTR; 1245 case CMDQ_MODIFY_QP_NEW_STATE_RTS: 1246 return IB_QPS_RTS; 1247 case CMDQ_MODIFY_QP_NEW_STATE_SQD: 1248 return IB_QPS_SQD; 1249 case CMDQ_MODIFY_QP_NEW_STATE_SQE: 1250 return IB_QPS_SQE; 1251 case CMDQ_MODIFY_QP_NEW_STATE_ERR: 1252 default: 1253 return IB_QPS_ERR; 1254 } 1255 } 1256 1257 static u32 __from_ib_mtu(enum ib_mtu mtu) 1258 { 1259 switch (mtu) { 1260 case IB_MTU_256: 1261 return CMDQ_MODIFY_QP_PATH_MTU_MTU_256; 1262 case IB_MTU_512: 1263 return CMDQ_MODIFY_QP_PATH_MTU_MTU_512; 1264 case IB_MTU_1024: 1265 return CMDQ_MODIFY_QP_PATH_MTU_MTU_1024; 1266 case IB_MTU_2048: 1267 return CMDQ_MODIFY_QP_PATH_MTU_MTU_2048; 1268 case IB_MTU_4096: 1269 return CMDQ_MODIFY_QP_PATH_MTU_MTU_4096; 1270 default: 1271 return CMDQ_MODIFY_QP_PATH_MTU_MTU_2048; 1272 } 1273 } 1274 1275 static enum ib_mtu __to_ib_mtu(u32 mtu) 1276 { 1277 switch (mtu & CREQ_QUERY_QP_RESP_SB_PATH_MTU_MASK) { 1278 case CMDQ_MODIFY_QP_PATH_MTU_MTU_256: 1279 return IB_MTU_256; 1280 case CMDQ_MODIFY_QP_PATH_MTU_MTU_512: 1281 return IB_MTU_512; 1282 case CMDQ_MODIFY_QP_PATH_MTU_MTU_1024: 1283 return IB_MTU_1024; 1284 case CMDQ_MODIFY_QP_PATH_MTU_MTU_2048: 1285 return IB_MTU_2048; 1286 case CMDQ_MODIFY_QP_PATH_MTU_MTU_4096: 1287 return IB_MTU_4096; 1288 default: 1289 return IB_MTU_2048; 1290 } 1291 } 1292 1293 /* Shared Receive Queues */ 1294 void bnxt_re_destroy_srq(struct ib_srq *ib_srq, struct ib_udata *udata) 1295 { 1296 struct bnxt_re_srq *srq = container_of(ib_srq, struct bnxt_re_srq, 1297 ib_srq); 1298 struct bnxt_re_dev *rdev = srq->rdev; 1299 struct bnxt_qplib_srq *qplib_srq = &srq->qplib_srq; 1300 struct bnxt_qplib_nq *nq = NULL; 1301 1302 if (qplib_srq->cq) 1303 nq = qplib_srq->cq->nq; 1304 bnxt_qplib_destroy_srq(&rdev->qplib_res, qplib_srq); 1305 if (srq->umem) 1306 ib_umem_release(srq->umem); 1307 atomic_dec(&rdev->srq_count); 1308 if (nq) 1309 nq->budget--; 1310 } 1311 1312 static int bnxt_re_init_user_srq(struct bnxt_re_dev *rdev, 1313 struct bnxt_re_pd *pd, 1314 struct bnxt_re_srq *srq, 1315 struct ib_udata *udata) 1316 { 1317 struct bnxt_re_srq_req ureq; 1318 struct bnxt_qplib_srq *qplib_srq = &srq->qplib_srq; 1319 struct ib_umem *umem; 1320 int bytes = 0; 1321 struct bnxt_re_ucontext *cntx = rdma_udata_to_drv_context( 1322 udata, struct bnxt_re_ucontext, ib_uctx); 1323 1324 if (ib_copy_from_udata(&ureq, udata, sizeof(ureq))) 1325 return -EFAULT; 1326 1327 bytes = (qplib_srq->max_wqe * BNXT_QPLIB_MAX_RQE_ENTRY_SIZE); 1328 bytes = PAGE_ALIGN(bytes); 1329 umem = ib_umem_get(udata, ureq.srqva, bytes, IB_ACCESS_LOCAL_WRITE, 1); 1330 if (IS_ERR(umem)) 1331 return PTR_ERR(umem); 1332 1333 srq->umem = umem; 1334 qplib_srq->sg_info.sglist = umem->sg_head.sgl; 1335 qplib_srq->sg_info.npages = ib_umem_num_pages(umem); 1336 qplib_srq->sg_info.nmap = umem->nmap; 1337 qplib_srq->srq_handle = ureq.srq_handle; 1338 qplib_srq->dpi = &cntx->dpi; 1339 1340 return 0; 1341 } 1342 1343 int bnxt_re_create_srq(struct ib_srq *ib_srq, 1344 struct ib_srq_init_attr *srq_init_attr, 1345 struct ib_udata *udata) 1346 { 1347 struct ib_pd *ib_pd = ib_srq->pd; 1348 struct bnxt_re_pd *pd = container_of(ib_pd, struct bnxt_re_pd, ib_pd); 1349 struct bnxt_re_dev *rdev = pd->rdev; 1350 struct bnxt_qplib_dev_attr *dev_attr = &rdev->dev_attr; 1351 struct bnxt_re_srq *srq = 1352 container_of(ib_srq, struct bnxt_re_srq, ib_srq); 1353 struct bnxt_qplib_nq *nq = NULL; 1354 int rc, entries; 1355 1356 if (srq_init_attr->attr.max_wr >= dev_attr->max_srq_wqes) { 1357 dev_err(rdev_to_dev(rdev), "Create CQ failed - max exceeded"); 1358 rc = -EINVAL; 1359 goto exit; 1360 } 1361 1362 if (srq_init_attr->srq_type != IB_SRQT_BASIC) { 1363 rc = -EOPNOTSUPP; 1364 goto exit; 1365 } 1366 1367 srq->rdev = rdev; 1368 srq->qplib_srq.pd = &pd->qplib_pd; 1369 srq->qplib_srq.dpi = &rdev->dpi_privileged; 1370 /* Allocate 1 more than what's provided so posting max doesn't 1371 * mean empty 1372 */ 1373 entries = roundup_pow_of_two(srq_init_attr->attr.max_wr + 1); 1374 if (entries > dev_attr->max_srq_wqes + 1) 1375 entries = dev_attr->max_srq_wqes + 1; 1376 1377 srq->qplib_srq.max_wqe = entries; 1378 srq->qplib_srq.max_sge = srq_init_attr->attr.max_sge; 1379 srq->qplib_srq.threshold = srq_init_attr->attr.srq_limit; 1380 srq->srq_limit = srq_init_attr->attr.srq_limit; 1381 srq->qplib_srq.eventq_hw_ring_id = rdev->nq[0].ring_id; 1382 nq = &rdev->nq[0]; 1383 1384 if (udata) { 1385 rc = bnxt_re_init_user_srq(rdev, pd, srq, udata); 1386 if (rc) 1387 goto fail; 1388 } 1389 1390 rc = bnxt_qplib_create_srq(&rdev->qplib_res, &srq->qplib_srq); 1391 if (rc) { 1392 dev_err(rdev_to_dev(rdev), "Create HW SRQ failed!"); 1393 goto fail; 1394 } 1395 1396 if (udata) { 1397 struct bnxt_re_srq_resp resp; 1398 1399 resp.srqid = srq->qplib_srq.id; 1400 rc = ib_copy_to_udata(udata, &resp, sizeof(resp)); 1401 if (rc) { 1402 dev_err(rdev_to_dev(rdev), "SRQ copy to udata failed!"); 1403 bnxt_qplib_destroy_srq(&rdev->qplib_res, 1404 &srq->qplib_srq); 1405 goto exit; 1406 } 1407 } 1408 if (nq) 1409 nq->budget++; 1410 atomic_inc(&rdev->srq_count); 1411 1412 return 0; 1413 1414 fail: 1415 if (srq->umem) 1416 ib_umem_release(srq->umem); 1417 exit: 1418 return rc; 1419 } 1420 1421 int bnxt_re_modify_srq(struct ib_srq *ib_srq, struct ib_srq_attr *srq_attr, 1422 enum ib_srq_attr_mask srq_attr_mask, 1423 struct ib_udata *udata) 1424 { 1425 struct bnxt_re_srq *srq = container_of(ib_srq, struct bnxt_re_srq, 1426 ib_srq); 1427 struct bnxt_re_dev *rdev = srq->rdev; 1428 int rc; 1429 1430 switch (srq_attr_mask) { 1431 case IB_SRQ_MAX_WR: 1432 /* SRQ resize is not supported */ 1433 break; 1434 case IB_SRQ_LIMIT: 1435 /* Change the SRQ threshold */ 1436 if (srq_attr->srq_limit > srq->qplib_srq.max_wqe) 1437 return -EINVAL; 1438 1439 srq->qplib_srq.threshold = srq_attr->srq_limit; 1440 rc = bnxt_qplib_modify_srq(&rdev->qplib_res, &srq->qplib_srq); 1441 if (rc) { 1442 dev_err(rdev_to_dev(rdev), "Modify HW SRQ failed!"); 1443 return rc; 1444 } 1445 /* On success, update the shadow */ 1446 srq->srq_limit = srq_attr->srq_limit; 1447 /* No need to Build and send response back to udata */ 1448 break; 1449 default: 1450 dev_err(rdev_to_dev(rdev), 1451 "Unsupported srq_attr_mask 0x%x", srq_attr_mask); 1452 return -EINVAL; 1453 } 1454 return 0; 1455 } 1456 1457 int bnxt_re_query_srq(struct ib_srq *ib_srq, struct ib_srq_attr *srq_attr) 1458 { 1459 struct bnxt_re_srq *srq = container_of(ib_srq, struct bnxt_re_srq, 1460 ib_srq); 1461 struct bnxt_re_srq tsrq; 1462 struct bnxt_re_dev *rdev = srq->rdev; 1463 int rc; 1464 1465 /* Get live SRQ attr */ 1466 tsrq.qplib_srq.id = srq->qplib_srq.id; 1467 rc = bnxt_qplib_query_srq(&rdev->qplib_res, &tsrq.qplib_srq); 1468 if (rc) { 1469 dev_err(rdev_to_dev(rdev), "Query HW SRQ failed!"); 1470 return rc; 1471 } 1472 srq_attr->max_wr = srq->qplib_srq.max_wqe; 1473 srq_attr->max_sge = srq->qplib_srq.max_sge; 1474 srq_attr->srq_limit = tsrq.qplib_srq.threshold; 1475 1476 return 0; 1477 } 1478 1479 int bnxt_re_post_srq_recv(struct ib_srq *ib_srq, const struct ib_recv_wr *wr, 1480 const struct ib_recv_wr **bad_wr) 1481 { 1482 struct bnxt_re_srq *srq = container_of(ib_srq, struct bnxt_re_srq, 1483 ib_srq); 1484 struct bnxt_qplib_swqe wqe; 1485 unsigned long flags; 1486 int rc = 0; 1487 1488 spin_lock_irqsave(&srq->lock, flags); 1489 while (wr) { 1490 /* Transcribe each ib_recv_wr to qplib_swqe */ 1491 wqe.num_sge = wr->num_sge; 1492 bnxt_re_build_sgl(wr->sg_list, wqe.sg_list, wr->num_sge); 1493 wqe.wr_id = wr->wr_id; 1494 wqe.type = BNXT_QPLIB_SWQE_TYPE_RECV; 1495 1496 rc = bnxt_qplib_post_srq_recv(&srq->qplib_srq, &wqe); 1497 if (rc) { 1498 *bad_wr = wr; 1499 break; 1500 } 1501 wr = wr->next; 1502 } 1503 spin_unlock_irqrestore(&srq->lock, flags); 1504 1505 return rc; 1506 } 1507 static int bnxt_re_modify_shadow_qp(struct bnxt_re_dev *rdev, 1508 struct bnxt_re_qp *qp1_qp, 1509 int qp_attr_mask) 1510 { 1511 struct bnxt_re_qp *qp = rdev->qp1_sqp; 1512 int rc = 0; 1513 1514 if (qp_attr_mask & IB_QP_STATE) { 1515 qp->qplib_qp.modify_flags |= CMDQ_MODIFY_QP_MODIFY_MASK_STATE; 1516 qp->qplib_qp.state = qp1_qp->qplib_qp.state; 1517 } 1518 if (qp_attr_mask & IB_QP_PKEY_INDEX) { 1519 qp->qplib_qp.modify_flags |= CMDQ_MODIFY_QP_MODIFY_MASK_PKEY; 1520 qp->qplib_qp.pkey_index = qp1_qp->qplib_qp.pkey_index; 1521 } 1522 1523 if (qp_attr_mask & IB_QP_QKEY) { 1524 qp->qplib_qp.modify_flags |= CMDQ_MODIFY_QP_MODIFY_MASK_QKEY; 1525 /* Using a Random QKEY */ 1526 qp->qplib_qp.qkey = 0x81818181; 1527 } 1528 if (qp_attr_mask & IB_QP_SQ_PSN) { 1529 qp->qplib_qp.modify_flags |= CMDQ_MODIFY_QP_MODIFY_MASK_SQ_PSN; 1530 qp->qplib_qp.sq.psn = qp1_qp->qplib_qp.sq.psn; 1531 } 1532 1533 rc = bnxt_qplib_modify_qp(&rdev->qplib_res, &qp->qplib_qp); 1534 if (rc) 1535 dev_err(rdev_to_dev(rdev), 1536 "Failed to modify Shadow QP for QP1"); 1537 return rc; 1538 } 1539 1540 int bnxt_re_modify_qp(struct ib_qp *ib_qp, struct ib_qp_attr *qp_attr, 1541 int qp_attr_mask, struct ib_udata *udata) 1542 { 1543 struct bnxt_re_qp *qp = container_of(ib_qp, struct bnxt_re_qp, ib_qp); 1544 struct bnxt_re_dev *rdev = qp->rdev; 1545 struct bnxt_qplib_dev_attr *dev_attr = &rdev->dev_attr; 1546 enum ib_qp_state curr_qp_state, new_qp_state; 1547 int rc, entries; 1548 unsigned int flags; 1549 u8 nw_type; 1550 1551 qp->qplib_qp.modify_flags = 0; 1552 if (qp_attr_mask & IB_QP_STATE) { 1553 curr_qp_state = __to_ib_qp_state(qp->qplib_qp.cur_qp_state); 1554 new_qp_state = qp_attr->qp_state; 1555 if (!ib_modify_qp_is_ok(curr_qp_state, new_qp_state, 1556 ib_qp->qp_type, qp_attr_mask)) { 1557 dev_err(rdev_to_dev(rdev), 1558 "Invalid attribute mask: %#x specified ", 1559 qp_attr_mask); 1560 dev_err(rdev_to_dev(rdev), 1561 "for qpn: %#x type: %#x", 1562 ib_qp->qp_num, ib_qp->qp_type); 1563 dev_err(rdev_to_dev(rdev), 1564 "curr_qp_state=0x%x, new_qp_state=0x%x\n", 1565 curr_qp_state, new_qp_state); 1566 return -EINVAL; 1567 } 1568 qp->qplib_qp.modify_flags |= CMDQ_MODIFY_QP_MODIFY_MASK_STATE; 1569 qp->qplib_qp.state = __from_ib_qp_state(qp_attr->qp_state); 1570 1571 if (!qp->sumem && 1572 qp->qplib_qp.state == CMDQ_MODIFY_QP_NEW_STATE_ERR) { 1573 dev_dbg(rdev_to_dev(rdev), 1574 "Move QP = %p to flush list\n", 1575 qp); 1576 flags = bnxt_re_lock_cqs(qp); 1577 bnxt_qplib_add_flush_qp(&qp->qplib_qp); 1578 bnxt_re_unlock_cqs(qp, flags); 1579 } 1580 if (!qp->sumem && 1581 qp->qplib_qp.state == CMDQ_MODIFY_QP_NEW_STATE_RESET) { 1582 dev_dbg(rdev_to_dev(rdev), 1583 "Move QP = %p out of flush list\n", 1584 qp); 1585 flags = bnxt_re_lock_cqs(qp); 1586 bnxt_qplib_clean_qp(&qp->qplib_qp); 1587 bnxt_re_unlock_cqs(qp, flags); 1588 } 1589 } 1590 if (qp_attr_mask & IB_QP_EN_SQD_ASYNC_NOTIFY) { 1591 qp->qplib_qp.modify_flags |= 1592 CMDQ_MODIFY_QP_MODIFY_MASK_EN_SQD_ASYNC_NOTIFY; 1593 qp->qplib_qp.en_sqd_async_notify = true; 1594 } 1595 if (qp_attr_mask & IB_QP_ACCESS_FLAGS) { 1596 qp->qplib_qp.modify_flags |= CMDQ_MODIFY_QP_MODIFY_MASK_ACCESS; 1597 qp->qplib_qp.access = 1598 __from_ib_access_flags(qp_attr->qp_access_flags); 1599 /* LOCAL_WRITE access must be set to allow RC receive */ 1600 qp->qplib_qp.access |= BNXT_QPLIB_ACCESS_LOCAL_WRITE; 1601 /* Temp: Set all params on QP as of now */ 1602 qp->qplib_qp.access |= CMDQ_MODIFY_QP_ACCESS_REMOTE_WRITE; 1603 qp->qplib_qp.access |= CMDQ_MODIFY_QP_ACCESS_REMOTE_READ; 1604 } 1605 if (qp_attr_mask & IB_QP_PKEY_INDEX) { 1606 qp->qplib_qp.modify_flags |= CMDQ_MODIFY_QP_MODIFY_MASK_PKEY; 1607 qp->qplib_qp.pkey_index = qp_attr->pkey_index; 1608 } 1609 if (qp_attr_mask & IB_QP_QKEY) { 1610 qp->qplib_qp.modify_flags |= CMDQ_MODIFY_QP_MODIFY_MASK_QKEY; 1611 qp->qplib_qp.qkey = qp_attr->qkey; 1612 } 1613 if (qp_attr_mask & IB_QP_AV) { 1614 const struct ib_global_route *grh = 1615 rdma_ah_read_grh(&qp_attr->ah_attr); 1616 const struct ib_gid_attr *sgid_attr; 1617 1618 qp->qplib_qp.modify_flags |= CMDQ_MODIFY_QP_MODIFY_MASK_DGID | 1619 CMDQ_MODIFY_QP_MODIFY_MASK_FLOW_LABEL | 1620 CMDQ_MODIFY_QP_MODIFY_MASK_SGID_INDEX | 1621 CMDQ_MODIFY_QP_MODIFY_MASK_HOP_LIMIT | 1622 CMDQ_MODIFY_QP_MODIFY_MASK_TRAFFIC_CLASS | 1623 CMDQ_MODIFY_QP_MODIFY_MASK_DEST_MAC | 1624 CMDQ_MODIFY_QP_MODIFY_MASK_VLAN_ID; 1625 memcpy(qp->qplib_qp.ah.dgid.data, grh->dgid.raw, 1626 sizeof(qp->qplib_qp.ah.dgid.data)); 1627 qp->qplib_qp.ah.flow_label = grh->flow_label; 1628 /* If RoCE V2 is enabled, stack will have two entries for 1629 * each GID entry. Avoiding this duplicte entry in HW. Dividing 1630 * the GID index by 2 for RoCE V2 1631 */ 1632 qp->qplib_qp.ah.sgid_index = grh->sgid_index / 2; 1633 qp->qplib_qp.ah.host_sgid_index = grh->sgid_index; 1634 qp->qplib_qp.ah.hop_limit = grh->hop_limit; 1635 qp->qplib_qp.ah.traffic_class = grh->traffic_class; 1636 qp->qplib_qp.ah.sl = rdma_ah_get_sl(&qp_attr->ah_attr); 1637 ether_addr_copy(qp->qplib_qp.ah.dmac, 1638 qp_attr->ah_attr.roce.dmac); 1639 1640 sgid_attr = qp_attr->ah_attr.grh.sgid_attr; 1641 rc = rdma_read_gid_l2_fields(sgid_attr, NULL, 1642 &qp->qplib_qp.smac[0]); 1643 if (rc) 1644 return rc; 1645 1646 nw_type = rdma_gid_attr_network_type(sgid_attr); 1647 switch (nw_type) { 1648 case RDMA_NETWORK_IPV4: 1649 qp->qplib_qp.nw_type = 1650 CMDQ_MODIFY_QP_NETWORK_TYPE_ROCEV2_IPV4; 1651 break; 1652 case RDMA_NETWORK_IPV6: 1653 qp->qplib_qp.nw_type = 1654 CMDQ_MODIFY_QP_NETWORK_TYPE_ROCEV2_IPV6; 1655 break; 1656 default: 1657 qp->qplib_qp.nw_type = 1658 CMDQ_MODIFY_QP_NETWORK_TYPE_ROCEV1; 1659 break; 1660 } 1661 } 1662 1663 if (qp_attr_mask & IB_QP_PATH_MTU) { 1664 qp->qplib_qp.modify_flags |= 1665 CMDQ_MODIFY_QP_MODIFY_MASK_PATH_MTU; 1666 qp->qplib_qp.path_mtu = __from_ib_mtu(qp_attr->path_mtu); 1667 qp->qplib_qp.mtu = ib_mtu_enum_to_int(qp_attr->path_mtu); 1668 } else if (qp_attr->qp_state == IB_QPS_RTR) { 1669 qp->qplib_qp.modify_flags |= 1670 CMDQ_MODIFY_QP_MODIFY_MASK_PATH_MTU; 1671 qp->qplib_qp.path_mtu = 1672 __from_ib_mtu(iboe_get_mtu(rdev->netdev->mtu)); 1673 qp->qplib_qp.mtu = 1674 ib_mtu_enum_to_int(iboe_get_mtu(rdev->netdev->mtu)); 1675 } 1676 1677 if (qp_attr_mask & IB_QP_TIMEOUT) { 1678 qp->qplib_qp.modify_flags |= CMDQ_MODIFY_QP_MODIFY_MASK_TIMEOUT; 1679 qp->qplib_qp.timeout = qp_attr->timeout; 1680 } 1681 if (qp_attr_mask & IB_QP_RETRY_CNT) { 1682 qp->qplib_qp.modify_flags |= 1683 CMDQ_MODIFY_QP_MODIFY_MASK_RETRY_CNT; 1684 qp->qplib_qp.retry_cnt = qp_attr->retry_cnt; 1685 } 1686 if (qp_attr_mask & IB_QP_RNR_RETRY) { 1687 qp->qplib_qp.modify_flags |= 1688 CMDQ_MODIFY_QP_MODIFY_MASK_RNR_RETRY; 1689 qp->qplib_qp.rnr_retry = qp_attr->rnr_retry; 1690 } 1691 if (qp_attr_mask & IB_QP_MIN_RNR_TIMER) { 1692 qp->qplib_qp.modify_flags |= 1693 CMDQ_MODIFY_QP_MODIFY_MASK_MIN_RNR_TIMER; 1694 qp->qplib_qp.min_rnr_timer = qp_attr->min_rnr_timer; 1695 } 1696 if (qp_attr_mask & IB_QP_RQ_PSN) { 1697 qp->qplib_qp.modify_flags |= CMDQ_MODIFY_QP_MODIFY_MASK_RQ_PSN; 1698 qp->qplib_qp.rq.psn = qp_attr->rq_psn; 1699 } 1700 if (qp_attr_mask & IB_QP_MAX_QP_RD_ATOMIC) { 1701 qp->qplib_qp.modify_flags |= 1702 CMDQ_MODIFY_QP_MODIFY_MASK_MAX_RD_ATOMIC; 1703 /* Cap the max_rd_atomic to device max */ 1704 qp->qplib_qp.max_rd_atomic = min_t(u32, qp_attr->max_rd_atomic, 1705 dev_attr->max_qp_rd_atom); 1706 } 1707 if (qp_attr_mask & IB_QP_SQ_PSN) { 1708 qp->qplib_qp.modify_flags |= CMDQ_MODIFY_QP_MODIFY_MASK_SQ_PSN; 1709 qp->qplib_qp.sq.psn = qp_attr->sq_psn; 1710 } 1711 if (qp_attr_mask & IB_QP_MAX_DEST_RD_ATOMIC) { 1712 if (qp_attr->max_dest_rd_atomic > 1713 dev_attr->max_qp_init_rd_atom) { 1714 dev_err(rdev_to_dev(rdev), 1715 "max_dest_rd_atomic requested%d is > dev_max%d", 1716 qp_attr->max_dest_rd_atomic, 1717 dev_attr->max_qp_init_rd_atom); 1718 return -EINVAL; 1719 } 1720 1721 qp->qplib_qp.modify_flags |= 1722 CMDQ_MODIFY_QP_MODIFY_MASK_MAX_DEST_RD_ATOMIC; 1723 qp->qplib_qp.max_dest_rd_atomic = qp_attr->max_dest_rd_atomic; 1724 } 1725 if (qp_attr_mask & IB_QP_CAP) { 1726 qp->qplib_qp.modify_flags |= 1727 CMDQ_MODIFY_QP_MODIFY_MASK_SQ_SIZE | 1728 CMDQ_MODIFY_QP_MODIFY_MASK_RQ_SIZE | 1729 CMDQ_MODIFY_QP_MODIFY_MASK_SQ_SGE | 1730 CMDQ_MODIFY_QP_MODIFY_MASK_RQ_SGE | 1731 CMDQ_MODIFY_QP_MODIFY_MASK_MAX_INLINE_DATA; 1732 if ((qp_attr->cap.max_send_wr >= dev_attr->max_qp_wqes) || 1733 (qp_attr->cap.max_recv_wr >= dev_attr->max_qp_wqes) || 1734 (qp_attr->cap.max_send_sge >= dev_attr->max_qp_sges) || 1735 (qp_attr->cap.max_recv_sge >= dev_attr->max_qp_sges) || 1736 (qp_attr->cap.max_inline_data >= 1737 dev_attr->max_inline_data)) { 1738 dev_err(rdev_to_dev(rdev), 1739 "Create QP failed - max exceeded"); 1740 return -EINVAL; 1741 } 1742 entries = roundup_pow_of_two(qp_attr->cap.max_send_wr); 1743 qp->qplib_qp.sq.max_wqe = min_t(u32, entries, 1744 dev_attr->max_qp_wqes + 1); 1745 qp->qplib_qp.sq.q_full_delta = qp->qplib_qp.sq.max_wqe - 1746 qp_attr->cap.max_send_wr; 1747 /* 1748 * Reserving one slot for Phantom WQE. Some application can 1749 * post one extra entry in this case. Allowing this to avoid 1750 * unexpected Queue full condition 1751 */ 1752 qp->qplib_qp.sq.q_full_delta -= 1; 1753 qp->qplib_qp.sq.max_sge = qp_attr->cap.max_send_sge; 1754 if (qp->qplib_qp.rq.max_wqe) { 1755 entries = roundup_pow_of_two(qp_attr->cap.max_recv_wr); 1756 qp->qplib_qp.rq.max_wqe = 1757 min_t(u32, entries, dev_attr->max_qp_wqes + 1); 1758 qp->qplib_qp.rq.q_full_delta = qp->qplib_qp.rq.max_wqe - 1759 qp_attr->cap.max_recv_wr; 1760 qp->qplib_qp.rq.max_sge = qp_attr->cap.max_recv_sge; 1761 } else { 1762 /* SRQ was used prior, just ignore the RQ caps */ 1763 } 1764 } 1765 if (qp_attr_mask & IB_QP_DEST_QPN) { 1766 qp->qplib_qp.modify_flags |= 1767 CMDQ_MODIFY_QP_MODIFY_MASK_DEST_QP_ID; 1768 qp->qplib_qp.dest_qpn = qp_attr->dest_qp_num; 1769 } 1770 rc = bnxt_qplib_modify_qp(&rdev->qplib_res, &qp->qplib_qp); 1771 if (rc) { 1772 dev_err(rdev_to_dev(rdev), "Failed to modify HW QP"); 1773 return rc; 1774 } 1775 if (ib_qp->qp_type == IB_QPT_GSI && rdev->qp1_sqp) 1776 rc = bnxt_re_modify_shadow_qp(rdev, qp, qp_attr_mask); 1777 return rc; 1778 } 1779 1780 int bnxt_re_query_qp(struct ib_qp *ib_qp, struct ib_qp_attr *qp_attr, 1781 int qp_attr_mask, struct ib_qp_init_attr *qp_init_attr) 1782 { 1783 struct bnxt_re_qp *qp = container_of(ib_qp, struct bnxt_re_qp, ib_qp); 1784 struct bnxt_re_dev *rdev = qp->rdev; 1785 struct bnxt_qplib_qp *qplib_qp; 1786 int rc; 1787 1788 qplib_qp = kzalloc(sizeof(*qplib_qp), GFP_KERNEL); 1789 if (!qplib_qp) 1790 return -ENOMEM; 1791 1792 qplib_qp->id = qp->qplib_qp.id; 1793 qplib_qp->ah.host_sgid_index = qp->qplib_qp.ah.host_sgid_index; 1794 1795 rc = bnxt_qplib_query_qp(&rdev->qplib_res, qplib_qp); 1796 if (rc) { 1797 dev_err(rdev_to_dev(rdev), "Failed to query HW QP"); 1798 goto out; 1799 } 1800 qp_attr->qp_state = __to_ib_qp_state(qplib_qp->state); 1801 qp_attr->en_sqd_async_notify = qplib_qp->en_sqd_async_notify ? 1 : 0; 1802 qp_attr->qp_access_flags = __to_ib_access_flags(qplib_qp->access); 1803 qp_attr->pkey_index = qplib_qp->pkey_index; 1804 qp_attr->qkey = qplib_qp->qkey; 1805 qp_attr->ah_attr.type = RDMA_AH_ATTR_TYPE_ROCE; 1806 rdma_ah_set_grh(&qp_attr->ah_attr, NULL, qplib_qp->ah.flow_label, 1807 qplib_qp->ah.host_sgid_index, 1808 qplib_qp->ah.hop_limit, 1809 qplib_qp->ah.traffic_class); 1810 rdma_ah_set_dgid_raw(&qp_attr->ah_attr, qplib_qp->ah.dgid.data); 1811 rdma_ah_set_sl(&qp_attr->ah_attr, qplib_qp->ah.sl); 1812 ether_addr_copy(qp_attr->ah_attr.roce.dmac, qplib_qp->ah.dmac); 1813 qp_attr->path_mtu = __to_ib_mtu(qplib_qp->path_mtu); 1814 qp_attr->timeout = qplib_qp->timeout; 1815 qp_attr->retry_cnt = qplib_qp->retry_cnt; 1816 qp_attr->rnr_retry = qplib_qp->rnr_retry; 1817 qp_attr->min_rnr_timer = qplib_qp->min_rnr_timer; 1818 qp_attr->rq_psn = qplib_qp->rq.psn; 1819 qp_attr->max_rd_atomic = qplib_qp->max_rd_atomic; 1820 qp_attr->sq_psn = qplib_qp->sq.psn; 1821 qp_attr->max_dest_rd_atomic = qplib_qp->max_dest_rd_atomic; 1822 qp_init_attr->sq_sig_type = qplib_qp->sig_type ? IB_SIGNAL_ALL_WR : 1823 IB_SIGNAL_REQ_WR; 1824 qp_attr->dest_qp_num = qplib_qp->dest_qpn; 1825 1826 qp_attr->cap.max_send_wr = qp->qplib_qp.sq.max_wqe; 1827 qp_attr->cap.max_send_sge = qp->qplib_qp.sq.max_sge; 1828 qp_attr->cap.max_recv_wr = qp->qplib_qp.rq.max_wqe; 1829 qp_attr->cap.max_recv_sge = qp->qplib_qp.rq.max_sge; 1830 qp_attr->cap.max_inline_data = qp->qplib_qp.max_inline_data; 1831 qp_init_attr->cap = qp_attr->cap; 1832 1833 out: 1834 kfree(qplib_qp); 1835 return rc; 1836 } 1837 1838 /* Routine for sending QP1 packets for RoCE V1 an V2 1839 */ 1840 static int bnxt_re_build_qp1_send_v2(struct bnxt_re_qp *qp, 1841 const struct ib_send_wr *wr, 1842 struct bnxt_qplib_swqe *wqe, 1843 int payload_size) 1844 { 1845 struct bnxt_re_ah *ah = container_of(ud_wr(wr)->ah, struct bnxt_re_ah, 1846 ib_ah); 1847 struct bnxt_qplib_ah *qplib_ah = &ah->qplib_ah; 1848 const struct ib_gid_attr *sgid_attr = ah->ib_ah.sgid_attr; 1849 struct bnxt_qplib_sge sge; 1850 u8 nw_type; 1851 u16 ether_type; 1852 union ib_gid dgid; 1853 bool is_eth = false; 1854 bool is_vlan = false; 1855 bool is_grh = false; 1856 bool is_udp = false; 1857 u8 ip_version = 0; 1858 u16 vlan_id = 0xFFFF; 1859 void *buf; 1860 int i, rc = 0; 1861 1862 memset(&qp->qp1_hdr, 0, sizeof(qp->qp1_hdr)); 1863 1864 rc = rdma_read_gid_l2_fields(sgid_attr, &vlan_id, NULL); 1865 if (rc) 1866 return rc; 1867 1868 /* Get network header type for this GID */ 1869 nw_type = rdma_gid_attr_network_type(sgid_attr); 1870 switch (nw_type) { 1871 case RDMA_NETWORK_IPV4: 1872 nw_type = BNXT_RE_ROCEV2_IPV4_PACKET; 1873 break; 1874 case RDMA_NETWORK_IPV6: 1875 nw_type = BNXT_RE_ROCEV2_IPV6_PACKET; 1876 break; 1877 default: 1878 nw_type = BNXT_RE_ROCE_V1_PACKET; 1879 break; 1880 } 1881 memcpy(&dgid.raw, &qplib_ah->dgid, 16); 1882 is_udp = sgid_attr->gid_type == IB_GID_TYPE_ROCE_UDP_ENCAP; 1883 if (is_udp) { 1884 if (ipv6_addr_v4mapped((struct in6_addr *)&sgid_attr->gid)) { 1885 ip_version = 4; 1886 ether_type = ETH_P_IP; 1887 } else { 1888 ip_version = 6; 1889 ether_type = ETH_P_IPV6; 1890 } 1891 is_grh = false; 1892 } else { 1893 ether_type = ETH_P_IBOE; 1894 is_grh = true; 1895 } 1896 1897 is_eth = true; 1898 is_vlan = (vlan_id && (vlan_id < 0x1000)) ? true : false; 1899 1900 ib_ud_header_init(payload_size, !is_eth, is_eth, is_vlan, is_grh, 1901 ip_version, is_udp, 0, &qp->qp1_hdr); 1902 1903 /* ETH */ 1904 ether_addr_copy(qp->qp1_hdr.eth.dmac_h, ah->qplib_ah.dmac); 1905 ether_addr_copy(qp->qp1_hdr.eth.smac_h, qp->qplib_qp.smac); 1906 1907 /* For vlan, check the sgid for vlan existence */ 1908 1909 if (!is_vlan) { 1910 qp->qp1_hdr.eth.type = cpu_to_be16(ether_type); 1911 } else { 1912 qp->qp1_hdr.vlan.type = cpu_to_be16(ether_type); 1913 qp->qp1_hdr.vlan.tag = cpu_to_be16(vlan_id); 1914 } 1915 1916 if (is_grh || (ip_version == 6)) { 1917 memcpy(qp->qp1_hdr.grh.source_gid.raw, sgid_attr->gid.raw, 1918 sizeof(sgid_attr->gid)); 1919 memcpy(qp->qp1_hdr.grh.destination_gid.raw, qplib_ah->dgid.data, 1920 sizeof(sgid_attr->gid)); 1921 qp->qp1_hdr.grh.hop_limit = qplib_ah->hop_limit; 1922 } 1923 1924 if (ip_version == 4) { 1925 qp->qp1_hdr.ip4.tos = 0; 1926 qp->qp1_hdr.ip4.id = 0; 1927 qp->qp1_hdr.ip4.frag_off = htons(IP_DF); 1928 qp->qp1_hdr.ip4.ttl = qplib_ah->hop_limit; 1929 1930 memcpy(&qp->qp1_hdr.ip4.saddr, sgid_attr->gid.raw + 12, 4); 1931 memcpy(&qp->qp1_hdr.ip4.daddr, qplib_ah->dgid.data + 12, 4); 1932 qp->qp1_hdr.ip4.check = ib_ud_ip4_csum(&qp->qp1_hdr); 1933 } 1934 1935 if (is_udp) { 1936 qp->qp1_hdr.udp.dport = htons(ROCE_V2_UDP_DPORT); 1937 qp->qp1_hdr.udp.sport = htons(0x8CD1); 1938 qp->qp1_hdr.udp.csum = 0; 1939 } 1940 1941 /* BTH */ 1942 if (wr->opcode == IB_WR_SEND_WITH_IMM) { 1943 qp->qp1_hdr.bth.opcode = IB_OPCODE_UD_SEND_ONLY_WITH_IMMEDIATE; 1944 qp->qp1_hdr.immediate_present = 1; 1945 } else { 1946 qp->qp1_hdr.bth.opcode = IB_OPCODE_UD_SEND_ONLY; 1947 } 1948 if (wr->send_flags & IB_SEND_SOLICITED) 1949 qp->qp1_hdr.bth.solicited_event = 1; 1950 /* pad_count */ 1951 qp->qp1_hdr.bth.pad_count = (4 - payload_size) & 3; 1952 1953 /* P_key for QP1 is for all members */ 1954 qp->qp1_hdr.bth.pkey = cpu_to_be16(0xFFFF); 1955 qp->qp1_hdr.bth.destination_qpn = IB_QP1; 1956 qp->qp1_hdr.bth.ack_req = 0; 1957 qp->send_psn++; 1958 qp->send_psn &= BTH_PSN_MASK; 1959 qp->qp1_hdr.bth.psn = cpu_to_be32(qp->send_psn); 1960 /* DETH */ 1961 /* Use the priviledged Q_Key for QP1 */ 1962 qp->qp1_hdr.deth.qkey = cpu_to_be32(IB_QP1_QKEY); 1963 qp->qp1_hdr.deth.source_qpn = IB_QP1; 1964 1965 /* Pack the QP1 to the transmit buffer */ 1966 buf = bnxt_qplib_get_qp1_sq_buf(&qp->qplib_qp, &sge); 1967 if (buf) { 1968 ib_ud_header_pack(&qp->qp1_hdr, buf); 1969 for (i = wqe->num_sge; i; i--) { 1970 wqe->sg_list[i].addr = wqe->sg_list[i - 1].addr; 1971 wqe->sg_list[i].lkey = wqe->sg_list[i - 1].lkey; 1972 wqe->sg_list[i].size = wqe->sg_list[i - 1].size; 1973 } 1974 1975 /* 1976 * Max Header buf size for IPV6 RoCE V2 is 86, 1977 * which is same as the QP1 SQ header buffer. 1978 * Header buf size for IPV4 RoCE V2 can be 66. 1979 * ETH(14) + VLAN(4)+ IP(20) + UDP (8) + BTH(20). 1980 * Subtract 20 bytes from QP1 SQ header buf size 1981 */ 1982 if (is_udp && ip_version == 4) 1983 sge.size -= 20; 1984 /* 1985 * Max Header buf size for RoCE V1 is 78. 1986 * ETH(14) + VLAN(4) + GRH(40) + BTH(20). 1987 * Subtract 8 bytes from QP1 SQ header buf size 1988 */ 1989 if (!is_udp) 1990 sge.size -= 8; 1991 1992 /* Subtract 4 bytes for non vlan packets */ 1993 if (!is_vlan) 1994 sge.size -= 4; 1995 1996 wqe->sg_list[0].addr = sge.addr; 1997 wqe->sg_list[0].lkey = sge.lkey; 1998 wqe->sg_list[0].size = sge.size; 1999 wqe->num_sge++; 2000 2001 } else { 2002 dev_err(rdev_to_dev(qp->rdev), "QP1 buffer is empty!"); 2003 rc = -ENOMEM; 2004 } 2005 return rc; 2006 } 2007 2008 /* For the MAD layer, it only provides the recv SGE the size of 2009 * ib_grh + MAD datagram. No Ethernet headers, Ethertype, BTH, DETH, 2010 * nor RoCE iCRC. The Cu+ solution must provide buffer for the entire 2011 * receive packet (334 bytes) with no VLAN and then copy the GRH 2012 * and the MAD datagram out to the provided SGE. 2013 */ 2014 static int bnxt_re_build_qp1_shadow_qp_recv(struct bnxt_re_qp *qp, 2015 const struct ib_recv_wr *wr, 2016 struct bnxt_qplib_swqe *wqe, 2017 int payload_size) 2018 { 2019 struct bnxt_qplib_sge ref, sge; 2020 u32 rq_prod_index; 2021 struct bnxt_re_sqp_entries *sqp_entry; 2022 2023 rq_prod_index = bnxt_qplib_get_rq_prod_index(&qp->qplib_qp); 2024 2025 if (!bnxt_qplib_get_qp1_rq_buf(&qp->qplib_qp, &sge)) 2026 return -ENOMEM; 2027 2028 /* Create 1 SGE to receive the entire 2029 * ethernet packet 2030 */ 2031 /* Save the reference from ULP */ 2032 ref.addr = wqe->sg_list[0].addr; 2033 ref.lkey = wqe->sg_list[0].lkey; 2034 ref.size = wqe->sg_list[0].size; 2035 2036 sqp_entry = &qp->rdev->sqp_tbl[rq_prod_index]; 2037 2038 /* SGE 1 */ 2039 wqe->sg_list[0].addr = sge.addr; 2040 wqe->sg_list[0].lkey = sge.lkey; 2041 wqe->sg_list[0].size = BNXT_QPLIB_MAX_QP1_RQ_HDR_SIZE_V2; 2042 sge.size -= wqe->sg_list[0].size; 2043 2044 sqp_entry->sge.addr = ref.addr; 2045 sqp_entry->sge.lkey = ref.lkey; 2046 sqp_entry->sge.size = ref.size; 2047 /* Store the wrid for reporting completion */ 2048 sqp_entry->wrid = wqe->wr_id; 2049 /* change the wqe->wrid to table index */ 2050 wqe->wr_id = rq_prod_index; 2051 return 0; 2052 } 2053 2054 static int is_ud_qp(struct bnxt_re_qp *qp) 2055 { 2056 return (qp->qplib_qp.type == CMDQ_CREATE_QP_TYPE_UD || 2057 qp->qplib_qp.type == CMDQ_CREATE_QP_TYPE_GSI); 2058 } 2059 2060 static int bnxt_re_build_send_wqe(struct bnxt_re_qp *qp, 2061 const struct ib_send_wr *wr, 2062 struct bnxt_qplib_swqe *wqe) 2063 { 2064 struct bnxt_re_ah *ah = NULL; 2065 2066 if (is_ud_qp(qp)) { 2067 ah = container_of(ud_wr(wr)->ah, struct bnxt_re_ah, ib_ah); 2068 wqe->send.q_key = ud_wr(wr)->remote_qkey; 2069 wqe->send.dst_qp = ud_wr(wr)->remote_qpn; 2070 wqe->send.avid = ah->qplib_ah.id; 2071 } 2072 switch (wr->opcode) { 2073 case IB_WR_SEND: 2074 wqe->type = BNXT_QPLIB_SWQE_TYPE_SEND; 2075 break; 2076 case IB_WR_SEND_WITH_IMM: 2077 wqe->type = BNXT_QPLIB_SWQE_TYPE_SEND_WITH_IMM; 2078 wqe->send.imm_data = wr->ex.imm_data; 2079 break; 2080 case IB_WR_SEND_WITH_INV: 2081 wqe->type = BNXT_QPLIB_SWQE_TYPE_SEND_WITH_INV; 2082 wqe->send.inv_key = wr->ex.invalidate_rkey; 2083 break; 2084 default: 2085 return -EINVAL; 2086 } 2087 if (wr->send_flags & IB_SEND_SIGNALED) 2088 wqe->flags |= BNXT_QPLIB_SWQE_FLAGS_SIGNAL_COMP; 2089 if (wr->send_flags & IB_SEND_FENCE) 2090 wqe->flags |= BNXT_QPLIB_SWQE_FLAGS_UC_FENCE; 2091 if (wr->send_flags & IB_SEND_SOLICITED) 2092 wqe->flags |= BNXT_QPLIB_SWQE_FLAGS_SOLICIT_EVENT; 2093 if (wr->send_flags & IB_SEND_INLINE) 2094 wqe->flags |= BNXT_QPLIB_SWQE_FLAGS_INLINE; 2095 2096 return 0; 2097 } 2098 2099 static int bnxt_re_build_rdma_wqe(const struct ib_send_wr *wr, 2100 struct bnxt_qplib_swqe *wqe) 2101 { 2102 switch (wr->opcode) { 2103 case IB_WR_RDMA_WRITE: 2104 wqe->type = BNXT_QPLIB_SWQE_TYPE_RDMA_WRITE; 2105 break; 2106 case IB_WR_RDMA_WRITE_WITH_IMM: 2107 wqe->type = BNXT_QPLIB_SWQE_TYPE_RDMA_WRITE_WITH_IMM; 2108 wqe->rdma.imm_data = wr->ex.imm_data; 2109 break; 2110 case IB_WR_RDMA_READ: 2111 wqe->type = BNXT_QPLIB_SWQE_TYPE_RDMA_READ; 2112 wqe->rdma.inv_key = wr->ex.invalidate_rkey; 2113 break; 2114 default: 2115 return -EINVAL; 2116 } 2117 wqe->rdma.remote_va = rdma_wr(wr)->remote_addr; 2118 wqe->rdma.r_key = rdma_wr(wr)->rkey; 2119 if (wr->send_flags & IB_SEND_SIGNALED) 2120 wqe->flags |= BNXT_QPLIB_SWQE_FLAGS_SIGNAL_COMP; 2121 if (wr->send_flags & IB_SEND_FENCE) 2122 wqe->flags |= BNXT_QPLIB_SWQE_FLAGS_UC_FENCE; 2123 if (wr->send_flags & IB_SEND_SOLICITED) 2124 wqe->flags |= BNXT_QPLIB_SWQE_FLAGS_SOLICIT_EVENT; 2125 if (wr->send_flags & IB_SEND_INLINE) 2126 wqe->flags |= BNXT_QPLIB_SWQE_FLAGS_INLINE; 2127 2128 return 0; 2129 } 2130 2131 static int bnxt_re_build_atomic_wqe(const struct ib_send_wr *wr, 2132 struct bnxt_qplib_swqe *wqe) 2133 { 2134 switch (wr->opcode) { 2135 case IB_WR_ATOMIC_CMP_AND_SWP: 2136 wqe->type = BNXT_QPLIB_SWQE_TYPE_ATOMIC_CMP_AND_SWP; 2137 wqe->atomic.cmp_data = atomic_wr(wr)->compare_add; 2138 wqe->atomic.swap_data = atomic_wr(wr)->swap; 2139 break; 2140 case IB_WR_ATOMIC_FETCH_AND_ADD: 2141 wqe->type = BNXT_QPLIB_SWQE_TYPE_ATOMIC_FETCH_AND_ADD; 2142 wqe->atomic.cmp_data = atomic_wr(wr)->compare_add; 2143 break; 2144 default: 2145 return -EINVAL; 2146 } 2147 wqe->atomic.remote_va = atomic_wr(wr)->remote_addr; 2148 wqe->atomic.r_key = atomic_wr(wr)->rkey; 2149 if (wr->send_flags & IB_SEND_SIGNALED) 2150 wqe->flags |= BNXT_QPLIB_SWQE_FLAGS_SIGNAL_COMP; 2151 if (wr->send_flags & IB_SEND_FENCE) 2152 wqe->flags |= BNXT_QPLIB_SWQE_FLAGS_UC_FENCE; 2153 if (wr->send_flags & IB_SEND_SOLICITED) 2154 wqe->flags |= BNXT_QPLIB_SWQE_FLAGS_SOLICIT_EVENT; 2155 return 0; 2156 } 2157 2158 static int bnxt_re_build_inv_wqe(const struct ib_send_wr *wr, 2159 struct bnxt_qplib_swqe *wqe) 2160 { 2161 wqe->type = BNXT_QPLIB_SWQE_TYPE_LOCAL_INV; 2162 wqe->local_inv.inv_l_key = wr->ex.invalidate_rkey; 2163 2164 /* Need unconditional fence for local invalidate 2165 * opcode to work as expected. 2166 */ 2167 wqe->flags |= BNXT_QPLIB_SWQE_FLAGS_UC_FENCE; 2168 2169 if (wr->send_flags & IB_SEND_SIGNALED) 2170 wqe->flags |= BNXT_QPLIB_SWQE_FLAGS_SIGNAL_COMP; 2171 if (wr->send_flags & IB_SEND_SOLICITED) 2172 wqe->flags |= BNXT_QPLIB_SWQE_FLAGS_SOLICIT_EVENT; 2173 2174 return 0; 2175 } 2176 2177 static int bnxt_re_build_reg_wqe(const struct ib_reg_wr *wr, 2178 struct bnxt_qplib_swqe *wqe) 2179 { 2180 struct bnxt_re_mr *mr = container_of(wr->mr, struct bnxt_re_mr, ib_mr); 2181 struct bnxt_qplib_frpl *qplib_frpl = &mr->qplib_frpl; 2182 int access = wr->access; 2183 2184 wqe->frmr.pbl_ptr = (__le64 *)qplib_frpl->hwq.pbl_ptr[0]; 2185 wqe->frmr.pbl_dma_ptr = qplib_frpl->hwq.pbl_dma_ptr[0]; 2186 wqe->frmr.page_list = mr->pages; 2187 wqe->frmr.page_list_len = mr->npages; 2188 wqe->frmr.levels = qplib_frpl->hwq.level + 1; 2189 wqe->type = BNXT_QPLIB_SWQE_TYPE_REG_MR; 2190 2191 /* Need unconditional fence for reg_mr 2192 * opcode to function as expected. 2193 */ 2194 2195 wqe->flags |= BNXT_QPLIB_SWQE_FLAGS_UC_FENCE; 2196 2197 if (wr->wr.send_flags & IB_SEND_SIGNALED) 2198 wqe->flags |= BNXT_QPLIB_SWQE_FLAGS_SIGNAL_COMP; 2199 2200 if (access & IB_ACCESS_LOCAL_WRITE) 2201 wqe->frmr.access_cntl |= SQ_FR_PMR_ACCESS_CNTL_LOCAL_WRITE; 2202 if (access & IB_ACCESS_REMOTE_READ) 2203 wqe->frmr.access_cntl |= SQ_FR_PMR_ACCESS_CNTL_REMOTE_READ; 2204 if (access & IB_ACCESS_REMOTE_WRITE) 2205 wqe->frmr.access_cntl |= SQ_FR_PMR_ACCESS_CNTL_REMOTE_WRITE; 2206 if (access & IB_ACCESS_REMOTE_ATOMIC) 2207 wqe->frmr.access_cntl |= SQ_FR_PMR_ACCESS_CNTL_REMOTE_ATOMIC; 2208 if (access & IB_ACCESS_MW_BIND) 2209 wqe->frmr.access_cntl |= SQ_FR_PMR_ACCESS_CNTL_WINDOW_BIND; 2210 2211 wqe->frmr.l_key = wr->key; 2212 wqe->frmr.length = wr->mr->length; 2213 wqe->frmr.pbl_pg_sz_log = (wr->mr->page_size >> PAGE_SHIFT_4K) - 1; 2214 wqe->frmr.va = wr->mr->iova; 2215 return 0; 2216 } 2217 2218 static int bnxt_re_copy_inline_data(struct bnxt_re_dev *rdev, 2219 const struct ib_send_wr *wr, 2220 struct bnxt_qplib_swqe *wqe) 2221 { 2222 /* Copy the inline data to the data field */ 2223 u8 *in_data; 2224 u32 i, sge_len; 2225 void *sge_addr; 2226 2227 in_data = wqe->inline_data; 2228 for (i = 0; i < wr->num_sge; i++) { 2229 sge_addr = (void *)(unsigned long) 2230 wr->sg_list[i].addr; 2231 sge_len = wr->sg_list[i].length; 2232 2233 if ((sge_len + wqe->inline_len) > 2234 BNXT_QPLIB_SWQE_MAX_INLINE_LENGTH) { 2235 dev_err(rdev_to_dev(rdev), 2236 "Inline data size requested > supported value"); 2237 return -EINVAL; 2238 } 2239 sge_len = wr->sg_list[i].length; 2240 2241 memcpy(in_data, sge_addr, sge_len); 2242 in_data += wr->sg_list[i].length; 2243 wqe->inline_len += wr->sg_list[i].length; 2244 } 2245 return wqe->inline_len; 2246 } 2247 2248 static int bnxt_re_copy_wr_payload(struct bnxt_re_dev *rdev, 2249 const struct ib_send_wr *wr, 2250 struct bnxt_qplib_swqe *wqe) 2251 { 2252 int payload_sz = 0; 2253 2254 if (wr->send_flags & IB_SEND_INLINE) 2255 payload_sz = bnxt_re_copy_inline_data(rdev, wr, wqe); 2256 else 2257 payload_sz = bnxt_re_build_sgl(wr->sg_list, wqe->sg_list, 2258 wqe->num_sge); 2259 2260 return payload_sz; 2261 } 2262 2263 static void bnxt_ud_qp_hw_stall_workaround(struct bnxt_re_qp *qp) 2264 { 2265 if ((qp->ib_qp.qp_type == IB_QPT_UD || 2266 qp->ib_qp.qp_type == IB_QPT_GSI || 2267 qp->ib_qp.qp_type == IB_QPT_RAW_ETHERTYPE) && 2268 qp->qplib_qp.wqe_cnt == BNXT_RE_UD_QP_HW_STALL) { 2269 int qp_attr_mask; 2270 struct ib_qp_attr qp_attr; 2271 2272 qp_attr_mask = IB_QP_STATE; 2273 qp_attr.qp_state = IB_QPS_RTS; 2274 bnxt_re_modify_qp(&qp->ib_qp, &qp_attr, qp_attr_mask, NULL); 2275 qp->qplib_qp.wqe_cnt = 0; 2276 } 2277 } 2278 2279 static int bnxt_re_post_send_shadow_qp(struct bnxt_re_dev *rdev, 2280 struct bnxt_re_qp *qp, 2281 const struct ib_send_wr *wr) 2282 { 2283 struct bnxt_qplib_swqe wqe; 2284 int rc = 0, payload_sz = 0; 2285 unsigned long flags; 2286 2287 spin_lock_irqsave(&qp->sq_lock, flags); 2288 memset(&wqe, 0, sizeof(wqe)); 2289 while (wr) { 2290 /* House keeping */ 2291 memset(&wqe, 0, sizeof(wqe)); 2292 2293 /* Common */ 2294 wqe.num_sge = wr->num_sge; 2295 if (wr->num_sge > qp->qplib_qp.sq.max_sge) { 2296 dev_err(rdev_to_dev(rdev), 2297 "Limit exceeded for Send SGEs"); 2298 rc = -EINVAL; 2299 goto bad; 2300 } 2301 2302 payload_sz = bnxt_re_copy_wr_payload(qp->rdev, wr, &wqe); 2303 if (payload_sz < 0) { 2304 rc = -EINVAL; 2305 goto bad; 2306 } 2307 wqe.wr_id = wr->wr_id; 2308 2309 wqe.type = BNXT_QPLIB_SWQE_TYPE_SEND; 2310 2311 rc = bnxt_re_build_send_wqe(qp, wr, &wqe); 2312 if (!rc) 2313 rc = bnxt_qplib_post_send(&qp->qplib_qp, &wqe); 2314 bad: 2315 if (rc) { 2316 dev_err(rdev_to_dev(rdev), 2317 "Post send failed opcode = %#x rc = %d", 2318 wr->opcode, rc); 2319 break; 2320 } 2321 wr = wr->next; 2322 } 2323 bnxt_qplib_post_send_db(&qp->qplib_qp); 2324 bnxt_ud_qp_hw_stall_workaround(qp); 2325 spin_unlock_irqrestore(&qp->sq_lock, flags); 2326 return rc; 2327 } 2328 2329 int bnxt_re_post_send(struct ib_qp *ib_qp, const struct ib_send_wr *wr, 2330 const struct ib_send_wr **bad_wr) 2331 { 2332 struct bnxt_re_qp *qp = container_of(ib_qp, struct bnxt_re_qp, ib_qp); 2333 struct bnxt_qplib_swqe wqe; 2334 int rc = 0, payload_sz = 0; 2335 unsigned long flags; 2336 2337 spin_lock_irqsave(&qp->sq_lock, flags); 2338 while (wr) { 2339 /* House keeping */ 2340 memset(&wqe, 0, sizeof(wqe)); 2341 2342 /* Common */ 2343 wqe.num_sge = wr->num_sge; 2344 if (wr->num_sge > qp->qplib_qp.sq.max_sge) { 2345 dev_err(rdev_to_dev(qp->rdev), 2346 "Limit exceeded for Send SGEs"); 2347 rc = -EINVAL; 2348 goto bad; 2349 } 2350 2351 payload_sz = bnxt_re_copy_wr_payload(qp->rdev, wr, &wqe); 2352 if (payload_sz < 0) { 2353 rc = -EINVAL; 2354 goto bad; 2355 } 2356 wqe.wr_id = wr->wr_id; 2357 2358 switch (wr->opcode) { 2359 case IB_WR_SEND: 2360 case IB_WR_SEND_WITH_IMM: 2361 if (qp->qplib_qp.type == CMDQ_CREATE_QP1_TYPE_GSI) { 2362 rc = bnxt_re_build_qp1_send_v2(qp, wr, &wqe, 2363 payload_sz); 2364 if (rc) 2365 goto bad; 2366 wqe.rawqp1.lflags |= 2367 SQ_SEND_RAWETH_QP1_LFLAGS_ROCE_CRC; 2368 } 2369 switch (wr->send_flags) { 2370 case IB_SEND_IP_CSUM: 2371 wqe.rawqp1.lflags |= 2372 SQ_SEND_RAWETH_QP1_LFLAGS_IP_CHKSUM; 2373 break; 2374 default: 2375 break; 2376 } 2377 /* fall through */ 2378 case IB_WR_SEND_WITH_INV: 2379 rc = bnxt_re_build_send_wqe(qp, wr, &wqe); 2380 break; 2381 case IB_WR_RDMA_WRITE: 2382 case IB_WR_RDMA_WRITE_WITH_IMM: 2383 case IB_WR_RDMA_READ: 2384 rc = bnxt_re_build_rdma_wqe(wr, &wqe); 2385 break; 2386 case IB_WR_ATOMIC_CMP_AND_SWP: 2387 case IB_WR_ATOMIC_FETCH_AND_ADD: 2388 rc = bnxt_re_build_atomic_wqe(wr, &wqe); 2389 break; 2390 case IB_WR_RDMA_READ_WITH_INV: 2391 dev_err(rdev_to_dev(qp->rdev), 2392 "RDMA Read with Invalidate is not supported"); 2393 rc = -EINVAL; 2394 goto bad; 2395 case IB_WR_LOCAL_INV: 2396 rc = bnxt_re_build_inv_wqe(wr, &wqe); 2397 break; 2398 case IB_WR_REG_MR: 2399 rc = bnxt_re_build_reg_wqe(reg_wr(wr), &wqe); 2400 break; 2401 default: 2402 /* Unsupported WRs */ 2403 dev_err(rdev_to_dev(qp->rdev), 2404 "WR (%#x) is not supported", wr->opcode); 2405 rc = -EINVAL; 2406 goto bad; 2407 } 2408 if (!rc) 2409 rc = bnxt_qplib_post_send(&qp->qplib_qp, &wqe); 2410 bad: 2411 if (rc) { 2412 dev_err(rdev_to_dev(qp->rdev), 2413 "post_send failed op:%#x qps = %#x rc = %d\n", 2414 wr->opcode, qp->qplib_qp.state, rc); 2415 *bad_wr = wr; 2416 break; 2417 } 2418 wr = wr->next; 2419 } 2420 bnxt_qplib_post_send_db(&qp->qplib_qp); 2421 bnxt_ud_qp_hw_stall_workaround(qp); 2422 spin_unlock_irqrestore(&qp->sq_lock, flags); 2423 2424 return rc; 2425 } 2426 2427 static int bnxt_re_post_recv_shadow_qp(struct bnxt_re_dev *rdev, 2428 struct bnxt_re_qp *qp, 2429 const struct ib_recv_wr *wr) 2430 { 2431 struct bnxt_qplib_swqe wqe; 2432 int rc = 0; 2433 2434 memset(&wqe, 0, sizeof(wqe)); 2435 while (wr) { 2436 /* House keeping */ 2437 memset(&wqe, 0, sizeof(wqe)); 2438 2439 /* Common */ 2440 wqe.num_sge = wr->num_sge; 2441 if (wr->num_sge > qp->qplib_qp.rq.max_sge) { 2442 dev_err(rdev_to_dev(rdev), 2443 "Limit exceeded for Receive SGEs"); 2444 rc = -EINVAL; 2445 break; 2446 } 2447 bnxt_re_build_sgl(wr->sg_list, wqe.sg_list, wr->num_sge); 2448 wqe.wr_id = wr->wr_id; 2449 wqe.type = BNXT_QPLIB_SWQE_TYPE_RECV; 2450 2451 rc = bnxt_qplib_post_recv(&qp->qplib_qp, &wqe); 2452 if (rc) 2453 break; 2454 2455 wr = wr->next; 2456 } 2457 if (!rc) 2458 bnxt_qplib_post_recv_db(&qp->qplib_qp); 2459 return rc; 2460 } 2461 2462 int bnxt_re_post_recv(struct ib_qp *ib_qp, const struct ib_recv_wr *wr, 2463 const struct ib_recv_wr **bad_wr) 2464 { 2465 struct bnxt_re_qp *qp = container_of(ib_qp, struct bnxt_re_qp, ib_qp); 2466 struct bnxt_qplib_swqe wqe; 2467 int rc = 0, payload_sz = 0; 2468 unsigned long flags; 2469 u32 count = 0; 2470 2471 spin_lock_irqsave(&qp->rq_lock, flags); 2472 while (wr) { 2473 /* House keeping */ 2474 memset(&wqe, 0, sizeof(wqe)); 2475 2476 /* Common */ 2477 wqe.num_sge = wr->num_sge; 2478 if (wr->num_sge > qp->qplib_qp.rq.max_sge) { 2479 dev_err(rdev_to_dev(qp->rdev), 2480 "Limit exceeded for Receive SGEs"); 2481 rc = -EINVAL; 2482 *bad_wr = wr; 2483 break; 2484 } 2485 2486 payload_sz = bnxt_re_build_sgl(wr->sg_list, wqe.sg_list, 2487 wr->num_sge); 2488 wqe.wr_id = wr->wr_id; 2489 wqe.type = BNXT_QPLIB_SWQE_TYPE_RECV; 2490 2491 if (ib_qp->qp_type == IB_QPT_GSI && 2492 qp->qplib_qp.type != CMDQ_CREATE_QP_TYPE_GSI) 2493 rc = bnxt_re_build_qp1_shadow_qp_recv(qp, wr, &wqe, 2494 payload_sz); 2495 if (!rc) 2496 rc = bnxt_qplib_post_recv(&qp->qplib_qp, &wqe); 2497 if (rc) { 2498 *bad_wr = wr; 2499 break; 2500 } 2501 2502 /* Ring DB if the RQEs posted reaches a threshold value */ 2503 if (++count >= BNXT_RE_RQ_WQE_THRESHOLD) { 2504 bnxt_qplib_post_recv_db(&qp->qplib_qp); 2505 count = 0; 2506 } 2507 2508 wr = wr->next; 2509 } 2510 2511 if (count) 2512 bnxt_qplib_post_recv_db(&qp->qplib_qp); 2513 2514 spin_unlock_irqrestore(&qp->rq_lock, flags); 2515 2516 return rc; 2517 } 2518 2519 /* Completion Queues */ 2520 int bnxt_re_destroy_cq(struct ib_cq *ib_cq, struct ib_udata *udata) 2521 { 2522 int rc; 2523 struct bnxt_re_cq *cq; 2524 struct bnxt_qplib_nq *nq; 2525 struct bnxt_re_dev *rdev; 2526 2527 cq = container_of(ib_cq, struct bnxt_re_cq, ib_cq); 2528 rdev = cq->rdev; 2529 nq = cq->qplib_cq.nq; 2530 2531 rc = bnxt_qplib_destroy_cq(&rdev->qplib_res, &cq->qplib_cq); 2532 if (rc) { 2533 dev_err(rdev_to_dev(rdev), "Failed to destroy HW CQ"); 2534 return rc; 2535 } 2536 if (!IS_ERR_OR_NULL(cq->umem)) 2537 ib_umem_release(cq->umem); 2538 2539 atomic_dec(&rdev->cq_count); 2540 nq->budget--; 2541 kfree(cq->cql); 2542 kfree(cq); 2543 2544 return 0; 2545 } 2546 2547 struct ib_cq *bnxt_re_create_cq(struct ib_device *ibdev, 2548 const struct ib_cq_init_attr *attr, 2549 struct ib_udata *udata) 2550 { 2551 struct bnxt_re_dev *rdev = to_bnxt_re_dev(ibdev, ibdev); 2552 struct bnxt_qplib_dev_attr *dev_attr = &rdev->dev_attr; 2553 struct bnxt_re_cq *cq = NULL; 2554 int rc, entries; 2555 int cqe = attr->cqe; 2556 struct bnxt_qplib_nq *nq = NULL; 2557 unsigned int nq_alloc_cnt; 2558 2559 /* Validate CQ fields */ 2560 if (cqe < 1 || cqe > dev_attr->max_cq_wqes) { 2561 dev_err(rdev_to_dev(rdev), "Failed to create CQ -max exceeded"); 2562 return ERR_PTR(-EINVAL); 2563 } 2564 cq = kzalloc(sizeof(*cq), GFP_KERNEL); 2565 if (!cq) 2566 return ERR_PTR(-ENOMEM); 2567 2568 cq->rdev = rdev; 2569 cq->qplib_cq.cq_handle = (u64)(unsigned long)(&cq->qplib_cq); 2570 2571 entries = roundup_pow_of_two(cqe + 1); 2572 if (entries > dev_attr->max_cq_wqes + 1) 2573 entries = dev_attr->max_cq_wqes + 1; 2574 2575 if (udata) { 2576 struct bnxt_re_cq_req req; 2577 struct bnxt_re_ucontext *uctx = rdma_udata_to_drv_context( 2578 udata, struct bnxt_re_ucontext, ib_uctx); 2579 if (ib_copy_from_udata(&req, udata, sizeof(req))) { 2580 rc = -EFAULT; 2581 goto fail; 2582 } 2583 2584 cq->umem = ib_umem_get(udata, req.cq_va, 2585 entries * sizeof(struct cq_base), 2586 IB_ACCESS_LOCAL_WRITE, 1); 2587 if (IS_ERR(cq->umem)) { 2588 rc = PTR_ERR(cq->umem); 2589 goto fail; 2590 } 2591 cq->qplib_cq.sg_info.sglist = cq->umem->sg_head.sgl; 2592 cq->qplib_cq.sg_info.npages = ib_umem_num_pages(cq->umem); 2593 cq->qplib_cq.sg_info.nmap = cq->umem->nmap; 2594 cq->qplib_cq.dpi = &uctx->dpi; 2595 } else { 2596 cq->max_cql = min_t(u32, entries, MAX_CQL_PER_POLL); 2597 cq->cql = kcalloc(cq->max_cql, sizeof(struct bnxt_qplib_cqe), 2598 GFP_KERNEL); 2599 if (!cq->cql) { 2600 rc = -ENOMEM; 2601 goto fail; 2602 } 2603 2604 cq->qplib_cq.dpi = &rdev->dpi_privileged; 2605 } 2606 /* 2607 * Allocating the NQ in a round robin fashion. nq_alloc_cnt is a 2608 * used for getting the NQ index. 2609 */ 2610 nq_alloc_cnt = atomic_inc_return(&rdev->nq_alloc_cnt); 2611 nq = &rdev->nq[nq_alloc_cnt % (rdev->num_msix - 1)]; 2612 cq->qplib_cq.max_wqe = entries; 2613 cq->qplib_cq.cnq_hw_ring_id = nq->ring_id; 2614 cq->qplib_cq.nq = nq; 2615 2616 rc = bnxt_qplib_create_cq(&rdev->qplib_res, &cq->qplib_cq); 2617 if (rc) { 2618 dev_err(rdev_to_dev(rdev), "Failed to create HW CQ"); 2619 goto fail; 2620 } 2621 2622 cq->ib_cq.cqe = entries; 2623 cq->cq_period = cq->qplib_cq.period; 2624 nq->budget++; 2625 2626 atomic_inc(&rdev->cq_count); 2627 spin_lock_init(&cq->cq_lock); 2628 2629 if (udata) { 2630 struct bnxt_re_cq_resp resp; 2631 2632 resp.cqid = cq->qplib_cq.id; 2633 resp.tail = cq->qplib_cq.hwq.cons; 2634 resp.phase = cq->qplib_cq.period; 2635 resp.rsvd = 0; 2636 rc = ib_copy_to_udata(udata, &resp, sizeof(resp)); 2637 if (rc) { 2638 dev_err(rdev_to_dev(rdev), "Failed to copy CQ udata"); 2639 bnxt_qplib_destroy_cq(&rdev->qplib_res, &cq->qplib_cq); 2640 goto c2fail; 2641 } 2642 } 2643 2644 return &cq->ib_cq; 2645 2646 c2fail: 2647 if (udata) 2648 ib_umem_release(cq->umem); 2649 fail: 2650 kfree(cq->cql); 2651 kfree(cq); 2652 return ERR_PTR(rc); 2653 } 2654 2655 static u8 __req_to_ib_wc_status(u8 qstatus) 2656 { 2657 switch (qstatus) { 2658 case CQ_REQ_STATUS_OK: 2659 return IB_WC_SUCCESS; 2660 case CQ_REQ_STATUS_BAD_RESPONSE_ERR: 2661 return IB_WC_BAD_RESP_ERR; 2662 case CQ_REQ_STATUS_LOCAL_LENGTH_ERR: 2663 return IB_WC_LOC_LEN_ERR; 2664 case CQ_REQ_STATUS_LOCAL_QP_OPERATION_ERR: 2665 return IB_WC_LOC_QP_OP_ERR; 2666 case CQ_REQ_STATUS_LOCAL_PROTECTION_ERR: 2667 return IB_WC_LOC_PROT_ERR; 2668 case CQ_REQ_STATUS_MEMORY_MGT_OPERATION_ERR: 2669 return IB_WC_GENERAL_ERR; 2670 case CQ_REQ_STATUS_REMOTE_INVALID_REQUEST_ERR: 2671 return IB_WC_REM_INV_REQ_ERR; 2672 case CQ_REQ_STATUS_REMOTE_ACCESS_ERR: 2673 return IB_WC_REM_ACCESS_ERR; 2674 case CQ_REQ_STATUS_REMOTE_OPERATION_ERR: 2675 return IB_WC_REM_OP_ERR; 2676 case CQ_REQ_STATUS_RNR_NAK_RETRY_CNT_ERR: 2677 return IB_WC_RNR_RETRY_EXC_ERR; 2678 case CQ_REQ_STATUS_TRANSPORT_RETRY_CNT_ERR: 2679 return IB_WC_RETRY_EXC_ERR; 2680 case CQ_REQ_STATUS_WORK_REQUEST_FLUSHED_ERR: 2681 return IB_WC_WR_FLUSH_ERR; 2682 default: 2683 return IB_WC_GENERAL_ERR; 2684 } 2685 return 0; 2686 } 2687 2688 static u8 __rawqp1_to_ib_wc_status(u8 qstatus) 2689 { 2690 switch (qstatus) { 2691 case CQ_RES_RAWETH_QP1_STATUS_OK: 2692 return IB_WC_SUCCESS; 2693 case CQ_RES_RAWETH_QP1_STATUS_LOCAL_ACCESS_ERROR: 2694 return IB_WC_LOC_ACCESS_ERR; 2695 case CQ_RES_RAWETH_QP1_STATUS_HW_LOCAL_LENGTH_ERR: 2696 return IB_WC_LOC_LEN_ERR; 2697 case CQ_RES_RAWETH_QP1_STATUS_LOCAL_PROTECTION_ERR: 2698 return IB_WC_LOC_PROT_ERR; 2699 case CQ_RES_RAWETH_QP1_STATUS_LOCAL_QP_OPERATION_ERR: 2700 return IB_WC_LOC_QP_OP_ERR; 2701 case CQ_RES_RAWETH_QP1_STATUS_MEMORY_MGT_OPERATION_ERR: 2702 return IB_WC_GENERAL_ERR; 2703 case CQ_RES_RAWETH_QP1_STATUS_WORK_REQUEST_FLUSHED_ERR: 2704 return IB_WC_WR_FLUSH_ERR; 2705 case CQ_RES_RAWETH_QP1_STATUS_HW_FLUSH_ERR: 2706 return IB_WC_WR_FLUSH_ERR; 2707 default: 2708 return IB_WC_GENERAL_ERR; 2709 } 2710 } 2711 2712 static u8 __rc_to_ib_wc_status(u8 qstatus) 2713 { 2714 switch (qstatus) { 2715 case CQ_RES_RC_STATUS_OK: 2716 return IB_WC_SUCCESS; 2717 case CQ_RES_RC_STATUS_LOCAL_ACCESS_ERROR: 2718 return IB_WC_LOC_ACCESS_ERR; 2719 case CQ_RES_RC_STATUS_LOCAL_LENGTH_ERR: 2720 return IB_WC_LOC_LEN_ERR; 2721 case CQ_RES_RC_STATUS_LOCAL_PROTECTION_ERR: 2722 return IB_WC_LOC_PROT_ERR; 2723 case CQ_RES_RC_STATUS_LOCAL_QP_OPERATION_ERR: 2724 return IB_WC_LOC_QP_OP_ERR; 2725 case CQ_RES_RC_STATUS_MEMORY_MGT_OPERATION_ERR: 2726 return IB_WC_GENERAL_ERR; 2727 case CQ_RES_RC_STATUS_REMOTE_INVALID_REQUEST_ERR: 2728 return IB_WC_REM_INV_REQ_ERR; 2729 case CQ_RES_RC_STATUS_WORK_REQUEST_FLUSHED_ERR: 2730 return IB_WC_WR_FLUSH_ERR; 2731 case CQ_RES_RC_STATUS_HW_FLUSH_ERR: 2732 return IB_WC_WR_FLUSH_ERR; 2733 default: 2734 return IB_WC_GENERAL_ERR; 2735 } 2736 } 2737 2738 static void bnxt_re_process_req_wc(struct ib_wc *wc, struct bnxt_qplib_cqe *cqe) 2739 { 2740 switch (cqe->type) { 2741 case BNXT_QPLIB_SWQE_TYPE_SEND: 2742 wc->opcode = IB_WC_SEND; 2743 break; 2744 case BNXT_QPLIB_SWQE_TYPE_SEND_WITH_IMM: 2745 wc->opcode = IB_WC_SEND; 2746 wc->wc_flags |= IB_WC_WITH_IMM; 2747 break; 2748 case BNXT_QPLIB_SWQE_TYPE_SEND_WITH_INV: 2749 wc->opcode = IB_WC_SEND; 2750 wc->wc_flags |= IB_WC_WITH_INVALIDATE; 2751 break; 2752 case BNXT_QPLIB_SWQE_TYPE_RDMA_WRITE: 2753 wc->opcode = IB_WC_RDMA_WRITE; 2754 break; 2755 case BNXT_QPLIB_SWQE_TYPE_RDMA_WRITE_WITH_IMM: 2756 wc->opcode = IB_WC_RDMA_WRITE; 2757 wc->wc_flags |= IB_WC_WITH_IMM; 2758 break; 2759 case BNXT_QPLIB_SWQE_TYPE_RDMA_READ: 2760 wc->opcode = IB_WC_RDMA_READ; 2761 break; 2762 case BNXT_QPLIB_SWQE_TYPE_ATOMIC_CMP_AND_SWP: 2763 wc->opcode = IB_WC_COMP_SWAP; 2764 break; 2765 case BNXT_QPLIB_SWQE_TYPE_ATOMIC_FETCH_AND_ADD: 2766 wc->opcode = IB_WC_FETCH_ADD; 2767 break; 2768 case BNXT_QPLIB_SWQE_TYPE_LOCAL_INV: 2769 wc->opcode = IB_WC_LOCAL_INV; 2770 break; 2771 case BNXT_QPLIB_SWQE_TYPE_REG_MR: 2772 wc->opcode = IB_WC_REG_MR; 2773 break; 2774 default: 2775 wc->opcode = IB_WC_SEND; 2776 break; 2777 } 2778 2779 wc->status = __req_to_ib_wc_status(cqe->status); 2780 } 2781 2782 static int bnxt_re_check_packet_type(u16 raweth_qp1_flags, 2783 u16 raweth_qp1_flags2) 2784 { 2785 bool is_ipv6 = false, is_ipv4 = false; 2786 2787 /* raweth_qp1_flags Bit 9-6 indicates itype */ 2788 if ((raweth_qp1_flags & CQ_RES_RAWETH_QP1_RAWETH_QP1_FLAGS_ITYPE_ROCE) 2789 != CQ_RES_RAWETH_QP1_RAWETH_QP1_FLAGS_ITYPE_ROCE) 2790 return -1; 2791 2792 if (raweth_qp1_flags2 & 2793 CQ_RES_RAWETH_QP1_RAWETH_QP1_FLAGS2_IP_CS_CALC && 2794 raweth_qp1_flags2 & 2795 CQ_RES_RAWETH_QP1_RAWETH_QP1_FLAGS2_L4_CS_CALC) { 2796 /* raweth_qp1_flags2 Bit 8 indicates ip_type. 0-v4 1 - v6 */ 2797 (raweth_qp1_flags2 & 2798 CQ_RES_RAWETH_QP1_RAWETH_QP1_FLAGS2_IP_TYPE) ? 2799 (is_ipv6 = true) : (is_ipv4 = true); 2800 return ((is_ipv6) ? 2801 BNXT_RE_ROCEV2_IPV6_PACKET : 2802 BNXT_RE_ROCEV2_IPV4_PACKET); 2803 } else { 2804 return BNXT_RE_ROCE_V1_PACKET; 2805 } 2806 } 2807 2808 static int bnxt_re_to_ib_nw_type(int nw_type) 2809 { 2810 u8 nw_hdr_type = 0xFF; 2811 2812 switch (nw_type) { 2813 case BNXT_RE_ROCE_V1_PACKET: 2814 nw_hdr_type = RDMA_NETWORK_ROCE_V1; 2815 break; 2816 case BNXT_RE_ROCEV2_IPV4_PACKET: 2817 nw_hdr_type = RDMA_NETWORK_IPV4; 2818 break; 2819 case BNXT_RE_ROCEV2_IPV6_PACKET: 2820 nw_hdr_type = RDMA_NETWORK_IPV6; 2821 break; 2822 } 2823 return nw_hdr_type; 2824 } 2825 2826 static bool bnxt_re_is_loopback_packet(struct bnxt_re_dev *rdev, 2827 void *rq_hdr_buf) 2828 { 2829 u8 *tmp_buf = NULL; 2830 struct ethhdr *eth_hdr; 2831 u16 eth_type; 2832 bool rc = false; 2833 2834 tmp_buf = (u8 *)rq_hdr_buf; 2835 /* 2836 * If dest mac is not same as I/F mac, this could be a 2837 * loopback address or multicast address, check whether 2838 * it is a loopback packet 2839 */ 2840 if (!ether_addr_equal(tmp_buf, rdev->netdev->dev_addr)) { 2841 tmp_buf += 4; 2842 /* Check the ether type */ 2843 eth_hdr = (struct ethhdr *)tmp_buf; 2844 eth_type = ntohs(eth_hdr->h_proto); 2845 switch (eth_type) { 2846 case ETH_P_IBOE: 2847 rc = true; 2848 break; 2849 case ETH_P_IP: 2850 case ETH_P_IPV6: { 2851 u32 len; 2852 struct udphdr *udp_hdr; 2853 2854 len = (eth_type == ETH_P_IP ? sizeof(struct iphdr) : 2855 sizeof(struct ipv6hdr)); 2856 tmp_buf += sizeof(struct ethhdr) + len; 2857 udp_hdr = (struct udphdr *)tmp_buf; 2858 if (ntohs(udp_hdr->dest) == 2859 ROCE_V2_UDP_DPORT) 2860 rc = true; 2861 break; 2862 } 2863 default: 2864 break; 2865 } 2866 } 2867 2868 return rc; 2869 } 2870 2871 static int bnxt_re_process_raw_qp_pkt_rx(struct bnxt_re_qp *qp1_qp, 2872 struct bnxt_qplib_cqe *cqe) 2873 { 2874 struct bnxt_re_dev *rdev = qp1_qp->rdev; 2875 struct bnxt_re_sqp_entries *sqp_entry = NULL; 2876 struct bnxt_re_qp *qp = rdev->qp1_sqp; 2877 struct ib_send_wr *swr; 2878 struct ib_ud_wr udwr; 2879 struct ib_recv_wr rwr; 2880 int pkt_type = 0; 2881 u32 tbl_idx; 2882 void *rq_hdr_buf; 2883 dma_addr_t rq_hdr_buf_map; 2884 dma_addr_t shrq_hdr_buf_map; 2885 u32 offset = 0; 2886 u32 skip_bytes = 0; 2887 struct ib_sge s_sge[2]; 2888 struct ib_sge r_sge[2]; 2889 int rc; 2890 2891 memset(&udwr, 0, sizeof(udwr)); 2892 memset(&rwr, 0, sizeof(rwr)); 2893 memset(&s_sge, 0, sizeof(s_sge)); 2894 memset(&r_sge, 0, sizeof(r_sge)); 2895 2896 swr = &udwr.wr; 2897 tbl_idx = cqe->wr_id; 2898 2899 rq_hdr_buf = qp1_qp->qplib_qp.rq_hdr_buf + 2900 (tbl_idx * qp1_qp->qplib_qp.rq_hdr_buf_size); 2901 rq_hdr_buf_map = bnxt_qplib_get_qp_buf_from_index(&qp1_qp->qplib_qp, 2902 tbl_idx); 2903 2904 /* Shadow QP header buffer */ 2905 shrq_hdr_buf_map = bnxt_qplib_get_qp_buf_from_index(&qp->qplib_qp, 2906 tbl_idx); 2907 sqp_entry = &rdev->sqp_tbl[tbl_idx]; 2908 2909 /* Store this cqe */ 2910 memcpy(&sqp_entry->cqe, cqe, sizeof(struct bnxt_qplib_cqe)); 2911 sqp_entry->qp1_qp = qp1_qp; 2912 2913 /* Find packet type from the cqe */ 2914 2915 pkt_type = bnxt_re_check_packet_type(cqe->raweth_qp1_flags, 2916 cqe->raweth_qp1_flags2); 2917 if (pkt_type < 0) { 2918 dev_err(rdev_to_dev(rdev), "Invalid packet\n"); 2919 return -EINVAL; 2920 } 2921 2922 /* Adjust the offset for the user buffer and post in the rq */ 2923 2924 if (pkt_type == BNXT_RE_ROCEV2_IPV4_PACKET) 2925 offset = 20; 2926 2927 /* 2928 * QP1 loopback packet has 4 bytes of internal header before 2929 * ether header. Skip these four bytes. 2930 */ 2931 if (bnxt_re_is_loopback_packet(rdev, rq_hdr_buf)) 2932 skip_bytes = 4; 2933 2934 /* First send SGE . Skip the ether header*/ 2935 s_sge[0].addr = rq_hdr_buf_map + BNXT_QPLIB_MAX_QP1_RQ_ETH_HDR_SIZE 2936 + skip_bytes; 2937 s_sge[0].lkey = 0xFFFFFFFF; 2938 s_sge[0].length = offset ? BNXT_QPLIB_MAX_GRH_HDR_SIZE_IPV4 : 2939 BNXT_QPLIB_MAX_GRH_HDR_SIZE_IPV6; 2940 2941 /* Second Send SGE */ 2942 s_sge[1].addr = s_sge[0].addr + s_sge[0].length + 2943 BNXT_QPLIB_MAX_QP1_RQ_BDETH_HDR_SIZE; 2944 if (pkt_type != BNXT_RE_ROCE_V1_PACKET) 2945 s_sge[1].addr += 8; 2946 s_sge[1].lkey = 0xFFFFFFFF; 2947 s_sge[1].length = 256; 2948 2949 /* First recv SGE */ 2950 2951 r_sge[0].addr = shrq_hdr_buf_map; 2952 r_sge[0].lkey = 0xFFFFFFFF; 2953 r_sge[0].length = 40; 2954 2955 r_sge[1].addr = sqp_entry->sge.addr + offset; 2956 r_sge[1].lkey = sqp_entry->sge.lkey; 2957 r_sge[1].length = BNXT_QPLIB_MAX_GRH_HDR_SIZE_IPV6 + 256 - offset; 2958 2959 /* Create receive work request */ 2960 rwr.num_sge = 2; 2961 rwr.sg_list = r_sge; 2962 rwr.wr_id = tbl_idx; 2963 rwr.next = NULL; 2964 2965 rc = bnxt_re_post_recv_shadow_qp(rdev, qp, &rwr); 2966 if (rc) { 2967 dev_err(rdev_to_dev(rdev), 2968 "Failed to post Rx buffers to shadow QP"); 2969 return -ENOMEM; 2970 } 2971 2972 swr->num_sge = 2; 2973 swr->sg_list = s_sge; 2974 swr->wr_id = tbl_idx; 2975 swr->opcode = IB_WR_SEND; 2976 swr->next = NULL; 2977 2978 udwr.ah = &rdev->sqp_ah->ib_ah; 2979 udwr.remote_qpn = rdev->qp1_sqp->qplib_qp.id; 2980 udwr.remote_qkey = rdev->qp1_sqp->qplib_qp.qkey; 2981 2982 /* post data received in the send queue */ 2983 rc = bnxt_re_post_send_shadow_qp(rdev, qp, swr); 2984 2985 return 0; 2986 } 2987 2988 static void bnxt_re_process_res_rawqp1_wc(struct ib_wc *wc, 2989 struct bnxt_qplib_cqe *cqe) 2990 { 2991 wc->opcode = IB_WC_RECV; 2992 wc->status = __rawqp1_to_ib_wc_status(cqe->status); 2993 wc->wc_flags |= IB_WC_GRH; 2994 } 2995 2996 static bool bnxt_re_is_vlan_pkt(struct bnxt_qplib_cqe *orig_cqe, 2997 u16 *vid, u8 *sl) 2998 { 2999 bool ret = false; 3000 u32 metadata; 3001 u16 tpid; 3002 3003 metadata = orig_cqe->raweth_qp1_metadata; 3004 if (orig_cqe->raweth_qp1_flags2 & 3005 CQ_RES_RAWETH_QP1_RAWETH_QP1_FLAGS2_META_FORMAT_VLAN) { 3006 tpid = ((metadata & 3007 CQ_RES_RAWETH_QP1_RAWETH_QP1_METADATA_TPID_MASK) >> 3008 CQ_RES_RAWETH_QP1_RAWETH_QP1_METADATA_TPID_SFT); 3009 if (tpid == ETH_P_8021Q) { 3010 *vid = metadata & 3011 CQ_RES_RAWETH_QP1_RAWETH_QP1_METADATA_VID_MASK; 3012 *sl = (metadata & 3013 CQ_RES_RAWETH_QP1_RAWETH_QP1_METADATA_PRI_MASK) >> 3014 CQ_RES_RAWETH_QP1_RAWETH_QP1_METADATA_PRI_SFT; 3015 ret = true; 3016 } 3017 } 3018 3019 return ret; 3020 } 3021 3022 static void bnxt_re_process_res_rc_wc(struct ib_wc *wc, 3023 struct bnxt_qplib_cqe *cqe) 3024 { 3025 wc->opcode = IB_WC_RECV; 3026 wc->status = __rc_to_ib_wc_status(cqe->status); 3027 3028 if (cqe->flags & CQ_RES_RC_FLAGS_IMM) 3029 wc->wc_flags |= IB_WC_WITH_IMM; 3030 if (cqe->flags & CQ_RES_RC_FLAGS_INV) 3031 wc->wc_flags |= IB_WC_WITH_INVALIDATE; 3032 if ((cqe->flags & (CQ_RES_RC_FLAGS_RDMA | CQ_RES_RC_FLAGS_IMM)) == 3033 (CQ_RES_RC_FLAGS_RDMA | CQ_RES_RC_FLAGS_IMM)) 3034 wc->opcode = IB_WC_RECV_RDMA_WITH_IMM; 3035 } 3036 3037 static void bnxt_re_process_res_shadow_qp_wc(struct bnxt_re_qp *qp, 3038 struct ib_wc *wc, 3039 struct bnxt_qplib_cqe *cqe) 3040 { 3041 struct bnxt_re_dev *rdev = qp->rdev; 3042 struct bnxt_re_qp *qp1_qp = NULL; 3043 struct bnxt_qplib_cqe *orig_cqe = NULL; 3044 struct bnxt_re_sqp_entries *sqp_entry = NULL; 3045 int nw_type; 3046 u32 tbl_idx; 3047 u16 vlan_id; 3048 u8 sl; 3049 3050 tbl_idx = cqe->wr_id; 3051 3052 sqp_entry = &rdev->sqp_tbl[tbl_idx]; 3053 qp1_qp = sqp_entry->qp1_qp; 3054 orig_cqe = &sqp_entry->cqe; 3055 3056 wc->wr_id = sqp_entry->wrid; 3057 wc->byte_len = orig_cqe->length; 3058 wc->qp = &qp1_qp->ib_qp; 3059 3060 wc->ex.imm_data = orig_cqe->immdata; 3061 wc->src_qp = orig_cqe->src_qp; 3062 memcpy(wc->smac, orig_cqe->smac, ETH_ALEN); 3063 if (bnxt_re_is_vlan_pkt(orig_cqe, &vlan_id, &sl)) { 3064 wc->vlan_id = vlan_id; 3065 wc->sl = sl; 3066 wc->wc_flags |= IB_WC_WITH_VLAN; 3067 } 3068 wc->port_num = 1; 3069 wc->vendor_err = orig_cqe->status; 3070 3071 wc->opcode = IB_WC_RECV; 3072 wc->status = __rawqp1_to_ib_wc_status(orig_cqe->status); 3073 wc->wc_flags |= IB_WC_GRH; 3074 3075 nw_type = bnxt_re_check_packet_type(orig_cqe->raweth_qp1_flags, 3076 orig_cqe->raweth_qp1_flags2); 3077 if (nw_type >= 0) { 3078 wc->network_hdr_type = bnxt_re_to_ib_nw_type(nw_type); 3079 wc->wc_flags |= IB_WC_WITH_NETWORK_HDR_TYPE; 3080 } 3081 } 3082 3083 static void bnxt_re_process_res_ud_wc(struct bnxt_re_qp *qp, 3084 struct ib_wc *wc, 3085 struct bnxt_qplib_cqe *cqe) 3086 { 3087 u8 nw_type; 3088 3089 wc->opcode = IB_WC_RECV; 3090 wc->status = __rc_to_ib_wc_status(cqe->status); 3091 3092 if (cqe->flags & CQ_RES_UD_FLAGS_IMM) 3093 wc->wc_flags |= IB_WC_WITH_IMM; 3094 /* report only on GSI QP for Thor */ 3095 if (qp->qplib_qp.type == CMDQ_CREATE_QP_TYPE_GSI) { 3096 wc->wc_flags |= IB_WC_GRH; 3097 memcpy(wc->smac, cqe->smac, ETH_ALEN); 3098 wc->wc_flags |= IB_WC_WITH_SMAC; 3099 if (cqe->flags & CQ_RES_UD_FLAGS_META_FORMAT_VLAN) { 3100 wc->vlan_id = (cqe->cfa_meta & 0xFFF); 3101 if (wc->vlan_id < 0x1000) 3102 wc->wc_flags |= IB_WC_WITH_VLAN; 3103 } 3104 nw_type = (cqe->flags & CQ_RES_UD_FLAGS_ROCE_IP_VER_MASK) >> 3105 CQ_RES_UD_FLAGS_ROCE_IP_VER_SFT; 3106 wc->network_hdr_type = bnxt_re_to_ib_nw_type(nw_type); 3107 wc->wc_flags |= IB_WC_WITH_NETWORK_HDR_TYPE; 3108 } 3109 3110 } 3111 3112 static int send_phantom_wqe(struct bnxt_re_qp *qp) 3113 { 3114 struct bnxt_qplib_qp *lib_qp = &qp->qplib_qp; 3115 unsigned long flags; 3116 int rc = 0; 3117 3118 spin_lock_irqsave(&qp->sq_lock, flags); 3119 3120 rc = bnxt_re_bind_fence_mw(lib_qp); 3121 if (!rc) { 3122 lib_qp->sq.phantom_wqe_cnt++; 3123 dev_dbg(&lib_qp->sq.hwq.pdev->dev, 3124 "qp %#x sq->prod %#x sw_prod %#x phantom_wqe_cnt %d\n", 3125 lib_qp->id, lib_qp->sq.hwq.prod, 3126 HWQ_CMP(lib_qp->sq.hwq.prod, &lib_qp->sq.hwq), 3127 lib_qp->sq.phantom_wqe_cnt); 3128 } 3129 3130 spin_unlock_irqrestore(&qp->sq_lock, flags); 3131 return rc; 3132 } 3133 3134 int bnxt_re_poll_cq(struct ib_cq *ib_cq, int num_entries, struct ib_wc *wc) 3135 { 3136 struct bnxt_re_cq *cq = container_of(ib_cq, struct bnxt_re_cq, ib_cq); 3137 struct bnxt_re_qp *qp; 3138 struct bnxt_qplib_cqe *cqe; 3139 int i, ncqe, budget; 3140 struct bnxt_qplib_q *sq; 3141 struct bnxt_qplib_qp *lib_qp; 3142 u32 tbl_idx; 3143 struct bnxt_re_sqp_entries *sqp_entry = NULL; 3144 unsigned long flags; 3145 3146 spin_lock_irqsave(&cq->cq_lock, flags); 3147 budget = min_t(u32, num_entries, cq->max_cql); 3148 num_entries = budget; 3149 if (!cq->cql) { 3150 dev_err(rdev_to_dev(cq->rdev), "POLL CQ : no CQL to use"); 3151 goto exit; 3152 } 3153 cqe = &cq->cql[0]; 3154 while (budget) { 3155 lib_qp = NULL; 3156 ncqe = bnxt_qplib_poll_cq(&cq->qplib_cq, cqe, budget, &lib_qp); 3157 if (lib_qp) { 3158 sq = &lib_qp->sq; 3159 if (sq->send_phantom) { 3160 qp = container_of(lib_qp, 3161 struct bnxt_re_qp, qplib_qp); 3162 if (send_phantom_wqe(qp) == -ENOMEM) 3163 dev_err(rdev_to_dev(cq->rdev), 3164 "Phantom failed! Scheduled to send again\n"); 3165 else 3166 sq->send_phantom = false; 3167 } 3168 } 3169 if (ncqe < budget) 3170 ncqe += bnxt_qplib_process_flush_list(&cq->qplib_cq, 3171 cqe + ncqe, 3172 budget - ncqe); 3173 3174 if (!ncqe) 3175 break; 3176 3177 for (i = 0; i < ncqe; i++, cqe++) { 3178 /* Transcribe each qplib_wqe back to ib_wc */ 3179 memset(wc, 0, sizeof(*wc)); 3180 3181 wc->wr_id = cqe->wr_id; 3182 wc->byte_len = cqe->length; 3183 qp = container_of 3184 ((struct bnxt_qplib_qp *) 3185 (unsigned long)(cqe->qp_handle), 3186 struct bnxt_re_qp, qplib_qp); 3187 if (!qp) { 3188 dev_err(rdev_to_dev(cq->rdev), 3189 "POLL CQ : bad QP handle"); 3190 continue; 3191 } 3192 wc->qp = &qp->ib_qp; 3193 wc->ex.imm_data = cqe->immdata; 3194 wc->src_qp = cqe->src_qp; 3195 memcpy(wc->smac, cqe->smac, ETH_ALEN); 3196 wc->port_num = 1; 3197 wc->vendor_err = cqe->status; 3198 3199 switch (cqe->opcode) { 3200 case CQ_BASE_CQE_TYPE_REQ: 3201 if (qp->rdev->qp1_sqp && qp->qplib_qp.id == 3202 qp->rdev->qp1_sqp->qplib_qp.id) { 3203 /* Handle this completion with 3204 * the stored completion 3205 */ 3206 memset(wc, 0, sizeof(*wc)); 3207 continue; 3208 } 3209 bnxt_re_process_req_wc(wc, cqe); 3210 break; 3211 case CQ_BASE_CQE_TYPE_RES_RAWETH_QP1: 3212 if (!cqe->status) { 3213 int rc = 0; 3214 3215 rc = bnxt_re_process_raw_qp_pkt_rx 3216 (qp, cqe); 3217 if (!rc) { 3218 memset(wc, 0, sizeof(*wc)); 3219 continue; 3220 } 3221 cqe->status = -1; 3222 } 3223 /* Errors need not be looped back. 3224 * But change the wr_id to the one 3225 * stored in the table 3226 */ 3227 tbl_idx = cqe->wr_id; 3228 sqp_entry = &cq->rdev->sqp_tbl[tbl_idx]; 3229 wc->wr_id = sqp_entry->wrid; 3230 bnxt_re_process_res_rawqp1_wc(wc, cqe); 3231 break; 3232 case CQ_BASE_CQE_TYPE_RES_RC: 3233 bnxt_re_process_res_rc_wc(wc, cqe); 3234 break; 3235 case CQ_BASE_CQE_TYPE_RES_UD: 3236 if (qp->rdev->qp1_sqp && qp->qplib_qp.id == 3237 qp->rdev->qp1_sqp->qplib_qp.id) { 3238 /* Handle this completion with 3239 * the stored completion 3240 */ 3241 if (cqe->status) { 3242 continue; 3243 } else { 3244 bnxt_re_process_res_shadow_qp_wc 3245 (qp, wc, cqe); 3246 break; 3247 } 3248 } 3249 bnxt_re_process_res_ud_wc(qp, wc, cqe); 3250 break; 3251 default: 3252 dev_err(rdev_to_dev(cq->rdev), 3253 "POLL CQ : type 0x%x not handled", 3254 cqe->opcode); 3255 continue; 3256 } 3257 wc++; 3258 budget--; 3259 } 3260 } 3261 exit: 3262 spin_unlock_irqrestore(&cq->cq_lock, flags); 3263 return num_entries - budget; 3264 } 3265 3266 int bnxt_re_req_notify_cq(struct ib_cq *ib_cq, 3267 enum ib_cq_notify_flags ib_cqn_flags) 3268 { 3269 struct bnxt_re_cq *cq = container_of(ib_cq, struct bnxt_re_cq, ib_cq); 3270 int type = 0, rc = 0; 3271 unsigned long flags; 3272 3273 spin_lock_irqsave(&cq->cq_lock, flags); 3274 /* Trigger on the very next completion */ 3275 if (ib_cqn_flags & IB_CQ_NEXT_COMP) 3276 type = DBC_DBC_TYPE_CQ_ARMALL; 3277 /* Trigger on the next solicited completion */ 3278 else if (ib_cqn_flags & IB_CQ_SOLICITED) 3279 type = DBC_DBC_TYPE_CQ_ARMSE; 3280 3281 /* Poll to see if there are missed events */ 3282 if ((ib_cqn_flags & IB_CQ_REPORT_MISSED_EVENTS) && 3283 !(bnxt_qplib_is_cq_empty(&cq->qplib_cq))) { 3284 rc = 1; 3285 goto exit; 3286 } 3287 bnxt_qplib_req_notify_cq(&cq->qplib_cq, type); 3288 3289 exit: 3290 spin_unlock_irqrestore(&cq->cq_lock, flags); 3291 return rc; 3292 } 3293 3294 /* Memory Regions */ 3295 struct ib_mr *bnxt_re_get_dma_mr(struct ib_pd *ib_pd, int mr_access_flags) 3296 { 3297 struct bnxt_re_pd *pd = container_of(ib_pd, struct bnxt_re_pd, ib_pd); 3298 struct bnxt_re_dev *rdev = pd->rdev; 3299 struct bnxt_re_mr *mr; 3300 u64 pbl = 0; 3301 int rc; 3302 3303 mr = kzalloc(sizeof(*mr), GFP_KERNEL); 3304 if (!mr) 3305 return ERR_PTR(-ENOMEM); 3306 3307 mr->rdev = rdev; 3308 mr->qplib_mr.pd = &pd->qplib_pd; 3309 mr->qplib_mr.flags = __from_ib_access_flags(mr_access_flags); 3310 mr->qplib_mr.type = CMDQ_ALLOCATE_MRW_MRW_FLAGS_PMR; 3311 3312 /* Allocate and register 0 as the address */ 3313 rc = bnxt_qplib_alloc_mrw(&rdev->qplib_res, &mr->qplib_mr); 3314 if (rc) 3315 goto fail; 3316 3317 mr->qplib_mr.hwq.level = PBL_LVL_MAX; 3318 mr->qplib_mr.total_size = -1; /* Infinte length */ 3319 rc = bnxt_qplib_reg_mr(&rdev->qplib_res, &mr->qplib_mr, &pbl, 0, false, 3320 PAGE_SIZE); 3321 if (rc) 3322 goto fail_mr; 3323 3324 mr->ib_mr.lkey = mr->qplib_mr.lkey; 3325 if (mr_access_flags & (IB_ACCESS_REMOTE_WRITE | IB_ACCESS_REMOTE_READ | 3326 IB_ACCESS_REMOTE_ATOMIC)) 3327 mr->ib_mr.rkey = mr->ib_mr.lkey; 3328 atomic_inc(&rdev->mr_count); 3329 3330 return &mr->ib_mr; 3331 3332 fail_mr: 3333 bnxt_qplib_free_mrw(&rdev->qplib_res, &mr->qplib_mr); 3334 fail: 3335 kfree(mr); 3336 return ERR_PTR(rc); 3337 } 3338 3339 int bnxt_re_dereg_mr(struct ib_mr *ib_mr, struct ib_udata *udata) 3340 { 3341 struct bnxt_re_mr *mr = container_of(ib_mr, struct bnxt_re_mr, ib_mr); 3342 struct bnxt_re_dev *rdev = mr->rdev; 3343 int rc; 3344 3345 rc = bnxt_qplib_free_mrw(&rdev->qplib_res, &mr->qplib_mr); 3346 if (rc) 3347 dev_err(rdev_to_dev(rdev), "Dereg MR failed: %#x\n", rc); 3348 3349 if (mr->pages) { 3350 rc = bnxt_qplib_free_fast_reg_page_list(&rdev->qplib_res, 3351 &mr->qplib_frpl); 3352 kfree(mr->pages); 3353 mr->npages = 0; 3354 mr->pages = NULL; 3355 } 3356 if (!IS_ERR_OR_NULL(mr->ib_umem)) 3357 ib_umem_release(mr->ib_umem); 3358 3359 kfree(mr); 3360 atomic_dec(&rdev->mr_count); 3361 return rc; 3362 } 3363 3364 static int bnxt_re_set_page(struct ib_mr *ib_mr, u64 addr) 3365 { 3366 struct bnxt_re_mr *mr = container_of(ib_mr, struct bnxt_re_mr, ib_mr); 3367 3368 if (unlikely(mr->npages == mr->qplib_frpl.max_pg_ptrs)) 3369 return -ENOMEM; 3370 3371 mr->pages[mr->npages++] = addr; 3372 return 0; 3373 } 3374 3375 int bnxt_re_map_mr_sg(struct ib_mr *ib_mr, struct scatterlist *sg, int sg_nents, 3376 unsigned int *sg_offset) 3377 { 3378 struct bnxt_re_mr *mr = container_of(ib_mr, struct bnxt_re_mr, ib_mr); 3379 3380 mr->npages = 0; 3381 return ib_sg_to_pages(ib_mr, sg, sg_nents, sg_offset, bnxt_re_set_page); 3382 } 3383 3384 struct ib_mr *bnxt_re_alloc_mr(struct ib_pd *ib_pd, enum ib_mr_type type, 3385 u32 max_num_sg, struct ib_udata *udata) 3386 { 3387 struct bnxt_re_pd *pd = container_of(ib_pd, struct bnxt_re_pd, ib_pd); 3388 struct bnxt_re_dev *rdev = pd->rdev; 3389 struct bnxt_re_mr *mr = NULL; 3390 int rc; 3391 3392 if (type != IB_MR_TYPE_MEM_REG) { 3393 dev_dbg(rdev_to_dev(rdev), "MR type 0x%x not supported", type); 3394 return ERR_PTR(-EINVAL); 3395 } 3396 if (max_num_sg > MAX_PBL_LVL_1_PGS) 3397 return ERR_PTR(-EINVAL); 3398 3399 mr = kzalloc(sizeof(*mr), GFP_KERNEL); 3400 if (!mr) 3401 return ERR_PTR(-ENOMEM); 3402 3403 mr->rdev = rdev; 3404 mr->qplib_mr.pd = &pd->qplib_pd; 3405 mr->qplib_mr.flags = BNXT_QPLIB_FR_PMR; 3406 mr->qplib_mr.type = CMDQ_ALLOCATE_MRW_MRW_FLAGS_PMR; 3407 3408 rc = bnxt_qplib_alloc_mrw(&rdev->qplib_res, &mr->qplib_mr); 3409 if (rc) 3410 goto bail; 3411 3412 mr->ib_mr.lkey = mr->qplib_mr.lkey; 3413 mr->ib_mr.rkey = mr->ib_mr.lkey; 3414 3415 mr->pages = kcalloc(max_num_sg, sizeof(u64), GFP_KERNEL); 3416 if (!mr->pages) { 3417 rc = -ENOMEM; 3418 goto fail; 3419 } 3420 rc = bnxt_qplib_alloc_fast_reg_page_list(&rdev->qplib_res, 3421 &mr->qplib_frpl, max_num_sg); 3422 if (rc) { 3423 dev_err(rdev_to_dev(rdev), 3424 "Failed to allocate HW FR page list"); 3425 goto fail_mr; 3426 } 3427 3428 atomic_inc(&rdev->mr_count); 3429 return &mr->ib_mr; 3430 3431 fail_mr: 3432 kfree(mr->pages); 3433 fail: 3434 bnxt_qplib_free_mrw(&rdev->qplib_res, &mr->qplib_mr); 3435 bail: 3436 kfree(mr); 3437 return ERR_PTR(rc); 3438 } 3439 3440 struct ib_mw *bnxt_re_alloc_mw(struct ib_pd *ib_pd, enum ib_mw_type type, 3441 struct ib_udata *udata) 3442 { 3443 struct bnxt_re_pd *pd = container_of(ib_pd, struct bnxt_re_pd, ib_pd); 3444 struct bnxt_re_dev *rdev = pd->rdev; 3445 struct bnxt_re_mw *mw; 3446 int rc; 3447 3448 mw = kzalloc(sizeof(*mw), GFP_KERNEL); 3449 if (!mw) 3450 return ERR_PTR(-ENOMEM); 3451 mw->rdev = rdev; 3452 mw->qplib_mw.pd = &pd->qplib_pd; 3453 3454 mw->qplib_mw.type = (type == IB_MW_TYPE_1 ? 3455 CMDQ_ALLOCATE_MRW_MRW_FLAGS_MW_TYPE1 : 3456 CMDQ_ALLOCATE_MRW_MRW_FLAGS_MW_TYPE2B); 3457 rc = bnxt_qplib_alloc_mrw(&rdev->qplib_res, &mw->qplib_mw); 3458 if (rc) { 3459 dev_err(rdev_to_dev(rdev), "Allocate MW failed!"); 3460 goto fail; 3461 } 3462 mw->ib_mw.rkey = mw->qplib_mw.rkey; 3463 3464 atomic_inc(&rdev->mw_count); 3465 return &mw->ib_mw; 3466 3467 fail: 3468 kfree(mw); 3469 return ERR_PTR(rc); 3470 } 3471 3472 int bnxt_re_dealloc_mw(struct ib_mw *ib_mw) 3473 { 3474 struct bnxt_re_mw *mw = container_of(ib_mw, struct bnxt_re_mw, ib_mw); 3475 struct bnxt_re_dev *rdev = mw->rdev; 3476 int rc; 3477 3478 rc = bnxt_qplib_free_mrw(&rdev->qplib_res, &mw->qplib_mw); 3479 if (rc) { 3480 dev_err(rdev_to_dev(rdev), "Free MW failed: %#x\n", rc); 3481 return rc; 3482 } 3483 3484 kfree(mw); 3485 atomic_dec(&rdev->mw_count); 3486 return rc; 3487 } 3488 3489 static int bnxt_re_page_size_ok(int page_shift) 3490 { 3491 switch (page_shift) { 3492 case CMDQ_REGISTER_MR_LOG2_PBL_PG_SIZE_PG_4K: 3493 case CMDQ_REGISTER_MR_LOG2_PBL_PG_SIZE_PG_8K: 3494 case CMDQ_REGISTER_MR_LOG2_PBL_PG_SIZE_PG_64K: 3495 case CMDQ_REGISTER_MR_LOG2_PBL_PG_SIZE_PG_2M: 3496 case CMDQ_REGISTER_MR_LOG2_PBL_PG_SIZE_PG_256K: 3497 case CMDQ_REGISTER_MR_LOG2_PBL_PG_SIZE_PG_1M: 3498 case CMDQ_REGISTER_MR_LOG2_PBL_PG_SIZE_PG_4M: 3499 case CMDQ_REGISTER_MR_LOG2_PBL_PG_SIZE_PG_1G: 3500 return 1; 3501 default: 3502 return 0; 3503 } 3504 } 3505 3506 static int fill_umem_pbl_tbl(struct ib_umem *umem, u64 *pbl_tbl_orig, 3507 int page_shift) 3508 { 3509 u64 *pbl_tbl = pbl_tbl_orig; 3510 u64 page_size = BIT_ULL(page_shift); 3511 struct ib_block_iter biter; 3512 3513 rdma_for_each_block(umem->sg_head.sgl, &biter, umem->nmap, page_size) 3514 *pbl_tbl++ = rdma_block_iter_dma_address(&biter); 3515 3516 return pbl_tbl - pbl_tbl_orig; 3517 } 3518 3519 /* uverbs */ 3520 struct ib_mr *bnxt_re_reg_user_mr(struct ib_pd *ib_pd, u64 start, u64 length, 3521 u64 virt_addr, int mr_access_flags, 3522 struct ib_udata *udata) 3523 { 3524 struct bnxt_re_pd *pd = container_of(ib_pd, struct bnxt_re_pd, ib_pd); 3525 struct bnxt_re_dev *rdev = pd->rdev; 3526 struct bnxt_re_mr *mr; 3527 struct ib_umem *umem; 3528 u64 *pbl_tbl = NULL; 3529 int umem_pgs, page_shift, rc; 3530 3531 if (length > BNXT_RE_MAX_MR_SIZE) { 3532 dev_err(rdev_to_dev(rdev), "MR Size: %lld > Max supported:%lld\n", 3533 length, BNXT_RE_MAX_MR_SIZE); 3534 return ERR_PTR(-ENOMEM); 3535 } 3536 3537 mr = kzalloc(sizeof(*mr), GFP_KERNEL); 3538 if (!mr) 3539 return ERR_PTR(-ENOMEM); 3540 3541 mr->rdev = rdev; 3542 mr->qplib_mr.pd = &pd->qplib_pd; 3543 mr->qplib_mr.flags = __from_ib_access_flags(mr_access_flags); 3544 mr->qplib_mr.type = CMDQ_ALLOCATE_MRW_MRW_FLAGS_MR; 3545 3546 rc = bnxt_qplib_alloc_mrw(&rdev->qplib_res, &mr->qplib_mr); 3547 if (rc) { 3548 dev_err(rdev_to_dev(rdev), "Failed to allocate MR"); 3549 goto free_mr; 3550 } 3551 /* The fixed portion of the rkey is the same as the lkey */ 3552 mr->ib_mr.rkey = mr->qplib_mr.rkey; 3553 3554 umem = ib_umem_get(udata, start, length, mr_access_flags, 0); 3555 if (IS_ERR(umem)) { 3556 dev_err(rdev_to_dev(rdev), "Failed to get umem"); 3557 rc = -EFAULT; 3558 goto free_mrw; 3559 } 3560 mr->ib_umem = umem; 3561 3562 mr->qplib_mr.va = virt_addr; 3563 umem_pgs = ib_umem_page_count(umem); 3564 if (!umem_pgs) { 3565 dev_err(rdev_to_dev(rdev), "umem is invalid!"); 3566 rc = -EINVAL; 3567 goto free_umem; 3568 } 3569 mr->qplib_mr.total_size = length; 3570 3571 pbl_tbl = kcalloc(umem_pgs, sizeof(u64 *), GFP_KERNEL); 3572 if (!pbl_tbl) { 3573 rc = -ENOMEM; 3574 goto free_umem; 3575 } 3576 3577 page_shift = __ffs(ib_umem_find_best_pgsz(umem, 3578 BNXT_RE_PAGE_SIZE_4K | BNXT_RE_PAGE_SIZE_2M, 3579 virt_addr)); 3580 3581 if (!bnxt_re_page_size_ok(page_shift)) { 3582 dev_err(rdev_to_dev(rdev), "umem page size unsupported!"); 3583 rc = -EFAULT; 3584 goto fail; 3585 } 3586 3587 if (page_shift == BNXT_RE_PAGE_SHIFT_4K && 3588 length > BNXT_RE_MAX_MR_SIZE_LOW) { 3589 dev_err(rdev_to_dev(rdev), "Requested MR Sz:%llu Max sup:%llu", 3590 length, (u64)BNXT_RE_MAX_MR_SIZE_LOW); 3591 rc = -EINVAL; 3592 goto fail; 3593 } 3594 3595 /* Map umem buf ptrs to the PBL */ 3596 umem_pgs = fill_umem_pbl_tbl(umem, pbl_tbl, page_shift); 3597 rc = bnxt_qplib_reg_mr(&rdev->qplib_res, &mr->qplib_mr, pbl_tbl, 3598 umem_pgs, false, 1 << page_shift); 3599 if (rc) { 3600 dev_err(rdev_to_dev(rdev), "Failed to register user MR"); 3601 goto fail; 3602 } 3603 3604 kfree(pbl_tbl); 3605 3606 mr->ib_mr.lkey = mr->qplib_mr.lkey; 3607 mr->ib_mr.rkey = mr->qplib_mr.lkey; 3608 atomic_inc(&rdev->mr_count); 3609 3610 return &mr->ib_mr; 3611 fail: 3612 kfree(pbl_tbl); 3613 free_umem: 3614 ib_umem_release(umem); 3615 free_mrw: 3616 bnxt_qplib_free_mrw(&rdev->qplib_res, &mr->qplib_mr); 3617 free_mr: 3618 kfree(mr); 3619 return ERR_PTR(rc); 3620 } 3621 3622 int bnxt_re_alloc_ucontext(struct ib_ucontext *ctx, struct ib_udata *udata) 3623 { 3624 struct ib_device *ibdev = ctx->device; 3625 struct bnxt_re_ucontext *uctx = 3626 container_of(ctx, struct bnxt_re_ucontext, ib_uctx); 3627 struct bnxt_re_dev *rdev = to_bnxt_re_dev(ibdev, ibdev); 3628 struct bnxt_qplib_dev_attr *dev_attr = &rdev->dev_attr; 3629 struct bnxt_re_uctx_resp resp; 3630 u32 chip_met_rev_num = 0; 3631 int rc; 3632 3633 dev_dbg(rdev_to_dev(rdev), "ABI version requested %d", 3634 ibdev->uverbs_abi_ver); 3635 3636 if (ibdev->uverbs_abi_ver != BNXT_RE_ABI_VERSION) { 3637 dev_dbg(rdev_to_dev(rdev), " is different from the device %d ", 3638 BNXT_RE_ABI_VERSION); 3639 return -EPERM; 3640 } 3641 3642 uctx->rdev = rdev; 3643 3644 uctx->shpg = (void *)__get_free_page(GFP_KERNEL); 3645 if (!uctx->shpg) { 3646 rc = -ENOMEM; 3647 goto fail; 3648 } 3649 spin_lock_init(&uctx->sh_lock); 3650 3651 resp.comp_mask = BNXT_RE_UCNTX_CMASK_HAVE_CCTX; 3652 chip_met_rev_num = rdev->chip_ctx.chip_num; 3653 chip_met_rev_num |= ((u32)rdev->chip_ctx.chip_rev & 0xFF) << 3654 BNXT_RE_CHIP_ID0_CHIP_REV_SFT; 3655 chip_met_rev_num |= ((u32)rdev->chip_ctx.chip_metal & 0xFF) << 3656 BNXT_RE_CHIP_ID0_CHIP_MET_SFT; 3657 resp.chip_id0 = chip_met_rev_num; 3658 /* Future extension of chip info */ 3659 resp.chip_id1 = 0; 3660 /*Temp, Use xa_alloc instead */ 3661 resp.dev_id = rdev->en_dev->pdev->devfn; 3662 resp.max_qp = rdev->qplib_ctx.qpc_count; 3663 resp.pg_size = PAGE_SIZE; 3664 resp.cqe_sz = sizeof(struct cq_base); 3665 resp.max_cqd = dev_attr->max_cq_wqes; 3666 resp.rsvd = 0; 3667 3668 rc = ib_copy_to_udata(udata, &resp, min(udata->outlen, sizeof(resp))); 3669 if (rc) { 3670 dev_err(rdev_to_dev(rdev), "Failed to copy user context"); 3671 rc = -EFAULT; 3672 goto cfail; 3673 } 3674 3675 return 0; 3676 cfail: 3677 free_page((unsigned long)uctx->shpg); 3678 uctx->shpg = NULL; 3679 fail: 3680 return rc; 3681 } 3682 3683 void bnxt_re_dealloc_ucontext(struct ib_ucontext *ib_uctx) 3684 { 3685 struct bnxt_re_ucontext *uctx = container_of(ib_uctx, 3686 struct bnxt_re_ucontext, 3687 ib_uctx); 3688 3689 struct bnxt_re_dev *rdev = uctx->rdev; 3690 3691 if (uctx->shpg) 3692 free_page((unsigned long)uctx->shpg); 3693 3694 if (uctx->dpi.dbr) { 3695 /* Free DPI only if this is the first PD allocated by the 3696 * application and mark the context dpi as NULL 3697 */ 3698 bnxt_qplib_dealloc_dpi(&rdev->qplib_res, 3699 &rdev->qplib_res.dpi_tbl, &uctx->dpi); 3700 uctx->dpi.dbr = NULL; 3701 } 3702 } 3703 3704 /* Helper function to mmap the virtual memory from user app */ 3705 int bnxt_re_mmap(struct ib_ucontext *ib_uctx, struct vm_area_struct *vma) 3706 { 3707 struct bnxt_re_ucontext *uctx = container_of(ib_uctx, 3708 struct bnxt_re_ucontext, 3709 ib_uctx); 3710 struct bnxt_re_dev *rdev = uctx->rdev; 3711 u64 pfn; 3712 3713 if (vma->vm_end - vma->vm_start != PAGE_SIZE) 3714 return -EINVAL; 3715 3716 if (vma->vm_pgoff) { 3717 vma->vm_page_prot = pgprot_noncached(vma->vm_page_prot); 3718 if (io_remap_pfn_range(vma, vma->vm_start, vma->vm_pgoff, 3719 PAGE_SIZE, vma->vm_page_prot)) { 3720 dev_err(rdev_to_dev(rdev), "Failed to map DPI"); 3721 return -EAGAIN; 3722 } 3723 } else { 3724 pfn = virt_to_phys(uctx->shpg) >> PAGE_SHIFT; 3725 if (remap_pfn_range(vma, vma->vm_start, 3726 pfn, PAGE_SIZE, vma->vm_page_prot)) { 3727 dev_err(rdev_to_dev(rdev), 3728 "Failed to map shared page"); 3729 return -EAGAIN; 3730 } 3731 } 3732 3733 return 0; 3734 } 3735