1 /* 2 * Broadcom NetXtreme-E RoCE driver. 3 * 4 * Copyright (c) 2016 - 2017, Broadcom. All rights reserved. The term 5 * Broadcom refers to Broadcom Limited and/or its subsidiaries. 6 * 7 * This software is available to you under a choice of one of two 8 * licenses. You may choose to be licensed under the terms of the GNU 9 * General Public License (GPL) Version 2, available from the file 10 * COPYING in the main directory of this source tree, or the 11 * BSD license below: 12 * 13 * Redistribution and use in source and binary forms, with or without 14 * modification, are permitted provided that the following conditions 15 * are met: 16 * 17 * 1. Redistributions of source code must retain the above copyright 18 * notice, this list of conditions and the following disclaimer. 19 * 2. Redistributions in binary form must reproduce the above copyright 20 * notice, this list of conditions and the following disclaimer in 21 * the documentation and/or other materials provided with the 22 * distribution. 23 * 24 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' 25 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, 26 * THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR 27 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS 28 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 29 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 30 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR 31 * BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, 32 * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE 33 * OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN 34 * IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 35 * 36 * Description: IB Verbs interpreter 37 */ 38 39 #include <linux/interrupt.h> 40 #include <linux/types.h> 41 #include <linux/pci.h> 42 #include <linux/netdevice.h> 43 #include <linux/if_ether.h> 44 45 #include <rdma/ib_verbs.h> 46 #include <rdma/ib_user_verbs.h> 47 #include <rdma/ib_umem.h> 48 #include <rdma/ib_addr.h> 49 #include <rdma/ib_mad.h> 50 #include <rdma/ib_cache.h> 51 52 #include "bnxt_ulp.h" 53 54 #include "roce_hsi.h" 55 #include "qplib_res.h" 56 #include "qplib_sp.h" 57 #include "qplib_fp.h" 58 #include "qplib_rcfw.h" 59 60 #include "bnxt_re.h" 61 #include "ib_verbs.h" 62 #include <rdma/bnxt_re-abi.h> 63 64 static int __from_ib_access_flags(int iflags) 65 { 66 int qflags = 0; 67 68 if (iflags & IB_ACCESS_LOCAL_WRITE) 69 qflags |= BNXT_QPLIB_ACCESS_LOCAL_WRITE; 70 if (iflags & IB_ACCESS_REMOTE_READ) 71 qflags |= BNXT_QPLIB_ACCESS_REMOTE_READ; 72 if (iflags & IB_ACCESS_REMOTE_WRITE) 73 qflags |= BNXT_QPLIB_ACCESS_REMOTE_WRITE; 74 if (iflags & IB_ACCESS_REMOTE_ATOMIC) 75 qflags |= BNXT_QPLIB_ACCESS_REMOTE_ATOMIC; 76 if (iflags & IB_ACCESS_MW_BIND) 77 qflags |= BNXT_QPLIB_ACCESS_MW_BIND; 78 if (iflags & IB_ZERO_BASED) 79 qflags |= BNXT_QPLIB_ACCESS_ZERO_BASED; 80 if (iflags & IB_ACCESS_ON_DEMAND) 81 qflags |= BNXT_QPLIB_ACCESS_ON_DEMAND; 82 return qflags; 83 }; 84 85 static enum ib_access_flags __to_ib_access_flags(int qflags) 86 { 87 enum ib_access_flags iflags = 0; 88 89 if (qflags & BNXT_QPLIB_ACCESS_LOCAL_WRITE) 90 iflags |= IB_ACCESS_LOCAL_WRITE; 91 if (qflags & BNXT_QPLIB_ACCESS_REMOTE_WRITE) 92 iflags |= IB_ACCESS_REMOTE_WRITE; 93 if (qflags & BNXT_QPLIB_ACCESS_REMOTE_READ) 94 iflags |= IB_ACCESS_REMOTE_READ; 95 if (qflags & BNXT_QPLIB_ACCESS_REMOTE_ATOMIC) 96 iflags |= IB_ACCESS_REMOTE_ATOMIC; 97 if (qflags & BNXT_QPLIB_ACCESS_MW_BIND) 98 iflags |= IB_ACCESS_MW_BIND; 99 if (qflags & BNXT_QPLIB_ACCESS_ZERO_BASED) 100 iflags |= IB_ZERO_BASED; 101 if (qflags & BNXT_QPLIB_ACCESS_ON_DEMAND) 102 iflags |= IB_ACCESS_ON_DEMAND; 103 return iflags; 104 }; 105 106 static int bnxt_re_build_sgl(struct ib_sge *ib_sg_list, 107 struct bnxt_qplib_sge *sg_list, int num) 108 { 109 int i, total = 0; 110 111 for (i = 0; i < num; i++) { 112 sg_list[i].addr = ib_sg_list[i].addr; 113 sg_list[i].lkey = ib_sg_list[i].lkey; 114 sg_list[i].size = ib_sg_list[i].length; 115 total += sg_list[i].size; 116 } 117 return total; 118 } 119 120 /* Device */ 121 struct net_device *bnxt_re_get_netdev(struct ib_device *ibdev, u8 port_num) 122 { 123 struct bnxt_re_dev *rdev = to_bnxt_re_dev(ibdev, ibdev); 124 struct net_device *netdev = NULL; 125 126 rcu_read_lock(); 127 if (rdev) 128 netdev = rdev->netdev; 129 if (netdev) 130 dev_hold(netdev); 131 132 rcu_read_unlock(); 133 return netdev; 134 } 135 136 int bnxt_re_query_device(struct ib_device *ibdev, 137 struct ib_device_attr *ib_attr, 138 struct ib_udata *udata) 139 { 140 struct bnxt_re_dev *rdev = to_bnxt_re_dev(ibdev, ibdev); 141 struct bnxt_qplib_dev_attr *dev_attr = &rdev->dev_attr; 142 143 memset(ib_attr, 0, sizeof(*ib_attr)); 144 memcpy(&ib_attr->fw_ver, dev_attr->fw_ver, 145 min(sizeof(dev_attr->fw_ver), 146 sizeof(ib_attr->fw_ver))); 147 bnxt_qplib_get_guid(rdev->netdev->dev_addr, 148 (u8 *)&ib_attr->sys_image_guid); 149 ib_attr->max_mr_size = BNXT_RE_MAX_MR_SIZE; 150 ib_attr->page_size_cap = BNXT_RE_PAGE_SIZE_4K | BNXT_RE_PAGE_SIZE_2M; 151 152 ib_attr->vendor_id = rdev->en_dev->pdev->vendor; 153 ib_attr->vendor_part_id = rdev->en_dev->pdev->device; 154 ib_attr->hw_ver = rdev->en_dev->pdev->subsystem_device; 155 ib_attr->max_qp = dev_attr->max_qp; 156 ib_attr->max_qp_wr = dev_attr->max_qp_wqes; 157 ib_attr->device_cap_flags = 158 IB_DEVICE_CURR_QP_STATE_MOD 159 | IB_DEVICE_RC_RNR_NAK_GEN 160 | IB_DEVICE_SHUTDOWN_PORT 161 | IB_DEVICE_SYS_IMAGE_GUID 162 | IB_DEVICE_LOCAL_DMA_LKEY 163 | IB_DEVICE_RESIZE_MAX_WR 164 | IB_DEVICE_PORT_ACTIVE_EVENT 165 | IB_DEVICE_N_NOTIFY_CQ 166 | IB_DEVICE_MEM_WINDOW 167 | IB_DEVICE_MEM_WINDOW_TYPE_2B 168 | IB_DEVICE_MEM_MGT_EXTENSIONS; 169 ib_attr->max_send_sge = dev_attr->max_qp_sges; 170 ib_attr->max_recv_sge = dev_attr->max_qp_sges; 171 ib_attr->max_sge_rd = dev_attr->max_qp_sges; 172 ib_attr->max_cq = dev_attr->max_cq; 173 ib_attr->max_cqe = dev_attr->max_cq_wqes; 174 ib_attr->max_mr = dev_attr->max_mr; 175 ib_attr->max_pd = dev_attr->max_pd; 176 ib_attr->max_qp_rd_atom = dev_attr->max_qp_rd_atom; 177 ib_attr->max_qp_init_rd_atom = dev_attr->max_qp_init_rd_atom; 178 ib_attr->atomic_cap = IB_ATOMIC_NONE; 179 ib_attr->masked_atomic_cap = IB_ATOMIC_NONE; 180 181 ib_attr->max_ee_rd_atom = 0; 182 ib_attr->max_res_rd_atom = 0; 183 ib_attr->max_ee_init_rd_atom = 0; 184 ib_attr->max_ee = 0; 185 ib_attr->max_rdd = 0; 186 ib_attr->max_mw = dev_attr->max_mw; 187 ib_attr->max_raw_ipv6_qp = 0; 188 ib_attr->max_raw_ethy_qp = dev_attr->max_raw_ethy_qp; 189 ib_attr->max_mcast_grp = 0; 190 ib_attr->max_mcast_qp_attach = 0; 191 ib_attr->max_total_mcast_qp_attach = 0; 192 ib_attr->max_ah = dev_attr->max_ah; 193 194 ib_attr->max_fmr = 0; 195 ib_attr->max_map_per_fmr = 0; 196 197 ib_attr->max_srq = dev_attr->max_srq; 198 ib_attr->max_srq_wr = dev_attr->max_srq_wqes; 199 ib_attr->max_srq_sge = dev_attr->max_srq_sges; 200 201 ib_attr->max_fast_reg_page_list_len = MAX_PBL_LVL_1_PGS; 202 203 ib_attr->max_pkeys = 1; 204 ib_attr->local_ca_ack_delay = BNXT_RE_DEFAULT_ACK_DELAY; 205 return 0; 206 } 207 208 int bnxt_re_modify_device(struct ib_device *ibdev, 209 int device_modify_mask, 210 struct ib_device_modify *device_modify) 211 { 212 switch (device_modify_mask) { 213 case IB_DEVICE_MODIFY_SYS_IMAGE_GUID: 214 /* Modify the GUID requires the modification of the GID table */ 215 /* GUID should be made as READ-ONLY */ 216 break; 217 case IB_DEVICE_MODIFY_NODE_DESC: 218 /* Node Desc should be made as READ-ONLY */ 219 break; 220 default: 221 break; 222 } 223 return 0; 224 } 225 226 /* Port */ 227 int bnxt_re_query_port(struct ib_device *ibdev, u8 port_num, 228 struct ib_port_attr *port_attr) 229 { 230 struct bnxt_re_dev *rdev = to_bnxt_re_dev(ibdev, ibdev); 231 struct bnxt_qplib_dev_attr *dev_attr = &rdev->dev_attr; 232 233 memset(port_attr, 0, sizeof(*port_attr)); 234 235 if (netif_running(rdev->netdev) && netif_carrier_ok(rdev->netdev)) { 236 port_attr->state = IB_PORT_ACTIVE; 237 port_attr->phys_state = 5; 238 } else { 239 port_attr->state = IB_PORT_DOWN; 240 port_attr->phys_state = 3; 241 } 242 port_attr->max_mtu = IB_MTU_4096; 243 port_attr->active_mtu = iboe_get_mtu(rdev->netdev->mtu); 244 port_attr->gid_tbl_len = dev_attr->max_sgid; 245 port_attr->port_cap_flags = IB_PORT_CM_SUP | IB_PORT_REINIT_SUP | 246 IB_PORT_DEVICE_MGMT_SUP | 247 IB_PORT_VENDOR_CLASS_SUP; 248 port_attr->ip_gids = true; 249 250 port_attr->max_msg_sz = (u32)BNXT_RE_MAX_MR_SIZE_LOW; 251 port_attr->bad_pkey_cntr = 0; 252 port_attr->qkey_viol_cntr = 0; 253 port_attr->pkey_tbl_len = dev_attr->max_pkey; 254 port_attr->lid = 0; 255 port_attr->sm_lid = 0; 256 port_attr->lmc = 0; 257 port_attr->max_vl_num = 4; 258 port_attr->sm_sl = 0; 259 port_attr->subnet_timeout = 0; 260 port_attr->init_type_reply = 0; 261 port_attr->active_speed = rdev->active_speed; 262 port_attr->active_width = rdev->active_width; 263 264 return 0; 265 } 266 267 int bnxt_re_get_port_immutable(struct ib_device *ibdev, u8 port_num, 268 struct ib_port_immutable *immutable) 269 { 270 struct ib_port_attr port_attr; 271 272 if (bnxt_re_query_port(ibdev, port_num, &port_attr)) 273 return -EINVAL; 274 275 immutable->pkey_tbl_len = port_attr.pkey_tbl_len; 276 immutable->gid_tbl_len = port_attr.gid_tbl_len; 277 immutable->core_cap_flags = RDMA_CORE_PORT_IBA_ROCE; 278 immutable->core_cap_flags |= RDMA_CORE_CAP_PROT_ROCE_UDP_ENCAP; 279 immutable->max_mad_size = IB_MGMT_MAD_SIZE; 280 return 0; 281 } 282 283 void bnxt_re_query_fw_str(struct ib_device *ibdev, char *str) 284 { 285 struct bnxt_re_dev *rdev = to_bnxt_re_dev(ibdev, ibdev); 286 287 snprintf(str, IB_FW_VERSION_NAME_MAX, "%d.%d.%d.%d", 288 rdev->dev_attr.fw_ver[0], rdev->dev_attr.fw_ver[1], 289 rdev->dev_attr.fw_ver[2], rdev->dev_attr.fw_ver[3]); 290 } 291 292 int bnxt_re_query_pkey(struct ib_device *ibdev, u8 port_num, 293 u16 index, u16 *pkey) 294 { 295 struct bnxt_re_dev *rdev = to_bnxt_re_dev(ibdev, ibdev); 296 297 /* Ignore port_num */ 298 299 memset(pkey, 0, sizeof(*pkey)); 300 return bnxt_qplib_get_pkey(&rdev->qplib_res, 301 &rdev->qplib_res.pkey_tbl, index, pkey); 302 } 303 304 int bnxt_re_query_gid(struct ib_device *ibdev, u8 port_num, 305 int index, union ib_gid *gid) 306 { 307 struct bnxt_re_dev *rdev = to_bnxt_re_dev(ibdev, ibdev); 308 int rc = 0; 309 310 /* Ignore port_num */ 311 memset(gid, 0, sizeof(*gid)); 312 rc = bnxt_qplib_get_sgid(&rdev->qplib_res, 313 &rdev->qplib_res.sgid_tbl, index, 314 (struct bnxt_qplib_gid *)gid); 315 return rc; 316 } 317 318 int bnxt_re_del_gid(const struct ib_gid_attr *attr, void **context) 319 { 320 int rc = 0; 321 struct bnxt_re_gid_ctx *ctx, **ctx_tbl; 322 struct bnxt_re_dev *rdev = to_bnxt_re_dev(attr->device, ibdev); 323 struct bnxt_qplib_sgid_tbl *sgid_tbl = &rdev->qplib_res.sgid_tbl; 324 struct bnxt_qplib_gid *gid_to_del; 325 326 /* Delete the entry from the hardware */ 327 ctx = *context; 328 if (!ctx) 329 return -EINVAL; 330 331 if (sgid_tbl && sgid_tbl->active) { 332 if (ctx->idx >= sgid_tbl->max) 333 return -EINVAL; 334 gid_to_del = &sgid_tbl->tbl[ctx->idx]; 335 /* DEL_GID is called in WQ context(netdevice_event_work_handler) 336 * or via the ib_unregister_device path. In the former case QP1 337 * may not be destroyed yet, in which case just return as FW 338 * needs that entry to be present and will fail it's deletion. 339 * We could get invoked again after QP1 is destroyed OR get an 340 * ADD_GID call with a different GID value for the same index 341 * where we issue MODIFY_GID cmd to update the GID entry -- TBD 342 */ 343 if (ctx->idx == 0 && 344 rdma_link_local_addr((struct in6_addr *)gid_to_del) && 345 ctx->refcnt == 1 && rdev->qp1_sqp) { 346 dev_dbg(rdev_to_dev(rdev), 347 "Trying to delete GID0 while QP1 is alive\n"); 348 return -EFAULT; 349 } 350 ctx->refcnt--; 351 if (!ctx->refcnt) { 352 rc = bnxt_qplib_del_sgid(sgid_tbl, gid_to_del, true); 353 if (rc) { 354 dev_err(rdev_to_dev(rdev), 355 "Failed to remove GID: %#x", rc); 356 } else { 357 ctx_tbl = sgid_tbl->ctx; 358 ctx_tbl[ctx->idx] = NULL; 359 kfree(ctx); 360 } 361 } 362 } else { 363 return -EINVAL; 364 } 365 return rc; 366 } 367 368 int bnxt_re_add_gid(const struct ib_gid_attr *attr, void **context) 369 { 370 int rc; 371 u32 tbl_idx = 0; 372 u16 vlan_id = 0xFFFF; 373 struct bnxt_re_gid_ctx *ctx, **ctx_tbl; 374 struct bnxt_re_dev *rdev = to_bnxt_re_dev(attr->device, ibdev); 375 struct bnxt_qplib_sgid_tbl *sgid_tbl = &rdev->qplib_res.sgid_tbl; 376 377 if ((attr->ndev) && is_vlan_dev(attr->ndev)) 378 vlan_id = vlan_dev_vlan_id(attr->ndev); 379 380 rc = bnxt_qplib_add_sgid(sgid_tbl, (struct bnxt_qplib_gid *)&attr->gid, 381 rdev->qplib_res.netdev->dev_addr, 382 vlan_id, true, &tbl_idx); 383 if (rc == -EALREADY) { 384 ctx_tbl = sgid_tbl->ctx; 385 ctx_tbl[tbl_idx]->refcnt++; 386 *context = ctx_tbl[tbl_idx]; 387 return 0; 388 } 389 390 if (rc < 0) { 391 dev_err(rdev_to_dev(rdev), "Failed to add GID: %#x", rc); 392 return rc; 393 } 394 395 ctx = kmalloc(sizeof(*ctx), GFP_KERNEL); 396 if (!ctx) 397 return -ENOMEM; 398 ctx_tbl = sgid_tbl->ctx; 399 ctx->idx = tbl_idx; 400 ctx->refcnt = 1; 401 ctx_tbl[tbl_idx] = ctx; 402 *context = ctx; 403 404 return rc; 405 } 406 407 enum rdma_link_layer bnxt_re_get_link_layer(struct ib_device *ibdev, 408 u8 port_num) 409 { 410 return IB_LINK_LAYER_ETHERNET; 411 } 412 413 #define BNXT_RE_FENCE_PBL_SIZE DIV_ROUND_UP(BNXT_RE_FENCE_BYTES, PAGE_SIZE) 414 415 static void bnxt_re_create_fence_wqe(struct bnxt_re_pd *pd) 416 { 417 struct bnxt_re_fence_data *fence = &pd->fence; 418 struct ib_mr *ib_mr = &fence->mr->ib_mr; 419 struct bnxt_qplib_swqe *wqe = &fence->bind_wqe; 420 421 memset(wqe, 0, sizeof(*wqe)); 422 wqe->type = BNXT_QPLIB_SWQE_TYPE_BIND_MW; 423 wqe->wr_id = BNXT_QPLIB_FENCE_WRID; 424 wqe->flags |= BNXT_QPLIB_SWQE_FLAGS_SIGNAL_COMP; 425 wqe->flags |= BNXT_QPLIB_SWQE_FLAGS_UC_FENCE; 426 wqe->bind.zero_based = false; 427 wqe->bind.parent_l_key = ib_mr->lkey; 428 wqe->bind.va = (u64)(unsigned long)fence->va; 429 wqe->bind.length = fence->size; 430 wqe->bind.access_cntl = __from_ib_access_flags(IB_ACCESS_REMOTE_READ); 431 wqe->bind.mw_type = SQ_BIND_MW_TYPE_TYPE1; 432 433 /* Save the initial rkey in fence structure for now; 434 * wqe->bind.r_key will be set at (re)bind time. 435 */ 436 fence->bind_rkey = ib_inc_rkey(fence->mw->rkey); 437 } 438 439 static int bnxt_re_bind_fence_mw(struct bnxt_qplib_qp *qplib_qp) 440 { 441 struct bnxt_re_qp *qp = container_of(qplib_qp, struct bnxt_re_qp, 442 qplib_qp); 443 struct ib_pd *ib_pd = qp->ib_qp.pd; 444 struct bnxt_re_pd *pd = container_of(ib_pd, struct bnxt_re_pd, ib_pd); 445 struct bnxt_re_fence_data *fence = &pd->fence; 446 struct bnxt_qplib_swqe *fence_wqe = &fence->bind_wqe; 447 struct bnxt_qplib_swqe wqe; 448 int rc; 449 450 memcpy(&wqe, fence_wqe, sizeof(wqe)); 451 wqe.bind.r_key = fence->bind_rkey; 452 fence->bind_rkey = ib_inc_rkey(fence->bind_rkey); 453 454 dev_dbg(rdev_to_dev(qp->rdev), 455 "Posting bind fence-WQE: rkey: %#x QP: %d PD: %p\n", 456 wqe.bind.r_key, qp->qplib_qp.id, pd); 457 rc = bnxt_qplib_post_send(&qp->qplib_qp, &wqe); 458 if (rc) { 459 dev_err(rdev_to_dev(qp->rdev), "Failed to bind fence-WQE\n"); 460 return rc; 461 } 462 bnxt_qplib_post_send_db(&qp->qplib_qp); 463 464 return rc; 465 } 466 467 static void bnxt_re_destroy_fence_mr(struct bnxt_re_pd *pd) 468 { 469 struct bnxt_re_fence_data *fence = &pd->fence; 470 struct bnxt_re_dev *rdev = pd->rdev; 471 struct device *dev = &rdev->en_dev->pdev->dev; 472 struct bnxt_re_mr *mr = fence->mr; 473 474 if (fence->mw) { 475 bnxt_re_dealloc_mw(fence->mw); 476 fence->mw = NULL; 477 } 478 if (mr) { 479 if (mr->ib_mr.rkey) 480 bnxt_qplib_dereg_mrw(&rdev->qplib_res, &mr->qplib_mr, 481 true); 482 if (mr->ib_mr.lkey) 483 bnxt_qplib_free_mrw(&rdev->qplib_res, &mr->qplib_mr); 484 kfree(mr); 485 fence->mr = NULL; 486 } 487 if (fence->dma_addr) { 488 dma_unmap_single(dev, fence->dma_addr, BNXT_RE_FENCE_BYTES, 489 DMA_BIDIRECTIONAL); 490 fence->dma_addr = 0; 491 } 492 } 493 494 static int bnxt_re_create_fence_mr(struct bnxt_re_pd *pd) 495 { 496 int mr_access_flags = IB_ACCESS_LOCAL_WRITE | IB_ACCESS_MW_BIND; 497 struct bnxt_re_fence_data *fence = &pd->fence; 498 struct bnxt_re_dev *rdev = pd->rdev; 499 struct device *dev = &rdev->en_dev->pdev->dev; 500 struct bnxt_re_mr *mr = NULL; 501 dma_addr_t dma_addr = 0; 502 struct ib_mw *mw; 503 u64 pbl_tbl; 504 int rc; 505 506 dma_addr = dma_map_single(dev, fence->va, BNXT_RE_FENCE_BYTES, 507 DMA_BIDIRECTIONAL); 508 rc = dma_mapping_error(dev, dma_addr); 509 if (rc) { 510 dev_err(rdev_to_dev(rdev), "Failed to dma-map fence-MR-mem\n"); 511 rc = -EIO; 512 fence->dma_addr = 0; 513 goto fail; 514 } 515 fence->dma_addr = dma_addr; 516 517 /* Allocate a MR */ 518 mr = kzalloc(sizeof(*mr), GFP_KERNEL); 519 if (!mr) { 520 rc = -ENOMEM; 521 goto fail; 522 } 523 fence->mr = mr; 524 mr->rdev = rdev; 525 mr->qplib_mr.pd = &pd->qplib_pd; 526 mr->qplib_mr.type = CMDQ_ALLOCATE_MRW_MRW_FLAGS_PMR; 527 mr->qplib_mr.flags = __from_ib_access_flags(mr_access_flags); 528 rc = bnxt_qplib_alloc_mrw(&rdev->qplib_res, &mr->qplib_mr); 529 if (rc) { 530 dev_err(rdev_to_dev(rdev), "Failed to alloc fence-HW-MR\n"); 531 goto fail; 532 } 533 534 /* Register MR */ 535 mr->ib_mr.lkey = mr->qplib_mr.lkey; 536 mr->qplib_mr.va = (u64)(unsigned long)fence->va; 537 mr->qplib_mr.total_size = BNXT_RE_FENCE_BYTES; 538 pbl_tbl = dma_addr; 539 rc = bnxt_qplib_reg_mr(&rdev->qplib_res, &mr->qplib_mr, &pbl_tbl, 540 BNXT_RE_FENCE_PBL_SIZE, false, PAGE_SIZE); 541 if (rc) { 542 dev_err(rdev_to_dev(rdev), "Failed to register fence-MR\n"); 543 goto fail; 544 } 545 mr->ib_mr.rkey = mr->qplib_mr.rkey; 546 547 /* Create a fence MW only for kernel consumers */ 548 mw = bnxt_re_alloc_mw(&pd->ib_pd, IB_MW_TYPE_1, NULL); 549 if (IS_ERR(mw)) { 550 dev_err(rdev_to_dev(rdev), 551 "Failed to create fence-MW for PD: %p\n", pd); 552 rc = PTR_ERR(mw); 553 goto fail; 554 } 555 fence->mw = mw; 556 557 bnxt_re_create_fence_wqe(pd); 558 return 0; 559 560 fail: 561 bnxt_re_destroy_fence_mr(pd); 562 return rc; 563 } 564 565 /* Protection Domains */ 566 int bnxt_re_dealloc_pd(struct ib_pd *ib_pd) 567 { 568 struct bnxt_re_pd *pd = container_of(ib_pd, struct bnxt_re_pd, ib_pd); 569 struct bnxt_re_dev *rdev = pd->rdev; 570 int rc; 571 572 bnxt_re_destroy_fence_mr(pd); 573 574 if (pd->qplib_pd.id) { 575 rc = bnxt_qplib_dealloc_pd(&rdev->qplib_res, 576 &rdev->qplib_res.pd_tbl, 577 &pd->qplib_pd); 578 if (rc) 579 dev_err(rdev_to_dev(rdev), "Failed to deallocate HW PD"); 580 } 581 582 kfree(pd); 583 return 0; 584 } 585 586 struct ib_pd *bnxt_re_alloc_pd(struct ib_device *ibdev, 587 struct ib_ucontext *ucontext, 588 struct ib_udata *udata) 589 { 590 struct bnxt_re_dev *rdev = to_bnxt_re_dev(ibdev, ibdev); 591 struct bnxt_re_ucontext *ucntx = container_of(ucontext, 592 struct bnxt_re_ucontext, 593 ib_uctx); 594 struct bnxt_re_pd *pd; 595 int rc; 596 597 pd = kzalloc(sizeof(*pd), GFP_KERNEL); 598 if (!pd) 599 return ERR_PTR(-ENOMEM); 600 601 pd->rdev = rdev; 602 if (bnxt_qplib_alloc_pd(&rdev->qplib_res.pd_tbl, &pd->qplib_pd)) { 603 dev_err(rdev_to_dev(rdev), "Failed to allocate HW PD"); 604 rc = -ENOMEM; 605 goto fail; 606 } 607 608 if (udata) { 609 struct bnxt_re_pd_resp resp; 610 611 if (!ucntx->dpi.dbr) { 612 /* Allocate DPI in alloc_pd to avoid failing of 613 * ibv_devinfo and family of application when DPIs 614 * are depleted. 615 */ 616 if (bnxt_qplib_alloc_dpi(&rdev->qplib_res.dpi_tbl, 617 &ucntx->dpi, ucntx)) { 618 rc = -ENOMEM; 619 goto dbfail; 620 } 621 } 622 623 resp.pdid = pd->qplib_pd.id; 624 /* Still allow mapping this DBR to the new user PD. */ 625 resp.dpi = ucntx->dpi.dpi; 626 resp.dbr = (u64)ucntx->dpi.umdbr; 627 628 rc = ib_copy_to_udata(udata, &resp, sizeof(resp)); 629 if (rc) { 630 dev_err(rdev_to_dev(rdev), 631 "Failed to copy user response\n"); 632 goto dbfail; 633 } 634 } 635 636 if (!udata) 637 if (bnxt_re_create_fence_mr(pd)) 638 dev_warn(rdev_to_dev(rdev), 639 "Failed to create Fence-MR\n"); 640 return &pd->ib_pd; 641 dbfail: 642 (void)bnxt_qplib_dealloc_pd(&rdev->qplib_res, &rdev->qplib_res.pd_tbl, 643 &pd->qplib_pd); 644 fail: 645 kfree(pd); 646 return ERR_PTR(rc); 647 } 648 649 /* Address Handles */ 650 int bnxt_re_destroy_ah(struct ib_ah *ib_ah) 651 { 652 struct bnxt_re_ah *ah = container_of(ib_ah, struct bnxt_re_ah, ib_ah); 653 struct bnxt_re_dev *rdev = ah->rdev; 654 int rc; 655 656 rc = bnxt_qplib_destroy_ah(&rdev->qplib_res, &ah->qplib_ah); 657 if (rc) { 658 dev_err(rdev_to_dev(rdev), "Failed to destroy HW AH"); 659 return rc; 660 } 661 kfree(ah); 662 return 0; 663 } 664 665 struct ib_ah *bnxt_re_create_ah(struct ib_pd *ib_pd, 666 struct rdma_ah_attr *ah_attr, 667 struct ib_udata *udata) 668 { 669 struct bnxt_re_pd *pd = container_of(ib_pd, struct bnxt_re_pd, ib_pd); 670 struct bnxt_re_dev *rdev = pd->rdev; 671 struct bnxt_re_ah *ah; 672 const struct ib_global_route *grh = rdma_ah_read_grh(ah_attr); 673 int rc; 674 u8 nw_type; 675 676 if (!(rdma_ah_get_ah_flags(ah_attr) & IB_AH_GRH)) { 677 dev_err(rdev_to_dev(rdev), "Failed to alloc AH: GRH not set"); 678 return ERR_PTR(-EINVAL); 679 } 680 ah = kzalloc(sizeof(*ah), GFP_ATOMIC); 681 if (!ah) 682 return ERR_PTR(-ENOMEM); 683 684 ah->rdev = rdev; 685 ah->qplib_ah.pd = &pd->qplib_pd; 686 687 /* Supply the configuration for the HW */ 688 memcpy(ah->qplib_ah.dgid.data, grh->dgid.raw, 689 sizeof(union ib_gid)); 690 /* 691 * If RoCE V2 is enabled, stack will have two entries for 692 * each GID entry. Avoiding this duplicte entry in HW. Dividing 693 * the GID index by 2 for RoCE V2 694 */ 695 ah->qplib_ah.sgid_index = grh->sgid_index / 2; 696 ah->qplib_ah.host_sgid_index = grh->sgid_index; 697 ah->qplib_ah.traffic_class = grh->traffic_class; 698 ah->qplib_ah.flow_label = grh->flow_label; 699 ah->qplib_ah.hop_limit = grh->hop_limit; 700 ah->qplib_ah.sl = rdma_ah_get_sl(ah_attr); 701 if (ib_pd->uobject && 702 !rdma_is_multicast_addr((struct in6_addr *) 703 grh->dgid.raw) && 704 !rdma_link_local_addr((struct in6_addr *) 705 grh->dgid.raw)) { 706 const struct ib_gid_attr *sgid_attr; 707 708 sgid_attr = grh->sgid_attr; 709 /* Get network header type for this GID */ 710 nw_type = rdma_gid_attr_network_type(sgid_attr); 711 switch (nw_type) { 712 case RDMA_NETWORK_IPV4: 713 ah->qplib_ah.nw_type = CMDQ_CREATE_AH_TYPE_V2IPV4; 714 break; 715 case RDMA_NETWORK_IPV6: 716 ah->qplib_ah.nw_type = CMDQ_CREATE_AH_TYPE_V2IPV6; 717 break; 718 default: 719 ah->qplib_ah.nw_type = CMDQ_CREATE_AH_TYPE_V1; 720 break; 721 } 722 } 723 724 memcpy(ah->qplib_ah.dmac, ah_attr->roce.dmac, ETH_ALEN); 725 rc = bnxt_qplib_create_ah(&rdev->qplib_res, &ah->qplib_ah); 726 if (rc) { 727 dev_err(rdev_to_dev(rdev), "Failed to allocate HW AH"); 728 goto fail; 729 } 730 731 /* Write AVID to shared page. */ 732 if (ib_pd->uobject) { 733 struct ib_ucontext *ib_uctx = ib_pd->uobject->context; 734 struct bnxt_re_ucontext *uctx; 735 unsigned long flag; 736 u32 *wrptr; 737 738 uctx = container_of(ib_uctx, struct bnxt_re_ucontext, ib_uctx); 739 spin_lock_irqsave(&uctx->sh_lock, flag); 740 wrptr = (u32 *)(uctx->shpg + BNXT_RE_AVID_OFFT); 741 *wrptr = ah->qplib_ah.id; 742 wmb(); /* make sure cache is updated. */ 743 spin_unlock_irqrestore(&uctx->sh_lock, flag); 744 } 745 746 return &ah->ib_ah; 747 748 fail: 749 kfree(ah); 750 return ERR_PTR(rc); 751 } 752 753 int bnxt_re_modify_ah(struct ib_ah *ib_ah, struct rdma_ah_attr *ah_attr) 754 { 755 return 0; 756 } 757 758 int bnxt_re_query_ah(struct ib_ah *ib_ah, struct rdma_ah_attr *ah_attr) 759 { 760 struct bnxt_re_ah *ah = container_of(ib_ah, struct bnxt_re_ah, ib_ah); 761 762 ah_attr->type = ib_ah->type; 763 rdma_ah_set_sl(ah_attr, ah->qplib_ah.sl); 764 memcpy(ah_attr->roce.dmac, ah->qplib_ah.dmac, ETH_ALEN); 765 rdma_ah_set_grh(ah_attr, NULL, 0, 766 ah->qplib_ah.host_sgid_index, 767 0, ah->qplib_ah.traffic_class); 768 rdma_ah_set_dgid_raw(ah_attr, ah->qplib_ah.dgid.data); 769 rdma_ah_set_port_num(ah_attr, 1); 770 rdma_ah_set_static_rate(ah_attr, 0); 771 return 0; 772 } 773 774 unsigned long bnxt_re_lock_cqs(struct bnxt_re_qp *qp) 775 __acquires(&qp->scq->cq_lock) __acquires(&qp->rcq->cq_lock) 776 { 777 unsigned long flags; 778 779 spin_lock_irqsave(&qp->scq->cq_lock, flags); 780 if (qp->rcq != qp->scq) 781 spin_lock(&qp->rcq->cq_lock); 782 else 783 __acquire(&qp->rcq->cq_lock); 784 785 return flags; 786 } 787 788 void bnxt_re_unlock_cqs(struct bnxt_re_qp *qp, 789 unsigned long flags) 790 __releases(&qp->scq->cq_lock) __releases(&qp->rcq->cq_lock) 791 { 792 if (qp->rcq != qp->scq) 793 spin_unlock(&qp->rcq->cq_lock); 794 else 795 __release(&qp->rcq->cq_lock); 796 spin_unlock_irqrestore(&qp->scq->cq_lock, flags); 797 } 798 799 /* Queue Pairs */ 800 int bnxt_re_destroy_qp(struct ib_qp *ib_qp) 801 { 802 struct bnxt_re_qp *qp = container_of(ib_qp, struct bnxt_re_qp, ib_qp); 803 struct bnxt_re_dev *rdev = qp->rdev; 804 int rc; 805 unsigned int flags; 806 807 bnxt_qplib_flush_cqn_wq(&qp->qplib_qp); 808 rc = bnxt_qplib_destroy_qp(&rdev->qplib_res, &qp->qplib_qp); 809 if (rc) { 810 dev_err(rdev_to_dev(rdev), "Failed to destroy HW QP"); 811 return rc; 812 } 813 814 flags = bnxt_re_lock_cqs(qp); 815 bnxt_qplib_clean_qp(&qp->qplib_qp); 816 bnxt_re_unlock_cqs(qp, flags); 817 bnxt_qplib_free_qp_res(&rdev->qplib_res, &qp->qplib_qp); 818 819 if (ib_qp->qp_type == IB_QPT_GSI && rdev->qp1_sqp) { 820 rc = bnxt_qplib_destroy_ah(&rdev->qplib_res, 821 &rdev->sqp_ah->qplib_ah); 822 if (rc) { 823 dev_err(rdev_to_dev(rdev), 824 "Failed to destroy HW AH for shadow QP"); 825 return rc; 826 } 827 828 bnxt_qplib_clean_qp(&qp->qplib_qp); 829 rc = bnxt_qplib_destroy_qp(&rdev->qplib_res, 830 &rdev->qp1_sqp->qplib_qp); 831 if (rc) { 832 dev_err(rdev_to_dev(rdev), 833 "Failed to destroy Shadow QP"); 834 return rc; 835 } 836 mutex_lock(&rdev->qp_lock); 837 list_del(&rdev->qp1_sqp->list); 838 atomic_dec(&rdev->qp_count); 839 mutex_unlock(&rdev->qp_lock); 840 841 kfree(rdev->sqp_ah); 842 kfree(rdev->qp1_sqp); 843 rdev->qp1_sqp = NULL; 844 rdev->sqp_ah = NULL; 845 } 846 847 if (!IS_ERR_OR_NULL(qp->rumem)) 848 ib_umem_release(qp->rumem); 849 if (!IS_ERR_OR_NULL(qp->sumem)) 850 ib_umem_release(qp->sumem); 851 852 mutex_lock(&rdev->qp_lock); 853 list_del(&qp->list); 854 atomic_dec(&rdev->qp_count); 855 mutex_unlock(&rdev->qp_lock); 856 kfree(qp); 857 return 0; 858 } 859 860 static u8 __from_ib_qp_type(enum ib_qp_type type) 861 { 862 switch (type) { 863 case IB_QPT_GSI: 864 return CMDQ_CREATE_QP1_TYPE_GSI; 865 case IB_QPT_RC: 866 return CMDQ_CREATE_QP_TYPE_RC; 867 case IB_QPT_UD: 868 return CMDQ_CREATE_QP_TYPE_UD; 869 default: 870 return IB_QPT_MAX; 871 } 872 } 873 874 static int bnxt_re_init_user_qp(struct bnxt_re_dev *rdev, struct bnxt_re_pd *pd, 875 struct bnxt_re_qp *qp, struct ib_udata *udata) 876 { 877 struct bnxt_re_qp_req ureq; 878 struct bnxt_qplib_qp *qplib_qp = &qp->qplib_qp; 879 struct ib_umem *umem; 880 int bytes = 0; 881 struct ib_ucontext *context = pd->ib_pd.uobject->context; 882 struct bnxt_re_ucontext *cntx = container_of(context, 883 struct bnxt_re_ucontext, 884 ib_uctx); 885 if (ib_copy_from_udata(&ureq, udata, sizeof(ureq))) 886 return -EFAULT; 887 888 bytes = (qplib_qp->sq.max_wqe * BNXT_QPLIB_MAX_SQE_ENTRY_SIZE); 889 /* Consider mapping PSN search memory only for RC QPs. */ 890 if (qplib_qp->type == CMDQ_CREATE_QP_TYPE_RC) 891 bytes += (qplib_qp->sq.max_wqe * sizeof(struct sq_psn_search)); 892 bytes = PAGE_ALIGN(bytes); 893 umem = ib_umem_get(context, ureq.qpsva, bytes, 894 IB_ACCESS_LOCAL_WRITE, 1); 895 if (IS_ERR(umem)) 896 return PTR_ERR(umem); 897 898 qp->sumem = umem; 899 qplib_qp->sq.sglist = umem->sg_head.sgl; 900 qplib_qp->sq.nmap = umem->nmap; 901 qplib_qp->qp_handle = ureq.qp_handle; 902 903 if (!qp->qplib_qp.srq) { 904 bytes = (qplib_qp->rq.max_wqe * BNXT_QPLIB_MAX_RQE_ENTRY_SIZE); 905 bytes = PAGE_ALIGN(bytes); 906 umem = ib_umem_get(context, ureq.qprva, bytes, 907 IB_ACCESS_LOCAL_WRITE, 1); 908 if (IS_ERR(umem)) 909 goto rqfail; 910 qp->rumem = umem; 911 qplib_qp->rq.sglist = umem->sg_head.sgl; 912 qplib_qp->rq.nmap = umem->nmap; 913 } 914 915 qplib_qp->dpi = &cntx->dpi; 916 return 0; 917 rqfail: 918 ib_umem_release(qp->sumem); 919 qp->sumem = NULL; 920 qplib_qp->sq.sglist = NULL; 921 qplib_qp->sq.nmap = 0; 922 923 return PTR_ERR(umem); 924 } 925 926 static struct bnxt_re_ah *bnxt_re_create_shadow_qp_ah 927 (struct bnxt_re_pd *pd, 928 struct bnxt_qplib_res *qp1_res, 929 struct bnxt_qplib_qp *qp1_qp) 930 { 931 struct bnxt_re_dev *rdev = pd->rdev; 932 struct bnxt_re_ah *ah; 933 union ib_gid sgid; 934 int rc; 935 936 ah = kzalloc(sizeof(*ah), GFP_KERNEL); 937 if (!ah) 938 return NULL; 939 940 ah->rdev = rdev; 941 ah->qplib_ah.pd = &pd->qplib_pd; 942 943 rc = bnxt_re_query_gid(&rdev->ibdev, 1, 0, &sgid); 944 if (rc) 945 goto fail; 946 947 /* supply the dgid data same as sgid */ 948 memcpy(ah->qplib_ah.dgid.data, &sgid.raw, 949 sizeof(union ib_gid)); 950 ah->qplib_ah.sgid_index = 0; 951 952 ah->qplib_ah.traffic_class = 0; 953 ah->qplib_ah.flow_label = 0; 954 ah->qplib_ah.hop_limit = 1; 955 ah->qplib_ah.sl = 0; 956 /* Have DMAC same as SMAC */ 957 ether_addr_copy(ah->qplib_ah.dmac, rdev->netdev->dev_addr); 958 959 rc = bnxt_qplib_create_ah(&rdev->qplib_res, &ah->qplib_ah); 960 if (rc) { 961 dev_err(rdev_to_dev(rdev), 962 "Failed to allocate HW AH for Shadow QP"); 963 goto fail; 964 } 965 966 return ah; 967 968 fail: 969 kfree(ah); 970 return NULL; 971 } 972 973 static struct bnxt_re_qp *bnxt_re_create_shadow_qp 974 (struct bnxt_re_pd *pd, 975 struct bnxt_qplib_res *qp1_res, 976 struct bnxt_qplib_qp *qp1_qp) 977 { 978 struct bnxt_re_dev *rdev = pd->rdev; 979 struct bnxt_re_qp *qp; 980 int rc; 981 982 qp = kzalloc(sizeof(*qp), GFP_KERNEL); 983 if (!qp) 984 return NULL; 985 986 qp->rdev = rdev; 987 988 /* Initialize the shadow QP structure from the QP1 values */ 989 ether_addr_copy(qp->qplib_qp.smac, rdev->netdev->dev_addr); 990 991 qp->qplib_qp.pd = &pd->qplib_pd; 992 qp->qplib_qp.qp_handle = (u64)(unsigned long)(&qp->qplib_qp); 993 qp->qplib_qp.type = IB_QPT_UD; 994 995 qp->qplib_qp.max_inline_data = 0; 996 qp->qplib_qp.sig_type = true; 997 998 /* Shadow QP SQ depth should be same as QP1 RQ depth */ 999 qp->qplib_qp.sq.max_wqe = qp1_qp->rq.max_wqe; 1000 qp->qplib_qp.sq.max_sge = 2; 1001 /* Q full delta can be 1 since it is internal QP */ 1002 qp->qplib_qp.sq.q_full_delta = 1; 1003 1004 qp->qplib_qp.scq = qp1_qp->scq; 1005 qp->qplib_qp.rcq = qp1_qp->rcq; 1006 1007 qp->qplib_qp.rq.max_wqe = qp1_qp->rq.max_wqe; 1008 qp->qplib_qp.rq.max_sge = qp1_qp->rq.max_sge; 1009 /* Q full delta can be 1 since it is internal QP */ 1010 qp->qplib_qp.rq.q_full_delta = 1; 1011 1012 qp->qplib_qp.mtu = qp1_qp->mtu; 1013 1014 qp->qplib_qp.sq_hdr_buf_size = 0; 1015 qp->qplib_qp.rq_hdr_buf_size = BNXT_QPLIB_MAX_GRH_HDR_SIZE_IPV6; 1016 qp->qplib_qp.dpi = &rdev->dpi_privileged; 1017 1018 rc = bnxt_qplib_create_qp(qp1_res, &qp->qplib_qp); 1019 if (rc) 1020 goto fail; 1021 1022 rdev->sqp_id = qp->qplib_qp.id; 1023 1024 spin_lock_init(&qp->sq_lock); 1025 INIT_LIST_HEAD(&qp->list); 1026 mutex_lock(&rdev->qp_lock); 1027 list_add_tail(&qp->list, &rdev->qp_list); 1028 atomic_inc(&rdev->qp_count); 1029 mutex_unlock(&rdev->qp_lock); 1030 return qp; 1031 fail: 1032 kfree(qp); 1033 return NULL; 1034 } 1035 1036 struct ib_qp *bnxt_re_create_qp(struct ib_pd *ib_pd, 1037 struct ib_qp_init_attr *qp_init_attr, 1038 struct ib_udata *udata) 1039 { 1040 struct bnxt_re_pd *pd = container_of(ib_pd, struct bnxt_re_pd, ib_pd); 1041 struct bnxt_re_dev *rdev = pd->rdev; 1042 struct bnxt_qplib_dev_attr *dev_attr = &rdev->dev_attr; 1043 struct bnxt_re_qp *qp; 1044 struct bnxt_re_cq *cq; 1045 struct bnxt_re_srq *srq; 1046 int rc, entries; 1047 1048 if ((qp_init_attr->cap.max_send_wr > dev_attr->max_qp_wqes) || 1049 (qp_init_attr->cap.max_recv_wr > dev_attr->max_qp_wqes) || 1050 (qp_init_attr->cap.max_send_sge > dev_attr->max_qp_sges) || 1051 (qp_init_attr->cap.max_recv_sge > dev_attr->max_qp_sges) || 1052 (qp_init_attr->cap.max_inline_data > dev_attr->max_inline_data)) 1053 return ERR_PTR(-EINVAL); 1054 1055 qp = kzalloc(sizeof(*qp), GFP_KERNEL); 1056 if (!qp) 1057 return ERR_PTR(-ENOMEM); 1058 1059 qp->rdev = rdev; 1060 ether_addr_copy(qp->qplib_qp.smac, rdev->netdev->dev_addr); 1061 qp->qplib_qp.pd = &pd->qplib_pd; 1062 qp->qplib_qp.qp_handle = (u64)(unsigned long)(&qp->qplib_qp); 1063 qp->qplib_qp.type = __from_ib_qp_type(qp_init_attr->qp_type); 1064 if (qp->qplib_qp.type == IB_QPT_MAX) { 1065 dev_err(rdev_to_dev(rdev), "QP type 0x%x not supported", 1066 qp->qplib_qp.type); 1067 rc = -EINVAL; 1068 goto fail; 1069 } 1070 qp->qplib_qp.max_inline_data = qp_init_attr->cap.max_inline_data; 1071 qp->qplib_qp.sig_type = ((qp_init_attr->sq_sig_type == 1072 IB_SIGNAL_ALL_WR) ? true : false); 1073 1074 qp->qplib_qp.sq.max_sge = qp_init_attr->cap.max_send_sge; 1075 if (qp->qplib_qp.sq.max_sge > dev_attr->max_qp_sges) 1076 qp->qplib_qp.sq.max_sge = dev_attr->max_qp_sges; 1077 1078 if (qp_init_attr->send_cq) { 1079 cq = container_of(qp_init_attr->send_cq, struct bnxt_re_cq, 1080 ib_cq); 1081 if (!cq) { 1082 dev_err(rdev_to_dev(rdev), "Send CQ not found"); 1083 rc = -EINVAL; 1084 goto fail; 1085 } 1086 qp->qplib_qp.scq = &cq->qplib_cq; 1087 qp->scq = cq; 1088 } 1089 1090 if (qp_init_attr->recv_cq) { 1091 cq = container_of(qp_init_attr->recv_cq, struct bnxt_re_cq, 1092 ib_cq); 1093 if (!cq) { 1094 dev_err(rdev_to_dev(rdev), "Receive CQ not found"); 1095 rc = -EINVAL; 1096 goto fail; 1097 } 1098 qp->qplib_qp.rcq = &cq->qplib_cq; 1099 qp->rcq = cq; 1100 } 1101 1102 if (qp_init_attr->srq) { 1103 srq = container_of(qp_init_attr->srq, struct bnxt_re_srq, 1104 ib_srq); 1105 if (!srq) { 1106 dev_err(rdev_to_dev(rdev), "SRQ not found"); 1107 rc = -EINVAL; 1108 goto fail; 1109 } 1110 qp->qplib_qp.srq = &srq->qplib_srq; 1111 qp->qplib_qp.rq.max_wqe = 0; 1112 } else { 1113 /* Allocate 1 more than what's provided so posting max doesn't 1114 * mean empty 1115 */ 1116 entries = roundup_pow_of_two(qp_init_attr->cap.max_recv_wr + 1); 1117 qp->qplib_qp.rq.max_wqe = min_t(u32, entries, 1118 dev_attr->max_qp_wqes + 1); 1119 1120 qp->qplib_qp.rq.q_full_delta = qp->qplib_qp.rq.max_wqe - 1121 qp_init_attr->cap.max_recv_wr; 1122 1123 qp->qplib_qp.rq.max_sge = qp_init_attr->cap.max_recv_sge; 1124 if (qp->qplib_qp.rq.max_sge > dev_attr->max_qp_sges) 1125 qp->qplib_qp.rq.max_sge = dev_attr->max_qp_sges; 1126 } 1127 1128 qp->qplib_qp.mtu = ib_mtu_enum_to_int(iboe_get_mtu(rdev->netdev->mtu)); 1129 1130 if (qp_init_attr->qp_type == IB_QPT_GSI) { 1131 /* Allocate 1 more than what's provided */ 1132 entries = roundup_pow_of_two(qp_init_attr->cap.max_send_wr + 1); 1133 qp->qplib_qp.sq.max_wqe = min_t(u32, entries, 1134 dev_attr->max_qp_wqes + 1); 1135 qp->qplib_qp.sq.q_full_delta = qp->qplib_qp.sq.max_wqe - 1136 qp_init_attr->cap.max_send_wr; 1137 qp->qplib_qp.rq.max_sge = dev_attr->max_qp_sges; 1138 if (qp->qplib_qp.rq.max_sge > dev_attr->max_qp_sges) 1139 qp->qplib_qp.rq.max_sge = dev_attr->max_qp_sges; 1140 qp->qplib_qp.sq.max_sge++; 1141 if (qp->qplib_qp.sq.max_sge > dev_attr->max_qp_sges) 1142 qp->qplib_qp.sq.max_sge = dev_attr->max_qp_sges; 1143 1144 qp->qplib_qp.rq_hdr_buf_size = 1145 BNXT_QPLIB_MAX_QP1_RQ_HDR_SIZE_V2; 1146 1147 qp->qplib_qp.sq_hdr_buf_size = 1148 BNXT_QPLIB_MAX_QP1_SQ_HDR_SIZE_V2; 1149 qp->qplib_qp.dpi = &rdev->dpi_privileged; 1150 rc = bnxt_qplib_create_qp1(&rdev->qplib_res, &qp->qplib_qp); 1151 if (rc) { 1152 dev_err(rdev_to_dev(rdev), "Failed to create HW QP1"); 1153 goto fail; 1154 } 1155 /* Create a shadow QP to handle the QP1 traffic */ 1156 rdev->qp1_sqp = bnxt_re_create_shadow_qp(pd, &rdev->qplib_res, 1157 &qp->qplib_qp); 1158 if (!rdev->qp1_sqp) { 1159 rc = -EINVAL; 1160 dev_err(rdev_to_dev(rdev), 1161 "Failed to create Shadow QP for QP1"); 1162 goto qp_destroy; 1163 } 1164 rdev->sqp_ah = bnxt_re_create_shadow_qp_ah(pd, &rdev->qplib_res, 1165 &qp->qplib_qp); 1166 if (!rdev->sqp_ah) { 1167 bnxt_qplib_destroy_qp(&rdev->qplib_res, 1168 &rdev->qp1_sqp->qplib_qp); 1169 rc = -EINVAL; 1170 dev_err(rdev_to_dev(rdev), 1171 "Failed to create AH entry for ShadowQP"); 1172 goto qp_destroy; 1173 } 1174 1175 } else { 1176 /* Allocate 128 + 1 more than what's provided */ 1177 entries = roundup_pow_of_two(qp_init_attr->cap.max_send_wr + 1178 BNXT_QPLIB_RESERVED_QP_WRS + 1); 1179 qp->qplib_qp.sq.max_wqe = min_t(u32, entries, 1180 dev_attr->max_qp_wqes + 1181 BNXT_QPLIB_RESERVED_QP_WRS + 1); 1182 qp->qplib_qp.sq.q_full_delta = BNXT_QPLIB_RESERVED_QP_WRS + 1; 1183 1184 /* 1185 * Reserving one slot for Phantom WQE. Application can 1186 * post one extra entry in this case. But allowing this to avoid 1187 * unexpected Queue full condition 1188 */ 1189 1190 qp->qplib_qp.sq.q_full_delta -= 1; 1191 1192 qp->qplib_qp.max_rd_atomic = dev_attr->max_qp_rd_atom; 1193 qp->qplib_qp.max_dest_rd_atomic = dev_attr->max_qp_init_rd_atom; 1194 if (udata) { 1195 rc = bnxt_re_init_user_qp(rdev, pd, qp, udata); 1196 if (rc) 1197 goto fail; 1198 } else { 1199 qp->qplib_qp.dpi = &rdev->dpi_privileged; 1200 } 1201 1202 rc = bnxt_qplib_create_qp(&rdev->qplib_res, &qp->qplib_qp); 1203 if (rc) { 1204 dev_err(rdev_to_dev(rdev), "Failed to create HW QP"); 1205 goto free_umem; 1206 } 1207 } 1208 1209 qp->ib_qp.qp_num = qp->qplib_qp.id; 1210 spin_lock_init(&qp->sq_lock); 1211 spin_lock_init(&qp->rq_lock); 1212 1213 if (udata) { 1214 struct bnxt_re_qp_resp resp; 1215 1216 resp.qpid = qp->ib_qp.qp_num; 1217 resp.rsvd = 0; 1218 rc = ib_copy_to_udata(udata, &resp, sizeof(resp)); 1219 if (rc) { 1220 dev_err(rdev_to_dev(rdev), "Failed to copy QP udata"); 1221 goto qp_destroy; 1222 } 1223 } 1224 INIT_LIST_HEAD(&qp->list); 1225 mutex_lock(&rdev->qp_lock); 1226 list_add_tail(&qp->list, &rdev->qp_list); 1227 atomic_inc(&rdev->qp_count); 1228 mutex_unlock(&rdev->qp_lock); 1229 1230 return &qp->ib_qp; 1231 qp_destroy: 1232 bnxt_qplib_destroy_qp(&rdev->qplib_res, &qp->qplib_qp); 1233 free_umem: 1234 if (udata) { 1235 if (qp->rumem) 1236 ib_umem_release(qp->rumem); 1237 if (qp->sumem) 1238 ib_umem_release(qp->sumem); 1239 } 1240 fail: 1241 kfree(qp); 1242 return ERR_PTR(rc); 1243 } 1244 1245 static u8 __from_ib_qp_state(enum ib_qp_state state) 1246 { 1247 switch (state) { 1248 case IB_QPS_RESET: 1249 return CMDQ_MODIFY_QP_NEW_STATE_RESET; 1250 case IB_QPS_INIT: 1251 return CMDQ_MODIFY_QP_NEW_STATE_INIT; 1252 case IB_QPS_RTR: 1253 return CMDQ_MODIFY_QP_NEW_STATE_RTR; 1254 case IB_QPS_RTS: 1255 return CMDQ_MODIFY_QP_NEW_STATE_RTS; 1256 case IB_QPS_SQD: 1257 return CMDQ_MODIFY_QP_NEW_STATE_SQD; 1258 case IB_QPS_SQE: 1259 return CMDQ_MODIFY_QP_NEW_STATE_SQE; 1260 case IB_QPS_ERR: 1261 default: 1262 return CMDQ_MODIFY_QP_NEW_STATE_ERR; 1263 } 1264 } 1265 1266 static enum ib_qp_state __to_ib_qp_state(u8 state) 1267 { 1268 switch (state) { 1269 case CMDQ_MODIFY_QP_NEW_STATE_RESET: 1270 return IB_QPS_RESET; 1271 case CMDQ_MODIFY_QP_NEW_STATE_INIT: 1272 return IB_QPS_INIT; 1273 case CMDQ_MODIFY_QP_NEW_STATE_RTR: 1274 return IB_QPS_RTR; 1275 case CMDQ_MODIFY_QP_NEW_STATE_RTS: 1276 return IB_QPS_RTS; 1277 case CMDQ_MODIFY_QP_NEW_STATE_SQD: 1278 return IB_QPS_SQD; 1279 case CMDQ_MODIFY_QP_NEW_STATE_SQE: 1280 return IB_QPS_SQE; 1281 case CMDQ_MODIFY_QP_NEW_STATE_ERR: 1282 default: 1283 return IB_QPS_ERR; 1284 } 1285 } 1286 1287 static u32 __from_ib_mtu(enum ib_mtu mtu) 1288 { 1289 switch (mtu) { 1290 case IB_MTU_256: 1291 return CMDQ_MODIFY_QP_PATH_MTU_MTU_256; 1292 case IB_MTU_512: 1293 return CMDQ_MODIFY_QP_PATH_MTU_MTU_512; 1294 case IB_MTU_1024: 1295 return CMDQ_MODIFY_QP_PATH_MTU_MTU_1024; 1296 case IB_MTU_2048: 1297 return CMDQ_MODIFY_QP_PATH_MTU_MTU_2048; 1298 case IB_MTU_4096: 1299 return CMDQ_MODIFY_QP_PATH_MTU_MTU_4096; 1300 default: 1301 return CMDQ_MODIFY_QP_PATH_MTU_MTU_2048; 1302 } 1303 } 1304 1305 static enum ib_mtu __to_ib_mtu(u32 mtu) 1306 { 1307 switch (mtu & CREQ_QUERY_QP_RESP_SB_PATH_MTU_MASK) { 1308 case CMDQ_MODIFY_QP_PATH_MTU_MTU_256: 1309 return IB_MTU_256; 1310 case CMDQ_MODIFY_QP_PATH_MTU_MTU_512: 1311 return IB_MTU_512; 1312 case CMDQ_MODIFY_QP_PATH_MTU_MTU_1024: 1313 return IB_MTU_1024; 1314 case CMDQ_MODIFY_QP_PATH_MTU_MTU_2048: 1315 return IB_MTU_2048; 1316 case CMDQ_MODIFY_QP_PATH_MTU_MTU_4096: 1317 return IB_MTU_4096; 1318 default: 1319 return IB_MTU_2048; 1320 } 1321 } 1322 1323 /* Shared Receive Queues */ 1324 int bnxt_re_destroy_srq(struct ib_srq *ib_srq) 1325 { 1326 struct bnxt_re_srq *srq = container_of(ib_srq, struct bnxt_re_srq, 1327 ib_srq); 1328 struct bnxt_re_dev *rdev = srq->rdev; 1329 struct bnxt_qplib_srq *qplib_srq = &srq->qplib_srq; 1330 struct bnxt_qplib_nq *nq = NULL; 1331 int rc; 1332 1333 if (qplib_srq->cq) 1334 nq = qplib_srq->cq->nq; 1335 rc = bnxt_qplib_destroy_srq(&rdev->qplib_res, qplib_srq); 1336 if (rc) { 1337 dev_err(rdev_to_dev(rdev), "Destroy HW SRQ failed!"); 1338 return rc; 1339 } 1340 1341 if (srq->umem) 1342 ib_umem_release(srq->umem); 1343 kfree(srq); 1344 atomic_dec(&rdev->srq_count); 1345 if (nq) 1346 nq->budget--; 1347 return 0; 1348 } 1349 1350 static int bnxt_re_init_user_srq(struct bnxt_re_dev *rdev, 1351 struct bnxt_re_pd *pd, 1352 struct bnxt_re_srq *srq, 1353 struct ib_udata *udata) 1354 { 1355 struct bnxt_re_srq_req ureq; 1356 struct bnxt_qplib_srq *qplib_srq = &srq->qplib_srq; 1357 struct ib_umem *umem; 1358 int bytes = 0; 1359 struct ib_ucontext *context = pd->ib_pd.uobject->context; 1360 struct bnxt_re_ucontext *cntx = container_of(context, 1361 struct bnxt_re_ucontext, 1362 ib_uctx); 1363 if (ib_copy_from_udata(&ureq, udata, sizeof(ureq))) 1364 return -EFAULT; 1365 1366 bytes = (qplib_srq->max_wqe * BNXT_QPLIB_MAX_RQE_ENTRY_SIZE); 1367 bytes = PAGE_ALIGN(bytes); 1368 umem = ib_umem_get(context, ureq.srqva, bytes, 1369 IB_ACCESS_LOCAL_WRITE, 1); 1370 if (IS_ERR(umem)) 1371 return PTR_ERR(umem); 1372 1373 srq->umem = umem; 1374 qplib_srq->nmap = umem->nmap; 1375 qplib_srq->sglist = umem->sg_head.sgl; 1376 qplib_srq->srq_handle = ureq.srq_handle; 1377 qplib_srq->dpi = &cntx->dpi; 1378 1379 return 0; 1380 } 1381 1382 struct ib_srq *bnxt_re_create_srq(struct ib_pd *ib_pd, 1383 struct ib_srq_init_attr *srq_init_attr, 1384 struct ib_udata *udata) 1385 { 1386 struct bnxt_re_pd *pd = container_of(ib_pd, struct bnxt_re_pd, ib_pd); 1387 struct bnxt_re_dev *rdev = pd->rdev; 1388 struct bnxt_qplib_dev_attr *dev_attr = &rdev->dev_attr; 1389 struct bnxt_re_srq *srq; 1390 struct bnxt_qplib_nq *nq = NULL; 1391 int rc, entries; 1392 1393 if (srq_init_attr->attr.max_wr >= dev_attr->max_srq_wqes) { 1394 dev_err(rdev_to_dev(rdev), "Create CQ failed - max exceeded"); 1395 rc = -EINVAL; 1396 goto exit; 1397 } 1398 1399 if (srq_init_attr->srq_type != IB_SRQT_BASIC) { 1400 rc = -EOPNOTSUPP; 1401 goto exit; 1402 } 1403 1404 srq = kzalloc(sizeof(*srq), GFP_KERNEL); 1405 if (!srq) { 1406 rc = -ENOMEM; 1407 goto exit; 1408 } 1409 srq->rdev = rdev; 1410 srq->qplib_srq.pd = &pd->qplib_pd; 1411 srq->qplib_srq.dpi = &rdev->dpi_privileged; 1412 /* Allocate 1 more than what's provided so posting max doesn't 1413 * mean empty 1414 */ 1415 entries = roundup_pow_of_two(srq_init_attr->attr.max_wr + 1); 1416 if (entries > dev_attr->max_srq_wqes + 1) 1417 entries = dev_attr->max_srq_wqes + 1; 1418 1419 srq->qplib_srq.max_wqe = entries; 1420 srq->qplib_srq.max_sge = srq_init_attr->attr.max_sge; 1421 srq->qplib_srq.threshold = srq_init_attr->attr.srq_limit; 1422 srq->srq_limit = srq_init_attr->attr.srq_limit; 1423 srq->qplib_srq.eventq_hw_ring_id = rdev->nq[0].ring_id; 1424 nq = &rdev->nq[0]; 1425 1426 if (udata) { 1427 rc = bnxt_re_init_user_srq(rdev, pd, srq, udata); 1428 if (rc) 1429 goto fail; 1430 } 1431 1432 rc = bnxt_qplib_create_srq(&rdev->qplib_res, &srq->qplib_srq); 1433 if (rc) { 1434 dev_err(rdev_to_dev(rdev), "Create HW SRQ failed!"); 1435 goto fail; 1436 } 1437 1438 if (udata) { 1439 struct bnxt_re_srq_resp resp; 1440 1441 resp.srqid = srq->qplib_srq.id; 1442 rc = ib_copy_to_udata(udata, &resp, sizeof(resp)); 1443 if (rc) { 1444 dev_err(rdev_to_dev(rdev), "SRQ copy to udata failed!"); 1445 bnxt_qplib_destroy_srq(&rdev->qplib_res, 1446 &srq->qplib_srq); 1447 goto exit; 1448 } 1449 } 1450 if (nq) 1451 nq->budget++; 1452 atomic_inc(&rdev->srq_count); 1453 1454 return &srq->ib_srq; 1455 1456 fail: 1457 if (srq->umem) 1458 ib_umem_release(srq->umem); 1459 kfree(srq); 1460 exit: 1461 return ERR_PTR(rc); 1462 } 1463 1464 int bnxt_re_modify_srq(struct ib_srq *ib_srq, struct ib_srq_attr *srq_attr, 1465 enum ib_srq_attr_mask srq_attr_mask, 1466 struct ib_udata *udata) 1467 { 1468 struct bnxt_re_srq *srq = container_of(ib_srq, struct bnxt_re_srq, 1469 ib_srq); 1470 struct bnxt_re_dev *rdev = srq->rdev; 1471 int rc; 1472 1473 switch (srq_attr_mask) { 1474 case IB_SRQ_MAX_WR: 1475 /* SRQ resize is not supported */ 1476 break; 1477 case IB_SRQ_LIMIT: 1478 /* Change the SRQ threshold */ 1479 if (srq_attr->srq_limit > srq->qplib_srq.max_wqe) 1480 return -EINVAL; 1481 1482 srq->qplib_srq.threshold = srq_attr->srq_limit; 1483 rc = bnxt_qplib_modify_srq(&rdev->qplib_res, &srq->qplib_srq); 1484 if (rc) { 1485 dev_err(rdev_to_dev(rdev), "Modify HW SRQ failed!"); 1486 return rc; 1487 } 1488 /* On success, update the shadow */ 1489 srq->srq_limit = srq_attr->srq_limit; 1490 /* No need to Build and send response back to udata */ 1491 break; 1492 default: 1493 dev_err(rdev_to_dev(rdev), 1494 "Unsupported srq_attr_mask 0x%x", srq_attr_mask); 1495 return -EINVAL; 1496 } 1497 return 0; 1498 } 1499 1500 int bnxt_re_query_srq(struct ib_srq *ib_srq, struct ib_srq_attr *srq_attr) 1501 { 1502 struct bnxt_re_srq *srq = container_of(ib_srq, struct bnxt_re_srq, 1503 ib_srq); 1504 struct bnxt_re_srq tsrq; 1505 struct bnxt_re_dev *rdev = srq->rdev; 1506 int rc; 1507 1508 /* Get live SRQ attr */ 1509 tsrq.qplib_srq.id = srq->qplib_srq.id; 1510 rc = bnxt_qplib_query_srq(&rdev->qplib_res, &tsrq.qplib_srq); 1511 if (rc) { 1512 dev_err(rdev_to_dev(rdev), "Query HW SRQ failed!"); 1513 return rc; 1514 } 1515 srq_attr->max_wr = srq->qplib_srq.max_wqe; 1516 srq_attr->max_sge = srq->qplib_srq.max_sge; 1517 srq_attr->srq_limit = tsrq.qplib_srq.threshold; 1518 1519 return 0; 1520 } 1521 1522 int bnxt_re_post_srq_recv(struct ib_srq *ib_srq, const struct ib_recv_wr *wr, 1523 const struct ib_recv_wr **bad_wr) 1524 { 1525 struct bnxt_re_srq *srq = container_of(ib_srq, struct bnxt_re_srq, 1526 ib_srq); 1527 struct bnxt_qplib_swqe wqe; 1528 unsigned long flags; 1529 int rc = 0; 1530 1531 spin_lock_irqsave(&srq->lock, flags); 1532 while (wr) { 1533 /* Transcribe each ib_recv_wr to qplib_swqe */ 1534 wqe.num_sge = wr->num_sge; 1535 bnxt_re_build_sgl(wr->sg_list, wqe.sg_list, wr->num_sge); 1536 wqe.wr_id = wr->wr_id; 1537 wqe.type = BNXT_QPLIB_SWQE_TYPE_RECV; 1538 1539 rc = bnxt_qplib_post_srq_recv(&srq->qplib_srq, &wqe); 1540 if (rc) { 1541 *bad_wr = wr; 1542 break; 1543 } 1544 wr = wr->next; 1545 } 1546 spin_unlock_irqrestore(&srq->lock, flags); 1547 1548 return rc; 1549 } 1550 static int bnxt_re_modify_shadow_qp(struct bnxt_re_dev *rdev, 1551 struct bnxt_re_qp *qp1_qp, 1552 int qp_attr_mask) 1553 { 1554 struct bnxt_re_qp *qp = rdev->qp1_sqp; 1555 int rc = 0; 1556 1557 if (qp_attr_mask & IB_QP_STATE) { 1558 qp->qplib_qp.modify_flags |= CMDQ_MODIFY_QP_MODIFY_MASK_STATE; 1559 qp->qplib_qp.state = qp1_qp->qplib_qp.state; 1560 } 1561 if (qp_attr_mask & IB_QP_PKEY_INDEX) { 1562 qp->qplib_qp.modify_flags |= CMDQ_MODIFY_QP_MODIFY_MASK_PKEY; 1563 qp->qplib_qp.pkey_index = qp1_qp->qplib_qp.pkey_index; 1564 } 1565 1566 if (qp_attr_mask & IB_QP_QKEY) { 1567 qp->qplib_qp.modify_flags |= CMDQ_MODIFY_QP_MODIFY_MASK_QKEY; 1568 /* Using a Random QKEY */ 1569 qp->qplib_qp.qkey = 0x81818181; 1570 } 1571 if (qp_attr_mask & IB_QP_SQ_PSN) { 1572 qp->qplib_qp.modify_flags |= CMDQ_MODIFY_QP_MODIFY_MASK_SQ_PSN; 1573 qp->qplib_qp.sq.psn = qp1_qp->qplib_qp.sq.psn; 1574 } 1575 1576 rc = bnxt_qplib_modify_qp(&rdev->qplib_res, &qp->qplib_qp); 1577 if (rc) 1578 dev_err(rdev_to_dev(rdev), 1579 "Failed to modify Shadow QP for QP1"); 1580 return rc; 1581 } 1582 1583 int bnxt_re_modify_qp(struct ib_qp *ib_qp, struct ib_qp_attr *qp_attr, 1584 int qp_attr_mask, struct ib_udata *udata) 1585 { 1586 struct bnxt_re_qp *qp = container_of(ib_qp, struct bnxt_re_qp, ib_qp); 1587 struct bnxt_re_dev *rdev = qp->rdev; 1588 struct bnxt_qplib_dev_attr *dev_attr = &rdev->dev_attr; 1589 enum ib_qp_state curr_qp_state, new_qp_state; 1590 int rc, entries; 1591 unsigned int flags; 1592 u8 nw_type; 1593 1594 qp->qplib_qp.modify_flags = 0; 1595 if (qp_attr_mask & IB_QP_STATE) { 1596 curr_qp_state = __to_ib_qp_state(qp->qplib_qp.cur_qp_state); 1597 new_qp_state = qp_attr->qp_state; 1598 if (!ib_modify_qp_is_ok(curr_qp_state, new_qp_state, 1599 ib_qp->qp_type, qp_attr_mask, 1600 IB_LINK_LAYER_ETHERNET)) { 1601 dev_err(rdev_to_dev(rdev), 1602 "Invalid attribute mask: %#x specified ", 1603 qp_attr_mask); 1604 dev_err(rdev_to_dev(rdev), 1605 "for qpn: %#x type: %#x", 1606 ib_qp->qp_num, ib_qp->qp_type); 1607 dev_err(rdev_to_dev(rdev), 1608 "curr_qp_state=0x%x, new_qp_state=0x%x\n", 1609 curr_qp_state, new_qp_state); 1610 return -EINVAL; 1611 } 1612 qp->qplib_qp.modify_flags |= CMDQ_MODIFY_QP_MODIFY_MASK_STATE; 1613 qp->qplib_qp.state = __from_ib_qp_state(qp_attr->qp_state); 1614 1615 if (!qp->sumem && 1616 qp->qplib_qp.state == CMDQ_MODIFY_QP_NEW_STATE_ERR) { 1617 dev_dbg(rdev_to_dev(rdev), 1618 "Move QP = %p to flush list\n", 1619 qp); 1620 flags = bnxt_re_lock_cqs(qp); 1621 bnxt_qplib_add_flush_qp(&qp->qplib_qp); 1622 bnxt_re_unlock_cqs(qp, flags); 1623 } 1624 if (!qp->sumem && 1625 qp->qplib_qp.state == CMDQ_MODIFY_QP_NEW_STATE_RESET) { 1626 dev_dbg(rdev_to_dev(rdev), 1627 "Move QP = %p out of flush list\n", 1628 qp); 1629 flags = bnxt_re_lock_cqs(qp); 1630 bnxt_qplib_clean_qp(&qp->qplib_qp); 1631 bnxt_re_unlock_cqs(qp, flags); 1632 } 1633 } 1634 if (qp_attr_mask & IB_QP_EN_SQD_ASYNC_NOTIFY) { 1635 qp->qplib_qp.modify_flags |= 1636 CMDQ_MODIFY_QP_MODIFY_MASK_EN_SQD_ASYNC_NOTIFY; 1637 qp->qplib_qp.en_sqd_async_notify = true; 1638 } 1639 if (qp_attr_mask & IB_QP_ACCESS_FLAGS) { 1640 qp->qplib_qp.modify_flags |= CMDQ_MODIFY_QP_MODIFY_MASK_ACCESS; 1641 qp->qplib_qp.access = 1642 __from_ib_access_flags(qp_attr->qp_access_flags); 1643 /* LOCAL_WRITE access must be set to allow RC receive */ 1644 qp->qplib_qp.access |= BNXT_QPLIB_ACCESS_LOCAL_WRITE; 1645 } 1646 if (qp_attr_mask & IB_QP_PKEY_INDEX) { 1647 qp->qplib_qp.modify_flags |= CMDQ_MODIFY_QP_MODIFY_MASK_PKEY; 1648 qp->qplib_qp.pkey_index = qp_attr->pkey_index; 1649 } 1650 if (qp_attr_mask & IB_QP_QKEY) { 1651 qp->qplib_qp.modify_flags |= CMDQ_MODIFY_QP_MODIFY_MASK_QKEY; 1652 qp->qplib_qp.qkey = qp_attr->qkey; 1653 } 1654 if (qp_attr_mask & IB_QP_AV) { 1655 const struct ib_global_route *grh = 1656 rdma_ah_read_grh(&qp_attr->ah_attr); 1657 const struct ib_gid_attr *sgid_attr; 1658 1659 qp->qplib_qp.modify_flags |= CMDQ_MODIFY_QP_MODIFY_MASK_DGID | 1660 CMDQ_MODIFY_QP_MODIFY_MASK_FLOW_LABEL | 1661 CMDQ_MODIFY_QP_MODIFY_MASK_SGID_INDEX | 1662 CMDQ_MODIFY_QP_MODIFY_MASK_HOP_LIMIT | 1663 CMDQ_MODIFY_QP_MODIFY_MASK_TRAFFIC_CLASS | 1664 CMDQ_MODIFY_QP_MODIFY_MASK_DEST_MAC | 1665 CMDQ_MODIFY_QP_MODIFY_MASK_VLAN_ID; 1666 memcpy(qp->qplib_qp.ah.dgid.data, grh->dgid.raw, 1667 sizeof(qp->qplib_qp.ah.dgid.data)); 1668 qp->qplib_qp.ah.flow_label = grh->flow_label; 1669 /* If RoCE V2 is enabled, stack will have two entries for 1670 * each GID entry. Avoiding this duplicte entry in HW. Dividing 1671 * the GID index by 2 for RoCE V2 1672 */ 1673 qp->qplib_qp.ah.sgid_index = grh->sgid_index / 2; 1674 qp->qplib_qp.ah.host_sgid_index = grh->sgid_index; 1675 qp->qplib_qp.ah.hop_limit = grh->hop_limit; 1676 qp->qplib_qp.ah.traffic_class = grh->traffic_class; 1677 qp->qplib_qp.ah.sl = rdma_ah_get_sl(&qp_attr->ah_attr); 1678 ether_addr_copy(qp->qplib_qp.ah.dmac, 1679 qp_attr->ah_attr.roce.dmac); 1680 1681 sgid_attr = qp_attr->ah_attr.grh.sgid_attr; 1682 memcpy(qp->qplib_qp.smac, sgid_attr->ndev->dev_addr, 1683 ETH_ALEN); 1684 nw_type = rdma_gid_attr_network_type(sgid_attr); 1685 switch (nw_type) { 1686 case RDMA_NETWORK_IPV4: 1687 qp->qplib_qp.nw_type = 1688 CMDQ_MODIFY_QP_NETWORK_TYPE_ROCEV2_IPV4; 1689 break; 1690 case RDMA_NETWORK_IPV6: 1691 qp->qplib_qp.nw_type = 1692 CMDQ_MODIFY_QP_NETWORK_TYPE_ROCEV2_IPV6; 1693 break; 1694 default: 1695 qp->qplib_qp.nw_type = 1696 CMDQ_MODIFY_QP_NETWORK_TYPE_ROCEV1; 1697 break; 1698 } 1699 } 1700 1701 if (qp_attr_mask & IB_QP_PATH_MTU) { 1702 qp->qplib_qp.modify_flags |= 1703 CMDQ_MODIFY_QP_MODIFY_MASK_PATH_MTU; 1704 qp->qplib_qp.path_mtu = __from_ib_mtu(qp_attr->path_mtu); 1705 qp->qplib_qp.mtu = ib_mtu_enum_to_int(qp_attr->path_mtu); 1706 } else if (qp_attr->qp_state == IB_QPS_RTR) { 1707 qp->qplib_qp.modify_flags |= 1708 CMDQ_MODIFY_QP_MODIFY_MASK_PATH_MTU; 1709 qp->qplib_qp.path_mtu = 1710 __from_ib_mtu(iboe_get_mtu(rdev->netdev->mtu)); 1711 qp->qplib_qp.mtu = 1712 ib_mtu_enum_to_int(iboe_get_mtu(rdev->netdev->mtu)); 1713 } 1714 1715 if (qp_attr_mask & IB_QP_TIMEOUT) { 1716 qp->qplib_qp.modify_flags |= CMDQ_MODIFY_QP_MODIFY_MASK_TIMEOUT; 1717 qp->qplib_qp.timeout = qp_attr->timeout; 1718 } 1719 if (qp_attr_mask & IB_QP_RETRY_CNT) { 1720 qp->qplib_qp.modify_flags |= 1721 CMDQ_MODIFY_QP_MODIFY_MASK_RETRY_CNT; 1722 qp->qplib_qp.retry_cnt = qp_attr->retry_cnt; 1723 } 1724 if (qp_attr_mask & IB_QP_RNR_RETRY) { 1725 qp->qplib_qp.modify_flags |= 1726 CMDQ_MODIFY_QP_MODIFY_MASK_RNR_RETRY; 1727 qp->qplib_qp.rnr_retry = qp_attr->rnr_retry; 1728 } 1729 if (qp_attr_mask & IB_QP_MIN_RNR_TIMER) { 1730 qp->qplib_qp.modify_flags |= 1731 CMDQ_MODIFY_QP_MODIFY_MASK_MIN_RNR_TIMER; 1732 qp->qplib_qp.min_rnr_timer = qp_attr->min_rnr_timer; 1733 } 1734 if (qp_attr_mask & IB_QP_RQ_PSN) { 1735 qp->qplib_qp.modify_flags |= CMDQ_MODIFY_QP_MODIFY_MASK_RQ_PSN; 1736 qp->qplib_qp.rq.psn = qp_attr->rq_psn; 1737 } 1738 if (qp_attr_mask & IB_QP_MAX_QP_RD_ATOMIC) { 1739 qp->qplib_qp.modify_flags |= 1740 CMDQ_MODIFY_QP_MODIFY_MASK_MAX_RD_ATOMIC; 1741 /* Cap the max_rd_atomic to device max */ 1742 qp->qplib_qp.max_rd_atomic = min_t(u32, qp_attr->max_rd_atomic, 1743 dev_attr->max_qp_rd_atom); 1744 } 1745 if (qp_attr_mask & IB_QP_SQ_PSN) { 1746 qp->qplib_qp.modify_flags |= CMDQ_MODIFY_QP_MODIFY_MASK_SQ_PSN; 1747 qp->qplib_qp.sq.psn = qp_attr->sq_psn; 1748 } 1749 if (qp_attr_mask & IB_QP_MAX_DEST_RD_ATOMIC) { 1750 if (qp_attr->max_dest_rd_atomic > 1751 dev_attr->max_qp_init_rd_atom) { 1752 dev_err(rdev_to_dev(rdev), 1753 "max_dest_rd_atomic requested%d is > dev_max%d", 1754 qp_attr->max_dest_rd_atomic, 1755 dev_attr->max_qp_init_rd_atom); 1756 return -EINVAL; 1757 } 1758 1759 qp->qplib_qp.modify_flags |= 1760 CMDQ_MODIFY_QP_MODIFY_MASK_MAX_DEST_RD_ATOMIC; 1761 qp->qplib_qp.max_dest_rd_atomic = qp_attr->max_dest_rd_atomic; 1762 } 1763 if (qp_attr_mask & IB_QP_CAP) { 1764 qp->qplib_qp.modify_flags |= 1765 CMDQ_MODIFY_QP_MODIFY_MASK_SQ_SIZE | 1766 CMDQ_MODIFY_QP_MODIFY_MASK_RQ_SIZE | 1767 CMDQ_MODIFY_QP_MODIFY_MASK_SQ_SGE | 1768 CMDQ_MODIFY_QP_MODIFY_MASK_RQ_SGE | 1769 CMDQ_MODIFY_QP_MODIFY_MASK_MAX_INLINE_DATA; 1770 if ((qp_attr->cap.max_send_wr >= dev_attr->max_qp_wqes) || 1771 (qp_attr->cap.max_recv_wr >= dev_attr->max_qp_wqes) || 1772 (qp_attr->cap.max_send_sge >= dev_attr->max_qp_sges) || 1773 (qp_attr->cap.max_recv_sge >= dev_attr->max_qp_sges) || 1774 (qp_attr->cap.max_inline_data >= 1775 dev_attr->max_inline_data)) { 1776 dev_err(rdev_to_dev(rdev), 1777 "Create QP failed - max exceeded"); 1778 return -EINVAL; 1779 } 1780 entries = roundup_pow_of_two(qp_attr->cap.max_send_wr); 1781 qp->qplib_qp.sq.max_wqe = min_t(u32, entries, 1782 dev_attr->max_qp_wqes + 1); 1783 qp->qplib_qp.sq.q_full_delta = qp->qplib_qp.sq.max_wqe - 1784 qp_attr->cap.max_send_wr; 1785 /* 1786 * Reserving one slot for Phantom WQE. Some application can 1787 * post one extra entry in this case. Allowing this to avoid 1788 * unexpected Queue full condition 1789 */ 1790 qp->qplib_qp.sq.q_full_delta -= 1; 1791 qp->qplib_qp.sq.max_sge = qp_attr->cap.max_send_sge; 1792 if (qp->qplib_qp.rq.max_wqe) { 1793 entries = roundup_pow_of_two(qp_attr->cap.max_recv_wr); 1794 qp->qplib_qp.rq.max_wqe = 1795 min_t(u32, entries, dev_attr->max_qp_wqes + 1); 1796 qp->qplib_qp.rq.q_full_delta = qp->qplib_qp.rq.max_wqe - 1797 qp_attr->cap.max_recv_wr; 1798 qp->qplib_qp.rq.max_sge = qp_attr->cap.max_recv_sge; 1799 } else { 1800 /* SRQ was used prior, just ignore the RQ caps */ 1801 } 1802 } 1803 if (qp_attr_mask & IB_QP_DEST_QPN) { 1804 qp->qplib_qp.modify_flags |= 1805 CMDQ_MODIFY_QP_MODIFY_MASK_DEST_QP_ID; 1806 qp->qplib_qp.dest_qpn = qp_attr->dest_qp_num; 1807 } 1808 rc = bnxt_qplib_modify_qp(&rdev->qplib_res, &qp->qplib_qp); 1809 if (rc) { 1810 dev_err(rdev_to_dev(rdev), "Failed to modify HW QP"); 1811 return rc; 1812 } 1813 if (ib_qp->qp_type == IB_QPT_GSI && rdev->qp1_sqp) 1814 rc = bnxt_re_modify_shadow_qp(rdev, qp, qp_attr_mask); 1815 return rc; 1816 } 1817 1818 int bnxt_re_query_qp(struct ib_qp *ib_qp, struct ib_qp_attr *qp_attr, 1819 int qp_attr_mask, struct ib_qp_init_attr *qp_init_attr) 1820 { 1821 struct bnxt_re_qp *qp = container_of(ib_qp, struct bnxt_re_qp, ib_qp); 1822 struct bnxt_re_dev *rdev = qp->rdev; 1823 struct bnxt_qplib_qp *qplib_qp; 1824 int rc; 1825 1826 qplib_qp = kzalloc(sizeof(*qplib_qp), GFP_KERNEL); 1827 if (!qplib_qp) 1828 return -ENOMEM; 1829 1830 qplib_qp->id = qp->qplib_qp.id; 1831 qplib_qp->ah.host_sgid_index = qp->qplib_qp.ah.host_sgid_index; 1832 1833 rc = bnxt_qplib_query_qp(&rdev->qplib_res, qplib_qp); 1834 if (rc) { 1835 dev_err(rdev_to_dev(rdev), "Failed to query HW QP"); 1836 goto out; 1837 } 1838 qp_attr->qp_state = __to_ib_qp_state(qplib_qp->state); 1839 qp_attr->en_sqd_async_notify = qplib_qp->en_sqd_async_notify ? 1 : 0; 1840 qp_attr->qp_access_flags = __to_ib_access_flags(qplib_qp->access); 1841 qp_attr->pkey_index = qplib_qp->pkey_index; 1842 qp_attr->qkey = qplib_qp->qkey; 1843 qp_attr->ah_attr.type = RDMA_AH_ATTR_TYPE_ROCE; 1844 rdma_ah_set_grh(&qp_attr->ah_attr, NULL, qplib_qp->ah.flow_label, 1845 qplib_qp->ah.host_sgid_index, 1846 qplib_qp->ah.hop_limit, 1847 qplib_qp->ah.traffic_class); 1848 rdma_ah_set_dgid_raw(&qp_attr->ah_attr, qplib_qp->ah.dgid.data); 1849 rdma_ah_set_sl(&qp_attr->ah_attr, qplib_qp->ah.sl); 1850 ether_addr_copy(qp_attr->ah_attr.roce.dmac, qplib_qp->ah.dmac); 1851 qp_attr->path_mtu = __to_ib_mtu(qplib_qp->path_mtu); 1852 qp_attr->timeout = qplib_qp->timeout; 1853 qp_attr->retry_cnt = qplib_qp->retry_cnt; 1854 qp_attr->rnr_retry = qplib_qp->rnr_retry; 1855 qp_attr->min_rnr_timer = qplib_qp->min_rnr_timer; 1856 qp_attr->rq_psn = qplib_qp->rq.psn; 1857 qp_attr->max_rd_atomic = qplib_qp->max_rd_atomic; 1858 qp_attr->sq_psn = qplib_qp->sq.psn; 1859 qp_attr->max_dest_rd_atomic = qplib_qp->max_dest_rd_atomic; 1860 qp_init_attr->sq_sig_type = qplib_qp->sig_type ? IB_SIGNAL_ALL_WR : 1861 IB_SIGNAL_REQ_WR; 1862 qp_attr->dest_qp_num = qplib_qp->dest_qpn; 1863 1864 qp_attr->cap.max_send_wr = qp->qplib_qp.sq.max_wqe; 1865 qp_attr->cap.max_send_sge = qp->qplib_qp.sq.max_sge; 1866 qp_attr->cap.max_recv_wr = qp->qplib_qp.rq.max_wqe; 1867 qp_attr->cap.max_recv_sge = qp->qplib_qp.rq.max_sge; 1868 qp_attr->cap.max_inline_data = qp->qplib_qp.max_inline_data; 1869 qp_init_attr->cap = qp_attr->cap; 1870 1871 out: 1872 kfree(qplib_qp); 1873 return rc; 1874 } 1875 1876 /* Routine for sending QP1 packets for RoCE V1 an V2 1877 */ 1878 static int bnxt_re_build_qp1_send_v2(struct bnxt_re_qp *qp, 1879 const struct ib_send_wr *wr, 1880 struct bnxt_qplib_swqe *wqe, 1881 int payload_size) 1882 { 1883 struct bnxt_re_ah *ah = container_of(ud_wr(wr)->ah, struct bnxt_re_ah, 1884 ib_ah); 1885 struct bnxt_qplib_ah *qplib_ah = &ah->qplib_ah; 1886 const struct ib_gid_attr *sgid_attr = ah->ib_ah.sgid_attr; 1887 struct bnxt_qplib_sge sge; 1888 u8 nw_type; 1889 u16 ether_type; 1890 union ib_gid dgid; 1891 bool is_eth = false; 1892 bool is_vlan = false; 1893 bool is_grh = false; 1894 bool is_udp = false; 1895 u8 ip_version = 0; 1896 u16 vlan_id = 0xFFFF; 1897 void *buf; 1898 int i, rc = 0; 1899 1900 memset(&qp->qp1_hdr, 0, sizeof(qp->qp1_hdr)); 1901 1902 if (is_vlan_dev(sgid_attr->ndev)) 1903 vlan_id = vlan_dev_vlan_id(sgid_attr->ndev); 1904 /* Get network header type for this GID */ 1905 nw_type = rdma_gid_attr_network_type(sgid_attr); 1906 switch (nw_type) { 1907 case RDMA_NETWORK_IPV4: 1908 nw_type = BNXT_RE_ROCEV2_IPV4_PACKET; 1909 break; 1910 case RDMA_NETWORK_IPV6: 1911 nw_type = BNXT_RE_ROCEV2_IPV6_PACKET; 1912 break; 1913 default: 1914 nw_type = BNXT_RE_ROCE_V1_PACKET; 1915 break; 1916 } 1917 memcpy(&dgid.raw, &qplib_ah->dgid, 16); 1918 is_udp = sgid_attr->gid_type == IB_GID_TYPE_ROCE_UDP_ENCAP; 1919 if (is_udp) { 1920 if (ipv6_addr_v4mapped((struct in6_addr *)&sgid_attr->gid)) { 1921 ip_version = 4; 1922 ether_type = ETH_P_IP; 1923 } else { 1924 ip_version = 6; 1925 ether_type = ETH_P_IPV6; 1926 } 1927 is_grh = false; 1928 } else { 1929 ether_type = ETH_P_IBOE; 1930 is_grh = true; 1931 } 1932 1933 is_eth = true; 1934 is_vlan = (vlan_id && (vlan_id < 0x1000)) ? true : false; 1935 1936 ib_ud_header_init(payload_size, !is_eth, is_eth, is_vlan, is_grh, 1937 ip_version, is_udp, 0, &qp->qp1_hdr); 1938 1939 /* ETH */ 1940 ether_addr_copy(qp->qp1_hdr.eth.dmac_h, ah->qplib_ah.dmac); 1941 ether_addr_copy(qp->qp1_hdr.eth.smac_h, qp->qplib_qp.smac); 1942 1943 /* For vlan, check the sgid for vlan existence */ 1944 1945 if (!is_vlan) { 1946 qp->qp1_hdr.eth.type = cpu_to_be16(ether_type); 1947 } else { 1948 qp->qp1_hdr.vlan.type = cpu_to_be16(ether_type); 1949 qp->qp1_hdr.vlan.tag = cpu_to_be16(vlan_id); 1950 } 1951 1952 if (is_grh || (ip_version == 6)) { 1953 memcpy(qp->qp1_hdr.grh.source_gid.raw, sgid_attr->gid.raw, 1954 sizeof(sgid_attr->gid)); 1955 memcpy(qp->qp1_hdr.grh.destination_gid.raw, qplib_ah->dgid.data, 1956 sizeof(sgid_attr->gid)); 1957 qp->qp1_hdr.grh.hop_limit = qplib_ah->hop_limit; 1958 } 1959 1960 if (ip_version == 4) { 1961 qp->qp1_hdr.ip4.tos = 0; 1962 qp->qp1_hdr.ip4.id = 0; 1963 qp->qp1_hdr.ip4.frag_off = htons(IP_DF); 1964 qp->qp1_hdr.ip4.ttl = qplib_ah->hop_limit; 1965 1966 memcpy(&qp->qp1_hdr.ip4.saddr, sgid_attr->gid.raw + 12, 4); 1967 memcpy(&qp->qp1_hdr.ip4.daddr, qplib_ah->dgid.data + 12, 4); 1968 qp->qp1_hdr.ip4.check = ib_ud_ip4_csum(&qp->qp1_hdr); 1969 } 1970 1971 if (is_udp) { 1972 qp->qp1_hdr.udp.dport = htons(ROCE_V2_UDP_DPORT); 1973 qp->qp1_hdr.udp.sport = htons(0x8CD1); 1974 qp->qp1_hdr.udp.csum = 0; 1975 } 1976 1977 /* BTH */ 1978 if (wr->opcode == IB_WR_SEND_WITH_IMM) { 1979 qp->qp1_hdr.bth.opcode = IB_OPCODE_UD_SEND_ONLY_WITH_IMMEDIATE; 1980 qp->qp1_hdr.immediate_present = 1; 1981 } else { 1982 qp->qp1_hdr.bth.opcode = IB_OPCODE_UD_SEND_ONLY; 1983 } 1984 if (wr->send_flags & IB_SEND_SOLICITED) 1985 qp->qp1_hdr.bth.solicited_event = 1; 1986 /* pad_count */ 1987 qp->qp1_hdr.bth.pad_count = (4 - payload_size) & 3; 1988 1989 /* P_key for QP1 is for all members */ 1990 qp->qp1_hdr.bth.pkey = cpu_to_be16(0xFFFF); 1991 qp->qp1_hdr.bth.destination_qpn = IB_QP1; 1992 qp->qp1_hdr.bth.ack_req = 0; 1993 qp->send_psn++; 1994 qp->send_psn &= BTH_PSN_MASK; 1995 qp->qp1_hdr.bth.psn = cpu_to_be32(qp->send_psn); 1996 /* DETH */ 1997 /* Use the priviledged Q_Key for QP1 */ 1998 qp->qp1_hdr.deth.qkey = cpu_to_be32(IB_QP1_QKEY); 1999 qp->qp1_hdr.deth.source_qpn = IB_QP1; 2000 2001 /* Pack the QP1 to the transmit buffer */ 2002 buf = bnxt_qplib_get_qp1_sq_buf(&qp->qplib_qp, &sge); 2003 if (buf) { 2004 ib_ud_header_pack(&qp->qp1_hdr, buf); 2005 for (i = wqe->num_sge; i; i--) { 2006 wqe->sg_list[i].addr = wqe->sg_list[i - 1].addr; 2007 wqe->sg_list[i].lkey = wqe->sg_list[i - 1].lkey; 2008 wqe->sg_list[i].size = wqe->sg_list[i - 1].size; 2009 } 2010 2011 /* 2012 * Max Header buf size for IPV6 RoCE V2 is 86, 2013 * which is same as the QP1 SQ header buffer. 2014 * Header buf size for IPV4 RoCE V2 can be 66. 2015 * ETH(14) + VLAN(4)+ IP(20) + UDP (8) + BTH(20). 2016 * Subtract 20 bytes from QP1 SQ header buf size 2017 */ 2018 if (is_udp && ip_version == 4) 2019 sge.size -= 20; 2020 /* 2021 * Max Header buf size for RoCE V1 is 78. 2022 * ETH(14) + VLAN(4) + GRH(40) + BTH(20). 2023 * Subtract 8 bytes from QP1 SQ header buf size 2024 */ 2025 if (!is_udp) 2026 sge.size -= 8; 2027 2028 /* Subtract 4 bytes for non vlan packets */ 2029 if (!is_vlan) 2030 sge.size -= 4; 2031 2032 wqe->sg_list[0].addr = sge.addr; 2033 wqe->sg_list[0].lkey = sge.lkey; 2034 wqe->sg_list[0].size = sge.size; 2035 wqe->num_sge++; 2036 2037 } else { 2038 dev_err(rdev_to_dev(qp->rdev), "QP1 buffer is empty!"); 2039 rc = -ENOMEM; 2040 } 2041 return rc; 2042 } 2043 2044 /* For the MAD layer, it only provides the recv SGE the size of 2045 * ib_grh + MAD datagram. No Ethernet headers, Ethertype, BTH, DETH, 2046 * nor RoCE iCRC. The Cu+ solution must provide buffer for the entire 2047 * receive packet (334 bytes) with no VLAN and then copy the GRH 2048 * and the MAD datagram out to the provided SGE. 2049 */ 2050 static int bnxt_re_build_qp1_shadow_qp_recv(struct bnxt_re_qp *qp, 2051 const struct ib_recv_wr *wr, 2052 struct bnxt_qplib_swqe *wqe, 2053 int payload_size) 2054 { 2055 struct bnxt_qplib_sge ref, sge; 2056 u32 rq_prod_index; 2057 struct bnxt_re_sqp_entries *sqp_entry; 2058 2059 rq_prod_index = bnxt_qplib_get_rq_prod_index(&qp->qplib_qp); 2060 2061 if (!bnxt_qplib_get_qp1_rq_buf(&qp->qplib_qp, &sge)) 2062 return -ENOMEM; 2063 2064 /* Create 1 SGE to receive the entire 2065 * ethernet packet 2066 */ 2067 /* Save the reference from ULP */ 2068 ref.addr = wqe->sg_list[0].addr; 2069 ref.lkey = wqe->sg_list[0].lkey; 2070 ref.size = wqe->sg_list[0].size; 2071 2072 sqp_entry = &qp->rdev->sqp_tbl[rq_prod_index]; 2073 2074 /* SGE 1 */ 2075 wqe->sg_list[0].addr = sge.addr; 2076 wqe->sg_list[0].lkey = sge.lkey; 2077 wqe->sg_list[0].size = BNXT_QPLIB_MAX_QP1_RQ_HDR_SIZE_V2; 2078 sge.size -= wqe->sg_list[0].size; 2079 2080 sqp_entry->sge.addr = ref.addr; 2081 sqp_entry->sge.lkey = ref.lkey; 2082 sqp_entry->sge.size = ref.size; 2083 /* Store the wrid for reporting completion */ 2084 sqp_entry->wrid = wqe->wr_id; 2085 /* change the wqe->wrid to table index */ 2086 wqe->wr_id = rq_prod_index; 2087 return 0; 2088 } 2089 2090 static int is_ud_qp(struct bnxt_re_qp *qp) 2091 { 2092 return qp->qplib_qp.type == CMDQ_CREATE_QP_TYPE_UD; 2093 } 2094 2095 static int bnxt_re_build_send_wqe(struct bnxt_re_qp *qp, 2096 const struct ib_send_wr *wr, 2097 struct bnxt_qplib_swqe *wqe) 2098 { 2099 struct bnxt_re_ah *ah = NULL; 2100 2101 if (is_ud_qp(qp)) { 2102 ah = container_of(ud_wr(wr)->ah, struct bnxt_re_ah, ib_ah); 2103 wqe->send.q_key = ud_wr(wr)->remote_qkey; 2104 wqe->send.dst_qp = ud_wr(wr)->remote_qpn; 2105 wqe->send.avid = ah->qplib_ah.id; 2106 } 2107 switch (wr->opcode) { 2108 case IB_WR_SEND: 2109 wqe->type = BNXT_QPLIB_SWQE_TYPE_SEND; 2110 break; 2111 case IB_WR_SEND_WITH_IMM: 2112 wqe->type = BNXT_QPLIB_SWQE_TYPE_SEND_WITH_IMM; 2113 wqe->send.imm_data = wr->ex.imm_data; 2114 break; 2115 case IB_WR_SEND_WITH_INV: 2116 wqe->type = BNXT_QPLIB_SWQE_TYPE_SEND_WITH_INV; 2117 wqe->send.inv_key = wr->ex.invalidate_rkey; 2118 break; 2119 default: 2120 return -EINVAL; 2121 } 2122 if (wr->send_flags & IB_SEND_SIGNALED) 2123 wqe->flags |= BNXT_QPLIB_SWQE_FLAGS_SIGNAL_COMP; 2124 if (wr->send_flags & IB_SEND_FENCE) 2125 wqe->flags |= BNXT_QPLIB_SWQE_FLAGS_UC_FENCE; 2126 if (wr->send_flags & IB_SEND_SOLICITED) 2127 wqe->flags |= BNXT_QPLIB_SWQE_FLAGS_SOLICIT_EVENT; 2128 if (wr->send_flags & IB_SEND_INLINE) 2129 wqe->flags |= BNXT_QPLIB_SWQE_FLAGS_INLINE; 2130 2131 return 0; 2132 } 2133 2134 static int bnxt_re_build_rdma_wqe(const struct ib_send_wr *wr, 2135 struct bnxt_qplib_swqe *wqe) 2136 { 2137 switch (wr->opcode) { 2138 case IB_WR_RDMA_WRITE: 2139 wqe->type = BNXT_QPLIB_SWQE_TYPE_RDMA_WRITE; 2140 break; 2141 case IB_WR_RDMA_WRITE_WITH_IMM: 2142 wqe->type = BNXT_QPLIB_SWQE_TYPE_RDMA_WRITE_WITH_IMM; 2143 wqe->rdma.imm_data = wr->ex.imm_data; 2144 break; 2145 case IB_WR_RDMA_READ: 2146 wqe->type = BNXT_QPLIB_SWQE_TYPE_RDMA_READ; 2147 wqe->rdma.inv_key = wr->ex.invalidate_rkey; 2148 break; 2149 default: 2150 return -EINVAL; 2151 } 2152 wqe->rdma.remote_va = rdma_wr(wr)->remote_addr; 2153 wqe->rdma.r_key = rdma_wr(wr)->rkey; 2154 if (wr->send_flags & IB_SEND_SIGNALED) 2155 wqe->flags |= BNXT_QPLIB_SWQE_FLAGS_SIGNAL_COMP; 2156 if (wr->send_flags & IB_SEND_FENCE) 2157 wqe->flags |= BNXT_QPLIB_SWQE_FLAGS_UC_FENCE; 2158 if (wr->send_flags & IB_SEND_SOLICITED) 2159 wqe->flags |= BNXT_QPLIB_SWQE_FLAGS_SOLICIT_EVENT; 2160 if (wr->send_flags & IB_SEND_INLINE) 2161 wqe->flags |= BNXT_QPLIB_SWQE_FLAGS_INLINE; 2162 2163 return 0; 2164 } 2165 2166 static int bnxt_re_build_atomic_wqe(const struct ib_send_wr *wr, 2167 struct bnxt_qplib_swqe *wqe) 2168 { 2169 switch (wr->opcode) { 2170 case IB_WR_ATOMIC_CMP_AND_SWP: 2171 wqe->type = BNXT_QPLIB_SWQE_TYPE_ATOMIC_CMP_AND_SWP; 2172 wqe->atomic.cmp_data = atomic_wr(wr)->compare_add; 2173 wqe->atomic.swap_data = atomic_wr(wr)->swap; 2174 break; 2175 case IB_WR_ATOMIC_FETCH_AND_ADD: 2176 wqe->type = BNXT_QPLIB_SWQE_TYPE_ATOMIC_FETCH_AND_ADD; 2177 wqe->atomic.cmp_data = atomic_wr(wr)->compare_add; 2178 break; 2179 default: 2180 return -EINVAL; 2181 } 2182 wqe->atomic.remote_va = atomic_wr(wr)->remote_addr; 2183 wqe->atomic.r_key = atomic_wr(wr)->rkey; 2184 if (wr->send_flags & IB_SEND_SIGNALED) 2185 wqe->flags |= BNXT_QPLIB_SWQE_FLAGS_SIGNAL_COMP; 2186 if (wr->send_flags & IB_SEND_FENCE) 2187 wqe->flags |= BNXT_QPLIB_SWQE_FLAGS_UC_FENCE; 2188 if (wr->send_flags & IB_SEND_SOLICITED) 2189 wqe->flags |= BNXT_QPLIB_SWQE_FLAGS_SOLICIT_EVENT; 2190 return 0; 2191 } 2192 2193 static int bnxt_re_build_inv_wqe(const struct ib_send_wr *wr, 2194 struct bnxt_qplib_swqe *wqe) 2195 { 2196 wqe->type = BNXT_QPLIB_SWQE_TYPE_LOCAL_INV; 2197 wqe->local_inv.inv_l_key = wr->ex.invalidate_rkey; 2198 2199 /* Need unconditional fence for local invalidate 2200 * opcode to work as expected. 2201 */ 2202 wqe->flags |= BNXT_QPLIB_SWQE_FLAGS_UC_FENCE; 2203 2204 if (wr->send_flags & IB_SEND_SIGNALED) 2205 wqe->flags |= BNXT_QPLIB_SWQE_FLAGS_SIGNAL_COMP; 2206 if (wr->send_flags & IB_SEND_SOLICITED) 2207 wqe->flags |= BNXT_QPLIB_SWQE_FLAGS_SOLICIT_EVENT; 2208 2209 return 0; 2210 } 2211 2212 static int bnxt_re_build_reg_wqe(const struct ib_reg_wr *wr, 2213 struct bnxt_qplib_swqe *wqe) 2214 { 2215 struct bnxt_re_mr *mr = container_of(wr->mr, struct bnxt_re_mr, ib_mr); 2216 struct bnxt_qplib_frpl *qplib_frpl = &mr->qplib_frpl; 2217 int access = wr->access; 2218 2219 wqe->frmr.pbl_ptr = (__le64 *)qplib_frpl->hwq.pbl_ptr[0]; 2220 wqe->frmr.pbl_dma_ptr = qplib_frpl->hwq.pbl_dma_ptr[0]; 2221 wqe->frmr.page_list = mr->pages; 2222 wqe->frmr.page_list_len = mr->npages; 2223 wqe->frmr.levels = qplib_frpl->hwq.level + 1; 2224 wqe->type = BNXT_QPLIB_SWQE_TYPE_REG_MR; 2225 2226 /* Need unconditional fence for reg_mr 2227 * opcode to function as expected. 2228 */ 2229 2230 wqe->flags |= BNXT_QPLIB_SWQE_FLAGS_UC_FENCE; 2231 2232 if (wr->wr.send_flags & IB_SEND_SIGNALED) 2233 wqe->flags |= BNXT_QPLIB_SWQE_FLAGS_SIGNAL_COMP; 2234 2235 if (access & IB_ACCESS_LOCAL_WRITE) 2236 wqe->frmr.access_cntl |= SQ_FR_PMR_ACCESS_CNTL_LOCAL_WRITE; 2237 if (access & IB_ACCESS_REMOTE_READ) 2238 wqe->frmr.access_cntl |= SQ_FR_PMR_ACCESS_CNTL_REMOTE_READ; 2239 if (access & IB_ACCESS_REMOTE_WRITE) 2240 wqe->frmr.access_cntl |= SQ_FR_PMR_ACCESS_CNTL_REMOTE_WRITE; 2241 if (access & IB_ACCESS_REMOTE_ATOMIC) 2242 wqe->frmr.access_cntl |= SQ_FR_PMR_ACCESS_CNTL_REMOTE_ATOMIC; 2243 if (access & IB_ACCESS_MW_BIND) 2244 wqe->frmr.access_cntl |= SQ_FR_PMR_ACCESS_CNTL_WINDOW_BIND; 2245 2246 wqe->frmr.l_key = wr->key; 2247 wqe->frmr.length = wr->mr->length; 2248 wqe->frmr.pbl_pg_sz_log = (wr->mr->page_size >> PAGE_SHIFT_4K) - 1; 2249 wqe->frmr.va = wr->mr->iova; 2250 return 0; 2251 } 2252 2253 static int bnxt_re_copy_inline_data(struct bnxt_re_dev *rdev, 2254 const struct ib_send_wr *wr, 2255 struct bnxt_qplib_swqe *wqe) 2256 { 2257 /* Copy the inline data to the data field */ 2258 u8 *in_data; 2259 u32 i, sge_len; 2260 void *sge_addr; 2261 2262 in_data = wqe->inline_data; 2263 for (i = 0; i < wr->num_sge; i++) { 2264 sge_addr = (void *)(unsigned long) 2265 wr->sg_list[i].addr; 2266 sge_len = wr->sg_list[i].length; 2267 2268 if ((sge_len + wqe->inline_len) > 2269 BNXT_QPLIB_SWQE_MAX_INLINE_LENGTH) { 2270 dev_err(rdev_to_dev(rdev), 2271 "Inline data size requested > supported value"); 2272 return -EINVAL; 2273 } 2274 sge_len = wr->sg_list[i].length; 2275 2276 memcpy(in_data, sge_addr, sge_len); 2277 in_data += wr->sg_list[i].length; 2278 wqe->inline_len += wr->sg_list[i].length; 2279 } 2280 return wqe->inline_len; 2281 } 2282 2283 static int bnxt_re_copy_wr_payload(struct bnxt_re_dev *rdev, 2284 const struct ib_send_wr *wr, 2285 struct bnxt_qplib_swqe *wqe) 2286 { 2287 int payload_sz = 0; 2288 2289 if (wr->send_flags & IB_SEND_INLINE) 2290 payload_sz = bnxt_re_copy_inline_data(rdev, wr, wqe); 2291 else 2292 payload_sz = bnxt_re_build_sgl(wr->sg_list, wqe->sg_list, 2293 wqe->num_sge); 2294 2295 return payload_sz; 2296 } 2297 2298 static void bnxt_ud_qp_hw_stall_workaround(struct bnxt_re_qp *qp) 2299 { 2300 if ((qp->ib_qp.qp_type == IB_QPT_UD || 2301 qp->ib_qp.qp_type == IB_QPT_GSI || 2302 qp->ib_qp.qp_type == IB_QPT_RAW_ETHERTYPE) && 2303 qp->qplib_qp.wqe_cnt == BNXT_RE_UD_QP_HW_STALL) { 2304 int qp_attr_mask; 2305 struct ib_qp_attr qp_attr; 2306 2307 qp_attr_mask = IB_QP_STATE; 2308 qp_attr.qp_state = IB_QPS_RTS; 2309 bnxt_re_modify_qp(&qp->ib_qp, &qp_attr, qp_attr_mask, NULL); 2310 qp->qplib_qp.wqe_cnt = 0; 2311 } 2312 } 2313 2314 static int bnxt_re_post_send_shadow_qp(struct bnxt_re_dev *rdev, 2315 struct bnxt_re_qp *qp, 2316 const struct ib_send_wr *wr) 2317 { 2318 struct bnxt_qplib_swqe wqe; 2319 int rc = 0, payload_sz = 0; 2320 unsigned long flags; 2321 2322 spin_lock_irqsave(&qp->sq_lock, flags); 2323 memset(&wqe, 0, sizeof(wqe)); 2324 while (wr) { 2325 /* House keeping */ 2326 memset(&wqe, 0, sizeof(wqe)); 2327 2328 /* Common */ 2329 wqe.num_sge = wr->num_sge; 2330 if (wr->num_sge > qp->qplib_qp.sq.max_sge) { 2331 dev_err(rdev_to_dev(rdev), 2332 "Limit exceeded for Send SGEs"); 2333 rc = -EINVAL; 2334 goto bad; 2335 } 2336 2337 payload_sz = bnxt_re_copy_wr_payload(qp->rdev, wr, &wqe); 2338 if (payload_sz < 0) { 2339 rc = -EINVAL; 2340 goto bad; 2341 } 2342 wqe.wr_id = wr->wr_id; 2343 2344 wqe.type = BNXT_QPLIB_SWQE_TYPE_SEND; 2345 2346 rc = bnxt_re_build_send_wqe(qp, wr, &wqe); 2347 if (!rc) 2348 rc = bnxt_qplib_post_send(&qp->qplib_qp, &wqe); 2349 bad: 2350 if (rc) { 2351 dev_err(rdev_to_dev(rdev), 2352 "Post send failed opcode = %#x rc = %d", 2353 wr->opcode, rc); 2354 break; 2355 } 2356 wr = wr->next; 2357 } 2358 bnxt_qplib_post_send_db(&qp->qplib_qp); 2359 bnxt_ud_qp_hw_stall_workaround(qp); 2360 spin_unlock_irqrestore(&qp->sq_lock, flags); 2361 return rc; 2362 } 2363 2364 int bnxt_re_post_send(struct ib_qp *ib_qp, const struct ib_send_wr *wr, 2365 const struct ib_send_wr **bad_wr) 2366 { 2367 struct bnxt_re_qp *qp = container_of(ib_qp, struct bnxt_re_qp, ib_qp); 2368 struct bnxt_qplib_swqe wqe; 2369 int rc = 0, payload_sz = 0; 2370 unsigned long flags; 2371 2372 spin_lock_irqsave(&qp->sq_lock, flags); 2373 while (wr) { 2374 /* House keeping */ 2375 memset(&wqe, 0, sizeof(wqe)); 2376 2377 /* Common */ 2378 wqe.num_sge = wr->num_sge; 2379 if (wr->num_sge > qp->qplib_qp.sq.max_sge) { 2380 dev_err(rdev_to_dev(qp->rdev), 2381 "Limit exceeded for Send SGEs"); 2382 rc = -EINVAL; 2383 goto bad; 2384 } 2385 2386 payload_sz = bnxt_re_copy_wr_payload(qp->rdev, wr, &wqe); 2387 if (payload_sz < 0) { 2388 rc = -EINVAL; 2389 goto bad; 2390 } 2391 wqe.wr_id = wr->wr_id; 2392 2393 switch (wr->opcode) { 2394 case IB_WR_SEND: 2395 case IB_WR_SEND_WITH_IMM: 2396 if (ib_qp->qp_type == IB_QPT_GSI) { 2397 rc = bnxt_re_build_qp1_send_v2(qp, wr, &wqe, 2398 payload_sz); 2399 if (rc) 2400 goto bad; 2401 wqe.rawqp1.lflags |= 2402 SQ_SEND_RAWETH_QP1_LFLAGS_ROCE_CRC; 2403 } 2404 switch (wr->send_flags) { 2405 case IB_SEND_IP_CSUM: 2406 wqe.rawqp1.lflags |= 2407 SQ_SEND_RAWETH_QP1_LFLAGS_IP_CHKSUM; 2408 break; 2409 default: 2410 break; 2411 } 2412 /* fall through */ 2413 case IB_WR_SEND_WITH_INV: 2414 rc = bnxt_re_build_send_wqe(qp, wr, &wqe); 2415 break; 2416 case IB_WR_RDMA_WRITE: 2417 case IB_WR_RDMA_WRITE_WITH_IMM: 2418 case IB_WR_RDMA_READ: 2419 rc = bnxt_re_build_rdma_wqe(wr, &wqe); 2420 break; 2421 case IB_WR_ATOMIC_CMP_AND_SWP: 2422 case IB_WR_ATOMIC_FETCH_AND_ADD: 2423 rc = bnxt_re_build_atomic_wqe(wr, &wqe); 2424 break; 2425 case IB_WR_RDMA_READ_WITH_INV: 2426 dev_err(rdev_to_dev(qp->rdev), 2427 "RDMA Read with Invalidate is not supported"); 2428 rc = -EINVAL; 2429 goto bad; 2430 case IB_WR_LOCAL_INV: 2431 rc = bnxt_re_build_inv_wqe(wr, &wqe); 2432 break; 2433 case IB_WR_REG_MR: 2434 rc = bnxt_re_build_reg_wqe(reg_wr(wr), &wqe); 2435 break; 2436 default: 2437 /* Unsupported WRs */ 2438 dev_err(rdev_to_dev(qp->rdev), 2439 "WR (%#x) is not supported", wr->opcode); 2440 rc = -EINVAL; 2441 goto bad; 2442 } 2443 if (!rc) 2444 rc = bnxt_qplib_post_send(&qp->qplib_qp, &wqe); 2445 bad: 2446 if (rc) { 2447 dev_err(rdev_to_dev(qp->rdev), 2448 "post_send failed op:%#x qps = %#x rc = %d\n", 2449 wr->opcode, qp->qplib_qp.state, rc); 2450 *bad_wr = wr; 2451 break; 2452 } 2453 wr = wr->next; 2454 } 2455 bnxt_qplib_post_send_db(&qp->qplib_qp); 2456 bnxt_ud_qp_hw_stall_workaround(qp); 2457 spin_unlock_irqrestore(&qp->sq_lock, flags); 2458 2459 return rc; 2460 } 2461 2462 static int bnxt_re_post_recv_shadow_qp(struct bnxt_re_dev *rdev, 2463 struct bnxt_re_qp *qp, 2464 const struct ib_recv_wr *wr) 2465 { 2466 struct bnxt_qplib_swqe wqe; 2467 int rc = 0; 2468 2469 memset(&wqe, 0, sizeof(wqe)); 2470 while (wr) { 2471 /* House keeping */ 2472 memset(&wqe, 0, sizeof(wqe)); 2473 2474 /* Common */ 2475 wqe.num_sge = wr->num_sge; 2476 if (wr->num_sge > qp->qplib_qp.rq.max_sge) { 2477 dev_err(rdev_to_dev(rdev), 2478 "Limit exceeded for Receive SGEs"); 2479 rc = -EINVAL; 2480 break; 2481 } 2482 bnxt_re_build_sgl(wr->sg_list, wqe.sg_list, wr->num_sge); 2483 wqe.wr_id = wr->wr_id; 2484 wqe.type = BNXT_QPLIB_SWQE_TYPE_RECV; 2485 2486 rc = bnxt_qplib_post_recv(&qp->qplib_qp, &wqe); 2487 if (rc) 2488 break; 2489 2490 wr = wr->next; 2491 } 2492 if (!rc) 2493 bnxt_qplib_post_recv_db(&qp->qplib_qp); 2494 return rc; 2495 } 2496 2497 int bnxt_re_post_recv(struct ib_qp *ib_qp, const struct ib_recv_wr *wr, 2498 const struct ib_recv_wr **bad_wr) 2499 { 2500 struct bnxt_re_qp *qp = container_of(ib_qp, struct bnxt_re_qp, ib_qp); 2501 struct bnxt_qplib_swqe wqe; 2502 int rc = 0, payload_sz = 0; 2503 unsigned long flags; 2504 u32 count = 0; 2505 2506 spin_lock_irqsave(&qp->rq_lock, flags); 2507 while (wr) { 2508 /* House keeping */ 2509 memset(&wqe, 0, sizeof(wqe)); 2510 2511 /* Common */ 2512 wqe.num_sge = wr->num_sge; 2513 if (wr->num_sge > qp->qplib_qp.rq.max_sge) { 2514 dev_err(rdev_to_dev(qp->rdev), 2515 "Limit exceeded for Receive SGEs"); 2516 rc = -EINVAL; 2517 *bad_wr = wr; 2518 break; 2519 } 2520 2521 payload_sz = bnxt_re_build_sgl(wr->sg_list, wqe.sg_list, 2522 wr->num_sge); 2523 wqe.wr_id = wr->wr_id; 2524 wqe.type = BNXT_QPLIB_SWQE_TYPE_RECV; 2525 2526 if (ib_qp->qp_type == IB_QPT_GSI) 2527 rc = bnxt_re_build_qp1_shadow_qp_recv(qp, wr, &wqe, 2528 payload_sz); 2529 if (!rc) 2530 rc = bnxt_qplib_post_recv(&qp->qplib_qp, &wqe); 2531 if (rc) { 2532 *bad_wr = wr; 2533 break; 2534 } 2535 2536 /* Ring DB if the RQEs posted reaches a threshold value */ 2537 if (++count >= BNXT_RE_RQ_WQE_THRESHOLD) { 2538 bnxt_qplib_post_recv_db(&qp->qplib_qp); 2539 count = 0; 2540 } 2541 2542 wr = wr->next; 2543 } 2544 2545 if (count) 2546 bnxt_qplib_post_recv_db(&qp->qplib_qp); 2547 2548 spin_unlock_irqrestore(&qp->rq_lock, flags); 2549 2550 return rc; 2551 } 2552 2553 /* Completion Queues */ 2554 int bnxt_re_destroy_cq(struct ib_cq *ib_cq) 2555 { 2556 int rc; 2557 struct bnxt_re_cq *cq; 2558 struct bnxt_qplib_nq *nq; 2559 struct bnxt_re_dev *rdev; 2560 2561 cq = container_of(ib_cq, struct bnxt_re_cq, ib_cq); 2562 rdev = cq->rdev; 2563 nq = cq->qplib_cq.nq; 2564 2565 rc = bnxt_qplib_destroy_cq(&rdev->qplib_res, &cq->qplib_cq); 2566 if (rc) { 2567 dev_err(rdev_to_dev(rdev), "Failed to destroy HW CQ"); 2568 return rc; 2569 } 2570 if (!IS_ERR_OR_NULL(cq->umem)) 2571 ib_umem_release(cq->umem); 2572 2573 atomic_dec(&rdev->cq_count); 2574 nq->budget--; 2575 kfree(cq->cql); 2576 kfree(cq); 2577 2578 return 0; 2579 } 2580 2581 struct ib_cq *bnxt_re_create_cq(struct ib_device *ibdev, 2582 const struct ib_cq_init_attr *attr, 2583 struct ib_ucontext *context, 2584 struct ib_udata *udata) 2585 { 2586 struct bnxt_re_dev *rdev = to_bnxt_re_dev(ibdev, ibdev); 2587 struct bnxt_qplib_dev_attr *dev_attr = &rdev->dev_attr; 2588 struct bnxt_re_cq *cq = NULL; 2589 int rc, entries; 2590 int cqe = attr->cqe; 2591 struct bnxt_qplib_nq *nq = NULL; 2592 unsigned int nq_alloc_cnt; 2593 2594 /* Validate CQ fields */ 2595 if (cqe < 1 || cqe > dev_attr->max_cq_wqes) { 2596 dev_err(rdev_to_dev(rdev), "Failed to create CQ -max exceeded"); 2597 return ERR_PTR(-EINVAL); 2598 } 2599 cq = kzalloc(sizeof(*cq), GFP_KERNEL); 2600 if (!cq) 2601 return ERR_PTR(-ENOMEM); 2602 2603 cq->rdev = rdev; 2604 cq->qplib_cq.cq_handle = (u64)(unsigned long)(&cq->qplib_cq); 2605 2606 entries = roundup_pow_of_two(cqe + 1); 2607 if (entries > dev_attr->max_cq_wqes + 1) 2608 entries = dev_attr->max_cq_wqes + 1; 2609 2610 if (context) { 2611 struct bnxt_re_cq_req req; 2612 struct bnxt_re_ucontext *uctx = container_of 2613 (context, 2614 struct bnxt_re_ucontext, 2615 ib_uctx); 2616 if (ib_copy_from_udata(&req, udata, sizeof(req))) { 2617 rc = -EFAULT; 2618 goto fail; 2619 } 2620 2621 cq->umem = ib_umem_get(context, req.cq_va, 2622 entries * sizeof(struct cq_base), 2623 IB_ACCESS_LOCAL_WRITE, 1); 2624 if (IS_ERR(cq->umem)) { 2625 rc = PTR_ERR(cq->umem); 2626 goto fail; 2627 } 2628 cq->qplib_cq.sghead = cq->umem->sg_head.sgl; 2629 cq->qplib_cq.nmap = cq->umem->nmap; 2630 cq->qplib_cq.dpi = &uctx->dpi; 2631 } else { 2632 cq->max_cql = min_t(u32, entries, MAX_CQL_PER_POLL); 2633 cq->cql = kcalloc(cq->max_cql, sizeof(struct bnxt_qplib_cqe), 2634 GFP_KERNEL); 2635 if (!cq->cql) { 2636 rc = -ENOMEM; 2637 goto fail; 2638 } 2639 2640 cq->qplib_cq.dpi = &rdev->dpi_privileged; 2641 cq->qplib_cq.sghead = NULL; 2642 cq->qplib_cq.nmap = 0; 2643 } 2644 /* 2645 * Allocating the NQ in a round robin fashion. nq_alloc_cnt is a 2646 * used for getting the NQ index. 2647 */ 2648 nq_alloc_cnt = atomic_inc_return(&rdev->nq_alloc_cnt); 2649 nq = &rdev->nq[nq_alloc_cnt % (rdev->num_msix - 1)]; 2650 cq->qplib_cq.max_wqe = entries; 2651 cq->qplib_cq.cnq_hw_ring_id = nq->ring_id; 2652 cq->qplib_cq.nq = nq; 2653 2654 rc = bnxt_qplib_create_cq(&rdev->qplib_res, &cq->qplib_cq); 2655 if (rc) { 2656 dev_err(rdev_to_dev(rdev), "Failed to create HW CQ"); 2657 goto fail; 2658 } 2659 2660 cq->ib_cq.cqe = entries; 2661 cq->cq_period = cq->qplib_cq.period; 2662 nq->budget++; 2663 2664 atomic_inc(&rdev->cq_count); 2665 2666 if (context) { 2667 struct bnxt_re_cq_resp resp; 2668 2669 resp.cqid = cq->qplib_cq.id; 2670 resp.tail = cq->qplib_cq.hwq.cons; 2671 resp.phase = cq->qplib_cq.period; 2672 resp.rsvd = 0; 2673 rc = ib_copy_to_udata(udata, &resp, sizeof(resp)); 2674 if (rc) { 2675 dev_err(rdev_to_dev(rdev), "Failed to copy CQ udata"); 2676 bnxt_qplib_destroy_cq(&rdev->qplib_res, &cq->qplib_cq); 2677 goto c2fail; 2678 } 2679 } 2680 2681 return &cq->ib_cq; 2682 2683 c2fail: 2684 if (context) 2685 ib_umem_release(cq->umem); 2686 fail: 2687 kfree(cq->cql); 2688 kfree(cq); 2689 return ERR_PTR(rc); 2690 } 2691 2692 static u8 __req_to_ib_wc_status(u8 qstatus) 2693 { 2694 switch (qstatus) { 2695 case CQ_REQ_STATUS_OK: 2696 return IB_WC_SUCCESS; 2697 case CQ_REQ_STATUS_BAD_RESPONSE_ERR: 2698 return IB_WC_BAD_RESP_ERR; 2699 case CQ_REQ_STATUS_LOCAL_LENGTH_ERR: 2700 return IB_WC_LOC_LEN_ERR; 2701 case CQ_REQ_STATUS_LOCAL_QP_OPERATION_ERR: 2702 return IB_WC_LOC_QP_OP_ERR; 2703 case CQ_REQ_STATUS_LOCAL_PROTECTION_ERR: 2704 return IB_WC_LOC_PROT_ERR; 2705 case CQ_REQ_STATUS_MEMORY_MGT_OPERATION_ERR: 2706 return IB_WC_GENERAL_ERR; 2707 case CQ_REQ_STATUS_REMOTE_INVALID_REQUEST_ERR: 2708 return IB_WC_REM_INV_REQ_ERR; 2709 case CQ_REQ_STATUS_REMOTE_ACCESS_ERR: 2710 return IB_WC_REM_ACCESS_ERR; 2711 case CQ_REQ_STATUS_REMOTE_OPERATION_ERR: 2712 return IB_WC_REM_OP_ERR; 2713 case CQ_REQ_STATUS_RNR_NAK_RETRY_CNT_ERR: 2714 return IB_WC_RNR_RETRY_EXC_ERR; 2715 case CQ_REQ_STATUS_TRANSPORT_RETRY_CNT_ERR: 2716 return IB_WC_RETRY_EXC_ERR; 2717 case CQ_REQ_STATUS_WORK_REQUEST_FLUSHED_ERR: 2718 return IB_WC_WR_FLUSH_ERR; 2719 default: 2720 return IB_WC_GENERAL_ERR; 2721 } 2722 return 0; 2723 } 2724 2725 static u8 __rawqp1_to_ib_wc_status(u8 qstatus) 2726 { 2727 switch (qstatus) { 2728 case CQ_RES_RAWETH_QP1_STATUS_OK: 2729 return IB_WC_SUCCESS; 2730 case CQ_RES_RAWETH_QP1_STATUS_LOCAL_ACCESS_ERROR: 2731 return IB_WC_LOC_ACCESS_ERR; 2732 case CQ_RES_RAWETH_QP1_STATUS_HW_LOCAL_LENGTH_ERR: 2733 return IB_WC_LOC_LEN_ERR; 2734 case CQ_RES_RAWETH_QP1_STATUS_LOCAL_PROTECTION_ERR: 2735 return IB_WC_LOC_PROT_ERR; 2736 case CQ_RES_RAWETH_QP1_STATUS_LOCAL_QP_OPERATION_ERR: 2737 return IB_WC_LOC_QP_OP_ERR; 2738 case CQ_RES_RAWETH_QP1_STATUS_MEMORY_MGT_OPERATION_ERR: 2739 return IB_WC_GENERAL_ERR; 2740 case CQ_RES_RAWETH_QP1_STATUS_WORK_REQUEST_FLUSHED_ERR: 2741 return IB_WC_WR_FLUSH_ERR; 2742 case CQ_RES_RAWETH_QP1_STATUS_HW_FLUSH_ERR: 2743 return IB_WC_WR_FLUSH_ERR; 2744 default: 2745 return IB_WC_GENERAL_ERR; 2746 } 2747 } 2748 2749 static u8 __rc_to_ib_wc_status(u8 qstatus) 2750 { 2751 switch (qstatus) { 2752 case CQ_RES_RC_STATUS_OK: 2753 return IB_WC_SUCCESS; 2754 case CQ_RES_RC_STATUS_LOCAL_ACCESS_ERROR: 2755 return IB_WC_LOC_ACCESS_ERR; 2756 case CQ_RES_RC_STATUS_LOCAL_LENGTH_ERR: 2757 return IB_WC_LOC_LEN_ERR; 2758 case CQ_RES_RC_STATUS_LOCAL_PROTECTION_ERR: 2759 return IB_WC_LOC_PROT_ERR; 2760 case CQ_RES_RC_STATUS_LOCAL_QP_OPERATION_ERR: 2761 return IB_WC_LOC_QP_OP_ERR; 2762 case CQ_RES_RC_STATUS_MEMORY_MGT_OPERATION_ERR: 2763 return IB_WC_GENERAL_ERR; 2764 case CQ_RES_RC_STATUS_REMOTE_INVALID_REQUEST_ERR: 2765 return IB_WC_REM_INV_REQ_ERR; 2766 case CQ_RES_RC_STATUS_WORK_REQUEST_FLUSHED_ERR: 2767 return IB_WC_WR_FLUSH_ERR; 2768 case CQ_RES_RC_STATUS_HW_FLUSH_ERR: 2769 return IB_WC_WR_FLUSH_ERR; 2770 default: 2771 return IB_WC_GENERAL_ERR; 2772 } 2773 } 2774 2775 static void bnxt_re_process_req_wc(struct ib_wc *wc, struct bnxt_qplib_cqe *cqe) 2776 { 2777 switch (cqe->type) { 2778 case BNXT_QPLIB_SWQE_TYPE_SEND: 2779 wc->opcode = IB_WC_SEND; 2780 break; 2781 case BNXT_QPLIB_SWQE_TYPE_SEND_WITH_IMM: 2782 wc->opcode = IB_WC_SEND; 2783 wc->wc_flags |= IB_WC_WITH_IMM; 2784 break; 2785 case BNXT_QPLIB_SWQE_TYPE_SEND_WITH_INV: 2786 wc->opcode = IB_WC_SEND; 2787 wc->wc_flags |= IB_WC_WITH_INVALIDATE; 2788 break; 2789 case BNXT_QPLIB_SWQE_TYPE_RDMA_WRITE: 2790 wc->opcode = IB_WC_RDMA_WRITE; 2791 break; 2792 case BNXT_QPLIB_SWQE_TYPE_RDMA_WRITE_WITH_IMM: 2793 wc->opcode = IB_WC_RDMA_WRITE; 2794 wc->wc_flags |= IB_WC_WITH_IMM; 2795 break; 2796 case BNXT_QPLIB_SWQE_TYPE_RDMA_READ: 2797 wc->opcode = IB_WC_RDMA_READ; 2798 break; 2799 case BNXT_QPLIB_SWQE_TYPE_ATOMIC_CMP_AND_SWP: 2800 wc->opcode = IB_WC_COMP_SWAP; 2801 break; 2802 case BNXT_QPLIB_SWQE_TYPE_ATOMIC_FETCH_AND_ADD: 2803 wc->opcode = IB_WC_FETCH_ADD; 2804 break; 2805 case BNXT_QPLIB_SWQE_TYPE_LOCAL_INV: 2806 wc->opcode = IB_WC_LOCAL_INV; 2807 break; 2808 case BNXT_QPLIB_SWQE_TYPE_REG_MR: 2809 wc->opcode = IB_WC_REG_MR; 2810 break; 2811 default: 2812 wc->opcode = IB_WC_SEND; 2813 break; 2814 } 2815 2816 wc->status = __req_to_ib_wc_status(cqe->status); 2817 } 2818 2819 static int bnxt_re_check_packet_type(u16 raweth_qp1_flags, 2820 u16 raweth_qp1_flags2) 2821 { 2822 bool is_ipv6 = false, is_ipv4 = false; 2823 2824 /* raweth_qp1_flags Bit 9-6 indicates itype */ 2825 if ((raweth_qp1_flags & CQ_RES_RAWETH_QP1_RAWETH_QP1_FLAGS_ITYPE_ROCE) 2826 != CQ_RES_RAWETH_QP1_RAWETH_QP1_FLAGS_ITYPE_ROCE) 2827 return -1; 2828 2829 if (raweth_qp1_flags2 & 2830 CQ_RES_RAWETH_QP1_RAWETH_QP1_FLAGS2_IP_CS_CALC && 2831 raweth_qp1_flags2 & 2832 CQ_RES_RAWETH_QP1_RAWETH_QP1_FLAGS2_L4_CS_CALC) { 2833 /* raweth_qp1_flags2 Bit 8 indicates ip_type. 0-v4 1 - v6 */ 2834 (raweth_qp1_flags2 & 2835 CQ_RES_RAWETH_QP1_RAWETH_QP1_FLAGS2_IP_TYPE) ? 2836 (is_ipv6 = true) : (is_ipv4 = true); 2837 return ((is_ipv6) ? 2838 BNXT_RE_ROCEV2_IPV6_PACKET : 2839 BNXT_RE_ROCEV2_IPV4_PACKET); 2840 } else { 2841 return BNXT_RE_ROCE_V1_PACKET; 2842 } 2843 } 2844 2845 static int bnxt_re_to_ib_nw_type(int nw_type) 2846 { 2847 u8 nw_hdr_type = 0xFF; 2848 2849 switch (nw_type) { 2850 case BNXT_RE_ROCE_V1_PACKET: 2851 nw_hdr_type = RDMA_NETWORK_ROCE_V1; 2852 break; 2853 case BNXT_RE_ROCEV2_IPV4_PACKET: 2854 nw_hdr_type = RDMA_NETWORK_IPV4; 2855 break; 2856 case BNXT_RE_ROCEV2_IPV6_PACKET: 2857 nw_hdr_type = RDMA_NETWORK_IPV6; 2858 break; 2859 } 2860 return nw_hdr_type; 2861 } 2862 2863 static bool bnxt_re_is_loopback_packet(struct bnxt_re_dev *rdev, 2864 void *rq_hdr_buf) 2865 { 2866 u8 *tmp_buf = NULL; 2867 struct ethhdr *eth_hdr; 2868 u16 eth_type; 2869 bool rc = false; 2870 2871 tmp_buf = (u8 *)rq_hdr_buf; 2872 /* 2873 * If dest mac is not same as I/F mac, this could be a 2874 * loopback address or multicast address, check whether 2875 * it is a loopback packet 2876 */ 2877 if (!ether_addr_equal(tmp_buf, rdev->netdev->dev_addr)) { 2878 tmp_buf += 4; 2879 /* Check the ether type */ 2880 eth_hdr = (struct ethhdr *)tmp_buf; 2881 eth_type = ntohs(eth_hdr->h_proto); 2882 switch (eth_type) { 2883 case ETH_P_IBOE: 2884 rc = true; 2885 break; 2886 case ETH_P_IP: 2887 case ETH_P_IPV6: { 2888 u32 len; 2889 struct udphdr *udp_hdr; 2890 2891 len = (eth_type == ETH_P_IP ? sizeof(struct iphdr) : 2892 sizeof(struct ipv6hdr)); 2893 tmp_buf += sizeof(struct ethhdr) + len; 2894 udp_hdr = (struct udphdr *)tmp_buf; 2895 if (ntohs(udp_hdr->dest) == 2896 ROCE_V2_UDP_DPORT) 2897 rc = true; 2898 break; 2899 } 2900 default: 2901 break; 2902 } 2903 } 2904 2905 return rc; 2906 } 2907 2908 static int bnxt_re_process_raw_qp_pkt_rx(struct bnxt_re_qp *qp1_qp, 2909 struct bnxt_qplib_cqe *cqe) 2910 { 2911 struct bnxt_re_dev *rdev = qp1_qp->rdev; 2912 struct bnxt_re_sqp_entries *sqp_entry = NULL; 2913 struct bnxt_re_qp *qp = rdev->qp1_sqp; 2914 struct ib_send_wr *swr; 2915 struct ib_ud_wr udwr; 2916 struct ib_recv_wr rwr; 2917 int pkt_type = 0; 2918 u32 tbl_idx; 2919 void *rq_hdr_buf; 2920 dma_addr_t rq_hdr_buf_map; 2921 dma_addr_t shrq_hdr_buf_map; 2922 u32 offset = 0; 2923 u32 skip_bytes = 0; 2924 struct ib_sge s_sge[2]; 2925 struct ib_sge r_sge[2]; 2926 int rc; 2927 2928 memset(&udwr, 0, sizeof(udwr)); 2929 memset(&rwr, 0, sizeof(rwr)); 2930 memset(&s_sge, 0, sizeof(s_sge)); 2931 memset(&r_sge, 0, sizeof(r_sge)); 2932 2933 swr = &udwr.wr; 2934 tbl_idx = cqe->wr_id; 2935 2936 rq_hdr_buf = qp1_qp->qplib_qp.rq_hdr_buf + 2937 (tbl_idx * qp1_qp->qplib_qp.rq_hdr_buf_size); 2938 rq_hdr_buf_map = bnxt_qplib_get_qp_buf_from_index(&qp1_qp->qplib_qp, 2939 tbl_idx); 2940 2941 /* Shadow QP header buffer */ 2942 shrq_hdr_buf_map = bnxt_qplib_get_qp_buf_from_index(&qp->qplib_qp, 2943 tbl_idx); 2944 sqp_entry = &rdev->sqp_tbl[tbl_idx]; 2945 2946 /* Store this cqe */ 2947 memcpy(&sqp_entry->cqe, cqe, sizeof(struct bnxt_qplib_cqe)); 2948 sqp_entry->qp1_qp = qp1_qp; 2949 2950 /* Find packet type from the cqe */ 2951 2952 pkt_type = bnxt_re_check_packet_type(cqe->raweth_qp1_flags, 2953 cqe->raweth_qp1_flags2); 2954 if (pkt_type < 0) { 2955 dev_err(rdev_to_dev(rdev), "Invalid packet\n"); 2956 return -EINVAL; 2957 } 2958 2959 /* Adjust the offset for the user buffer and post in the rq */ 2960 2961 if (pkt_type == BNXT_RE_ROCEV2_IPV4_PACKET) 2962 offset = 20; 2963 2964 /* 2965 * QP1 loopback packet has 4 bytes of internal header before 2966 * ether header. Skip these four bytes. 2967 */ 2968 if (bnxt_re_is_loopback_packet(rdev, rq_hdr_buf)) 2969 skip_bytes = 4; 2970 2971 /* First send SGE . Skip the ether header*/ 2972 s_sge[0].addr = rq_hdr_buf_map + BNXT_QPLIB_MAX_QP1_RQ_ETH_HDR_SIZE 2973 + skip_bytes; 2974 s_sge[0].lkey = 0xFFFFFFFF; 2975 s_sge[0].length = offset ? BNXT_QPLIB_MAX_GRH_HDR_SIZE_IPV4 : 2976 BNXT_QPLIB_MAX_GRH_HDR_SIZE_IPV6; 2977 2978 /* Second Send SGE */ 2979 s_sge[1].addr = s_sge[0].addr + s_sge[0].length + 2980 BNXT_QPLIB_MAX_QP1_RQ_BDETH_HDR_SIZE; 2981 if (pkt_type != BNXT_RE_ROCE_V1_PACKET) 2982 s_sge[1].addr += 8; 2983 s_sge[1].lkey = 0xFFFFFFFF; 2984 s_sge[1].length = 256; 2985 2986 /* First recv SGE */ 2987 2988 r_sge[0].addr = shrq_hdr_buf_map; 2989 r_sge[0].lkey = 0xFFFFFFFF; 2990 r_sge[0].length = 40; 2991 2992 r_sge[1].addr = sqp_entry->sge.addr + offset; 2993 r_sge[1].lkey = sqp_entry->sge.lkey; 2994 r_sge[1].length = BNXT_QPLIB_MAX_GRH_HDR_SIZE_IPV6 + 256 - offset; 2995 2996 /* Create receive work request */ 2997 rwr.num_sge = 2; 2998 rwr.sg_list = r_sge; 2999 rwr.wr_id = tbl_idx; 3000 rwr.next = NULL; 3001 3002 rc = bnxt_re_post_recv_shadow_qp(rdev, qp, &rwr); 3003 if (rc) { 3004 dev_err(rdev_to_dev(rdev), 3005 "Failed to post Rx buffers to shadow QP"); 3006 return -ENOMEM; 3007 } 3008 3009 swr->num_sge = 2; 3010 swr->sg_list = s_sge; 3011 swr->wr_id = tbl_idx; 3012 swr->opcode = IB_WR_SEND; 3013 swr->next = NULL; 3014 3015 udwr.ah = &rdev->sqp_ah->ib_ah; 3016 udwr.remote_qpn = rdev->qp1_sqp->qplib_qp.id; 3017 udwr.remote_qkey = rdev->qp1_sqp->qplib_qp.qkey; 3018 3019 /* post data received in the send queue */ 3020 rc = bnxt_re_post_send_shadow_qp(rdev, qp, swr); 3021 3022 return 0; 3023 } 3024 3025 static void bnxt_re_process_res_rawqp1_wc(struct ib_wc *wc, 3026 struct bnxt_qplib_cqe *cqe) 3027 { 3028 wc->opcode = IB_WC_RECV; 3029 wc->status = __rawqp1_to_ib_wc_status(cqe->status); 3030 wc->wc_flags |= IB_WC_GRH; 3031 } 3032 3033 static bool bnxt_re_is_vlan_pkt(struct bnxt_qplib_cqe *orig_cqe, 3034 u16 *vid, u8 *sl) 3035 { 3036 bool ret = false; 3037 u32 metadata; 3038 u16 tpid; 3039 3040 metadata = orig_cqe->raweth_qp1_metadata; 3041 if (orig_cqe->raweth_qp1_flags2 & 3042 CQ_RES_RAWETH_QP1_RAWETH_QP1_FLAGS2_META_FORMAT_VLAN) { 3043 tpid = ((metadata & 3044 CQ_RES_RAWETH_QP1_RAWETH_QP1_METADATA_TPID_MASK) >> 3045 CQ_RES_RAWETH_QP1_RAWETH_QP1_METADATA_TPID_SFT); 3046 if (tpid == ETH_P_8021Q) { 3047 *vid = metadata & 3048 CQ_RES_RAWETH_QP1_RAWETH_QP1_METADATA_VID_MASK; 3049 *sl = (metadata & 3050 CQ_RES_RAWETH_QP1_RAWETH_QP1_METADATA_PRI_MASK) >> 3051 CQ_RES_RAWETH_QP1_RAWETH_QP1_METADATA_PRI_SFT; 3052 ret = true; 3053 } 3054 } 3055 3056 return ret; 3057 } 3058 3059 static void bnxt_re_process_res_rc_wc(struct ib_wc *wc, 3060 struct bnxt_qplib_cqe *cqe) 3061 { 3062 wc->opcode = IB_WC_RECV; 3063 wc->status = __rc_to_ib_wc_status(cqe->status); 3064 3065 if (cqe->flags & CQ_RES_RC_FLAGS_IMM) 3066 wc->wc_flags |= IB_WC_WITH_IMM; 3067 if (cqe->flags & CQ_RES_RC_FLAGS_INV) 3068 wc->wc_flags |= IB_WC_WITH_INVALIDATE; 3069 if ((cqe->flags & (CQ_RES_RC_FLAGS_RDMA | CQ_RES_RC_FLAGS_IMM)) == 3070 (CQ_RES_RC_FLAGS_RDMA | CQ_RES_RC_FLAGS_IMM)) 3071 wc->opcode = IB_WC_RECV_RDMA_WITH_IMM; 3072 } 3073 3074 static void bnxt_re_process_res_shadow_qp_wc(struct bnxt_re_qp *qp, 3075 struct ib_wc *wc, 3076 struct bnxt_qplib_cqe *cqe) 3077 { 3078 struct bnxt_re_dev *rdev = qp->rdev; 3079 struct bnxt_re_qp *qp1_qp = NULL; 3080 struct bnxt_qplib_cqe *orig_cqe = NULL; 3081 struct bnxt_re_sqp_entries *sqp_entry = NULL; 3082 int nw_type; 3083 u32 tbl_idx; 3084 u16 vlan_id; 3085 u8 sl; 3086 3087 tbl_idx = cqe->wr_id; 3088 3089 sqp_entry = &rdev->sqp_tbl[tbl_idx]; 3090 qp1_qp = sqp_entry->qp1_qp; 3091 orig_cqe = &sqp_entry->cqe; 3092 3093 wc->wr_id = sqp_entry->wrid; 3094 wc->byte_len = orig_cqe->length; 3095 wc->qp = &qp1_qp->ib_qp; 3096 3097 wc->ex.imm_data = orig_cqe->immdata; 3098 wc->src_qp = orig_cqe->src_qp; 3099 memcpy(wc->smac, orig_cqe->smac, ETH_ALEN); 3100 if (bnxt_re_is_vlan_pkt(orig_cqe, &vlan_id, &sl)) { 3101 wc->vlan_id = vlan_id; 3102 wc->sl = sl; 3103 wc->wc_flags |= IB_WC_WITH_VLAN; 3104 } 3105 wc->port_num = 1; 3106 wc->vendor_err = orig_cqe->status; 3107 3108 wc->opcode = IB_WC_RECV; 3109 wc->status = __rawqp1_to_ib_wc_status(orig_cqe->status); 3110 wc->wc_flags |= IB_WC_GRH; 3111 3112 nw_type = bnxt_re_check_packet_type(orig_cqe->raweth_qp1_flags, 3113 orig_cqe->raweth_qp1_flags2); 3114 if (nw_type >= 0) { 3115 wc->network_hdr_type = bnxt_re_to_ib_nw_type(nw_type); 3116 wc->wc_flags |= IB_WC_WITH_NETWORK_HDR_TYPE; 3117 } 3118 } 3119 3120 static void bnxt_re_process_res_ud_wc(struct ib_wc *wc, 3121 struct bnxt_qplib_cqe *cqe) 3122 { 3123 wc->opcode = IB_WC_RECV; 3124 wc->status = __rc_to_ib_wc_status(cqe->status); 3125 3126 if (cqe->flags & CQ_RES_RC_FLAGS_IMM) 3127 wc->wc_flags |= IB_WC_WITH_IMM; 3128 if (cqe->flags & CQ_RES_RC_FLAGS_INV) 3129 wc->wc_flags |= IB_WC_WITH_INVALIDATE; 3130 if ((cqe->flags & (CQ_RES_RC_FLAGS_RDMA | CQ_RES_RC_FLAGS_IMM)) == 3131 (CQ_RES_RC_FLAGS_RDMA | CQ_RES_RC_FLAGS_IMM)) 3132 wc->opcode = IB_WC_RECV_RDMA_WITH_IMM; 3133 } 3134 3135 static int send_phantom_wqe(struct bnxt_re_qp *qp) 3136 { 3137 struct bnxt_qplib_qp *lib_qp = &qp->qplib_qp; 3138 unsigned long flags; 3139 int rc = 0; 3140 3141 spin_lock_irqsave(&qp->sq_lock, flags); 3142 3143 rc = bnxt_re_bind_fence_mw(lib_qp); 3144 if (!rc) { 3145 lib_qp->sq.phantom_wqe_cnt++; 3146 dev_dbg(&lib_qp->sq.hwq.pdev->dev, 3147 "qp %#x sq->prod %#x sw_prod %#x phantom_wqe_cnt %d\n", 3148 lib_qp->id, lib_qp->sq.hwq.prod, 3149 HWQ_CMP(lib_qp->sq.hwq.prod, &lib_qp->sq.hwq), 3150 lib_qp->sq.phantom_wqe_cnt); 3151 } 3152 3153 spin_unlock_irqrestore(&qp->sq_lock, flags); 3154 return rc; 3155 } 3156 3157 int bnxt_re_poll_cq(struct ib_cq *ib_cq, int num_entries, struct ib_wc *wc) 3158 { 3159 struct bnxt_re_cq *cq = container_of(ib_cq, struct bnxt_re_cq, ib_cq); 3160 struct bnxt_re_qp *qp; 3161 struct bnxt_qplib_cqe *cqe; 3162 int i, ncqe, budget; 3163 struct bnxt_qplib_q *sq; 3164 struct bnxt_qplib_qp *lib_qp; 3165 u32 tbl_idx; 3166 struct bnxt_re_sqp_entries *sqp_entry = NULL; 3167 unsigned long flags; 3168 3169 spin_lock_irqsave(&cq->cq_lock, flags); 3170 budget = min_t(u32, num_entries, cq->max_cql); 3171 num_entries = budget; 3172 if (!cq->cql) { 3173 dev_err(rdev_to_dev(cq->rdev), "POLL CQ : no CQL to use"); 3174 goto exit; 3175 } 3176 cqe = &cq->cql[0]; 3177 while (budget) { 3178 lib_qp = NULL; 3179 ncqe = bnxt_qplib_poll_cq(&cq->qplib_cq, cqe, budget, &lib_qp); 3180 if (lib_qp) { 3181 sq = &lib_qp->sq; 3182 if (sq->send_phantom) { 3183 qp = container_of(lib_qp, 3184 struct bnxt_re_qp, qplib_qp); 3185 if (send_phantom_wqe(qp) == -ENOMEM) 3186 dev_err(rdev_to_dev(cq->rdev), 3187 "Phantom failed! Scheduled to send again\n"); 3188 else 3189 sq->send_phantom = false; 3190 } 3191 } 3192 if (ncqe < budget) 3193 ncqe += bnxt_qplib_process_flush_list(&cq->qplib_cq, 3194 cqe + ncqe, 3195 budget - ncqe); 3196 3197 if (!ncqe) 3198 break; 3199 3200 for (i = 0; i < ncqe; i++, cqe++) { 3201 /* Transcribe each qplib_wqe back to ib_wc */ 3202 memset(wc, 0, sizeof(*wc)); 3203 3204 wc->wr_id = cqe->wr_id; 3205 wc->byte_len = cqe->length; 3206 qp = container_of 3207 ((struct bnxt_qplib_qp *) 3208 (unsigned long)(cqe->qp_handle), 3209 struct bnxt_re_qp, qplib_qp); 3210 if (!qp) { 3211 dev_err(rdev_to_dev(cq->rdev), 3212 "POLL CQ : bad QP handle"); 3213 continue; 3214 } 3215 wc->qp = &qp->ib_qp; 3216 wc->ex.imm_data = cqe->immdata; 3217 wc->src_qp = cqe->src_qp; 3218 memcpy(wc->smac, cqe->smac, ETH_ALEN); 3219 wc->port_num = 1; 3220 wc->vendor_err = cqe->status; 3221 3222 switch (cqe->opcode) { 3223 case CQ_BASE_CQE_TYPE_REQ: 3224 if (qp->qplib_qp.id == 3225 qp->rdev->qp1_sqp->qplib_qp.id) { 3226 /* Handle this completion with 3227 * the stored completion 3228 */ 3229 memset(wc, 0, sizeof(*wc)); 3230 continue; 3231 } 3232 bnxt_re_process_req_wc(wc, cqe); 3233 break; 3234 case CQ_BASE_CQE_TYPE_RES_RAWETH_QP1: 3235 if (!cqe->status) { 3236 int rc = 0; 3237 3238 rc = bnxt_re_process_raw_qp_pkt_rx 3239 (qp, cqe); 3240 if (!rc) { 3241 memset(wc, 0, sizeof(*wc)); 3242 continue; 3243 } 3244 cqe->status = -1; 3245 } 3246 /* Errors need not be looped back. 3247 * But change the wr_id to the one 3248 * stored in the table 3249 */ 3250 tbl_idx = cqe->wr_id; 3251 sqp_entry = &cq->rdev->sqp_tbl[tbl_idx]; 3252 wc->wr_id = sqp_entry->wrid; 3253 bnxt_re_process_res_rawqp1_wc(wc, cqe); 3254 break; 3255 case CQ_BASE_CQE_TYPE_RES_RC: 3256 bnxt_re_process_res_rc_wc(wc, cqe); 3257 break; 3258 case CQ_BASE_CQE_TYPE_RES_UD: 3259 if (qp->qplib_qp.id == 3260 qp->rdev->qp1_sqp->qplib_qp.id) { 3261 /* Handle this completion with 3262 * the stored completion 3263 */ 3264 if (cqe->status) { 3265 continue; 3266 } else { 3267 bnxt_re_process_res_shadow_qp_wc 3268 (qp, wc, cqe); 3269 break; 3270 } 3271 } 3272 bnxt_re_process_res_ud_wc(wc, cqe); 3273 break; 3274 default: 3275 dev_err(rdev_to_dev(cq->rdev), 3276 "POLL CQ : type 0x%x not handled", 3277 cqe->opcode); 3278 continue; 3279 } 3280 wc++; 3281 budget--; 3282 } 3283 } 3284 exit: 3285 spin_unlock_irqrestore(&cq->cq_lock, flags); 3286 return num_entries - budget; 3287 } 3288 3289 int bnxt_re_req_notify_cq(struct ib_cq *ib_cq, 3290 enum ib_cq_notify_flags ib_cqn_flags) 3291 { 3292 struct bnxt_re_cq *cq = container_of(ib_cq, struct bnxt_re_cq, ib_cq); 3293 int type = 0, rc = 0; 3294 unsigned long flags; 3295 3296 spin_lock_irqsave(&cq->cq_lock, flags); 3297 /* Trigger on the very next completion */ 3298 if (ib_cqn_flags & IB_CQ_NEXT_COMP) 3299 type = DBR_DBR_TYPE_CQ_ARMALL; 3300 /* Trigger on the next solicited completion */ 3301 else if (ib_cqn_flags & IB_CQ_SOLICITED) 3302 type = DBR_DBR_TYPE_CQ_ARMSE; 3303 3304 /* Poll to see if there are missed events */ 3305 if ((ib_cqn_flags & IB_CQ_REPORT_MISSED_EVENTS) && 3306 !(bnxt_qplib_is_cq_empty(&cq->qplib_cq))) { 3307 rc = 1; 3308 goto exit; 3309 } 3310 bnxt_qplib_req_notify_cq(&cq->qplib_cq, type); 3311 3312 exit: 3313 spin_unlock_irqrestore(&cq->cq_lock, flags); 3314 return rc; 3315 } 3316 3317 /* Memory Regions */ 3318 struct ib_mr *bnxt_re_get_dma_mr(struct ib_pd *ib_pd, int mr_access_flags) 3319 { 3320 struct bnxt_re_pd *pd = container_of(ib_pd, struct bnxt_re_pd, ib_pd); 3321 struct bnxt_re_dev *rdev = pd->rdev; 3322 struct bnxt_re_mr *mr; 3323 u64 pbl = 0; 3324 int rc; 3325 3326 mr = kzalloc(sizeof(*mr), GFP_KERNEL); 3327 if (!mr) 3328 return ERR_PTR(-ENOMEM); 3329 3330 mr->rdev = rdev; 3331 mr->qplib_mr.pd = &pd->qplib_pd; 3332 mr->qplib_mr.flags = __from_ib_access_flags(mr_access_flags); 3333 mr->qplib_mr.type = CMDQ_ALLOCATE_MRW_MRW_FLAGS_PMR; 3334 3335 /* Allocate and register 0 as the address */ 3336 rc = bnxt_qplib_alloc_mrw(&rdev->qplib_res, &mr->qplib_mr); 3337 if (rc) 3338 goto fail; 3339 3340 mr->qplib_mr.hwq.level = PBL_LVL_MAX; 3341 mr->qplib_mr.total_size = -1; /* Infinte length */ 3342 rc = bnxt_qplib_reg_mr(&rdev->qplib_res, &mr->qplib_mr, &pbl, 0, false, 3343 PAGE_SIZE); 3344 if (rc) 3345 goto fail_mr; 3346 3347 mr->ib_mr.lkey = mr->qplib_mr.lkey; 3348 if (mr_access_flags & (IB_ACCESS_REMOTE_WRITE | IB_ACCESS_REMOTE_READ | 3349 IB_ACCESS_REMOTE_ATOMIC)) 3350 mr->ib_mr.rkey = mr->ib_mr.lkey; 3351 atomic_inc(&rdev->mr_count); 3352 3353 return &mr->ib_mr; 3354 3355 fail_mr: 3356 bnxt_qplib_free_mrw(&rdev->qplib_res, &mr->qplib_mr); 3357 fail: 3358 kfree(mr); 3359 return ERR_PTR(rc); 3360 } 3361 3362 int bnxt_re_dereg_mr(struct ib_mr *ib_mr) 3363 { 3364 struct bnxt_re_mr *mr = container_of(ib_mr, struct bnxt_re_mr, ib_mr); 3365 struct bnxt_re_dev *rdev = mr->rdev; 3366 int rc; 3367 3368 rc = bnxt_qplib_free_mrw(&rdev->qplib_res, &mr->qplib_mr); 3369 if (rc) 3370 dev_err(rdev_to_dev(rdev), "Dereg MR failed: %#x\n", rc); 3371 3372 if (mr->pages) { 3373 rc = bnxt_qplib_free_fast_reg_page_list(&rdev->qplib_res, 3374 &mr->qplib_frpl); 3375 kfree(mr->pages); 3376 mr->npages = 0; 3377 mr->pages = NULL; 3378 } 3379 if (!IS_ERR_OR_NULL(mr->ib_umem)) 3380 ib_umem_release(mr->ib_umem); 3381 3382 kfree(mr); 3383 atomic_dec(&rdev->mr_count); 3384 return rc; 3385 } 3386 3387 static int bnxt_re_set_page(struct ib_mr *ib_mr, u64 addr) 3388 { 3389 struct bnxt_re_mr *mr = container_of(ib_mr, struct bnxt_re_mr, ib_mr); 3390 3391 if (unlikely(mr->npages == mr->qplib_frpl.max_pg_ptrs)) 3392 return -ENOMEM; 3393 3394 mr->pages[mr->npages++] = addr; 3395 return 0; 3396 } 3397 3398 int bnxt_re_map_mr_sg(struct ib_mr *ib_mr, struct scatterlist *sg, int sg_nents, 3399 unsigned int *sg_offset) 3400 { 3401 struct bnxt_re_mr *mr = container_of(ib_mr, struct bnxt_re_mr, ib_mr); 3402 3403 mr->npages = 0; 3404 return ib_sg_to_pages(ib_mr, sg, sg_nents, sg_offset, bnxt_re_set_page); 3405 } 3406 3407 struct ib_mr *bnxt_re_alloc_mr(struct ib_pd *ib_pd, enum ib_mr_type type, 3408 u32 max_num_sg) 3409 { 3410 struct bnxt_re_pd *pd = container_of(ib_pd, struct bnxt_re_pd, ib_pd); 3411 struct bnxt_re_dev *rdev = pd->rdev; 3412 struct bnxt_re_mr *mr = NULL; 3413 int rc; 3414 3415 if (type != IB_MR_TYPE_MEM_REG) { 3416 dev_dbg(rdev_to_dev(rdev), "MR type 0x%x not supported", type); 3417 return ERR_PTR(-EINVAL); 3418 } 3419 if (max_num_sg > MAX_PBL_LVL_1_PGS) 3420 return ERR_PTR(-EINVAL); 3421 3422 mr = kzalloc(sizeof(*mr), GFP_KERNEL); 3423 if (!mr) 3424 return ERR_PTR(-ENOMEM); 3425 3426 mr->rdev = rdev; 3427 mr->qplib_mr.pd = &pd->qplib_pd; 3428 mr->qplib_mr.flags = BNXT_QPLIB_FR_PMR; 3429 mr->qplib_mr.type = CMDQ_ALLOCATE_MRW_MRW_FLAGS_PMR; 3430 3431 rc = bnxt_qplib_alloc_mrw(&rdev->qplib_res, &mr->qplib_mr); 3432 if (rc) 3433 goto bail; 3434 3435 mr->ib_mr.lkey = mr->qplib_mr.lkey; 3436 mr->ib_mr.rkey = mr->ib_mr.lkey; 3437 3438 mr->pages = kcalloc(max_num_sg, sizeof(u64), GFP_KERNEL); 3439 if (!mr->pages) { 3440 rc = -ENOMEM; 3441 goto fail; 3442 } 3443 rc = bnxt_qplib_alloc_fast_reg_page_list(&rdev->qplib_res, 3444 &mr->qplib_frpl, max_num_sg); 3445 if (rc) { 3446 dev_err(rdev_to_dev(rdev), 3447 "Failed to allocate HW FR page list"); 3448 goto fail_mr; 3449 } 3450 3451 atomic_inc(&rdev->mr_count); 3452 return &mr->ib_mr; 3453 3454 fail_mr: 3455 kfree(mr->pages); 3456 fail: 3457 bnxt_qplib_free_mrw(&rdev->qplib_res, &mr->qplib_mr); 3458 bail: 3459 kfree(mr); 3460 return ERR_PTR(rc); 3461 } 3462 3463 struct ib_mw *bnxt_re_alloc_mw(struct ib_pd *ib_pd, enum ib_mw_type type, 3464 struct ib_udata *udata) 3465 { 3466 struct bnxt_re_pd *pd = container_of(ib_pd, struct bnxt_re_pd, ib_pd); 3467 struct bnxt_re_dev *rdev = pd->rdev; 3468 struct bnxt_re_mw *mw; 3469 int rc; 3470 3471 mw = kzalloc(sizeof(*mw), GFP_KERNEL); 3472 if (!mw) 3473 return ERR_PTR(-ENOMEM); 3474 mw->rdev = rdev; 3475 mw->qplib_mw.pd = &pd->qplib_pd; 3476 3477 mw->qplib_mw.type = (type == IB_MW_TYPE_1 ? 3478 CMDQ_ALLOCATE_MRW_MRW_FLAGS_MW_TYPE1 : 3479 CMDQ_ALLOCATE_MRW_MRW_FLAGS_MW_TYPE2B); 3480 rc = bnxt_qplib_alloc_mrw(&rdev->qplib_res, &mw->qplib_mw); 3481 if (rc) { 3482 dev_err(rdev_to_dev(rdev), "Allocate MW failed!"); 3483 goto fail; 3484 } 3485 mw->ib_mw.rkey = mw->qplib_mw.rkey; 3486 3487 atomic_inc(&rdev->mw_count); 3488 return &mw->ib_mw; 3489 3490 fail: 3491 kfree(mw); 3492 return ERR_PTR(rc); 3493 } 3494 3495 int bnxt_re_dealloc_mw(struct ib_mw *ib_mw) 3496 { 3497 struct bnxt_re_mw *mw = container_of(ib_mw, struct bnxt_re_mw, ib_mw); 3498 struct bnxt_re_dev *rdev = mw->rdev; 3499 int rc; 3500 3501 rc = bnxt_qplib_free_mrw(&rdev->qplib_res, &mw->qplib_mw); 3502 if (rc) { 3503 dev_err(rdev_to_dev(rdev), "Free MW failed: %#x\n", rc); 3504 return rc; 3505 } 3506 3507 kfree(mw); 3508 atomic_dec(&rdev->mw_count); 3509 return rc; 3510 } 3511 3512 static int bnxt_re_page_size_ok(int page_shift) 3513 { 3514 switch (page_shift) { 3515 case CMDQ_REGISTER_MR_LOG2_PBL_PG_SIZE_PG_4K: 3516 case CMDQ_REGISTER_MR_LOG2_PBL_PG_SIZE_PG_8K: 3517 case CMDQ_REGISTER_MR_LOG2_PBL_PG_SIZE_PG_64K: 3518 case CMDQ_REGISTER_MR_LOG2_PBL_PG_SIZE_PG_2M: 3519 case CMDQ_REGISTER_MR_LOG2_PBL_PG_SIZE_PG_256K: 3520 case CMDQ_REGISTER_MR_LOG2_PBL_PG_SIZE_PG_1M: 3521 case CMDQ_REGISTER_MR_LOG2_PBL_PG_SIZE_PG_4M: 3522 case CMDQ_REGISTER_MR_LOG2_PBL_PG_SIZE_PG_1G: 3523 return 1; 3524 default: 3525 return 0; 3526 } 3527 } 3528 3529 static int fill_umem_pbl_tbl(struct ib_umem *umem, u64 *pbl_tbl_orig, 3530 int page_shift) 3531 { 3532 u64 *pbl_tbl = pbl_tbl_orig; 3533 u64 paddr; 3534 u64 page_mask = (1ULL << page_shift) - 1; 3535 int i, pages; 3536 struct scatterlist *sg; 3537 int entry; 3538 3539 for_each_sg(umem->sg_head.sgl, sg, umem->nmap, entry) { 3540 pages = sg_dma_len(sg) >> PAGE_SHIFT; 3541 for (i = 0; i < pages; i++) { 3542 paddr = sg_dma_address(sg) + (i << PAGE_SHIFT); 3543 if (pbl_tbl == pbl_tbl_orig) 3544 *pbl_tbl++ = paddr & ~page_mask; 3545 else if ((paddr & page_mask) == 0) 3546 *pbl_tbl++ = paddr; 3547 } 3548 } 3549 return pbl_tbl - pbl_tbl_orig; 3550 } 3551 3552 /* uverbs */ 3553 struct ib_mr *bnxt_re_reg_user_mr(struct ib_pd *ib_pd, u64 start, u64 length, 3554 u64 virt_addr, int mr_access_flags, 3555 struct ib_udata *udata) 3556 { 3557 struct bnxt_re_pd *pd = container_of(ib_pd, struct bnxt_re_pd, ib_pd); 3558 struct bnxt_re_dev *rdev = pd->rdev; 3559 struct bnxt_re_mr *mr; 3560 struct ib_umem *umem; 3561 u64 *pbl_tbl = NULL; 3562 int umem_pgs, page_shift, rc; 3563 3564 if (length > BNXT_RE_MAX_MR_SIZE) { 3565 dev_err(rdev_to_dev(rdev), "MR Size: %lld > Max supported:%lld\n", 3566 length, BNXT_RE_MAX_MR_SIZE); 3567 return ERR_PTR(-ENOMEM); 3568 } 3569 3570 mr = kzalloc(sizeof(*mr), GFP_KERNEL); 3571 if (!mr) 3572 return ERR_PTR(-ENOMEM); 3573 3574 mr->rdev = rdev; 3575 mr->qplib_mr.pd = &pd->qplib_pd; 3576 mr->qplib_mr.flags = __from_ib_access_flags(mr_access_flags); 3577 mr->qplib_mr.type = CMDQ_ALLOCATE_MRW_MRW_FLAGS_MR; 3578 3579 rc = bnxt_qplib_alloc_mrw(&rdev->qplib_res, &mr->qplib_mr); 3580 if (rc) { 3581 dev_err(rdev_to_dev(rdev), "Failed to allocate MR"); 3582 goto free_mr; 3583 } 3584 /* The fixed portion of the rkey is the same as the lkey */ 3585 mr->ib_mr.rkey = mr->qplib_mr.rkey; 3586 3587 umem = ib_umem_get(ib_pd->uobject->context, start, length, 3588 mr_access_flags, 0); 3589 if (IS_ERR(umem)) { 3590 dev_err(rdev_to_dev(rdev), "Failed to get umem"); 3591 rc = -EFAULT; 3592 goto free_mrw; 3593 } 3594 mr->ib_umem = umem; 3595 3596 mr->qplib_mr.va = virt_addr; 3597 umem_pgs = ib_umem_page_count(umem); 3598 if (!umem_pgs) { 3599 dev_err(rdev_to_dev(rdev), "umem is invalid!"); 3600 rc = -EINVAL; 3601 goto free_umem; 3602 } 3603 mr->qplib_mr.total_size = length; 3604 3605 pbl_tbl = kcalloc(umem_pgs, sizeof(u64 *), GFP_KERNEL); 3606 if (!pbl_tbl) { 3607 rc = -ENOMEM; 3608 goto free_umem; 3609 } 3610 3611 page_shift = umem->page_shift; 3612 3613 if (!bnxt_re_page_size_ok(page_shift)) { 3614 dev_err(rdev_to_dev(rdev), "umem page size unsupported!"); 3615 rc = -EFAULT; 3616 goto fail; 3617 } 3618 3619 if (!umem->hugetlb && length > BNXT_RE_MAX_MR_SIZE_LOW) { 3620 dev_err(rdev_to_dev(rdev), "Requested MR Sz:%llu Max sup:%llu", 3621 length, (u64)BNXT_RE_MAX_MR_SIZE_LOW); 3622 rc = -EINVAL; 3623 goto fail; 3624 } 3625 if (umem->hugetlb && length > BNXT_RE_PAGE_SIZE_2M) { 3626 page_shift = BNXT_RE_PAGE_SHIFT_2M; 3627 dev_warn(rdev_to_dev(rdev), "umem hugetlb set page_size %x", 3628 1 << page_shift); 3629 } 3630 3631 /* Map umem buf ptrs to the PBL */ 3632 umem_pgs = fill_umem_pbl_tbl(umem, pbl_tbl, page_shift); 3633 rc = bnxt_qplib_reg_mr(&rdev->qplib_res, &mr->qplib_mr, pbl_tbl, 3634 umem_pgs, false, 1 << page_shift); 3635 if (rc) { 3636 dev_err(rdev_to_dev(rdev), "Failed to register user MR"); 3637 goto fail; 3638 } 3639 3640 kfree(pbl_tbl); 3641 3642 mr->ib_mr.lkey = mr->qplib_mr.lkey; 3643 mr->ib_mr.rkey = mr->qplib_mr.lkey; 3644 atomic_inc(&rdev->mr_count); 3645 3646 return &mr->ib_mr; 3647 fail: 3648 kfree(pbl_tbl); 3649 free_umem: 3650 ib_umem_release(umem); 3651 free_mrw: 3652 bnxt_qplib_free_mrw(&rdev->qplib_res, &mr->qplib_mr); 3653 free_mr: 3654 kfree(mr); 3655 return ERR_PTR(rc); 3656 } 3657 3658 struct ib_ucontext *bnxt_re_alloc_ucontext(struct ib_device *ibdev, 3659 struct ib_udata *udata) 3660 { 3661 struct bnxt_re_dev *rdev = to_bnxt_re_dev(ibdev, ibdev); 3662 struct bnxt_re_uctx_resp resp; 3663 struct bnxt_re_ucontext *uctx; 3664 struct bnxt_qplib_dev_attr *dev_attr = &rdev->dev_attr; 3665 int rc; 3666 3667 dev_dbg(rdev_to_dev(rdev), "ABI version requested %d", 3668 ibdev->uverbs_abi_ver); 3669 3670 if (ibdev->uverbs_abi_ver != BNXT_RE_ABI_VERSION) { 3671 dev_dbg(rdev_to_dev(rdev), " is different from the device %d ", 3672 BNXT_RE_ABI_VERSION); 3673 return ERR_PTR(-EPERM); 3674 } 3675 3676 uctx = kzalloc(sizeof(*uctx), GFP_KERNEL); 3677 if (!uctx) 3678 return ERR_PTR(-ENOMEM); 3679 3680 uctx->rdev = rdev; 3681 3682 uctx->shpg = (void *)__get_free_page(GFP_KERNEL); 3683 if (!uctx->shpg) { 3684 rc = -ENOMEM; 3685 goto fail; 3686 } 3687 spin_lock_init(&uctx->sh_lock); 3688 3689 resp.dev_id = rdev->en_dev->pdev->devfn; /*Temp, Use idr_alloc instead*/ 3690 resp.max_qp = rdev->qplib_ctx.qpc_count; 3691 resp.pg_size = PAGE_SIZE; 3692 resp.cqe_sz = sizeof(struct cq_base); 3693 resp.max_cqd = dev_attr->max_cq_wqes; 3694 resp.rsvd = 0; 3695 3696 rc = ib_copy_to_udata(udata, &resp, sizeof(resp)); 3697 if (rc) { 3698 dev_err(rdev_to_dev(rdev), "Failed to copy user context"); 3699 rc = -EFAULT; 3700 goto cfail; 3701 } 3702 3703 return &uctx->ib_uctx; 3704 cfail: 3705 free_page((unsigned long)uctx->shpg); 3706 uctx->shpg = NULL; 3707 fail: 3708 kfree(uctx); 3709 return ERR_PTR(rc); 3710 } 3711 3712 int bnxt_re_dealloc_ucontext(struct ib_ucontext *ib_uctx) 3713 { 3714 struct bnxt_re_ucontext *uctx = container_of(ib_uctx, 3715 struct bnxt_re_ucontext, 3716 ib_uctx); 3717 3718 struct bnxt_re_dev *rdev = uctx->rdev; 3719 int rc = 0; 3720 3721 if (uctx->shpg) 3722 free_page((unsigned long)uctx->shpg); 3723 3724 if (uctx->dpi.dbr) { 3725 /* Free DPI only if this is the first PD allocated by the 3726 * application and mark the context dpi as NULL 3727 */ 3728 rc = bnxt_qplib_dealloc_dpi(&rdev->qplib_res, 3729 &rdev->qplib_res.dpi_tbl, 3730 &uctx->dpi); 3731 if (rc) 3732 dev_err(rdev_to_dev(rdev), "Deallocate HW DPI failed!"); 3733 /* Don't fail, continue*/ 3734 uctx->dpi.dbr = NULL; 3735 } 3736 3737 kfree(uctx); 3738 return 0; 3739 } 3740 3741 /* Helper function to mmap the virtual memory from user app */ 3742 int bnxt_re_mmap(struct ib_ucontext *ib_uctx, struct vm_area_struct *vma) 3743 { 3744 struct bnxt_re_ucontext *uctx = container_of(ib_uctx, 3745 struct bnxt_re_ucontext, 3746 ib_uctx); 3747 struct bnxt_re_dev *rdev = uctx->rdev; 3748 u64 pfn; 3749 3750 if (vma->vm_end - vma->vm_start != PAGE_SIZE) 3751 return -EINVAL; 3752 3753 if (vma->vm_pgoff) { 3754 vma->vm_page_prot = pgprot_noncached(vma->vm_page_prot); 3755 if (io_remap_pfn_range(vma, vma->vm_start, vma->vm_pgoff, 3756 PAGE_SIZE, vma->vm_page_prot)) { 3757 dev_err(rdev_to_dev(rdev), "Failed to map DPI"); 3758 return -EAGAIN; 3759 } 3760 } else { 3761 pfn = virt_to_phys(uctx->shpg) >> PAGE_SHIFT; 3762 if (remap_pfn_range(vma, vma->vm_start, 3763 pfn, PAGE_SIZE, vma->vm_page_prot)) { 3764 dev_err(rdev_to_dev(rdev), 3765 "Failed to map shared page"); 3766 return -EAGAIN; 3767 } 3768 } 3769 3770 return 0; 3771 } 3772