1 /*
2  * Broadcom NetXtreme-E RoCE driver.
3  *
4  * Copyright (c) 2016 - 2017, Broadcom. All rights reserved.  The term
5  * Broadcom refers to Broadcom Limited and/or its subsidiaries.
6  *
7  * This software is available to you under a choice of one of two
8  * licenses.  You may choose to be licensed under the terms of the GNU
9  * General Public License (GPL) Version 2, available from the file
10  * COPYING in the main directory of this source tree, or the
11  * BSD license below:
12  *
13  * Redistribution and use in source and binary forms, with or without
14  * modification, are permitted provided that the following conditions
15  * are met:
16  *
17  * 1. Redistributions of source code must retain the above copyright
18  *    notice, this list of conditions and the following disclaimer.
19  * 2. Redistributions in binary form must reproduce the above copyright
20  *    notice, this list of conditions and the following disclaimer in
21  *    the documentation and/or other materials provided with the
22  *    distribution.
23  *
24  * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS''
25  * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO,
26  * THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
27  * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS
28  * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
29  * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
30  * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR
31  * BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
32  * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE
33  * OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN
34  * IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
35  *
36  * Description: IB Verbs interpreter
37  */
38 
39 #include <linux/interrupt.h>
40 #include <linux/types.h>
41 #include <linux/pci.h>
42 #include <linux/netdevice.h>
43 #include <linux/if_ether.h>
44 
45 #include <rdma/ib_verbs.h>
46 #include <rdma/ib_user_verbs.h>
47 #include <rdma/ib_umem.h>
48 #include <rdma/ib_addr.h>
49 #include <rdma/ib_mad.h>
50 #include <rdma/ib_cache.h>
51 #include <rdma/uverbs_ioctl.h>
52 
53 #include "bnxt_ulp.h"
54 
55 #include "roce_hsi.h"
56 #include "qplib_res.h"
57 #include "qplib_sp.h"
58 #include "qplib_fp.h"
59 #include "qplib_rcfw.h"
60 
61 #include "bnxt_re.h"
62 #include "ib_verbs.h"
63 #include <rdma/bnxt_re-abi.h>
64 
65 static int __from_ib_access_flags(int iflags)
66 {
67 	int qflags = 0;
68 
69 	if (iflags & IB_ACCESS_LOCAL_WRITE)
70 		qflags |= BNXT_QPLIB_ACCESS_LOCAL_WRITE;
71 	if (iflags & IB_ACCESS_REMOTE_READ)
72 		qflags |= BNXT_QPLIB_ACCESS_REMOTE_READ;
73 	if (iflags & IB_ACCESS_REMOTE_WRITE)
74 		qflags |= BNXT_QPLIB_ACCESS_REMOTE_WRITE;
75 	if (iflags & IB_ACCESS_REMOTE_ATOMIC)
76 		qflags |= BNXT_QPLIB_ACCESS_REMOTE_ATOMIC;
77 	if (iflags & IB_ACCESS_MW_BIND)
78 		qflags |= BNXT_QPLIB_ACCESS_MW_BIND;
79 	if (iflags & IB_ZERO_BASED)
80 		qflags |= BNXT_QPLIB_ACCESS_ZERO_BASED;
81 	if (iflags & IB_ACCESS_ON_DEMAND)
82 		qflags |= BNXT_QPLIB_ACCESS_ON_DEMAND;
83 	return qflags;
84 };
85 
86 static enum ib_access_flags __to_ib_access_flags(int qflags)
87 {
88 	enum ib_access_flags iflags = 0;
89 
90 	if (qflags & BNXT_QPLIB_ACCESS_LOCAL_WRITE)
91 		iflags |= IB_ACCESS_LOCAL_WRITE;
92 	if (qflags & BNXT_QPLIB_ACCESS_REMOTE_WRITE)
93 		iflags |= IB_ACCESS_REMOTE_WRITE;
94 	if (qflags & BNXT_QPLIB_ACCESS_REMOTE_READ)
95 		iflags |= IB_ACCESS_REMOTE_READ;
96 	if (qflags & BNXT_QPLIB_ACCESS_REMOTE_ATOMIC)
97 		iflags |= IB_ACCESS_REMOTE_ATOMIC;
98 	if (qflags & BNXT_QPLIB_ACCESS_MW_BIND)
99 		iflags |= IB_ACCESS_MW_BIND;
100 	if (qflags & BNXT_QPLIB_ACCESS_ZERO_BASED)
101 		iflags |= IB_ZERO_BASED;
102 	if (qflags & BNXT_QPLIB_ACCESS_ON_DEMAND)
103 		iflags |= IB_ACCESS_ON_DEMAND;
104 	return iflags;
105 };
106 
107 static int bnxt_re_build_sgl(struct ib_sge *ib_sg_list,
108 			     struct bnxt_qplib_sge *sg_list, int num)
109 {
110 	int i, total = 0;
111 
112 	for (i = 0; i < num; i++) {
113 		sg_list[i].addr = ib_sg_list[i].addr;
114 		sg_list[i].lkey = ib_sg_list[i].lkey;
115 		sg_list[i].size = ib_sg_list[i].length;
116 		total += sg_list[i].size;
117 	}
118 	return total;
119 }
120 
121 /* Device */
122 int bnxt_re_query_device(struct ib_device *ibdev,
123 			 struct ib_device_attr *ib_attr,
124 			 struct ib_udata *udata)
125 {
126 	struct bnxt_re_dev *rdev = to_bnxt_re_dev(ibdev, ibdev);
127 	struct bnxt_qplib_dev_attr *dev_attr = &rdev->dev_attr;
128 
129 	memset(ib_attr, 0, sizeof(*ib_attr));
130 	memcpy(&ib_attr->fw_ver, dev_attr->fw_ver,
131 	       min(sizeof(dev_attr->fw_ver),
132 		   sizeof(ib_attr->fw_ver)));
133 	bnxt_qplib_get_guid(rdev->netdev->dev_addr,
134 			    (u8 *)&ib_attr->sys_image_guid);
135 	ib_attr->max_mr_size = BNXT_RE_MAX_MR_SIZE;
136 	ib_attr->page_size_cap = BNXT_RE_PAGE_SIZE_4K | BNXT_RE_PAGE_SIZE_2M;
137 
138 	ib_attr->vendor_id = rdev->en_dev->pdev->vendor;
139 	ib_attr->vendor_part_id = rdev->en_dev->pdev->device;
140 	ib_attr->hw_ver = rdev->en_dev->pdev->subsystem_device;
141 	ib_attr->max_qp = dev_attr->max_qp;
142 	ib_attr->max_qp_wr = dev_attr->max_qp_wqes;
143 	ib_attr->device_cap_flags =
144 				    IB_DEVICE_CURR_QP_STATE_MOD
145 				    | IB_DEVICE_RC_RNR_NAK_GEN
146 				    | IB_DEVICE_SHUTDOWN_PORT
147 				    | IB_DEVICE_SYS_IMAGE_GUID
148 				    | IB_DEVICE_LOCAL_DMA_LKEY
149 				    | IB_DEVICE_RESIZE_MAX_WR
150 				    | IB_DEVICE_PORT_ACTIVE_EVENT
151 				    | IB_DEVICE_N_NOTIFY_CQ
152 				    | IB_DEVICE_MEM_WINDOW
153 				    | IB_DEVICE_MEM_WINDOW_TYPE_2B
154 				    | IB_DEVICE_MEM_MGT_EXTENSIONS;
155 	ib_attr->max_send_sge = dev_attr->max_qp_sges;
156 	ib_attr->max_recv_sge = dev_attr->max_qp_sges;
157 	ib_attr->max_sge_rd = dev_attr->max_qp_sges;
158 	ib_attr->max_cq = dev_attr->max_cq;
159 	ib_attr->max_cqe = dev_attr->max_cq_wqes;
160 	ib_attr->max_mr = dev_attr->max_mr;
161 	ib_attr->max_pd = dev_attr->max_pd;
162 	ib_attr->max_qp_rd_atom = dev_attr->max_qp_rd_atom;
163 	ib_attr->max_qp_init_rd_atom = dev_attr->max_qp_init_rd_atom;
164 	ib_attr->atomic_cap = IB_ATOMIC_NONE;
165 	ib_attr->masked_atomic_cap = IB_ATOMIC_NONE;
166 
167 	ib_attr->max_ee_rd_atom = 0;
168 	ib_attr->max_res_rd_atom = 0;
169 	ib_attr->max_ee_init_rd_atom = 0;
170 	ib_attr->max_ee = 0;
171 	ib_attr->max_rdd = 0;
172 	ib_attr->max_mw = dev_attr->max_mw;
173 	ib_attr->max_raw_ipv6_qp = 0;
174 	ib_attr->max_raw_ethy_qp = dev_attr->max_raw_ethy_qp;
175 	ib_attr->max_mcast_grp = 0;
176 	ib_attr->max_mcast_qp_attach = 0;
177 	ib_attr->max_total_mcast_qp_attach = 0;
178 	ib_attr->max_ah = dev_attr->max_ah;
179 
180 	ib_attr->max_srq = dev_attr->max_srq;
181 	ib_attr->max_srq_wr = dev_attr->max_srq_wqes;
182 	ib_attr->max_srq_sge = dev_attr->max_srq_sges;
183 
184 	ib_attr->max_fast_reg_page_list_len = MAX_PBL_LVL_1_PGS;
185 
186 	ib_attr->max_pkeys = 1;
187 	ib_attr->local_ca_ack_delay = BNXT_RE_DEFAULT_ACK_DELAY;
188 	return 0;
189 }
190 
191 /* Port */
192 int bnxt_re_query_port(struct ib_device *ibdev, u8 port_num,
193 		       struct ib_port_attr *port_attr)
194 {
195 	struct bnxt_re_dev *rdev = to_bnxt_re_dev(ibdev, ibdev);
196 	struct bnxt_qplib_dev_attr *dev_attr = &rdev->dev_attr;
197 
198 	memset(port_attr, 0, sizeof(*port_attr));
199 
200 	if (netif_running(rdev->netdev) && netif_carrier_ok(rdev->netdev)) {
201 		port_attr->state = IB_PORT_ACTIVE;
202 		port_attr->phys_state = IB_PORT_PHYS_STATE_LINK_UP;
203 	} else {
204 		port_attr->state = IB_PORT_DOWN;
205 		port_attr->phys_state = IB_PORT_PHYS_STATE_DISABLED;
206 	}
207 	port_attr->max_mtu = IB_MTU_4096;
208 	port_attr->active_mtu = iboe_get_mtu(rdev->netdev->mtu);
209 	port_attr->gid_tbl_len = dev_attr->max_sgid;
210 	port_attr->port_cap_flags = IB_PORT_CM_SUP | IB_PORT_REINIT_SUP |
211 				    IB_PORT_DEVICE_MGMT_SUP |
212 				    IB_PORT_VENDOR_CLASS_SUP;
213 	port_attr->ip_gids = true;
214 
215 	port_attr->max_msg_sz = (u32)BNXT_RE_MAX_MR_SIZE_LOW;
216 	port_attr->bad_pkey_cntr = 0;
217 	port_attr->qkey_viol_cntr = 0;
218 	port_attr->pkey_tbl_len = dev_attr->max_pkey;
219 	port_attr->lid = 0;
220 	port_attr->sm_lid = 0;
221 	port_attr->lmc = 0;
222 	port_attr->max_vl_num = 4;
223 	port_attr->sm_sl = 0;
224 	port_attr->subnet_timeout = 0;
225 	port_attr->init_type_reply = 0;
226 	port_attr->active_speed = rdev->active_speed;
227 	port_attr->active_width = rdev->active_width;
228 
229 	return 0;
230 }
231 
232 int bnxt_re_get_port_immutable(struct ib_device *ibdev, u8 port_num,
233 			       struct ib_port_immutable *immutable)
234 {
235 	struct ib_port_attr port_attr;
236 
237 	if (bnxt_re_query_port(ibdev, port_num, &port_attr))
238 		return -EINVAL;
239 
240 	immutable->pkey_tbl_len = port_attr.pkey_tbl_len;
241 	immutable->gid_tbl_len = port_attr.gid_tbl_len;
242 	immutable->core_cap_flags = RDMA_CORE_PORT_IBA_ROCE;
243 	immutable->core_cap_flags |= RDMA_CORE_CAP_PROT_ROCE_UDP_ENCAP;
244 	immutable->max_mad_size = IB_MGMT_MAD_SIZE;
245 	return 0;
246 }
247 
248 void bnxt_re_query_fw_str(struct ib_device *ibdev, char *str)
249 {
250 	struct bnxt_re_dev *rdev = to_bnxt_re_dev(ibdev, ibdev);
251 
252 	snprintf(str, IB_FW_VERSION_NAME_MAX, "%d.%d.%d.%d",
253 		 rdev->dev_attr.fw_ver[0], rdev->dev_attr.fw_ver[1],
254 		 rdev->dev_attr.fw_ver[2], rdev->dev_attr.fw_ver[3]);
255 }
256 
257 int bnxt_re_query_pkey(struct ib_device *ibdev, u8 port_num,
258 		       u16 index, u16 *pkey)
259 {
260 	struct bnxt_re_dev *rdev = to_bnxt_re_dev(ibdev, ibdev);
261 
262 	/* Ignore port_num */
263 
264 	memset(pkey, 0, sizeof(*pkey));
265 	return bnxt_qplib_get_pkey(&rdev->qplib_res,
266 				   &rdev->qplib_res.pkey_tbl, index, pkey);
267 }
268 
269 int bnxt_re_query_gid(struct ib_device *ibdev, u8 port_num,
270 		      int index, union ib_gid *gid)
271 {
272 	struct bnxt_re_dev *rdev = to_bnxt_re_dev(ibdev, ibdev);
273 	int rc = 0;
274 
275 	/* Ignore port_num */
276 	memset(gid, 0, sizeof(*gid));
277 	rc = bnxt_qplib_get_sgid(&rdev->qplib_res,
278 				 &rdev->qplib_res.sgid_tbl, index,
279 				 (struct bnxt_qplib_gid *)gid);
280 	return rc;
281 }
282 
283 int bnxt_re_del_gid(const struct ib_gid_attr *attr, void **context)
284 {
285 	int rc = 0;
286 	struct bnxt_re_gid_ctx *ctx, **ctx_tbl;
287 	struct bnxt_re_dev *rdev = to_bnxt_re_dev(attr->device, ibdev);
288 	struct bnxt_qplib_sgid_tbl *sgid_tbl = &rdev->qplib_res.sgid_tbl;
289 	struct bnxt_qplib_gid *gid_to_del;
290 	u16 vlan_id = 0xFFFF;
291 
292 	/* Delete the entry from the hardware */
293 	ctx = *context;
294 	if (!ctx)
295 		return -EINVAL;
296 
297 	if (sgid_tbl && sgid_tbl->active) {
298 		if (ctx->idx >= sgid_tbl->max)
299 			return -EINVAL;
300 		gid_to_del = &sgid_tbl->tbl[ctx->idx].gid;
301 		vlan_id = sgid_tbl->tbl[ctx->idx].vlan_id;
302 		/* DEL_GID is called in WQ context(netdevice_event_work_handler)
303 		 * or via the ib_unregister_device path. In the former case QP1
304 		 * may not be destroyed yet, in which case just return as FW
305 		 * needs that entry to be present and will fail it's deletion.
306 		 * We could get invoked again after QP1 is destroyed OR get an
307 		 * ADD_GID call with a different GID value for the same index
308 		 * where we issue MODIFY_GID cmd to update the GID entry -- TBD
309 		 */
310 		if (ctx->idx == 0 &&
311 		    rdma_link_local_addr((struct in6_addr *)gid_to_del) &&
312 		    ctx->refcnt == 1 && rdev->gsi_ctx.gsi_sqp) {
313 			ibdev_dbg(&rdev->ibdev,
314 				  "Trying to delete GID0 while QP1 is alive\n");
315 			return -EFAULT;
316 		}
317 		ctx->refcnt--;
318 		if (!ctx->refcnt) {
319 			rc = bnxt_qplib_del_sgid(sgid_tbl, gid_to_del,
320 						 vlan_id,  true);
321 			if (rc) {
322 				ibdev_err(&rdev->ibdev,
323 					  "Failed to remove GID: %#x", rc);
324 			} else {
325 				ctx_tbl = sgid_tbl->ctx;
326 				ctx_tbl[ctx->idx] = NULL;
327 				kfree(ctx);
328 			}
329 		}
330 	} else {
331 		return -EINVAL;
332 	}
333 	return rc;
334 }
335 
336 int bnxt_re_add_gid(const struct ib_gid_attr *attr, void **context)
337 {
338 	int rc;
339 	u32 tbl_idx = 0;
340 	u16 vlan_id = 0xFFFF;
341 	struct bnxt_re_gid_ctx *ctx, **ctx_tbl;
342 	struct bnxt_re_dev *rdev = to_bnxt_re_dev(attr->device, ibdev);
343 	struct bnxt_qplib_sgid_tbl *sgid_tbl = &rdev->qplib_res.sgid_tbl;
344 
345 	rc = rdma_read_gid_l2_fields(attr, &vlan_id, NULL);
346 	if (rc)
347 		return rc;
348 
349 	rc = bnxt_qplib_add_sgid(sgid_tbl, (struct bnxt_qplib_gid *)&attr->gid,
350 				 rdev->qplib_res.netdev->dev_addr,
351 				 vlan_id, true, &tbl_idx);
352 	if (rc == -EALREADY) {
353 		ctx_tbl = sgid_tbl->ctx;
354 		ctx_tbl[tbl_idx]->refcnt++;
355 		*context = ctx_tbl[tbl_idx];
356 		return 0;
357 	}
358 
359 	if (rc < 0) {
360 		ibdev_err(&rdev->ibdev, "Failed to add GID: %#x", rc);
361 		return rc;
362 	}
363 
364 	ctx = kmalloc(sizeof(*ctx), GFP_KERNEL);
365 	if (!ctx)
366 		return -ENOMEM;
367 	ctx_tbl = sgid_tbl->ctx;
368 	ctx->idx = tbl_idx;
369 	ctx->refcnt = 1;
370 	ctx_tbl[tbl_idx] = ctx;
371 	*context = ctx;
372 
373 	return rc;
374 }
375 
376 enum rdma_link_layer bnxt_re_get_link_layer(struct ib_device *ibdev,
377 					    u8 port_num)
378 {
379 	return IB_LINK_LAYER_ETHERNET;
380 }
381 
382 #define	BNXT_RE_FENCE_PBL_SIZE	DIV_ROUND_UP(BNXT_RE_FENCE_BYTES, PAGE_SIZE)
383 
384 static void bnxt_re_create_fence_wqe(struct bnxt_re_pd *pd)
385 {
386 	struct bnxt_re_fence_data *fence = &pd->fence;
387 	struct ib_mr *ib_mr = &fence->mr->ib_mr;
388 	struct bnxt_qplib_swqe *wqe = &fence->bind_wqe;
389 
390 	memset(wqe, 0, sizeof(*wqe));
391 	wqe->type = BNXT_QPLIB_SWQE_TYPE_BIND_MW;
392 	wqe->wr_id = BNXT_QPLIB_FENCE_WRID;
393 	wqe->flags |= BNXT_QPLIB_SWQE_FLAGS_SIGNAL_COMP;
394 	wqe->flags |= BNXT_QPLIB_SWQE_FLAGS_UC_FENCE;
395 	wqe->bind.zero_based = false;
396 	wqe->bind.parent_l_key = ib_mr->lkey;
397 	wqe->bind.va = (u64)(unsigned long)fence->va;
398 	wqe->bind.length = fence->size;
399 	wqe->bind.access_cntl = __from_ib_access_flags(IB_ACCESS_REMOTE_READ);
400 	wqe->bind.mw_type = SQ_BIND_MW_TYPE_TYPE1;
401 
402 	/* Save the initial rkey in fence structure for now;
403 	 * wqe->bind.r_key will be set at (re)bind time.
404 	 */
405 	fence->bind_rkey = ib_inc_rkey(fence->mw->rkey);
406 }
407 
408 static int bnxt_re_bind_fence_mw(struct bnxt_qplib_qp *qplib_qp)
409 {
410 	struct bnxt_re_qp *qp = container_of(qplib_qp, struct bnxt_re_qp,
411 					     qplib_qp);
412 	struct ib_pd *ib_pd = qp->ib_qp.pd;
413 	struct bnxt_re_pd *pd = container_of(ib_pd, struct bnxt_re_pd, ib_pd);
414 	struct bnxt_re_fence_data *fence = &pd->fence;
415 	struct bnxt_qplib_swqe *fence_wqe = &fence->bind_wqe;
416 	struct bnxt_qplib_swqe wqe;
417 	int rc;
418 
419 	memcpy(&wqe, fence_wqe, sizeof(wqe));
420 	wqe.bind.r_key = fence->bind_rkey;
421 	fence->bind_rkey = ib_inc_rkey(fence->bind_rkey);
422 
423 	ibdev_dbg(&qp->rdev->ibdev,
424 		  "Posting bind fence-WQE: rkey: %#x QP: %d PD: %p\n",
425 		wqe.bind.r_key, qp->qplib_qp.id, pd);
426 	rc = bnxt_qplib_post_send(&qp->qplib_qp, &wqe);
427 	if (rc) {
428 		ibdev_err(&qp->rdev->ibdev, "Failed to bind fence-WQE\n");
429 		return rc;
430 	}
431 	bnxt_qplib_post_send_db(&qp->qplib_qp);
432 
433 	return rc;
434 }
435 
436 static void bnxt_re_destroy_fence_mr(struct bnxt_re_pd *pd)
437 {
438 	struct bnxt_re_fence_data *fence = &pd->fence;
439 	struct bnxt_re_dev *rdev = pd->rdev;
440 	struct device *dev = &rdev->en_dev->pdev->dev;
441 	struct bnxt_re_mr *mr = fence->mr;
442 
443 	if (fence->mw) {
444 		bnxt_re_dealloc_mw(fence->mw);
445 		fence->mw = NULL;
446 	}
447 	if (mr) {
448 		if (mr->ib_mr.rkey)
449 			bnxt_qplib_dereg_mrw(&rdev->qplib_res, &mr->qplib_mr,
450 					     true);
451 		if (mr->ib_mr.lkey)
452 			bnxt_qplib_free_mrw(&rdev->qplib_res, &mr->qplib_mr);
453 		kfree(mr);
454 		fence->mr = NULL;
455 	}
456 	if (fence->dma_addr) {
457 		dma_unmap_single(dev, fence->dma_addr, BNXT_RE_FENCE_BYTES,
458 				 DMA_BIDIRECTIONAL);
459 		fence->dma_addr = 0;
460 	}
461 }
462 
463 static int bnxt_re_create_fence_mr(struct bnxt_re_pd *pd)
464 {
465 	int mr_access_flags = IB_ACCESS_LOCAL_WRITE | IB_ACCESS_MW_BIND;
466 	struct bnxt_re_fence_data *fence = &pd->fence;
467 	struct bnxt_re_dev *rdev = pd->rdev;
468 	struct device *dev = &rdev->en_dev->pdev->dev;
469 	struct bnxt_re_mr *mr = NULL;
470 	dma_addr_t dma_addr = 0;
471 	struct ib_mw *mw;
472 	u64 pbl_tbl;
473 	int rc;
474 
475 	dma_addr = dma_map_single(dev, fence->va, BNXT_RE_FENCE_BYTES,
476 				  DMA_BIDIRECTIONAL);
477 	rc = dma_mapping_error(dev, dma_addr);
478 	if (rc) {
479 		ibdev_err(&rdev->ibdev, "Failed to dma-map fence-MR-mem\n");
480 		rc = -EIO;
481 		fence->dma_addr = 0;
482 		goto fail;
483 	}
484 	fence->dma_addr = dma_addr;
485 
486 	/* Allocate a MR */
487 	mr = kzalloc(sizeof(*mr), GFP_KERNEL);
488 	if (!mr) {
489 		rc = -ENOMEM;
490 		goto fail;
491 	}
492 	fence->mr = mr;
493 	mr->rdev = rdev;
494 	mr->qplib_mr.pd = &pd->qplib_pd;
495 	mr->qplib_mr.type = CMDQ_ALLOCATE_MRW_MRW_FLAGS_PMR;
496 	mr->qplib_mr.flags = __from_ib_access_flags(mr_access_flags);
497 	rc = bnxt_qplib_alloc_mrw(&rdev->qplib_res, &mr->qplib_mr);
498 	if (rc) {
499 		ibdev_err(&rdev->ibdev, "Failed to alloc fence-HW-MR\n");
500 		goto fail;
501 	}
502 
503 	/* Register MR */
504 	mr->ib_mr.lkey = mr->qplib_mr.lkey;
505 	mr->qplib_mr.va = (u64)(unsigned long)fence->va;
506 	mr->qplib_mr.total_size = BNXT_RE_FENCE_BYTES;
507 	pbl_tbl = dma_addr;
508 	rc = bnxt_qplib_reg_mr(&rdev->qplib_res, &mr->qplib_mr, &pbl_tbl,
509 			       BNXT_RE_FENCE_PBL_SIZE, false, PAGE_SIZE);
510 	if (rc) {
511 		ibdev_err(&rdev->ibdev, "Failed to register fence-MR\n");
512 		goto fail;
513 	}
514 	mr->ib_mr.rkey = mr->qplib_mr.rkey;
515 
516 	/* Create a fence MW only for kernel consumers */
517 	mw = bnxt_re_alloc_mw(&pd->ib_pd, IB_MW_TYPE_1, NULL);
518 	if (IS_ERR(mw)) {
519 		ibdev_err(&rdev->ibdev,
520 			  "Failed to create fence-MW for PD: %p\n", pd);
521 		rc = PTR_ERR(mw);
522 		goto fail;
523 	}
524 	fence->mw = mw;
525 
526 	bnxt_re_create_fence_wqe(pd);
527 	return 0;
528 
529 fail:
530 	bnxt_re_destroy_fence_mr(pd);
531 	return rc;
532 }
533 
534 /* Protection Domains */
535 void bnxt_re_dealloc_pd(struct ib_pd *ib_pd, struct ib_udata *udata)
536 {
537 	struct bnxt_re_pd *pd = container_of(ib_pd, struct bnxt_re_pd, ib_pd);
538 	struct bnxt_re_dev *rdev = pd->rdev;
539 
540 	bnxt_re_destroy_fence_mr(pd);
541 
542 	if (pd->qplib_pd.id)
543 		bnxt_qplib_dealloc_pd(&rdev->qplib_res, &rdev->qplib_res.pd_tbl,
544 				      &pd->qplib_pd);
545 }
546 
547 int bnxt_re_alloc_pd(struct ib_pd *ibpd, struct ib_udata *udata)
548 {
549 	struct ib_device *ibdev = ibpd->device;
550 	struct bnxt_re_dev *rdev = to_bnxt_re_dev(ibdev, ibdev);
551 	struct bnxt_re_ucontext *ucntx = rdma_udata_to_drv_context(
552 		udata, struct bnxt_re_ucontext, ib_uctx);
553 	struct bnxt_re_pd *pd = container_of(ibpd, struct bnxt_re_pd, ib_pd);
554 	int rc;
555 
556 	pd->rdev = rdev;
557 	if (bnxt_qplib_alloc_pd(&rdev->qplib_res.pd_tbl, &pd->qplib_pd)) {
558 		ibdev_err(&rdev->ibdev, "Failed to allocate HW PD");
559 		rc = -ENOMEM;
560 		goto fail;
561 	}
562 
563 	if (udata) {
564 		struct bnxt_re_pd_resp resp;
565 
566 		if (!ucntx->dpi.dbr) {
567 			/* Allocate DPI in alloc_pd to avoid failing of
568 			 * ibv_devinfo and family of application when DPIs
569 			 * are depleted.
570 			 */
571 			if (bnxt_qplib_alloc_dpi(&rdev->qplib_res.dpi_tbl,
572 						 &ucntx->dpi, ucntx)) {
573 				rc = -ENOMEM;
574 				goto dbfail;
575 			}
576 		}
577 
578 		resp.pdid = pd->qplib_pd.id;
579 		/* Still allow mapping this DBR to the new user PD. */
580 		resp.dpi = ucntx->dpi.dpi;
581 		resp.dbr = (u64)ucntx->dpi.umdbr;
582 
583 		rc = ib_copy_to_udata(udata, &resp, sizeof(resp));
584 		if (rc) {
585 			ibdev_err(&rdev->ibdev,
586 				  "Failed to copy user response\n");
587 			goto dbfail;
588 		}
589 	}
590 
591 	if (!udata)
592 		if (bnxt_re_create_fence_mr(pd))
593 			ibdev_warn(&rdev->ibdev,
594 				   "Failed to create Fence-MR\n");
595 	return 0;
596 dbfail:
597 	bnxt_qplib_dealloc_pd(&rdev->qplib_res, &rdev->qplib_res.pd_tbl,
598 			      &pd->qplib_pd);
599 fail:
600 	return rc;
601 }
602 
603 /* Address Handles */
604 void bnxt_re_destroy_ah(struct ib_ah *ib_ah, u32 flags)
605 {
606 	struct bnxt_re_ah *ah = container_of(ib_ah, struct bnxt_re_ah, ib_ah);
607 	struct bnxt_re_dev *rdev = ah->rdev;
608 
609 	bnxt_qplib_destroy_ah(&rdev->qplib_res, &ah->qplib_ah,
610 			      !(flags & RDMA_DESTROY_AH_SLEEPABLE));
611 }
612 
613 static u8 bnxt_re_stack_to_dev_nw_type(enum rdma_network_type ntype)
614 {
615 	u8 nw_type;
616 
617 	switch (ntype) {
618 	case RDMA_NETWORK_IPV4:
619 		nw_type = CMDQ_CREATE_AH_TYPE_V2IPV4;
620 		break;
621 	case RDMA_NETWORK_IPV6:
622 		nw_type = CMDQ_CREATE_AH_TYPE_V2IPV6;
623 		break;
624 	default:
625 		nw_type = CMDQ_CREATE_AH_TYPE_V1;
626 		break;
627 	}
628 	return nw_type;
629 }
630 
631 int bnxt_re_create_ah(struct ib_ah *ib_ah, struct rdma_ah_init_attr *init_attr,
632 		      struct ib_udata *udata)
633 {
634 	struct ib_pd *ib_pd = ib_ah->pd;
635 	struct bnxt_re_pd *pd = container_of(ib_pd, struct bnxt_re_pd, ib_pd);
636 	struct rdma_ah_attr *ah_attr = init_attr->ah_attr;
637 	const struct ib_global_route *grh = rdma_ah_read_grh(ah_attr);
638 	struct bnxt_re_dev *rdev = pd->rdev;
639 	const struct ib_gid_attr *sgid_attr;
640 	struct bnxt_re_gid_ctx *ctx;
641 	struct bnxt_re_ah *ah = container_of(ib_ah, struct bnxt_re_ah, ib_ah);
642 	u8 nw_type;
643 	int rc;
644 
645 	if (!(rdma_ah_get_ah_flags(ah_attr) & IB_AH_GRH)) {
646 		ibdev_err(&rdev->ibdev, "Failed to alloc AH: GRH not set");
647 		return -EINVAL;
648 	}
649 
650 	ah->rdev = rdev;
651 	ah->qplib_ah.pd = &pd->qplib_pd;
652 
653 	/* Supply the configuration for the HW */
654 	memcpy(ah->qplib_ah.dgid.data, grh->dgid.raw,
655 	       sizeof(union ib_gid));
656 	sgid_attr = grh->sgid_attr;
657 	/* Get the HW context of the GID. The reference
658 	 * of GID table entry is already taken by the caller.
659 	 */
660 	ctx = rdma_read_gid_hw_context(sgid_attr);
661 	ah->qplib_ah.sgid_index = ctx->idx;
662 	ah->qplib_ah.host_sgid_index = grh->sgid_index;
663 	ah->qplib_ah.traffic_class = grh->traffic_class;
664 	ah->qplib_ah.flow_label = grh->flow_label;
665 	ah->qplib_ah.hop_limit = grh->hop_limit;
666 	ah->qplib_ah.sl = rdma_ah_get_sl(ah_attr);
667 
668 	/* Get network header type for this GID */
669 	nw_type = rdma_gid_attr_network_type(sgid_attr);
670 	ah->qplib_ah.nw_type = bnxt_re_stack_to_dev_nw_type(nw_type);
671 
672 	memcpy(ah->qplib_ah.dmac, ah_attr->roce.dmac, ETH_ALEN);
673 	rc = bnxt_qplib_create_ah(&rdev->qplib_res, &ah->qplib_ah,
674 				  !(init_attr->flags &
675 				    RDMA_CREATE_AH_SLEEPABLE));
676 	if (rc) {
677 		ibdev_err(&rdev->ibdev, "Failed to allocate HW AH");
678 		return rc;
679 	}
680 
681 	/* Write AVID to shared page. */
682 	if (udata) {
683 		struct bnxt_re_ucontext *uctx = rdma_udata_to_drv_context(
684 			udata, struct bnxt_re_ucontext, ib_uctx);
685 		unsigned long flag;
686 		u32 *wrptr;
687 
688 		spin_lock_irqsave(&uctx->sh_lock, flag);
689 		wrptr = (u32 *)(uctx->shpg + BNXT_RE_AVID_OFFT);
690 		*wrptr = ah->qplib_ah.id;
691 		wmb(); /* make sure cache is updated. */
692 		spin_unlock_irqrestore(&uctx->sh_lock, flag);
693 	}
694 
695 	return 0;
696 }
697 
698 int bnxt_re_modify_ah(struct ib_ah *ib_ah, struct rdma_ah_attr *ah_attr)
699 {
700 	return 0;
701 }
702 
703 int bnxt_re_query_ah(struct ib_ah *ib_ah, struct rdma_ah_attr *ah_attr)
704 {
705 	struct bnxt_re_ah *ah = container_of(ib_ah, struct bnxt_re_ah, ib_ah);
706 
707 	ah_attr->type = ib_ah->type;
708 	rdma_ah_set_sl(ah_attr, ah->qplib_ah.sl);
709 	memcpy(ah_attr->roce.dmac, ah->qplib_ah.dmac, ETH_ALEN);
710 	rdma_ah_set_grh(ah_attr, NULL, 0,
711 			ah->qplib_ah.host_sgid_index,
712 			0, ah->qplib_ah.traffic_class);
713 	rdma_ah_set_dgid_raw(ah_attr, ah->qplib_ah.dgid.data);
714 	rdma_ah_set_port_num(ah_attr, 1);
715 	rdma_ah_set_static_rate(ah_attr, 0);
716 	return 0;
717 }
718 
719 unsigned long bnxt_re_lock_cqs(struct bnxt_re_qp *qp)
720 	__acquires(&qp->scq->cq_lock) __acquires(&qp->rcq->cq_lock)
721 {
722 	unsigned long flags;
723 
724 	spin_lock_irqsave(&qp->scq->cq_lock, flags);
725 	if (qp->rcq != qp->scq)
726 		spin_lock(&qp->rcq->cq_lock);
727 	else
728 		__acquire(&qp->rcq->cq_lock);
729 
730 	return flags;
731 }
732 
733 void bnxt_re_unlock_cqs(struct bnxt_re_qp *qp,
734 			unsigned long flags)
735 	__releases(&qp->scq->cq_lock) __releases(&qp->rcq->cq_lock)
736 {
737 	if (qp->rcq != qp->scq)
738 		spin_unlock(&qp->rcq->cq_lock);
739 	else
740 		__release(&qp->rcq->cq_lock);
741 	spin_unlock_irqrestore(&qp->scq->cq_lock, flags);
742 }
743 
744 static int bnxt_re_destroy_gsi_sqp(struct bnxt_re_qp *qp)
745 {
746 	struct bnxt_re_qp *gsi_sqp;
747 	struct bnxt_re_ah *gsi_sah;
748 	struct bnxt_re_dev *rdev;
749 	int rc = 0;
750 
751 	rdev = qp->rdev;
752 	gsi_sqp = rdev->gsi_ctx.gsi_sqp;
753 	gsi_sah = rdev->gsi_ctx.gsi_sah;
754 
755 	/* remove from active qp list */
756 	mutex_lock(&rdev->qp_lock);
757 	list_del(&gsi_sqp->list);
758 	mutex_unlock(&rdev->qp_lock);
759 	atomic_dec(&rdev->qp_count);
760 
761 	ibdev_dbg(&rdev->ibdev, "Destroy the shadow AH\n");
762 	bnxt_qplib_destroy_ah(&rdev->qplib_res,
763 			      &gsi_sah->qplib_ah,
764 			      true);
765 	bnxt_qplib_clean_qp(&qp->qplib_qp);
766 
767 	ibdev_dbg(&rdev->ibdev, "Destroy the shadow QP\n");
768 	rc = bnxt_qplib_destroy_qp(&rdev->qplib_res, &gsi_sqp->qplib_qp);
769 	if (rc) {
770 		ibdev_err(&rdev->ibdev, "Destroy Shadow QP failed");
771 		goto fail;
772 	}
773 	bnxt_qplib_free_qp_res(&rdev->qplib_res, &gsi_sqp->qplib_qp);
774 
775 	kfree(rdev->gsi_ctx.sqp_tbl);
776 	kfree(gsi_sah);
777 	kfree(gsi_sqp);
778 	rdev->gsi_ctx.gsi_sqp = NULL;
779 	rdev->gsi_ctx.gsi_sah = NULL;
780 	rdev->gsi_ctx.sqp_tbl = NULL;
781 
782 	return 0;
783 fail:
784 	return rc;
785 }
786 
787 /* Queue Pairs */
788 int bnxt_re_destroy_qp(struct ib_qp *ib_qp, struct ib_udata *udata)
789 {
790 	struct bnxt_re_qp *qp = container_of(ib_qp, struct bnxt_re_qp, ib_qp);
791 	struct bnxt_re_dev *rdev = qp->rdev;
792 	unsigned int flags;
793 	int rc;
794 
795 	mutex_lock(&rdev->qp_lock);
796 	list_del(&qp->list);
797 	mutex_unlock(&rdev->qp_lock);
798 	atomic_dec(&rdev->qp_count);
799 
800 	bnxt_qplib_flush_cqn_wq(&qp->qplib_qp);
801 
802 	rc = bnxt_qplib_destroy_qp(&rdev->qplib_res, &qp->qplib_qp);
803 	if (rc) {
804 		ibdev_err(&rdev->ibdev, "Failed to destroy HW QP");
805 		return rc;
806 	}
807 
808 	if (rdma_is_kernel_res(&qp->ib_qp.res)) {
809 		flags = bnxt_re_lock_cqs(qp);
810 		bnxt_qplib_clean_qp(&qp->qplib_qp);
811 		bnxt_re_unlock_cqs(qp, flags);
812 	}
813 
814 	bnxt_qplib_free_qp_res(&rdev->qplib_res, &qp->qplib_qp);
815 
816 	if (ib_qp->qp_type == IB_QPT_GSI && rdev->gsi_ctx.gsi_sqp) {
817 		rc = bnxt_re_destroy_gsi_sqp(qp);
818 		if (rc)
819 			goto sh_fail;
820 	}
821 
822 	ib_umem_release(qp->rumem);
823 	ib_umem_release(qp->sumem);
824 
825 	kfree(qp);
826 	return 0;
827 sh_fail:
828 	return rc;
829 }
830 
831 static u8 __from_ib_qp_type(enum ib_qp_type type)
832 {
833 	switch (type) {
834 	case IB_QPT_GSI:
835 		return CMDQ_CREATE_QP1_TYPE_GSI;
836 	case IB_QPT_RC:
837 		return CMDQ_CREATE_QP_TYPE_RC;
838 	case IB_QPT_UD:
839 		return CMDQ_CREATE_QP_TYPE_UD;
840 	default:
841 		return IB_QPT_MAX;
842 	}
843 }
844 
845 static int bnxt_re_init_user_qp(struct bnxt_re_dev *rdev, struct bnxt_re_pd *pd,
846 				struct bnxt_re_qp *qp, struct ib_udata *udata)
847 {
848 	struct bnxt_re_qp_req ureq;
849 	struct bnxt_qplib_qp *qplib_qp = &qp->qplib_qp;
850 	struct ib_umem *umem;
851 	int bytes = 0, psn_sz;
852 	struct bnxt_re_ucontext *cntx = rdma_udata_to_drv_context(
853 		udata, struct bnxt_re_ucontext, ib_uctx);
854 
855 	if (ib_copy_from_udata(&ureq, udata, sizeof(ureq)))
856 		return -EFAULT;
857 
858 	bytes = (qplib_qp->sq.max_wqe * qplib_qp->sq.wqe_size);
859 	/* Consider mapping PSN search memory only for RC QPs. */
860 	if (qplib_qp->type == CMDQ_CREATE_QP_TYPE_RC) {
861 		psn_sz = bnxt_qplib_is_chip_gen_p5(rdev->chip_ctx) ?
862 					sizeof(struct sq_psn_search_ext) :
863 					sizeof(struct sq_psn_search);
864 		bytes += (qplib_qp->sq.max_wqe * psn_sz);
865 	}
866 	bytes = PAGE_ALIGN(bytes);
867 	umem = ib_umem_get(&rdev->ibdev, ureq.qpsva, bytes,
868 			   IB_ACCESS_LOCAL_WRITE);
869 	if (IS_ERR(umem))
870 		return PTR_ERR(umem);
871 
872 	qp->sumem = umem;
873 	qplib_qp->sq.sg_info.sghead = umem->sg_head.sgl;
874 	qplib_qp->sq.sg_info.npages = ib_umem_num_pages(umem);
875 	qplib_qp->sq.sg_info.nmap = umem->nmap;
876 	qplib_qp->sq.sg_info.pgsize = PAGE_SIZE;
877 	qplib_qp->sq.sg_info.pgshft = PAGE_SHIFT;
878 	qplib_qp->qp_handle = ureq.qp_handle;
879 
880 	if (!qp->qplib_qp.srq) {
881 		bytes = (qplib_qp->rq.max_wqe * qplib_qp->rq.wqe_size);
882 		bytes = PAGE_ALIGN(bytes);
883 		umem = ib_umem_get(&rdev->ibdev, ureq.qprva, bytes,
884 				   IB_ACCESS_LOCAL_WRITE);
885 		if (IS_ERR(umem))
886 			goto rqfail;
887 		qp->rumem = umem;
888 		qplib_qp->rq.sg_info.sghead = umem->sg_head.sgl;
889 		qplib_qp->rq.sg_info.npages = ib_umem_num_pages(umem);
890 		qplib_qp->rq.sg_info.nmap = umem->nmap;
891 		qplib_qp->rq.sg_info.pgsize = PAGE_SIZE;
892 		qplib_qp->rq.sg_info.pgshft = PAGE_SHIFT;
893 	}
894 
895 	qplib_qp->dpi = &cntx->dpi;
896 	return 0;
897 rqfail:
898 	ib_umem_release(qp->sumem);
899 	qp->sumem = NULL;
900 	memset(&qplib_qp->sq.sg_info, 0, sizeof(qplib_qp->sq.sg_info));
901 
902 	return PTR_ERR(umem);
903 }
904 
905 static struct bnxt_re_ah *bnxt_re_create_shadow_qp_ah
906 				(struct bnxt_re_pd *pd,
907 				 struct bnxt_qplib_res *qp1_res,
908 				 struct bnxt_qplib_qp *qp1_qp)
909 {
910 	struct bnxt_re_dev *rdev = pd->rdev;
911 	struct bnxt_re_ah *ah;
912 	union ib_gid sgid;
913 	int rc;
914 
915 	ah = kzalloc(sizeof(*ah), GFP_KERNEL);
916 	if (!ah)
917 		return NULL;
918 
919 	ah->rdev = rdev;
920 	ah->qplib_ah.pd = &pd->qplib_pd;
921 
922 	rc = bnxt_re_query_gid(&rdev->ibdev, 1, 0, &sgid);
923 	if (rc)
924 		goto fail;
925 
926 	/* supply the dgid data same as sgid */
927 	memcpy(ah->qplib_ah.dgid.data, &sgid.raw,
928 	       sizeof(union ib_gid));
929 	ah->qplib_ah.sgid_index = 0;
930 
931 	ah->qplib_ah.traffic_class = 0;
932 	ah->qplib_ah.flow_label = 0;
933 	ah->qplib_ah.hop_limit = 1;
934 	ah->qplib_ah.sl = 0;
935 	/* Have DMAC same as SMAC */
936 	ether_addr_copy(ah->qplib_ah.dmac, rdev->netdev->dev_addr);
937 
938 	rc = bnxt_qplib_create_ah(&rdev->qplib_res, &ah->qplib_ah, false);
939 	if (rc) {
940 		ibdev_err(&rdev->ibdev,
941 			  "Failed to allocate HW AH for Shadow QP");
942 		goto fail;
943 	}
944 
945 	return ah;
946 
947 fail:
948 	kfree(ah);
949 	return NULL;
950 }
951 
952 static struct bnxt_re_qp *bnxt_re_create_shadow_qp
953 				(struct bnxt_re_pd *pd,
954 				 struct bnxt_qplib_res *qp1_res,
955 				 struct bnxt_qplib_qp *qp1_qp)
956 {
957 	struct bnxt_re_dev *rdev = pd->rdev;
958 	struct bnxt_re_qp *qp;
959 	int rc;
960 
961 	qp = kzalloc(sizeof(*qp), GFP_KERNEL);
962 	if (!qp)
963 		return NULL;
964 
965 	qp->rdev = rdev;
966 
967 	/* Initialize the shadow QP structure from the QP1 values */
968 	ether_addr_copy(qp->qplib_qp.smac, rdev->netdev->dev_addr);
969 
970 	qp->qplib_qp.pd = &pd->qplib_pd;
971 	qp->qplib_qp.qp_handle = (u64)(unsigned long)(&qp->qplib_qp);
972 	qp->qplib_qp.type = IB_QPT_UD;
973 
974 	qp->qplib_qp.max_inline_data = 0;
975 	qp->qplib_qp.sig_type = true;
976 
977 	/* Shadow QP SQ depth should be same as QP1 RQ depth */
978 	qp->qplib_qp.sq.wqe_size = bnxt_re_get_swqe_size();
979 	qp->qplib_qp.sq.max_wqe = qp1_qp->rq.max_wqe;
980 	qp->qplib_qp.sq.max_sge = 2;
981 	/* Q full delta can be 1 since it is internal QP */
982 	qp->qplib_qp.sq.q_full_delta = 1;
983 	qp->qplib_qp.sq.sg_info.pgsize = PAGE_SIZE;
984 	qp->qplib_qp.sq.sg_info.pgshft = PAGE_SHIFT;
985 
986 	qp->qplib_qp.scq = qp1_qp->scq;
987 	qp->qplib_qp.rcq = qp1_qp->rcq;
988 
989 	qp->qplib_qp.rq.wqe_size = bnxt_re_get_rwqe_size();
990 	qp->qplib_qp.rq.max_wqe = qp1_qp->rq.max_wqe;
991 	qp->qplib_qp.rq.max_sge = qp1_qp->rq.max_sge;
992 	/* Q full delta can be 1 since it is internal QP */
993 	qp->qplib_qp.rq.q_full_delta = 1;
994 	qp->qplib_qp.rq.sg_info.pgsize = PAGE_SIZE;
995 	qp->qplib_qp.rq.sg_info.pgshft = PAGE_SHIFT;
996 
997 	qp->qplib_qp.mtu = qp1_qp->mtu;
998 
999 	qp->qplib_qp.sq_hdr_buf_size = 0;
1000 	qp->qplib_qp.rq_hdr_buf_size = BNXT_QPLIB_MAX_GRH_HDR_SIZE_IPV6;
1001 	qp->qplib_qp.dpi = &rdev->dpi_privileged;
1002 
1003 	rc = bnxt_qplib_create_qp(qp1_res, &qp->qplib_qp);
1004 	if (rc)
1005 		goto fail;
1006 
1007 	spin_lock_init(&qp->sq_lock);
1008 	INIT_LIST_HEAD(&qp->list);
1009 	mutex_lock(&rdev->qp_lock);
1010 	list_add_tail(&qp->list, &rdev->qp_list);
1011 	atomic_inc(&rdev->qp_count);
1012 	mutex_unlock(&rdev->qp_lock);
1013 	return qp;
1014 fail:
1015 	kfree(qp);
1016 	return NULL;
1017 }
1018 
1019 static int bnxt_re_init_rq_attr(struct bnxt_re_qp *qp,
1020 				struct ib_qp_init_attr *init_attr)
1021 {
1022 	struct bnxt_qplib_dev_attr *dev_attr;
1023 	struct bnxt_qplib_qp *qplqp;
1024 	struct bnxt_re_dev *rdev;
1025 	struct bnxt_qplib_q *rq;
1026 	int entries;
1027 
1028 	rdev = qp->rdev;
1029 	qplqp = &qp->qplib_qp;
1030 	rq = &qplqp->rq;
1031 	dev_attr = &rdev->dev_attr;
1032 
1033 	if (init_attr->srq) {
1034 		struct bnxt_re_srq *srq;
1035 
1036 		srq = container_of(init_attr->srq, struct bnxt_re_srq, ib_srq);
1037 		if (!srq) {
1038 			ibdev_err(&rdev->ibdev, "SRQ not found");
1039 			return -EINVAL;
1040 		}
1041 		qplqp->srq = &srq->qplib_srq;
1042 		rq->max_wqe = 0;
1043 	} else {
1044 		rq->wqe_size = bnxt_re_get_rwqe_size();
1045 		/* Allocate 1 more than what's provided so posting max doesn't
1046 		 * mean empty.
1047 		 */
1048 		entries = roundup_pow_of_two(init_attr->cap.max_recv_wr + 1);
1049 		rq->max_wqe = min_t(u32, entries, dev_attr->max_qp_wqes + 1);
1050 		rq->q_full_delta = rq->max_wqe - init_attr->cap.max_recv_wr;
1051 		rq->max_sge = init_attr->cap.max_recv_sge;
1052 		if (rq->max_sge > dev_attr->max_qp_sges)
1053 			rq->max_sge = dev_attr->max_qp_sges;
1054 	}
1055 	rq->sg_info.pgsize = PAGE_SIZE;
1056 	rq->sg_info.pgshft = PAGE_SHIFT;
1057 
1058 	return 0;
1059 }
1060 
1061 static void bnxt_re_adjust_gsi_rq_attr(struct bnxt_re_qp *qp)
1062 {
1063 	struct bnxt_qplib_dev_attr *dev_attr;
1064 	struct bnxt_qplib_qp *qplqp;
1065 	struct bnxt_re_dev *rdev;
1066 
1067 	rdev = qp->rdev;
1068 	qplqp = &qp->qplib_qp;
1069 	dev_attr = &rdev->dev_attr;
1070 
1071 	qplqp->rq.max_sge = dev_attr->max_qp_sges;
1072 	if (qplqp->rq.max_sge > dev_attr->max_qp_sges)
1073 		qplqp->rq.max_sge = dev_attr->max_qp_sges;
1074 	qplqp->rq.max_sge = 6;
1075 }
1076 
1077 static void bnxt_re_init_sq_attr(struct bnxt_re_qp *qp,
1078 				 struct ib_qp_init_attr *init_attr,
1079 				 struct ib_udata *udata)
1080 {
1081 	struct bnxt_qplib_dev_attr *dev_attr;
1082 	struct bnxt_qplib_qp *qplqp;
1083 	struct bnxt_re_dev *rdev;
1084 	struct bnxt_qplib_q *sq;
1085 	int entries;
1086 
1087 	rdev = qp->rdev;
1088 	qplqp = &qp->qplib_qp;
1089 	sq = &qplqp->sq;
1090 	dev_attr = &rdev->dev_attr;
1091 
1092 	sq->wqe_size = bnxt_re_get_swqe_size();
1093 	sq->max_sge = init_attr->cap.max_send_sge;
1094 	if (sq->max_sge > dev_attr->max_qp_sges)
1095 		sq->max_sge = dev_attr->max_qp_sges;
1096 	/*
1097 	 * Change the SQ depth if user has requested minimum using
1098 	 * configfs. Only supported for kernel consumers
1099 	 */
1100 	entries = init_attr->cap.max_send_wr;
1101 	/* Allocate 128 + 1 more than what's provided */
1102 	entries = roundup_pow_of_two(entries + BNXT_QPLIB_RESERVED_QP_WRS + 1);
1103 	sq->max_wqe = min_t(u32, entries, dev_attr->max_qp_wqes +
1104 			    BNXT_QPLIB_RESERVED_QP_WRS + 1);
1105 	sq->q_full_delta = BNXT_QPLIB_RESERVED_QP_WRS + 1;
1106 	/*
1107 	 * Reserving one slot for Phantom WQE. Application can
1108 	 * post one extra entry in this case. But allowing this to avoid
1109 	 * unexpected Queue full condition
1110 	 */
1111 	qplqp->sq.q_full_delta -= 1;
1112 	qplqp->sq.sg_info.pgsize = PAGE_SIZE;
1113 	qplqp->sq.sg_info.pgshft = PAGE_SHIFT;
1114 }
1115 
1116 static void bnxt_re_adjust_gsi_sq_attr(struct bnxt_re_qp *qp,
1117 				       struct ib_qp_init_attr *init_attr)
1118 {
1119 	struct bnxt_qplib_dev_attr *dev_attr;
1120 	struct bnxt_qplib_qp *qplqp;
1121 	struct bnxt_re_dev *rdev;
1122 	int entries;
1123 
1124 	rdev = qp->rdev;
1125 	qplqp = &qp->qplib_qp;
1126 	dev_attr = &rdev->dev_attr;
1127 
1128 	entries = roundup_pow_of_two(init_attr->cap.max_send_wr + 1);
1129 	qplqp->sq.max_wqe = min_t(u32, entries, dev_attr->max_qp_wqes + 1);
1130 	qplqp->sq.q_full_delta = qplqp->sq.max_wqe -
1131 				 init_attr->cap.max_send_wr;
1132 	qplqp->sq.max_sge++; /* Need one extra sge to put UD header */
1133 	if (qplqp->sq.max_sge > dev_attr->max_qp_sges)
1134 		qplqp->sq.max_sge = dev_attr->max_qp_sges;
1135 }
1136 
1137 static int bnxt_re_init_qp_type(struct bnxt_re_dev *rdev,
1138 				struct ib_qp_init_attr *init_attr)
1139 {
1140 	struct bnxt_qplib_chip_ctx *chip_ctx;
1141 	int qptype;
1142 
1143 	chip_ctx = rdev->chip_ctx;
1144 
1145 	qptype = __from_ib_qp_type(init_attr->qp_type);
1146 	if (qptype == IB_QPT_MAX) {
1147 		ibdev_err(&rdev->ibdev, "QP type 0x%x not supported", qptype);
1148 		qptype = -EOPNOTSUPP;
1149 		goto out;
1150 	}
1151 
1152 	if (bnxt_qplib_is_chip_gen_p5(chip_ctx) &&
1153 	    init_attr->qp_type == IB_QPT_GSI)
1154 		qptype = CMDQ_CREATE_QP_TYPE_GSI;
1155 out:
1156 	return qptype;
1157 }
1158 
1159 static int bnxt_re_init_qp_attr(struct bnxt_re_qp *qp, struct bnxt_re_pd *pd,
1160 				struct ib_qp_init_attr *init_attr,
1161 				struct ib_udata *udata)
1162 {
1163 	struct bnxt_qplib_dev_attr *dev_attr;
1164 	struct bnxt_qplib_qp *qplqp;
1165 	struct bnxt_re_dev *rdev;
1166 	struct bnxt_re_cq *cq;
1167 	int rc = 0, qptype;
1168 
1169 	rdev = qp->rdev;
1170 	qplqp = &qp->qplib_qp;
1171 	dev_attr = &rdev->dev_attr;
1172 
1173 	/* Setup misc params */
1174 	ether_addr_copy(qplqp->smac, rdev->netdev->dev_addr);
1175 	qplqp->pd = &pd->qplib_pd;
1176 	qplqp->qp_handle = (u64)qplqp;
1177 	qplqp->max_inline_data = init_attr->cap.max_inline_data;
1178 	qplqp->sig_type = ((init_attr->sq_sig_type == IB_SIGNAL_ALL_WR) ?
1179 			    true : false);
1180 	qptype = bnxt_re_init_qp_type(rdev, init_attr);
1181 	if (qptype < 0) {
1182 		rc = qptype;
1183 		goto out;
1184 	}
1185 	qplqp->type = (u8)qptype;
1186 
1187 	if (init_attr->qp_type == IB_QPT_RC) {
1188 		qplqp->max_rd_atomic = dev_attr->max_qp_rd_atom;
1189 		qplqp->max_dest_rd_atomic = dev_attr->max_qp_init_rd_atom;
1190 	}
1191 	qplqp->mtu = ib_mtu_enum_to_int(iboe_get_mtu(rdev->netdev->mtu));
1192 	qplqp->dpi = &rdev->dpi_privileged; /* Doorbell page */
1193 	if (init_attr->create_flags)
1194 		ibdev_dbg(&rdev->ibdev,
1195 			  "QP create flags 0x%x not supported",
1196 			  init_attr->create_flags);
1197 
1198 	/* Setup CQs */
1199 	if (init_attr->send_cq) {
1200 		cq = container_of(init_attr->send_cq, struct bnxt_re_cq, ib_cq);
1201 		if (!cq) {
1202 			ibdev_err(&rdev->ibdev, "Send CQ not found");
1203 			rc = -EINVAL;
1204 			goto out;
1205 		}
1206 		qplqp->scq = &cq->qplib_cq;
1207 		qp->scq = cq;
1208 	}
1209 
1210 	if (init_attr->recv_cq) {
1211 		cq = container_of(init_attr->recv_cq, struct bnxt_re_cq, ib_cq);
1212 		if (!cq) {
1213 			ibdev_err(&rdev->ibdev, "Receive CQ not found");
1214 			rc = -EINVAL;
1215 			goto out;
1216 		}
1217 		qplqp->rcq = &cq->qplib_cq;
1218 		qp->rcq = cq;
1219 	}
1220 
1221 	/* Setup RQ/SRQ */
1222 	rc = bnxt_re_init_rq_attr(qp, init_attr);
1223 	if (rc)
1224 		goto out;
1225 	if (init_attr->qp_type == IB_QPT_GSI)
1226 		bnxt_re_adjust_gsi_rq_attr(qp);
1227 
1228 	/* Setup SQ */
1229 	bnxt_re_init_sq_attr(qp, init_attr, udata);
1230 	if (init_attr->qp_type == IB_QPT_GSI)
1231 		bnxt_re_adjust_gsi_sq_attr(qp, init_attr);
1232 
1233 	if (udata) /* This will update DPI and qp_handle */
1234 		rc = bnxt_re_init_user_qp(rdev, pd, qp, udata);
1235 out:
1236 	return rc;
1237 }
1238 
1239 static int bnxt_re_create_shadow_gsi(struct bnxt_re_qp *qp,
1240 				     struct bnxt_re_pd *pd)
1241 {
1242 	struct bnxt_re_sqp_entries *sqp_tbl = NULL;
1243 	struct bnxt_re_dev *rdev;
1244 	struct bnxt_re_qp *sqp;
1245 	struct bnxt_re_ah *sah;
1246 	int rc = 0;
1247 
1248 	rdev = qp->rdev;
1249 	/* Create a shadow QP to handle the QP1 traffic */
1250 	sqp_tbl = kzalloc(sizeof(*sqp_tbl) * BNXT_RE_MAX_GSI_SQP_ENTRIES,
1251 			  GFP_KERNEL);
1252 	if (!sqp_tbl)
1253 		return -ENOMEM;
1254 	rdev->gsi_ctx.sqp_tbl = sqp_tbl;
1255 
1256 	sqp = bnxt_re_create_shadow_qp(pd, &rdev->qplib_res, &qp->qplib_qp);
1257 	if (!sqp) {
1258 		rc = -ENODEV;
1259 		ibdev_err(&rdev->ibdev, "Failed to create Shadow QP for QP1");
1260 		goto out;
1261 	}
1262 	rdev->gsi_ctx.gsi_sqp = sqp;
1263 
1264 	sqp->rcq = qp->rcq;
1265 	sqp->scq = qp->scq;
1266 	sah = bnxt_re_create_shadow_qp_ah(pd, &rdev->qplib_res,
1267 					  &qp->qplib_qp);
1268 	if (!sah) {
1269 		bnxt_qplib_destroy_qp(&rdev->qplib_res,
1270 				      &sqp->qplib_qp);
1271 		rc = -ENODEV;
1272 		ibdev_err(&rdev->ibdev,
1273 			  "Failed to create AH entry for ShadowQP");
1274 		goto out;
1275 	}
1276 	rdev->gsi_ctx.gsi_sah = sah;
1277 
1278 	return 0;
1279 out:
1280 	kfree(sqp_tbl);
1281 	return rc;
1282 }
1283 
1284 static int bnxt_re_create_gsi_qp(struct bnxt_re_qp *qp, struct bnxt_re_pd *pd,
1285 				 struct ib_qp_init_attr *init_attr)
1286 {
1287 	struct bnxt_re_dev *rdev;
1288 	struct bnxt_qplib_qp *qplqp;
1289 	int rc = 0;
1290 
1291 	rdev = qp->rdev;
1292 	qplqp = &qp->qplib_qp;
1293 
1294 	qplqp->rq_hdr_buf_size = BNXT_QPLIB_MAX_QP1_RQ_HDR_SIZE_V2;
1295 	qplqp->sq_hdr_buf_size = BNXT_QPLIB_MAX_QP1_SQ_HDR_SIZE_V2;
1296 
1297 	rc = bnxt_qplib_create_qp1(&rdev->qplib_res, qplqp);
1298 	if (rc) {
1299 		ibdev_err(&rdev->ibdev, "create HW QP1 failed!");
1300 		goto out;
1301 	}
1302 
1303 	rc = bnxt_re_create_shadow_gsi(qp, pd);
1304 out:
1305 	return rc;
1306 }
1307 
1308 static bool bnxt_re_test_qp_limits(struct bnxt_re_dev *rdev,
1309 				   struct ib_qp_init_attr *init_attr,
1310 				   struct bnxt_qplib_dev_attr *dev_attr)
1311 {
1312 	bool rc = true;
1313 
1314 	if (init_attr->cap.max_send_wr > dev_attr->max_qp_wqes ||
1315 	    init_attr->cap.max_recv_wr > dev_attr->max_qp_wqes ||
1316 	    init_attr->cap.max_send_sge > dev_attr->max_qp_sges ||
1317 	    init_attr->cap.max_recv_sge > dev_attr->max_qp_sges ||
1318 	    init_attr->cap.max_inline_data > dev_attr->max_inline_data) {
1319 		ibdev_err(&rdev->ibdev,
1320 			  "Create QP failed - max exceeded! 0x%x/0x%x 0x%x/0x%x 0x%x/0x%x 0x%x/0x%x 0x%x/0x%x",
1321 			  init_attr->cap.max_send_wr, dev_attr->max_qp_wqes,
1322 			  init_attr->cap.max_recv_wr, dev_attr->max_qp_wqes,
1323 			  init_attr->cap.max_send_sge, dev_attr->max_qp_sges,
1324 			  init_attr->cap.max_recv_sge, dev_attr->max_qp_sges,
1325 			  init_attr->cap.max_inline_data,
1326 			  dev_attr->max_inline_data);
1327 		rc = false;
1328 	}
1329 	return rc;
1330 }
1331 
1332 struct ib_qp *bnxt_re_create_qp(struct ib_pd *ib_pd,
1333 				struct ib_qp_init_attr *qp_init_attr,
1334 				struct ib_udata *udata)
1335 {
1336 	struct bnxt_re_pd *pd = container_of(ib_pd, struct bnxt_re_pd, ib_pd);
1337 	struct bnxt_re_dev *rdev = pd->rdev;
1338 	struct bnxt_qplib_dev_attr *dev_attr = &rdev->dev_attr;
1339 	struct bnxt_re_qp *qp;
1340 	int rc;
1341 
1342 	rc = bnxt_re_test_qp_limits(rdev, qp_init_attr, dev_attr);
1343 	if (!rc) {
1344 		rc = -EINVAL;
1345 		goto exit;
1346 	}
1347 
1348 	qp = kzalloc(sizeof(*qp), GFP_KERNEL);
1349 	if (!qp) {
1350 		rc = -ENOMEM;
1351 		goto exit;
1352 	}
1353 	qp->rdev = rdev;
1354 	rc = bnxt_re_init_qp_attr(qp, pd, qp_init_attr, udata);
1355 	if (rc)
1356 		goto fail;
1357 
1358 	if (qp_init_attr->qp_type == IB_QPT_GSI &&
1359 	    !(bnxt_qplib_is_chip_gen_p5(rdev->chip_ctx))) {
1360 		rc = bnxt_re_create_gsi_qp(qp, pd, qp_init_attr);
1361 		if (rc == -ENODEV)
1362 			goto qp_destroy;
1363 		if (rc)
1364 			goto fail;
1365 	} else {
1366 		rc = bnxt_qplib_create_qp(&rdev->qplib_res, &qp->qplib_qp);
1367 		if (rc) {
1368 			ibdev_err(&rdev->ibdev, "Failed to create HW QP");
1369 			goto free_umem;
1370 		}
1371 		if (udata) {
1372 			struct bnxt_re_qp_resp resp;
1373 
1374 			resp.qpid = qp->qplib_qp.id;
1375 			resp.rsvd = 0;
1376 			rc = ib_copy_to_udata(udata, &resp, sizeof(resp));
1377 			if (rc) {
1378 				ibdev_err(&rdev->ibdev, "Failed to copy QP udata");
1379 				goto qp_destroy;
1380 			}
1381 		}
1382 	}
1383 
1384 	qp->ib_qp.qp_num = qp->qplib_qp.id;
1385 	if (qp_init_attr->qp_type == IB_QPT_GSI)
1386 		rdev->gsi_ctx.gsi_qp = qp;
1387 	spin_lock_init(&qp->sq_lock);
1388 	spin_lock_init(&qp->rq_lock);
1389 	INIT_LIST_HEAD(&qp->list);
1390 	mutex_lock(&rdev->qp_lock);
1391 	list_add_tail(&qp->list, &rdev->qp_list);
1392 	mutex_unlock(&rdev->qp_lock);
1393 	atomic_inc(&rdev->qp_count);
1394 
1395 	return &qp->ib_qp;
1396 qp_destroy:
1397 	bnxt_qplib_destroy_qp(&rdev->qplib_res, &qp->qplib_qp);
1398 free_umem:
1399 	ib_umem_release(qp->rumem);
1400 	ib_umem_release(qp->sumem);
1401 fail:
1402 	kfree(qp);
1403 exit:
1404 	return ERR_PTR(rc);
1405 }
1406 
1407 static u8 __from_ib_qp_state(enum ib_qp_state state)
1408 {
1409 	switch (state) {
1410 	case IB_QPS_RESET:
1411 		return CMDQ_MODIFY_QP_NEW_STATE_RESET;
1412 	case IB_QPS_INIT:
1413 		return CMDQ_MODIFY_QP_NEW_STATE_INIT;
1414 	case IB_QPS_RTR:
1415 		return CMDQ_MODIFY_QP_NEW_STATE_RTR;
1416 	case IB_QPS_RTS:
1417 		return CMDQ_MODIFY_QP_NEW_STATE_RTS;
1418 	case IB_QPS_SQD:
1419 		return CMDQ_MODIFY_QP_NEW_STATE_SQD;
1420 	case IB_QPS_SQE:
1421 		return CMDQ_MODIFY_QP_NEW_STATE_SQE;
1422 	case IB_QPS_ERR:
1423 	default:
1424 		return CMDQ_MODIFY_QP_NEW_STATE_ERR;
1425 	}
1426 }
1427 
1428 static enum ib_qp_state __to_ib_qp_state(u8 state)
1429 {
1430 	switch (state) {
1431 	case CMDQ_MODIFY_QP_NEW_STATE_RESET:
1432 		return IB_QPS_RESET;
1433 	case CMDQ_MODIFY_QP_NEW_STATE_INIT:
1434 		return IB_QPS_INIT;
1435 	case CMDQ_MODIFY_QP_NEW_STATE_RTR:
1436 		return IB_QPS_RTR;
1437 	case CMDQ_MODIFY_QP_NEW_STATE_RTS:
1438 		return IB_QPS_RTS;
1439 	case CMDQ_MODIFY_QP_NEW_STATE_SQD:
1440 		return IB_QPS_SQD;
1441 	case CMDQ_MODIFY_QP_NEW_STATE_SQE:
1442 		return IB_QPS_SQE;
1443 	case CMDQ_MODIFY_QP_NEW_STATE_ERR:
1444 	default:
1445 		return IB_QPS_ERR;
1446 	}
1447 }
1448 
1449 static u32 __from_ib_mtu(enum ib_mtu mtu)
1450 {
1451 	switch (mtu) {
1452 	case IB_MTU_256:
1453 		return CMDQ_MODIFY_QP_PATH_MTU_MTU_256;
1454 	case IB_MTU_512:
1455 		return CMDQ_MODIFY_QP_PATH_MTU_MTU_512;
1456 	case IB_MTU_1024:
1457 		return CMDQ_MODIFY_QP_PATH_MTU_MTU_1024;
1458 	case IB_MTU_2048:
1459 		return CMDQ_MODIFY_QP_PATH_MTU_MTU_2048;
1460 	case IB_MTU_4096:
1461 		return CMDQ_MODIFY_QP_PATH_MTU_MTU_4096;
1462 	default:
1463 		return CMDQ_MODIFY_QP_PATH_MTU_MTU_2048;
1464 	}
1465 }
1466 
1467 static enum ib_mtu __to_ib_mtu(u32 mtu)
1468 {
1469 	switch (mtu & CREQ_QUERY_QP_RESP_SB_PATH_MTU_MASK) {
1470 	case CMDQ_MODIFY_QP_PATH_MTU_MTU_256:
1471 		return IB_MTU_256;
1472 	case CMDQ_MODIFY_QP_PATH_MTU_MTU_512:
1473 		return IB_MTU_512;
1474 	case CMDQ_MODIFY_QP_PATH_MTU_MTU_1024:
1475 		return IB_MTU_1024;
1476 	case CMDQ_MODIFY_QP_PATH_MTU_MTU_2048:
1477 		return IB_MTU_2048;
1478 	case CMDQ_MODIFY_QP_PATH_MTU_MTU_4096:
1479 		return IB_MTU_4096;
1480 	default:
1481 		return IB_MTU_2048;
1482 	}
1483 }
1484 
1485 /* Shared Receive Queues */
1486 void bnxt_re_destroy_srq(struct ib_srq *ib_srq, struct ib_udata *udata)
1487 {
1488 	struct bnxt_re_srq *srq = container_of(ib_srq, struct bnxt_re_srq,
1489 					       ib_srq);
1490 	struct bnxt_re_dev *rdev = srq->rdev;
1491 	struct bnxt_qplib_srq *qplib_srq = &srq->qplib_srq;
1492 	struct bnxt_qplib_nq *nq = NULL;
1493 
1494 	if (qplib_srq->cq)
1495 		nq = qplib_srq->cq->nq;
1496 	bnxt_qplib_destroy_srq(&rdev->qplib_res, qplib_srq);
1497 	ib_umem_release(srq->umem);
1498 	atomic_dec(&rdev->srq_count);
1499 	if (nq)
1500 		nq->budget--;
1501 }
1502 
1503 static int bnxt_re_init_user_srq(struct bnxt_re_dev *rdev,
1504 				 struct bnxt_re_pd *pd,
1505 				 struct bnxt_re_srq *srq,
1506 				 struct ib_udata *udata)
1507 {
1508 	struct bnxt_re_srq_req ureq;
1509 	struct bnxt_qplib_srq *qplib_srq = &srq->qplib_srq;
1510 	struct ib_umem *umem;
1511 	int bytes = 0;
1512 	struct bnxt_re_ucontext *cntx = rdma_udata_to_drv_context(
1513 		udata, struct bnxt_re_ucontext, ib_uctx);
1514 
1515 	if (ib_copy_from_udata(&ureq, udata, sizeof(ureq)))
1516 		return -EFAULT;
1517 
1518 	bytes = (qplib_srq->max_wqe * qplib_srq->wqe_size);
1519 	bytes = PAGE_ALIGN(bytes);
1520 	umem = ib_umem_get(&rdev->ibdev, ureq.srqva, bytes,
1521 			   IB_ACCESS_LOCAL_WRITE);
1522 	if (IS_ERR(umem))
1523 		return PTR_ERR(umem);
1524 
1525 	srq->umem = umem;
1526 	qplib_srq->sg_info.sghead = umem->sg_head.sgl;
1527 	qplib_srq->sg_info.npages = ib_umem_num_pages(umem);
1528 	qplib_srq->sg_info.nmap = umem->nmap;
1529 	qplib_srq->sg_info.pgsize = PAGE_SIZE;
1530 	qplib_srq->sg_info.pgshft = PAGE_SHIFT;
1531 	qplib_srq->srq_handle = ureq.srq_handle;
1532 	qplib_srq->dpi = &cntx->dpi;
1533 
1534 	return 0;
1535 }
1536 
1537 int bnxt_re_create_srq(struct ib_srq *ib_srq,
1538 		       struct ib_srq_init_attr *srq_init_attr,
1539 		       struct ib_udata *udata)
1540 {
1541 	struct bnxt_qplib_dev_attr *dev_attr;
1542 	struct bnxt_qplib_nq *nq = NULL;
1543 	struct bnxt_re_dev *rdev;
1544 	struct bnxt_re_srq *srq;
1545 	struct bnxt_re_pd *pd;
1546 	struct ib_pd *ib_pd;
1547 	int rc, entries;
1548 
1549 	ib_pd = ib_srq->pd;
1550 	pd = container_of(ib_pd, struct bnxt_re_pd, ib_pd);
1551 	rdev = pd->rdev;
1552 	dev_attr = &rdev->dev_attr;
1553 	srq = container_of(ib_srq, struct bnxt_re_srq, ib_srq);
1554 
1555 	if (srq_init_attr->attr.max_wr >= dev_attr->max_srq_wqes) {
1556 		ibdev_err(&rdev->ibdev, "Create CQ failed - max exceeded");
1557 		rc = -EINVAL;
1558 		goto exit;
1559 	}
1560 
1561 	if (srq_init_attr->srq_type != IB_SRQT_BASIC) {
1562 		rc = -EOPNOTSUPP;
1563 		goto exit;
1564 	}
1565 
1566 	srq->rdev = rdev;
1567 	srq->qplib_srq.pd = &pd->qplib_pd;
1568 	srq->qplib_srq.dpi = &rdev->dpi_privileged;
1569 	/* Allocate 1 more than what's provided so posting max doesn't
1570 	 * mean empty
1571 	 */
1572 	entries = roundup_pow_of_two(srq_init_attr->attr.max_wr + 1);
1573 	if (entries > dev_attr->max_srq_wqes + 1)
1574 		entries = dev_attr->max_srq_wqes + 1;
1575 	srq->qplib_srq.max_wqe = entries;
1576 
1577 	srq->qplib_srq.wqe_size = bnxt_re_get_rwqe_size();
1578 	srq->qplib_srq.max_sge = srq_init_attr->attr.max_sge;
1579 	srq->qplib_srq.threshold = srq_init_attr->attr.srq_limit;
1580 	srq->srq_limit = srq_init_attr->attr.srq_limit;
1581 	srq->qplib_srq.eventq_hw_ring_id = rdev->nq[0].ring_id;
1582 	nq = &rdev->nq[0];
1583 
1584 	if (udata) {
1585 		rc = bnxt_re_init_user_srq(rdev, pd, srq, udata);
1586 		if (rc)
1587 			goto fail;
1588 	}
1589 
1590 	rc = bnxt_qplib_create_srq(&rdev->qplib_res, &srq->qplib_srq);
1591 	if (rc) {
1592 		ibdev_err(&rdev->ibdev, "Create HW SRQ failed!");
1593 		goto fail;
1594 	}
1595 
1596 	if (udata) {
1597 		struct bnxt_re_srq_resp resp;
1598 
1599 		resp.srqid = srq->qplib_srq.id;
1600 		rc = ib_copy_to_udata(udata, &resp, sizeof(resp));
1601 		if (rc) {
1602 			ibdev_err(&rdev->ibdev, "SRQ copy to udata failed!");
1603 			bnxt_qplib_destroy_srq(&rdev->qplib_res,
1604 					       &srq->qplib_srq);
1605 			goto fail;
1606 		}
1607 	}
1608 	if (nq)
1609 		nq->budget++;
1610 	atomic_inc(&rdev->srq_count);
1611 
1612 	return 0;
1613 
1614 fail:
1615 	ib_umem_release(srq->umem);
1616 exit:
1617 	return rc;
1618 }
1619 
1620 int bnxt_re_modify_srq(struct ib_srq *ib_srq, struct ib_srq_attr *srq_attr,
1621 		       enum ib_srq_attr_mask srq_attr_mask,
1622 		       struct ib_udata *udata)
1623 {
1624 	struct bnxt_re_srq *srq = container_of(ib_srq, struct bnxt_re_srq,
1625 					       ib_srq);
1626 	struct bnxt_re_dev *rdev = srq->rdev;
1627 	int rc;
1628 
1629 	switch (srq_attr_mask) {
1630 	case IB_SRQ_MAX_WR:
1631 		/* SRQ resize is not supported */
1632 		break;
1633 	case IB_SRQ_LIMIT:
1634 		/* Change the SRQ threshold */
1635 		if (srq_attr->srq_limit > srq->qplib_srq.max_wqe)
1636 			return -EINVAL;
1637 
1638 		srq->qplib_srq.threshold = srq_attr->srq_limit;
1639 		rc = bnxt_qplib_modify_srq(&rdev->qplib_res, &srq->qplib_srq);
1640 		if (rc) {
1641 			ibdev_err(&rdev->ibdev, "Modify HW SRQ failed!");
1642 			return rc;
1643 		}
1644 		/* On success, update the shadow */
1645 		srq->srq_limit = srq_attr->srq_limit;
1646 		/* No need to Build and send response back to udata */
1647 		break;
1648 	default:
1649 		ibdev_err(&rdev->ibdev,
1650 			  "Unsupported srq_attr_mask 0x%x", srq_attr_mask);
1651 		return -EINVAL;
1652 	}
1653 	return 0;
1654 }
1655 
1656 int bnxt_re_query_srq(struct ib_srq *ib_srq, struct ib_srq_attr *srq_attr)
1657 {
1658 	struct bnxt_re_srq *srq = container_of(ib_srq, struct bnxt_re_srq,
1659 					       ib_srq);
1660 	struct bnxt_re_srq tsrq;
1661 	struct bnxt_re_dev *rdev = srq->rdev;
1662 	int rc;
1663 
1664 	/* Get live SRQ attr */
1665 	tsrq.qplib_srq.id = srq->qplib_srq.id;
1666 	rc = bnxt_qplib_query_srq(&rdev->qplib_res, &tsrq.qplib_srq);
1667 	if (rc) {
1668 		ibdev_err(&rdev->ibdev, "Query HW SRQ failed!");
1669 		return rc;
1670 	}
1671 	srq_attr->max_wr = srq->qplib_srq.max_wqe;
1672 	srq_attr->max_sge = srq->qplib_srq.max_sge;
1673 	srq_attr->srq_limit = tsrq.qplib_srq.threshold;
1674 
1675 	return 0;
1676 }
1677 
1678 int bnxt_re_post_srq_recv(struct ib_srq *ib_srq, const struct ib_recv_wr *wr,
1679 			  const struct ib_recv_wr **bad_wr)
1680 {
1681 	struct bnxt_re_srq *srq = container_of(ib_srq, struct bnxt_re_srq,
1682 					       ib_srq);
1683 	struct bnxt_qplib_swqe wqe;
1684 	unsigned long flags;
1685 	int rc = 0;
1686 
1687 	spin_lock_irqsave(&srq->lock, flags);
1688 	while (wr) {
1689 		/* Transcribe each ib_recv_wr to qplib_swqe */
1690 		wqe.num_sge = wr->num_sge;
1691 		bnxt_re_build_sgl(wr->sg_list, wqe.sg_list, wr->num_sge);
1692 		wqe.wr_id = wr->wr_id;
1693 		wqe.type = BNXT_QPLIB_SWQE_TYPE_RECV;
1694 
1695 		rc = bnxt_qplib_post_srq_recv(&srq->qplib_srq, &wqe);
1696 		if (rc) {
1697 			*bad_wr = wr;
1698 			break;
1699 		}
1700 		wr = wr->next;
1701 	}
1702 	spin_unlock_irqrestore(&srq->lock, flags);
1703 
1704 	return rc;
1705 }
1706 static int bnxt_re_modify_shadow_qp(struct bnxt_re_dev *rdev,
1707 				    struct bnxt_re_qp *qp1_qp,
1708 				    int qp_attr_mask)
1709 {
1710 	struct bnxt_re_qp *qp = rdev->gsi_ctx.gsi_sqp;
1711 	int rc = 0;
1712 
1713 	if (qp_attr_mask & IB_QP_STATE) {
1714 		qp->qplib_qp.modify_flags |= CMDQ_MODIFY_QP_MODIFY_MASK_STATE;
1715 		qp->qplib_qp.state = qp1_qp->qplib_qp.state;
1716 	}
1717 	if (qp_attr_mask & IB_QP_PKEY_INDEX) {
1718 		qp->qplib_qp.modify_flags |= CMDQ_MODIFY_QP_MODIFY_MASK_PKEY;
1719 		qp->qplib_qp.pkey_index = qp1_qp->qplib_qp.pkey_index;
1720 	}
1721 
1722 	if (qp_attr_mask & IB_QP_QKEY) {
1723 		qp->qplib_qp.modify_flags |= CMDQ_MODIFY_QP_MODIFY_MASK_QKEY;
1724 		/* Using a Random  QKEY */
1725 		qp->qplib_qp.qkey = 0x81818181;
1726 	}
1727 	if (qp_attr_mask & IB_QP_SQ_PSN) {
1728 		qp->qplib_qp.modify_flags |= CMDQ_MODIFY_QP_MODIFY_MASK_SQ_PSN;
1729 		qp->qplib_qp.sq.psn = qp1_qp->qplib_qp.sq.psn;
1730 	}
1731 
1732 	rc = bnxt_qplib_modify_qp(&rdev->qplib_res, &qp->qplib_qp);
1733 	if (rc)
1734 		ibdev_err(&rdev->ibdev, "Failed to modify Shadow QP for QP1");
1735 	return rc;
1736 }
1737 
1738 int bnxt_re_modify_qp(struct ib_qp *ib_qp, struct ib_qp_attr *qp_attr,
1739 		      int qp_attr_mask, struct ib_udata *udata)
1740 {
1741 	struct bnxt_re_qp *qp = container_of(ib_qp, struct bnxt_re_qp, ib_qp);
1742 	struct bnxt_re_dev *rdev = qp->rdev;
1743 	struct bnxt_qplib_dev_attr *dev_attr = &rdev->dev_attr;
1744 	enum ib_qp_state curr_qp_state, new_qp_state;
1745 	int rc, entries;
1746 	unsigned int flags;
1747 	u8 nw_type;
1748 
1749 	qp->qplib_qp.modify_flags = 0;
1750 	if (qp_attr_mask & IB_QP_STATE) {
1751 		curr_qp_state = __to_ib_qp_state(qp->qplib_qp.cur_qp_state);
1752 		new_qp_state = qp_attr->qp_state;
1753 		if (!ib_modify_qp_is_ok(curr_qp_state, new_qp_state,
1754 					ib_qp->qp_type, qp_attr_mask)) {
1755 			ibdev_err(&rdev->ibdev,
1756 				  "Invalid attribute mask: %#x specified ",
1757 				  qp_attr_mask);
1758 			ibdev_err(&rdev->ibdev,
1759 				  "for qpn: %#x type: %#x",
1760 				  ib_qp->qp_num, ib_qp->qp_type);
1761 			ibdev_err(&rdev->ibdev,
1762 				  "curr_qp_state=0x%x, new_qp_state=0x%x\n",
1763 				  curr_qp_state, new_qp_state);
1764 			return -EINVAL;
1765 		}
1766 		qp->qplib_qp.modify_flags |= CMDQ_MODIFY_QP_MODIFY_MASK_STATE;
1767 		qp->qplib_qp.state = __from_ib_qp_state(qp_attr->qp_state);
1768 
1769 		if (!qp->sumem &&
1770 		    qp->qplib_qp.state == CMDQ_MODIFY_QP_NEW_STATE_ERR) {
1771 			ibdev_dbg(&rdev->ibdev,
1772 				  "Move QP = %p to flush list\n", qp);
1773 			flags = bnxt_re_lock_cqs(qp);
1774 			bnxt_qplib_add_flush_qp(&qp->qplib_qp);
1775 			bnxt_re_unlock_cqs(qp, flags);
1776 		}
1777 		if (!qp->sumem &&
1778 		    qp->qplib_qp.state == CMDQ_MODIFY_QP_NEW_STATE_RESET) {
1779 			ibdev_dbg(&rdev->ibdev,
1780 				  "Move QP = %p out of flush list\n", qp);
1781 			flags = bnxt_re_lock_cqs(qp);
1782 			bnxt_qplib_clean_qp(&qp->qplib_qp);
1783 			bnxt_re_unlock_cqs(qp, flags);
1784 		}
1785 	}
1786 	if (qp_attr_mask & IB_QP_EN_SQD_ASYNC_NOTIFY) {
1787 		qp->qplib_qp.modify_flags |=
1788 				CMDQ_MODIFY_QP_MODIFY_MASK_EN_SQD_ASYNC_NOTIFY;
1789 		qp->qplib_qp.en_sqd_async_notify = true;
1790 	}
1791 	if (qp_attr_mask & IB_QP_ACCESS_FLAGS) {
1792 		qp->qplib_qp.modify_flags |= CMDQ_MODIFY_QP_MODIFY_MASK_ACCESS;
1793 		qp->qplib_qp.access =
1794 			__from_ib_access_flags(qp_attr->qp_access_flags);
1795 		/* LOCAL_WRITE access must be set to allow RC receive */
1796 		qp->qplib_qp.access |= BNXT_QPLIB_ACCESS_LOCAL_WRITE;
1797 		/* Temp: Set all params on QP as of now */
1798 		qp->qplib_qp.access |= CMDQ_MODIFY_QP_ACCESS_REMOTE_WRITE;
1799 		qp->qplib_qp.access |= CMDQ_MODIFY_QP_ACCESS_REMOTE_READ;
1800 	}
1801 	if (qp_attr_mask & IB_QP_PKEY_INDEX) {
1802 		qp->qplib_qp.modify_flags |= CMDQ_MODIFY_QP_MODIFY_MASK_PKEY;
1803 		qp->qplib_qp.pkey_index = qp_attr->pkey_index;
1804 	}
1805 	if (qp_attr_mask & IB_QP_QKEY) {
1806 		qp->qplib_qp.modify_flags |= CMDQ_MODIFY_QP_MODIFY_MASK_QKEY;
1807 		qp->qplib_qp.qkey = qp_attr->qkey;
1808 	}
1809 	if (qp_attr_mask & IB_QP_AV) {
1810 		const struct ib_global_route *grh =
1811 			rdma_ah_read_grh(&qp_attr->ah_attr);
1812 		const struct ib_gid_attr *sgid_attr;
1813 		struct bnxt_re_gid_ctx *ctx;
1814 
1815 		qp->qplib_qp.modify_flags |= CMDQ_MODIFY_QP_MODIFY_MASK_DGID |
1816 				     CMDQ_MODIFY_QP_MODIFY_MASK_FLOW_LABEL |
1817 				     CMDQ_MODIFY_QP_MODIFY_MASK_SGID_INDEX |
1818 				     CMDQ_MODIFY_QP_MODIFY_MASK_HOP_LIMIT |
1819 				     CMDQ_MODIFY_QP_MODIFY_MASK_TRAFFIC_CLASS |
1820 				     CMDQ_MODIFY_QP_MODIFY_MASK_DEST_MAC |
1821 				     CMDQ_MODIFY_QP_MODIFY_MASK_VLAN_ID;
1822 		memcpy(qp->qplib_qp.ah.dgid.data, grh->dgid.raw,
1823 		       sizeof(qp->qplib_qp.ah.dgid.data));
1824 		qp->qplib_qp.ah.flow_label = grh->flow_label;
1825 		sgid_attr = grh->sgid_attr;
1826 		/* Get the HW context of the GID. The reference
1827 		 * of GID table entry is already taken by the caller.
1828 		 */
1829 		ctx = rdma_read_gid_hw_context(sgid_attr);
1830 		qp->qplib_qp.ah.sgid_index = ctx->idx;
1831 		qp->qplib_qp.ah.host_sgid_index = grh->sgid_index;
1832 		qp->qplib_qp.ah.hop_limit = grh->hop_limit;
1833 		qp->qplib_qp.ah.traffic_class = grh->traffic_class;
1834 		qp->qplib_qp.ah.sl = rdma_ah_get_sl(&qp_attr->ah_attr);
1835 		ether_addr_copy(qp->qplib_qp.ah.dmac,
1836 				qp_attr->ah_attr.roce.dmac);
1837 
1838 		rc = rdma_read_gid_l2_fields(sgid_attr, NULL,
1839 					     &qp->qplib_qp.smac[0]);
1840 		if (rc)
1841 			return rc;
1842 
1843 		nw_type = rdma_gid_attr_network_type(sgid_attr);
1844 		switch (nw_type) {
1845 		case RDMA_NETWORK_IPV4:
1846 			qp->qplib_qp.nw_type =
1847 				CMDQ_MODIFY_QP_NETWORK_TYPE_ROCEV2_IPV4;
1848 			break;
1849 		case RDMA_NETWORK_IPV6:
1850 			qp->qplib_qp.nw_type =
1851 				CMDQ_MODIFY_QP_NETWORK_TYPE_ROCEV2_IPV6;
1852 			break;
1853 		default:
1854 			qp->qplib_qp.nw_type =
1855 				CMDQ_MODIFY_QP_NETWORK_TYPE_ROCEV1;
1856 			break;
1857 		}
1858 	}
1859 
1860 	if (qp_attr_mask & IB_QP_PATH_MTU) {
1861 		qp->qplib_qp.modify_flags |=
1862 				CMDQ_MODIFY_QP_MODIFY_MASK_PATH_MTU;
1863 		qp->qplib_qp.path_mtu = __from_ib_mtu(qp_attr->path_mtu);
1864 		qp->qplib_qp.mtu = ib_mtu_enum_to_int(qp_attr->path_mtu);
1865 	} else if (qp_attr->qp_state == IB_QPS_RTR) {
1866 		qp->qplib_qp.modify_flags |=
1867 			CMDQ_MODIFY_QP_MODIFY_MASK_PATH_MTU;
1868 		qp->qplib_qp.path_mtu =
1869 			__from_ib_mtu(iboe_get_mtu(rdev->netdev->mtu));
1870 		qp->qplib_qp.mtu =
1871 			ib_mtu_enum_to_int(iboe_get_mtu(rdev->netdev->mtu));
1872 	}
1873 
1874 	if (qp_attr_mask & IB_QP_TIMEOUT) {
1875 		qp->qplib_qp.modify_flags |= CMDQ_MODIFY_QP_MODIFY_MASK_TIMEOUT;
1876 		qp->qplib_qp.timeout = qp_attr->timeout;
1877 	}
1878 	if (qp_attr_mask & IB_QP_RETRY_CNT) {
1879 		qp->qplib_qp.modify_flags |=
1880 				CMDQ_MODIFY_QP_MODIFY_MASK_RETRY_CNT;
1881 		qp->qplib_qp.retry_cnt = qp_attr->retry_cnt;
1882 	}
1883 	if (qp_attr_mask & IB_QP_RNR_RETRY) {
1884 		qp->qplib_qp.modify_flags |=
1885 				CMDQ_MODIFY_QP_MODIFY_MASK_RNR_RETRY;
1886 		qp->qplib_qp.rnr_retry = qp_attr->rnr_retry;
1887 	}
1888 	if (qp_attr_mask & IB_QP_MIN_RNR_TIMER) {
1889 		qp->qplib_qp.modify_flags |=
1890 				CMDQ_MODIFY_QP_MODIFY_MASK_MIN_RNR_TIMER;
1891 		qp->qplib_qp.min_rnr_timer = qp_attr->min_rnr_timer;
1892 	}
1893 	if (qp_attr_mask & IB_QP_RQ_PSN) {
1894 		qp->qplib_qp.modify_flags |= CMDQ_MODIFY_QP_MODIFY_MASK_RQ_PSN;
1895 		qp->qplib_qp.rq.psn = qp_attr->rq_psn;
1896 	}
1897 	if (qp_attr_mask & IB_QP_MAX_QP_RD_ATOMIC) {
1898 		qp->qplib_qp.modify_flags |=
1899 				CMDQ_MODIFY_QP_MODIFY_MASK_MAX_RD_ATOMIC;
1900 		/* Cap the max_rd_atomic to device max */
1901 		qp->qplib_qp.max_rd_atomic = min_t(u32, qp_attr->max_rd_atomic,
1902 						   dev_attr->max_qp_rd_atom);
1903 	}
1904 	if (qp_attr_mask & IB_QP_SQ_PSN) {
1905 		qp->qplib_qp.modify_flags |= CMDQ_MODIFY_QP_MODIFY_MASK_SQ_PSN;
1906 		qp->qplib_qp.sq.psn = qp_attr->sq_psn;
1907 	}
1908 	if (qp_attr_mask & IB_QP_MAX_DEST_RD_ATOMIC) {
1909 		if (qp_attr->max_dest_rd_atomic >
1910 		    dev_attr->max_qp_init_rd_atom) {
1911 			ibdev_err(&rdev->ibdev,
1912 				  "max_dest_rd_atomic requested%d is > dev_max%d",
1913 				  qp_attr->max_dest_rd_atomic,
1914 				  dev_attr->max_qp_init_rd_atom);
1915 			return -EINVAL;
1916 		}
1917 
1918 		qp->qplib_qp.modify_flags |=
1919 				CMDQ_MODIFY_QP_MODIFY_MASK_MAX_DEST_RD_ATOMIC;
1920 		qp->qplib_qp.max_dest_rd_atomic = qp_attr->max_dest_rd_atomic;
1921 	}
1922 	if (qp_attr_mask & IB_QP_CAP) {
1923 		qp->qplib_qp.modify_flags |=
1924 				CMDQ_MODIFY_QP_MODIFY_MASK_SQ_SIZE |
1925 				CMDQ_MODIFY_QP_MODIFY_MASK_RQ_SIZE |
1926 				CMDQ_MODIFY_QP_MODIFY_MASK_SQ_SGE |
1927 				CMDQ_MODIFY_QP_MODIFY_MASK_RQ_SGE |
1928 				CMDQ_MODIFY_QP_MODIFY_MASK_MAX_INLINE_DATA;
1929 		if ((qp_attr->cap.max_send_wr >= dev_attr->max_qp_wqes) ||
1930 		    (qp_attr->cap.max_recv_wr >= dev_attr->max_qp_wqes) ||
1931 		    (qp_attr->cap.max_send_sge >= dev_attr->max_qp_sges) ||
1932 		    (qp_attr->cap.max_recv_sge >= dev_attr->max_qp_sges) ||
1933 		    (qp_attr->cap.max_inline_data >=
1934 						dev_attr->max_inline_data)) {
1935 			ibdev_err(&rdev->ibdev,
1936 				  "Create QP failed - max exceeded");
1937 			return -EINVAL;
1938 		}
1939 		entries = roundup_pow_of_two(qp_attr->cap.max_send_wr);
1940 		qp->qplib_qp.sq.max_wqe = min_t(u32, entries,
1941 						dev_attr->max_qp_wqes + 1);
1942 		qp->qplib_qp.sq.q_full_delta = qp->qplib_qp.sq.max_wqe -
1943 						qp_attr->cap.max_send_wr;
1944 		/*
1945 		 * Reserving one slot for Phantom WQE. Some application can
1946 		 * post one extra entry in this case. Allowing this to avoid
1947 		 * unexpected Queue full condition
1948 		 */
1949 		qp->qplib_qp.sq.q_full_delta -= 1;
1950 		qp->qplib_qp.sq.max_sge = qp_attr->cap.max_send_sge;
1951 		if (qp->qplib_qp.rq.max_wqe) {
1952 			entries = roundup_pow_of_two(qp_attr->cap.max_recv_wr);
1953 			qp->qplib_qp.rq.max_wqe =
1954 				min_t(u32, entries, dev_attr->max_qp_wqes + 1);
1955 			qp->qplib_qp.rq.q_full_delta = qp->qplib_qp.rq.max_wqe -
1956 						       qp_attr->cap.max_recv_wr;
1957 			qp->qplib_qp.rq.max_sge = qp_attr->cap.max_recv_sge;
1958 		} else {
1959 			/* SRQ was used prior, just ignore the RQ caps */
1960 		}
1961 	}
1962 	if (qp_attr_mask & IB_QP_DEST_QPN) {
1963 		qp->qplib_qp.modify_flags |=
1964 				CMDQ_MODIFY_QP_MODIFY_MASK_DEST_QP_ID;
1965 		qp->qplib_qp.dest_qpn = qp_attr->dest_qp_num;
1966 	}
1967 	rc = bnxt_qplib_modify_qp(&rdev->qplib_res, &qp->qplib_qp);
1968 	if (rc) {
1969 		ibdev_err(&rdev->ibdev, "Failed to modify HW QP");
1970 		return rc;
1971 	}
1972 	if (ib_qp->qp_type == IB_QPT_GSI && rdev->gsi_ctx.gsi_sqp)
1973 		rc = bnxt_re_modify_shadow_qp(rdev, qp, qp_attr_mask);
1974 	return rc;
1975 }
1976 
1977 int bnxt_re_query_qp(struct ib_qp *ib_qp, struct ib_qp_attr *qp_attr,
1978 		     int qp_attr_mask, struct ib_qp_init_attr *qp_init_attr)
1979 {
1980 	struct bnxt_re_qp *qp = container_of(ib_qp, struct bnxt_re_qp, ib_qp);
1981 	struct bnxt_re_dev *rdev = qp->rdev;
1982 	struct bnxt_qplib_qp *qplib_qp;
1983 	int rc;
1984 
1985 	qplib_qp = kzalloc(sizeof(*qplib_qp), GFP_KERNEL);
1986 	if (!qplib_qp)
1987 		return -ENOMEM;
1988 
1989 	qplib_qp->id = qp->qplib_qp.id;
1990 	qplib_qp->ah.host_sgid_index = qp->qplib_qp.ah.host_sgid_index;
1991 
1992 	rc = bnxt_qplib_query_qp(&rdev->qplib_res, qplib_qp);
1993 	if (rc) {
1994 		ibdev_err(&rdev->ibdev, "Failed to query HW QP");
1995 		goto out;
1996 	}
1997 	qp_attr->qp_state = __to_ib_qp_state(qplib_qp->state);
1998 	qp_attr->en_sqd_async_notify = qplib_qp->en_sqd_async_notify ? 1 : 0;
1999 	qp_attr->qp_access_flags = __to_ib_access_flags(qplib_qp->access);
2000 	qp_attr->pkey_index = qplib_qp->pkey_index;
2001 	qp_attr->qkey = qplib_qp->qkey;
2002 	qp_attr->ah_attr.type = RDMA_AH_ATTR_TYPE_ROCE;
2003 	rdma_ah_set_grh(&qp_attr->ah_attr, NULL, qplib_qp->ah.flow_label,
2004 			qplib_qp->ah.host_sgid_index,
2005 			qplib_qp->ah.hop_limit,
2006 			qplib_qp->ah.traffic_class);
2007 	rdma_ah_set_dgid_raw(&qp_attr->ah_attr, qplib_qp->ah.dgid.data);
2008 	rdma_ah_set_sl(&qp_attr->ah_attr, qplib_qp->ah.sl);
2009 	ether_addr_copy(qp_attr->ah_attr.roce.dmac, qplib_qp->ah.dmac);
2010 	qp_attr->path_mtu = __to_ib_mtu(qplib_qp->path_mtu);
2011 	qp_attr->timeout = qplib_qp->timeout;
2012 	qp_attr->retry_cnt = qplib_qp->retry_cnt;
2013 	qp_attr->rnr_retry = qplib_qp->rnr_retry;
2014 	qp_attr->min_rnr_timer = qplib_qp->min_rnr_timer;
2015 	qp_attr->rq_psn = qplib_qp->rq.psn;
2016 	qp_attr->max_rd_atomic = qplib_qp->max_rd_atomic;
2017 	qp_attr->sq_psn = qplib_qp->sq.psn;
2018 	qp_attr->max_dest_rd_atomic = qplib_qp->max_dest_rd_atomic;
2019 	qp_init_attr->sq_sig_type = qplib_qp->sig_type ? IB_SIGNAL_ALL_WR :
2020 							 IB_SIGNAL_REQ_WR;
2021 	qp_attr->dest_qp_num = qplib_qp->dest_qpn;
2022 
2023 	qp_attr->cap.max_send_wr = qp->qplib_qp.sq.max_wqe;
2024 	qp_attr->cap.max_send_sge = qp->qplib_qp.sq.max_sge;
2025 	qp_attr->cap.max_recv_wr = qp->qplib_qp.rq.max_wqe;
2026 	qp_attr->cap.max_recv_sge = qp->qplib_qp.rq.max_sge;
2027 	qp_attr->cap.max_inline_data = qp->qplib_qp.max_inline_data;
2028 	qp_init_attr->cap = qp_attr->cap;
2029 
2030 out:
2031 	kfree(qplib_qp);
2032 	return rc;
2033 }
2034 
2035 /* Routine for sending QP1 packets for RoCE V1 an V2
2036  */
2037 static int bnxt_re_build_qp1_send_v2(struct bnxt_re_qp *qp,
2038 				     const struct ib_send_wr *wr,
2039 				     struct bnxt_qplib_swqe *wqe,
2040 				     int payload_size)
2041 {
2042 	struct bnxt_re_ah *ah = container_of(ud_wr(wr)->ah, struct bnxt_re_ah,
2043 					     ib_ah);
2044 	struct bnxt_qplib_ah *qplib_ah = &ah->qplib_ah;
2045 	const struct ib_gid_attr *sgid_attr = ah->ib_ah.sgid_attr;
2046 	struct bnxt_qplib_sge sge;
2047 	u8 nw_type;
2048 	u16 ether_type;
2049 	union ib_gid dgid;
2050 	bool is_eth = false;
2051 	bool is_vlan = false;
2052 	bool is_grh = false;
2053 	bool is_udp = false;
2054 	u8 ip_version = 0;
2055 	u16 vlan_id = 0xFFFF;
2056 	void *buf;
2057 	int i, rc = 0;
2058 
2059 	memset(&qp->qp1_hdr, 0, sizeof(qp->qp1_hdr));
2060 
2061 	rc = rdma_read_gid_l2_fields(sgid_attr, &vlan_id, NULL);
2062 	if (rc)
2063 		return rc;
2064 
2065 	/* Get network header type for this GID */
2066 	nw_type = rdma_gid_attr_network_type(sgid_attr);
2067 	switch (nw_type) {
2068 	case RDMA_NETWORK_IPV4:
2069 		nw_type = BNXT_RE_ROCEV2_IPV4_PACKET;
2070 		break;
2071 	case RDMA_NETWORK_IPV6:
2072 		nw_type = BNXT_RE_ROCEV2_IPV6_PACKET;
2073 		break;
2074 	default:
2075 		nw_type = BNXT_RE_ROCE_V1_PACKET;
2076 		break;
2077 	}
2078 	memcpy(&dgid.raw, &qplib_ah->dgid, 16);
2079 	is_udp = sgid_attr->gid_type == IB_GID_TYPE_ROCE_UDP_ENCAP;
2080 	if (is_udp) {
2081 		if (ipv6_addr_v4mapped((struct in6_addr *)&sgid_attr->gid)) {
2082 			ip_version = 4;
2083 			ether_type = ETH_P_IP;
2084 		} else {
2085 			ip_version = 6;
2086 			ether_type = ETH_P_IPV6;
2087 		}
2088 		is_grh = false;
2089 	} else {
2090 		ether_type = ETH_P_IBOE;
2091 		is_grh = true;
2092 	}
2093 
2094 	is_eth = true;
2095 	is_vlan = (vlan_id && (vlan_id < 0x1000)) ? true : false;
2096 
2097 	ib_ud_header_init(payload_size, !is_eth, is_eth, is_vlan, is_grh,
2098 			  ip_version, is_udp, 0, &qp->qp1_hdr);
2099 
2100 	/* ETH */
2101 	ether_addr_copy(qp->qp1_hdr.eth.dmac_h, ah->qplib_ah.dmac);
2102 	ether_addr_copy(qp->qp1_hdr.eth.smac_h, qp->qplib_qp.smac);
2103 
2104 	/* For vlan, check the sgid for vlan existence */
2105 
2106 	if (!is_vlan) {
2107 		qp->qp1_hdr.eth.type = cpu_to_be16(ether_type);
2108 	} else {
2109 		qp->qp1_hdr.vlan.type = cpu_to_be16(ether_type);
2110 		qp->qp1_hdr.vlan.tag = cpu_to_be16(vlan_id);
2111 	}
2112 
2113 	if (is_grh || (ip_version == 6)) {
2114 		memcpy(qp->qp1_hdr.grh.source_gid.raw, sgid_attr->gid.raw,
2115 		       sizeof(sgid_attr->gid));
2116 		memcpy(qp->qp1_hdr.grh.destination_gid.raw, qplib_ah->dgid.data,
2117 		       sizeof(sgid_attr->gid));
2118 		qp->qp1_hdr.grh.hop_limit     = qplib_ah->hop_limit;
2119 	}
2120 
2121 	if (ip_version == 4) {
2122 		qp->qp1_hdr.ip4.tos = 0;
2123 		qp->qp1_hdr.ip4.id = 0;
2124 		qp->qp1_hdr.ip4.frag_off = htons(IP_DF);
2125 		qp->qp1_hdr.ip4.ttl = qplib_ah->hop_limit;
2126 
2127 		memcpy(&qp->qp1_hdr.ip4.saddr, sgid_attr->gid.raw + 12, 4);
2128 		memcpy(&qp->qp1_hdr.ip4.daddr, qplib_ah->dgid.data + 12, 4);
2129 		qp->qp1_hdr.ip4.check = ib_ud_ip4_csum(&qp->qp1_hdr);
2130 	}
2131 
2132 	if (is_udp) {
2133 		qp->qp1_hdr.udp.dport = htons(ROCE_V2_UDP_DPORT);
2134 		qp->qp1_hdr.udp.sport = htons(0x8CD1);
2135 		qp->qp1_hdr.udp.csum = 0;
2136 	}
2137 
2138 	/* BTH */
2139 	if (wr->opcode == IB_WR_SEND_WITH_IMM) {
2140 		qp->qp1_hdr.bth.opcode = IB_OPCODE_UD_SEND_ONLY_WITH_IMMEDIATE;
2141 		qp->qp1_hdr.immediate_present = 1;
2142 	} else {
2143 		qp->qp1_hdr.bth.opcode = IB_OPCODE_UD_SEND_ONLY;
2144 	}
2145 	if (wr->send_flags & IB_SEND_SOLICITED)
2146 		qp->qp1_hdr.bth.solicited_event = 1;
2147 	/* pad_count */
2148 	qp->qp1_hdr.bth.pad_count = (4 - payload_size) & 3;
2149 
2150 	/* P_key for QP1 is for all members */
2151 	qp->qp1_hdr.bth.pkey = cpu_to_be16(0xFFFF);
2152 	qp->qp1_hdr.bth.destination_qpn = IB_QP1;
2153 	qp->qp1_hdr.bth.ack_req = 0;
2154 	qp->send_psn++;
2155 	qp->send_psn &= BTH_PSN_MASK;
2156 	qp->qp1_hdr.bth.psn = cpu_to_be32(qp->send_psn);
2157 	/* DETH */
2158 	/* Use the priviledged Q_Key for QP1 */
2159 	qp->qp1_hdr.deth.qkey = cpu_to_be32(IB_QP1_QKEY);
2160 	qp->qp1_hdr.deth.source_qpn = IB_QP1;
2161 
2162 	/* Pack the QP1 to the transmit buffer */
2163 	buf = bnxt_qplib_get_qp1_sq_buf(&qp->qplib_qp, &sge);
2164 	if (buf) {
2165 		ib_ud_header_pack(&qp->qp1_hdr, buf);
2166 		for (i = wqe->num_sge; i; i--) {
2167 			wqe->sg_list[i].addr = wqe->sg_list[i - 1].addr;
2168 			wqe->sg_list[i].lkey = wqe->sg_list[i - 1].lkey;
2169 			wqe->sg_list[i].size = wqe->sg_list[i - 1].size;
2170 		}
2171 
2172 		/*
2173 		 * Max Header buf size for IPV6 RoCE V2 is 86,
2174 		 * which is same as the QP1 SQ header buffer.
2175 		 * Header buf size for IPV4 RoCE V2 can be 66.
2176 		 * ETH(14) + VLAN(4)+ IP(20) + UDP (8) + BTH(20).
2177 		 * Subtract 20 bytes from QP1 SQ header buf size
2178 		 */
2179 		if (is_udp && ip_version == 4)
2180 			sge.size -= 20;
2181 		/*
2182 		 * Max Header buf size for RoCE V1 is 78.
2183 		 * ETH(14) + VLAN(4) + GRH(40) + BTH(20).
2184 		 * Subtract 8 bytes from QP1 SQ header buf size
2185 		 */
2186 		if (!is_udp)
2187 			sge.size -= 8;
2188 
2189 		/* Subtract 4 bytes for non vlan packets */
2190 		if (!is_vlan)
2191 			sge.size -= 4;
2192 
2193 		wqe->sg_list[0].addr = sge.addr;
2194 		wqe->sg_list[0].lkey = sge.lkey;
2195 		wqe->sg_list[0].size = sge.size;
2196 		wqe->num_sge++;
2197 
2198 	} else {
2199 		ibdev_err(&qp->rdev->ibdev, "QP1 buffer is empty!");
2200 		rc = -ENOMEM;
2201 	}
2202 	return rc;
2203 }
2204 
2205 /* For the MAD layer, it only provides the recv SGE the size of
2206  * ib_grh + MAD datagram.  No Ethernet headers, Ethertype, BTH, DETH,
2207  * nor RoCE iCRC.  The Cu+ solution must provide buffer for the entire
2208  * receive packet (334 bytes) with no VLAN and then copy the GRH
2209  * and the MAD datagram out to the provided SGE.
2210  */
2211 static int bnxt_re_build_qp1_shadow_qp_recv(struct bnxt_re_qp *qp,
2212 					    const struct ib_recv_wr *wr,
2213 					    struct bnxt_qplib_swqe *wqe,
2214 					    int payload_size)
2215 {
2216 	struct bnxt_re_sqp_entries *sqp_entry;
2217 	struct bnxt_qplib_sge ref, sge;
2218 	struct bnxt_re_dev *rdev;
2219 	u32 rq_prod_index;
2220 
2221 	rdev = qp->rdev;
2222 
2223 	rq_prod_index = bnxt_qplib_get_rq_prod_index(&qp->qplib_qp);
2224 
2225 	if (!bnxt_qplib_get_qp1_rq_buf(&qp->qplib_qp, &sge))
2226 		return -ENOMEM;
2227 
2228 	/* Create 1 SGE to receive the entire
2229 	 * ethernet packet
2230 	 */
2231 	/* Save the reference from ULP */
2232 	ref.addr = wqe->sg_list[0].addr;
2233 	ref.lkey = wqe->sg_list[0].lkey;
2234 	ref.size = wqe->sg_list[0].size;
2235 
2236 	sqp_entry = &rdev->gsi_ctx.sqp_tbl[rq_prod_index];
2237 
2238 	/* SGE 1 */
2239 	wqe->sg_list[0].addr = sge.addr;
2240 	wqe->sg_list[0].lkey = sge.lkey;
2241 	wqe->sg_list[0].size = BNXT_QPLIB_MAX_QP1_RQ_HDR_SIZE_V2;
2242 	sge.size -= wqe->sg_list[0].size;
2243 
2244 	sqp_entry->sge.addr = ref.addr;
2245 	sqp_entry->sge.lkey = ref.lkey;
2246 	sqp_entry->sge.size = ref.size;
2247 	/* Store the wrid for reporting completion */
2248 	sqp_entry->wrid = wqe->wr_id;
2249 	/* change the wqe->wrid to table index */
2250 	wqe->wr_id = rq_prod_index;
2251 	return 0;
2252 }
2253 
2254 static int is_ud_qp(struct bnxt_re_qp *qp)
2255 {
2256 	return (qp->qplib_qp.type == CMDQ_CREATE_QP_TYPE_UD ||
2257 		qp->qplib_qp.type == CMDQ_CREATE_QP_TYPE_GSI);
2258 }
2259 
2260 static int bnxt_re_build_send_wqe(struct bnxt_re_qp *qp,
2261 				  const struct ib_send_wr *wr,
2262 				  struct bnxt_qplib_swqe *wqe)
2263 {
2264 	struct bnxt_re_ah *ah = NULL;
2265 
2266 	if (is_ud_qp(qp)) {
2267 		ah = container_of(ud_wr(wr)->ah, struct bnxt_re_ah, ib_ah);
2268 		wqe->send.q_key = ud_wr(wr)->remote_qkey;
2269 		wqe->send.dst_qp = ud_wr(wr)->remote_qpn;
2270 		wqe->send.avid = ah->qplib_ah.id;
2271 	}
2272 	switch (wr->opcode) {
2273 	case IB_WR_SEND:
2274 		wqe->type = BNXT_QPLIB_SWQE_TYPE_SEND;
2275 		break;
2276 	case IB_WR_SEND_WITH_IMM:
2277 		wqe->type = BNXT_QPLIB_SWQE_TYPE_SEND_WITH_IMM;
2278 		wqe->send.imm_data = wr->ex.imm_data;
2279 		break;
2280 	case IB_WR_SEND_WITH_INV:
2281 		wqe->type = BNXT_QPLIB_SWQE_TYPE_SEND_WITH_INV;
2282 		wqe->send.inv_key = wr->ex.invalidate_rkey;
2283 		break;
2284 	default:
2285 		return -EINVAL;
2286 	}
2287 	if (wr->send_flags & IB_SEND_SIGNALED)
2288 		wqe->flags |= BNXT_QPLIB_SWQE_FLAGS_SIGNAL_COMP;
2289 	if (wr->send_flags & IB_SEND_FENCE)
2290 		wqe->flags |= BNXT_QPLIB_SWQE_FLAGS_UC_FENCE;
2291 	if (wr->send_flags & IB_SEND_SOLICITED)
2292 		wqe->flags |= BNXT_QPLIB_SWQE_FLAGS_SOLICIT_EVENT;
2293 	if (wr->send_flags & IB_SEND_INLINE)
2294 		wqe->flags |= BNXT_QPLIB_SWQE_FLAGS_INLINE;
2295 
2296 	return 0;
2297 }
2298 
2299 static int bnxt_re_build_rdma_wqe(const struct ib_send_wr *wr,
2300 				  struct bnxt_qplib_swqe *wqe)
2301 {
2302 	switch (wr->opcode) {
2303 	case IB_WR_RDMA_WRITE:
2304 		wqe->type = BNXT_QPLIB_SWQE_TYPE_RDMA_WRITE;
2305 		break;
2306 	case IB_WR_RDMA_WRITE_WITH_IMM:
2307 		wqe->type = BNXT_QPLIB_SWQE_TYPE_RDMA_WRITE_WITH_IMM;
2308 		wqe->rdma.imm_data = wr->ex.imm_data;
2309 		break;
2310 	case IB_WR_RDMA_READ:
2311 		wqe->type = BNXT_QPLIB_SWQE_TYPE_RDMA_READ;
2312 		wqe->rdma.inv_key = wr->ex.invalidate_rkey;
2313 		break;
2314 	default:
2315 		return -EINVAL;
2316 	}
2317 	wqe->rdma.remote_va = rdma_wr(wr)->remote_addr;
2318 	wqe->rdma.r_key = rdma_wr(wr)->rkey;
2319 	if (wr->send_flags & IB_SEND_SIGNALED)
2320 		wqe->flags |= BNXT_QPLIB_SWQE_FLAGS_SIGNAL_COMP;
2321 	if (wr->send_flags & IB_SEND_FENCE)
2322 		wqe->flags |= BNXT_QPLIB_SWQE_FLAGS_UC_FENCE;
2323 	if (wr->send_flags & IB_SEND_SOLICITED)
2324 		wqe->flags |= BNXT_QPLIB_SWQE_FLAGS_SOLICIT_EVENT;
2325 	if (wr->send_flags & IB_SEND_INLINE)
2326 		wqe->flags |= BNXT_QPLIB_SWQE_FLAGS_INLINE;
2327 
2328 	return 0;
2329 }
2330 
2331 static int bnxt_re_build_atomic_wqe(const struct ib_send_wr *wr,
2332 				    struct bnxt_qplib_swqe *wqe)
2333 {
2334 	switch (wr->opcode) {
2335 	case IB_WR_ATOMIC_CMP_AND_SWP:
2336 		wqe->type = BNXT_QPLIB_SWQE_TYPE_ATOMIC_CMP_AND_SWP;
2337 		wqe->atomic.cmp_data = atomic_wr(wr)->compare_add;
2338 		wqe->atomic.swap_data = atomic_wr(wr)->swap;
2339 		break;
2340 	case IB_WR_ATOMIC_FETCH_AND_ADD:
2341 		wqe->type = BNXT_QPLIB_SWQE_TYPE_ATOMIC_FETCH_AND_ADD;
2342 		wqe->atomic.cmp_data = atomic_wr(wr)->compare_add;
2343 		break;
2344 	default:
2345 		return -EINVAL;
2346 	}
2347 	wqe->atomic.remote_va = atomic_wr(wr)->remote_addr;
2348 	wqe->atomic.r_key = atomic_wr(wr)->rkey;
2349 	if (wr->send_flags & IB_SEND_SIGNALED)
2350 		wqe->flags |= BNXT_QPLIB_SWQE_FLAGS_SIGNAL_COMP;
2351 	if (wr->send_flags & IB_SEND_FENCE)
2352 		wqe->flags |= BNXT_QPLIB_SWQE_FLAGS_UC_FENCE;
2353 	if (wr->send_flags & IB_SEND_SOLICITED)
2354 		wqe->flags |= BNXT_QPLIB_SWQE_FLAGS_SOLICIT_EVENT;
2355 	return 0;
2356 }
2357 
2358 static int bnxt_re_build_inv_wqe(const struct ib_send_wr *wr,
2359 				 struct bnxt_qplib_swqe *wqe)
2360 {
2361 	wqe->type = BNXT_QPLIB_SWQE_TYPE_LOCAL_INV;
2362 	wqe->local_inv.inv_l_key = wr->ex.invalidate_rkey;
2363 
2364 	/* Need unconditional fence for local invalidate
2365 	 * opcode to work as expected.
2366 	 */
2367 	wqe->flags |= BNXT_QPLIB_SWQE_FLAGS_UC_FENCE;
2368 
2369 	if (wr->send_flags & IB_SEND_SIGNALED)
2370 		wqe->flags |= BNXT_QPLIB_SWQE_FLAGS_SIGNAL_COMP;
2371 	if (wr->send_flags & IB_SEND_SOLICITED)
2372 		wqe->flags |= BNXT_QPLIB_SWQE_FLAGS_SOLICIT_EVENT;
2373 
2374 	return 0;
2375 }
2376 
2377 static int bnxt_re_build_reg_wqe(const struct ib_reg_wr *wr,
2378 				 struct bnxt_qplib_swqe *wqe)
2379 {
2380 	struct bnxt_re_mr *mr = container_of(wr->mr, struct bnxt_re_mr, ib_mr);
2381 	struct bnxt_qplib_frpl *qplib_frpl = &mr->qplib_frpl;
2382 	int access = wr->access;
2383 
2384 	wqe->frmr.pbl_ptr = (__le64 *)qplib_frpl->hwq.pbl_ptr[0];
2385 	wqe->frmr.pbl_dma_ptr = qplib_frpl->hwq.pbl_dma_ptr[0];
2386 	wqe->frmr.page_list = mr->pages;
2387 	wqe->frmr.page_list_len = mr->npages;
2388 	wqe->frmr.levels = qplib_frpl->hwq.level;
2389 	wqe->type = BNXT_QPLIB_SWQE_TYPE_REG_MR;
2390 
2391 	/* Need unconditional fence for reg_mr
2392 	 * opcode to function as expected.
2393 	 */
2394 
2395 	wqe->flags |= BNXT_QPLIB_SWQE_FLAGS_UC_FENCE;
2396 
2397 	if (wr->wr.send_flags & IB_SEND_SIGNALED)
2398 		wqe->flags |= BNXT_QPLIB_SWQE_FLAGS_SIGNAL_COMP;
2399 
2400 	if (access & IB_ACCESS_LOCAL_WRITE)
2401 		wqe->frmr.access_cntl |= SQ_FR_PMR_ACCESS_CNTL_LOCAL_WRITE;
2402 	if (access & IB_ACCESS_REMOTE_READ)
2403 		wqe->frmr.access_cntl |= SQ_FR_PMR_ACCESS_CNTL_REMOTE_READ;
2404 	if (access & IB_ACCESS_REMOTE_WRITE)
2405 		wqe->frmr.access_cntl |= SQ_FR_PMR_ACCESS_CNTL_REMOTE_WRITE;
2406 	if (access & IB_ACCESS_REMOTE_ATOMIC)
2407 		wqe->frmr.access_cntl |= SQ_FR_PMR_ACCESS_CNTL_REMOTE_ATOMIC;
2408 	if (access & IB_ACCESS_MW_BIND)
2409 		wqe->frmr.access_cntl |= SQ_FR_PMR_ACCESS_CNTL_WINDOW_BIND;
2410 
2411 	wqe->frmr.l_key = wr->key;
2412 	wqe->frmr.length = wr->mr->length;
2413 	wqe->frmr.pbl_pg_sz_log = (wr->mr->page_size >> PAGE_SHIFT_4K) - 1;
2414 	wqe->frmr.va = wr->mr->iova;
2415 	return 0;
2416 }
2417 
2418 static int bnxt_re_copy_inline_data(struct bnxt_re_dev *rdev,
2419 				    const struct ib_send_wr *wr,
2420 				    struct bnxt_qplib_swqe *wqe)
2421 {
2422 	/*  Copy the inline data to the data  field */
2423 	u8 *in_data;
2424 	u32 i, sge_len;
2425 	void *sge_addr;
2426 
2427 	in_data = wqe->inline_data;
2428 	for (i = 0; i < wr->num_sge; i++) {
2429 		sge_addr = (void *)(unsigned long)
2430 				wr->sg_list[i].addr;
2431 		sge_len = wr->sg_list[i].length;
2432 
2433 		if ((sge_len + wqe->inline_len) >
2434 		    BNXT_QPLIB_SWQE_MAX_INLINE_LENGTH) {
2435 			ibdev_err(&rdev->ibdev,
2436 				  "Inline data size requested > supported value");
2437 			return -EINVAL;
2438 		}
2439 		sge_len = wr->sg_list[i].length;
2440 
2441 		memcpy(in_data, sge_addr, sge_len);
2442 		in_data += wr->sg_list[i].length;
2443 		wqe->inline_len += wr->sg_list[i].length;
2444 	}
2445 	return wqe->inline_len;
2446 }
2447 
2448 static int bnxt_re_copy_wr_payload(struct bnxt_re_dev *rdev,
2449 				   const struct ib_send_wr *wr,
2450 				   struct bnxt_qplib_swqe *wqe)
2451 {
2452 	int payload_sz = 0;
2453 
2454 	if (wr->send_flags & IB_SEND_INLINE)
2455 		payload_sz = bnxt_re_copy_inline_data(rdev, wr, wqe);
2456 	else
2457 		payload_sz = bnxt_re_build_sgl(wr->sg_list, wqe->sg_list,
2458 					       wqe->num_sge);
2459 
2460 	return payload_sz;
2461 }
2462 
2463 static void bnxt_ud_qp_hw_stall_workaround(struct bnxt_re_qp *qp)
2464 {
2465 	if ((qp->ib_qp.qp_type == IB_QPT_UD ||
2466 	     qp->ib_qp.qp_type == IB_QPT_GSI ||
2467 	     qp->ib_qp.qp_type == IB_QPT_RAW_ETHERTYPE) &&
2468 	     qp->qplib_qp.wqe_cnt == BNXT_RE_UD_QP_HW_STALL) {
2469 		int qp_attr_mask;
2470 		struct ib_qp_attr qp_attr;
2471 
2472 		qp_attr_mask = IB_QP_STATE;
2473 		qp_attr.qp_state = IB_QPS_RTS;
2474 		bnxt_re_modify_qp(&qp->ib_qp, &qp_attr, qp_attr_mask, NULL);
2475 		qp->qplib_qp.wqe_cnt = 0;
2476 	}
2477 }
2478 
2479 static int bnxt_re_post_send_shadow_qp(struct bnxt_re_dev *rdev,
2480 				       struct bnxt_re_qp *qp,
2481 				       const struct ib_send_wr *wr)
2482 {
2483 	int rc = 0, payload_sz = 0;
2484 	unsigned long flags;
2485 
2486 	spin_lock_irqsave(&qp->sq_lock, flags);
2487 	while (wr) {
2488 		struct bnxt_qplib_swqe wqe = {};
2489 
2490 		/* Common */
2491 		wqe.num_sge = wr->num_sge;
2492 		if (wr->num_sge > qp->qplib_qp.sq.max_sge) {
2493 			ibdev_err(&rdev->ibdev,
2494 				  "Limit exceeded for Send SGEs");
2495 			rc = -EINVAL;
2496 			goto bad;
2497 		}
2498 
2499 		payload_sz = bnxt_re_copy_wr_payload(qp->rdev, wr, &wqe);
2500 		if (payload_sz < 0) {
2501 			rc = -EINVAL;
2502 			goto bad;
2503 		}
2504 		wqe.wr_id = wr->wr_id;
2505 
2506 		wqe.type = BNXT_QPLIB_SWQE_TYPE_SEND;
2507 
2508 		rc = bnxt_re_build_send_wqe(qp, wr, &wqe);
2509 		if (!rc)
2510 			rc = bnxt_qplib_post_send(&qp->qplib_qp, &wqe);
2511 bad:
2512 		if (rc) {
2513 			ibdev_err(&rdev->ibdev,
2514 				  "Post send failed opcode = %#x rc = %d",
2515 				  wr->opcode, rc);
2516 			break;
2517 		}
2518 		wr = wr->next;
2519 	}
2520 	bnxt_qplib_post_send_db(&qp->qplib_qp);
2521 	bnxt_ud_qp_hw_stall_workaround(qp);
2522 	spin_unlock_irqrestore(&qp->sq_lock, flags);
2523 	return rc;
2524 }
2525 
2526 int bnxt_re_post_send(struct ib_qp *ib_qp, const struct ib_send_wr *wr,
2527 		      const struct ib_send_wr **bad_wr)
2528 {
2529 	struct bnxt_re_qp *qp = container_of(ib_qp, struct bnxt_re_qp, ib_qp);
2530 	struct bnxt_qplib_swqe wqe;
2531 	int rc = 0, payload_sz = 0;
2532 	unsigned long flags;
2533 
2534 	spin_lock_irqsave(&qp->sq_lock, flags);
2535 	while (wr) {
2536 		/* House keeping */
2537 		memset(&wqe, 0, sizeof(wqe));
2538 
2539 		/* Common */
2540 		wqe.num_sge = wr->num_sge;
2541 		if (wr->num_sge > qp->qplib_qp.sq.max_sge) {
2542 			ibdev_err(&qp->rdev->ibdev,
2543 				  "Limit exceeded for Send SGEs");
2544 			rc = -EINVAL;
2545 			goto bad;
2546 		}
2547 
2548 		payload_sz = bnxt_re_copy_wr_payload(qp->rdev, wr, &wqe);
2549 		if (payload_sz < 0) {
2550 			rc = -EINVAL;
2551 			goto bad;
2552 		}
2553 		wqe.wr_id = wr->wr_id;
2554 
2555 		switch (wr->opcode) {
2556 		case IB_WR_SEND:
2557 		case IB_WR_SEND_WITH_IMM:
2558 			if (qp->qplib_qp.type == CMDQ_CREATE_QP1_TYPE_GSI) {
2559 				rc = bnxt_re_build_qp1_send_v2(qp, wr, &wqe,
2560 							       payload_sz);
2561 				if (rc)
2562 					goto bad;
2563 				wqe.rawqp1.lflags |=
2564 					SQ_SEND_RAWETH_QP1_LFLAGS_ROCE_CRC;
2565 			}
2566 			switch (wr->send_flags) {
2567 			case IB_SEND_IP_CSUM:
2568 				wqe.rawqp1.lflags |=
2569 					SQ_SEND_RAWETH_QP1_LFLAGS_IP_CHKSUM;
2570 				break;
2571 			default:
2572 				break;
2573 			}
2574 			/* fall through */
2575 		case IB_WR_SEND_WITH_INV:
2576 			rc = bnxt_re_build_send_wqe(qp, wr, &wqe);
2577 			break;
2578 		case IB_WR_RDMA_WRITE:
2579 		case IB_WR_RDMA_WRITE_WITH_IMM:
2580 		case IB_WR_RDMA_READ:
2581 			rc = bnxt_re_build_rdma_wqe(wr, &wqe);
2582 			break;
2583 		case IB_WR_ATOMIC_CMP_AND_SWP:
2584 		case IB_WR_ATOMIC_FETCH_AND_ADD:
2585 			rc = bnxt_re_build_atomic_wqe(wr, &wqe);
2586 			break;
2587 		case IB_WR_RDMA_READ_WITH_INV:
2588 			ibdev_err(&qp->rdev->ibdev,
2589 				  "RDMA Read with Invalidate is not supported");
2590 			rc = -EINVAL;
2591 			goto bad;
2592 		case IB_WR_LOCAL_INV:
2593 			rc = bnxt_re_build_inv_wqe(wr, &wqe);
2594 			break;
2595 		case IB_WR_REG_MR:
2596 			rc = bnxt_re_build_reg_wqe(reg_wr(wr), &wqe);
2597 			break;
2598 		default:
2599 			/* Unsupported WRs */
2600 			ibdev_err(&qp->rdev->ibdev,
2601 				  "WR (%#x) is not supported", wr->opcode);
2602 			rc = -EINVAL;
2603 			goto bad;
2604 		}
2605 		if (!rc)
2606 			rc = bnxt_qplib_post_send(&qp->qplib_qp, &wqe);
2607 bad:
2608 		if (rc) {
2609 			ibdev_err(&qp->rdev->ibdev,
2610 				  "post_send failed op:%#x qps = %#x rc = %d\n",
2611 				  wr->opcode, qp->qplib_qp.state, rc);
2612 			*bad_wr = wr;
2613 			break;
2614 		}
2615 		wr = wr->next;
2616 	}
2617 	bnxt_qplib_post_send_db(&qp->qplib_qp);
2618 	bnxt_ud_qp_hw_stall_workaround(qp);
2619 	spin_unlock_irqrestore(&qp->sq_lock, flags);
2620 
2621 	return rc;
2622 }
2623 
2624 static int bnxt_re_post_recv_shadow_qp(struct bnxt_re_dev *rdev,
2625 				       struct bnxt_re_qp *qp,
2626 				       const struct ib_recv_wr *wr)
2627 {
2628 	struct bnxt_qplib_swqe wqe;
2629 	int rc = 0;
2630 
2631 	memset(&wqe, 0, sizeof(wqe));
2632 	while (wr) {
2633 		/* House keeping */
2634 		memset(&wqe, 0, sizeof(wqe));
2635 
2636 		/* Common */
2637 		wqe.num_sge = wr->num_sge;
2638 		if (wr->num_sge > qp->qplib_qp.rq.max_sge) {
2639 			ibdev_err(&rdev->ibdev,
2640 				  "Limit exceeded for Receive SGEs");
2641 			rc = -EINVAL;
2642 			break;
2643 		}
2644 		bnxt_re_build_sgl(wr->sg_list, wqe.sg_list, wr->num_sge);
2645 		wqe.wr_id = wr->wr_id;
2646 		wqe.type = BNXT_QPLIB_SWQE_TYPE_RECV;
2647 
2648 		rc = bnxt_qplib_post_recv(&qp->qplib_qp, &wqe);
2649 		if (rc)
2650 			break;
2651 
2652 		wr = wr->next;
2653 	}
2654 	if (!rc)
2655 		bnxt_qplib_post_recv_db(&qp->qplib_qp);
2656 	return rc;
2657 }
2658 
2659 int bnxt_re_post_recv(struct ib_qp *ib_qp, const struct ib_recv_wr *wr,
2660 		      const struct ib_recv_wr **bad_wr)
2661 {
2662 	struct bnxt_re_qp *qp = container_of(ib_qp, struct bnxt_re_qp, ib_qp);
2663 	struct bnxt_qplib_swqe wqe;
2664 	int rc = 0, payload_sz = 0;
2665 	unsigned long flags;
2666 	u32 count = 0;
2667 
2668 	spin_lock_irqsave(&qp->rq_lock, flags);
2669 	while (wr) {
2670 		/* House keeping */
2671 		memset(&wqe, 0, sizeof(wqe));
2672 
2673 		/* Common */
2674 		wqe.num_sge = wr->num_sge;
2675 		if (wr->num_sge > qp->qplib_qp.rq.max_sge) {
2676 			ibdev_err(&qp->rdev->ibdev,
2677 				  "Limit exceeded for Receive SGEs");
2678 			rc = -EINVAL;
2679 			*bad_wr = wr;
2680 			break;
2681 		}
2682 
2683 		payload_sz = bnxt_re_build_sgl(wr->sg_list, wqe.sg_list,
2684 					       wr->num_sge);
2685 		wqe.wr_id = wr->wr_id;
2686 		wqe.type = BNXT_QPLIB_SWQE_TYPE_RECV;
2687 
2688 		if (ib_qp->qp_type == IB_QPT_GSI &&
2689 		    qp->qplib_qp.type != CMDQ_CREATE_QP_TYPE_GSI)
2690 			rc = bnxt_re_build_qp1_shadow_qp_recv(qp, wr, &wqe,
2691 							      payload_sz);
2692 		if (!rc)
2693 			rc = bnxt_qplib_post_recv(&qp->qplib_qp, &wqe);
2694 		if (rc) {
2695 			*bad_wr = wr;
2696 			break;
2697 		}
2698 
2699 		/* Ring DB if the RQEs posted reaches a threshold value */
2700 		if (++count >= BNXT_RE_RQ_WQE_THRESHOLD) {
2701 			bnxt_qplib_post_recv_db(&qp->qplib_qp);
2702 			count = 0;
2703 		}
2704 
2705 		wr = wr->next;
2706 	}
2707 
2708 	if (count)
2709 		bnxt_qplib_post_recv_db(&qp->qplib_qp);
2710 
2711 	spin_unlock_irqrestore(&qp->rq_lock, flags);
2712 
2713 	return rc;
2714 }
2715 
2716 /* Completion Queues */
2717 void bnxt_re_destroy_cq(struct ib_cq *ib_cq, struct ib_udata *udata)
2718 {
2719 	struct bnxt_re_cq *cq;
2720 	struct bnxt_qplib_nq *nq;
2721 	struct bnxt_re_dev *rdev;
2722 
2723 	cq = container_of(ib_cq, struct bnxt_re_cq, ib_cq);
2724 	rdev = cq->rdev;
2725 	nq = cq->qplib_cq.nq;
2726 
2727 	bnxt_qplib_destroy_cq(&rdev->qplib_res, &cq->qplib_cq);
2728 	ib_umem_release(cq->umem);
2729 
2730 	atomic_dec(&rdev->cq_count);
2731 	nq->budget--;
2732 	kfree(cq->cql);
2733 }
2734 
2735 int bnxt_re_create_cq(struct ib_cq *ibcq, const struct ib_cq_init_attr *attr,
2736 		      struct ib_udata *udata)
2737 {
2738 	struct bnxt_re_dev *rdev = to_bnxt_re_dev(ibcq->device, ibdev);
2739 	struct bnxt_qplib_dev_attr *dev_attr = &rdev->dev_attr;
2740 	struct bnxt_re_cq *cq = container_of(ibcq, struct bnxt_re_cq, ib_cq);
2741 	int rc, entries;
2742 	int cqe = attr->cqe;
2743 	struct bnxt_qplib_nq *nq = NULL;
2744 	unsigned int nq_alloc_cnt;
2745 
2746 	/* Validate CQ fields */
2747 	if (cqe < 1 || cqe > dev_attr->max_cq_wqes) {
2748 		ibdev_err(&rdev->ibdev, "Failed to create CQ -max exceeded");
2749 		return -EINVAL;
2750 	}
2751 
2752 	cq->rdev = rdev;
2753 	cq->qplib_cq.cq_handle = (u64)(unsigned long)(&cq->qplib_cq);
2754 
2755 	entries = roundup_pow_of_two(cqe + 1);
2756 	if (entries > dev_attr->max_cq_wqes + 1)
2757 		entries = dev_attr->max_cq_wqes + 1;
2758 
2759 	cq->qplib_cq.sg_info.pgsize = PAGE_SIZE;
2760 	cq->qplib_cq.sg_info.pgshft = PAGE_SHIFT;
2761 	if (udata) {
2762 		struct bnxt_re_cq_req req;
2763 		struct bnxt_re_ucontext *uctx = rdma_udata_to_drv_context(
2764 			udata, struct bnxt_re_ucontext, ib_uctx);
2765 		if (ib_copy_from_udata(&req, udata, sizeof(req))) {
2766 			rc = -EFAULT;
2767 			goto fail;
2768 		}
2769 
2770 		cq->umem = ib_umem_get(&rdev->ibdev, req.cq_va,
2771 				       entries * sizeof(struct cq_base),
2772 				       IB_ACCESS_LOCAL_WRITE);
2773 		if (IS_ERR(cq->umem)) {
2774 			rc = PTR_ERR(cq->umem);
2775 			goto fail;
2776 		}
2777 		cq->qplib_cq.sg_info.sghead = cq->umem->sg_head.sgl;
2778 		cq->qplib_cq.sg_info.npages = ib_umem_num_pages(cq->umem);
2779 		cq->qplib_cq.sg_info.nmap = cq->umem->nmap;
2780 		cq->qplib_cq.dpi = &uctx->dpi;
2781 	} else {
2782 		cq->max_cql = min_t(u32, entries, MAX_CQL_PER_POLL);
2783 		cq->cql = kcalloc(cq->max_cql, sizeof(struct bnxt_qplib_cqe),
2784 				  GFP_KERNEL);
2785 		if (!cq->cql) {
2786 			rc = -ENOMEM;
2787 			goto fail;
2788 		}
2789 
2790 		cq->qplib_cq.dpi = &rdev->dpi_privileged;
2791 	}
2792 	/*
2793 	 * Allocating the NQ in a round robin fashion. nq_alloc_cnt is a
2794 	 * used for getting the NQ index.
2795 	 */
2796 	nq_alloc_cnt = atomic_inc_return(&rdev->nq_alloc_cnt);
2797 	nq = &rdev->nq[nq_alloc_cnt % (rdev->num_msix - 1)];
2798 	cq->qplib_cq.max_wqe = entries;
2799 	cq->qplib_cq.cnq_hw_ring_id = nq->ring_id;
2800 	cq->qplib_cq.nq	= nq;
2801 
2802 	rc = bnxt_qplib_create_cq(&rdev->qplib_res, &cq->qplib_cq);
2803 	if (rc) {
2804 		ibdev_err(&rdev->ibdev, "Failed to create HW CQ");
2805 		goto fail;
2806 	}
2807 
2808 	cq->ib_cq.cqe = entries;
2809 	cq->cq_period = cq->qplib_cq.period;
2810 	nq->budget++;
2811 
2812 	atomic_inc(&rdev->cq_count);
2813 	spin_lock_init(&cq->cq_lock);
2814 
2815 	if (udata) {
2816 		struct bnxt_re_cq_resp resp;
2817 
2818 		resp.cqid = cq->qplib_cq.id;
2819 		resp.tail = cq->qplib_cq.hwq.cons;
2820 		resp.phase = cq->qplib_cq.period;
2821 		resp.rsvd = 0;
2822 		rc = ib_copy_to_udata(udata, &resp, sizeof(resp));
2823 		if (rc) {
2824 			ibdev_err(&rdev->ibdev, "Failed to copy CQ udata");
2825 			bnxt_qplib_destroy_cq(&rdev->qplib_res, &cq->qplib_cq);
2826 			goto c2fail;
2827 		}
2828 	}
2829 
2830 	return 0;
2831 
2832 c2fail:
2833 	ib_umem_release(cq->umem);
2834 fail:
2835 	kfree(cq->cql);
2836 	return rc;
2837 }
2838 
2839 static u8 __req_to_ib_wc_status(u8 qstatus)
2840 {
2841 	switch (qstatus) {
2842 	case CQ_REQ_STATUS_OK:
2843 		return IB_WC_SUCCESS;
2844 	case CQ_REQ_STATUS_BAD_RESPONSE_ERR:
2845 		return IB_WC_BAD_RESP_ERR;
2846 	case CQ_REQ_STATUS_LOCAL_LENGTH_ERR:
2847 		return IB_WC_LOC_LEN_ERR;
2848 	case CQ_REQ_STATUS_LOCAL_QP_OPERATION_ERR:
2849 		return IB_WC_LOC_QP_OP_ERR;
2850 	case CQ_REQ_STATUS_LOCAL_PROTECTION_ERR:
2851 		return IB_WC_LOC_PROT_ERR;
2852 	case CQ_REQ_STATUS_MEMORY_MGT_OPERATION_ERR:
2853 		return IB_WC_GENERAL_ERR;
2854 	case CQ_REQ_STATUS_REMOTE_INVALID_REQUEST_ERR:
2855 		return IB_WC_REM_INV_REQ_ERR;
2856 	case CQ_REQ_STATUS_REMOTE_ACCESS_ERR:
2857 		return IB_WC_REM_ACCESS_ERR;
2858 	case CQ_REQ_STATUS_REMOTE_OPERATION_ERR:
2859 		return IB_WC_REM_OP_ERR;
2860 	case CQ_REQ_STATUS_RNR_NAK_RETRY_CNT_ERR:
2861 		return IB_WC_RNR_RETRY_EXC_ERR;
2862 	case CQ_REQ_STATUS_TRANSPORT_RETRY_CNT_ERR:
2863 		return IB_WC_RETRY_EXC_ERR;
2864 	case CQ_REQ_STATUS_WORK_REQUEST_FLUSHED_ERR:
2865 		return IB_WC_WR_FLUSH_ERR;
2866 	default:
2867 		return IB_WC_GENERAL_ERR;
2868 	}
2869 	return 0;
2870 }
2871 
2872 static u8 __rawqp1_to_ib_wc_status(u8 qstatus)
2873 {
2874 	switch (qstatus) {
2875 	case CQ_RES_RAWETH_QP1_STATUS_OK:
2876 		return IB_WC_SUCCESS;
2877 	case CQ_RES_RAWETH_QP1_STATUS_LOCAL_ACCESS_ERROR:
2878 		return IB_WC_LOC_ACCESS_ERR;
2879 	case CQ_RES_RAWETH_QP1_STATUS_HW_LOCAL_LENGTH_ERR:
2880 		return IB_WC_LOC_LEN_ERR;
2881 	case CQ_RES_RAWETH_QP1_STATUS_LOCAL_PROTECTION_ERR:
2882 		return IB_WC_LOC_PROT_ERR;
2883 	case CQ_RES_RAWETH_QP1_STATUS_LOCAL_QP_OPERATION_ERR:
2884 		return IB_WC_LOC_QP_OP_ERR;
2885 	case CQ_RES_RAWETH_QP1_STATUS_MEMORY_MGT_OPERATION_ERR:
2886 		return IB_WC_GENERAL_ERR;
2887 	case CQ_RES_RAWETH_QP1_STATUS_WORK_REQUEST_FLUSHED_ERR:
2888 		return IB_WC_WR_FLUSH_ERR;
2889 	case CQ_RES_RAWETH_QP1_STATUS_HW_FLUSH_ERR:
2890 		return IB_WC_WR_FLUSH_ERR;
2891 	default:
2892 		return IB_WC_GENERAL_ERR;
2893 	}
2894 }
2895 
2896 static u8 __rc_to_ib_wc_status(u8 qstatus)
2897 {
2898 	switch (qstatus) {
2899 	case CQ_RES_RC_STATUS_OK:
2900 		return IB_WC_SUCCESS;
2901 	case CQ_RES_RC_STATUS_LOCAL_ACCESS_ERROR:
2902 		return IB_WC_LOC_ACCESS_ERR;
2903 	case CQ_RES_RC_STATUS_LOCAL_LENGTH_ERR:
2904 		return IB_WC_LOC_LEN_ERR;
2905 	case CQ_RES_RC_STATUS_LOCAL_PROTECTION_ERR:
2906 		return IB_WC_LOC_PROT_ERR;
2907 	case CQ_RES_RC_STATUS_LOCAL_QP_OPERATION_ERR:
2908 		return IB_WC_LOC_QP_OP_ERR;
2909 	case CQ_RES_RC_STATUS_MEMORY_MGT_OPERATION_ERR:
2910 		return IB_WC_GENERAL_ERR;
2911 	case CQ_RES_RC_STATUS_REMOTE_INVALID_REQUEST_ERR:
2912 		return IB_WC_REM_INV_REQ_ERR;
2913 	case CQ_RES_RC_STATUS_WORK_REQUEST_FLUSHED_ERR:
2914 		return IB_WC_WR_FLUSH_ERR;
2915 	case CQ_RES_RC_STATUS_HW_FLUSH_ERR:
2916 		return IB_WC_WR_FLUSH_ERR;
2917 	default:
2918 		return IB_WC_GENERAL_ERR;
2919 	}
2920 }
2921 
2922 static void bnxt_re_process_req_wc(struct ib_wc *wc, struct bnxt_qplib_cqe *cqe)
2923 {
2924 	switch (cqe->type) {
2925 	case BNXT_QPLIB_SWQE_TYPE_SEND:
2926 		wc->opcode = IB_WC_SEND;
2927 		break;
2928 	case BNXT_QPLIB_SWQE_TYPE_SEND_WITH_IMM:
2929 		wc->opcode = IB_WC_SEND;
2930 		wc->wc_flags |= IB_WC_WITH_IMM;
2931 		break;
2932 	case BNXT_QPLIB_SWQE_TYPE_SEND_WITH_INV:
2933 		wc->opcode = IB_WC_SEND;
2934 		wc->wc_flags |= IB_WC_WITH_INVALIDATE;
2935 		break;
2936 	case BNXT_QPLIB_SWQE_TYPE_RDMA_WRITE:
2937 		wc->opcode = IB_WC_RDMA_WRITE;
2938 		break;
2939 	case BNXT_QPLIB_SWQE_TYPE_RDMA_WRITE_WITH_IMM:
2940 		wc->opcode = IB_WC_RDMA_WRITE;
2941 		wc->wc_flags |= IB_WC_WITH_IMM;
2942 		break;
2943 	case BNXT_QPLIB_SWQE_TYPE_RDMA_READ:
2944 		wc->opcode = IB_WC_RDMA_READ;
2945 		break;
2946 	case BNXT_QPLIB_SWQE_TYPE_ATOMIC_CMP_AND_SWP:
2947 		wc->opcode = IB_WC_COMP_SWAP;
2948 		break;
2949 	case BNXT_QPLIB_SWQE_TYPE_ATOMIC_FETCH_AND_ADD:
2950 		wc->opcode = IB_WC_FETCH_ADD;
2951 		break;
2952 	case BNXT_QPLIB_SWQE_TYPE_LOCAL_INV:
2953 		wc->opcode = IB_WC_LOCAL_INV;
2954 		break;
2955 	case BNXT_QPLIB_SWQE_TYPE_REG_MR:
2956 		wc->opcode = IB_WC_REG_MR;
2957 		break;
2958 	default:
2959 		wc->opcode = IB_WC_SEND;
2960 		break;
2961 	}
2962 
2963 	wc->status = __req_to_ib_wc_status(cqe->status);
2964 }
2965 
2966 static int bnxt_re_check_packet_type(u16 raweth_qp1_flags,
2967 				     u16 raweth_qp1_flags2)
2968 {
2969 	bool is_ipv6 = false, is_ipv4 = false;
2970 
2971 	/* raweth_qp1_flags Bit 9-6 indicates itype */
2972 	if ((raweth_qp1_flags & CQ_RES_RAWETH_QP1_RAWETH_QP1_FLAGS_ITYPE_ROCE)
2973 	    != CQ_RES_RAWETH_QP1_RAWETH_QP1_FLAGS_ITYPE_ROCE)
2974 		return -1;
2975 
2976 	if (raweth_qp1_flags2 &
2977 	    CQ_RES_RAWETH_QP1_RAWETH_QP1_FLAGS2_IP_CS_CALC &&
2978 	    raweth_qp1_flags2 &
2979 	    CQ_RES_RAWETH_QP1_RAWETH_QP1_FLAGS2_L4_CS_CALC) {
2980 		/* raweth_qp1_flags2 Bit 8 indicates ip_type. 0-v4 1 - v6 */
2981 		(raweth_qp1_flags2 &
2982 		 CQ_RES_RAWETH_QP1_RAWETH_QP1_FLAGS2_IP_TYPE) ?
2983 			(is_ipv6 = true) : (is_ipv4 = true);
2984 		return ((is_ipv6) ?
2985 			 BNXT_RE_ROCEV2_IPV6_PACKET :
2986 			 BNXT_RE_ROCEV2_IPV4_PACKET);
2987 	} else {
2988 		return BNXT_RE_ROCE_V1_PACKET;
2989 	}
2990 }
2991 
2992 static int bnxt_re_to_ib_nw_type(int nw_type)
2993 {
2994 	u8 nw_hdr_type = 0xFF;
2995 
2996 	switch (nw_type) {
2997 	case BNXT_RE_ROCE_V1_PACKET:
2998 		nw_hdr_type = RDMA_NETWORK_ROCE_V1;
2999 		break;
3000 	case BNXT_RE_ROCEV2_IPV4_PACKET:
3001 		nw_hdr_type = RDMA_NETWORK_IPV4;
3002 		break;
3003 	case BNXT_RE_ROCEV2_IPV6_PACKET:
3004 		nw_hdr_type = RDMA_NETWORK_IPV6;
3005 		break;
3006 	}
3007 	return nw_hdr_type;
3008 }
3009 
3010 static bool bnxt_re_is_loopback_packet(struct bnxt_re_dev *rdev,
3011 				       void *rq_hdr_buf)
3012 {
3013 	u8 *tmp_buf = NULL;
3014 	struct ethhdr *eth_hdr;
3015 	u16 eth_type;
3016 	bool rc = false;
3017 
3018 	tmp_buf = (u8 *)rq_hdr_buf;
3019 	/*
3020 	 * If dest mac is not same as I/F mac, this could be a
3021 	 * loopback address or multicast address, check whether
3022 	 * it is a loopback packet
3023 	 */
3024 	if (!ether_addr_equal(tmp_buf, rdev->netdev->dev_addr)) {
3025 		tmp_buf += 4;
3026 		/* Check the  ether type */
3027 		eth_hdr = (struct ethhdr *)tmp_buf;
3028 		eth_type = ntohs(eth_hdr->h_proto);
3029 		switch (eth_type) {
3030 		case ETH_P_IBOE:
3031 			rc = true;
3032 			break;
3033 		case ETH_P_IP:
3034 		case ETH_P_IPV6: {
3035 			u32 len;
3036 			struct udphdr *udp_hdr;
3037 
3038 			len = (eth_type == ETH_P_IP ? sizeof(struct iphdr) :
3039 						      sizeof(struct ipv6hdr));
3040 			tmp_buf += sizeof(struct ethhdr) + len;
3041 			udp_hdr = (struct udphdr *)tmp_buf;
3042 			if (ntohs(udp_hdr->dest) ==
3043 				    ROCE_V2_UDP_DPORT)
3044 				rc = true;
3045 			break;
3046 			}
3047 		default:
3048 			break;
3049 		}
3050 	}
3051 
3052 	return rc;
3053 }
3054 
3055 static int bnxt_re_process_raw_qp_pkt_rx(struct bnxt_re_qp *gsi_qp,
3056 					 struct bnxt_qplib_cqe *cqe)
3057 {
3058 	struct bnxt_re_dev *rdev = gsi_qp->rdev;
3059 	struct bnxt_re_sqp_entries *sqp_entry = NULL;
3060 	struct bnxt_re_qp *gsi_sqp = rdev->gsi_ctx.gsi_sqp;
3061 	struct bnxt_re_ah *gsi_sah;
3062 	struct ib_send_wr *swr;
3063 	struct ib_ud_wr udwr;
3064 	struct ib_recv_wr rwr;
3065 	int pkt_type = 0;
3066 	u32 tbl_idx;
3067 	void *rq_hdr_buf;
3068 	dma_addr_t rq_hdr_buf_map;
3069 	dma_addr_t shrq_hdr_buf_map;
3070 	u32 offset = 0;
3071 	u32 skip_bytes = 0;
3072 	struct ib_sge s_sge[2];
3073 	struct ib_sge r_sge[2];
3074 	int rc;
3075 
3076 	memset(&udwr, 0, sizeof(udwr));
3077 	memset(&rwr, 0, sizeof(rwr));
3078 	memset(&s_sge, 0, sizeof(s_sge));
3079 	memset(&r_sge, 0, sizeof(r_sge));
3080 
3081 	swr = &udwr.wr;
3082 	tbl_idx = cqe->wr_id;
3083 
3084 	rq_hdr_buf = gsi_qp->qplib_qp.rq_hdr_buf +
3085 			(tbl_idx * gsi_qp->qplib_qp.rq_hdr_buf_size);
3086 	rq_hdr_buf_map = bnxt_qplib_get_qp_buf_from_index(&gsi_qp->qplib_qp,
3087 							  tbl_idx);
3088 
3089 	/* Shadow QP header buffer */
3090 	shrq_hdr_buf_map = bnxt_qplib_get_qp_buf_from_index(&gsi_qp->qplib_qp,
3091 							    tbl_idx);
3092 	sqp_entry = &rdev->gsi_ctx.sqp_tbl[tbl_idx];
3093 
3094 	/* Store this cqe */
3095 	memcpy(&sqp_entry->cqe, cqe, sizeof(struct bnxt_qplib_cqe));
3096 	sqp_entry->qp1_qp = gsi_qp;
3097 
3098 	/* Find packet type from the cqe */
3099 
3100 	pkt_type = bnxt_re_check_packet_type(cqe->raweth_qp1_flags,
3101 					     cqe->raweth_qp1_flags2);
3102 	if (pkt_type < 0) {
3103 		ibdev_err(&rdev->ibdev, "Invalid packet\n");
3104 		return -EINVAL;
3105 	}
3106 
3107 	/* Adjust the offset for the user buffer and post in the rq */
3108 
3109 	if (pkt_type == BNXT_RE_ROCEV2_IPV4_PACKET)
3110 		offset = 20;
3111 
3112 	/*
3113 	 * QP1 loopback packet has 4 bytes of internal header before
3114 	 * ether header. Skip these four bytes.
3115 	 */
3116 	if (bnxt_re_is_loopback_packet(rdev, rq_hdr_buf))
3117 		skip_bytes = 4;
3118 
3119 	/* First send SGE . Skip the ether header*/
3120 	s_sge[0].addr = rq_hdr_buf_map + BNXT_QPLIB_MAX_QP1_RQ_ETH_HDR_SIZE
3121 			+ skip_bytes;
3122 	s_sge[0].lkey = 0xFFFFFFFF;
3123 	s_sge[0].length = offset ? BNXT_QPLIB_MAX_GRH_HDR_SIZE_IPV4 :
3124 				BNXT_QPLIB_MAX_GRH_HDR_SIZE_IPV6;
3125 
3126 	/* Second Send SGE */
3127 	s_sge[1].addr = s_sge[0].addr + s_sge[0].length +
3128 			BNXT_QPLIB_MAX_QP1_RQ_BDETH_HDR_SIZE;
3129 	if (pkt_type != BNXT_RE_ROCE_V1_PACKET)
3130 		s_sge[1].addr += 8;
3131 	s_sge[1].lkey = 0xFFFFFFFF;
3132 	s_sge[1].length = 256;
3133 
3134 	/* First recv SGE */
3135 
3136 	r_sge[0].addr = shrq_hdr_buf_map;
3137 	r_sge[0].lkey = 0xFFFFFFFF;
3138 	r_sge[0].length = 40;
3139 
3140 	r_sge[1].addr = sqp_entry->sge.addr + offset;
3141 	r_sge[1].lkey = sqp_entry->sge.lkey;
3142 	r_sge[1].length = BNXT_QPLIB_MAX_GRH_HDR_SIZE_IPV6 + 256 - offset;
3143 
3144 	/* Create receive work request */
3145 	rwr.num_sge = 2;
3146 	rwr.sg_list = r_sge;
3147 	rwr.wr_id = tbl_idx;
3148 	rwr.next = NULL;
3149 
3150 	rc = bnxt_re_post_recv_shadow_qp(rdev, gsi_sqp, &rwr);
3151 	if (rc) {
3152 		ibdev_err(&rdev->ibdev,
3153 			  "Failed to post Rx buffers to shadow QP");
3154 		return -ENOMEM;
3155 	}
3156 
3157 	swr->num_sge = 2;
3158 	swr->sg_list = s_sge;
3159 	swr->wr_id = tbl_idx;
3160 	swr->opcode = IB_WR_SEND;
3161 	swr->next = NULL;
3162 	gsi_sah = rdev->gsi_ctx.gsi_sah;
3163 	udwr.ah = &gsi_sah->ib_ah;
3164 	udwr.remote_qpn = gsi_sqp->qplib_qp.id;
3165 	udwr.remote_qkey = gsi_sqp->qplib_qp.qkey;
3166 
3167 	/* post data received  in the send queue */
3168 	rc = bnxt_re_post_send_shadow_qp(rdev, gsi_sqp, swr);
3169 
3170 	return 0;
3171 }
3172 
3173 static void bnxt_re_process_res_rawqp1_wc(struct ib_wc *wc,
3174 					  struct bnxt_qplib_cqe *cqe)
3175 {
3176 	wc->opcode = IB_WC_RECV;
3177 	wc->status = __rawqp1_to_ib_wc_status(cqe->status);
3178 	wc->wc_flags |= IB_WC_GRH;
3179 }
3180 
3181 static bool bnxt_re_is_vlan_pkt(struct bnxt_qplib_cqe *orig_cqe,
3182 				u16 *vid, u8 *sl)
3183 {
3184 	bool ret = false;
3185 	u32 metadata;
3186 	u16 tpid;
3187 
3188 	metadata = orig_cqe->raweth_qp1_metadata;
3189 	if (orig_cqe->raweth_qp1_flags2 &
3190 		CQ_RES_RAWETH_QP1_RAWETH_QP1_FLAGS2_META_FORMAT_VLAN) {
3191 		tpid = ((metadata &
3192 			 CQ_RES_RAWETH_QP1_RAWETH_QP1_METADATA_TPID_MASK) >>
3193 			 CQ_RES_RAWETH_QP1_RAWETH_QP1_METADATA_TPID_SFT);
3194 		if (tpid == ETH_P_8021Q) {
3195 			*vid = metadata &
3196 			       CQ_RES_RAWETH_QP1_RAWETH_QP1_METADATA_VID_MASK;
3197 			*sl = (metadata &
3198 			       CQ_RES_RAWETH_QP1_RAWETH_QP1_METADATA_PRI_MASK) >>
3199 			       CQ_RES_RAWETH_QP1_RAWETH_QP1_METADATA_PRI_SFT;
3200 			ret = true;
3201 		}
3202 	}
3203 
3204 	return ret;
3205 }
3206 
3207 static void bnxt_re_process_res_rc_wc(struct ib_wc *wc,
3208 				      struct bnxt_qplib_cqe *cqe)
3209 {
3210 	wc->opcode = IB_WC_RECV;
3211 	wc->status = __rc_to_ib_wc_status(cqe->status);
3212 
3213 	if (cqe->flags & CQ_RES_RC_FLAGS_IMM)
3214 		wc->wc_flags |= IB_WC_WITH_IMM;
3215 	if (cqe->flags & CQ_RES_RC_FLAGS_INV)
3216 		wc->wc_flags |= IB_WC_WITH_INVALIDATE;
3217 	if ((cqe->flags & (CQ_RES_RC_FLAGS_RDMA | CQ_RES_RC_FLAGS_IMM)) ==
3218 	    (CQ_RES_RC_FLAGS_RDMA | CQ_RES_RC_FLAGS_IMM))
3219 		wc->opcode = IB_WC_RECV_RDMA_WITH_IMM;
3220 }
3221 
3222 static void bnxt_re_process_res_shadow_qp_wc(struct bnxt_re_qp *gsi_sqp,
3223 					     struct ib_wc *wc,
3224 					     struct bnxt_qplib_cqe *cqe)
3225 {
3226 	struct bnxt_re_dev *rdev = gsi_sqp->rdev;
3227 	struct bnxt_re_qp *gsi_qp = NULL;
3228 	struct bnxt_qplib_cqe *orig_cqe = NULL;
3229 	struct bnxt_re_sqp_entries *sqp_entry = NULL;
3230 	int nw_type;
3231 	u32 tbl_idx;
3232 	u16 vlan_id;
3233 	u8 sl;
3234 
3235 	tbl_idx = cqe->wr_id;
3236 
3237 	sqp_entry = &rdev->gsi_ctx.sqp_tbl[tbl_idx];
3238 	gsi_qp = sqp_entry->qp1_qp;
3239 	orig_cqe = &sqp_entry->cqe;
3240 
3241 	wc->wr_id = sqp_entry->wrid;
3242 	wc->byte_len = orig_cqe->length;
3243 	wc->qp = &gsi_qp->ib_qp;
3244 
3245 	wc->ex.imm_data = orig_cqe->immdata;
3246 	wc->src_qp = orig_cqe->src_qp;
3247 	memcpy(wc->smac, orig_cqe->smac, ETH_ALEN);
3248 	if (bnxt_re_is_vlan_pkt(orig_cqe, &vlan_id, &sl)) {
3249 		wc->vlan_id = vlan_id;
3250 		wc->sl = sl;
3251 		wc->wc_flags |= IB_WC_WITH_VLAN;
3252 	}
3253 	wc->port_num = 1;
3254 	wc->vendor_err = orig_cqe->status;
3255 
3256 	wc->opcode = IB_WC_RECV;
3257 	wc->status = __rawqp1_to_ib_wc_status(orig_cqe->status);
3258 	wc->wc_flags |= IB_WC_GRH;
3259 
3260 	nw_type = bnxt_re_check_packet_type(orig_cqe->raweth_qp1_flags,
3261 					    orig_cqe->raweth_qp1_flags2);
3262 	if (nw_type >= 0) {
3263 		wc->network_hdr_type = bnxt_re_to_ib_nw_type(nw_type);
3264 		wc->wc_flags |= IB_WC_WITH_NETWORK_HDR_TYPE;
3265 	}
3266 }
3267 
3268 static void bnxt_re_process_res_ud_wc(struct bnxt_re_qp *qp,
3269 				      struct ib_wc *wc,
3270 				      struct bnxt_qplib_cqe *cqe)
3271 {
3272 	u8 nw_type;
3273 
3274 	wc->opcode = IB_WC_RECV;
3275 	wc->status = __rc_to_ib_wc_status(cqe->status);
3276 
3277 	if (cqe->flags & CQ_RES_UD_FLAGS_IMM)
3278 		wc->wc_flags |= IB_WC_WITH_IMM;
3279 	/* report only on GSI QP for Thor */
3280 	if (qp->qplib_qp.type == CMDQ_CREATE_QP_TYPE_GSI) {
3281 		wc->wc_flags |= IB_WC_GRH;
3282 		memcpy(wc->smac, cqe->smac, ETH_ALEN);
3283 		wc->wc_flags |= IB_WC_WITH_SMAC;
3284 		if (cqe->flags & CQ_RES_UD_FLAGS_META_FORMAT_VLAN) {
3285 			wc->vlan_id = (cqe->cfa_meta & 0xFFF);
3286 			if (wc->vlan_id < 0x1000)
3287 				wc->wc_flags |= IB_WC_WITH_VLAN;
3288 		}
3289 		nw_type = (cqe->flags & CQ_RES_UD_FLAGS_ROCE_IP_VER_MASK) >>
3290 			   CQ_RES_UD_FLAGS_ROCE_IP_VER_SFT;
3291 		wc->network_hdr_type = bnxt_re_to_ib_nw_type(nw_type);
3292 		wc->wc_flags |= IB_WC_WITH_NETWORK_HDR_TYPE;
3293 	}
3294 
3295 }
3296 
3297 static int send_phantom_wqe(struct bnxt_re_qp *qp)
3298 {
3299 	struct bnxt_qplib_qp *lib_qp = &qp->qplib_qp;
3300 	unsigned long flags;
3301 	int rc = 0;
3302 
3303 	spin_lock_irqsave(&qp->sq_lock, flags);
3304 
3305 	rc = bnxt_re_bind_fence_mw(lib_qp);
3306 	if (!rc) {
3307 		lib_qp->sq.phantom_wqe_cnt++;
3308 		ibdev_dbg(&qp->rdev->ibdev,
3309 			  "qp %#x sq->prod %#x sw_prod %#x phantom_wqe_cnt %d\n",
3310 			  lib_qp->id, lib_qp->sq.hwq.prod,
3311 			  HWQ_CMP(lib_qp->sq.hwq.prod, &lib_qp->sq.hwq),
3312 			  lib_qp->sq.phantom_wqe_cnt);
3313 	}
3314 
3315 	spin_unlock_irqrestore(&qp->sq_lock, flags);
3316 	return rc;
3317 }
3318 
3319 int bnxt_re_poll_cq(struct ib_cq *ib_cq, int num_entries, struct ib_wc *wc)
3320 {
3321 	struct bnxt_re_cq *cq = container_of(ib_cq, struct bnxt_re_cq, ib_cq);
3322 	struct bnxt_re_qp *qp, *sh_qp;
3323 	struct bnxt_qplib_cqe *cqe;
3324 	int i, ncqe, budget;
3325 	struct bnxt_qplib_q *sq;
3326 	struct bnxt_qplib_qp *lib_qp;
3327 	u32 tbl_idx;
3328 	struct bnxt_re_sqp_entries *sqp_entry = NULL;
3329 	unsigned long flags;
3330 
3331 	spin_lock_irqsave(&cq->cq_lock, flags);
3332 	budget = min_t(u32, num_entries, cq->max_cql);
3333 	num_entries = budget;
3334 	if (!cq->cql) {
3335 		ibdev_err(&cq->rdev->ibdev, "POLL CQ : no CQL to use");
3336 		goto exit;
3337 	}
3338 	cqe = &cq->cql[0];
3339 	while (budget) {
3340 		lib_qp = NULL;
3341 		ncqe = bnxt_qplib_poll_cq(&cq->qplib_cq, cqe, budget, &lib_qp);
3342 		if (lib_qp) {
3343 			sq = &lib_qp->sq;
3344 			if (sq->send_phantom) {
3345 				qp = container_of(lib_qp,
3346 						  struct bnxt_re_qp, qplib_qp);
3347 				if (send_phantom_wqe(qp) == -ENOMEM)
3348 					ibdev_err(&cq->rdev->ibdev,
3349 						  "Phantom failed! Scheduled to send again\n");
3350 				else
3351 					sq->send_phantom = false;
3352 			}
3353 		}
3354 		if (ncqe < budget)
3355 			ncqe += bnxt_qplib_process_flush_list(&cq->qplib_cq,
3356 							      cqe + ncqe,
3357 							      budget - ncqe);
3358 
3359 		if (!ncqe)
3360 			break;
3361 
3362 		for (i = 0; i < ncqe; i++, cqe++) {
3363 			/* Transcribe each qplib_wqe back to ib_wc */
3364 			memset(wc, 0, sizeof(*wc));
3365 
3366 			wc->wr_id = cqe->wr_id;
3367 			wc->byte_len = cqe->length;
3368 			qp = container_of
3369 				((struct bnxt_qplib_qp *)
3370 				 (unsigned long)(cqe->qp_handle),
3371 				 struct bnxt_re_qp, qplib_qp);
3372 			if (!qp) {
3373 				ibdev_err(&cq->rdev->ibdev, "POLL CQ : bad QP handle");
3374 				continue;
3375 			}
3376 			wc->qp = &qp->ib_qp;
3377 			wc->ex.imm_data = cqe->immdata;
3378 			wc->src_qp = cqe->src_qp;
3379 			memcpy(wc->smac, cqe->smac, ETH_ALEN);
3380 			wc->port_num = 1;
3381 			wc->vendor_err = cqe->status;
3382 
3383 			switch (cqe->opcode) {
3384 			case CQ_BASE_CQE_TYPE_REQ:
3385 				sh_qp = qp->rdev->gsi_ctx.gsi_sqp;
3386 				if (sh_qp &&
3387 				    qp->qplib_qp.id == sh_qp->qplib_qp.id) {
3388 					/* Handle this completion with
3389 					 * the stored completion
3390 					 */
3391 					memset(wc, 0, sizeof(*wc));
3392 					continue;
3393 				}
3394 				bnxt_re_process_req_wc(wc, cqe);
3395 				break;
3396 			case CQ_BASE_CQE_TYPE_RES_RAWETH_QP1:
3397 				if (!cqe->status) {
3398 					int rc = 0;
3399 
3400 					rc = bnxt_re_process_raw_qp_pkt_rx
3401 								(qp, cqe);
3402 					if (!rc) {
3403 						memset(wc, 0, sizeof(*wc));
3404 						continue;
3405 					}
3406 					cqe->status = -1;
3407 				}
3408 				/* Errors need not be looped back.
3409 				 * But change the wr_id to the one
3410 				 * stored in the table
3411 				 */
3412 				tbl_idx = cqe->wr_id;
3413 				sqp_entry = &cq->rdev->gsi_ctx.sqp_tbl[tbl_idx];
3414 				wc->wr_id = sqp_entry->wrid;
3415 				bnxt_re_process_res_rawqp1_wc(wc, cqe);
3416 				break;
3417 			case CQ_BASE_CQE_TYPE_RES_RC:
3418 				bnxt_re_process_res_rc_wc(wc, cqe);
3419 				break;
3420 			case CQ_BASE_CQE_TYPE_RES_UD:
3421 				sh_qp = qp->rdev->gsi_ctx.gsi_sqp;
3422 				if (sh_qp &&
3423 				    qp->qplib_qp.id == sh_qp->qplib_qp.id) {
3424 					/* Handle this completion with
3425 					 * the stored completion
3426 					 */
3427 					if (cqe->status) {
3428 						continue;
3429 					} else {
3430 						bnxt_re_process_res_shadow_qp_wc
3431 								(qp, wc, cqe);
3432 						break;
3433 					}
3434 				}
3435 				bnxt_re_process_res_ud_wc(qp, wc, cqe);
3436 				break;
3437 			default:
3438 				ibdev_err(&cq->rdev->ibdev,
3439 					  "POLL CQ : type 0x%x not handled",
3440 					  cqe->opcode);
3441 				continue;
3442 			}
3443 			wc++;
3444 			budget--;
3445 		}
3446 	}
3447 exit:
3448 	spin_unlock_irqrestore(&cq->cq_lock, flags);
3449 	return num_entries - budget;
3450 }
3451 
3452 int bnxt_re_req_notify_cq(struct ib_cq *ib_cq,
3453 			  enum ib_cq_notify_flags ib_cqn_flags)
3454 {
3455 	struct bnxt_re_cq *cq = container_of(ib_cq, struct bnxt_re_cq, ib_cq);
3456 	int type = 0, rc = 0;
3457 	unsigned long flags;
3458 
3459 	spin_lock_irqsave(&cq->cq_lock, flags);
3460 	/* Trigger on the very next completion */
3461 	if (ib_cqn_flags & IB_CQ_NEXT_COMP)
3462 		type = DBC_DBC_TYPE_CQ_ARMALL;
3463 	/* Trigger on the next solicited completion */
3464 	else if (ib_cqn_flags & IB_CQ_SOLICITED)
3465 		type = DBC_DBC_TYPE_CQ_ARMSE;
3466 
3467 	/* Poll to see if there are missed events */
3468 	if ((ib_cqn_flags & IB_CQ_REPORT_MISSED_EVENTS) &&
3469 	    !(bnxt_qplib_is_cq_empty(&cq->qplib_cq))) {
3470 		rc = 1;
3471 		goto exit;
3472 	}
3473 	bnxt_qplib_req_notify_cq(&cq->qplib_cq, type);
3474 
3475 exit:
3476 	spin_unlock_irqrestore(&cq->cq_lock, flags);
3477 	return rc;
3478 }
3479 
3480 /* Memory Regions */
3481 struct ib_mr *bnxt_re_get_dma_mr(struct ib_pd *ib_pd, int mr_access_flags)
3482 {
3483 	struct bnxt_re_pd *pd = container_of(ib_pd, struct bnxt_re_pd, ib_pd);
3484 	struct bnxt_re_dev *rdev = pd->rdev;
3485 	struct bnxt_re_mr *mr;
3486 	u64 pbl = 0;
3487 	int rc;
3488 
3489 	mr = kzalloc(sizeof(*mr), GFP_KERNEL);
3490 	if (!mr)
3491 		return ERR_PTR(-ENOMEM);
3492 
3493 	mr->rdev = rdev;
3494 	mr->qplib_mr.pd = &pd->qplib_pd;
3495 	mr->qplib_mr.flags = __from_ib_access_flags(mr_access_flags);
3496 	mr->qplib_mr.type = CMDQ_ALLOCATE_MRW_MRW_FLAGS_PMR;
3497 
3498 	/* Allocate and register 0 as the address */
3499 	rc = bnxt_qplib_alloc_mrw(&rdev->qplib_res, &mr->qplib_mr);
3500 	if (rc)
3501 		goto fail;
3502 
3503 	mr->qplib_mr.hwq.level = PBL_LVL_MAX;
3504 	mr->qplib_mr.total_size = -1; /* Infinte length */
3505 	rc = bnxt_qplib_reg_mr(&rdev->qplib_res, &mr->qplib_mr, &pbl, 0, false,
3506 			       PAGE_SIZE);
3507 	if (rc)
3508 		goto fail_mr;
3509 
3510 	mr->ib_mr.lkey = mr->qplib_mr.lkey;
3511 	if (mr_access_flags & (IB_ACCESS_REMOTE_WRITE | IB_ACCESS_REMOTE_READ |
3512 			       IB_ACCESS_REMOTE_ATOMIC))
3513 		mr->ib_mr.rkey = mr->ib_mr.lkey;
3514 	atomic_inc(&rdev->mr_count);
3515 
3516 	return &mr->ib_mr;
3517 
3518 fail_mr:
3519 	bnxt_qplib_free_mrw(&rdev->qplib_res, &mr->qplib_mr);
3520 fail:
3521 	kfree(mr);
3522 	return ERR_PTR(rc);
3523 }
3524 
3525 int bnxt_re_dereg_mr(struct ib_mr *ib_mr, struct ib_udata *udata)
3526 {
3527 	struct bnxt_re_mr *mr = container_of(ib_mr, struct bnxt_re_mr, ib_mr);
3528 	struct bnxt_re_dev *rdev = mr->rdev;
3529 	int rc;
3530 
3531 	rc = bnxt_qplib_free_mrw(&rdev->qplib_res, &mr->qplib_mr);
3532 	if (rc) {
3533 		ibdev_err(&rdev->ibdev, "Dereg MR failed: %#x\n", rc);
3534 		return rc;
3535 	}
3536 
3537 	if (mr->pages) {
3538 		rc = bnxt_qplib_free_fast_reg_page_list(&rdev->qplib_res,
3539 							&mr->qplib_frpl);
3540 		kfree(mr->pages);
3541 		mr->npages = 0;
3542 		mr->pages = NULL;
3543 	}
3544 	ib_umem_release(mr->ib_umem);
3545 
3546 	kfree(mr);
3547 	atomic_dec(&rdev->mr_count);
3548 	return rc;
3549 }
3550 
3551 static int bnxt_re_set_page(struct ib_mr *ib_mr, u64 addr)
3552 {
3553 	struct bnxt_re_mr *mr = container_of(ib_mr, struct bnxt_re_mr, ib_mr);
3554 
3555 	if (unlikely(mr->npages == mr->qplib_frpl.max_pg_ptrs))
3556 		return -ENOMEM;
3557 
3558 	mr->pages[mr->npages++] = addr;
3559 	return 0;
3560 }
3561 
3562 int bnxt_re_map_mr_sg(struct ib_mr *ib_mr, struct scatterlist *sg, int sg_nents,
3563 		      unsigned int *sg_offset)
3564 {
3565 	struct bnxt_re_mr *mr = container_of(ib_mr, struct bnxt_re_mr, ib_mr);
3566 
3567 	mr->npages = 0;
3568 	return ib_sg_to_pages(ib_mr, sg, sg_nents, sg_offset, bnxt_re_set_page);
3569 }
3570 
3571 struct ib_mr *bnxt_re_alloc_mr(struct ib_pd *ib_pd, enum ib_mr_type type,
3572 			       u32 max_num_sg, struct ib_udata *udata)
3573 {
3574 	struct bnxt_re_pd *pd = container_of(ib_pd, struct bnxt_re_pd, ib_pd);
3575 	struct bnxt_re_dev *rdev = pd->rdev;
3576 	struct bnxt_re_mr *mr = NULL;
3577 	int rc;
3578 
3579 	if (type != IB_MR_TYPE_MEM_REG) {
3580 		ibdev_dbg(&rdev->ibdev, "MR type 0x%x not supported", type);
3581 		return ERR_PTR(-EINVAL);
3582 	}
3583 	if (max_num_sg > MAX_PBL_LVL_1_PGS)
3584 		return ERR_PTR(-EINVAL);
3585 
3586 	mr = kzalloc(sizeof(*mr), GFP_KERNEL);
3587 	if (!mr)
3588 		return ERR_PTR(-ENOMEM);
3589 
3590 	mr->rdev = rdev;
3591 	mr->qplib_mr.pd = &pd->qplib_pd;
3592 	mr->qplib_mr.flags = BNXT_QPLIB_FR_PMR;
3593 	mr->qplib_mr.type = CMDQ_ALLOCATE_MRW_MRW_FLAGS_PMR;
3594 
3595 	rc = bnxt_qplib_alloc_mrw(&rdev->qplib_res, &mr->qplib_mr);
3596 	if (rc)
3597 		goto bail;
3598 
3599 	mr->ib_mr.lkey = mr->qplib_mr.lkey;
3600 	mr->ib_mr.rkey = mr->ib_mr.lkey;
3601 
3602 	mr->pages = kcalloc(max_num_sg, sizeof(u64), GFP_KERNEL);
3603 	if (!mr->pages) {
3604 		rc = -ENOMEM;
3605 		goto fail;
3606 	}
3607 	rc = bnxt_qplib_alloc_fast_reg_page_list(&rdev->qplib_res,
3608 						 &mr->qplib_frpl, max_num_sg);
3609 	if (rc) {
3610 		ibdev_err(&rdev->ibdev,
3611 			  "Failed to allocate HW FR page list");
3612 		goto fail_mr;
3613 	}
3614 
3615 	atomic_inc(&rdev->mr_count);
3616 	return &mr->ib_mr;
3617 
3618 fail_mr:
3619 	kfree(mr->pages);
3620 fail:
3621 	bnxt_qplib_free_mrw(&rdev->qplib_res, &mr->qplib_mr);
3622 bail:
3623 	kfree(mr);
3624 	return ERR_PTR(rc);
3625 }
3626 
3627 struct ib_mw *bnxt_re_alloc_mw(struct ib_pd *ib_pd, enum ib_mw_type type,
3628 			       struct ib_udata *udata)
3629 {
3630 	struct bnxt_re_pd *pd = container_of(ib_pd, struct bnxt_re_pd, ib_pd);
3631 	struct bnxt_re_dev *rdev = pd->rdev;
3632 	struct bnxt_re_mw *mw;
3633 	int rc;
3634 
3635 	mw = kzalloc(sizeof(*mw), GFP_KERNEL);
3636 	if (!mw)
3637 		return ERR_PTR(-ENOMEM);
3638 	mw->rdev = rdev;
3639 	mw->qplib_mw.pd = &pd->qplib_pd;
3640 
3641 	mw->qplib_mw.type = (type == IB_MW_TYPE_1 ?
3642 			       CMDQ_ALLOCATE_MRW_MRW_FLAGS_MW_TYPE1 :
3643 			       CMDQ_ALLOCATE_MRW_MRW_FLAGS_MW_TYPE2B);
3644 	rc = bnxt_qplib_alloc_mrw(&rdev->qplib_res, &mw->qplib_mw);
3645 	if (rc) {
3646 		ibdev_err(&rdev->ibdev, "Allocate MW failed!");
3647 		goto fail;
3648 	}
3649 	mw->ib_mw.rkey = mw->qplib_mw.rkey;
3650 
3651 	atomic_inc(&rdev->mw_count);
3652 	return &mw->ib_mw;
3653 
3654 fail:
3655 	kfree(mw);
3656 	return ERR_PTR(rc);
3657 }
3658 
3659 int bnxt_re_dealloc_mw(struct ib_mw *ib_mw)
3660 {
3661 	struct bnxt_re_mw *mw = container_of(ib_mw, struct bnxt_re_mw, ib_mw);
3662 	struct bnxt_re_dev *rdev = mw->rdev;
3663 	int rc;
3664 
3665 	rc = bnxt_qplib_free_mrw(&rdev->qplib_res, &mw->qplib_mw);
3666 	if (rc) {
3667 		ibdev_err(&rdev->ibdev, "Free MW failed: %#x\n", rc);
3668 		return rc;
3669 	}
3670 
3671 	kfree(mw);
3672 	atomic_dec(&rdev->mw_count);
3673 	return rc;
3674 }
3675 
3676 static int bnxt_re_page_size_ok(int page_shift)
3677 {
3678 	switch (page_shift) {
3679 	case CMDQ_REGISTER_MR_LOG2_PBL_PG_SIZE_PG_4K:
3680 	case CMDQ_REGISTER_MR_LOG2_PBL_PG_SIZE_PG_8K:
3681 	case CMDQ_REGISTER_MR_LOG2_PBL_PG_SIZE_PG_64K:
3682 	case CMDQ_REGISTER_MR_LOG2_PBL_PG_SIZE_PG_2M:
3683 	case CMDQ_REGISTER_MR_LOG2_PBL_PG_SIZE_PG_256K:
3684 	case CMDQ_REGISTER_MR_LOG2_PBL_PG_SIZE_PG_1M:
3685 	case CMDQ_REGISTER_MR_LOG2_PBL_PG_SIZE_PG_4M:
3686 	case CMDQ_REGISTER_MR_LOG2_PBL_PG_SIZE_PG_1G:
3687 		return 1;
3688 	default:
3689 		return 0;
3690 	}
3691 }
3692 
3693 static int fill_umem_pbl_tbl(struct ib_umem *umem, u64 *pbl_tbl_orig,
3694 			     int page_shift)
3695 {
3696 	u64 *pbl_tbl = pbl_tbl_orig;
3697 	u64 page_size =  BIT_ULL(page_shift);
3698 	struct ib_block_iter biter;
3699 
3700 	rdma_for_each_block(umem->sg_head.sgl, &biter, umem->nmap, page_size)
3701 		*pbl_tbl++ = rdma_block_iter_dma_address(&biter);
3702 
3703 	return pbl_tbl - pbl_tbl_orig;
3704 }
3705 
3706 /* uverbs */
3707 struct ib_mr *bnxt_re_reg_user_mr(struct ib_pd *ib_pd, u64 start, u64 length,
3708 				  u64 virt_addr, int mr_access_flags,
3709 				  struct ib_udata *udata)
3710 {
3711 	struct bnxt_re_pd *pd = container_of(ib_pd, struct bnxt_re_pd, ib_pd);
3712 	struct bnxt_re_dev *rdev = pd->rdev;
3713 	struct bnxt_re_mr *mr;
3714 	struct ib_umem *umem;
3715 	u64 *pbl_tbl = NULL;
3716 	int umem_pgs, page_shift, rc;
3717 
3718 	if (length > BNXT_RE_MAX_MR_SIZE) {
3719 		ibdev_err(&rdev->ibdev, "MR Size: %lld > Max supported:%lld\n",
3720 			  length, BNXT_RE_MAX_MR_SIZE);
3721 		return ERR_PTR(-ENOMEM);
3722 	}
3723 
3724 	mr = kzalloc(sizeof(*mr), GFP_KERNEL);
3725 	if (!mr)
3726 		return ERR_PTR(-ENOMEM);
3727 
3728 	mr->rdev = rdev;
3729 	mr->qplib_mr.pd = &pd->qplib_pd;
3730 	mr->qplib_mr.flags = __from_ib_access_flags(mr_access_flags);
3731 	mr->qplib_mr.type = CMDQ_ALLOCATE_MRW_MRW_FLAGS_MR;
3732 
3733 	rc = bnxt_qplib_alloc_mrw(&rdev->qplib_res, &mr->qplib_mr);
3734 	if (rc) {
3735 		ibdev_err(&rdev->ibdev, "Failed to allocate MR");
3736 		goto free_mr;
3737 	}
3738 	/* The fixed portion of the rkey is the same as the lkey */
3739 	mr->ib_mr.rkey = mr->qplib_mr.rkey;
3740 
3741 	umem = ib_umem_get(&rdev->ibdev, start, length, mr_access_flags);
3742 	if (IS_ERR(umem)) {
3743 		ibdev_err(&rdev->ibdev, "Failed to get umem");
3744 		rc = -EFAULT;
3745 		goto free_mrw;
3746 	}
3747 	mr->ib_umem = umem;
3748 
3749 	mr->qplib_mr.va = virt_addr;
3750 	umem_pgs = ib_umem_page_count(umem);
3751 	if (!umem_pgs) {
3752 		ibdev_err(&rdev->ibdev, "umem is invalid!");
3753 		rc = -EINVAL;
3754 		goto free_umem;
3755 	}
3756 	mr->qplib_mr.total_size = length;
3757 
3758 	pbl_tbl = kcalloc(umem_pgs, sizeof(u64 *), GFP_KERNEL);
3759 	if (!pbl_tbl) {
3760 		rc = -ENOMEM;
3761 		goto free_umem;
3762 	}
3763 
3764 	page_shift = __ffs(ib_umem_find_best_pgsz(umem,
3765 				BNXT_RE_PAGE_SIZE_4K | BNXT_RE_PAGE_SIZE_2M,
3766 				virt_addr));
3767 
3768 	if (!bnxt_re_page_size_ok(page_shift)) {
3769 		ibdev_err(&rdev->ibdev, "umem page size unsupported!");
3770 		rc = -EFAULT;
3771 		goto fail;
3772 	}
3773 
3774 	if (page_shift == BNXT_RE_PAGE_SHIFT_4K &&
3775 	    length > BNXT_RE_MAX_MR_SIZE_LOW) {
3776 		ibdev_err(&rdev->ibdev, "Requested MR Sz:%llu Max sup:%llu",
3777 			  length, (u64)BNXT_RE_MAX_MR_SIZE_LOW);
3778 		rc = -EINVAL;
3779 		goto fail;
3780 	}
3781 
3782 	/* Map umem buf ptrs to the PBL */
3783 	umem_pgs = fill_umem_pbl_tbl(umem, pbl_tbl, page_shift);
3784 	rc = bnxt_qplib_reg_mr(&rdev->qplib_res, &mr->qplib_mr, pbl_tbl,
3785 			       umem_pgs, false, 1 << page_shift);
3786 	if (rc) {
3787 		ibdev_err(&rdev->ibdev, "Failed to register user MR");
3788 		goto fail;
3789 	}
3790 
3791 	kfree(pbl_tbl);
3792 
3793 	mr->ib_mr.lkey = mr->qplib_mr.lkey;
3794 	mr->ib_mr.rkey = mr->qplib_mr.lkey;
3795 	atomic_inc(&rdev->mr_count);
3796 
3797 	return &mr->ib_mr;
3798 fail:
3799 	kfree(pbl_tbl);
3800 free_umem:
3801 	ib_umem_release(umem);
3802 free_mrw:
3803 	bnxt_qplib_free_mrw(&rdev->qplib_res, &mr->qplib_mr);
3804 free_mr:
3805 	kfree(mr);
3806 	return ERR_PTR(rc);
3807 }
3808 
3809 int bnxt_re_alloc_ucontext(struct ib_ucontext *ctx, struct ib_udata *udata)
3810 {
3811 	struct ib_device *ibdev = ctx->device;
3812 	struct bnxt_re_ucontext *uctx =
3813 		container_of(ctx, struct bnxt_re_ucontext, ib_uctx);
3814 	struct bnxt_re_dev *rdev = to_bnxt_re_dev(ibdev, ibdev);
3815 	struct bnxt_qplib_dev_attr *dev_attr = &rdev->dev_attr;
3816 	struct bnxt_re_uctx_resp resp;
3817 	u32 chip_met_rev_num = 0;
3818 	int rc;
3819 
3820 	ibdev_dbg(ibdev, "ABI version requested %u", ibdev->ops.uverbs_abi_ver);
3821 
3822 	if (ibdev->ops.uverbs_abi_ver != BNXT_RE_ABI_VERSION) {
3823 		ibdev_dbg(ibdev, " is different from the device %d ",
3824 			  BNXT_RE_ABI_VERSION);
3825 		return -EPERM;
3826 	}
3827 
3828 	uctx->rdev = rdev;
3829 
3830 	uctx->shpg = (void *)__get_free_page(GFP_KERNEL);
3831 	if (!uctx->shpg) {
3832 		rc = -ENOMEM;
3833 		goto fail;
3834 	}
3835 	spin_lock_init(&uctx->sh_lock);
3836 
3837 	resp.comp_mask = BNXT_RE_UCNTX_CMASK_HAVE_CCTX;
3838 	chip_met_rev_num = rdev->chip_ctx->chip_num;
3839 	chip_met_rev_num |= ((u32)rdev->chip_ctx->chip_rev & 0xFF) <<
3840 			     BNXT_RE_CHIP_ID0_CHIP_REV_SFT;
3841 	chip_met_rev_num |= ((u32)rdev->chip_ctx->chip_metal & 0xFF) <<
3842 			     BNXT_RE_CHIP_ID0_CHIP_MET_SFT;
3843 	resp.chip_id0 = chip_met_rev_num;
3844 	/* Future extension of chip info */
3845 	resp.chip_id1 = 0;
3846 	/*Temp, Use xa_alloc instead */
3847 	resp.dev_id = rdev->en_dev->pdev->devfn;
3848 	resp.max_qp = rdev->qplib_ctx.qpc_count;
3849 	resp.pg_size = PAGE_SIZE;
3850 	resp.cqe_sz = sizeof(struct cq_base);
3851 	resp.max_cqd = dev_attr->max_cq_wqes;
3852 	resp.rsvd    = 0;
3853 
3854 	rc = ib_copy_to_udata(udata, &resp, min(udata->outlen, sizeof(resp)));
3855 	if (rc) {
3856 		ibdev_err(ibdev, "Failed to copy user context");
3857 		rc = -EFAULT;
3858 		goto cfail;
3859 	}
3860 
3861 	return 0;
3862 cfail:
3863 	free_page((unsigned long)uctx->shpg);
3864 	uctx->shpg = NULL;
3865 fail:
3866 	return rc;
3867 }
3868 
3869 void bnxt_re_dealloc_ucontext(struct ib_ucontext *ib_uctx)
3870 {
3871 	struct bnxt_re_ucontext *uctx = container_of(ib_uctx,
3872 						   struct bnxt_re_ucontext,
3873 						   ib_uctx);
3874 
3875 	struct bnxt_re_dev *rdev = uctx->rdev;
3876 
3877 	if (uctx->shpg)
3878 		free_page((unsigned long)uctx->shpg);
3879 
3880 	if (uctx->dpi.dbr) {
3881 		/* Free DPI only if this is the first PD allocated by the
3882 		 * application and mark the context dpi as NULL
3883 		 */
3884 		bnxt_qplib_dealloc_dpi(&rdev->qplib_res,
3885 				       &rdev->qplib_res.dpi_tbl, &uctx->dpi);
3886 		uctx->dpi.dbr = NULL;
3887 	}
3888 }
3889 
3890 /* Helper function to mmap the virtual memory from user app */
3891 int bnxt_re_mmap(struct ib_ucontext *ib_uctx, struct vm_area_struct *vma)
3892 {
3893 	struct bnxt_re_ucontext *uctx = container_of(ib_uctx,
3894 						   struct bnxt_re_ucontext,
3895 						   ib_uctx);
3896 	struct bnxt_re_dev *rdev = uctx->rdev;
3897 	u64 pfn;
3898 
3899 	if (vma->vm_end - vma->vm_start != PAGE_SIZE)
3900 		return -EINVAL;
3901 
3902 	if (vma->vm_pgoff) {
3903 		vma->vm_page_prot = pgprot_noncached(vma->vm_page_prot);
3904 		if (io_remap_pfn_range(vma, vma->vm_start, vma->vm_pgoff,
3905 				       PAGE_SIZE, vma->vm_page_prot)) {
3906 			ibdev_err(&rdev->ibdev, "Failed to map DPI");
3907 			return -EAGAIN;
3908 		}
3909 	} else {
3910 		pfn = virt_to_phys(uctx->shpg) >> PAGE_SHIFT;
3911 		if (remap_pfn_range(vma, vma->vm_start,
3912 				    pfn, PAGE_SIZE, vma->vm_page_prot)) {
3913 			ibdev_err(&rdev->ibdev, "Failed to map shared page");
3914 			return -EAGAIN;
3915 		}
3916 	}
3917 
3918 	return 0;
3919 }
3920