1 /*
2  * Broadcom NetXtreme-E RoCE driver.
3  *
4  * Copyright (c) 2016 - 2017, Broadcom. All rights reserved.  The term
5  * Broadcom refers to Broadcom Limited and/or its subsidiaries.
6  *
7  * This software is available to you under a choice of one of two
8  * licenses.  You may choose to be licensed under the terms of the GNU
9  * General Public License (GPL) Version 2, available from the file
10  * COPYING in the main directory of this source tree, or the
11  * BSD license below:
12  *
13  * Redistribution and use in source and binary forms, with or without
14  * modification, are permitted provided that the following conditions
15  * are met:
16  *
17  * 1. Redistributions of source code must retain the above copyright
18  *    notice, this list of conditions and the following disclaimer.
19  * 2. Redistributions in binary form must reproduce the above copyright
20  *    notice, this list of conditions and the following disclaimer in
21  *    the documentation and/or other materials provided with the
22  *    distribution.
23  *
24  * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS''
25  * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO,
26  * THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
27  * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS
28  * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
29  * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
30  * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR
31  * BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
32  * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE
33  * OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN
34  * IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
35  *
36  * Description: IB Verbs interpreter
37  */
38 
39 #include <linux/interrupt.h>
40 #include <linux/types.h>
41 #include <linux/pci.h>
42 #include <linux/netdevice.h>
43 #include <linux/if_ether.h>
44 #include <net/addrconf.h>
45 
46 #include <rdma/ib_verbs.h>
47 #include <rdma/ib_user_verbs.h>
48 #include <rdma/ib_umem.h>
49 #include <rdma/ib_addr.h>
50 #include <rdma/ib_mad.h>
51 #include <rdma/ib_cache.h>
52 #include <rdma/uverbs_ioctl.h>
53 
54 #include "bnxt_ulp.h"
55 
56 #include "roce_hsi.h"
57 #include "qplib_res.h"
58 #include "qplib_sp.h"
59 #include "qplib_fp.h"
60 #include "qplib_rcfw.h"
61 
62 #include "bnxt_re.h"
63 #include "ib_verbs.h"
64 
65 #include <rdma/uverbs_types.h>
66 #include <rdma/uverbs_std_types.h>
67 
68 #include <rdma/ib_user_ioctl_cmds.h>
69 
70 #define UVERBS_MODULE_NAME bnxt_re
71 #include <rdma/uverbs_named_ioctl.h>
72 
73 #include <rdma/bnxt_re-abi.h>
74 
75 static int __from_ib_access_flags(int iflags)
76 {
77 	int qflags = 0;
78 
79 	if (iflags & IB_ACCESS_LOCAL_WRITE)
80 		qflags |= BNXT_QPLIB_ACCESS_LOCAL_WRITE;
81 	if (iflags & IB_ACCESS_REMOTE_READ)
82 		qflags |= BNXT_QPLIB_ACCESS_REMOTE_READ;
83 	if (iflags & IB_ACCESS_REMOTE_WRITE)
84 		qflags |= BNXT_QPLIB_ACCESS_REMOTE_WRITE;
85 	if (iflags & IB_ACCESS_REMOTE_ATOMIC)
86 		qflags |= BNXT_QPLIB_ACCESS_REMOTE_ATOMIC;
87 	if (iflags & IB_ACCESS_MW_BIND)
88 		qflags |= BNXT_QPLIB_ACCESS_MW_BIND;
89 	if (iflags & IB_ZERO_BASED)
90 		qflags |= BNXT_QPLIB_ACCESS_ZERO_BASED;
91 	if (iflags & IB_ACCESS_ON_DEMAND)
92 		qflags |= BNXT_QPLIB_ACCESS_ON_DEMAND;
93 	return qflags;
94 };
95 
96 static enum ib_access_flags __to_ib_access_flags(int qflags)
97 {
98 	enum ib_access_flags iflags = 0;
99 
100 	if (qflags & BNXT_QPLIB_ACCESS_LOCAL_WRITE)
101 		iflags |= IB_ACCESS_LOCAL_WRITE;
102 	if (qflags & BNXT_QPLIB_ACCESS_REMOTE_WRITE)
103 		iflags |= IB_ACCESS_REMOTE_WRITE;
104 	if (qflags & BNXT_QPLIB_ACCESS_REMOTE_READ)
105 		iflags |= IB_ACCESS_REMOTE_READ;
106 	if (qflags & BNXT_QPLIB_ACCESS_REMOTE_ATOMIC)
107 		iflags |= IB_ACCESS_REMOTE_ATOMIC;
108 	if (qflags & BNXT_QPLIB_ACCESS_MW_BIND)
109 		iflags |= IB_ACCESS_MW_BIND;
110 	if (qflags & BNXT_QPLIB_ACCESS_ZERO_BASED)
111 		iflags |= IB_ZERO_BASED;
112 	if (qflags & BNXT_QPLIB_ACCESS_ON_DEMAND)
113 		iflags |= IB_ACCESS_ON_DEMAND;
114 	return iflags;
115 };
116 
117 static int bnxt_re_build_sgl(struct ib_sge *ib_sg_list,
118 			     struct bnxt_qplib_sge *sg_list, int num)
119 {
120 	int i, total = 0;
121 
122 	for (i = 0; i < num; i++) {
123 		sg_list[i].addr = ib_sg_list[i].addr;
124 		sg_list[i].lkey = ib_sg_list[i].lkey;
125 		sg_list[i].size = ib_sg_list[i].length;
126 		total += sg_list[i].size;
127 	}
128 	return total;
129 }
130 
131 /* Device */
132 int bnxt_re_query_device(struct ib_device *ibdev,
133 			 struct ib_device_attr *ib_attr,
134 			 struct ib_udata *udata)
135 {
136 	struct bnxt_re_dev *rdev = to_bnxt_re_dev(ibdev, ibdev);
137 	struct bnxt_qplib_dev_attr *dev_attr = &rdev->dev_attr;
138 
139 	memset(ib_attr, 0, sizeof(*ib_attr));
140 	memcpy(&ib_attr->fw_ver, dev_attr->fw_ver,
141 	       min(sizeof(dev_attr->fw_ver),
142 		   sizeof(ib_attr->fw_ver)));
143 	addrconf_addr_eui48((u8 *)&ib_attr->sys_image_guid,
144 			    rdev->netdev->dev_addr);
145 	ib_attr->max_mr_size = BNXT_RE_MAX_MR_SIZE;
146 	ib_attr->page_size_cap = BNXT_RE_PAGE_SIZE_SUPPORTED;
147 
148 	ib_attr->vendor_id = rdev->en_dev->pdev->vendor;
149 	ib_attr->vendor_part_id = rdev->en_dev->pdev->device;
150 	ib_attr->hw_ver = rdev->en_dev->pdev->subsystem_device;
151 	ib_attr->max_qp = dev_attr->max_qp;
152 	ib_attr->max_qp_wr = dev_attr->max_qp_wqes;
153 	ib_attr->device_cap_flags =
154 				    IB_DEVICE_CURR_QP_STATE_MOD
155 				    | IB_DEVICE_RC_RNR_NAK_GEN
156 				    | IB_DEVICE_SHUTDOWN_PORT
157 				    | IB_DEVICE_SYS_IMAGE_GUID
158 				    | IB_DEVICE_RESIZE_MAX_WR
159 				    | IB_DEVICE_PORT_ACTIVE_EVENT
160 				    | IB_DEVICE_N_NOTIFY_CQ
161 				    | IB_DEVICE_MEM_WINDOW
162 				    | IB_DEVICE_MEM_WINDOW_TYPE_2B
163 				    | IB_DEVICE_MEM_MGT_EXTENSIONS;
164 	ib_attr->kernel_cap_flags = IBK_LOCAL_DMA_LKEY;
165 	ib_attr->max_send_sge = dev_attr->max_qp_sges;
166 	ib_attr->max_recv_sge = dev_attr->max_qp_sges;
167 	ib_attr->max_sge_rd = dev_attr->max_qp_sges;
168 	ib_attr->max_cq = dev_attr->max_cq;
169 	ib_attr->max_cqe = dev_attr->max_cq_wqes;
170 	ib_attr->max_mr = dev_attr->max_mr;
171 	ib_attr->max_pd = dev_attr->max_pd;
172 	ib_attr->max_qp_rd_atom = dev_attr->max_qp_rd_atom;
173 	ib_attr->max_qp_init_rd_atom = dev_attr->max_qp_init_rd_atom;
174 	ib_attr->atomic_cap = IB_ATOMIC_NONE;
175 	ib_attr->masked_atomic_cap = IB_ATOMIC_NONE;
176 	if (dev_attr->is_atomic) {
177 		ib_attr->atomic_cap = IB_ATOMIC_GLOB;
178 		ib_attr->masked_atomic_cap = IB_ATOMIC_GLOB;
179 	}
180 
181 	ib_attr->max_ee_rd_atom = 0;
182 	ib_attr->max_res_rd_atom = 0;
183 	ib_attr->max_ee_init_rd_atom = 0;
184 	ib_attr->max_ee = 0;
185 	ib_attr->max_rdd = 0;
186 	ib_attr->max_mw = dev_attr->max_mw;
187 	ib_attr->max_raw_ipv6_qp = 0;
188 	ib_attr->max_raw_ethy_qp = dev_attr->max_raw_ethy_qp;
189 	ib_attr->max_mcast_grp = 0;
190 	ib_attr->max_mcast_qp_attach = 0;
191 	ib_attr->max_total_mcast_qp_attach = 0;
192 	ib_attr->max_ah = dev_attr->max_ah;
193 
194 	ib_attr->max_srq = dev_attr->max_srq;
195 	ib_attr->max_srq_wr = dev_attr->max_srq_wqes;
196 	ib_attr->max_srq_sge = dev_attr->max_srq_sges;
197 
198 	ib_attr->max_fast_reg_page_list_len = MAX_PBL_LVL_1_PGS;
199 
200 	ib_attr->max_pkeys = 1;
201 	ib_attr->local_ca_ack_delay = BNXT_RE_DEFAULT_ACK_DELAY;
202 	return 0;
203 }
204 
205 /* Port */
206 int bnxt_re_query_port(struct ib_device *ibdev, u32 port_num,
207 		       struct ib_port_attr *port_attr)
208 {
209 	struct bnxt_re_dev *rdev = to_bnxt_re_dev(ibdev, ibdev);
210 	struct bnxt_qplib_dev_attr *dev_attr = &rdev->dev_attr;
211 	int rc;
212 
213 	memset(port_attr, 0, sizeof(*port_attr));
214 
215 	if (netif_running(rdev->netdev) && netif_carrier_ok(rdev->netdev)) {
216 		port_attr->state = IB_PORT_ACTIVE;
217 		port_attr->phys_state = IB_PORT_PHYS_STATE_LINK_UP;
218 	} else {
219 		port_attr->state = IB_PORT_DOWN;
220 		port_attr->phys_state = IB_PORT_PHYS_STATE_DISABLED;
221 	}
222 	port_attr->max_mtu = IB_MTU_4096;
223 	port_attr->active_mtu = iboe_get_mtu(rdev->netdev->mtu);
224 	port_attr->gid_tbl_len = dev_attr->max_sgid;
225 	port_attr->port_cap_flags = IB_PORT_CM_SUP | IB_PORT_REINIT_SUP |
226 				    IB_PORT_DEVICE_MGMT_SUP |
227 				    IB_PORT_VENDOR_CLASS_SUP;
228 	port_attr->ip_gids = true;
229 
230 	port_attr->max_msg_sz = (u32)BNXT_RE_MAX_MR_SIZE_LOW;
231 	port_attr->bad_pkey_cntr = 0;
232 	port_attr->qkey_viol_cntr = 0;
233 	port_attr->pkey_tbl_len = dev_attr->max_pkey;
234 	port_attr->lid = 0;
235 	port_attr->sm_lid = 0;
236 	port_attr->lmc = 0;
237 	port_attr->max_vl_num = 4;
238 	port_attr->sm_sl = 0;
239 	port_attr->subnet_timeout = 0;
240 	port_attr->init_type_reply = 0;
241 	rc = ib_get_eth_speed(&rdev->ibdev, port_num, &port_attr->active_speed,
242 			      &port_attr->active_width);
243 
244 	return rc;
245 }
246 
247 int bnxt_re_get_port_immutable(struct ib_device *ibdev, u32 port_num,
248 			       struct ib_port_immutable *immutable)
249 {
250 	struct ib_port_attr port_attr;
251 
252 	if (bnxt_re_query_port(ibdev, port_num, &port_attr))
253 		return -EINVAL;
254 
255 	immutable->pkey_tbl_len = port_attr.pkey_tbl_len;
256 	immutable->gid_tbl_len = port_attr.gid_tbl_len;
257 	immutable->core_cap_flags = RDMA_CORE_PORT_IBA_ROCE;
258 	immutable->core_cap_flags |= RDMA_CORE_CAP_PROT_ROCE_UDP_ENCAP;
259 	immutable->max_mad_size = IB_MGMT_MAD_SIZE;
260 	return 0;
261 }
262 
263 void bnxt_re_query_fw_str(struct ib_device *ibdev, char *str)
264 {
265 	struct bnxt_re_dev *rdev = to_bnxt_re_dev(ibdev, ibdev);
266 
267 	snprintf(str, IB_FW_VERSION_NAME_MAX, "%d.%d.%d.%d",
268 		 rdev->dev_attr.fw_ver[0], rdev->dev_attr.fw_ver[1],
269 		 rdev->dev_attr.fw_ver[2], rdev->dev_attr.fw_ver[3]);
270 }
271 
272 int bnxt_re_query_pkey(struct ib_device *ibdev, u32 port_num,
273 		       u16 index, u16 *pkey)
274 {
275 	if (index > 0)
276 		return -EINVAL;
277 
278 	*pkey = IB_DEFAULT_PKEY_FULL;
279 
280 	return 0;
281 }
282 
283 int bnxt_re_query_gid(struct ib_device *ibdev, u32 port_num,
284 		      int index, union ib_gid *gid)
285 {
286 	struct bnxt_re_dev *rdev = to_bnxt_re_dev(ibdev, ibdev);
287 	int rc;
288 
289 	/* Ignore port_num */
290 	memset(gid, 0, sizeof(*gid));
291 	rc = bnxt_qplib_get_sgid(&rdev->qplib_res,
292 				 &rdev->qplib_res.sgid_tbl, index,
293 				 (struct bnxt_qplib_gid *)gid);
294 	return rc;
295 }
296 
297 int bnxt_re_del_gid(const struct ib_gid_attr *attr, void **context)
298 {
299 	int rc = 0;
300 	struct bnxt_re_gid_ctx *ctx, **ctx_tbl;
301 	struct bnxt_re_dev *rdev = to_bnxt_re_dev(attr->device, ibdev);
302 	struct bnxt_qplib_sgid_tbl *sgid_tbl = &rdev->qplib_res.sgid_tbl;
303 	struct bnxt_qplib_gid *gid_to_del;
304 	u16 vlan_id = 0xFFFF;
305 
306 	/* Delete the entry from the hardware */
307 	ctx = *context;
308 	if (!ctx)
309 		return -EINVAL;
310 
311 	if (sgid_tbl && sgid_tbl->active) {
312 		if (ctx->idx >= sgid_tbl->max)
313 			return -EINVAL;
314 		gid_to_del = &sgid_tbl->tbl[ctx->idx].gid;
315 		vlan_id = sgid_tbl->tbl[ctx->idx].vlan_id;
316 		/* DEL_GID is called in WQ context(netdevice_event_work_handler)
317 		 * or via the ib_unregister_device path. In the former case QP1
318 		 * may not be destroyed yet, in which case just return as FW
319 		 * needs that entry to be present and will fail it's deletion.
320 		 * We could get invoked again after QP1 is destroyed OR get an
321 		 * ADD_GID call with a different GID value for the same index
322 		 * where we issue MODIFY_GID cmd to update the GID entry -- TBD
323 		 */
324 		if (ctx->idx == 0 &&
325 		    rdma_link_local_addr((struct in6_addr *)gid_to_del) &&
326 		    ctx->refcnt == 1 && rdev->gsi_ctx.gsi_sqp) {
327 			ibdev_dbg(&rdev->ibdev,
328 				  "Trying to delete GID0 while QP1 is alive\n");
329 			return -EFAULT;
330 		}
331 		ctx->refcnt--;
332 		if (!ctx->refcnt) {
333 			rc = bnxt_qplib_del_sgid(sgid_tbl, gid_to_del,
334 						 vlan_id,  true);
335 			if (rc) {
336 				ibdev_err(&rdev->ibdev,
337 					  "Failed to remove GID: %#x", rc);
338 			} else {
339 				ctx_tbl = sgid_tbl->ctx;
340 				ctx_tbl[ctx->idx] = NULL;
341 				kfree(ctx);
342 			}
343 		}
344 	} else {
345 		return -EINVAL;
346 	}
347 	return rc;
348 }
349 
350 int bnxt_re_add_gid(const struct ib_gid_attr *attr, void **context)
351 {
352 	int rc;
353 	u32 tbl_idx = 0;
354 	u16 vlan_id = 0xFFFF;
355 	struct bnxt_re_gid_ctx *ctx, **ctx_tbl;
356 	struct bnxt_re_dev *rdev = to_bnxt_re_dev(attr->device, ibdev);
357 	struct bnxt_qplib_sgid_tbl *sgid_tbl = &rdev->qplib_res.sgid_tbl;
358 
359 	rc = rdma_read_gid_l2_fields(attr, &vlan_id, NULL);
360 	if (rc)
361 		return rc;
362 
363 	rc = bnxt_qplib_add_sgid(sgid_tbl, (struct bnxt_qplib_gid *)&attr->gid,
364 				 rdev->qplib_res.netdev->dev_addr,
365 				 vlan_id, true, &tbl_idx);
366 	if (rc == -EALREADY) {
367 		ctx_tbl = sgid_tbl->ctx;
368 		ctx_tbl[tbl_idx]->refcnt++;
369 		*context = ctx_tbl[tbl_idx];
370 		return 0;
371 	}
372 
373 	if (rc < 0) {
374 		ibdev_err(&rdev->ibdev, "Failed to add GID: %#x", rc);
375 		return rc;
376 	}
377 
378 	ctx = kmalloc(sizeof(*ctx), GFP_KERNEL);
379 	if (!ctx)
380 		return -ENOMEM;
381 	ctx_tbl = sgid_tbl->ctx;
382 	ctx->idx = tbl_idx;
383 	ctx->refcnt = 1;
384 	ctx_tbl[tbl_idx] = ctx;
385 	*context = ctx;
386 
387 	return rc;
388 }
389 
390 enum rdma_link_layer bnxt_re_get_link_layer(struct ib_device *ibdev,
391 					    u32 port_num)
392 {
393 	return IB_LINK_LAYER_ETHERNET;
394 }
395 
396 #define	BNXT_RE_FENCE_PBL_SIZE	DIV_ROUND_UP(BNXT_RE_FENCE_BYTES, PAGE_SIZE)
397 
398 static void bnxt_re_create_fence_wqe(struct bnxt_re_pd *pd)
399 {
400 	struct bnxt_re_fence_data *fence = &pd->fence;
401 	struct ib_mr *ib_mr = &fence->mr->ib_mr;
402 	struct bnxt_qplib_swqe *wqe = &fence->bind_wqe;
403 
404 	memset(wqe, 0, sizeof(*wqe));
405 	wqe->type = BNXT_QPLIB_SWQE_TYPE_BIND_MW;
406 	wqe->wr_id = BNXT_QPLIB_FENCE_WRID;
407 	wqe->flags |= BNXT_QPLIB_SWQE_FLAGS_SIGNAL_COMP;
408 	wqe->flags |= BNXT_QPLIB_SWQE_FLAGS_UC_FENCE;
409 	wqe->bind.zero_based = false;
410 	wqe->bind.parent_l_key = ib_mr->lkey;
411 	wqe->bind.va = (u64)(unsigned long)fence->va;
412 	wqe->bind.length = fence->size;
413 	wqe->bind.access_cntl = __from_ib_access_flags(IB_ACCESS_REMOTE_READ);
414 	wqe->bind.mw_type = SQ_BIND_MW_TYPE_TYPE1;
415 
416 	/* Save the initial rkey in fence structure for now;
417 	 * wqe->bind.r_key will be set at (re)bind time.
418 	 */
419 	fence->bind_rkey = ib_inc_rkey(fence->mw->rkey);
420 }
421 
422 static int bnxt_re_bind_fence_mw(struct bnxt_qplib_qp *qplib_qp)
423 {
424 	struct bnxt_re_qp *qp = container_of(qplib_qp, struct bnxt_re_qp,
425 					     qplib_qp);
426 	struct ib_pd *ib_pd = qp->ib_qp.pd;
427 	struct bnxt_re_pd *pd = container_of(ib_pd, struct bnxt_re_pd, ib_pd);
428 	struct bnxt_re_fence_data *fence = &pd->fence;
429 	struct bnxt_qplib_swqe *fence_wqe = &fence->bind_wqe;
430 	struct bnxt_qplib_swqe wqe;
431 	int rc;
432 
433 	memcpy(&wqe, fence_wqe, sizeof(wqe));
434 	wqe.bind.r_key = fence->bind_rkey;
435 	fence->bind_rkey = ib_inc_rkey(fence->bind_rkey);
436 
437 	ibdev_dbg(&qp->rdev->ibdev,
438 		  "Posting bind fence-WQE: rkey: %#x QP: %d PD: %p\n",
439 		wqe.bind.r_key, qp->qplib_qp.id, pd);
440 	rc = bnxt_qplib_post_send(&qp->qplib_qp, &wqe);
441 	if (rc) {
442 		ibdev_err(&qp->rdev->ibdev, "Failed to bind fence-WQE\n");
443 		return rc;
444 	}
445 	bnxt_qplib_post_send_db(&qp->qplib_qp);
446 
447 	return rc;
448 }
449 
450 static void bnxt_re_destroy_fence_mr(struct bnxt_re_pd *pd)
451 {
452 	struct bnxt_re_fence_data *fence = &pd->fence;
453 	struct bnxt_re_dev *rdev = pd->rdev;
454 	struct device *dev = &rdev->en_dev->pdev->dev;
455 	struct bnxt_re_mr *mr = fence->mr;
456 
457 	if (fence->mw) {
458 		bnxt_re_dealloc_mw(fence->mw);
459 		fence->mw = NULL;
460 	}
461 	if (mr) {
462 		if (mr->ib_mr.rkey)
463 			bnxt_qplib_dereg_mrw(&rdev->qplib_res, &mr->qplib_mr,
464 					     true);
465 		if (mr->ib_mr.lkey)
466 			bnxt_qplib_free_mrw(&rdev->qplib_res, &mr->qplib_mr);
467 		kfree(mr);
468 		fence->mr = NULL;
469 	}
470 	if (fence->dma_addr) {
471 		dma_unmap_single(dev, fence->dma_addr, BNXT_RE_FENCE_BYTES,
472 				 DMA_BIDIRECTIONAL);
473 		fence->dma_addr = 0;
474 	}
475 }
476 
477 static int bnxt_re_create_fence_mr(struct bnxt_re_pd *pd)
478 {
479 	int mr_access_flags = IB_ACCESS_LOCAL_WRITE | IB_ACCESS_MW_BIND;
480 	struct bnxt_re_fence_data *fence = &pd->fence;
481 	struct bnxt_re_dev *rdev = pd->rdev;
482 	struct device *dev = &rdev->en_dev->pdev->dev;
483 	struct bnxt_re_mr *mr = NULL;
484 	dma_addr_t dma_addr = 0;
485 	struct ib_mw *mw;
486 	int rc;
487 
488 	dma_addr = dma_map_single(dev, fence->va, BNXT_RE_FENCE_BYTES,
489 				  DMA_BIDIRECTIONAL);
490 	rc = dma_mapping_error(dev, dma_addr);
491 	if (rc) {
492 		ibdev_err(&rdev->ibdev, "Failed to dma-map fence-MR-mem\n");
493 		rc = -EIO;
494 		fence->dma_addr = 0;
495 		goto fail;
496 	}
497 	fence->dma_addr = dma_addr;
498 
499 	/* Allocate a MR */
500 	mr = kzalloc(sizeof(*mr), GFP_KERNEL);
501 	if (!mr) {
502 		rc = -ENOMEM;
503 		goto fail;
504 	}
505 	fence->mr = mr;
506 	mr->rdev = rdev;
507 	mr->qplib_mr.pd = &pd->qplib_pd;
508 	mr->qplib_mr.type = CMDQ_ALLOCATE_MRW_MRW_FLAGS_PMR;
509 	mr->qplib_mr.flags = __from_ib_access_flags(mr_access_flags);
510 	rc = bnxt_qplib_alloc_mrw(&rdev->qplib_res, &mr->qplib_mr);
511 	if (rc) {
512 		ibdev_err(&rdev->ibdev, "Failed to alloc fence-HW-MR\n");
513 		goto fail;
514 	}
515 
516 	/* Register MR */
517 	mr->ib_mr.lkey = mr->qplib_mr.lkey;
518 	mr->qplib_mr.va = (u64)(unsigned long)fence->va;
519 	mr->qplib_mr.total_size = BNXT_RE_FENCE_BYTES;
520 	rc = bnxt_qplib_reg_mr(&rdev->qplib_res, &mr->qplib_mr, NULL,
521 			       BNXT_RE_FENCE_PBL_SIZE, PAGE_SIZE);
522 	if (rc) {
523 		ibdev_err(&rdev->ibdev, "Failed to register fence-MR\n");
524 		goto fail;
525 	}
526 	mr->ib_mr.rkey = mr->qplib_mr.rkey;
527 
528 	/* Create a fence MW only for kernel consumers */
529 	mw = bnxt_re_alloc_mw(&pd->ib_pd, IB_MW_TYPE_1, NULL);
530 	if (IS_ERR(mw)) {
531 		ibdev_err(&rdev->ibdev,
532 			  "Failed to create fence-MW for PD: %p\n", pd);
533 		rc = PTR_ERR(mw);
534 		goto fail;
535 	}
536 	fence->mw = mw;
537 
538 	bnxt_re_create_fence_wqe(pd);
539 	return 0;
540 
541 fail:
542 	bnxt_re_destroy_fence_mr(pd);
543 	return rc;
544 }
545 
546 static struct bnxt_re_user_mmap_entry*
547 bnxt_re_mmap_entry_insert(struct bnxt_re_ucontext *uctx, u64 mem_offset,
548 			  enum bnxt_re_mmap_flag mmap_flag, u64 *offset)
549 {
550 	struct bnxt_re_user_mmap_entry *entry;
551 	int ret;
552 
553 	entry = kzalloc(sizeof(*entry), GFP_KERNEL);
554 	if (!entry)
555 		return NULL;
556 
557 	entry->mem_offset = mem_offset;
558 	entry->mmap_flag = mmap_flag;
559 	entry->uctx = uctx;
560 
561 	switch (mmap_flag) {
562 	case BNXT_RE_MMAP_SH_PAGE:
563 		ret = rdma_user_mmap_entry_insert_exact(&uctx->ib_uctx,
564 							&entry->rdma_entry, PAGE_SIZE, 0);
565 		break;
566 	case BNXT_RE_MMAP_UC_DB:
567 	case BNXT_RE_MMAP_WC_DB:
568 	case BNXT_RE_MMAP_DBR_BAR:
569 	case BNXT_RE_MMAP_DBR_PAGE:
570 		ret = rdma_user_mmap_entry_insert(&uctx->ib_uctx,
571 						  &entry->rdma_entry, PAGE_SIZE);
572 		break;
573 	default:
574 		ret = -EINVAL;
575 		break;
576 	}
577 
578 	if (ret) {
579 		kfree(entry);
580 		return NULL;
581 	}
582 	if (offset)
583 		*offset = rdma_user_mmap_get_offset(&entry->rdma_entry);
584 
585 	return entry;
586 }
587 
588 /* Protection Domains */
589 int bnxt_re_dealloc_pd(struct ib_pd *ib_pd, struct ib_udata *udata)
590 {
591 	struct bnxt_re_pd *pd = container_of(ib_pd, struct bnxt_re_pd, ib_pd);
592 	struct bnxt_re_dev *rdev = pd->rdev;
593 
594 	if (udata) {
595 		rdma_user_mmap_entry_remove(pd->pd_db_mmap);
596 		pd->pd_db_mmap = NULL;
597 	}
598 
599 	bnxt_re_destroy_fence_mr(pd);
600 
601 	if (pd->qplib_pd.id) {
602 		if (!bnxt_qplib_dealloc_pd(&rdev->qplib_res,
603 					   &rdev->qplib_res.pd_tbl,
604 					   &pd->qplib_pd))
605 			atomic_dec(&rdev->stats.res.pd_count);
606 	}
607 	return 0;
608 }
609 
610 int bnxt_re_alloc_pd(struct ib_pd *ibpd, struct ib_udata *udata)
611 {
612 	struct ib_device *ibdev = ibpd->device;
613 	struct bnxt_re_dev *rdev = to_bnxt_re_dev(ibdev, ibdev);
614 	struct bnxt_re_ucontext *ucntx = rdma_udata_to_drv_context(
615 		udata, struct bnxt_re_ucontext, ib_uctx);
616 	struct bnxt_re_pd *pd = container_of(ibpd, struct bnxt_re_pd, ib_pd);
617 	struct bnxt_re_user_mmap_entry *entry = NULL;
618 	u32 active_pds;
619 	int rc = 0;
620 
621 	pd->rdev = rdev;
622 	if (bnxt_qplib_alloc_pd(&rdev->qplib_res, &pd->qplib_pd)) {
623 		ibdev_err(&rdev->ibdev, "Failed to allocate HW PD");
624 		rc = -ENOMEM;
625 		goto fail;
626 	}
627 
628 	if (udata) {
629 		struct bnxt_re_pd_resp resp = {};
630 
631 		if (!ucntx->dpi.dbr) {
632 			/* Allocate DPI in alloc_pd to avoid failing of
633 			 * ibv_devinfo and family of application when DPIs
634 			 * are depleted.
635 			 */
636 			if (bnxt_qplib_alloc_dpi(&rdev->qplib_res,
637 						 &ucntx->dpi, ucntx, BNXT_QPLIB_DPI_TYPE_UC)) {
638 				rc = -ENOMEM;
639 				goto dbfail;
640 			}
641 		}
642 
643 		resp.pdid = pd->qplib_pd.id;
644 		/* Still allow mapping this DBR to the new user PD. */
645 		resp.dpi = ucntx->dpi.dpi;
646 
647 		entry = bnxt_re_mmap_entry_insert(ucntx, (u64)ucntx->dpi.umdbr,
648 						  BNXT_RE_MMAP_UC_DB, &resp.dbr);
649 
650 		if (!entry) {
651 			rc = -ENOMEM;
652 			goto dbfail;
653 		}
654 
655 		pd->pd_db_mmap = &entry->rdma_entry;
656 
657 		rc = ib_copy_to_udata(udata, &resp, min(sizeof(resp), udata->outlen));
658 		if (rc) {
659 			rdma_user_mmap_entry_remove(pd->pd_db_mmap);
660 			rc = -EFAULT;
661 			goto dbfail;
662 		}
663 	}
664 
665 	if (!udata)
666 		if (bnxt_re_create_fence_mr(pd))
667 			ibdev_warn(&rdev->ibdev,
668 				   "Failed to create Fence-MR\n");
669 	active_pds = atomic_inc_return(&rdev->stats.res.pd_count);
670 	if (active_pds > rdev->stats.res.pd_watermark)
671 		rdev->stats.res.pd_watermark = active_pds;
672 
673 	return 0;
674 dbfail:
675 	bnxt_qplib_dealloc_pd(&rdev->qplib_res, &rdev->qplib_res.pd_tbl,
676 			      &pd->qplib_pd);
677 fail:
678 	return rc;
679 }
680 
681 /* Address Handles */
682 int bnxt_re_destroy_ah(struct ib_ah *ib_ah, u32 flags)
683 {
684 	struct bnxt_re_ah *ah = container_of(ib_ah, struct bnxt_re_ah, ib_ah);
685 	struct bnxt_re_dev *rdev = ah->rdev;
686 	bool block = true;
687 	int rc;
688 
689 	block = !(flags & RDMA_DESTROY_AH_SLEEPABLE);
690 	rc = bnxt_qplib_destroy_ah(&rdev->qplib_res, &ah->qplib_ah, block);
691 	if (BNXT_RE_CHECK_RC(rc)) {
692 		if (rc == -ETIMEDOUT)
693 			rc = 0;
694 		else
695 			goto fail;
696 	}
697 	atomic_dec(&rdev->stats.res.ah_count);
698 fail:
699 	return rc;
700 }
701 
702 static u8 bnxt_re_stack_to_dev_nw_type(enum rdma_network_type ntype)
703 {
704 	u8 nw_type;
705 
706 	switch (ntype) {
707 	case RDMA_NETWORK_IPV4:
708 		nw_type = CMDQ_CREATE_AH_TYPE_V2IPV4;
709 		break;
710 	case RDMA_NETWORK_IPV6:
711 		nw_type = CMDQ_CREATE_AH_TYPE_V2IPV6;
712 		break;
713 	default:
714 		nw_type = CMDQ_CREATE_AH_TYPE_V1;
715 		break;
716 	}
717 	return nw_type;
718 }
719 
720 int bnxt_re_create_ah(struct ib_ah *ib_ah, struct rdma_ah_init_attr *init_attr,
721 		      struct ib_udata *udata)
722 {
723 	struct ib_pd *ib_pd = ib_ah->pd;
724 	struct bnxt_re_pd *pd = container_of(ib_pd, struct bnxt_re_pd, ib_pd);
725 	struct rdma_ah_attr *ah_attr = init_attr->ah_attr;
726 	const struct ib_global_route *grh = rdma_ah_read_grh(ah_attr);
727 	struct bnxt_re_dev *rdev = pd->rdev;
728 	const struct ib_gid_attr *sgid_attr;
729 	struct bnxt_re_gid_ctx *ctx;
730 	struct bnxt_re_ah *ah = container_of(ib_ah, struct bnxt_re_ah, ib_ah);
731 	u32 active_ahs;
732 	u8 nw_type;
733 	int rc;
734 
735 	if (!(rdma_ah_get_ah_flags(ah_attr) & IB_AH_GRH)) {
736 		ibdev_err(&rdev->ibdev, "Failed to alloc AH: GRH not set");
737 		return -EINVAL;
738 	}
739 
740 	ah->rdev = rdev;
741 	ah->qplib_ah.pd = &pd->qplib_pd;
742 
743 	/* Supply the configuration for the HW */
744 	memcpy(ah->qplib_ah.dgid.data, grh->dgid.raw,
745 	       sizeof(union ib_gid));
746 	sgid_attr = grh->sgid_attr;
747 	/* Get the HW context of the GID. The reference
748 	 * of GID table entry is already taken by the caller.
749 	 */
750 	ctx = rdma_read_gid_hw_context(sgid_attr);
751 	ah->qplib_ah.sgid_index = ctx->idx;
752 	ah->qplib_ah.host_sgid_index = grh->sgid_index;
753 	ah->qplib_ah.traffic_class = grh->traffic_class;
754 	ah->qplib_ah.flow_label = grh->flow_label;
755 	ah->qplib_ah.hop_limit = grh->hop_limit;
756 	ah->qplib_ah.sl = rdma_ah_get_sl(ah_attr);
757 
758 	/* Get network header type for this GID */
759 	nw_type = rdma_gid_attr_network_type(sgid_attr);
760 	ah->qplib_ah.nw_type = bnxt_re_stack_to_dev_nw_type(nw_type);
761 
762 	memcpy(ah->qplib_ah.dmac, ah_attr->roce.dmac, ETH_ALEN);
763 	rc = bnxt_qplib_create_ah(&rdev->qplib_res, &ah->qplib_ah,
764 				  !(init_attr->flags &
765 				    RDMA_CREATE_AH_SLEEPABLE));
766 	if (rc) {
767 		ibdev_err(&rdev->ibdev, "Failed to allocate HW AH");
768 		return rc;
769 	}
770 
771 	/* Write AVID to shared page. */
772 	if (udata) {
773 		struct bnxt_re_ucontext *uctx = rdma_udata_to_drv_context(
774 			udata, struct bnxt_re_ucontext, ib_uctx);
775 		unsigned long flag;
776 		u32 *wrptr;
777 
778 		spin_lock_irqsave(&uctx->sh_lock, flag);
779 		wrptr = (u32 *)(uctx->shpg + BNXT_RE_AVID_OFFT);
780 		*wrptr = ah->qplib_ah.id;
781 		wmb(); /* make sure cache is updated. */
782 		spin_unlock_irqrestore(&uctx->sh_lock, flag);
783 	}
784 	active_ahs = atomic_inc_return(&rdev->stats.res.ah_count);
785 	if (active_ahs > rdev->stats.res.ah_watermark)
786 		rdev->stats.res.ah_watermark = active_ahs;
787 
788 	return 0;
789 }
790 
791 int bnxt_re_query_ah(struct ib_ah *ib_ah, struct rdma_ah_attr *ah_attr)
792 {
793 	struct bnxt_re_ah *ah = container_of(ib_ah, struct bnxt_re_ah, ib_ah);
794 
795 	ah_attr->type = ib_ah->type;
796 	rdma_ah_set_sl(ah_attr, ah->qplib_ah.sl);
797 	memcpy(ah_attr->roce.dmac, ah->qplib_ah.dmac, ETH_ALEN);
798 	rdma_ah_set_grh(ah_attr, NULL, 0,
799 			ah->qplib_ah.host_sgid_index,
800 			0, ah->qplib_ah.traffic_class);
801 	rdma_ah_set_dgid_raw(ah_attr, ah->qplib_ah.dgid.data);
802 	rdma_ah_set_port_num(ah_attr, 1);
803 	rdma_ah_set_static_rate(ah_attr, 0);
804 	return 0;
805 }
806 
807 unsigned long bnxt_re_lock_cqs(struct bnxt_re_qp *qp)
808 	__acquires(&qp->scq->cq_lock) __acquires(&qp->rcq->cq_lock)
809 {
810 	unsigned long flags;
811 
812 	spin_lock_irqsave(&qp->scq->cq_lock, flags);
813 	if (qp->rcq != qp->scq)
814 		spin_lock(&qp->rcq->cq_lock);
815 	else
816 		__acquire(&qp->rcq->cq_lock);
817 
818 	return flags;
819 }
820 
821 void bnxt_re_unlock_cqs(struct bnxt_re_qp *qp,
822 			unsigned long flags)
823 	__releases(&qp->scq->cq_lock) __releases(&qp->rcq->cq_lock)
824 {
825 	if (qp->rcq != qp->scq)
826 		spin_unlock(&qp->rcq->cq_lock);
827 	else
828 		__release(&qp->rcq->cq_lock);
829 	spin_unlock_irqrestore(&qp->scq->cq_lock, flags);
830 }
831 
832 static int bnxt_re_destroy_gsi_sqp(struct bnxt_re_qp *qp)
833 {
834 	struct bnxt_re_qp *gsi_sqp;
835 	struct bnxt_re_ah *gsi_sah;
836 	struct bnxt_re_dev *rdev;
837 	int rc;
838 
839 	rdev = qp->rdev;
840 	gsi_sqp = rdev->gsi_ctx.gsi_sqp;
841 	gsi_sah = rdev->gsi_ctx.gsi_sah;
842 
843 	ibdev_dbg(&rdev->ibdev, "Destroy the shadow AH\n");
844 	bnxt_qplib_destroy_ah(&rdev->qplib_res,
845 			      &gsi_sah->qplib_ah,
846 			      true);
847 	atomic_dec(&rdev->stats.res.ah_count);
848 	bnxt_qplib_clean_qp(&qp->qplib_qp);
849 
850 	ibdev_dbg(&rdev->ibdev, "Destroy the shadow QP\n");
851 	rc = bnxt_qplib_destroy_qp(&rdev->qplib_res, &gsi_sqp->qplib_qp);
852 	if (rc) {
853 		ibdev_err(&rdev->ibdev, "Destroy Shadow QP failed");
854 		goto fail;
855 	}
856 	bnxt_qplib_free_qp_res(&rdev->qplib_res, &gsi_sqp->qplib_qp);
857 
858 	/* remove from active qp list */
859 	mutex_lock(&rdev->qp_lock);
860 	list_del(&gsi_sqp->list);
861 	mutex_unlock(&rdev->qp_lock);
862 	atomic_dec(&rdev->stats.res.qp_count);
863 
864 	kfree(rdev->gsi_ctx.sqp_tbl);
865 	kfree(gsi_sah);
866 	kfree(gsi_sqp);
867 	rdev->gsi_ctx.gsi_sqp = NULL;
868 	rdev->gsi_ctx.gsi_sah = NULL;
869 	rdev->gsi_ctx.sqp_tbl = NULL;
870 
871 	return 0;
872 fail:
873 	return rc;
874 }
875 
876 /* Queue Pairs */
877 int bnxt_re_destroy_qp(struct ib_qp *ib_qp, struct ib_udata *udata)
878 {
879 	struct bnxt_re_qp *qp = container_of(ib_qp, struct bnxt_re_qp, ib_qp);
880 	struct bnxt_qplib_qp *qplib_qp = &qp->qplib_qp;
881 	struct bnxt_re_dev *rdev = qp->rdev;
882 	struct bnxt_qplib_nq *scq_nq = NULL;
883 	struct bnxt_qplib_nq *rcq_nq = NULL;
884 	unsigned int flags;
885 	int rc;
886 
887 	bnxt_qplib_flush_cqn_wq(&qp->qplib_qp);
888 
889 	rc = bnxt_qplib_destroy_qp(&rdev->qplib_res, &qp->qplib_qp);
890 	if (rc) {
891 		ibdev_err(&rdev->ibdev, "Failed to destroy HW QP");
892 		return rc;
893 	}
894 
895 	if (rdma_is_kernel_res(&qp->ib_qp.res)) {
896 		flags = bnxt_re_lock_cqs(qp);
897 		bnxt_qplib_clean_qp(&qp->qplib_qp);
898 		bnxt_re_unlock_cqs(qp, flags);
899 	}
900 
901 	bnxt_qplib_free_qp_res(&rdev->qplib_res, &qp->qplib_qp);
902 
903 	if (ib_qp->qp_type == IB_QPT_GSI && rdev->gsi_ctx.gsi_sqp) {
904 		rc = bnxt_re_destroy_gsi_sqp(qp);
905 		if (rc)
906 			return rc;
907 	}
908 
909 	mutex_lock(&rdev->qp_lock);
910 	list_del(&qp->list);
911 	mutex_unlock(&rdev->qp_lock);
912 	atomic_dec(&rdev->stats.res.qp_count);
913 	if (qp->qplib_qp.type == CMDQ_CREATE_QP_TYPE_RC)
914 		atomic_dec(&rdev->stats.res.rc_qp_count);
915 	else if (qp->qplib_qp.type == CMDQ_CREATE_QP_TYPE_UD)
916 		atomic_dec(&rdev->stats.res.ud_qp_count);
917 
918 	ib_umem_release(qp->rumem);
919 	ib_umem_release(qp->sumem);
920 
921 	/* Flush all the entries of notification queue associated with
922 	 * given qp.
923 	 */
924 	scq_nq = qplib_qp->scq->nq;
925 	rcq_nq = qplib_qp->rcq->nq;
926 	bnxt_re_synchronize_nq(scq_nq);
927 	if (scq_nq != rcq_nq)
928 		bnxt_re_synchronize_nq(rcq_nq);
929 
930 	return 0;
931 }
932 
933 static u8 __from_ib_qp_type(enum ib_qp_type type)
934 {
935 	switch (type) {
936 	case IB_QPT_GSI:
937 		return CMDQ_CREATE_QP1_TYPE_GSI;
938 	case IB_QPT_RC:
939 		return CMDQ_CREATE_QP_TYPE_RC;
940 	case IB_QPT_UD:
941 		return CMDQ_CREATE_QP_TYPE_UD;
942 	default:
943 		return IB_QPT_MAX;
944 	}
945 }
946 
947 static u16 bnxt_re_setup_rwqe_size(struct bnxt_qplib_qp *qplqp,
948 				   int rsge, int max)
949 {
950 	if (qplqp->wqe_mode == BNXT_QPLIB_WQE_MODE_STATIC)
951 		rsge = max;
952 	return bnxt_re_get_rwqe_size(rsge);
953 }
954 
955 static u16 bnxt_re_get_wqe_size(int ilsize, int nsge)
956 {
957 	u16 wqe_size, calc_ils;
958 
959 	wqe_size = bnxt_re_get_swqe_size(nsge);
960 	if (ilsize) {
961 		calc_ils = sizeof(struct sq_send_hdr) + ilsize;
962 		wqe_size = max_t(u16, calc_ils, wqe_size);
963 		wqe_size = ALIGN(wqe_size, sizeof(struct sq_send_hdr));
964 	}
965 	return wqe_size;
966 }
967 
968 static int bnxt_re_setup_swqe_size(struct bnxt_re_qp *qp,
969 				   struct ib_qp_init_attr *init_attr)
970 {
971 	struct bnxt_qplib_dev_attr *dev_attr;
972 	struct bnxt_qplib_qp *qplqp;
973 	struct bnxt_re_dev *rdev;
974 	struct bnxt_qplib_q *sq;
975 	int align, ilsize;
976 
977 	rdev = qp->rdev;
978 	qplqp = &qp->qplib_qp;
979 	sq = &qplqp->sq;
980 	dev_attr = &rdev->dev_attr;
981 
982 	align = sizeof(struct sq_send_hdr);
983 	ilsize = ALIGN(init_attr->cap.max_inline_data, align);
984 
985 	sq->wqe_size = bnxt_re_get_wqe_size(ilsize, sq->max_sge);
986 	if (sq->wqe_size > bnxt_re_get_swqe_size(dev_attr->max_qp_sges))
987 		return -EINVAL;
988 	/* For gen p4 and gen p5 backward compatibility mode
989 	 * wqe size is fixed to 128 bytes
990 	 */
991 	if (sq->wqe_size < bnxt_re_get_swqe_size(dev_attr->max_qp_sges) &&
992 			qplqp->wqe_mode == BNXT_QPLIB_WQE_MODE_STATIC)
993 		sq->wqe_size = bnxt_re_get_swqe_size(dev_attr->max_qp_sges);
994 
995 	if (init_attr->cap.max_inline_data) {
996 		qplqp->max_inline_data = sq->wqe_size -
997 			sizeof(struct sq_send_hdr);
998 		init_attr->cap.max_inline_data = qplqp->max_inline_data;
999 		if (qplqp->wqe_mode == BNXT_QPLIB_WQE_MODE_STATIC)
1000 			sq->max_sge = qplqp->max_inline_data /
1001 				sizeof(struct sq_sge);
1002 	}
1003 
1004 	return 0;
1005 }
1006 
1007 static int bnxt_re_init_user_qp(struct bnxt_re_dev *rdev, struct bnxt_re_pd *pd,
1008 				struct bnxt_re_qp *qp, struct ib_udata *udata)
1009 {
1010 	struct bnxt_qplib_qp *qplib_qp;
1011 	struct bnxt_re_ucontext *cntx;
1012 	struct bnxt_re_qp_req ureq;
1013 	int bytes = 0, psn_sz;
1014 	struct ib_umem *umem;
1015 	int psn_nume;
1016 
1017 	qplib_qp = &qp->qplib_qp;
1018 	cntx = rdma_udata_to_drv_context(udata, struct bnxt_re_ucontext,
1019 					 ib_uctx);
1020 	if (ib_copy_from_udata(&ureq, udata, sizeof(ureq)))
1021 		return -EFAULT;
1022 
1023 	bytes = (qplib_qp->sq.max_wqe * qplib_qp->sq.wqe_size);
1024 	/* Consider mapping PSN search memory only for RC QPs. */
1025 	if (qplib_qp->type == CMDQ_CREATE_QP_TYPE_RC) {
1026 		psn_sz = bnxt_qplib_is_chip_gen_p5(rdev->chip_ctx) ?
1027 						   sizeof(struct sq_psn_search_ext) :
1028 						   sizeof(struct sq_psn_search);
1029 		psn_nume = (qplib_qp->wqe_mode == BNXT_QPLIB_WQE_MODE_STATIC) ?
1030 			    qplib_qp->sq.max_wqe :
1031 			    ((qplib_qp->sq.max_wqe * qplib_qp->sq.wqe_size) /
1032 			      sizeof(struct bnxt_qplib_sge));
1033 		bytes += (psn_nume * psn_sz);
1034 	}
1035 
1036 	bytes = PAGE_ALIGN(bytes);
1037 	umem = ib_umem_get(&rdev->ibdev, ureq.qpsva, bytes,
1038 			   IB_ACCESS_LOCAL_WRITE);
1039 	if (IS_ERR(umem))
1040 		return PTR_ERR(umem);
1041 
1042 	qp->sumem = umem;
1043 	qplib_qp->sq.sg_info.umem = umem;
1044 	qplib_qp->sq.sg_info.pgsize = PAGE_SIZE;
1045 	qplib_qp->sq.sg_info.pgshft = PAGE_SHIFT;
1046 	qplib_qp->qp_handle = ureq.qp_handle;
1047 
1048 	if (!qp->qplib_qp.srq) {
1049 		bytes = (qplib_qp->rq.max_wqe * qplib_qp->rq.wqe_size);
1050 		bytes = PAGE_ALIGN(bytes);
1051 		umem = ib_umem_get(&rdev->ibdev, ureq.qprva, bytes,
1052 				   IB_ACCESS_LOCAL_WRITE);
1053 		if (IS_ERR(umem))
1054 			goto rqfail;
1055 		qp->rumem = umem;
1056 		qplib_qp->rq.sg_info.umem = umem;
1057 		qplib_qp->rq.sg_info.pgsize = PAGE_SIZE;
1058 		qplib_qp->rq.sg_info.pgshft = PAGE_SHIFT;
1059 	}
1060 
1061 	qplib_qp->dpi = &cntx->dpi;
1062 	return 0;
1063 rqfail:
1064 	ib_umem_release(qp->sumem);
1065 	qp->sumem = NULL;
1066 	memset(&qplib_qp->sq.sg_info, 0, sizeof(qplib_qp->sq.sg_info));
1067 
1068 	return PTR_ERR(umem);
1069 }
1070 
1071 static struct bnxt_re_ah *bnxt_re_create_shadow_qp_ah
1072 				(struct bnxt_re_pd *pd,
1073 				 struct bnxt_qplib_res *qp1_res,
1074 				 struct bnxt_qplib_qp *qp1_qp)
1075 {
1076 	struct bnxt_re_dev *rdev = pd->rdev;
1077 	struct bnxt_re_ah *ah;
1078 	union ib_gid sgid;
1079 	int rc;
1080 
1081 	ah = kzalloc(sizeof(*ah), GFP_KERNEL);
1082 	if (!ah)
1083 		return NULL;
1084 
1085 	ah->rdev = rdev;
1086 	ah->qplib_ah.pd = &pd->qplib_pd;
1087 
1088 	rc = bnxt_re_query_gid(&rdev->ibdev, 1, 0, &sgid);
1089 	if (rc)
1090 		goto fail;
1091 
1092 	/* supply the dgid data same as sgid */
1093 	memcpy(ah->qplib_ah.dgid.data, &sgid.raw,
1094 	       sizeof(union ib_gid));
1095 	ah->qplib_ah.sgid_index = 0;
1096 
1097 	ah->qplib_ah.traffic_class = 0;
1098 	ah->qplib_ah.flow_label = 0;
1099 	ah->qplib_ah.hop_limit = 1;
1100 	ah->qplib_ah.sl = 0;
1101 	/* Have DMAC same as SMAC */
1102 	ether_addr_copy(ah->qplib_ah.dmac, rdev->netdev->dev_addr);
1103 
1104 	rc = bnxt_qplib_create_ah(&rdev->qplib_res, &ah->qplib_ah, false);
1105 	if (rc) {
1106 		ibdev_err(&rdev->ibdev,
1107 			  "Failed to allocate HW AH for Shadow QP");
1108 		goto fail;
1109 	}
1110 	atomic_inc(&rdev->stats.res.ah_count);
1111 
1112 	return ah;
1113 
1114 fail:
1115 	kfree(ah);
1116 	return NULL;
1117 }
1118 
1119 static struct bnxt_re_qp *bnxt_re_create_shadow_qp
1120 				(struct bnxt_re_pd *pd,
1121 				 struct bnxt_qplib_res *qp1_res,
1122 				 struct bnxt_qplib_qp *qp1_qp)
1123 {
1124 	struct bnxt_re_dev *rdev = pd->rdev;
1125 	struct bnxt_re_qp *qp;
1126 	int rc;
1127 
1128 	qp = kzalloc(sizeof(*qp), GFP_KERNEL);
1129 	if (!qp)
1130 		return NULL;
1131 
1132 	qp->rdev = rdev;
1133 
1134 	/* Initialize the shadow QP structure from the QP1 values */
1135 	ether_addr_copy(qp->qplib_qp.smac, rdev->netdev->dev_addr);
1136 
1137 	qp->qplib_qp.pd = &pd->qplib_pd;
1138 	qp->qplib_qp.qp_handle = (u64)(unsigned long)(&qp->qplib_qp);
1139 	qp->qplib_qp.type = IB_QPT_UD;
1140 
1141 	qp->qplib_qp.max_inline_data = 0;
1142 	qp->qplib_qp.sig_type = true;
1143 
1144 	/* Shadow QP SQ depth should be same as QP1 RQ depth */
1145 	qp->qplib_qp.sq.wqe_size = bnxt_re_get_wqe_size(0, 6);
1146 	qp->qplib_qp.sq.max_wqe = qp1_qp->rq.max_wqe;
1147 	qp->qplib_qp.sq.max_sge = 2;
1148 	/* Q full delta can be 1 since it is internal QP */
1149 	qp->qplib_qp.sq.q_full_delta = 1;
1150 	qp->qplib_qp.sq.sg_info.pgsize = PAGE_SIZE;
1151 	qp->qplib_qp.sq.sg_info.pgshft = PAGE_SHIFT;
1152 
1153 	qp->qplib_qp.scq = qp1_qp->scq;
1154 	qp->qplib_qp.rcq = qp1_qp->rcq;
1155 
1156 	qp->qplib_qp.rq.wqe_size = bnxt_re_get_rwqe_size(6);
1157 	qp->qplib_qp.rq.max_wqe = qp1_qp->rq.max_wqe;
1158 	qp->qplib_qp.rq.max_sge = qp1_qp->rq.max_sge;
1159 	/* Q full delta can be 1 since it is internal QP */
1160 	qp->qplib_qp.rq.q_full_delta = 1;
1161 	qp->qplib_qp.rq.sg_info.pgsize = PAGE_SIZE;
1162 	qp->qplib_qp.rq.sg_info.pgshft = PAGE_SHIFT;
1163 
1164 	qp->qplib_qp.mtu = qp1_qp->mtu;
1165 
1166 	qp->qplib_qp.sq_hdr_buf_size = 0;
1167 	qp->qplib_qp.rq_hdr_buf_size = BNXT_QPLIB_MAX_GRH_HDR_SIZE_IPV6;
1168 	qp->qplib_qp.dpi = &rdev->dpi_privileged;
1169 
1170 	rc = bnxt_qplib_create_qp(qp1_res, &qp->qplib_qp);
1171 	if (rc)
1172 		goto fail;
1173 
1174 	spin_lock_init(&qp->sq_lock);
1175 	INIT_LIST_HEAD(&qp->list);
1176 	mutex_lock(&rdev->qp_lock);
1177 	list_add_tail(&qp->list, &rdev->qp_list);
1178 	atomic_inc(&rdev->stats.res.qp_count);
1179 	mutex_unlock(&rdev->qp_lock);
1180 	return qp;
1181 fail:
1182 	kfree(qp);
1183 	return NULL;
1184 }
1185 
1186 static int bnxt_re_init_rq_attr(struct bnxt_re_qp *qp,
1187 				struct ib_qp_init_attr *init_attr,
1188 				struct bnxt_re_ucontext *uctx)
1189 {
1190 	struct bnxt_qplib_dev_attr *dev_attr;
1191 	struct bnxt_qplib_qp *qplqp;
1192 	struct bnxt_re_dev *rdev;
1193 	struct bnxt_qplib_q *rq;
1194 	int entries;
1195 
1196 	rdev = qp->rdev;
1197 	qplqp = &qp->qplib_qp;
1198 	rq = &qplqp->rq;
1199 	dev_attr = &rdev->dev_attr;
1200 
1201 	if (init_attr->srq) {
1202 		struct bnxt_re_srq *srq;
1203 
1204 		srq = container_of(init_attr->srq, struct bnxt_re_srq, ib_srq);
1205 		qplqp->srq = &srq->qplib_srq;
1206 		rq->max_wqe = 0;
1207 	} else {
1208 		rq->max_sge = init_attr->cap.max_recv_sge;
1209 		if (rq->max_sge > dev_attr->max_qp_sges)
1210 			rq->max_sge = dev_attr->max_qp_sges;
1211 		init_attr->cap.max_recv_sge = rq->max_sge;
1212 		rq->wqe_size = bnxt_re_setup_rwqe_size(qplqp, rq->max_sge,
1213 						       dev_attr->max_qp_sges);
1214 		/* Allocate 1 more than what's provided so posting max doesn't
1215 		 * mean empty.
1216 		 */
1217 		entries = bnxt_re_init_depth(init_attr->cap.max_recv_wr + 1, uctx);
1218 		rq->max_wqe = min_t(u32, entries, dev_attr->max_qp_wqes + 1);
1219 		rq->q_full_delta = 0;
1220 		rq->sg_info.pgsize = PAGE_SIZE;
1221 		rq->sg_info.pgshft = PAGE_SHIFT;
1222 	}
1223 
1224 	return 0;
1225 }
1226 
1227 static void bnxt_re_adjust_gsi_rq_attr(struct bnxt_re_qp *qp)
1228 {
1229 	struct bnxt_qplib_dev_attr *dev_attr;
1230 	struct bnxt_qplib_qp *qplqp;
1231 	struct bnxt_re_dev *rdev;
1232 
1233 	rdev = qp->rdev;
1234 	qplqp = &qp->qplib_qp;
1235 	dev_attr = &rdev->dev_attr;
1236 
1237 	if (!bnxt_qplib_is_chip_gen_p5(rdev->chip_ctx)) {
1238 		qplqp->rq.max_sge = dev_attr->max_qp_sges;
1239 		if (qplqp->rq.max_sge > dev_attr->max_qp_sges)
1240 			qplqp->rq.max_sge = dev_attr->max_qp_sges;
1241 		qplqp->rq.max_sge = 6;
1242 	}
1243 }
1244 
1245 static int bnxt_re_init_sq_attr(struct bnxt_re_qp *qp,
1246 				struct ib_qp_init_attr *init_attr,
1247 				struct bnxt_re_ucontext *uctx)
1248 {
1249 	struct bnxt_qplib_dev_attr *dev_attr;
1250 	struct bnxt_qplib_qp *qplqp;
1251 	struct bnxt_re_dev *rdev;
1252 	struct bnxt_qplib_q *sq;
1253 	int entries;
1254 	int diff;
1255 	int rc;
1256 
1257 	rdev = qp->rdev;
1258 	qplqp = &qp->qplib_qp;
1259 	sq = &qplqp->sq;
1260 	dev_attr = &rdev->dev_attr;
1261 
1262 	sq->max_sge = init_attr->cap.max_send_sge;
1263 	if (sq->max_sge > dev_attr->max_qp_sges) {
1264 		sq->max_sge = dev_attr->max_qp_sges;
1265 		init_attr->cap.max_send_sge = sq->max_sge;
1266 	}
1267 
1268 	rc = bnxt_re_setup_swqe_size(qp, init_attr);
1269 	if (rc)
1270 		return rc;
1271 
1272 	entries = init_attr->cap.max_send_wr;
1273 	/* Allocate 128 + 1 more than what's provided */
1274 	diff = (qplqp->wqe_mode == BNXT_QPLIB_WQE_MODE_VARIABLE) ?
1275 		0 : BNXT_QPLIB_RESERVED_QP_WRS;
1276 	entries = bnxt_re_init_depth(entries + diff + 1, uctx);
1277 	sq->max_wqe = min_t(u32, entries, dev_attr->max_qp_wqes + diff + 1);
1278 	sq->q_full_delta = diff + 1;
1279 	/*
1280 	 * Reserving one slot for Phantom WQE. Application can
1281 	 * post one extra entry in this case. But allowing this to avoid
1282 	 * unexpected Queue full condition
1283 	 */
1284 	qplqp->sq.q_full_delta -= 1;
1285 	qplqp->sq.sg_info.pgsize = PAGE_SIZE;
1286 	qplqp->sq.sg_info.pgshft = PAGE_SHIFT;
1287 
1288 	return 0;
1289 }
1290 
1291 static void bnxt_re_adjust_gsi_sq_attr(struct bnxt_re_qp *qp,
1292 				       struct ib_qp_init_attr *init_attr,
1293 				       struct bnxt_re_ucontext *uctx)
1294 {
1295 	struct bnxt_qplib_dev_attr *dev_attr;
1296 	struct bnxt_qplib_qp *qplqp;
1297 	struct bnxt_re_dev *rdev;
1298 	int entries;
1299 
1300 	rdev = qp->rdev;
1301 	qplqp = &qp->qplib_qp;
1302 	dev_attr = &rdev->dev_attr;
1303 
1304 	if (!bnxt_qplib_is_chip_gen_p5(rdev->chip_ctx)) {
1305 		entries = bnxt_re_init_depth(init_attr->cap.max_send_wr + 1, uctx);
1306 		qplqp->sq.max_wqe = min_t(u32, entries,
1307 					  dev_attr->max_qp_wqes + 1);
1308 		qplqp->sq.q_full_delta = qplqp->sq.max_wqe -
1309 			init_attr->cap.max_send_wr;
1310 		qplqp->sq.max_sge++; /* Need one extra sge to put UD header */
1311 		if (qplqp->sq.max_sge > dev_attr->max_qp_sges)
1312 			qplqp->sq.max_sge = dev_attr->max_qp_sges;
1313 	}
1314 }
1315 
1316 static int bnxt_re_init_qp_type(struct bnxt_re_dev *rdev,
1317 				struct ib_qp_init_attr *init_attr)
1318 {
1319 	struct bnxt_qplib_chip_ctx *chip_ctx;
1320 	int qptype;
1321 
1322 	chip_ctx = rdev->chip_ctx;
1323 
1324 	qptype = __from_ib_qp_type(init_attr->qp_type);
1325 	if (qptype == IB_QPT_MAX) {
1326 		ibdev_err(&rdev->ibdev, "QP type 0x%x not supported", qptype);
1327 		qptype = -EOPNOTSUPP;
1328 		goto out;
1329 	}
1330 
1331 	if (bnxt_qplib_is_chip_gen_p5(chip_ctx) &&
1332 	    init_attr->qp_type == IB_QPT_GSI)
1333 		qptype = CMDQ_CREATE_QP_TYPE_GSI;
1334 out:
1335 	return qptype;
1336 }
1337 
1338 static int bnxt_re_init_qp_attr(struct bnxt_re_qp *qp, struct bnxt_re_pd *pd,
1339 				struct ib_qp_init_attr *init_attr,
1340 				struct ib_udata *udata)
1341 {
1342 	struct bnxt_qplib_dev_attr *dev_attr;
1343 	struct bnxt_re_ucontext *uctx;
1344 	struct bnxt_qplib_qp *qplqp;
1345 	struct bnxt_re_dev *rdev;
1346 	struct bnxt_re_cq *cq;
1347 	int rc = 0, qptype;
1348 
1349 	rdev = qp->rdev;
1350 	qplqp = &qp->qplib_qp;
1351 	dev_attr = &rdev->dev_attr;
1352 
1353 	uctx = rdma_udata_to_drv_context(udata, struct bnxt_re_ucontext, ib_uctx);
1354 	/* Setup misc params */
1355 	ether_addr_copy(qplqp->smac, rdev->netdev->dev_addr);
1356 	qplqp->pd = &pd->qplib_pd;
1357 	qplqp->qp_handle = (u64)qplqp;
1358 	qplqp->max_inline_data = init_attr->cap.max_inline_data;
1359 	qplqp->sig_type = init_attr->sq_sig_type == IB_SIGNAL_ALL_WR;
1360 	qptype = bnxt_re_init_qp_type(rdev, init_attr);
1361 	if (qptype < 0) {
1362 		rc = qptype;
1363 		goto out;
1364 	}
1365 	qplqp->type = (u8)qptype;
1366 	qplqp->wqe_mode = rdev->chip_ctx->modes.wqe_mode;
1367 
1368 	if (init_attr->qp_type == IB_QPT_RC) {
1369 		qplqp->max_rd_atomic = dev_attr->max_qp_rd_atom;
1370 		qplqp->max_dest_rd_atomic = dev_attr->max_qp_init_rd_atom;
1371 	}
1372 	qplqp->mtu = ib_mtu_enum_to_int(iboe_get_mtu(rdev->netdev->mtu));
1373 	qplqp->dpi = &rdev->dpi_privileged; /* Doorbell page */
1374 	if (init_attr->create_flags) {
1375 		ibdev_dbg(&rdev->ibdev,
1376 			  "QP create flags 0x%x not supported",
1377 			  init_attr->create_flags);
1378 		return -EOPNOTSUPP;
1379 	}
1380 
1381 	/* Setup CQs */
1382 	if (init_attr->send_cq) {
1383 		cq = container_of(init_attr->send_cq, struct bnxt_re_cq, ib_cq);
1384 		qplqp->scq = &cq->qplib_cq;
1385 		qp->scq = cq;
1386 	}
1387 
1388 	if (init_attr->recv_cq) {
1389 		cq = container_of(init_attr->recv_cq, struct bnxt_re_cq, ib_cq);
1390 		qplqp->rcq = &cq->qplib_cq;
1391 		qp->rcq = cq;
1392 	}
1393 
1394 	/* Setup RQ/SRQ */
1395 	rc = bnxt_re_init_rq_attr(qp, init_attr, uctx);
1396 	if (rc)
1397 		goto out;
1398 	if (init_attr->qp_type == IB_QPT_GSI)
1399 		bnxt_re_adjust_gsi_rq_attr(qp);
1400 
1401 	/* Setup SQ */
1402 	rc = bnxt_re_init_sq_attr(qp, init_attr, uctx);
1403 	if (rc)
1404 		goto out;
1405 	if (init_attr->qp_type == IB_QPT_GSI)
1406 		bnxt_re_adjust_gsi_sq_attr(qp, init_attr, uctx);
1407 
1408 	if (udata) /* This will update DPI and qp_handle */
1409 		rc = bnxt_re_init_user_qp(rdev, pd, qp, udata);
1410 out:
1411 	return rc;
1412 }
1413 
1414 static int bnxt_re_create_shadow_gsi(struct bnxt_re_qp *qp,
1415 				     struct bnxt_re_pd *pd)
1416 {
1417 	struct bnxt_re_sqp_entries *sqp_tbl;
1418 	struct bnxt_re_dev *rdev;
1419 	struct bnxt_re_qp *sqp;
1420 	struct bnxt_re_ah *sah;
1421 	int rc = 0;
1422 
1423 	rdev = qp->rdev;
1424 	/* Create a shadow QP to handle the QP1 traffic */
1425 	sqp_tbl = kcalloc(BNXT_RE_MAX_GSI_SQP_ENTRIES, sizeof(*sqp_tbl),
1426 			  GFP_KERNEL);
1427 	if (!sqp_tbl)
1428 		return -ENOMEM;
1429 	rdev->gsi_ctx.sqp_tbl = sqp_tbl;
1430 
1431 	sqp = bnxt_re_create_shadow_qp(pd, &rdev->qplib_res, &qp->qplib_qp);
1432 	if (!sqp) {
1433 		rc = -ENODEV;
1434 		ibdev_err(&rdev->ibdev, "Failed to create Shadow QP for QP1");
1435 		goto out;
1436 	}
1437 	rdev->gsi_ctx.gsi_sqp = sqp;
1438 
1439 	sqp->rcq = qp->rcq;
1440 	sqp->scq = qp->scq;
1441 	sah = bnxt_re_create_shadow_qp_ah(pd, &rdev->qplib_res,
1442 					  &qp->qplib_qp);
1443 	if (!sah) {
1444 		bnxt_qplib_destroy_qp(&rdev->qplib_res,
1445 				      &sqp->qplib_qp);
1446 		rc = -ENODEV;
1447 		ibdev_err(&rdev->ibdev,
1448 			  "Failed to create AH entry for ShadowQP");
1449 		goto out;
1450 	}
1451 	rdev->gsi_ctx.gsi_sah = sah;
1452 
1453 	return 0;
1454 out:
1455 	kfree(sqp_tbl);
1456 	return rc;
1457 }
1458 
1459 static int bnxt_re_create_gsi_qp(struct bnxt_re_qp *qp, struct bnxt_re_pd *pd,
1460 				 struct ib_qp_init_attr *init_attr)
1461 {
1462 	struct bnxt_re_dev *rdev;
1463 	struct bnxt_qplib_qp *qplqp;
1464 	int rc;
1465 
1466 	rdev = qp->rdev;
1467 	qplqp = &qp->qplib_qp;
1468 
1469 	qplqp->rq_hdr_buf_size = BNXT_QPLIB_MAX_QP1_RQ_HDR_SIZE_V2;
1470 	qplqp->sq_hdr_buf_size = BNXT_QPLIB_MAX_QP1_SQ_HDR_SIZE_V2;
1471 
1472 	rc = bnxt_qplib_create_qp1(&rdev->qplib_res, qplqp);
1473 	if (rc) {
1474 		ibdev_err(&rdev->ibdev, "create HW QP1 failed!");
1475 		goto out;
1476 	}
1477 
1478 	rc = bnxt_re_create_shadow_gsi(qp, pd);
1479 out:
1480 	return rc;
1481 }
1482 
1483 static bool bnxt_re_test_qp_limits(struct bnxt_re_dev *rdev,
1484 				   struct ib_qp_init_attr *init_attr,
1485 				   struct bnxt_qplib_dev_attr *dev_attr)
1486 {
1487 	bool rc = true;
1488 
1489 	if (init_attr->cap.max_send_wr > dev_attr->max_qp_wqes ||
1490 	    init_attr->cap.max_recv_wr > dev_attr->max_qp_wqes ||
1491 	    init_attr->cap.max_send_sge > dev_attr->max_qp_sges ||
1492 	    init_attr->cap.max_recv_sge > dev_attr->max_qp_sges ||
1493 	    init_attr->cap.max_inline_data > dev_attr->max_inline_data) {
1494 		ibdev_err(&rdev->ibdev,
1495 			  "Create QP failed - max exceeded! 0x%x/0x%x 0x%x/0x%x 0x%x/0x%x 0x%x/0x%x 0x%x/0x%x",
1496 			  init_attr->cap.max_send_wr, dev_attr->max_qp_wqes,
1497 			  init_attr->cap.max_recv_wr, dev_attr->max_qp_wqes,
1498 			  init_attr->cap.max_send_sge, dev_attr->max_qp_sges,
1499 			  init_attr->cap.max_recv_sge, dev_attr->max_qp_sges,
1500 			  init_attr->cap.max_inline_data,
1501 			  dev_attr->max_inline_data);
1502 		rc = false;
1503 	}
1504 	return rc;
1505 }
1506 
1507 int bnxt_re_create_qp(struct ib_qp *ib_qp, struct ib_qp_init_attr *qp_init_attr,
1508 		      struct ib_udata *udata)
1509 {
1510 	struct ib_pd *ib_pd = ib_qp->pd;
1511 	struct bnxt_re_pd *pd = container_of(ib_pd, struct bnxt_re_pd, ib_pd);
1512 	struct bnxt_re_dev *rdev = pd->rdev;
1513 	struct bnxt_qplib_dev_attr *dev_attr = &rdev->dev_attr;
1514 	struct bnxt_re_qp *qp = container_of(ib_qp, struct bnxt_re_qp, ib_qp);
1515 	u32 active_qps;
1516 	int rc;
1517 
1518 	rc = bnxt_re_test_qp_limits(rdev, qp_init_attr, dev_attr);
1519 	if (!rc) {
1520 		rc = -EINVAL;
1521 		goto fail;
1522 	}
1523 
1524 	qp->rdev = rdev;
1525 	rc = bnxt_re_init_qp_attr(qp, pd, qp_init_attr, udata);
1526 	if (rc)
1527 		goto fail;
1528 
1529 	if (qp_init_attr->qp_type == IB_QPT_GSI &&
1530 	    !(bnxt_qplib_is_chip_gen_p5(rdev->chip_ctx))) {
1531 		rc = bnxt_re_create_gsi_qp(qp, pd, qp_init_attr);
1532 		if (rc == -ENODEV)
1533 			goto qp_destroy;
1534 		if (rc)
1535 			goto fail;
1536 	} else {
1537 		rc = bnxt_qplib_create_qp(&rdev->qplib_res, &qp->qplib_qp);
1538 		if (rc) {
1539 			ibdev_err(&rdev->ibdev, "Failed to create HW QP");
1540 			goto free_umem;
1541 		}
1542 		if (udata) {
1543 			struct bnxt_re_qp_resp resp;
1544 
1545 			resp.qpid = qp->qplib_qp.id;
1546 			resp.rsvd = 0;
1547 			rc = ib_copy_to_udata(udata, &resp, sizeof(resp));
1548 			if (rc) {
1549 				ibdev_err(&rdev->ibdev, "Failed to copy QP udata");
1550 				goto qp_destroy;
1551 			}
1552 		}
1553 	}
1554 
1555 	qp->ib_qp.qp_num = qp->qplib_qp.id;
1556 	if (qp_init_attr->qp_type == IB_QPT_GSI)
1557 		rdev->gsi_ctx.gsi_qp = qp;
1558 	spin_lock_init(&qp->sq_lock);
1559 	spin_lock_init(&qp->rq_lock);
1560 	INIT_LIST_HEAD(&qp->list);
1561 	mutex_lock(&rdev->qp_lock);
1562 	list_add_tail(&qp->list, &rdev->qp_list);
1563 	mutex_unlock(&rdev->qp_lock);
1564 	active_qps = atomic_inc_return(&rdev->stats.res.qp_count);
1565 	if (active_qps > rdev->stats.res.qp_watermark)
1566 		rdev->stats.res.qp_watermark = active_qps;
1567 	if (qp_init_attr->qp_type == IB_QPT_RC) {
1568 		active_qps = atomic_inc_return(&rdev->stats.res.rc_qp_count);
1569 		if (active_qps > rdev->stats.res.rc_qp_watermark)
1570 			rdev->stats.res.rc_qp_watermark = active_qps;
1571 	} else if (qp_init_attr->qp_type == IB_QPT_UD) {
1572 		active_qps = atomic_inc_return(&rdev->stats.res.ud_qp_count);
1573 		if (active_qps > rdev->stats.res.ud_qp_watermark)
1574 			rdev->stats.res.ud_qp_watermark = active_qps;
1575 	}
1576 
1577 	return 0;
1578 qp_destroy:
1579 	bnxt_qplib_destroy_qp(&rdev->qplib_res, &qp->qplib_qp);
1580 free_umem:
1581 	ib_umem_release(qp->rumem);
1582 	ib_umem_release(qp->sumem);
1583 fail:
1584 	return rc;
1585 }
1586 
1587 static u8 __from_ib_qp_state(enum ib_qp_state state)
1588 {
1589 	switch (state) {
1590 	case IB_QPS_RESET:
1591 		return CMDQ_MODIFY_QP_NEW_STATE_RESET;
1592 	case IB_QPS_INIT:
1593 		return CMDQ_MODIFY_QP_NEW_STATE_INIT;
1594 	case IB_QPS_RTR:
1595 		return CMDQ_MODIFY_QP_NEW_STATE_RTR;
1596 	case IB_QPS_RTS:
1597 		return CMDQ_MODIFY_QP_NEW_STATE_RTS;
1598 	case IB_QPS_SQD:
1599 		return CMDQ_MODIFY_QP_NEW_STATE_SQD;
1600 	case IB_QPS_SQE:
1601 		return CMDQ_MODIFY_QP_NEW_STATE_SQE;
1602 	case IB_QPS_ERR:
1603 	default:
1604 		return CMDQ_MODIFY_QP_NEW_STATE_ERR;
1605 	}
1606 }
1607 
1608 static enum ib_qp_state __to_ib_qp_state(u8 state)
1609 {
1610 	switch (state) {
1611 	case CMDQ_MODIFY_QP_NEW_STATE_RESET:
1612 		return IB_QPS_RESET;
1613 	case CMDQ_MODIFY_QP_NEW_STATE_INIT:
1614 		return IB_QPS_INIT;
1615 	case CMDQ_MODIFY_QP_NEW_STATE_RTR:
1616 		return IB_QPS_RTR;
1617 	case CMDQ_MODIFY_QP_NEW_STATE_RTS:
1618 		return IB_QPS_RTS;
1619 	case CMDQ_MODIFY_QP_NEW_STATE_SQD:
1620 		return IB_QPS_SQD;
1621 	case CMDQ_MODIFY_QP_NEW_STATE_SQE:
1622 		return IB_QPS_SQE;
1623 	case CMDQ_MODIFY_QP_NEW_STATE_ERR:
1624 	default:
1625 		return IB_QPS_ERR;
1626 	}
1627 }
1628 
1629 static u32 __from_ib_mtu(enum ib_mtu mtu)
1630 {
1631 	switch (mtu) {
1632 	case IB_MTU_256:
1633 		return CMDQ_MODIFY_QP_PATH_MTU_MTU_256;
1634 	case IB_MTU_512:
1635 		return CMDQ_MODIFY_QP_PATH_MTU_MTU_512;
1636 	case IB_MTU_1024:
1637 		return CMDQ_MODIFY_QP_PATH_MTU_MTU_1024;
1638 	case IB_MTU_2048:
1639 		return CMDQ_MODIFY_QP_PATH_MTU_MTU_2048;
1640 	case IB_MTU_4096:
1641 		return CMDQ_MODIFY_QP_PATH_MTU_MTU_4096;
1642 	default:
1643 		return CMDQ_MODIFY_QP_PATH_MTU_MTU_2048;
1644 	}
1645 }
1646 
1647 static enum ib_mtu __to_ib_mtu(u32 mtu)
1648 {
1649 	switch (mtu & CREQ_QUERY_QP_RESP_SB_PATH_MTU_MASK) {
1650 	case CMDQ_MODIFY_QP_PATH_MTU_MTU_256:
1651 		return IB_MTU_256;
1652 	case CMDQ_MODIFY_QP_PATH_MTU_MTU_512:
1653 		return IB_MTU_512;
1654 	case CMDQ_MODIFY_QP_PATH_MTU_MTU_1024:
1655 		return IB_MTU_1024;
1656 	case CMDQ_MODIFY_QP_PATH_MTU_MTU_2048:
1657 		return IB_MTU_2048;
1658 	case CMDQ_MODIFY_QP_PATH_MTU_MTU_4096:
1659 		return IB_MTU_4096;
1660 	default:
1661 		return IB_MTU_2048;
1662 	}
1663 }
1664 
1665 /* Shared Receive Queues */
1666 int bnxt_re_destroy_srq(struct ib_srq *ib_srq, struct ib_udata *udata)
1667 {
1668 	struct bnxt_re_srq *srq = container_of(ib_srq, struct bnxt_re_srq,
1669 					       ib_srq);
1670 	struct bnxt_re_dev *rdev = srq->rdev;
1671 	struct bnxt_qplib_srq *qplib_srq = &srq->qplib_srq;
1672 	struct bnxt_qplib_nq *nq = NULL;
1673 
1674 	if (qplib_srq->cq)
1675 		nq = qplib_srq->cq->nq;
1676 	bnxt_qplib_destroy_srq(&rdev->qplib_res, qplib_srq);
1677 	ib_umem_release(srq->umem);
1678 	atomic_dec(&rdev->stats.res.srq_count);
1679 	if (nq)
1680 		nq->budget--;
1681 	return 0;
1682 }
1683 
1684 static int bnxt_re_init_user_srq(struct bnxt_re_dev *rdev,
1685 				 struct bnxt_re_pd *pd,
1686 				 struct bnxt_re_srq *srq,
1687 				 struct ib_udata *udata)
1688 {
1689 	struct bnxt_re_srq_req ureq;
1690 	struct bnxt_qplib_srq *qplib_srq = &srq->qplib_srq;
1691 	struct ib_umem *umem;
1692 	int bytes = 0;
1693 	struct bnxt_re_ucontext *cntx = rdma_udata_to_drv_context(
1694 		udata, struct bnxt_re_ucontext, ib_uctx);
1695 
1696 	if (ib_copy_from_udata(&ureq, udata, sizeof(ureq)))
1697 		return -EFAULT;
1698 
1699 	bytes = (qplib_srq->max_wqe * qplib_srq->wqe_size);
1700 	bytes = PAGE_ALIGN(bytes);
1701 	umem = ib_umem_get(&rdev->ibdev, ureq.srqva, bytes,
1702 			   IB_ACCESS_LOCAL_WRITE);
1703 	if (IS_ERR(umem))
1704 		return PTR_ERR(umem);
1705 
1706 	srq->umem = umem;
1707 	qplib_srq->sg_info.umem = umem;
1708 	qplib_srq->sg_info.pgsize = PAGE_SIZE;
1709 	qplib_srq->sg_info.pgshft = PAGE_SHIFT;
1710 	qplib_srq->srq_handle = ureq.srq_handle;
1711 	qplib_srq->dpi = &cntx->dpi;
1712 
1713 	return 0;
1714 }
1715 
1716 int bnxt_re_create_srq(struct ib_srq *ib_srq,
1717 		       struct ib_srq_init_attr *srq_init_attr,
1718 		       struct ib_udata *udata)
1719 {
1720 	struct bnxt_qplib_dev_attr *dev_attr;
1721 	struct bnxt_qplib_nq *nq = NULL;
1722 	struct bnxt_re_ucontext *uctx;
1723 	struct bnxt_re_dev *rdev;
1724 	struct bnxt_re_srq *srq;
1725 	struct bnxt_re_pd *pd;
1726 	struct ib_pd *ib_pd;
1727 	u32 active_srqs;
1728 	int rc, entries;
1729 
1730 	ib_pd = ib_srq->pd;
1731 	pd = container_of(ib_pd, struct bnxt_re_pd, ib_pd);
1732 	rdev = pd->rdev;
1733 	dev_attr = &rdev->dev_attr;
1734 	srq = container_of(ib_srq, struct bnxt_re_srq, ib_srq);
1735 
1736 	if (srq_init_attr->attr.max_wr >= dev_attr->max_srq_wqes) {
1737 		ibdev_err(&rdev->ibdev, "Create CQ failed - max exceeded");
1738 		rc = -EINVAL;
1739 		goto exit;
1740 	}
1741 
1742 	if (srq_init_attr->srq_type != IB_SRQT_BASIC) {
1743 		rc = -EOPNOTSUPP;
1744 		goto exit;
1745 	}
1746 
1747 	uctx = rdma_udata_to_drv_context(udata, struct bnxt_re_ucontext, ib_uctx);
1748 	srq->rdev = rdev;
1749 	srq->qplib_srq.pd = &pd->qplib_pd;
1750 	srq->qplib_srq.dpi = &rdev->dpi_privileged;
1751 	/* Allocate 1 more than what's provided so posting max doesn't
1752 	 * mean empty
1753 	 */
1754 	entries = bnxt_re_init_depth(srq_init_attr->attr.max_wr + 1, uctx);
1755 	if (entries > dev_attr->max_srq_wqes + 1)
1756 		entries = dev_attr->max_srq_wqes + 1;
1757 	srq->qplib_srq.max_wqe = entries;
1758 
1759 	srq->qplib_srq.max_sge = srq_init_attr->attr.max_sge;
1760 	 /* 128 byte wqe size for SRQ . So use max sges */
1761 	srq->qplib_srq.wqe_size = bnxt_re_get_rwqe_size(dev_attr->max_srq_sges);
1762 	srq->qplib_srq.threshold = srq_init_attr->attr.srq_limit;
1763 	srq->srq_limit = srq_init_attr->attr.srq_limit;
1764 	srq->qplib_srq.eventq_hw_ring_id = rdev->nq[0].ring_id;
1765 	nq = &rdev->nq[0];
1766 
1767 	if (udata) {
1768 		rc = bnxt_re_init_user_srq(rdev, pd, srq, udata);
1769 		if (rc)
1770 			goto fail;
1771 	}
1772 
1773 	rc = bnxt_qplib_create_srq(&rdev->qplib_res, &srq->qplib_srq);
1774 	if (rc) {
1775 		ibdev_err(&rdev->ibdev, "Create HW SRQ failed!");
1776 		goto fail;
1777 	}
1778 
1779 	if (udata) {
1780 		struct bnxt_re_srq_resp resp;
1781 
1782 		resp.srqid = srq->qplib_srq.id;
1783 		rc = ib_copy_to_udata(udata, &resp, sizeof(resp));
1784 		if (rc) {
1785 			ibdev_err(&rdev->ibdev, "SRQ copy to udata failed!");
1786 			bnxt_qplib_destroy_srq(&rdev->qplib_res,
1787 					       &srq->qplib_srq);
1788 			goto fail;
1789 		}
1790 	}
1791 	if (nq)
1792 		nq->budget++;
1793 	active_srqs = atomic_inc_return(&rdev->stats.res.srq_count);
1794 	if (active_srqs > rdev->stats.res.srq_watermark)
1795 		rdev->stats.res.srq_watermark = active_srqs;
1796 	spin_lock_init(&srq->lock);
1797 
1798 	return 0;
1799 
1800 fail:
1801 	ib_umem_release(srq->umem);
1802 exit:
1803 	return rc;
1804 }
1805 
1806 int bnxt_re_modify_srq(struct ib_srq *ib_srq, struct ib_srq_attr *srq_attr,
1807 		       enum ib_srq_attr_mask srq_attr_mask,
1808 		       struct ib_udata *udata)
1809 {
1810 	struct bnxt_re_srq *srq = container_of(ib_srq, struct bnxt_re_srq,
1811 					       ib_srq);
1812 	struct bnxt_re_dev *rdev = srq->rdev;
1813 	int rc;
1814 
1815 	switch (srq_attr_mask) {
1816 	case IB_SRQ_MAX_WR:
1817 		/* SRQ resize is not supported */
1818 		return -EINVAL;
1819 	case IB_SRQ_LIMIT:
1820 		/* Change the SRQ threshold */
1821 		if (srq_attr->srq_limit > srq->qplib_srq.max_wqe)
1822 			return -EINVAL;
1823 
1824 		srq->qplib_srq.threshold = srq_attr->srq_limit;
1825 		rc = bnxt_qplib_modify_srq(&rdev->qplib_res, &srq->qplib_srq);
1826 		if (rc) {
1827 			ibdev_err(&rdev->ibdev, "Modify HW SRQ failed!");
1828 			return rc;
1829 		}
1830 		/* On success, update the shadow */
1831 		srq->srq_limit = srq_attr->srq_limit;
1832 		/* No need to Build and send response back to udata */
1833 		return 0;
1834 	default:
1835 		ibdev_err(&rdev->ibdev,
1836 			  "Unsupported srq_attr_mask 0x%x", srq_attr_mask);
1837 		return -EINVAL;
1838 	}
1839 }
1840 
1841 int bnxt_re_query_srq(struct ib_srq *ib_srq, struct ib_srq_attr *srq_attr)
1842 {
1843 	struct bnxt_re_srq *srq = container_of(ib_srq, struct bnxt_re_srq,
1844 					       ib_srq);
1845 	struct bnxt_re_srq tsrq;
1846 	struct bnxt_re_dev *rdev = srq->rdev;
1847 	int rc;
1848 
1849 	/* Get live SRQ attr */
1850 	tsrq.qplib_srq.id = srq->qplib_srq.id;
1851 	rc = bnxt_qplib_query_srq(&rdev->qplib_res, &tsrq.qplib_srq);
1852 	if (rc) {
1853 		ibdev_err(&rdev->ibdev, "Query HW SRQ failed!");
1854 		return rc;
1855 	}
1856 	srq_attr->max_wr = srq->qplib_srq.max_wqe;
1857 	srq_attr->max_sge = srq->qplib_srq.max_sge;
1858 	srq_attr->srq_limit = tsrq.qplib_srq.threshold;
1859 
1860 	return 0;
1861 }
1862 
1863 int bnxt_re_post_srq_recv(struct ib_srq *ib_srq, const struct ib_recv_wr *wr,
1864 			  const struct ib_recv_wr **bad_wr)
1865 {
1866 	struct bnxt_re_srq *srq = container_of(ib_srq, struct bnxt_re_srq,
1867 					       ib_srq);
1868 	struct bnxt_qplib_swqe wqe;
1869 	unsigned long flags;
1870 	int rc = 0;
1871 
1872 	spin_lock_irqsave(&srq->lock, flags);
1873 	while (wr) {
1874 		/* Transcribe each ib_recv_wr to qplib_swqe */
1875 		wqe.num_sge = wr->num_sge;
1876 		bnxt_re_build_sgl(wr->sg_list, wqe.sg_list, wr->num_sge);
1877 		wqe.wr_id = wr->wr_id;
1878 		wqe.type = BNXT_QPLIB_SWQE_TYPE_RECV;
1879 
1880 		rc = bnxt_qplib_post_srq_recv(&srq->qplib_srq, &wqe);
1881 		if (rc) {
1882 			*bad_wr = wr;
1883 			break;
1884 		}
1885 		wr = wr->next;
1886 	}
1887 	spin_unlock_irqrestore(&srq->lock, flags);
1888 
1889 	return rc;
1890 }
1891 static int bnxt_re_modify_shadow_qp(struct bnxt_re_dev *rdev,
1892 				    struct bnxt_re_qp *qp1_qp,
1893 				    int qp_attr_mask)
1894 {
1895 	struct bnxt_re_qp *qp = rdev->gsi_ctx.gsi_sqp;
1896 	int rc;
1897 
1898 	if (qp_attr_mask & IB_QP_STATE) {
1899 		qp->qplib_qp.modify_flags |= CMDQ_MODIFY_QP_MODIFY_MASK_STATE;
1900 		qp->qplib_qp.state = qp1_qp->qplib_qp.state;
1901 	}
1902 	if (qp_attr_mask & IB_QP_PKEY_INDEX) {
1903 		qp->qplib_qp.modify_flags |= CMDQ_MODIFY_QP_MODIFY_MASK_PKEY;
1904 		qp->qplib_qp.pkey_index = qp1_qp->qplib_qp.pkey_index;
1905 	}
1906 
1907 	if (qp_attr_mask & IB_QP_QKEY) {
1908 		qp->qplib_qp.modify_flags |= CMDQ_MODIFY_QP_MODIFY_MASK_QKEY;
1909 		/* Using a Random  QKEY */
1910 		qp->qplib_qp.qkey = 0x81818181;
1911 	}
1912 	if (qp_attr_mask & IB_QP_SQ_PSN) {
1913 		qp->qplib_qp.modify_flags |= CMDQ_MODIFY_QP_MODIFY_MASK_SQ_PSN;
1914 		qp->qplib_qp.sq.psn = qp1_qp->qplib_qp.sq.psn;
1915 	}
1916 
1917 	rc = bnxt_qplib_modify_qp(&rdev->qplib_res, &qp->qplib_qp);
1918 	if (rc)
1919 		ibdev_err(&rdev->ibdev, "Failed to modify Shadow QP for QP1");
1920 	return rc;
1921 }
1922 
1923 int bnxt_re_modify_qp(struct ib_qp *ib_qp, struct ib_qp_attr *qp_attr,
1924 		      int qp_attr_mask, struct ib_udata *udata)
1925 {
1926 	struct bnxt_re_qp *qp = container_of(ib_qp, struct bnxt_re_qp, ib_qp);
1927 	struct bnxt_re_dev *rdev = qp->rdev;
1928 	struct bnxt_qplib_dev_attr *dev_attr = &rdev->dev_attr;
1929 	enum ib_qp_state curr_qp_state, new_qp_state;
1930 	int rc, entries;
1931 	unsigned int flags;
1932 	u8 nw_type;
1933 
1934 	if (qp_attr_mask & ~IB_QP_ATTR_STANDARD_BITS)
1935 		return -EOPNOTSUPP;
1936 
1937 	qp->qplib_qp.modify_flags = 0;
1938 	if (qp_attr_mask & IB_QP_STATE) {
1939 		curr_qp_state = __to_ib_qp_state(qp->qplib_qp.cur_qp_state);
1940 		new_qp_state = qp_attr->qp_state;
1941 		if (!ib_modify_qp_is_ok(curr_qp_state, new_qp_state,
1942 					ib_qp->qp_type, qp_attr_mask)) {
1943 			ibdev_err(&rdev->ibdev,
1944 				  "Invalid attribute mask: %#x specified ",
1945 				  qp_attr_mask);
1946 			ibdev_err(&rdev->ibdev,
1947 				  "for qpn: %#x type: %#x",
1948 				  ib_qp->qp_num, ib_qp->qp_type);
1949 			ibdev_err(&rdev->ibdev,
1950 				  "curr_qp_state=0x%x, new_qp_state=0x%x\n",
1951 				  curr_qp_state, new_qp_state);
1952 			return -EINVAL;
1953 		}
1954 		qp->qplib_qp.modify_flags |= CMDQ_MODIFY_QP_MODIFY_MASK_STATE;
1955 		qp->qplib_qp.state = __from_ib_qp_state(qp_attr->qp_state);
1956 
1957 		if (!qp->sumem &&
1958 		    qp->qplib_qp.state == CMDQ_MODIFY_QP_NEW_STATE_ERR) {
1959 			ibdev_dbg(&rdev->ibdev,
1960 				  "Move QP = %p to flush list\n", qp);
1961 			flags = bnxt_re_lock_cqs(qp);
1962 			bnxt_qplib_add_flush_qp(&qp->qplib_qp);
1963 			bnxt_re_unlock_cqs(qp, flags);
1964 		}
1965 		if (!qp->sumem &&
1966 		    qp->qplib_qp.state == CMDQ_MODIFY_QP_NEW_STATE_RESET) {
1967 			ibdev_dbg(&rdev->ibdev,
1968 				  "Move QP = %p out of flush list\n", qp);
1969 			flags = bnxt_re_lock_cqs(qp);
1970 			bnxt_qplib_clean_qp(&qp->qplib_qp);
1971 			bnxt_re_unlock_cqs(qp, flags);
1972 		}
1973 	}
1974 	if (qp_attr_mask & IB_QP_EN_SQD_ASYNC_NOTIFY) {
1975 		qp->qplib_qp.modify_flags |=
1976 				CMDQ_MODIFY_QP_MODIFY_MASK_EN_SQD_ASYNC_NOTIFY;
1977 		qp->qplib_qp.en_sqd_async_notify = true;
1978 	}
1979 	if (qp_attr_mask & IB_QP_ACCESS_FLAGS) {
1980 		qp->qplib_qp.modify_flags |= CMDQ_MODIFY_QP_MODIFY_MASK_ACCESS;
1981 		qp->qplib_qp.access =
1982 			__from_ib_access_flags(qp_attr->qp_access_flags);
1983 		/* LOCAL_WRITE access must be set to allow RC receive */
1984 		qp->qplib_qp.access |= BNXT_QPLIB_ACCESS_LOCAL_WRITE;
1985 		/* Temp: Set all params on QP as of now */
1986 		qp->qplib_qp.access |= CMDQ_MODIFY_QP_ACCESS_REMOTE_WRITE;
1987 		qp->qplib_qp.access |= CMDQ_MODIFY_QP_ACCESS_REMOTE_READ;
1988 	}
1989 	if (qp_attr_mask & IB_QP_PKEY_INDEX) {
1990 		qp->qplib_qp.modify_flags |= CMDQ_MODIFY_QP_MODIFY_MASK_PKEY;
1991 		qp->qplib_qp.pkey_index = qp_attr->pkey_index;
1992 	}
1993 	if (qp_attr_mask & IB_QP_QKEY) {
1994 		qp->qplib_qp.modify_flags |= CMDQ_MODIFY_QP_MODIFY_MASK_QKEY;
1995 		qp->qplib_qp.qkey = qp_attr->qkey;
1996 	}
1997 	if (qp_attr_mask & IB_QP_AV) {
1998 		const struct ib_global_route *grh =
1999 			rdma_ah_read_grh(&qp_attr->ah_attr);
2000 		const struct ib_gid_attr *sgid_attr;
2001 		struct bnxt_re_gid_ctx *ctx;
2002 
2003 		qp->qplib_qp.modify_flags |= CMDQ_MODIFY_QP_MODIFY_MASK_DGID |
2004 				     CMDQ_MODIFY_QP_MODIFY_MASK_FLOW_LABEL |
2005 				     CMDQ_MODIFY_QP_MODIFY_MASK_SGID_INDEX |
2006 				     CMDQ_MODIFY_QP_MODIFY_MASK_HOP_LIMIT |
2007 				     CMDQ_MODIFY_QP_MODIFY_MASK_TRAFFIC_CLASS |
2008 				     CMDQ_MODIFY_QP_MODIFY_MASK_DEST_MAC |
2009 				     CMDQ_MODIFY_QP_MODIFY_MASK_VLAN_ID;
2010 		memcpy(qp->qplib_qp.ah.dgid.data, grh->dgid.raw,
2011 		       sizeof(qp->qplib_qp.ah.dgid.data));
2012 		qp->qplib_qp.ah.flow_label = grh->flow_label;
2013 		sgid_attr = grh->sgid_attr;
2014 		/* Get the HW context of the GID. The reference
2015 		 * of GID table entry is already taken by the caller.
2016 		 */
2017 		ctx = rdma_read_gid_hw_context(sgid_attr);
2018 		qp->qplib_qp.ah.sgid_index = ctx->idx;
2019 		qp->qplib_qp.ah.host_sgid_index = grh->sgid_index;
2020 		qp->qplib_qp.ah.hop_limit = grh->hop_limit;
2021 		qp->qplib_qp.ah.traffic_class = grh->traffic_class;
2022 		qp->qplib_qp.ah.sl = rdma_ah_get_sl(&qp_attr->ah_attr);
2023 		ether_addr_copy(qp->qplib_qp.ah.dmac,
2024 				qp_attr->ah_attr.roce.dmac);
2025 
2026 		rc = rdma_read_gid_l2_fields(sgid_attr, NULL,
2027 					     &qp->qplib_qp.smac[0]);
2028 		if (rc)
2029 			return rc;
2030 
2031 		nw_type = rdma_gid_attr_network_type(sgid_attr);
2032 		switch (nw_type) {
2033 		case RDMA_NETWORK_IPV4:
2034 			qp->qplib_qp.nw_type =
2035 				CMDQ_MODIFY_QP_NETWORK_TYPE_ROCEV2_IPV4;
2036 			break;
2037 		case RDMA_NETWORK_IPV6:
2038 			qp->qplib_qp.nw_type =
2039 				CMDQ_MODIFY_QP_NETWORK_TYPE_ROCEV2_IPV6;
2040 			break;
2041 		default:
2042 			qp->qplib_qp.nw_type =
2043 				CMDQ_MODIFY_QP_NETWORK_TYPE_ROCEV1;
2044 			break;
2045 		}
2046 	}
2047 
2048 	if (qp_attr_mask & IB_QP_PATH_MTU) {
2049 		qp->qplib_qp.modify_flags |=
2050 				CMDQ_MODIFY_QP_MODIFY_MASK_PATH_MTU;
2051 		qp->qplib_qp.path_mtu = __from_ib_mtu(qp_attr->path_mtu);
2052 		qp->qplib_qp.mtu = ib_mtu_enum_to_int(qp_attr->path_mtu);
2053 	} else if (qp_attr->qp_state == IB_QPS_RTR) {
2054 		qp->qplib_qp.modify_flags |=
2055 			CMDQ_MODIFY_QP_MODIFY_MASK_PATH_MTU;
2056 		qp->qplib_qp.path_mtu =
2057 			__from_ib_mtu(iboe_get_mtu(rdev->netdev->mtu));
2058 		qp->qplib_qp.mtu =
2059 			ib_mtu_enum_to_int(iboe_get_mtu(rdev->netdev->mtu));
2060 	}
2061 
2062 	if (qp_attr_mask & IB_QP_TIMEOUT) {
2063 		qp->qplib_qp.modify_flags |= CMDQ_MODIFY_QP_MODIFY_MASK_TIMEOUT;
2064 		qp->qplib_qp.timeout = qp_attr->timeout;
2065 	}
2066 	if (qp_attr_mask & IB_QP_RETRY_CNT) {
2067 		qp->qplib_qp.modify_flags |=
2068 				CMDQ_MODIFY_QP_MODIFY_MASK_RETRY_CNT;
2069 		qp->qplib_qp.retry_cnt = qp_attr->retry_cnt;
2070 	}
2071 	if (qp_attr_mask & IB_QP_RNR_RETRY) {
2072 		qp->qplib_qp.modify_flags |=
2073 				CMDQ_MODIFY_QP_MODIFY_MASK_RNR_RETRY;
2074 		qp->qplib_qp.rnr_retry = qp_attr->rnr_retry;
2075 	}
2076 	if (qp_attr_mask & IB_QP_MIN_RNR_TIMER) {
2077 		qp->qplib_qp.modify_flags |=
2078 				CMDQ_MODIFY_QP_MODIFY_MASK_MIN_RNR_TIMER;
2079 		qp->qplib_qp.min_rnr_timer = qp_attr->min_rnr_timer;
2080 	}
2081 	if (qp_attr_mask & IB_QP_RQ_PSN) {
2082 		qp->qplib_qp.modify_flags |= CMDQ_MODIFY_QP_MODIFY_MASK_RQ_PSN;
2083 		qp->qplib_qp.rq.psn = qp_attr->rq_psn;
2084 	}
2085 	if (qp_attr_mask & IB_QP_MAX_QP_RD_ATOMIC) {
2086 		qp->qplib_qp.modify_flags |=
2087 				CMDQ_MODIFY_QP_MODIFY_MASK_MAX_RD_ATOMIC;
2088 		/* Cap the max_rd_atomic to device max */
2089 		qp->qplib_qp.max_rd_atomic = min_t(u32, qp_attr->max_rd_atomic,
2090 						   dev_attr->max_qp_rd_atom);
2091 	}
2092 	if (qp_attr_mask & IB_QP_SQ_PSN) {
2093 		qp->qplib_qp.modify_flags |= CMDQ_MODIFY_QP_MODIFY_MASK_SQ_PSN;
2094 		qp->qplib_qp.sq.psn = qp_attr->sq_psn;
2095 	}
2096 	if (qp_attr_mask & IB_QP_MAX_DEST_RD_ATOMIC) {
2097 		if (qp_attr->max_dest_rd_atomic >
2098 		    dev_attr->max_qp_init_rd_atom) {
2099 			ibdev_err(&rdev->ibdev,
2100 				  "max_dest_rd_atomic requested%d is > dev_max%d",
2101 				  qp_attr->max_dest_rd_atomic,
2102 				  dev_attr->max_qp_init_rd_atom);
2103 			return -EINVAL;
2104 		}
2105 
2106 		qp->qplib_qp.modify_flags |=
2107 				CMDQ_MODIFY_QP_MODIFY_MASK_MAX_DEST_RD_ATOMIC;
2108 		qp->qplib_qp.max_dest_rd_atomic = qp_attr->max_dest_rd_atomic;
2109 	}
2110 	if (qp_attr_mask & IB_QP_CAP) {
2111 		struct bnxt_re_ucontext *uctx =
2112 			rdma_udata_to_drv_context(udata, struct bnxt_re_ucontext, ib_uctx);
2113 
2114 		qp->qplib_qp.modify_flags |=
2115 				CMDQ_MODIFY_QP_MODIFY_MASK_SQ_SIZE |
2116 				CMDQ_MODIFY_QP_MODIFY_MASK_RQ_SIZE |
2117 				CMDQ_MODIFY_QP_MODIFY_MASK_SQ_SGE |
2118 				CMDQ_MODIFY_QP_MODIFY_MASK_RQ_SGE |
2119 				CMDQ_MODIFY_QP_MODIFY_MASK_MAX_INLINE_DATA;
2120 		if ((qp_attr->cap.max_send_wr >= dev_attr->max_qp_wqes) ||
2121 		    (qp_attr->cap.max_recv_wr >= dev_attr->max_qp_wqes) ||
2122 		    (qp_attr->cap.max_send_sge >= dev_attr->max_qp_sges) ||
2123 		    (qp_attr->cap.max_recv_sge >= dev_attr->max_qp_sges) ||
2124 		    (qp_attr->cap.max_inline_data >=
2125 						dev_attr->max_inline_data)) {
2126 			ibdev_err(&rdev->ibdev,
2127 				  "Create QP failed - max exceeded");
2128 			return -EINVAL;
2129 		}
2130 		entries = bnxt_re_init_depth(qp_attr->cap.max_send_wr, uctx);
2131 		qp->qplib_qp.sq.max_wqe = min_t(u32, entries,
2132 						dev_attr->max_qp_wqes + 1);
2133 		qp->qplib_qp.sq.q_full_delta = qp->qplib_qp.sq.max_wqe -
2134 						qp_attr->cap.max_send_wr;
2135 		/*
2136 		 * Reserving one slot for Phantom WQE. Some application can
2137 		 * post one extra entry in this case. Allowing this to avoid
2138 		 * unexpected Queue full condition
2139 		 */
2140 		qp->qplib_qp.sq.q_full_delta -= 1;
2141 		qp->qplib_qp.sq.max_sge = qp_attr->cap.max_send_sge;
2142 		if (qp->qplib_qp.rq.max_wqe) {
2143 			entries = bnxt_re_init_depth(qp_attr->cap.max_recv_wr, uctx);
2144 			qp->qplib_qp.rq.max_wqe =
2145 				min_t(u32, entries, dev_attr->max_qp_wqes + 1);
2146 			qp->qplib_qp.rq.q_full_delta = qp->qplib_qp.rq.max_wqe -
2147 						       qp_attr->cap.max_recv_wr;
2148 			qp->qplib_qp.rq.max_sge = qp_attr->cap.max_recv_sge;
2149 		} else {
2150 			/* SRQ was used prior, just ignore the RQ caps */
2151 		}
2152 	}
2153 	if (qp_attr_mask & IB_QP_DEST_QPN) {
2154 		qp->qplib_qp.modify_flags |=
2155 				CMDQ_MODIFY_QP_MODIFY_MASK_DEST_QP_ID;
2156 		qp->qplib_qp.dest_qpn = qp_attr->dest_qp_num;
2157 	}
2158 	rc = bnxt_qplib_modify_qp(&rdev->qplib_res, &qp->qplib_qp);
2159 	if (rc) {
2160 		ibdev_err(&rdev->ibdev, "Failed to modify HW QP");
2161 		return rc;
2162 	}
2163 	if (ib_qp->qp_type == IB_QPT_GSI && rdev->gsi_ctx.gsi_sqp)
2164 		rc = bnxt_re_modify_shadow_qp(rdev, qp, qp_attr_mask);
2165 	return rc;
2166 }
2167 
2168 int bnxt_re_query_qp(struct ib_qp *ib_qp, struct ib_qp_attr *qp_attr,
2169 		     int qp_attr_mask, struct ib_qp_init_attr *qp_init_attr)
2170 {
2171 	struct bnxt_re_qp *qp = container_of(ib_qp, struct bnxt_re_qp, ib_qp);
2172 	struct bnxt_re_dev *rdev = qp->rdev;
2173 	struct bnxt_qplib_qp *qplib_qp;
2174 	int rc;
2175 
2176 	qplib_qp = kzalloc(sizeof(*qplib_qp), GFP_KERNEL);
2177 	if (!qplib_qp)
2178 		return -ENOMEM;
2179 
2180 	qplib_qp->id = qp->qplib_qp.id;
2181 	qplib_qp->ah.host_sgid_index = qp->qplib_qp.ah.host_sgid_index;
2182 
2183 	rc = bnxt_qplib_query_qp(&rdev->qplib_res, qplib_qp);
2184 	if (rc) {
2185 		ibdev_err(&rdev->ibdev, "Failed to query HW QP");
2186 		goto out;
2187 	}
2188 	qp_attr->qp_state = __to_ib_qp_state(qplib_qp->state);
2189 	qp_attr->cur_qp_state = __to_ib_qp_state(qplib_qp->cur_qp_state);
2190 	qp_attr->en_sqd_async_notify = qplib_qp->en_sqd_async_notify ? 1 : 0;
2191 	qp_attr->qp_access_flags = __to_ib_access_flags(qplib_qp->access);
2192 	qp_attr->pkey_index = qplib_qp->pkey_index;
2193 	qp_attr->qkey = qplib_qp->qkey;
2194 	qp_attr->ah_attr.type = RDMA_AH_ATTR_TYPE_ROCE;
2195 	rdma_ah_set_grh(&qp_attr->ah_attr, NULL, qplib_qp->ah.flow_label,
2196 			qplib_qp->ah.host_sgid_index,
2197 			qplib_qp->ah.hop_limit,
2198 			qplib_qp->ah.traffic_class);
2199 	rdma_ah_set_dgid_raw(&qp_attr->ah_attr, qplib_qp->ah.dgid.data);
2200 	rdma_ah_set_sl(&qp_attr->ah_attr, qplib_qp->ah.sl);
2201 	ether_addr_copy(qp_attr->ah_attr.roce.dmac, qplib_qp->ah.dmac);
2202 	qp_attr->path_mtu = __to_ib_mtu(qplib_qp->path_mtu);
2203 	qp_attr->timeout = qplib_qp->timeout;
2204 	qp_attr->retry_cnt = qplib_qp->retry_cnt;
2205 	qp_attr->rnr_retry = qplib_qp->rnr_retry;
2206 	qp_attr->min_rnr_timer = qplib_qp->min_rnr_timer;
2207 	qp_attr->rq_psn = qplib_qp->rq.psn;
2208 	qp_attr->max_rd_atomic = qplib_qp->max_rd_atomic;
2209 	qp_attr->sq_psn = qplib_qp->sq.psn;
2210 	qp_attr->max_dest_rd_atomic = qplib_qp->max_dest_rd_atomic;
2211 	qp_init_attr->sq_sig_type = qplib_qp->sig_type ? IB_SIGNAL_ALL_WR :
2212 							 IB_SIGNAL_REQ_WR;
2213 	qp_attr->dest_qp_num = qplib_qp->dest_qpn;
2214 
2215 	qp_attr->cap.max_send_wr = qp->qplib_qp.sq.max_wqe;
2216 	qp_attr->cap.max_send_sge = qp->qplib_qp.sq.max_sge;
2217 	qp_attr->cap.max_recv_wr = qp->qplib_qp.rq.max_wqe;
2218 	qp_attr->cap.max_recv_sge = qp->qplib_qp.rq.max_sge;
2219 	qp_attr->cap.max_inline_data = qp->qplib_qp.max_inline_data;
2220 	qp_init_attr->cap = qp_attr->cap;
2221 
2222 out:
2223 	kfree(qplib_qp);
2224 	return rc;
2225 }
2226 
2227 /* Routine for sending QP1 packets for RoCE V1 an V2
2228  */
2229 static int bnxt_re_build_qp1_send_v2(struct bnxt_re_qp *qp,
2230 				     const struct ib_send_wr *wr,
2231 				     struct bnxt_qplib_swqe *wqe,
2232 				     int payload_size)
2233 {
2234 	struct bnxt_re_ah *ah = container_of(ud_wr(wr)->ah, struct bnxt_re_ah,
2235 					     ib_ah);
2236 	struct bnxt_qplib_ah *qplib_ah = &ah->qplib_ah;
2237 	const struct ib_gid_attr *sgid_attr = ah->ib_ah.sgid_attr;
2238 	struct bnxt_qplib_sge sge;
2239 	u8 nw_type;
2240 	u16 ether_type;
2241 	union ib_gid dgid;
2242 	bool is_eth = false;
2243 	bool is_vlan = false;
2244 	bool is_grh = false;
2245 	bool is_udp = false;
2246 	u8 ip_version = 0;
2247 	u16 vlan_id = 0xFFFF;
2248 	void *buf;
2249 	int i, rc;
2250 
2251 	memset(&qp->qp1_hdr, 0, sizeof(qp->qp1_hdr));
2252 
2253 	rc = rdma_read_gid_l2_fields(sgid_attr, &vlan_id, NULL);
2254 	if (rc)
2255 		return rc;
2256 
2257 	/* Get network header type for this GID */
2258 	nw_type = rdma_gid_attr_network_type(sgid_attr);
2259 	switch (nw_type) {
2260 	case RDMA_NETWORK_IPV4:
2261 		nw_type = BNXT_RE_ROCEV2_IPV4_PACKET;
2262 		break;
2263 	case RDMA_NETWORK_IPV6:
2264 		nw_type = BNXT_RE_ROCEV2_IPV6_PACKET;
2265 		break;
2266 	default:
2267 		nw_type = BNXT_RE_ROCE_V1_PACKET;
2268 		break;
2269 	}
2270 	memcpy(&dgid.raw, &qplib_ah->dgid, 16);
2271 	is_udp = sgid_attr->gid_type == IB_GID_TYPE_ROCE_UDP_ENCAP;
2272 	if (is_udp) {
2273 		if (ipv6_addr_v4mapped((struct in6_addr *)&sgid_attr->gid)) {
2274 			ip_version = 4;
2275 			ether_type = ETH_P_IP;
2276 		} else {
2277 			ip_version = 6;
2278 			ether_type = ETH_P_IPV6;
2279 		}
2280 		is_grh = false;
2281 	} else {
2282 		ether_type = ETH_P_IBOE;
2283 		is_grh = true;
2284 	}
2285 
2286 	is_eth = true;
2287 	is_vlan = vlan_id && (vlan_id < 0x1000);
2288 
2289 	ib_ud_header_init(payload_size, !is_eth, is_eth, is_vlan, is_grh,
2290 			  ip_version, is_udp, 0, &qp->qp1_hdr);
2291 
2292 	/* ETH */
2293 	ether_addr_copy(qp->qp1_hdr.eth.dmac_h, ah->qplib_ah.dmac);
2294 	ether_addr_copy(qp->qp1_hdr.eth.smac_h, qp->qplib_qp.smac);
2295 
2296 	/* For vlan, check the sgid for vlan existence */
2297 
2298 	if (!is_vlan) {
2299 		qp->qp1_hdr.eth.type = cpu_to_be16(ether_type);
2300 	} else {
2301 		qp->qp1_hdr.vlan.type = cpu_to_be16(ether_type);
2302 		qp->qp1_hdr.vlan.tag = cpu_to_be16(vlan_id);
2303 	}
2304 
2305 	if (is_grh || (ip_version == 6)) {
2306 		memcpy(qp->qp1_hdr.grh.source_gid.raw, sgid_attr->gid.raw,
2307 		       sizeof(sgid_attr->gid));
2308 		memcpy(qp->qp1_hdr.grh.destination_gid.raw, qplib_ah->dgid.data,
2309 		       sizeof(sgid_attr->gid));
2310 		qp->qp1_hdr.grh.hop_limit     = qplib_ah->hop_limit;
2311 	}
2312 
2313 	if (ip_version == 4) {
2314 		qp->qp1_hdr.ip4.tos = 0;
2315 		qp->qp1_hdr.ip4.id = 0;
2316 		qp->qp1_hdr.ip4.frag_off = htons(IP_DF);
2317 		qp->qp1_hdr.ip4.ttl = qplib_ah->hop_limit;
2318 
2319 		memcpy(&qp->qp1_hdr.ip4.saddr, sgid_attr->gid.raw + 12, 4);
2320 		memcpy(&qp->qp1_hdr.ip4.daddr, qplib_ah->dgid.data + 12, 4);
2321 		qp->qp1_hdr.ip4.check = ib_ud_ip4_csum(&qp->qp1_hdr);
2322 	}
2323 
2324 	if (is_udp) {
2325 		qp->qp1_hdr.udp.dport = htons(ROCE_V2_UDP_DPORT);
2326 		qp->qp1_hdr.udp.sport = htons(0x8CD1);
2327 		qp->qp1_hdr.udp.csum = 0;
2328 	}
2329 
2330 	/* BTH */
2331 	if (wr->opcode == IB_WR_SEND_WITH_IMM) {
2332 		qp->qp1_hdr.bth.opcode = IB_OPCODE_UD_SEND_ONLY_WITH_IMMEDIATE;
2333 		qp->qp1_hdr.immediate_present = 1;
2334 	} else {
2335 		qp->qp1_hdr.bth.opcode = IB_OPCODE_UD_SEND_ONLY;
2336 	}
2337 	if (wr->send_flags & IB_SEND_SOLICITED)
2338 		qp->qp1_hdr.bth.solicited_event = 1;
2339 	/* pad_count */
2340 	qp->qp1_hdr.bth.pad_count = (4 - payload_size) & 3;
2341 
2342 	/* P_key for QP1 is for all members */
2343 	qp->qp1_hdr.bth.pkey = cpu_to_be16(0xFFFF);
2344 	qp->qp1_hdr.bth.destination_qpn = IB_QP1;
2345 	qp->qp1_hdr.bth.ack_req = 0;
2346 	qp->send_psn++;
2347 	qp->send_psn &= BTH_PSN_MASK;
2348 	qp->qp1_hdr.bth.psn = cpu_to_be32(qp->send_psn);
2349 	/* DETH */
2350 	/* Use the priviledged Q_Key for QP1 */
2351 	qp->qp1_hdr.deth.qkey = cpu_to_be32(IB_QP1_QKEY);
2352 	qp->qp1_hdr.deth.source_qpn = IB_QP1;
2353 
2354 	/* Pack the QP1 to the transmit buffer */
2355 	buf = bnxt_qplib_get_qp1_sq_buf(&qp->qplib_qp, &sge);
2356 	if (buf) {
2357 		ib_ud_header_pack(&qp->qp1_hdr, buf);
2358 		for (i = wqe->num_sge; i; i--) {
2359 			wqe->sg_list[i].addr = wqe->sg_list[i - 1].addr;
2360 			wqe->sg_list[i].lkey = wqe->sg_list[i - 1].lkey;
2361 			wqe->sg_list[i].size = wqe->sg_list[i - 1].size;
2362 		}
2363 
2364 		/*
2365 		 * Max Header buf size for IPV6 RoCE V2 is 86,
2366 		 * which is same as the QP1 SQ header buffer.
2367 		 * Header buf size for IPV4 RoCE V2 can be 66.
2368 		 * ETH(14) + VLAN(4)+ IP(20) + UDP (8) + BTH(20).
2369 		 * Subtract 20 bytes from QP1 SQ header buf size
2370 		 */
2371 		if (is_udp && ip_version == 4)
2372 			sge.size -= 20;
2373 		/*
2374 		 * Max Header buf size for RoCE V1 is 78.
2375 		 * ETH(14) + VLAN(4) + GRH(40) + BTH(20).
2376 		 * Subtract 8 bytes from QP1 SQ header buf size
2377 		 */
2378 		if (!is_udp)
2379 			sge.size -= 8;
2380 
2381 		/* Subtract 4 bytes for non vlan packets */
2382 		if (!is_vlan)
2383 			sge.size -= 4;
2384 
2385 		wqe->sg_list[0].addr = sge.addr;
2386 		wqe->sg_list[0].lkey = sge.lkey;
2387 		wqe->sg_list[0].size = sge.size;
2388 		wqe->num_sge++;
2389 
2390 	} else {
2391 		ibdev_err(&qp->rdev->ibdev, "QP1 buffer is empty!");
2392 		rc = -ENOMEM;
2393 	}
2394 	return rc;
2395 }
2396 
2397 /* For the MAD layer, it only provides the recv SGE the size of
2398  * ib_grh + MAD datagram.  No Ethernet headers, Ethertype, BTH, DETH,
2399  * nor RoCE iCRC.  The Cu+ solution must provide buffer for the entire
2400  * receive packet (334 bytes) with no VLAN and then copy the GRH
2401  * and the MAD datagram out to the provided SGE.
2402  */
2403 static int bnxt_re_build_qp1_shadow_qp_recv(struct bnxt_re_qp *qp,
2404 					    const struct ib_recv_wr *wr,
2405 					    struct bnxt_qplib_swqe *wqe,
2406 					    int payload_size)
2407 {
2408 	struct bnxt_re_sqp_entries *sqp_entry;
2409 	struct bnxt_qplib_sge ref, sge;
2410 	struct bnxt_re_dev *rdev;
2411 	u32 rq_prod_index;
2412 
2413 	rdev = qp->rdev;
2414 
2415 	rq_prod_index = bnxt_qplib_get_rq_prod_index(&qp->qplib_qp);
2416 
2417 	if (!bnxt_qplib_get_qp1_rq_buf(&qp->qplib_qp, &sge))
2418 		return -ENOMEM;
2419 
2420 	/* Create 1 SGE to receive the entire
2421 	 * ethernet packet
2422 	 */
2423 	/* Save the reference from ULP */
2424 	ref.addr = wqe->sg_list[0].addr;
2425 	ref.lkey = wqe->sg_list[0].lkey;
2426 	ref.size = wqe->sg_list[0].size;
2427 
2428 	sqp_entry = &rdev->gsi_ctx.sqp_tbl[rq_prod_index];
2429 
2430 	/* SGE 1 */
2431 	wqe->sg_list[0].addr = sge.addr;
2432 	wqe->sg_list[0].lkey = sge.lkey;
2433 	wqe->sg_list[0].size = BNXT_QPLIB_MAX_QP1_RQ_HDR_SIZE_V2;
2434 	sge.size -= wqe->sg_list[0].size;
2435 
2436 	sqp_entry->sge.addr = ref.addr;
2437 	sqp_entry->sge.lkey = ref.lkey;
2438 	sqp_entry->sge.size = ref.size;
2439 	/* Store the wrid for reporting completion */
2440 	sqp_entry->wrid = wqe->wr_id;
2441 	/* change the wqe->wrid to table index */
2442 	wqe->wr_id = rq_prod_index;
2443 	return 0;
2444 }
2445 
2446 static int is_ud_qp(struct bnxt_re_qp *qp)
2447 {
2448 	return (qp->qplib_qp.type == CMDQ_CREATE_QP_TYPE_UD ||
2449 		qp->qplib_qp.type == CMDQ_CREATE_QP_TYPE_GSI);
2450 }
2451 
2452 static int bnxt_re_build_send_wqe(struct bnxt_re_qp *qp,
2453 				  const struct ib_send_wr *wr,
2454 				  struct bnxt_qplib_swqe *wqe)
2455 {
2456 	struct bnxt_re_ah *ah = NULL;
2457 
2458 	if (is_ud_qp(qp)) {
2459 		ah = container_of(ud_wr(wr)->ah, struct bnxt_re_ah, ib_ah);
2460 		wqe->send.q_key = ud_wr(wr)->remote_qkey;
2461 		wqe->send.dst_qp = ud_wr(wr)->remote_qpn;
2462 		wqe->send.avid = ah->qplib_ah.id;
2463 	}
2464 	switch (wr->opcode) {
2465 	case IB_WR_SEND:
2466 		wqe->type = BNXT_QPLIB_SWQE_TYPE_SEND;
2467 		break;
2468 	case IB_WR_SEND_WITH_IMM:
2469 		wqe->type = BNXT_QPLIB_SWQE_TYPE_SEND_WITH_IMM;
2470 		wqe->send.imm_data = wr->ex.imm_data;
2471 		break;
2472 	case IB_WR_SEND_WITH_INV:
2473 		wqe->type = BNXT_QPLIB_SWQE_TYPE_SEND_WITH_INV;
2474 		wqe->send.inv_key = wr->ex.invalidate_rkey;
2475 		break;
2476 	default:
2477 		return -EINVAL;
2478 	}
2479 	if (wr->send_flags & IB_SEND_SIGNALED)
2480 		wqe->flags |= BNXT_QPLIB_SWQE_FLAGS_SIGNAL_COMP;
2481 	if (wr->send_flags & IB_SEND_FENCE)
2482 		wqe->flags |= BNXT_QPLIB_SWQE_FLAGS_UC_FENCE;
2483 	if (wr->send_flags & IB_SEND_SOLICITED)
2484 		wqe->flags |= BNXT_QPLIB_SWQE_FLAGS_SOLICIT_EVENT;
2485 	if (wr->send_flags & IB_SEND_INLINE)
2486 		wqe->flags |= BNXT_QPLIB_SWQE_FLAGS_INLINE;
2487 
2488 	return 0;
2489 }
2490 
2491 static int bnxt_re_build_rdma_wqe(const struct ib_send_wr *wr,
2492 				  struct bnxt_qplib_swqe *wqe)
2493 {
2494 	switch (wr->opcode) {
2495 	case IB_WR_RDMA_WRITE:
2496 		wqe->type = BNXT_QPLIB_SWQE_TYPE_RDMA_WRITE;
2497 		break;
2498 	case IB_WR_RDMA_WRITE_WITH_IMM:
2499 		wqe->type = BNXT_QPLIB_SWQE_TYPE_RDMA_WRITE_WITH_IMM;
2500 		wqe->rdma.imm_data = wr->ex.imm_data;
2501 		break;
2502 	case IB_WR_RDMA_READ:
2503 		wqe->type = BNXT_QPLIB_SWQE_TYPE_RDMA_READ;
2504 		wqe->rdma.inv_key = wr->ex.invalidate_rkey;
2505 		break;
2506 	default:
2507 		return -EINVAL;
2508 	}
2509 	wqe->rdma.remote_va = rdma_wr(wr)->remote_addr;
2510 	wqe->rdma.r_key = rdma_wr(wr)->rkey;
2511 	if (wr->send_flags & IB_SEND_SIGNALED)
2512 		wqe->flags |= BNXT_QPLIB_SWQE_FLAGS_SIGNAL_COMP;
2513 	if (wr->send_flags & IB_SEND_FENCE)
2514 		wqe->flags |= BNXT_QPLIB_SWQE_FLAGS_UC_FENCE;
2515 	if (wr->send_flags & IB_SEND_SOLICITED)
2516 		wqe->flags |= BNXT_QPLIB_SWQE_FLAGS_SOLICIT_EVENT;
2517 	if (wr->send_flags & IB_SEND_INLINE)
2518 		wqe->flags |= BNXT_QPLIB_SWQE_FLAGS_INLINE;
2519 
2520 	return 0;
2521 }
2522 
2523 static int bnxt_re_build_atomic_wqe(const struct ib_send_wr *wr,
2524 				    struct bnxt_qplib_swqe *wqe)
2525 {
2526 	switch (wr->opcode) {
2527 	case IB_WR_ATOMIC_CMP_AND_SWP:
2528 		wqe->type = BNXT_QPLIB_SWQE_TYPE_ATOMIC_CMP_AND_SWP;
2529 		wqe->atomic.cmp_data = atomic_wr(wr)->compare_add;
2530 		wqe->atomic.swap_data = atomic_wr(wr)->swap;
2531 		break;
2532 	case IB_WR_ATOMIC_FETCH_AND_ADD:
2533 		wqe->type = BNXT_QPLIB_SWQE_TYPE_ATOMIC_FETCH_AND_ADD;
2534 		wqe->atomic.cmp_data = atomic_wr(wr)->compare_add;
2535 		break;
2536 	default:
2537 		return -EINVAL;
2538 	}
2539 	wqe->atomic.remote_va = atomic_wr(wr)->remote_addr;
2540 	wqe->atomic.r_key = atomic_wr(wr)->rkey;
2541 	if (wr->send_flags & IB_SEND_SIGNALED)
2542 		wqe->flags |= BNXT_QPLIB_SWQE_FLAGS_SIGNAL_COMP;
2543 	if (wr->send_flags & IB_SEND_FENCE)
2544 		wqe->flags |= BNXT_QPLIB_SWQE_FLAGS_UC_FENCE;
2545 	if (wr->send_flags & IB_SEND_SOLICITED)
2546 		wqe->flags |= BNXT_QPLIB_SWQE_FLAGS_SOLICIT_EVENT;
2547 	return 0;
2548 }
2549 
2550 static int bnxt_re_build_inv_wqe(const struct ib_send_wr *wr,
2551 				 struct bnxt_qplib_swqe *wqe)
2552 {
2553 	wqe->type = BNXT_QPLIB_SWQE_TYPE_LOCAL_INV;
2554 	wqe->local_inv.inv_l_key = wr->ex.invalidate_rkey;
2555 
2556 	/* Need unconditional fence for local invalidate
2557 	 * opcode to work as expected.
2558 	 */
2559 	wqe->flags |= BNXT_QPLIB_SWQE_FLAGS_UC_FENCE;
2560 
2561 	if (wr->send_flags & IB_SEND_SIGNALED)
2562 		wqe->flags |= BNXT_QPLIB_SWQE_FLAGS_SIGNAL_COMP;
2563 	if (wr->send_flags & IB_SEND_SOLICITED)
2564 		wqe->flags |= BNXT_QPLIB_SWQE_FLAGS_SOLICIT_EVENT;
2565 
2566 	return 0;
2567 }
2568 
2569 static int bnxt_re_build_reg_wqe(const struct ib_reg_wr *wr,
2570 				 struct bnxt_qplib_swqe *wqe)
2571 {
2572 	struct bnxt_re_mr *mr = container_of(wr->mr, struct bnxt_re_mr, ib_mr);
2573 	struct bnxt_qplib_frpl *qplib_frpl = &mr->qplib_frpl;
2574 	int access = wr->access;
2575 
2576 	wqe->frmr.pbl_ptr = (__le64 *)qplib_frpl->hwq.pbl_ptr[0];
2577 	wqe->frmr.pbl_dma_ptr = qplib_frpl->hwq.pbl_dma_ptr[0];
2578 	wqe->frmr.page_list = mr->pages;
2579 	wqe->frmr.page_list_len = mr->npages;
2580 	wqe->frmr.levels = qplib_frpl->hwq.level;
2581 	wqe->type = BNXT_QPLIB_SWQE_TYPE_REG_MR;
2582 
2583 	/* Need unconditional fence for reg_mr
2584 	 * opcode to function as expected.
2585 	 */
2586 
2587 	wqe->flags |= BNXT_QPLIB_SWQE_FLAGS_UC_FENCE;
2588 
2589 	if (wr->wr.send_flags & IB_SEND_SIGNALED)
2590 		wqe->flags |= BNXT_QPLIB_SWQE_FLAGS_SIGNAL_COMP;
2591 
2592 	if (access & IB_ACCESS_LOCAL_WRITE)
2593 		wqe->frmr.access_cntl |= SQ_FR_PMR_ACCESS_CNTL_LOCAL_WRITE;
2594 	if (access & IB_ACCESS_REMOTE_READ)
2595 		wqe->frmr.access_cntl |= SQ_FR_PMR_ACCESS_CNTL_REMOTE_READ;
2596 	if (access & IB_ACCESS_REMOTE_WRITE)
2597 		wqe->frmr.access_cntl |= SQ_FR_PMR_ACCESS_CNTL_REMOTE_WRITE;
2598 	if (access & IB_ACCESS_REMOTE_ATOMIC)
2599 		wqe->frmr.access_cntl |= SQ_FR_PMR_ACCESS_CNTL_REMOTE_ATOMIC;
2600 	if (access & IB_ACCESS_MW_BIND)
2601 		wqe->frmr.access_cntl |= SQ_FR_PMR_ACCESS_CNTL_WINDOW_BIND;
2602 
2603 	wqe->frmr.l_key = wr->key;
2604 	wqe->frmr.length = wr->mr->length;
2605 	wqe->frmr.pbl_pg_sz_log = ilog2(PAGE_SIZE >> PAGE_SHIFT_4K);
2606 	wqe->frmr.pg_sz_log = ilog2(wr->mr->page_size >> PAGE_SHIFT_4K);
2607 	wqe->frmr.va = wr->mr->iova;
2608 	return 0;
2609 }
2610 
2611 static int bnxt_re_copy_inline_data(struct bnxt_re_dev *rdev,
2612 				    const struct ib_send_wr *wr,
2613 				    struct bnxt_qplib_swqe *wqe)
2614 {
2615 	/*  Copy the inline data to the data  field */
2616 	u8 *in_data;
2617 	u32 i, sge_len;
2618 	void *sge_addr;
2619 
2620 	in_data = wqe->inline_data;
2621 	for (i = 0; i < wr->num_sge; i++) {
2622 		sge_addr = (void *)(unsigned long)
2623 				wr->sg_list[i].addr;
2624 		sge_len = wr->sg_list[i].length;
2625 
2626 		if ((sge_len + wqe->inline_len) >
2627 		    BNXT_QPLIB_SWQE_MAX_INLINE_LENGTH) {
2628 			ibdev_err(&rdev->ibdev,
2629 				  "Inline data size requested > supported value");
2630 			return -EINVAL;
2631 		}
2632 		sge_len = wr->sg_list[i].length;
2633 
2634 		memcpy(in_data, sge_addr, sge_len);
2635 		in_data += wr->sg_list[i].length;
2636 		wqe->inline_len += wr->sg_list[i].length;
2637 	}
2638 	return wqe->inline_len;
2639 }
2640 
2641 static int bnxt_re_copy_wr_payload(struct bnxt_re_dev *rdev,
2642 				   const struct ib_send_wr *wr,
2643 				   struct bnxt_qplib_swqe *wqe)
2644 {
2645 	int payload_sz = 0;
2646 
2647 	if (wr->send_flags & IB_SEND_INLINE)
2648 		payload_sz = bnxt_re_copy_inline_data(rdev, wr, wqe);
2649 	else
2650 		payload_sz = bnxt_re_build_sgl(wr->sg_list, wqe->sg_list,
2651 					       wqe->num_sge);
2652 
2653 	return payload_sz;
2654 }
2655 
2656 static void bnxt_ud_qp_hw_stall_workaround(struct bnxt_re_qp *qp)
2657 {
2658 	if ((qp->ib_qp.qp_type == IB_QPT_UD ||
2659 	     qp->ib_qp.qp_type == IB_QPT_GSI ||
2660 	     qp->ib_qp.qp_type == IB_QPT_RAW_ETHERTYPE) &&
2661 	     qp->qplib_qp.wqe_cnt == BNXT_RE_UD_QP_HW_STALL) {
2662 		int qp_attr_mask;
2663 		struct ib_qp_attr qp_attr;
2664 
2665 		qp_attr_mask = IB_QP_STATE;
2666 		qp_attr.qp_state = IB_QPS_RTS;
2667 		bnxt_re_modify_qp(&qp->ib_qp, &qp_attr, qp_attr_mask, NULL);
2668 		qp->qplib_qp.wqe_cnt = 0;
2669 	}
2670 }
2671 
2672 static int bnxt_re_post_send_shadow_qp(struct bnxt_re_dev *rdev,
2673 				       struct bnxt_re_qp *qp,
2674 				       const struct ib_send_wr *wr)
2675 {
2676 	int rc = 0, payload_sz = 0;
2677 	unsigned long flags;
2678 
2679 	spin_lock_irqsave(&qp->sq_lock, flags);
2680 	while (wr) {
2681 		struct bnxt_qplib_swqe wqe = {};
2682 
2683 		/* Common */
2684 		wqe.num_sge = wr->num_sge;
2685 		if (wr->num_sge > qp->qplib_qp.sq.max_sge) {
2686 			ibdev_err(&rdev->ibdev,
2687 				  "Limit exceeded for Send SGEs");
2688 			rc = -EINVAL;
2689 			goto bad;
2690 		}
2691 
2692 		payload_sz = bnxt_re_copy_wr_payload(qp->rdev, wr, &wqe);
2693 		if (payload_sz < 0) {
2694 			rc = -EINVAL;
2695 			goto bad;
2696 		}
2697 		wqe.wr_id = wr->wr_id;
2698 
2699 		wqe.type = BNXT_QPLIB_SWQE_TYPE_SEND;
2700 
2701 		rc = bnxt_re_build_send_wqe(qp, wr, &wqe);
2702 		if (!rc)
2703 			rc = bnxt_qplib_post_send(&qp->qplib_qp, &wqe);
2704 bad:
2705 		if (rc) {
2706 			ibdev_err(&rdev->ibdev,
2707 				  "Post send failed opcode = %#x rc = %d",
2708 				  wr->opcode, rc);
2709 			break;
2710 		}
2711 		wr = wr->next;
2712 	}
2713 	bnxt_qplib_post_send_db(&qp->qplib_qp);
2714 	bnxt_ud_qp_hw_stall_workaround(qp);
2715 	spin_unlock_irqrestore(&qp->sq_lock, flags);
2716 	return rc;
2717 }
2718 
2719 int bnxt_re_post_send(struct ib_qp *ib_qp, const struct ib_send_wr *wr,
2720 		      const struct ib_send_wr **bad_wr)
2721 {
2722 	struct bnxt_re_qp *qp = container_of(ib_qp, struct bnxt_re_qp, ib_qp);
2723 	struct bnxt_qplib_swqe wqe;
2724 	int rc = 0, payload_sz = 0;
2725 	unsigned long flags;
2726 
2727 	spin_lock_irqsave(&qp->sq_lock, flags);
2728 	while (wr) {
2729 		/* House keeping */
2730 		memset(&wqe, 0, sizeof(wqe));
2731 
2732 		/* Common */
2733 		wqe.num_sge = wr->num_sge;
2734 		if (wr->num_sge > qp->qplib_qp.sq.max_sge) {
2735 			ibdev_err(&qp->rdev->ibdev,
2736 				  "Limit exceeded for Send SGEs");
2737 			rc = -EINVAL;
2738 			goto bad;
2739 		}
2740 
2741 		payload_sz = bnxt_re_copy_wr_payload(qp->rdev, wr, &wqe);
2742 		if (payload_sz < 0) {
2743 			rc = -EINVAL;
2744 			goto bad;
2745 		}
2746 		wqe.wr_id = wr->wr_id;
2747 
2748 		switch (wr->opcode) {
2749 		case IB_WR_SEND:
2750 		case IB_WR_SEND_WITH_IMM:
2751 			if (qp->qplib_qp.type == CMDQ_CREATE_QP1_TYPE_GSI) {
2752 				rc = bnxt_re_build_qp1_send_v2(qp, wr, &wqe,
2753 							       payload_sz);
2754 				if (rc)
2755 					goto bad;
2756 				wqe.rawqp1.lflags |=
2757 					SQ_SEND_RAWETH_QP1_LFLAGS_ROCE_CRC;
2758 			}
2759 			switch (wr->send_flags) {
2760 			case IB_SEND_IP_CSUM:
2761 				wqe.rawqp1.lflags |=
2762 					SQ_SEND_RAWETH_QP1_LFLAGS_IP_CHKSUM;
2763 				break;
2764 			default:
2765 				break;
2766 			}
2767 			fallthrough;
2768 		case IB_WR_SEND_WITH_INV:
2769 			rc = bnxt_re_build_send_wqe(qp, wr, &wqe);
2770 			break;
2771 		case IB_WR_RDMA_WRITE:
2772 		case IB_WR_RDMA_WRITE_WITH_IMM:
2773 		case IB_WR_RDMA_READ:
2774 			rc = bnxt_re_build_rdma_wqe(wr, &wqe);
2775 			break;
2776 		case IB_WR_ATOMIC_CMP_AND_SWP:
2777 		case IB_WR_ATOMIC_FETCH_AND_ADD:
2778 			rc = bnxt_re_build_atomic_wqe(wr, &wqe);
2779 			break;
2780 		case IB_WR_RDMA_READ_WITH_INV:
2781 			ibdev_err(&qp->rdev->ibdev,
2782 				  "RDMA Read with Invalidate is not supported");
2783 			rc = -EINVAL;
2784 			goto bad;
2785 		case IB_WR_LOCAL_INV:
2786 			rc = bnxt_re_build_inv_wqe(wr, &wqe);
2787 			break;
2788 		case IB_WR_REG_MR:
2789 			rc = bnxt_re_build_reg_wqe(reg_wr(wr), &wqe);
2790 			break;
2791 		default:
2792 			/* Unsupported WRs */
2793 			ibdev_err(&qp->rdev->ibdev,
2794 				  "WR (%#x) is not supported", wr->opcode);
2795 			rc = -EINVAL;
2796 			goto bad;
2797 		}
2798 		if (!rc)
2799 			rc = bnxt_qplib_post_send(&qp->qplib_qp, &wqe);
2800 bad:
2801 		if (rc) {
2802 			ibdev_err(&qp->rdev->ibdev,
2803 				  "post_send failed op:%#x qps = %#x rc = %d\n",
2804 				  wr->opcode, qp->qplib_qp.state, rc);
2805 			*bad_wr = wr;
2806 			break;
2807 		}
2808 		wr = wr->next;
2809 	}
2810 	bnxt_qplib_post_send_db(&qp->qplib_qp);
2811 	bnxt_ud_qp_hw_stall_workaround(qp);
2812 	spin_unlock_irqrestore(&qp->sq_lock, flags);
2813 
2814 	return rc;
2815 }
2816 
2817 static int bnxt_re_post_recv_shadow_qp(struct bnxt_re_dev *rdev,
2818 				       struct bnxt_re_qp *qp,
2819 				       const struct ib_recv_wr *wr)
2820 {
2821 	struct bnxt_qplib_swqe wqe;
2822 	int rc = 0;
2823 
2824 	while (wr) {
2825 		/* House keeping */
2826 		memset(&wqe, 0, sizeof(wqe));
2827 
2828 		/* Common */
2829 		wqe.num_sge = wr->num_sge;
2830 		if (wr->num_sge > qp->qplib_qp.rq.max_sge) {
2831 			ibdev_err(&rdev->ibdev,
2832 				  "Limit exceeded for Receive SGEs");
2833 			rc = -EINVAL;
2834 			break;
2835 		}
2836 		bnxt_re_build_sgl(wr->sg_list, wqe.sg_list, wr->num_sge);
2837 		wqe.wr_id = wr->wr_id;
2838 		wqe.type = BNXT_QPLIB_SWQE_TYPE_RECV;
2839 
2840 		rc = bnxt_qplib_post_recv(&qp->qplib_qp, &wqe);
2841 		if (rc)
2842 			break;
2843 
2844 		wr = wr->next;
2845 	}
2846 	if (!rc)
2847 		bnxt_qplib_post_recv_db(&qp->qplib_qp);
2848 	return rc;
2849 }
2850 
2851 int bnxt_re_post_recv(struct ib_qp *ib_qp, const struct ib_recv_wr *wr,
2852 		      const struct ib_recv_wr **bad_wr)
2853 {
2854 	struct bnxt_re_qp *qp = container_of(ib_qp, struct bnxt_re_qp, ib_qp);
2855 	struct bnxt_qplib_swqe wqe;
2856 	int rc = 0, payload_sz = 0;
2857 	unsigned long flags;
2858 	u32 count = 0;
2859 
2860 	spin_lock_irqsave(&qp->rq_lock, flags);
2861 	while (wr) {
2862 		/* House keeping */
2863 		memset(&wqe, 0, sizeof(wqe));
2864 
2865 		/* Common */
2866 		wqe.num_sge = wr->num_sge;
2867 		if (wr->num_sge > qp->qplib_qp.rq.max_sge) {
2868 			ibdev_err(&qp->rdev->ibdev,
2869 				  "Limit exceeded for Receive SGEs");
2870 			rc = -EINVAL;
2871 			*bad_wr = wr;
2872 			break;
2873 		}
2874 
2875 		payload_sz = bnxt_re_build_sgl(wr->sg_list, wqe.sg_list,
2876 					       wr->num_sge);
2877 		wqe.wr_id = wr->wr_id;
2878 		wqe.type = BNXT_QPLIB_SWQE_TYPE_RECV;
2879 
2880 		if (ib_qp->qp_type == IB_QPT_GSI &&
2881 		    qp->qplib_qp.type != CMDQ_CREATE_QP_TYPE_GSI)
2882 			rc = bnxt_re_build_qp1_shadow_qp_recv(qp, wr, &wqe,
2883 							      payload_sz);
2884 		if (!rc)
2885 			rc = bnxt_qplib_post_recv(&qp->qplib_qp, &wqe);
2886 		if (rc) {
2887 			*bad_wr = wr;
2888 			break;
2889 		}
2890 
2891 		/* Ring DB if the RQEs posted reaches a threshold value */
2892 		if (++count >= BNXT_RE_RQ_WQE_THRESHOLD) {
2893 			bnxt_qplib_post_recv_db(&qp->qplib_qp);
2894 			count = 0;
2895 		}
2896 
2897 		wr = wr->next;
2898 	}
2899 
2900 	if (count)
2901 		bnxt_qplib_post_recv_db(&qp->qplib_qp);
2902 
2903 	spin_unlock_irqrestore(&qp->rq_lock, flags);
2904 
2905 	return rc;
2906 }
2907 
2908 /* Completion Queues */
2909 int bnxt_re_destroy_cq(struct ib_cq *ib_cq, struct ib_udata *udata)
2910 {
2911 	struct bnxt_re_cq *cq;
2912 	struct bnxt_qplib_nq *nq;
2913 	struct bnxt_re_dev *rdev;
2914 
2915 	cq = container_of(ib_cq, struct bnxt_re_cq, ib_cq);
2916 	rdev = cq->rdev;
2917 	nq = cq->qplib_cq.nq;
2918 
2919 	bnxt_qplib_destroy_cq(&rdev->qplib_res, &cq->qplib_cq);
2920 	ib_umem_release(cq->umem);
2921 
2922 	atomic_dec(&rdev->stats.res.cq_count);
2923 	nq->budget--;
2924 	kfree(cq->cql);
2925 	return 0;
2926 }
2927 
2928 int bnxt_re_create_cq(struct ib_cq *ibcq, const struct ib_cq_init_attr *attr,
2929 		      struct ib_udata *udata)
2930 {
2931 	struct bnxt_re_cq *cq = container_of(ibcq, struct bnxt_re_cq, ib_cq);
2932 	struct bnxt_re_dev *rdev = to_bnxt_re_dev(ibcq->device, ibdev);
2933 	struct bnxt_re_ucontext *uctx =
2934 		rdma_udata_to_drv_context(udata, struct bnxt_re_ucontext, ib_uctx);
2935 	struct bnxt_qplib_dev_attr *dev_attr = &rdev->dev_attr;
2936 	int rc, entries;
2937 	int cqe = attr->cqe;
2938 	struct bnxt_qplib_nq *nq = NULL;
2939 	unsigned int nq_alloc_cnt;
2940 	u32 active_cqs;
2941 
2942 	if (attr->flags)
2943 		return -EOPNOTSUPP;
2944 
2945 	/* Validate CQ fields */
2946 	if (cqe < 1 || cqe > dev_attr->max_cq_wqes) {
2947 		ibdev_err(&rdev->ibdev, "Failed to create CQ -max exceeded");
2948 		return -EINVAL;
2949 	}
2950 
2951 	cq->rdev = rdev;
2952 	cq->qplib_cq.cq_handle = (u64)(unsigned long)(&cq->qplib_cq);
2953 
2954 	entries = bnxt_re_init_depth(cqe + 1, uctx);
2955 	if (entries > dev_attr->max_cq_wqes + 1)
2956 		entries = dev_attr->max_cq_wqes + 1;
2957 
2958 	cq->qplib_cq.sg_info.pgsize = PAGE_SIZE;
2959 	cq->qplib_cq.sg_info.pgshft = PAGE_SHIFT;
2960 	if (udata) {
2961 		struct bnxt_re_cq_req req;
2962 		if (ib_copy_from_udata(&req, udata, sizeof(req))) {
2963 			rc = -EFAULT;
2964 			goto fail;
2965 		}
2966 
2967 		cq->umem = ib_umem_get(&rdev->ibdev, req.cq_va,
2968 				       entries * sizeof(struct cq_base),
2969 				       IB_ACCESS_LOCAL_WRITE);
2970 		if (IS_ERR(cq->umem)) {
2971 			rc = PTR_ERR(cq->umem);
2972 			goto fail;
2973 		}
2974 		cq->qplib_cq.sg_info.umem = cq->umem;
2975 		cq->qplib_cq.dpi = &uctx->dpi;
2976 	} else {
2977 		cq->max_cql = min_t(u32, entries, MAX_CQL_PER_POLL);
2978 		cq->cql = kcalloc(cq->max_cql, sizeof(struct bnxt_qplib_cqe),
2979 				  GFP_KERNEL);
2980 		if (!cq->cql) {
2981 			rc = -ENOMEM;
2982 			goto fail;
2983 		}
2984 
2985 		cq->qplib_cq.dpi = &rdev->dpi_privileged;
2986 	}
2987 	/*
2988 	 * Allocating the NQ in a round robin fashion. nq_alloc_cnt is a
2989 	 * used for getting the NQ index.
2990 	 */
2991 	nq_alloc_cnt = atomic_inc_return(&rdev->nq_alloc_cnt);
2992 	nq = &rdev->nq[nq_alloc_cnt % (rdev->num_msix - 1)];
2993 	cq->qplib_cq.max_wqe = entries;
2994 	cq->qplib_cq.cnq_hw_ring_id = nq->ring_id;
2995 	cq->qplib_cq.nq	= nq;
2996 
2997 	rc = bnxt_qplib_create_cq(&rdev->qplib_res, &cq->qplib_cq);
2998 	if (rc) {
2999 		ibdev_err(&rdev->ibdev, "Failed to create HW CQ");
3000 		goto fail;
3001 	}
3002 
3003 	cq->ib_cq.cqe = entries;
3004 	cq->cq_period = cq->qplib_cq.period;
3005 	nq->budget++;
3006 
3007 	active_cqs = atomic_inc_return(&rdev->stats.res.cq_count);
3008 	if (active_cqs > rdev->stats.res.cq_watermark)
3009 		rdev->stats.res.cq_watermark = active_cqs;
3010 	spin_lock_init(&cq->cq_lock);
3011 
3012 	if (udata) {
3013 		struct bnxt_re_cq_resp resp;
3014 
3015 		resp.cqid = cq->qplib_cq.id;
3016 		resp.tail = cq->qplib_cq.hwq.cons;
3017 		resp.phase = cq->qplib_cq.period;
3018 		resp.rsvd = 0;
3019 		rc = ib_copy_to_udata(udata, &resp, sizeof(resp));
3020 		if (rc) {
3021 			ibdev_err(&rdev->ibdev, "Failed to copy CQ udata");
3022 			bnxt_qplib_destroy_cq(&rdev->qplib_res, &cq->qplib_cq);
3023 			goto c2fail;
3024 		}
3025 	}
3026 
3027 	return 0;
3028 
3029 c2fail:
3030 	ib_umem_release(cq->umem);
3031 fail:
3032 	kfree(cq->cql);
3033 	return rc;
3034 }
3035 
3036 static void bnxt_re_resize_cq_complete(struct bnxt_re_cq *cq)
3037 {
3038 	struct bnxt_re_dev *rdev = cq->rdev;
3039 
3040 	bnxt_qplib_resize_cq_complete(&rdev->qplib_res, &cq->qplib_cq);
3041 
3042 	cq->qplib_cq.max_wqe = cq->resize_cqe;
3043 	if (cq->resize_umem) {
3044 		ib_umem_release(cq->umem);
3045 		cq->umem = cq->resize_umem;
3046 		cq->resize_umem = NULL;
3047 		cq->resize_cqe = 0;
3048 	}
3049 }
3050 
3051 int bnxt_re_resize_cq(struct ib_cq *ibcq, int cqe, struct ib_udata *udata)
3052 {
3053 	struct bnxt_qplib_sg_info sg_info = {};
3054 	struct bnxt_qplib_dpi *orig_dpi = NULL;
3055 	struct bnxt_qplib_dev_attr *dev_attr;
3056 	struct bnxt_re_ucontext *uctx = NULL;
3057 	struct bnxt_re_resize_cq_req req;
3058 	struct bnxt_re_dev *rdev;
3059 	struct bnxt_re_cq *cq;
3060 	int rc, entries;
3061 
3062 	cq =  container_of(ibcq, struct bnxt_re_cq, ib_cq);
3063 	rdev = cq->rdev;
3064 	dev_attr = &rdev->dev_attr;
3065 	if (!ibcq->uobject) {
3066 		ibdev_err(&rdev->ibdev, "Kernel CQ Resize not supported");
3067 		return -EOPNOTSUPP;
3068 	}
3069 
3070 	if (cq->resize_umem) {
3071 		ibdev_err(&rdev->ibdev, "Resize CQ %#x failed - Busy",
3072 			  cq->qplib_cq.id);
3073 		return -EBUSY;
3074 	}
3075 
3076 	/* Check the requested cq depth out of supported depth */
3077 	if (cqe < 1 || cqe > dev_attr->max_cq_wqes) {
3078 		ibdev_err(&rdev->ibdev, "Resize CQ %#x failed - out of range cqe %d",
3079 			  cq->qplib_cq.id, cqe);
3080 		return -EINVAL;
3081 	}
3082 
3083 	uctx = rdma_udata_to_drv_context(udata, struct bnxt_re_ucontext, ib_uctx);
3084 	entries = bnxt_re_init_depth(cqe + 1, uctx);
3085 	if (entries > dev_attr->max_cq_wqes + 1)
3086 		entries = dev_attr->max_cq_wqes + 1;
3087 
3088 	/* uverbs consumer */
3089 	if (ib_copy_from_udata(&req, udata, sizeof(req))) {
3090 		rc = -EFAULT;
3091 		goto fail;
3092 	}
3093 
3094 	cq->resize_umem = ib_umem_get(&rdev->ibdev, req.cq_va,
3095 				      entries * sizeof(struct cq_base),
3096 				      IB_ACCESS_LOCAL_WRITE);
3097 	if (IS_ERR(cq->resize_umem)) {
3098 		rc = PTR_ERR(cq->resize_umem);
3099 		cq->resize_umem = NULL;
3100 		ibdev_err(&rdev->ibdev, "%s: ib_umem_get failed! rc = %d\n",
3101 			  __func__, rc);
3102 		goto fail;
3103 	}
3104 	cq->resize_cqe = entries;
3105 	memcpy(&sg_info, &cq->qplib_cq.sg_info, sizeof(sg_info));
3106 	orig_dpi = cq->qplib_cq.dpi;
3107 
3108 	cq->qplib_cq.sg_info.umem = cq->resize_umem;
3109 	cq->qplib_cq.sg_info.pgsize = PAGE_SIZE;
3110 	cq->qplib_cq.sg_info.pgshft = PAGE_SHIFT;
3111 	cq->qplib_cq.dpi = &uctx->dpi;
3112 
3113 	rc = bnxt_qplib_resize_cq(&rdev->qplib_res, &cq->qplib_cq, entries);
3114 	if (rc) {
3115 		ibdev_err(&rdev->ibdev, "Resize HW CQ %#x failed!",
3116 			  cq->qplib_cq.id);
3117 		goto fail;
3118 	}
3119 
3120 	cq->ib_cq.cqe = cq->resize_cqe;
3121 	atomic_inc(&rdev->stats.res.resize_count);
3122 
3123 	return 0;
3124 
3125 fail:
3126 	if (cq->resize_umem) {
3127 		ib_umem_release(cq->resize_umem);
3128 		cq->resize_umem = NULL;
3129 		cq->resize_cqe = 0;
3130 		memcpy(&cq->qplib_cq.sg_info, &sg_info, sizeof(sg_info));
3131 		cq->qplib_cq.dpi = orig_dpi;
3132 	}
3133 	return rc;
3134 }
3135 
3136 static u8 __req_to_ib_wc_status(u8 qstatus)
3137 {
3138 	switch (qstatus) {
3139 	case CQ_REQ_STATUS_OK:
3140 		return IB_WC_SUCCESS;
3141 	case CQ_REQ_STATUS_BAD_RESPONSE_ERR:
3142 		return IB_WC_BAD_RESP_ERR;
3143 	case CQ_REQ_STATUS_LOCAL_LENGTH_ERR:
3144 		return IB_WC_LOC_LEN_ERR;
3145 	case CQ_REQ_STATUS_LOCAL_QP_OPERATION_ERR:
3146 		return IB_WC_LOC_QP_OP_ERR;
3147 	case CQ_REQ_STATUS_LOCAL_PROTECTION_ERR:
3148 		return IB_WC_LOC_PROT_ERR;
3149 	case CQ_REQ_STATUS_MEMORY_MGT_OPERATION_ERR:
3150 		return IB_WC_GENERAL_ERR;
3151 	case CQ_REQ_STATUS_REMOTE_INVALID_REQUEST_ERR:
3152 		return IB_WC_REM_INV_REQ_ERR;
3153 	case CQ_REQ_STATUS_REMOTE_ACCESS_ERR:
3154 		return IB_WC_REM_ACCESS_ERR;
3155 	case CQ_REQ_STATUS_REMOTE_OPERATION_ERR:
3156 		return IB_WC_REM_OP_ERR;
3157 	case CQ_REQ_STATUS_RNR_NAK_RETRY_CNT_ERR:
3158 		return IB_WC_RNR_RETRY_EXC_ERR;
3159 	case CQ_REQ_STATUS_TRANSPORT_RETRY_CNT_ERR:
3160 		return IB_WC_RETRY_EXC_ERR;
3161 	case CQ_REQ_STATUS_WORK_REQUEST_FLUSHED_ERR:
3162 		return IB_WC_WR_FLUSH_ERR;
3163 	default:
3164 		return IB_WC_GENERAL_ERR;
3165 	}
3166 	return 0;
3167 }
3168 
3169 static u8 __rawqp1_to_ib_wc_status(u8 qstatus)
3170 {
3171 	switch (qstatus) {
3172 	case CQ_RES_RAWETH_QP1_STATUS_OK:
3173 		return IB_WC_SUCCESS;
3174 	case CQ_RES_RAWETH_QP1_STATUS_LOCAL_ACCESS_ERROR:
3175 		return IB_WC_LOC_ACCESS_ERR;
3176 	case CQ_RES_RAWETH_QP1_STATUS_HW_LOCAL_LENGTH_ERR:
3177 		return IB_WC_LOC_LEN_ERR;
3178 	case CQ_RES_RAWETH_QP1_STATUS_LOCAL_PROTECTION_ERR:
3179 		return IB_WC_LOC_PROT_ERR;
3180 	case CQ_RES_RAWETH_QP1_STATUS_LOCAL_QP_OPERATION_ERR:
3181 		return IB_WC_LOC_QP_OP_ERR;
3182 	case CQ_RES_RAWETH_QP1_STATUS_MEMORY_MGT_OPERATION_ERR:
3183 		return IB_WC_GENERAL_ERR;
3184 	case CQ_RES_RAWETH_QP1_STATUS_WORK_REQUEST_FLUSHED_ERR:
3185 		return IB_WC_WR_FLUSH_ERR;
3186 	case CQ_RES_RAWETH_QP1_STATUS_HW_FLUSH_ERR:
3187 		return IB_WC_WR_FLUSH_ERR;
3188 	default:
3189 		return IB_WC_GENERAL_ERR;
3190 	}
3191 }
3192 
3193 static u8 __rc_to_ib_wc_status(u8 qstatus)
3194 {
3195 	switch (qstatus) {
3196 	case CQ_RES_RC_STATUS_OK:
3197 		return IB_WC_SUCCESS;
3198 	case CQ_RES_RC_STATUS_LOCAL_ACCESS_ERROR:
3199 		return IB_WC_LOC_ACCESS_ERR;
3200 	case CQ_RES_RC_STATUS_LOCAL_LENGTH_ERR:
3201 		return IB_WC_LOC_LEN_ERR;
3202 	case CQ_RES_RC_STATUS_LOCAL_PROTECTION_ERR:
3203 		return IB_WC_LOC_PROT_ERR;
3204 	case CQ_RES_RC_STATUS_LOCAL_QP_OPERATION_ERR:
3205 		return IB_WC_LOC_QP_OP_ERR;
3206 	case CQ_RES_RC_STATUS_MEMORY_MGT_OPERATION_ERR:
3207 		return IB_WC_GENERAL_ERR;
3208 	case CQ_RES_RC_STATUS_REMOTE_INVALID_REQUEST_ERR:
3209 		return IB_WC_REM_INV_REQ_ERR;
3210 	case CQ_RES_RC_STATUS_WORK_REQUEST_FLUSHED_ERR:
3211 		return IB_WC_WR_FLUSH_ERR;
3212 	case CQ_RES_RC_STATUS_HW_FLUSH_ERR:
3213 		return IB_WC_WR_FLUSH_ERR;
3214 	default:
3215 		return IB_WC_GENERAL_ERR;
3216 	}
3217 }
3218 
3219 static void bnxt_re_process_req_wc(struct ib_wc *wc, struct bnxt_qplib_cqe *cqe)
3220 {
3221 	switch (cqe->type) {
3222 	case BNXT_QPLIB_SWQE_TYPE_SEND:
3223 		wc->opcode = IB_WC_SEND;
3224 		break;
3225 	case BNXT_QPLIB_SWQE_TYPE_SEND_WITH_IMM:
3226 		wc->opcode = IB_WC_SEND;
3227 		wc->wc_flags |= IB_WC_WITH_IMM;
3228 		break;
3229 	case BNXT_QPLIB_SWQE_TYPE_SEND_WITH_INV:
3230 		wc->opcode = IB_WC_SEND;
3231 		wc->wc_flags |= IB_WC_WITH_INVALIDATE;
3232 		break;
3233 	case BNXT_QPLIB_SWQE_TYPE_RDMA_WRITE:
3234 		wc->opcode = IB_WC_RDMA_WRITE;
3235 		break;
3236 	case BNXT_QPLIB_SWQE_TYPE_RDMA_WRITE_WITH_IMM:
3237 		wc->opcode = IB_WC_RDMA_WRITE;
3238 		wc->wc_flags |= IB_WC_WITH_IMM;
3239 		break;
3240 	case BNXT_QPLIB_SWQE_TYPE_RDMA_READ:
3241 		wc->opcode = IB_WC_RDMA_READ;
3242 		break;
3243 	case BNXT_QPLIB_SWQE_TYPE_ATOMIC_CMP_AND_SWP:
3244 		wc->opcode = IB_WC_COMP_SWAP;
3245 		break;
3246 	case BNXT_QPLIB_SWQE_TYPE_ATOMIC_FETCH_AND_ADD:
3247 		wc->opcode = IB_WC_FETCH_ADD;
3248 		break;
3249 	case BNXT_QPLIB_SWQE_TYPE_LOCAL_INV:
3250 		wc->opcode = IB_WC_LOCAL_INV;
3251 		break;
3252 	case BNXT_QPLIB_SWQE_TYPE_REG_MR:
3253 		wc->opcode = IB_WC_REG_MR;
3254 		break;
3255 	default:
3256 		wc->opcode = IB_WC_SEND;
3257 		break;
3258 	}
3259 
3260 	wc->status = __req_to_ib_wc_status(cqe->status);
3261 }
3262 
3263 static int bnxt_re_check_packet_type(u16 raweth_qp1_flags,
3264 				     u16 raweth_qp1_flags2)
3265 {
3266 	bool is_ipv6 = false, is_ipv4 = false;
3267 
3268 	/* raweth_qp1_flags Bit 9-6 indicates itype */
3269 	if ((raweth_qp1_flags & CQ_RES_RAWETH_QP1_RAWETH_QP1_FLAGS_ITYPE_ROCE)
3270 	    != CQ_RES_RAWETH_QP1_RAWETH_QP1_FLAGS_ITYPE_ROCE)
3271 		return -1;
3272 
3273 	if (raweth_qp1_flags2 &
3274 	    CQ_RES_RAWETH_QP1_RAWETH_QP1_FLAGS2_IP_CS_CALC &&
3275 	    raweth_qp1_flags2 &
3276 	    CQ_RES_RAWETH_QP1_RAWETH_QP1_FLAGS2_L4_CS_CALC) {
3277 		/* raweth_qp1_flags2 Bit 8 indicates ip_type. 0-v4 1 - v6 */
3278 		(raweth_qp1_flags2 &
3279 		 CQ_RES_RAWETH_QP1_RAWETH_QP1_FLAGS2_IP_TYPE) ?
3280 			(is_ipv6 = true) : (is_ipv4 = true);
3281 		return ((is_ipv6) ?
3282 			 BNXT_RE_ROCEV2_IPV6_PACKET :
3283 			 BNXT_RE_ROCEV2_IPV4_PACKET);
3284 	} else {
3285 		return BNXT_RE_ROCE_V1_PACKET;
3286 	}
3287 }
3288 
3289 static int bnxt_re_to_ib_nw_type(int nw_type)
3290 {
3291 	u8 nw_hdr_type = 0xFF;
3292 
3293 	switch (nw_type) {
3294 	case BNXT_RE_ROCE_V1_PACKET:
3295 		nw_hdr_type = RDMA_NETWORK_ROCE_V1;
3296 		break;
3297 	case BNXT_RE_ROCEV2_IPV4_PACKET:
3298 		nw_hdr_type = RDMA_NETWORK_IPV4;
3299 		break;
3300 	case BNXT_RE_ROCEV2_IPV6_PACKET:
3301 		nw_hdr_type = RDMA_NETWORK_IPV6;
3302 		break;
3303 	}
3304 	return nw_hdr_type;
3305 }
3306 
3307 static bool bnxt_re_is_loopback_packet(struct bnxt_re_dev *rdev,
3308 				       void *rq_hdr_buf)
3309 {
3310 	u8 *tmp_buf = NULL;
3311 	struct ethhdr *eth_hdr;
3312 	u16 eth_type;
3313 	bool rc = false;
3314 
3315 	tmp_buf = (u8 *)rq_hdr_buf;
3316 	/*
3317 	 * If dest mac is not same as I/F mac, this could be a
3318 	 * loopback address or multicast address, check whether
3319 	 * it is a loopback packet
3320 	 */
3321 	if (!ether_addr_equal(tmp_buf, rdev->netdev->dev_addr)) {
3322 		tmp_buf += 4;
3323 		/* Check the  ether type */
3324 		eth_hdr = (struct ethhdr *)tmp_buf;
3325 		eth_type = ntohs(eth_hdr->h_proto);
3326 		switch (eth_type) {
3327 		case ETH_P_IBOE:
3328 			rc = true;
3329 			break;
3330 		case ETH_P_IP:
3331 		case ETH_P_IPV6: {
3332 			u32 len;
3333 			struct udphdr *udp_hdr;
3334 
3335 			len = (eth_type == ETH_P_IP ? sizeof(struct iphdr) :
3336 						      sizeof(struct ipv6hdr));
3337 			tmp_buf += sizeof(struct ethhdr) + len;
3338 			udp_hdr = (struct udphdr *)tmp_buf;
3339 			if (ntohs(udp_hdr->dest) ==
3340 				    ROCE_V2_UDP_DPORT)
3341 				rc = true;
3342 			break;
3343 			}
3344 		default:
3345 			break;
3346 		}
3347 	}
3348 
3349 	return rc;
3350 }
3351 
3352 static int bnxt_re_process_raw_qp_pkt_rx(struct bnxt_re_qp *gsi_qp,
3353 					 struct bnxt_qplib_cqe *cqe)
3354 {
3355 	struct bnxt_re_dev *rdev = gsi_qp->rdev;
3356 	struct bnxt_re_sqp_entries *sqp_entry = NULL;
3357 	struct bnxt_re_qp *gsi_sqp = rdev->gsi_ctx.gsi_sqp;
3358 	dma_addr_t shrq_hdr_buf_map;
3359 	struct ib_sge s_sge[2] = {};
3360 	struct ib_sge r_sge[2] = {};
3361 	struct bnxt_re_ah *gsi_sah;
3362 	struct ib_recv_wr rwr = {};
3363 	dma_addr_t rq_hdr_buf_map;
3364 	struct ib_ud_wr udwr = {};
3365 	struct ib_send_wr *swr;
3366 	u32 skip_bytes = 0;
3367 	int pkt_type = 0;
3368 	void *rq_hdr_buf;
3369 	u32 offset = 0;
3370 	u32 tbl_idx;
3371 	int rc;
3372 
3373 	swr = &udwr.wr;
3374 	tbl_idx = cqe->wr_id;
3375 
3376 	rq_hdr_buf = gsi_qp->qplib_qp.rq_hdr_buf +
3377 			(tbl_idx * gsi_qp->qplib_qp.rq_hdr_buf_size);
3378 	rq_hdr_buf_map = bnxt_qplib_get_qp_buf_from_index(&gsi_qp->qplib_qp,
3379 							  tbl_idx);
3380 
3381 	/* Shadow QP header buffer */
3382 	shrq_hdr_buf_map = bnxt_qplib_get_qp_buf_from_index(&gsi_qp->qplib_qp,
3383 							    tbl_idx);
3384 	sqp_entry = &rdev->gsi_ctx.sqp_tbl[tbl_idx];
3385 
3386 	/* Store this cqe */
3387 	memcpy(&sqp_entry->cqe, cqe, sizeof(struct bnxt_qplib_cqe));
3388 	sqp_entry->qp1_qp = gsi_qp;
3389 
3390 	/* Find packet type from the cqe */
3391 
3392 	pkt_type = bnxt_re_check_packet_type(cqe->raweth_qp1_flags,
3393 					     cqe->raweth_qp1_flags2);
3394 	if (pkt_type < 0) {
3395 		ibdev_err(&rdev->ibdev, "Invalid packet\n");
3396 		return -EINVAL;
3397 	}
3398 
3399 	/* Adjust the offset for the user buffer and post in the rq */
3400 
3401 	if (pkt_type == BNXT_RE_ROCEV2_IPV4_PACKET)
3402 		offset = 20;
3403 
3404 	/*
3405 	 * QP1 loopback packet has 4 bytes of internal header before
3406 	 * ether header. Skip these four bytes.
3407 	 */
3408 	if (bnxt_re_is_loopback_packet(rdev, rq_hdr_buf))
3409 		skip_bytes = 4;
3410 
3411 	/* First send SGE . Skip the ether header*/
3412 	s_sge[0].addr = rq_hdr_buf_map + BNXT_QPLIB_MAX_QP1_RQ_ETH_HDR_SIZE
3413 			+ skip_bytes;
3414 	s_sge[0].lkey = 0xFFFFFFFF;
3415 	s_sge[0].length = offset ? BNXT_QPLIB_MAX_GRH_HDR_SIZE_IPV4 :
3416 				BNXT_QPLIB_MAX_GRH_HDR_SIZE_IPV6;
3417 
3418 	/* Second Send SGE */
3419 	s_sge[1].addr = s_sge[0].addr + s_sge[0].length +
3420 			BNXT_QPLIB_MAX_QP1_RQ_BDETH_HDR_SIZE;
3421 	if (pkt_type != BNXT_RE_ROCE_V1_PACKET)
3422 		s_sge[1].addr += 8;
3423 	s_sge[1].lkey = 0xFFFFFFFF;
3424 	s_sge[1].length = 256;
3425 
3426 	/* First recv SGE */
3427 
3428 	r_sge[0].addr = shrq_hdr_buf_map;
3429 	r_sge[0].lkey = 0xFFFFFFFF;
3430 	r_sge[0].length = 40;
3431 
3432 	r_sge[1].addr = sqp_entry->sge.addr + offset;
3433 	r_sge[1].lkey = sqp_entry->sge.lkey;
3434 	r_sge[1].length = BNXT_QPLIB_MAX_GRH_HDR_SIZE_IPV6 + 256 - offset;
3435 
3436 	/* Create receive work request */
3437 	rwr.num_sge = 2;
3438 	rwr.sg_list = r_sge;
3439 	rwr.wr_id = tbl_idx;
3440 	rwr.next = NULL;
3441 
3442 	rc = bnxt_re_post_recv_shadow_qp(rdev, gsi_sqp, &rwr);
3443 	if (rc) {
3444 		ibdev_err(&rdev->ibdev,
3445 			  "Failed to post Rx buffers to shadow QP");
3446 		return -ENOMEM;
3447 	}
3448 
3449 	swr->num_sge = 2;
3450 	swr->sg_list = s_sge;
3451 	swr->wr_id = tbl_idx;
3452 	swr->opcode = IB_WR_SEND;
3453 	swr->next = NULL;
3454 	gsi_sah = rdev->gsi_ctx.gsi_sah;
3455 	udwr.ah = &gsi_sah->ib_ah;
3456 	udwr.remote_qpn = gsi_sqp->qplib_qp.id;
3457 	udwr.remote_qkey = gsi_sqp->qplib_qp.qkey;
3458 
3459 	/* post data received  in the send queue */
3460 	return bnxt_re_post_send_shadow_qp(rdev, gsi_sqp, swr);
3461 }
3462 
3463 static void bnxt_re_process_res_rawqp1_wc(struct ib_wc *wc,
3464 					  struct bnxt_qplib_cqe *cqe)
3465 {
3466 	wc->opcode = IB_WC_RECV;
3467 	wc->status = __rawqp1_to_ib_wc_status(cqe->status);
3468 	wc->wc_flags |= IB_WC_GRH;
3469 }
3470 
3471 static bool bnxt_re_check_if_vlan_valid(struct bnxt_re_dev *rdev,
3472 					u16 vlan_id)
3473 {
3474 	/*
3475 	 * Check if the vlan is configured in the host.  If not configured, it
3476 	 * can be a transparent VLAN. So dont report the vlan id.
3477 	 */
3478 	if (!__vlan_find_dev_deep_rcu(rdev->netdev,
3479 				      htons(ETH_P_8021Q), vlan_id))
3480 		return false;
3481 	return true;
3482 }
3483 
3484 static bool bnxt_re_is_vlan_pkt(struct bnxt_qplib_cqe *orig_cqe,
3485 				u16 *vid, u8 *sl)
3486 {
3487 	bool ret = false;
3488 	u32 metadata;
3489 	u16 tpid;
3490 
3491 	metadata = orig_cqe->raweth_qp1_metadata;
3492 	if (orig_cqe->raweth_qp1_flags2 &
3493 		CQ_RES_RAWETH_QP1_RAWETH_QP1_FLAGS2_META_FORMAT_VLAN) {
3494 		tpid = ((metadata &
3495 			 CQ_RES_RAWETH_QP1_RAWETH_QP1_METADATA_TPID_MASK) >>
3496 			 CQ_RES_RAWETH_QP1_RAWETH_QP1_METADATA_TPID_SFT);
3497 		if (tpid == ETH_P_8021Q) {
3498 			*vid = metadata &
3499 			       CQ_RES_RAWETH_QP1_RAWETH_QP1_METADATA_VID_MASK;
3500 			*sl = (metadata &
3501 			       CQ_RES_RAWETH_QP1_RAWETH_QP1_METADATA_PRI_MASK) >>
3502 			       CQ_RES_RAWETH_QP1_RAWETH_QP1_METADATA_PRI_SFT;
3503 			ret = true;
3504 		}
3505 	}
3506 
3507 	return ret;
3508 }
3509 
3510 static void bnxt_re_process_res_rc_wc(struct ib_wc *wc,
3511 				      struct bnxt_qplib_cqe *cqe)
3512 {
3513 	wc->opcode = IB_WC_RECV;
3514 	wc->status = __rc_to_ib_wc_status(cqe->status);
3515 
3516 	if (cqe->flags & CQ_RES_RC_FLAGS_IMM)
3517 		wc->wc_flags |= IB_WC_WITH_IMM;
3518 	if (cqe->flags & CQ_RES_RC_FLAGS_INV)
3519 		wc->wc_flags |= IB_WC_WITH_INVALIDATE;
3520 	if ((cqe->flags & (CQ_RES_RC_FLAGS_RDMA | CQ_RES_RC_FLAGS_IMM)) ==
3521 	    (CQ_RES_RC_FLAGS_RDMA | CQ_RES_RC_FLAGS_IMM))
3522 		wc->opcode = IB_WC_RECV_RDMA_WITH_IMM;
3523 }
3524 
3525 static void bnxt_re_process_res_shadow_qp_wc(struct bnxt_re_qp *gsi_sqp,
3526 					     struct ib_wc *wc,
3527 					     struct bnxt_qplib_cqe *cqe)
3528 {
3529 	struct bnxt_re_dev *rdev = gsi_sqp->rdev;
3530 	struct bnxt_re_qp *gsi_qp = NULL;
3531 	struct bnxt_qplib_cqe *orig_cqe = NULL;
3532 	struct bnxt_re_sqp_entries *sqp_entry = NULL;
3533 	int nw_type;
3534 	u32 tbl_idx;
3535 	u16 vlan_id;
3536 	u8 sl;
3537 
3538 	tbl_idx = cqe->wr_id;
3539 
3540 	sqp_entry = &rdev->gsi_ctx.sqp_tbl[tbl_idx];
3541 	gsi_qp = sqp_entry->qp1_qp;
3542 	orig_cqe = &sqp_entry->cqe;
3543 
3544 	wc->wr_id = sqp_entry->wrid;
3545 	wc->byte_len = orig_cqe->length;
3546 	wc->qp = &gsi_qp->ib_qp;
3547 
3548 	wc->ex.imm_data = orig_cqe->immdata;
3549 	wc->src_qp = orig_cqe->src_qp;
3550 	memcpy(wc->smac, orig_cqe->smac, ETH_ALEN);
3551 	if (bnxt_re_is_vlan_pkt(orig_cqe, &vlan_id, &sl)) {
3552 		if (bnxt_re_check_if_vlan_valid(rdev, vlan_id)) {
3553 			wc->vlan_id = vlan_id;
3554 			wc->sl = sl;
3555 			wc->wc_flags |= IB_WC_WITH_VLAN;
3556 		}
3557 	}
3558 	wc->port_num = 1;
3559 	wc->vendor_err = orig_cqe->status;
3560 
3561 	wc->opcode = IB_WC_RECV;
3562 	wc->status = __rawqp1_to_ib_wc_status(orig_cqe->status);
3563 	wc->wc_flags |= IB_WC_GRH;
3564 
3565 	nw_type = bnxt_re_check_packet_type(orig_cqe->raweth_qp1_flags,
3566 					    orig_cqe->raweth_qp1_flags2);
3567 	if (nw_type >= 0) {
3568 		wc->network_hdr_type = bnxt_re_to_ib_nw_type(nw_type);
3569 		wc->wc_flags |= IB_WC_WITH_NETWORK_HDR_TYPE;
3570 	}
3571 }
3572 
3573 static void bnxt_re_process_res_ud_wc(struct bnxt_re_qp *qp,
3574 				      struct ib_wc *wc,
3575 				      struct bnxt_qplib_cqe *cqe)
3576 {
3577 	struct bnxt_re_dev *rdev;
3578 	u16 vlan_id = 0;
3579 	u8 nw_type;
3580 
3581 	rdev = qp->rdev;
3582 	wc->opcode = IB_WC_RECV;
3583 	wc->status = __rc_to_ib_wc_status(cqe->status);
3584 
3585 	if (cqe->flags & CQ_RES_UD_FLAGS_IMM)
3586 		wc->wc_flags |= IB_WC_WITH_IMM;
3587 	/* report only on GSI QP for Thor */
3588 	if (qp->qplib_qp.type == CMDQ_CREATE_QP_TYPE_GSI) {
3589 		wc->wc_flags |= IB_WC_GRH;
3590 		memcpy(wc->smac, cqe->smac, ETH_ALEN);
3591 		wc->wc_flags |= IB_WC_WITH_SMAC;
3592 		if (cqe->flags & CQ_RES_UD_FLAGS_META_FORMAT_VLAN) {
3593 			vlan_id = (cqe->cfa_meta & 0xFFF);
3594 		}
3595 		/* Mark only if vlan_id is non zero */
3596 		if (vlan_id && bnxt_re_check_if_vlan_valid(rdev, vlan_id)) {
3597 			wc->vlan_id = vlan_id;
3598 			wc->wc_flags |= IB_WC_WITH_VLAN;
3599 		}
3600 		nw_type = (cqe->flags & CQ_RES_UD_FLAGS_ROCE_IP_VER_MASK) >>
3601 			   CQ_RES_UD_FLAGS_ROCE_IP_VER_SFT;
3602 		wc->network_hdr_type = bnxt_re_to_ib_nw_type(nw_type);
3603 		wc->wc_flags |= IB_WC_WITH_NETWORK_HDR_TYPE;
3604 	}
3605 
3606 }
3607 
3608 static int send_phantom_wqe(struct bnxt_re_qp *qp)
3609 {
3610 	struct bnxt_qplib_qp *lib_qp = &qp->qplib_qp;
3611 	unsigned long flags;
3612 	int rc;
3613 
3614 	spin_lock_irqsave(&qp->sq_lock, flags);
3615 
3616 	rc = bnxt_re_bind_fence_mw(lib_qp);
3617 	if (!rc) {
3618 		lib_qp->sq.phantom_wqe_cnt++;
3619 		ibdev_dbg(&qp->rdev->ibdev,
3620 			  "qp %#x sq->prod %#x sw_prod %#x phantom_wqe_cnt %d\n",
3621 			  lib_qp->id, lib_qp->sq.hwq.prod,
3622 			  HWQ_CMP(lib_qp->sq.hwq.prod, &lib_qp->sq.hwq),
3623 			  lib_qp->sq.phantom_wqe_cnt);
3624 	}
3625 
3626 	spin_unlock_irqrestore(&qp->sq_lock, flags);
3627 	return rc;
3628 }
3629 
3630 int bnxt_re_poll_cq(struct ib_cq *ib_cq, int num_entries, struct ib_wc *wc)
3631 {
3632 	struct bnxt_re_cq *cq = container_of(ib_cq, struct bnxt_re_cq, ib_cq);
3633 	struct bnxt_re_qp *qp, *sh_qp;
3634 	struct bnxt_qplib_cqe *cqe;
3635 	int i, ncqe, budget;
3636 	struct bnxt_qplib_q *sq;
3637 	struct bnxt_qplib_qp *lib_qp;
3638 	u32 tbl_idx;
3639 	struct bnxt_re_sqp_entries *sqp_entry = NULL;
3640 	unsigned long flags;
3641 
3642 	/* User CQ; the only processing we do is to
3643 	 * complete any pending CQ resize operation.
3644 	 */
3645 	if (cq->umem) {
3646 		if (cq->resize_umem)
3647 			bnxt_re_resize_cq_complete(cq);
3648 		return 0;
3649 	}
3650 
3651 	spin_lock_irqsave(&cq->cq_lock, flags);
3652 	budget = min_t(u32, num_entries, cq->max_cql);
3653 	num_entries = budget;
3654 	if (!cq->cql) {
3655 		ibdev_err(&cq->rdev->ibdev, "POLL CQ : no CQL to use");
3656 		goto exit;
3657 	}
3658 	cqe = &cq->cql[0];
3659 	while (budget) {
3660 		lib_qp = NULL;
3661 		ncqe = bnxt_qplib_poll_cq(&cq->qplib_cq, cqe, budget, &lib_qp);
3662 		if (lib_qp) {
3663 			sq = &lib_qp->sq;
3664 			if (sq->send_phantom) {
3665 				qp = container_of(lib_qp,
3666 						  struct bnxt_re_qp, qplib_qp);
3667 				if (send_phantom_wqe(qp) == -ENOMEM)
3668 					ibdev_err(&cq->rdev->ibdev,
3669 						  "Phantom failed! Scheduled to send again\n");
3670 				else
3671 					sq->send_phantom = false;
3672 			}
3673 		}
3674 		if (ncqe < budget)
3675 			ncqe += bnxt_qplib_process_flush_list(&cq->qplib_cq,
3676 							      cqe + ncqe,
3677 							      budget - ncqe);
3678 
3679 		if (!ncqe)
3680 			break;
3681 
3682 		for (i = 0; i < ncqe; i++, cqe++) {
3683 			/* Transcribe each qplib_wqe back to ib_wc */
3684 			memset(wc, 0, sizeof(*wc));
3685 
3686 			wc->wr_id = cqe->wr_id;
3687 			wc->byte_len = cqe->length;
3688 			qp = container_of
3689 				((struct bnxt_qplib_qp *)
3690 				 (unsigned long)(cqe->qp_handle),
3691 				 struct bnxt_re_qp, qplib_qp);
3692 			wc->qp = &qp->ib_qp;
3693 			wc->ex.imm_data = cqe->immdata;
3694 			wc->src_qp = cqe->src_qp;
3695 			memcpy(wc->smac, cqe->smac, ETH_ALEN);
3696 			wc->port_num = 1;
3697 			wc->vendor_err = cqe->status;
3698 
3699 			switch (cqe->opcode) {
3700 			case CQ_BASE_CQE_TYPE_REQ:
3701 				sh_qp = qp->rdev->gsi_ctx.gsi_sqp;
3702 				if (sh_qp &&
3703 				    qp->qplib_qp.id == sh_qp->qplib_qp.id) {
3704 					/* Handle this completion with
3705 					 * the stored completion
3706 					 */
3707 					memset(wc, 0, sizeof(*wc));
3708 					continue;
3709 				}
3710 				bnxt_re_process_req_wc(wc, cqe);
3711 				break;
3712 			case CQ_BASE_CQE_TYPE_RES_RAWETH_QP1:
3713 				if (!cqe->status) {
3714 					int rc = 0;
3715 
3716 					rc = bnxt_re_process_raw_qp_pkt_rx
3717 								(qp, cqe);
3718 					if (!rc) {
3719 						memset(wc, 0, sizeof(*wc));
3720 						continue;
3721 					}
3722 					cqe->status = -1;
3723 				}
3724 				/* Errors need not be looped back.
3725 				 * But change the wr_id to the one
3726 				 * stored in the table
3727 				 */
3728 				tbl_idx = cqe->wr_id;
3729 				sqp_entry = &cq->rdev->gsi_ctx.sqp_tbl[tbl_idx];
3730 				wc->wr_id = sqp_entry->wrid;
3731 				bnxt_re_process_res_rawqp1_wc(wc, cqe);
3732 				break;
3733 			case CQ_BASE_CQE_TYPE_RES_RC:
3734 				bnxt_re_process_res_rc_wc(wc, cqe);
3735 				break;
3736 			case CQ_BASE_CQE_TYPE_RES_UD:
3737 				sh_qp = qp->rdev->gsi_ctx.gsi_sqp;
3738 				if (sh_qp &&
3739 				    qp->qplib_qp.id == sh_qp->qplib_qp.id) {
3740 					/* Handle this completion with
3741 					 * the stored completion
3742 					 */
3743 					if (cqe->status) {
3744 						continue;
3745 					} else {
3746 						bnxt_re_process_res_shadow_qp_wc
3747 								(qp, wc, cqe);
3748 						break;
3749 					}
3750 				}
3751 				bnxt_re_process_res_ud_wc(qp, wc, cqe);
3752 				break;
3753 			default:
3754 				ibdev_err(&cq->rdev->ibdev,
3755 					  "POLL CQ : type 0x%x not handled",
3756 					  cqe->opcode);
3757 				continue;
3758 			}
3759 			wc++;
3760 			budget--;
3761 		}
3762 	}
3763 exit:
3764 	spin_unlock_irqrestore(&cq->cq_lock, flags);
3765 	return num_entries - budget;
3766 }
3767 
3768 int bnxt_re_req_notify_cq(struct ib_cq *ib_cq,
3769 			  enum ib_cq_notify_flags ib_cqn_flags)
3770 {
3771 	struct bnxt_re_cq *cq = container_of(ib_cq, struct bnxt_re_cq, ib_cq);
3772 	int type = 0, rc = 0;
3773 	unsigned long flags;
3774 
3775 	spin_lock_irqsave(&cq->cq_lock, flags);
3776 	/* Trigger on the very next completion */
3777 	if (ib_cqn_flags & IB_CQ_NEXT_COMP)
3778 		type = DBC_DBC_TYPE_CQ_ARMALL;
3779 	/* Trigger on the next solicited completion */
3780 	else if (ib_cqn_flags & IB_CQ_SOLICITED)
3781 		type = DBC_DBC_TYPE_CQ_ARMSE;
3782 
3783 	/* Poll to see if there are missed events */
3784 	if ((ib_cqn_flags & IB_CQ_REPORT_MISSED_EVENTS) &&
3785 	    !(bnxt_qplib_is_cq_empty(&cq->qplib_cq))) {
3786 		rc = 1;
3787 		goto exit;
3788 	}
3789 	bnxt_qplib_req_notify_cq(&cq->qplib_cq, type);
3790 
3791 exit:
3792 	spin_unlock_irqrestore(&cq->cq_lock, flags);
3793 	return rc;
3794 }
3795 
3796 /* Memory Regions */
3797 struct ib_mr *bnxt_re_get_dma_mr(struct ib_pd *ib_pd, int mr_access_flags)
3798 {
3799 	struct bnxt_re_pd *pd = container_of(ib_pd, struct bnxt_re_pd, ib_pd);
3800 	struct bnxt_re_dev *rdev = pd->rdev;
3801 	struct bnxt_re_mr *mr;
3802 	u32 active_mrs;
3803 	int rc;
3804 
3805 	mr = kzalloc(sizeof(*mr), GFP_KERNEL);
3806 	if (!mr)
3807 		return ERR_PTR(-ENOMEM);
3808 
3809 	mr->rdev = rdev;
3810 	mr->qplib_mr.pd = &pd->qplib_pd;
3811 	mr->qplib_mr.flags = __from_ib_access_flags(mr_access_flags);
3812 	mr->qplib_mr.type = CMDQ_ALLOCATE_MRW_MRW_FLAGS_PMR;
3813 
3814 	/* Allocate and register 0 as the address */
3815 	rc = bnxt_qplib_alloc_mrw(&rdev->qplib_res, &mr->qplib_mr);
3816 	if (rc)
3817 		goto fail;
3818 
3819 	mr->qplib_mr.hwq.level = PBL_LVL_MAX;
3820 	mr->qplib_mr.total_size = -1; /* Infinte length */
3821 	rc = bnxt_qplib_reg_mr(&rdev->qplib_res, &mr->qplib_mr, NULL, 0,
3822 			       PAGE_SIZE);
3823 	if (rc)
3824 		goto fail_mr;
3825 
3826 	mr->ib_mr.lkey = mr->qplib_mr.lkey;
3827 	if (mr_access_flags & (IB_ACCESS_REMOTE_WRITE | IB_ACCESS_REMOTE_READ |
3828 			       IB_ACCESS_REMOTE_ATOMIC))
3829 		mr->ib_mr.rkey = mr->ib_mr.lkey;
3830 	active_mrs = atomic_inc_return(&rdev->stats.res.mr_count);
3831 	if (active_mrs > rdev->stats.res.mr_watermark)
3832 		rdev->stats.res.mr_watermark = active_mrs;
3833 
3834 	return &mr->ib_mr;
3835 
3836 fail_mr:
3837 	bnxt_qplib_free_mrw(&rdev->qplib_res, &mr->qplib_mr);
3838 fail:
3839 	kfree(mr);
3840 	return ERR_PTR(rc);
3841 }
3842 
3843 int bnxt_re_dereg_mr(struct ib_mr *ib_mr, struct ib_udata *udata)
3844 {
3845 	struct bnxt_re_mr *mr = container_of(ib_mr, struct bnxt_re_mr, ib_mr);
3846 	struct bnxt_re_dev *rdev = mr->rdev;
3847 	int rc;
3848 
3849 	rc = bnxt_qplib_free_mrw(&rdev->qplib_res, &mr->qplib_mr);
3850 	if (rc) {
3851 		ibdev_err(&rdev->ibdev, "Dereg MR failed: %#x\n", rc);
3852 		return rc;
3853 	}
3854 
3855 	if (mr->pages) {
3856 		rc = bnxt_qplib_free_fast_reg_page_list(&rdev->qplib_res,
3857 							&mr->qplib_frpl);
3858 		kfree(mr->pages);
3859 		mr->npages = 0;
3860 		mr->pages = NULL;
3861 	}
3862 	ib_umem_release(mr->ib_umem);
3863 
3864 	kfree(mr);
3865 	atomic_dec(&rdev->stats.res.mr_count);
3866 	return rc;
3867 }
3868 
3869 static int bnxt_re_set_page(struct ib_mr *ib_mr, u64 addr)
3870 {
3871 	struct bnxt_re_mr *mr = container_of(ib_mr, struct bnxt_re_mr, ib_mr);
3872 
3873 	if (unlikely(mr->npages == mr->qplib_frpl.max_pg_ptrs))
3874 		return -ENOMEM;
3875 
3876 	mr->pages[mr->npages++] = addr;
3877 	return 0;
3878 }
3879 
3880 int bnxt_re_map_mr_sg(struct ib_mr *ib_mr, struct scatterlist *sg, int sg_nents,
3881 		      unsigned int *sg_offset)
3882 {
3883 	struct bnxt_re_mr *mr = container_of(ib_mr, struct bnxt_re_mr, ib_mr);
3884 
3885 	mr->npages = 0;
3886 	return ib_sg_to_pages(ib_mr, sg, sg_nents, sg_offset, bnxt_re_set_page);
3887 }
3888 
3889 struct ib_mr *bnxt_re_alloc_mr(struct ib_pd *ib_pd, enum ib_mr_type type,
3890 			       u32 max_num_sg)
3891 {
3892 	struct bnxt_re_pd *pd = container_of(ib_pd, struct bnxt_re_pd, ib_pd);
3893 	struct bnxt_re_dev *rdev = pd->rdev;
3894 	struct bnxt_re_mr *mr = NULL;
3895 	u32 active_mrs;
3896 	int rc;
3897 
3898 	if (type != IB_MR_TYPE_MEM_REG) {
3899 		ibdev_dbg(&rdev->ibdev, "MR type 0x%x not supported", type);
3900 		return ERR_PTR(-EINVAL);
3901 	}
3902 	if (max_num_sg > MAX_PBL_LVL_1_PGS)
3903 		return ERR_PTR(-EINVAL);
3904 
3905 	mr = kzalloc(sizeof(*mr), GFP_KERNEL);
3906 	if (!mr)
3907 		return ERR_PTR(-ENOMEM);
3908 
3909 	mr->rdev = rdev;
3910 	mr->qplib_mr.pd = &pd->qplib_pd;
3911 	mr->qplib_mr.flags = BNXT_QPLIB_FR_PMR;
3912 	mr->qplib_mr.type = CMDQ_ALLOCATE_MRW_MRW_FLAGS_PMR;
3913 
3914 	rc = bnxt_qplib_alloc_mrw(&rdev->qplib_res, &mr->qplib_mr);
3915 	if (rc)
3916 		goto bail;
3917 
3918 	mr->ib_mr.lkey = mr->qplib_mr.lkey;
3919 	mr->ib_mr.rkey = mr->ib_mr.lkey;
3920 
3921 	mr->pages = kcalloc(max_num_sg, sizeof(u64), GFP_KERNEL);
3922 	if (!mr->pages) {
3923 		rc = -ENOMEM;
3924 		goto fail;
3925 	}
3926 	rc = bnxt_qplib_alloc_fast_reg_page_list(&rdev->qplib_res,
3927 						 &mr->qplib_frpl, max_num_sg);
3928 	if (rc) {
3929 		ibdev_err(&rdev->ibdev,
3930 			  "Failed to allocate HW FR page list");
3931 		goto fail_mr;
3932 	}
3933 
3934 	active_mrs = atomic_inc_return(&rdev->stats.res.mr_count);
3935 	if (active_mrs > rdev->stats.res.mr_watermark)
3936 		rdev->stats.res.mr_watermark = active_mrs;
3937 	return &mr->ib_mr;
3938 
3939 fail_mr:
3940 	kfree(mr->pages);
3941 fail:
3942 	bnxt_qplib_free_mrw(&rdev->qplib_res, &mr->qplib_mr);
3943 bail:
3944 	kfree(mr);
3945 	return ERR_PTR(rc);
3946 }
3947 
3948 struct ib_mw *bnxt_re_alloc_mw(struct ib_pd *ib_pd, enum ib_mw_type type,
3949 			       struct ib_udata *udata)
3950 {
3951 	struct bnxt_re_pd *pd = container_of(ib_pd, struct bnxt_re_pd, ib_pd);
3952 	struct bnxt_re_dev *rdev = pd->rdev;
3953 	struct bnxt_re_mw *mw;
3954 	u32 active_mws;
3955 	int rc;
3956 
3957 	mw = kzalloc(sizeof(*mw), GFP_KERNEL);
3958 	if (!mw)
3959 		return ERR_PTR(-ENOMEM);
3960 	mw->rdev = rdev;
3961 	mw->qplib_mw.pd = &pd->qplib_pd;
3962 
3963 	mw->qplib_mw.type = (type == IB_MW_TYPE_1 ?
3964 			       CMDQ_ALLOCATE_MRW_MRW_FLAGS_MW_TYPE1 :
3965 			       CMDQ_ALLOCATE_MRW_MRW_FLAGS_MW_TYPE2B);
3966 	rc = bnxt_qplib_alloc_mrw(&rdev->qplib_res, &mw->qplib_mw);
3967 	if (rc) {
3968 		ibdev_err(&rdev->ibdev, "Allocate MW failed!");
3969 		goto fail;
3970 	}
3971 	mw->ib_mw.rkey = mw->qplib_mw.rkey;
3972 
3973 	active_mws = atomic_inc_return(&rdev->stats.res.mw_count);
3974 	if (active_mws > rdev->stats.res.mw_watermark)
3975 		rdev->stats.res.mw_watermark = active_mws;
3976 	return &mw->ib_mw;
3977 
3978 fail:
3979 	kfree(mw);
3980 	return ERR_PTR(rc);
3981 }
3982 
3983 int bnxt_re_dealloc_mw(struct ib_mw *ib_mw)
3984 {
3985 	struct bnxt_re_mw *mw = container_of(ib_mw, struct bnxt_re_mw, ib_mw);
3986 	struct bnxt_re_dev *rdev = mw->rdev;
3987 	int rc;
3988 
3989 	rc = bnxt_qplib_free_mrw(&rdev->qplib_res, &mw->qplib_mw);
3990 	if (rc) {
3991 		ibdev_err(&rdev->ibdev, "Free MW failed: %#x\n", rc);
3992 		return rc;
3993 	}
3994 
3995 	kfree(mw);
3996 	atomic_dec(&rdev->stats.res.mw_count);
3997 	return rc;
3998 }
3999 
4000 static struct ib_mr *__bnxt_re_user_reg_mr(struct ib_pd *ib_pd, u64 length, u64 virt_addr,
4001 					   int mr_access_flags, struct ib_umem *umem)
4002 {
4003 	struct bnxt_re_pd *pd = container_of(ib_pd, struct bnxt_re_pd, ib_pd);
4004 	struct bnxt_re_dev *rdev = pd->rdev;
4005 	unsigned long page_size;
4006 	struct bnxt_re_mr *mr;
4007 	int umem_pgs, rc;
4008 	u32 active_mrs;
4009 
4010 	if (length > BNXT_RE_MAX_MR_SIZE) {
4011 		ibdev_err(&rdev->ibdev, "MR Size: %lld > Max supported:%lld\n",
4012 			  length, BNXT_RE_MAX_MR_SIZE);
4013 		return ERR_PTR(-ENOMEM);
4014 	}
4015 
4016 	page_size = ib_umem_find_best_pgsz(umem, BNXT_RE_PAGE_SIZE_SUPPORTED, virt_addr);
4017 	if (!page_size) {
4018 		ibdev_err(&rdev->ibdev, "umem page size unsupported!");
4019 		return ERR_PTR(-EINVAL);
4020 	}
4021 
4022 	mr = kzalloc(sizeof(*mr), GFP_KERNEL);
4023 	if (!mr)
4024 		return ERR_PTR(-ENOMEM);
4025 
4026 	mr->rdev = rdev;
4027 	mr->qplib_mr.pd = &pd->qplib_pd;
4028 	mr->qplib_mr.flags = __from_ib_access_flags(mr_access_flags);
4029 	mr->qplib_mr.type = CMDQ_ALLOCATE_MRW_MRW_FLAGS_MR;
4030 
4031 	rc = bnxt_qplib_alloc_mrw(&rdev->qplib_res, &mr->qplib_mr);
4032 	if (rc) {
4033 		ibdev_err(&rdev->ibdev, "Failed to allocate MR rc = %d", rc);
4034 		rc = -EIO;
4035 		goto free_mr;
4036 	}
4037 	/* The fixed portion of the rkey is the same as the lkey */
4038 	mr->ib_mr.rkey = mr->qplib_mr.rkey;
4039 	mr->ib_umem = umem;
4040 	mr->qplib_mr.va = virt_addr;
4041 	mr->qplib_mr.total_size = length;
4042 
4043 	umem_pgs = ib_umem_num_dma_blocks(umem, page_size);
4044 	rc = bnxt_qplib_reg_mr(&rdev->qplib_res, &mr->qplib_mr, umem,
4045 			       umem_pgs, page_size);
4046 	if (rc) {
4047 		ibdev_err(&rdev->ibdev, "Failed to register user MR - rc = %d\n", rc);
4048 		rc = -EIO;
4049 		goto free_mrw;
4050 	}
4051 
4052 	mr->ib_mr.lkey = mr->qplib_mr.lkey;
4053 	mr->ib_mr.rkey = mr->qplib_mr.lkey;
4054 	active_mrs = atomic_inc_return(&rdev->stats.res.mr_count);
4055 	if (active_mrs > rdev->stats.res.mr_watermark)
4056 		rdev->stats.res.mr_watermark = active_mrs;
4057 
4058 	return &mr->ib_mr;
4059 
4060 free_mrw:
4061 	bnxt_qplib_free_mrw(&rdev->qplib_res, &mr->qplib_mr);
4062 free_mr:
4063 	kfree(mr);
4064 	return ERR_PTR(rc);
4065 }
4066 
4067 struct ib_mr *bnxt_re_reg_user_mr(struct ib_pd *ib_pd, u64 start, u64 length,
4068 				  u64 virt_addr, int mr_access_flags,
4069 				  struct ib_udata *udata)
4070 {
4071 	struct bnxt_re_pd *pd = container_of(ib_pd, struct bnxt_re_pd, ib_pd);
4072 	struct bnxt_re_dev *rdev = pd->rdev;
4073 	struct ib_umem *umem;
4074 	struct ib_mr *ib_mr;
4075 
4076 	umem = ib_umem_get(&rdev->ibdev, start, length, mr_access_flags);
4077 	if (IS_ERR(umem))
4078 		return ERR_CAST(umem);
4079 
4080 	ib_mr = __bnxt_re_user_reg_mr(ib_pd, length, virt_addr, mr_access_flags, umem);
4081 	if (IS_ERR(ib_mr))
4082 		ib_umem_release(umem);
4083 	return ib_mr;
4084 }
4085 
4086 struct ib_mr *bnxt_re_reg_user_mr_dmabuf(struct ib_pd *ib_pd, u64 start,
4087 					 u64 length, u64 virt_addr, int fd,
4088 					 int mr_access_flags, struct ib_udata *udata)
4089 {
4090 	struct bnxt_re_pd *pd = container_of(ib_pd, struct bnxt_re_pd, ib_pd);
4091 	struct bnxt_re_dev *rdev = pd->rdev;
4092 	struct ib_umem_dmabuf *umem_dmabuf;
4093 	struct ib_umem *umem;
4094 	struct ib_mr *ib_mr;
4095 
4096 	umem_dmabuf = ib_umem_dmabuf_get_pinned(&rdev->ibdev, start, length,
4097 						fd, mr_access_flags);
4098 	if (IS_ERR(umem_dmabuf))
4099 		return ERR_CAST(umem_dmabuf);
4100 
4101 	umem = &umem_dmabuf->umem;
4102 
4103 	ib_mr = __bnxt_re_user_reg_mr(ib_pd, length, virt_addr, mr_access_flags, umem);
4104 	if (IS_ERR(ib_mr))
4105 		ib_umem_release(umem);
4106 	return ib_mr;
4107 }
4108 
4109 int bnxt_re_alloc_ucontext(struct ib_ucontext *ctx, struct ib_udata *udata)
4110 {
4111 	struct ib_device *ibdev = ctx->device;
4112 	struct bnxt_re_ucontext *uctx =
4113 		container_of(ctx, struct bnxt_re_ucontext, ib_uctx);
4114 	struct bnxt_re_dev *rdev = to_bnxt_re_dev(ibdev, ibdev);
4115 	struct bnxt_qplib_dev_attr *dev_attr = &rdev->dev_attr;
4116 	struct bnxt_re_user_mmap_entry *entry;
4117 	struct bnxt_re_uctx_resp resp = {};
4118 	struct bnxt_re_uctx_req ureq = {};
4119 	u32 chip_met_rev_num = 0;
4120 	int rc;
4121 
4122 	ibdev_dbg(ibdev, "ABI version requested %u", ibdev->ops.uverbs_abi_ver);
4123 
4124 	if (ibdev->ops.uverbs_abi_ver != BNXT_RE_ABI_VERSION) {
4125 		ibdev_dbg(ibdev, " is different from the device %d ",
4126 			  BNXT_RE_ABI_VERSION);
4127 		return -EPERM;
4128 	}
4129 
4130 	uctx->rdev = rdev;
4131 
4132 	uctx->shpg = (void *)__get_free_page(GFP_KERNEL);
4133 	if (!uctx->shpg) {
4134 		rc = -ENOMEM;
4135 		goto fail;
4136 	}
4137 	spin_lock_init(&uctx->sh_lock);
4138 
4139 	resp.comp_mask = BNXT_RE_UCNTX_CMASK_HAVE_CCTX;
4140 	chip_met_rev_num = rdev->chip_ctx->chip_num;
4141 	chip_met_rev_num |= ((u32)rdev->chip_ctx->chip_rev & 0xFF) <<
4142 			     BNXT_RE_CHIP_ID0_CHIP_REV_SFT;
4143 	chip_met_rev_num |= ((u32)rdev->chip_ctx->chip_metal & 0xFF) <<
4144 			     BNXT_RE_CHIP_ID0_CHIP_MET_SFT;
4145 	resp.chip_id0 = chip_met_rev_num;
4146 	/*Temp, Use xa_alloc instead */
4147 	resp.dev_id = rdev->en_dev->pdev->devfn;
4148 	resp.max_qp = rdev->qplib_ctx.qpc_count;
4149 	resp.pg_size = PAGE_SIZE;
4150 	resp.cqe_sz = sizeof(struct cq_base);
4151 	resp.max_cqd = dev_attr->max_cq_wqes;
4152 
4153 	resp.comp_mask |= BNXT_RE_UCNTX_CMASK_HAVE_MODE;
4154 	resp.mode = rdev->chip_ctx->modes.wqe_mode;
4155 
4156 	if (rdev->chip_ctx->modes.db_push)
4157 		resp.comp_mask |= BNXT_RE_UCNTX_CMASK_WC_DPI_ENABLED;
4158 
4159 	entry = bnxt_re_mmap_entry_insert(uctx, 0, BNXT_RE_MMAP_SH_PAGE, NULL);
4160 	if (!entry) {
4161 		rc = -ENOMEM;
4162 		goto cfail;
4163 	}
4164 	uctx->shpage_mmap = &entry->rdma_entry;
4165 	if (rdev->pacing.dbr_pacing)
4166 		resp.comp_mask |= BNXT_RE_UCNTX_CMASK_DBR_PACING_ENABLED;
4167 
4168 	if (udata->inlen >= sizeof(ureq)) {
4169 		rc = ib_copy_from_udata(&ureq, udata, min(udata->inlen, sizeof(ureq)));
4170 		if (rc)
4171 			goto cfail;
4172 		if (ureq.comp_mask & BNXT_RE_COMP_MASK_REQ_UCNTX_POW2_SUPPORT) {
4173 			resp.comp_mask |= BNXT_RE_UCNTX_CMASK_POW2_DISABLED;
4174 			uctx->cmask |= BNXT_RE_UCNTX_CMASK_POW2_DISABLED;
4175 		}
4176 	}
4177 
4178 	rc = ib_copy_to_udata(udata, &resp, min(udata->outlen, sizeof(resp)));
4179 	if (rc) {
4180 		ibdev_err(ibdev, "Failed to copy user context");
4181 		rc = -EFAULT;
4182 		goto cfail;
4183 	}
4184 
4185 	return 0;
4186 cfail:
4187 	free_page((unsigned long)uctx->shpg);
4188 	uctx->shpg = NULL;
4189 fail:
4190 	return rc;
4191 }
4192 
4193 void bnxt_re_dealloc_ucontext(struct ib_ucontext *ib_uctx)
4194 {
4195 	struct bnxt_re_ucontext *uctx = container_of(ib_uctx,
4196 						   struct bnxt_re_ucontext,
4197 						   ib_uctx);
4198 
4199 	struct bnxt_re_dev *rdev = uctx->rdev;
4200 
4201 	rdma_user_mmap_entry_remove(uctx->shpage_mmap);
4202 	uctx->shpage_mmap = NULL;
4203 	if (uctx->shpg)
4204 		free_page((unsigned long)uctx->shpg);
4205 
4206 	if (uctx->dpi.dbr) {
4207 		/* Free DPI only if this is the first PD allocated by the
4208 		 * application and mark the context dpi as NULL
4209 		 */
4210 		bnxt_qplib_dealloc_dpi(&rdev->qplib_res, &uctx->dpi);
4211 		uctx->dpi.dbr = NULL;
4212 	}
4213 }
4214 
4215 /* Helper function to mmap the virtual memory from user app */
4216 int bnxt_re_mmap(struct ib_ucontext *ib_uctx, struct vm_area_struct *vma)
4217 {
4218 	struct bnxt_re_ucontext *uctx = container_of(ib_uctx,
4219 						   struct bnxt_re_ucontext,
4220 						   ib_uctx);
4221 	struct bnxt_re_user_mmap_entry *bnxt_entry;
4222 	struct rdma_user_mmap_entry *rdma_entry;
4223 	int ret = 0;
4224 	u64 pfn;
4225 
4226 	rdma_entry = rdma_user_mmap_entry_get(&uctx->ib_uctx, vma);
4227 	if (!rdma_entry)
4228 		return -EINVAL;
4229 
4230 	bnxt_entry = container_of(rdma_entry, struct bnxt_re_user_mmap_entry,
4231 				  rdma_entry);
4232 
4233 	switch (bnxt_entry->mmap_flag) {
4234 	case BNXT_RE_MMAP_WC_DB:
4235 		pfn = bnxt_entry->mem_offset >> PAGE_SHIFT;
4236 		ret = rdma_user_mmap_io(ib_uctx, vma, pfn, PAGE_SIZE,
4237 					pgprot_writecombine(vma->vm_page_prot),
4238 					rdma_entry);
4239 		break;
4240 	case BNXT_RE_MMAP_UC_DB:
4241 		pfn = bnxt_entry->mem_offset >> PAGE_SHIFT;
4242 		ret = rdma_user_mmap_io(ib_uctx, vma, pfn, PAGE_SIZE,
4243 					pgprot_noncached(vma->vm_page_prot),
4244 				rdma_entry);
4245 		break;
4246 	case BNXT_RE_MMAP_SH_PAGE:
4247 		ret = vm_insert_page(vma, vma->vm_start, virt_to_page(uctx->shpg));
4248 		break;
4249 	case BNXT_RE_MMAP_DBR_BAR:
4250 		pfn = bnxt_entry->mem_offset >> PAGE_SHIFT;
4251 		ret = rdma_user_mmap_io(ib_uctx, vma, pfn, PAGE_SIZE,
4252 					pgprot_noncached(vma->vm_page_prot),
4253 					rdma_entry);
4254 		break;
4255 	case BNXT_RE_MMAP_DBR_PAGE:
4256 		/* Driver doesn't expect write access for user space */
4257 		if (vma->vm_flags & VM_WRITE)
4258 			return -EFAULT;
4259 		ret = vm_insert_page(vma, vma->vm_start,
4260 				     virt_to_page((void *)bnxt_entry->mem_offset));
4261 		break;
4262 	default:
4263 		ret = -EINVAL;
4264 		break;
4265 	}
4266 
4267 	rdma_user_mmap_entry_put(rdma_entry);
4268 	return ret;
4269 }
4270 
4271 void bnxt_re_mmap_free(struct rdma_user_mmap_entry *rdma_entry)
4272 {
4273 	struct bnxt_re_user_mmap_entry *bnxt_entry;
4274 
4275 	bnxt_entry = container_of(rdma_entry, struct bnxt_re_user_mmap_entry,
4276 				  rdma_entry);
4277 
4278 	kfree(bnxt_entry);
4279 }
4280 
4281 static int UVERBS_HANDLER(BNXT_RE_METHOD_NOTIFY_DRV)(struct uverbs_attr_bundle *attrs)
4282 {
4283 	struct bnxt_re_ucontext *uctx;
4284 
4285 	uctx = container_of(ib_uverbs_get_ucontext(attrs), struct bnxt_re_ucontext, ib_uctx);
4286 	bnxt_re_pacing_alert(uctx->rdev);
4287 	return 0;
4288 }
4289 
4290 static int UVERBS_HANDLER(BNXT_RE_METHOD_ALLOC_PAGE)(struct uverbs_attr_bundle *attrs)
4291 {
4292 	struct ib_uobject *uobj = uverbs_attr_get_uobject(attrs, BNXT_RE_ALLOC_PAGE_HANDLE);
4293 	enum bnxt_re_alloc_page_type alloc_type;
4294 	struct bnxt_re_user_mmap_entry *entry;
4295 	enum bnxt_re_mmap_flag mmap_flag;
4296 	struct bnxt_qplib_chip_ctx *cctx;
4297 	struct bnxt_re_ucontext *uctx;
4298 	struct bnxt_re_dev *rdev;
4299 	u64 mmap_offset;
4300 	u32 length;
4301 	u32 dpi;
4302 	u64 addr;
4303 	int err;
4304 
4305 	uctx = container_of(ib_uverbs_get_ucontext(attrs), struct bnxt_re_ucontext, ib_uctx);
4306 	if (IS_ERR(uctx))
4307 		return PTR_ERR(uctx);
4308 
4309 	err = uverbs_get_const(&alloc_type, attrs, BNXT_RE_ALLOC_PAGE_TYPE);
4310 	if (err)
4311 		return err;
4312 
4313 	rdev = uctx->rdev;
4314 	cctx = rdev->chip_ctx;
4315 
4316 	switch (alloc_type) {
4317 	case BNXT_RE_ALLOC_WC_PAGE:
4318 		if (cctx->modes.db_push)  {
4319 			if (bnxt_qplib_alloc_dpi(&rdev->qplib_res, &uctx->wcdpi,
4320 						 uctx, BNXT_QPLIB_DPI_TYPE_WC))
4321 				return -ENOMEM;
4322 			length = PAGE_SIZE;
4323 			dpi = uctx->wcdpi.dpi;
4324 			addr = (u64)uctx->wcdpi.umdbr;
4325 			mmap_flag = BNXT_RE_MMAP_WC_DB;
4326 		} else {
4327 			return -EINVAL;
4328 		}
4329 
4330 		break;
4331 	case BNXT_RE_ALLOC_DBR_BAR_PAGE:
4332 		length = PAGE_SIZE;
4333 		addr = (u64)rdev->pacing.dbr_bar_addr;
4334 		mmap_flag = BNXT_RE_MMAP_DBR_BAR;
4335 		break;
4336 
4337 	case BNXT_RE_ALLOC_DBR_PAGE:
4338 		length = PAGE_SIZE;
4339 		addr = (u64)rdev->pacing.dbr_page;
4340 		mmap_flag = BNXT_RE_MMAP_DBR_PAGE;
4341 		break;
4342 
4343 	default:
4344 		return -EOPNOTSUPP;
4345 	}
4346 
4347 	entry = bnxt_re_mmap_entry_insert(uctx, addr, mmap_flag, &mmap_offset);
4348 	if (!entry)
4349 		return -ENOMEM;
4350 
4351 	uobj->object = entry;
4352 	uverbs_finalize_uobj_create(attrs, BNXT_RE_ALLOC_PAGE_HANDLE);
4353 	err = uverbs_copy_to(attrs, BNXT_RE_ALLOC_PAGE_MMAP_OFFSET,
4354 			     &mmap_offset, sizeof(mmap_offset));
4355 	if (err)
4356 		return err;
4357 
4358 	err = uverbs_copy_to(attrs, BNXT_RE_ALLOC_PAGE_MMAP_LENGTH,
4359 			     &length, sizeof(length));
4360 	if (err)
4361 		return err;
4362 
4363 	err = uverbs_copy_to(attrs, BNXT_RE_ALLOC_PAGE_DPI,
4364 			     &dpi, sizeof(length));
4365 	if (err)
4366 		return err;
4367 
4368 	return 0;
4369 }
4370 
4371 static int alloc_page_obj_cleanup(struct ib_uobject *uobject,
4372 				  enum rdma_remove_reason why,
4373 			    struct uverbs_attr_bundle *attrs)
4374 {
4375 	struct  bnxt_re_user_mmap_entry *entry = uobject->object;
4376 	struct bnxt_re_ucontext *uctx = entry->uctx;
4377 
4378 	switch (entry->mmap_flag) {
4379 	case BNXT_RE_MMAP_WC_DB:
4380 		if (uctx && uctx->wcdpi.dbr) {
4381 			struct bnxt_re_dev *rdev = uctx->rdev;
4382 
4383 			bnxt_qplib_dealloc_dpi(&rdev->qplib_res, &uctx->wcdpi);
4384 			uctx->wcdpi.dbr = NULL;
4385 		}
4386 		break;
4387 	case BNXT_RE_MMAP_DBR_BAR:
4388 	case BNXT_RE_MMAP_DBR_PAGE:
4389 		break;
4390 	default:
4391 		goto exit;
4392 	}
4393 	rdma_user_mmap_entry_remove(&entry->rdma_entry);
4394 exit:
4395 	return 0;
4396 }
4397 
4398 DECLARE_UVERBS_NAMED_METHOD(BNXT_RE_METHOD_ALLOC_PAGE,
4399 			    UVERBS_ATTR_IDR(BNXT_RE_ALLOC_PAGE_HANDLE,
4400 					    BNXT_RE_OBJECT_ALLOC_PAGE,
4401 					    UVERBS_ACCESS_NEW,
4402 					    UA_MANDATORY),
4403 			    UVERBS_ATTR_CONST_IN(BNXT_RE_ALLOC_PAGE_TYPE,
4404 						 enum bnxt_re_alloc_page_type,
4405 						 UA_MANDATORY),
4406 			    UVERBS_ATTR_PTR_OUT(BNXT_RE_ALLOC_PAGE_MMAP_OFFSET,
4407 						UVERBS_ATTR_TYPE(u64),
4408 						UA_MANDATORY),
4409 			    UVERBS_ATTR_PTR_OUT(BNXT_RE_ALLOC_PAGE_MMAP_LENGTH,
4410 						UVERBS_ATTR_TYPE(u32),
4411 						UA_MANDATORY),
4412 			    UVERBS_ATTR_PTR_OUT(BNXT_RE_ALLOC_PAGE_DPI,
4413 						UVERBS_ATTR_TYPE(u32),
4414 						UA_MANDATORY));
4415 
4416 DECLARE_UVERBS_NAMED_METHOD_DESTROY(BNXT_RE_METHOD_DESTROY_PAGE,
4417 				    UVERBS_ATTR_IDR(BNXT_RE_DESTROY_PAGE_HANDLE,
4418 						    BNXT_RE_OBJECT_ALLOC_PAGE,
4419 						    UVERBS_ACCESS_DESTROY,
4420 						    UA_MANDATORY));
4421 
4422 DECLARE_UVERBS_NAMED_OBJECT(BNXT_RE_OBJECT_ALLOC_PAGE,
4423 			    UVERBS_TYPE_ALLOC_IDR(alloc_page_obj_cleanup),
4424 			    &UVERBS_METHOD(BNXT_RE_METHOD_ALLOC_PAGE),
4425 			    &UVERBS_METHOD(BNXT_RE_METHOD_DESTROY_PAGE));
4426 
4427 DECLARE_UVERBS_NAMED_METHOD(BNXT_RE_METHOD_NOTIFY_DRV);
4428 
4429 DECLARE_UVERBS_GLOBAL_METHODS(BNXT_RE_OBJECT_NOTIFY_DRV,
4430 			      &UVERBS_METHOD(BNXT_RE_METHOD_NOTIFY_DRV));
4431 
4432 const struct uapi_definition bnxt_re_uapi_defs[] = {
4433 	UAPI_DEF_CHAIN_OBJ_TREE_NAMED(BNXT_RE_OBJECT_ALLOC_PAGE),
4434 	UAPI_DEF_CHAIN_OBJ_TREE_NAMED(BNXT_RE_OBJECT_NOTIFY_DRV),
4435 	{}
4436 };
4437