1 /* 2 * Copyright (C) STMicroelectronics 2016 3 * 4 * Author: Benjamin Gaignard <benjamin.gaignard@st.com> 5 * 6 * License terms: GNU General Public License (GPL), version 2 7 */ 8 9 #include <linux/iio/iio.h> 10 #include <linux/iio/sysfs.h> 11 #include <linux/iio/timer/stm32-timer-trigger.h> 12 #include <linux/iio/trigger.h> 13 #include <linux/mfd/stm32-timers.h> 14 #include <linux/module.h> 15 #include <linux/platform_device.h> 16 17 #define MAX_TRIGGERS 7 18 #define MAX_VALIDS 5 19 20 /* List the triggers created by each timer */ 21 static const void *triggers_table[][MAX_TRIGGERS] = { 22 { TIM1_TRGO, TIM1_TRGO2, TIM1_CH1, TIM1_CH2, TIM1_CH3, TIM1_CH4,}, 23 { TIM2_TRGO, TIM2_CH1, TIM2_CH2, TIM2_CH3, TIM2_CH4,}, 24 { TIM3_TRGO, TIM3_CH1, TIM3_CH2, TIM3_CH3, TIM3_CH4,}, 25 { TIM4_TRGO, TIM4_CH1, TIM4_CH2, TIM4_CH3, TIM4_CH4,}, 26 { TIM5_TRGO, TIM5_CH1, TIM5_CH2, TIM5_CH3, TIM5_CH4,}, 27 { TIM6_TRGO,}, 28 { TIM7_TRGO,}, 29 { TIM8_TRGO, TIM8_TRGO2, TIM8_CH1, TIM8_CH2, TIM8_CH3, TIM8_CH4,}, 30 { TIM9_TRGO, TIM9_CH1, TIM9_CH2,}, 31 { }, /* timer 10 */ 32 { }, /* timer 11 */ 33 { TIM12_TRGO, TIM12_CH1, TIM12_CH2,}, 34 }; 35 36 /* List the triggers accepted by each timer */ 37 static const void *valids_table[][MAX_VALIDS] = { 38 { TIM5_TRGO, TIM2_TRGO, TIM3_TRGO, TIM4_TRGO,}, 39 { TIM1_TRGO, TIM8_TRGO, TIM3_TRGO, TIM4_TRGO,}, 40 { TIM1_TRGO, TIM2_TRGO, TIM5_TRGO, TIM4_TRGO,}, 41 { TIM1_TRGO, TIM2_TRGO, TIM3_TRGO, TIM8_TRGO,}, 42 { TIM2_TRGO, TIM3_TRGO, TIM4_TRGO, TIM8_TRGO,}, 43 { }, /* timer 6 */ 44 { }, /* timer 7 */ 45 { TIM1_TRGO, TIM2_TRGO, TIM4_TRGO, TIM5_TRGO,}, 46 { TIM2_TRGO, TIM3_TRGO,}, 47 { }, /* timer 10 */ 48 { }, /* timer 11 */ 49 { TIM4_TRGO, TIM5_TRGO,}, 50 }; 51 52 struct stm32_timer_trigger { 53 struct device *dev; 54 struct regmap *regmap; 55 struct clk *clk; 56 u32 max_arr; 57 const void *triggers; 58 const void *valids; 59 bool has_trgo2; 60 }; 61 62 static bool stm32_timer_is_trgo2_name(const char *name) 63 { 64 return !!strstr(name, "trgo2"); 65 } 66 67 static int stm32_timer_start(struct stm32_timer_trigger *priv, 68 struct iio_trigger *trig, 69 unsigned int frequency) 70 { 71 unsigned long long prd, div; 72 int prescaler = 0; 73 u32 ccer, cr1; 74 75 /* Period and prescaler values depends of clock rate */ 76 div = (unsigned long long)clk_get_rate(priv->clk); 77 78 do_div(div, frequency); 79 80 prd = div; 81 82 /* 83 * Increase prescaler value until we get a result that fit 84 * with auto reload register maximum value. 85 */ 86 while (div > priv->max_arr) { 87 prescaler++; 88 div = prd; 89 do_div(div, (prescaler + 1)); 90 } 91 prd = div; 92 93 if (prescaler > MAX_TIM_PSC) { 94 dev_err(priv->dev, "prescaler exceeds the maximum value\n"); 95 return -EINVAL; 96 } 97 98 /* Check if nobody else use the timer */ 99 regmap_read(priv->regmap, TIM_CCER, &ccer); 100 if (ccer & TIM_CCER_CCXE) 101 return -EBUSY; 102 103 regmap_read(priv->regmap, TIM_CR1, &cr1); 104 if (!(cr1 & TIM_CR1_CEN)) 105 clk_enable(priv->clk); 106 107 regmap_write(priv->regmap, TIM_PSC, prescaler); 108 regmap_write(priv->regmap, TIM_ARR, prd - 1); 109 regmap_update_bits(priv->regmap, TIM_CR1, TIM_CR1_ARPE, TIM_CR1_ARPE); 110 111 /* Force master mode to update mode */ 112 if (stm32_timer_is_trgo2_name(trig->name)) 113 regmap_update_bits(priv->regmap, TIM_CR2, TIM_CR2_MMS2, 114 0x2 << TIM_CR2_MMS2_SHIFT); 115 else 116 regmap_update_bits(priv->regmap, TIM_CR2, TIM_CR2_MMS, 117 0x2 << TIM_CR2_MMS_SHIFT); 118 119 /* Make sure that registers are updated */ 120 regmap_update_bits(priv->regmap, TIM_EGR, TIM_EGR_UG, TIM_EGR_UG); 121 122 /* Enable controller */ 123 regmap_update_bits(priv->regmap, TIM_CR1, TIM_CR1_CEN, TIM_CR1_CEN); 124 125 return 0; 126 } 127 128 static void stm32_timer_stop(struct stm32_timer_trigger *priv) 129 { 130 u32 ccer, cr1; 131 132 regmap_read(priv->regmap, TIM_CCER, &ccer); 133 if (ccer & TIM_CCER_CCXE) 134 return; 135 136 regmap_read(priv->regmap, TIM_CR1, &cr1); 137 if (cr1 & TIM_CR1_CEN) 138 clk_disable(priv->clk); 139 140 /* Stop timer */ 141 regmap_update_bits(priv->regmap, TIM_CR1, TIM_CR1_CEN, 0); 142 regmap_write(priv->regmap, TIM_PSC, 0); 143 regmap_write(priv->regmap, TIM_ARR, 0); 144 145 /* Make sure that registers are updated */ 146 regmap_update_bits(priv->regmap, TIM_EGR, TIM_EGR_UG, TIM_EGR_UG); 147 } 148 149 static ssize_t stm32_tt_store_frequency(struct device *dev, 150 struct device_attribute *attr, 151 const char *buf, size_t len) 152 { 153 struct iio_trigger *trig = to_iio_trigger(dev); 154 struct stm32_timer_trigger *priv = iio_trigger_get_drvdata(trig); 155 unsigned int freq; 156 int ret; 157 158 ret = kstrtouint(buf, 10, &freq); 159 if (ret) 160 return ret; 161 162 if (freq == 0) { 163 stm32_timer_stop(priv); 164 } else { 165 ret = stm32_timer_start(priv, trig, freq); 166 if (ret) 167 return ret; 168 } 169 170 return len; 171 } 172 173 static ssize_t stm32_tt_read_frequency(struct device *dev, 174 struct device_attribute *attr, char *buf) 175 { 176 struct iio_trigger *trig = to_iio_trigger(dev); 177 struct stm32_timer_trigger *priv = iio_trigger_get_drvdata(trig); 178 u32 psc, arr, cr1; 179 unsigned long long freq = 0; 180 181 regmap_read(priv->regmap, TIM_CR1, &cr1); 182 regmap_read(priv->regmap, TIM_PSC, &psc); 183 regmap_read(priv->regmap, TIM_ARR, &arr); 184 185 if (cr1 & TIM_CR1_CEN) { 186 freq = (unsigned long long)clk_get_rate(priv->clk); 187 do_div(freq, psc + 1); 188 do_div(freq, arr + 1); 189 } 190 191 return sprintf(buf, "%d\n", (unsigned int)freq); 192 } 193 194 static IIO_DEV_ATTR_SAMP_FREQ(0660, 195 stm32_tt_read_frequency, 196 stm32_tt_store_frequency); 197 198 #define MASTER_MODE_MAX 7 199 #define MASTER_MODE2_MAX 15 200 201 static char *master_mode_table[] = { 202 "reset", 203 "enable", 204 "update", 205 "compare_pulse", 206 "OC1REF", 207 "OC2REF", 208 "OC3REF", 209 "OC4REF", 210 /* Master mode selection 2 only */ 211 "OC5REF", 212 "OC6REF", 213 "compare_pulse_OC4REF", 214 "compare_pulse_OC6REF", 215 "compare_pulse_OC4REF_r_or_OC6REF_r", 216 "compare_pulse_OC4REF_r_or_OC6REF_f", 217 "compare_pulse_OC5REF_r_or_OC6REF_r", 218 "compare_pulse_OC5REF_r_or_OC6REF_f", 219 }; 220 221 static ssize_t stm32_tt_show_master_mode(struct device *dev, 222 struct device_attribute *attr, 223 char *buf) 224 { 225 struct stm32_timer_trigger *priv = dev_get_drvdata(dev); 226 struct iio_trigger *trig = to_iio_trigger(dev); 227 u32 cr2; 228 229 regmap_read(priv->regmap, TIM_CR2, &cr2); 230 231 if (stm32_timer_is_trgo2_name(trig->name)) 232 cr2 = (cr2 & TIM_CR2_MMS2) >> TIM_CR2_MMS2_SHIFT; 233 else 234 cr2 = (cr2 & TIM_CR2_MMS) >> TIM_CR2_MMS_SHIFT; 235 236 return snprintf(buf, PAGE_SIZE, "%s\n", master_mode_table[cr2]); 237 } 238 239 static ssize_t stm32_tt_store_master_mode(struct device *dev, 240 struct device_attribute *attr, 241 const char *buf, size_t len) 242 { 243 struct stm32_timer_trigger *priv = dev_get_drvdata(dev); 244 struct iio_trigger *trig = to_iio_trigger(dev); 245 u32 mask, shift, master_mode_max; 246 int i; 247 248 if (stm32_timer_is_trgo2_name(trig->name)) { 249 mask = TIM_CR2_MMS2; 250 shift = TIM_CR2_MMS2_SHIFT; 251 master_mode_max = MASTER_MODE2_MAX; 252 } else { 253 mask = TIM_CR2_MMS; 254 shift = TIM_CR2_MMS_SHIFT; 255 master_mode_max = MASTER_MODE_MAX; 256 } 257 258 for (i = 0; i <= master_mode_max; i++) { 259 if (!strncmp(master_mode_table[i], buf, 260 strlen(master_mode_table[i]))) { 261 regmap_update_bits(priv->regmap, TIM_CR2, mask, 262 i << shift); 263 /* Make sure that registers are updated */ 264 regmap_update_bits(priv->regmap, TIM_EGR, 265 TIM_EGR_UG, TIM_EGR_UG); 266 return len; 267 } 268 } 269 270 return -EINVAL; 271 } 272 273 static ssize_t stm32_tt_show_master_mode_avail(struct device *dev, 274 struct device_attribute *attr, 275 char *buf) 276 { 277 struct iio_trigger *trig = to_iio_trigger(dev); 278 unsigned int i, master_mode_max; 279 size_t len = 0; 280 281 if (stm32_timer_is_trgo2_name(trig->name)) 282 master_mode_max = MASTER_MODE2_MAX; 283 else 284 master_mode_max = MASTER_MODE_MAX; 285 286 for (i = 0; i <= master_mode_max; i++) 287 len += scnprintf(buf + len, PAGE_SIZE - len, 288 "%s ", master_mode_table[i]); 289 290 /* replace trailing space by newline */ 291 buf[len - 1] = '\n'; 292 293 return len; 294 } 295 296 static IIO_DEVICE_ATTR(master_mode_available, 0444, 297 stm32_tt_show_master_mode_avail, NULL, 0); 298 299 static IIO_DEVICE_ATTR(master_mode, 0660, 300 stm32_tt_show_master_mode, 301 stm32_tt_store_master_mode, 302 0); 303 304 static struct attribute *stm32_trigger_attrs[] = { 305 &iio_dev_attr_sampling_frequency.dev_attr.attr, 306 &iio_dev_attr_master_mode.dev_attr.attr, 307 &iio_dev_attr_master_mode_available.dev_attr.attr, 308 NULL, 309 }; 310 311 static const struct attribute_group stm32_trigger_attr_group = { 312 .attrs = stm32_trigger_attrs, 313 }; 314 315 static const struct attribute_group *stm32_trigger_attr_groups[] = { 316 &stm32_trigger_attr_group, 317 NULL, 318 }; 319 320 static const struct iio_trigger_ops timer_trigger_ops = { 321 .owner = THIS_MODULE, 322 }; 323 324 static int stm32_setup_iio_triggers(struct stm32_timer_trigger *priv) 325 { 326 int ret; 327 const char * const *cur = priv->triggers; 328 329 while (cur && *cur) { 330 struct iio_trigger *trig; 331 bool cur_is_trgo2 = stm32_timer_is_trgo2_name(*cur); 332 333 if (cur_is_trgo2 && !priv->has_trgo2) { 334 cur++; 335 continue; 336 } 337 338 trig = devm_iio_trigger_alloc(priv->dev, "%s", *cur); 339 if (!trig) 340 return -ENOMEM; 341 342 trig->dev.parent = priv->dev->parent; 343 trig->ops = &timer_trigger_ops; 344 345 /* 346 * sampling frequency and master mode attributes 347 * should only be available on trgo trigger which 348 * is always the first in the list. 349 */ 350 if (cur == priv->triggers || cur_is_trgo2) 351 trig->dev.groups = stm32_trigger_attr_groups; 352 353 iio_trigger_set_drvdata(trig, priv); 354 355 ret = devm_iio_trigger_register(priv->dev, trig); 356 if (ret) 357 return ret; 358 cur++; 359 } 360 361 return 0; 362 } 363 364 static int stm32_counter_read_raw(struct iio_dev *indio_dev, 365 struct iio_chan_spec const *chan, 366 int *val, int *val2, long mask) 367 { 368 struct stm32_timer_trigger *priv = iio_priv(indio_dev); 369 u32 dat; 370 371 switch (mask) { 372 case IIO_CHAN_INFO_RAW: 373 regmap_read(priv->regmap, TIM_CNT, &dat); 374 *val = dat; 375 return IIO_VAL_INT; 376 377 case IIO_CHAN_INFO_ENABLE: 378 regmap_read(priv->regmap, TIM_CR1, &dat); 379 *val = (dat & TIM_CR1_CEN) ? 1 : 0; 380 return IIO_VAL_INT; 381 382 case IIO_CHAN_INFO_SCALE: 383 regmap_read(priv->regmap, TIM_SMCR, &dat); 384 dat &= TIM_SMCR_SMS; 385 386 *val = 1; 387 *val2 = 0; 388 389 /* in quadrature case scale = 0.25 */ 390 if (dat == 3) 391 *val2 = 2; 392 393 return IIO_VAL_FRACTIONAL_LOG2; 394 } 395 396 return -EINVAL; 397 } 398 399 static int stm32_counter_write_raw(struct iio_dev *indio_dev, 400 struct iio_chan_spec const *chan, 401 int val, int val2, long mask) 402 { 403 struct stm32_timer_trigger *priv = iio_priv(indio_dev); 404 u32 dat; 405 406 switch (mask) { 407 case IIO_CHAN_INFO_RAW: 408 return regmap_write(priv->regmap, TIM_CNT, val); 409 410 case IIO_CHAN_INFO_SCALE: 411 /* fixed scale */ 412 return -EINVAL; 413 414 case IIO_CHAN_INFO_ENABLE: 415 if (val) { 416 regmap_read(priv->regmap, TIM_CR1, &dat); 417 if (!(dat & TIM_CR1_CEN)) 418 clk_enable(priv->clk); 419 regmap_update_bits(priv->regmap, TIM_CR1, TIM_CR1_CEN, 420 TIM_CR1_CEN); 421 } else { 422 regmap_read(priv->regmap, TIM_CR1, &dat); 423 regmap_update_bits(priv->regmap, TIM_CR1, TIM_CR1_CEN, 424 0); 425 if (dat & TIM_CR1_CEN) 426 clk_disable(priv->clk); 427 } 428 return 0; 429 } 430 431 return -EINVAL; 432 } 433 434 static int stm32_counter_validate_trigger(struct iio_dev *indio_dev, 435 struct iio_trigger *trig) 436 { 437 struct stm32_timer_trigger *priv = iio_priv(indio_dev); 438 const char * const *cur = priv->valids; 439 unsigned int i = 0; 440 441 if (!is_stm32_timer_trigger(trig)) 442 return -EINVAL; 443 444 while (cur && *cur) { 445 if (!strncmp(trig->name, *cur, strlen(trig->name))) { 446 regmap_update_bits(priv->regmap, 447 TIM_SMCR, TIM_SMCR_TS, 448 i << TIM_SMCR_TS_SHIFT); 449 return 0; 450 } 451 cur++; 452 i++; 453 } 454 455 return -EINVAL; 456 } 457 458 static const struct iio_info stm32_trigger_info = { 459 .driver_module = THIS_MODULE, 460 .validate_trigger = stm32_counter_validate_trigger, 461 .read_raw = stm32_counter_read_raw, 462 .write_raw = stm32_counter_write_raw 463 }; 464 465 static const char *const stm32_trigger_modes[] = { 466 "trigger", 467 }; 468 469 static int stm32_set_trigger_mode(struct iio_dev *indio_dev, 470 const struct iio_chan_spec *chan, 471 unsigned int mode) 472 { 473 struct stm32_timer_trigger *priv = iio_priv(indio_dev); 474 475 regmap_update_bits(priv->regmap, TIM_SMCR, TIM_SMCR_SMS, TIM_SMCR_SMS); 476 477 return 0; 478 } 479 480 static int stm32_get_trigger_mode(struct iio_dev *indio_dev, 481 const struct iio_chan_spec *chan) 482 { 483 struct stm32_timer_trigger *priv = iio_priv(indio_dev); 484 u32 smcr; 485 486 regmap_read(priv->regmap, TIM_SMCR, &smcr); 487 488 return (smcr & TIM_SMCR_SMS) == TIM_SMCR_SMS ? 0 : -EINVAL; 489 } 490 491 static const struct iio_enum stm32_trigger_mode_enum = { 492 .items = stm32_trigger_modes, 493 .num_items = ARRAY_SIZE(stm32_trigger_modes), 494 .set = stm32_set_trigger_mode, 495 .get = stm32_get_trigger_mode 496 }; 497 498 static const char *const stm32_enable_modes[] = { 499 "always", 500 "gated", 501 "triggered", 502 }; 503 504 static int stm32_enable_mode2sms(int mode) 505 { 506 switch (mode) { 507 case 0: 508 return 0; 509 case 1: 510 return 5; 511 case 2: 512 return 6; 513 } 514 515 return -EINVAL; 516 } 517 518 static int stm32_set_enable_mode(struct iio_dev *indio_dev, 519 const struct iio_chan_spec *chan, 520 unsigned int mode) 521 { 522 struct stm32_timer_trigger *priv = iio_priv(indio_dev); 523 int sms = stm32_enable_mode2sms(mode); 524 u32 val; 525 526 if (sms < 0) 527 return sms; 528 /* 529 * Triggered mode sets CEN bit automatically by hardware. So, first 530 * enable counter clock, so it can use it. Keeps it in sync with CEN. 531 */ 532 if (sms == 6) { 533 regmap_read(priv->regmap, TIM_CR1, &val); 534 if (!(val & TIM_CR1_CEN)) 535 clk_enable(priv->clk); 536 } 537 538 regmap_update_bits(priv->regmap, TIM_SMCR, TIM_SMCR_SMS, sms); 539 540 return 0; 541 } 542 543 static int stm32_sms2enable_mode(int mode) 544 { 545 switch (mode) { 546 case 0: 547 return 0; 548 case 5: 549 return 1; 550 case 6: 551 return 2; 552 } 553 554 return -EINVAL; 555 } 556 557 static int stm32_get_enable_mode(struct iio_dev *indio_dev, 558 const struct iio_chan_spec *chan) 559 { 560 struct stm32_timer_trigger *priv = iio_priv(indio_dev); 561 u32 smcr; 562 563 regmap_read(priv->regmap, TIM_SMCR, &smcr); 564 smcr &= TIM_SMCR_SMS; 565 566 return stm32_sms2enable_mode(smcr); 567 } 568 569 static const struct iio_enum stm32_enable_mode_enum = { 570 .items = stm32_enable_modes, 571 .num_items = ARRAY_SIZE(stm32_enable_modes), 572 .set = stm32_set_enable_mode, 573 .get = stm32_get_enable_mode 574 }; 575 576 static const char *const stm32_quadrature_modes[] = { 577 "channel_A", 578 "channel_B", 579 "quadrature", 580 }; 581 582 static int stm32_set_quadrature_mode(struct iio_dev *indio_dev, 583 const struct iio_chan_spec *chan, 584 unsigned int mode) 585 { 586 struct stm32_timer_trigger *priv = iio_priv(indio_dev); 587 588 regmap_update_bits(priv->regmap, TIM_SMCR, TIM_SMCR_SMS, mode + 1); 589 590 return 0; 591 } 592 593 static int stm32_get_quadrature_mode(struct iio_dev *indio_dev, 594 const struct iio_chan_spec *chan) 595 { 596 struct stm32_timer_trigger *priv = iio_priv(indio_dev); 597 u32 smcr; 598 int mode; 599 600 regmap_read(priv->regmap, TIM_SMCR, &smcr); 601 mode = (smcr & TIM_SMCR_SMS) - 1; 602 if ((mode < 0) || (mode > ARRAY_SIZE(stm32_quadrature_modes))) 603 return -EINVAL; 604 605 return mode; 606 } 607 608 static const struct iio_enum stm32_quadrature_mode_enum = { 609 .items = stm32_quadrature_modes, 610 .num_items = ARRAY_SIZE(stm32_quadrature_modes), 611 .set = stm32_set_quadrature_mode, 612 .get = stm32_get_quadrature_mode 613 }; 614 615 static const char *const stm32_count_direction_states[] = { 616 "up", 617 "down" 618 }; 619 620 static int stm32_set_count_direction(struct iio_dev *indio_dev, 621 const struct iio_chan_spec *chan, 622 unsigned int dir) 623 { 624 struct stm32_timer_trigger *priv = iio_priv(indio_dev); 625 u32 val; 626 int mode; 627 628 /* In encoder mode, direction is RO (given by TI1/TI2 signals) */ 629 regmap_read(priv->regmap, TIM_SMCR, &val); 630 mode = (val & TIM_SMCR_SMS) - 1; 631 if ((mode >= 0) || (mode < ARRAY_SIZE(stm32_quadrature_modes))) 632 return -EBUSY; 633 634 return regmap_update_bits(priv->regmap, TIM_CR1, TIM_CR1_DIR, 635 dir ? TIM_CR1_DIR : 0); 636 } 637 638 static int stm32_get_count_direction(struct iio_dev *indio_dev, 639 const struct iio_chan_spec *chan) 640 { 641 struct stm32_timer_trigger *priv = iio_priv(indio_dev); 642 u32 cr1; 643 644 regmap_read(priv->regmap, TIM_CR1, &cr1); 645 646 return ((cr1 & TIM_CR1_DIR) ? 1 : 0); 647 } 648 649 static const struct iio_enum stm32_count_direction_enum = { 650 .items = stm32_count_direction_states, 651 .num_items = ARRAY_SIZE(stm32_count_direction_states), 652 .set = stm32_set_count_direction, 653 .get = stm32_get_count_direction 654 }; 655 656 static ssize_t stm32_count_get_preset(struct iio_dev *indio_dev, 657 uintptr_t private, 658 const struct iio_chan_spec *chan, 659 char *buf) 660 { 661 struct stm32_timer_trigger *priv = iio_priv(indio_dev); 662 u32 arr; 663 664 regmap_read(priv->regmap, TIM_ARR, &arr); 665 666 return snprintf(buf, PAGE_SIZE, "%u\n", arr); 667 } 668 669 static ssize_t stm32_count_set_preset(struct iio_dev *indio_dev, 670 uintptr_t private, 671 const struct iio_chan_spec *chan, 672 const char *buf, size_t len) 673 { 674 struct stm32_timer_trigger *priv = iio_priv(indio_dev); 675 unsigned int preset; 676 int ret; 677 678 ret = kstrtouint(buf, 0, &preset); 679 if (ret) 680 return ret; 681 682 regmap_write(priv->regmap, TIM_ARR, preset); 683 regmap_update_bits(priv->regmap, TIM_CR1, TIM_CR1_ARPE, TIM_CR1_ARPE); 684 685 return len; 686 } 687 688 static const struct iio_chan_spec_ext_info stm32_trigger_count_info[] = { 689 { 690 .name = "preset", 691 .shared = IIO_SEPARATE, 692 .read = stm32_count_get_preset, 693 .write = stm32_count_set_preset 694 }, 695 IIO_ENUM("count_direction", IIO_SEPARATE, &stm32_count_direction_enum), 696 IIO_ENUM_AVAILABLE("count_direction", &stm32_count_direction_enum), 697 IIO_ENUM("quadrature_mode", IIO_SEPARATE, &stm32_quadrature_mode_enum), 698 IIO_ENUM_AVAILABLE("quadrature_mode", &stm32_quadrature_mode_enum), 699 IIO_ENUM("enable_mode", IIO_SEPARATE, &stm32_enable_mode_enum), 700 IIO_ENUM_AVAILABLE("enable_mode", &stm32_enable_mode_enum), 701 IIO_ENUM("trigger_mode", IIO_SEPARATE, &stm32_trigger_mode_enum), 702 IIO_ENUM_AVAILABLE("trigger_mode", &stm32_trigger_mode_enum), 703 {} 704 }; 705 706 static const struct iio_chan_spec stm32_trigger_channel = { 707 .type = IIO_COUNT, 708 .channel = 0, 709 .info_mask_separate = BIT(IIO_CHAN_INFO_RAW) | 710 BIT(IIO_CHAN_INFO_ENABLE) | 711 BIT(IIO_CHAN_INFO_SCALE), 712 .ext_info = stm32_trigger_count_info, 713 .indexed = 1 714 }; 715 716 static struct stm32_timer_trigger *stm32_setup_counter_device(struct device *dev) 717 { 718 struct iio_dev *indio_dev; 719 int ret; 720 721 indio_dev = devm_iio_device_alloc(dev, 722 sizeof(struct stm32_timer_trigger)); 723 if (!indio_dev) 724 return NULL; 725 726 indio_dev->name = dev_name(dev); 727 indio_dev->dev.parent = dev; 728 indio_dev->info = &stm32_trigger_info; 729 indio_dev->modes = INDIO_HARDWARE_TRIGGERED; 730 indio_dev->num_channels = 1; 731 indio_dev->channels = &stm32_trigger_channel; 732 indio_dev->dev.of_node = dev->of_node; 733 734 ret = devm_iio_device_register(dev, indio_dev); 735 if (ret) 736 return NULL; 737 738 return iio_priv(indio_dev); 739 } 740 741 /** 742 * is_stm32_timer_trigger 743 * @trig: trigger to be checked 744 * 745 * return true if the trigger is a valid stm32 iio timer trigger 746 * either return false 747 */ 748 bool is_stm32_timer_trigger(struct iio_trigger *trig) 749 { 750 return (trig->ops == &timer_trigger_ops); 751 } 752 EXPORT_SYMBOL(is_stm32_timer_trigger); 753 754 static void stm32_timer_detect_trgo2(struct stm32_timer_trigger *priv) 755 { 756 u32 val; 757 758 /* 759 * Master mode selection 2 bits can only be written and read back when 760 * timer supports it. 761 */ 762 regmap_update_bits(priv->regmap, TIM_CR2, TIM_CR2_MMS2, TIM_CR2_MMS2); 763 regmap_read(priv->regmap, TIM_CR2, &val); 764 regmap_update_bits(priv->regmap, TIM_CR2, TIM_CR2_MMS2, 0); 765 priv->has_trgo2 = !!val; 766 } 767 768 static int stm32_timer_trigger_probe(struct platform_device *pdev) 769 { 770 struct device *dev = &pdev->dev; 771 struct stm32_timer_trigger *priv; 772 struct stm32_timers *ddata = dev_get_drvdata(pdev->dev.parent); 773 unsigned int index; 774 int ret; 775 776 if (of_property_read_u32(dev->of_node, "reg", &index)) 777 return -EINVAL; 778 779 if (index >= ARRAY_SIZE(triggers_table) || 780 index >= ARRAY_SIZE(valids_table)) 781 return -EINVAL; 782 783 /* Create an IIO device only if we have triggers to be validated */ 784 if (*valids_table[index]) 785 priv = stm32_setup_counter_device(dev); 786 else 787 priv = devm_kzalloc(dev, sizeof(*priv), GFP_KERNEL); 788 789 if (!priv) 790 return -ENOMEM; 791 792 priv->dev = dev; 793 priv->regmap = ddata->regmap; 794 priv->clk = ddata->clk; 795 priv->max_arr = ddata->max_arr; 796 priv->triggers = triggers_table[index]; 797 priv->valids = valids_table[index]; 798 stm32_timer_detect_trgo2(priv); 799 800 ret = stm32_setup_iio_triggers(priv); 801 if (ret) 802 return ret; 803 804 platform_set_drvdata(pdev, priv); 805 806 return 0; 807 } 808 809 static const struct of_device_id stm32_trig_of_match[] = { 810 { .compatible = "st,stm32-timer-trigger", }, 811 { /* end node */ }, 812 }; 813 MODULE_DEVICE_TABLE(of, stm32_trig_of_match); 814 815 static struct platform_driver stm32_timer_trigger_driver = { 816 .probe = stm32_timer_trigger_probe, 817 .driver = { 818 .name = "stm32-timer-trigger", 819 .of_match_table = stm32_trig_of_match, 820 }, 821 }; 822 module_platform_driver(stm32_timer_trigger_driver); 823 824 MODULE_ALIAS("platform: stm32-timer-trigger"); 825 MODULE_DESCRIPTION("STMicroelectronics STM32 Timer Trigger driver"); 826 MODULE_LICENSE("GPL v2"); 827