1 /* 2 * Copyright (C) STMicroelectronics 2016 3 * 4 * Author: Benjamin Gaignard <benjamin.gaignard@st.com> 5 * 6 * License terms: GNU General Public License (GPL), version 2 7 */ 8 9 #include <linux/iio/iio.h> 10 #include <linux/iio/sysfs.h> 11 #include <linux/iio/timer/stm32-timer-trigger.h> 12 #include <linux/iio/trigger.h> 13 #include <linux/mfd/stm32-timers.h> 14 #include <linux/module.h> 15 #include <linux/platform_device.h> 16 #include <linux/of_device.h> 17 18 #define MAX_TRIGGERS 7 19 #define MAX_VALIDS 5 20 21 /* List the triggers created by each timer */ 22 static const void *triggers_table[][MAX_TRIGGERS] = { 23 { TIM1_TRGO, TIM1_TRGO2, TIM1_CH1, TIM1_CH2, TIM1_CH3, TIM1_CH4,}, 24 { TIM2_TRGO, TIM2_CH1, TIM2_CH2, TIM2_CH3, TIM2_CH4,}, 25 { TIM3_TRGO, TIM3_CH1, TIM3_CH2, TIM3_CH3, TIM3_CH4,}, 26 { TIM4_TRGO, TIM4_CH1, TIM4_CH2, TIM4_CH3, TIM4_CH4,}, 27 { TIM5_TRGO, TIM5_CH1, TIM5_CH2, TIM5_CH3, TIM5_CH4,}, 28 { TIM6_TRGO,}, 29 { TIM7_TRGO,}, 30 { TIM8_TRGO, TIM8_TRGO2, TIM8_CH1, TIM8_CH2, TIM8_CH3, TIM8_CH4,}, 31 { TIM9_TRGO, TIM9_CH1, TIM9_CH2,}, 32 { TIM10_OC1,}, 33 { TIM11_OC1,}, 34 { TIM12_TRGO, TIM12_CH1, TIM12_CH2,}, 35 { TIM13_OC1,}, 36 { TIM14_OC1,}, 37 { TIM15_TRGO,}, 38 { TIM16_OC1,}, 39 { TIM17_OC1,}, 40 }; 41 42 /* List the triggers accepted by each timer */ 43 static const void *valids_table[][MAX_VALIDS] = { 44 { TIM5_TRGO, TIM2_TRGO, TIM3_TRGO, TIM4_TRGO,}, 45 { TIM1_TRGO, TIM8_TRGO, TIM3_TRGO, TIM4_TRGO,}, 46 { TIM1_TRGO, TIM2_TRGO, TIM5_TRGO, TIM4_TRGO,}, 47 { TIM1_TRGO, TIM2_TRGO, TIM3_TRGO, TIM8_TRGO,}, 48 { TIM2_TRGO, TIM3_TRGO, TIM4_TRGO, TIM8_TRGO,}, 49 { }, /* timer 6 */ 50 { }, /* timer 7 */ 51 { TIM1_TRGO, TIM2_TRGO, TIM4_TRGO, TIM5_TRGO,}, 52 { TIM2_TRGO, TIM3_TRGO, TIM10_OC1, TIM11_OC1,}, 53 { }, /* timer 10 */ 54 { }, /* timer 11 */ 55 { TIM4_TRGO, TIM5_TRGO, TIM13_OC1, TIM14_OC1,}, 56 }; 57 58 static const void *stm32h7_valids_table[][MAX_VALIDS] = { 59 { TIM15_TRGO, TIM2_TRGO, TIM3_TRGO, TIM4_TRGO,}, 60 { TIM1_TRGO, TIM8_TRGO, TIM3_TRGO, TIM4_TRGO,}, 61 { TIM1_TRGO, TIM2_TRGO, TIM15_TRGO, TIM4_TRGO,}, 62 { TIM1_TRGO, TIM2_TRGO, TIM3_TRGO, TIM8_TRGO,}, 63 { TIM1_TRGO, TIM8_TRGO, TIM3_TRGO, TIM4_TRGO,}, 64 { }, /* timer 6 */ 65 { }, /* timer 7 */ 66 { TIM1_TRGO, TIM2_TRGO, TIM4_TRGO, TIM5_TRGO,}, 67 { }, /* timer 9 */ 68 { }, /* timer 10 */ 69 { }, /* timer 11 */ 70 { TIM4_TRGO, TIM5_TRGO, TIM13_OC1, TIM14_OC1,}, 71 { }, /* timer 13 */ 72 { }, /* timer 14 */ 73 { TIM1_TRGO, TIM3_TRGO, TIM16_OC1, TIM17_OC1,}, 74 { }, /* timer 16 */ 75 { }, /* timer 17 */ 76 }; 77 78 struct stm32_timer_trigger { 79 struct device *dev; 80 struct regmap *regmap; 81 struct clk *clk; 82 u32 max_arr; 83 const void *triggers; 84 const void *valids; 85 bool has_trgo2; 86 }; 87 88 struct stm32_timer_trigger_cfg { 89 const void *(*valids_table)[MAX_VALIDS]; 90 const unsigned int num_valids_table; 91 }; 92 93 static bool stm32_timer_is_trgo2_name(const char *name) 94 { 95 return !!strstr(name, "trgo2"); 96 } 97 98 static bool stm32_timer_is_trgo_name(const char *name) 99 { 100 return (!!strstr(name, "trgo") && !strstr(name, "trgo2")); 101 } 102 103 static int stm32_timer_start(struct stm32_timer_trigger *priv, 104 struct iio_trigger *trig, 105 unsigned int frequency) 106 { 107 unsigned long long prd, div; 108 int prescaler = 0; 109 u32 ccer, cr1; 110 111 /* Period and prescaler values depends of clock rate */ 112 div = (unsigned long long)clk_get_rate(priv->clk); 113 114 do_div(div, frequency); 115 116 prd = div; 117 118 /* 119 * Increase prescaler value until we get a result that fit 120 * with auto reload register maximum value. 121 */ 122 while (div > priv->max_arr) { 123 prescaler++; 124 div = prd; 125 do_div(div, (prescaler + 1)); 126 } 127 prd = div; 128 129 if (prescaler > MAX_TIM_PSC) { 130 dev_err(priv->dev, "prescaler exceeds the maximum value\n"); 131 return -EINVAL; 132 } 133 134 /* Check if nobody else use the timer */ 135 regmap_read(priv->regmap, TIM_CCER, &ccer); 136 if (ccer & TIM_CCER_CCXE) 137 return -EBUSY; 138 139 regmap_read(priv->regmap, TIM_CR1, &cr1); 140 if (!(cr1 & TIM_CR1_CEN)) 141 clk_enable(priv->clk); 142 143 regmap_write(priv->regmap, TIM_PSC, prescaler); 144 regmap_write(priv->regmap, TIM_ARR, prd - 1); 145 regmap_update_bits(priv->regmap, TIM_CR1, TIM_CR1_ARPE, TIM_CR1_ARPE); 146 147 /* Force master mode to update mode */ 148 if (stm32_timer_is_trgo2_name(trig->name)) 149 regmap_update_bits(priv->regmap, TIM_CR2, TIM_CR2_MMS2, 150 0x2 << TIM_CR2_MMS2_SHIFT); 151 else 152 regmap_update_bits(priv->regmap, TIM_CR2, TIM_CR2_MMS, 153 0x2 << TIM_CR2_MMS_SHIFT); 154 155 /* Make sure that registers are updated */ 156 regmap_update_bits(priv->regmap, TIM_EGR, TIM_EGR_UG, TIM_EGR_UG); 157 158 /* Enable controller */ 159 regmap_update_bits(priv->regmap, TIM_CR1, TIM_CR1_CEN, TIM_CR1_CEN); 160 161 return 0; 162 } 163 164 static void stm32_timer_stop(struct stm32_timer_trigger *priv) 165 { 166 u32 ccer, cr1; 167 168 regmap_read(priv->regmap, TIM_CCER, &ccer); 169 if (ccer & TIM_CCER_CCXE) 170 return; 171 172 regmap_read(priv->regmap, TIM_CR1, &cr1); 173 if (cr1 & TIM_CR1_CEN) 174 clk_disable(priv->clk); 175 176 /* Stop timer */ 177 regmap_update_bits(priv->regmap, TIM_CR1, TIM_CR1_ARPE, 0); 178 regmap_update_bits(priv->regmap, TIM_CR1, TIM_CR1_CEN, 0); 179 regmap_write(priv->regmap, TIM_PSC, 0); 180 regmap_write(priv->regmap, TIM_ARR, 0); 181 182 /* Make sure that registers are updated */ 183 regmap_update_bits(priv->regmap, TIM_EGR, TIM_EGR_UG, TIM_EGR_UG); 184 } 185 186 static ssize_t stm32_tt_store_frequency(struct device *dev, 187 struct device_attribute *attr, 188 const char *buf, size_t len) 189 { 190 struct iio_trigger *trig = to_iio_trigger(dev); 191 struct stm32_timer_trigger *priv = iio_trigger_get_drvdata(trig); 192 unsigned int freq; 193 int ret; 194 195 ret = kstrtouint(buf, 10, &freq); 196 if (ret) 197 return ret; 198 199 if (freq == 0) { 200 stm32_timer_stop(priv); 201 } else { 202 ret = stm32_timer_start(priv, trig, freq); 203 if (ret) 204 return ret; 205 } 206 207 return len; 208 } 209 210 static ssize_t stm32_tt_read_frequency(struct device *dev, 211 struct device_attribute *attr, char *buf) 212 { 213 struct iio_trigger *trig = to_iio_trigger(dev); 214 struct stm32_timer_trigger *priv = iio_trigger_get_drvdata(trig); 215 u32 psc, arr, cr1; 216 unsigned long long freq = 0; 217 218 regmap_read(priv->regmap, TIM_CR1, &cr1); 219 regmap_read(priv->regmap, TIM_PSC, &psc); 220 regmap_read(priv->regmap, TIM_ARR, &arr); 221 222 if (cr1 & TIM_CR1_CEN) { 223 freq = (unsigned long long)clk_get_rate(priv->clk); 224 do_div(freq, psc + 1); 225 do_div(freq, arr + 1); 226 } 227 228 return sprintf(buf, "%d\n", (unsigned int)freq); 229 } 230 231 static IIO_DEV_ATTR_SAMP_FREQ(0660, 232 stm32_tt_read_frequency, 233 stm32_tt_store_frequency); 234 235 #define MASTER_MODE_MAX 7 236 #define MASTER_MODE2_MAX 15 237 238 static char *master_mode_table[] = { 239 "reset", 240 "enable", 241 "update", 242 "compare_pulse", 243 "OC1REF", 244 "OC2REF", 245 "OC3REF", 246 "OC4REF", 247 /* Master mode selection 2 only */ 248 "OC5REF", 249 "OC6REF", 250 "compare_pulse_OC4REF", 251 "compare_pulse_OC6REF", 252 "compare_pulse_OC4REF_r_or_OC6REF_r", 253 "compare_pulse_OC4REF_r_or_OC6REF_f", 254 "compare_pulse_OC5REF_r_or_OC6REF_r", 255 "compare_pulse_OC5REF_r_or_OC6REF_f", 256 }; 257 258 static ssize_t stm32_tt_show_master_mode(struct device *dev, 259 struct device_attribute *attr, 260 char *buf) 261 { 262 struct stm32_timer_trigger *priv = dev_get_drvdata(dev); 263 struct iio_trigger *trig = to_iio_trigger(dev); 264 u32 cr2; 265 266 regmap_read(priv->regmap, TIM_CR2, &cr2); 267 268 if (stm32_timer_is_trgo2_name(trig->name)) 269 cr2 = (cr2 & TIM_CR2_MMS2) >> TIM_CR2_MMS2_SHIFT; 270 else 271 cr2 = (cr2 & TIM_CR2_MMS) >> TIM_CR2_MMS_SHIFT; 272 273 return snprintf(buf, PAGE_SIZE, "%s\n", master_mode_table[cr2]); 274 } 275 276 static ssize_t stm32_tt_store_master_mode(struct device *dev, 277 struct device_attribute *attr, 278 const char *buf, size_t len) 279 { 280 struct stm32_timer_trigger *priv = dev_get_drvdata(dev); 281 struct iio_trigger *trig = to_iio_trigger(dev); 282 u32 mask, shift, master_mode_max; 283 int i; 284 285 if (stm32_timer_is_trgo2_name(trig->name)) { 286 mask = TIM_CR2_MMS2; 287 shift = TIM_CR2_MMS2_SHIFT; 288 master_mode_max = MASTER_MODE2_MAX; 289 } else { 290 mask = TIM_CR2_MMS; 291 shift = TIM_CR2_MMS_SHIFT; 292 master_mode_max = MASTER_MODE_MAX; 293 } 294 295 for (i = 0; i <= master_mode_max; i++) { 296 if (!strncmp(master_mode_table[i], buf, 297 strlen(master_mode_table[i]))) { 298 regmap_update_bits(priv->regmap, TIM_CR2, mask, 299 i << shift); 300 /* Make sure that registers are updated */ 301 regmap_update_bits(priv->regmap, TIM_EGR, 302 TIM_EGR_UG, TIM_EGR_UG); 303 return len; 304 } 305 } 306 307 return -EINVAL; 308 } 309 310 static ssize_t stm32_tt_show_master_mode_avail(struct device *dev, 311 struct device_attribute *attr, 312 char *buf) 313 { 314 struct iio_trigger *trig = to_iio_trigger(dev); 315 unsigned int i, master_mode_max; 316 size_t len = 0; 317 318 if (stm32_timer_is_trgo2_name(trig->name)) 319 master_mode_max = MASTER_MODE2_MAX; 320 else 321 master_mode_max = MASTER_MODE_MAX; 322 323 for (i = 0; i <= master_mode_max; i++) 324 len += scnprintf(buf + len, PAGE_SIZE - len, 325 "%s ", master_mode_table[i]); 326 327 /* replace trailing space by newline */ 328 buf[len - 1] = '\n'; 329 330 return len; 331 } 332 333 static IIO_DEVICE_ATTR(master_mode_available, 0444, 334 stm32_tt_show_master_mode_avail, NULL, 0); 335 336 static IIO_DEVICE_ATTR(master_mode, 0660, 337 stm32_tt_show_master_mode, 338 stm32_tt_store_master_mode, 339 0); 340 341 static struct attribute *stm32_trigger_attrs[] = { 342 &iio_dev_attr_sampling_frequency.dev_attr.attr, 343 &iio_dev_attr_master_mode.dev_attr.attr, 344 &iio_dev_attr_master_mode_available.dev_attr.attr, 345 NULL, 346 }; 347 348 static const struct attribute_group stm32_trigger_attr_group = { 349 .attrs = stm32_trigger_attrs, 350 }; 351 352 static const struct attribute_group *stm32_trigger_attr_groups[] = { 353 &stm32_trigger_attr_group, 354 NULL, 355 }; 356 357 static const struct iio_trigger_ops timer_trigger_ops = { 358 .owner = THIS_MODULE, 359 }; 360 361 static int stm32_setup_iio_triggers(struct stm32_timer_trigger *priv) 362 { 363 int ret; 364 const char * const *cur = priv->triggers; 365 366 while (cur && *cur) { 367 struct iio_trigger *trig; 368 bool cur_is_trgo = stm32_timer_is_trgo_name(*cur); 369 bool cur_is_trgo2 = stm32_timer_is_trgo2_name(*cur); 370 371 if (cur_is_trgo2 && !priv->has_trgo2) { 372 cur++; 373 continue; 374 } 375 376 trig = devm_iio_trigger_alloc(priv->dev, "%s", *cur); 377 if (!trig) 378 return -ENOMEM; 379 380 trig->dev.parent = priv->dev->parent; 381 trig->ops = &timer_trigger_ops; 382 383 /* 384 * sampling frequency and master mode attributes 385 * should only be available on trgo/trgo2 triggers 386 */ 387 if (cur_is_trgo || cur_is_trgo2) 388 trig->dev.groups = stm32_trigger_attr_groups; 389 390 iio_trigger_set_drvdata(trig, priv); 391 392 ret = devm_iio_trigger_register(priv->dev, trig); 393 if (ret) 394 return ret; 395 cur++; 396 } 397 398 return 0; 399 } 400 401 static int stm32_counter_read_raw(struct iio_dev *indio_dev, 402 struct iio_chan_spec const *chan, 403 int *val, int *val2, long mask) 404 { 405 struct stm32_timer_trigger *priv = iio_priv(indio_dev); 406 u32 dat; 407 408 switch (mask) { 409 case IIO_CHAN_INFO_RAW: 410 regmap_read(priv->regmap, TIM_CNT, &dat); 411 *val = dat; 412 return IIO_VAL_INT; 413 414 case IIO_CHAN_INFO_ENABLE: 415 regmap_read(priv->regmap, TIM_CR1, &dat); 416 *val = (dat & TIM_CR1_CEN) ? 1 : 0; 417 return IIO_VAL_INT; 418 419 case IIO_CHAN_INFO_SCALE: 420 regmap_read(priv->regmap, TIM_SMCR, &dat); 421 dat &= TIM_SMCR_SMS; 422 423 *val = 1; 424 *val2 = 0; 425 426 /* in quadrature case scale = 0.25 */ 427 if (dat == 3) 428 *val2 = 2; 429 430 return IIO_VAL_FRACTIONAL_LOG2; 431 } 432 433 return -EINVAL; 434 } 435 436 static int stm32_counter_write_raw(struct iio_dev *indio_dev, 437 struct iio_chan_spec const *chan, 438 int val, int val2, long mask) 439 { 440 struct stm32_timer_trigger *priv = iio_priv(indio_dev); 441 u32 dat; 442 443 switch (mask) { 444 case IIO_CHAN_INFO_RAW: 445 return regmap_write(priv->regmap, TIM_CNT, val); 446 447 case IIO_CHAN_INFO_SCALE: 448 /* fixed scale */ 449 return -EINVAL; 450 451 case IIO_CHAN_INFO_ENABLE: 452 if (val) { 453 regmap_read(priv->regmap, TIM_CR1, &dat); 454 if (!(dat & TIM_CR1_CEN)) 455 clk_enable(priv->clk); 456 regmap_update_bits(priv->regmap, TIM_CR1, TIM_CR1_CEN, 457 TIM_CR1_CEN); 458 } else { 459 regmap_read(priv->regmap, TIM_CR1, &dat); 460 regmap_update_bits(priv->regmap, TIM_CR1, TIM_CR1_CEN, 461 0); 462 if (dat & TIM_CR1_CEN) 463 clk_disable(priv->clk); 464 } 465 return 0; 466 } 467 468 return -EINVAL; 469 } 470 471 static int stm32_counter_validate_trigger(struct iio_dev *indio_dev, 472 struct iio_trigger *trig) 473 { 474 struct stm32_timer_trigger *priv = iio_priv(indio_dev); 475 const char * const *cur = priv->valids; 476 unsigned int i = 0; 477 478 if (!is_stm32_timer_trigger(trig)) 479 return -EINVAL; 480 481 while (cur && *cur) { 482 if (!strncmp(trig->name, *cur, strlen(trig->name))) { 483 regmap_update_bits(priv->regmap, 484 TIM_SMCR, TIM_SMCR_TS, 485 i << TIM_SMCR_TS_SHIFT); 486 return 0; 487 } 488 cur++; 489 i++; 490 } 491 492 return -EINVAL; 493 } 494 495 static const struct iio_info stm32_trigger_info = { 496 .driver_module = THIS_MODULE, 497 .validate_trigger = stm32_counter_validate_trigger, 498 .read_raw = stm32_counter_read_raw, 499 .write_raw = stm32_counter_write_raw 500 }; 501 502 static const char *const stm32_trigger_modes[] = { 503 "trigger", 504 }; 505 506 static int stm32_set_trigger_mode(struct iio_dev *indio_dev, 507 const struct iio_chan_spec *chan, 508 unsigned int mode) 509 { 510 struct stm32_timer_trigger *priv = iio_priv(indio_dev); 511 512 regmap_update_bits(priv->regmap, TIM_SMCR, TIM_SMCR_SMS, TIM_SMCR_SMS); 513 514 return 0; 515 } 516 517 static int stm32_get_trigger_mode(struct iio_dev *indio_dev, 518 const struct iio_chan_spec *chan) 519 { 520 struct stm32_timer_trigger *priv = iio_priv(indio_dev); 521 u32 smcr; 522 523 regmap_read(priv->regmap, TIM_SMCR, &smcr); 524 525 return (smcr & TIM_SMCR_SMS) == TIM_SMCR_SMS ? 0 : -EINVAL; 526 } 527 528 static const struct iio_enum stm32_trigger_mode_enum = { 529 .items = stm32_trigger_modes, 530 .num_items = ARRAY_SIZE(stm32_trigger_modes), 531 .set = stm32_set_trigger_mode, 532 .get = stm32_get_trigger_mode 533 }; 534 535 static const char *const stm32_enable_modes[] = { 536 "always", 537 "gated", 538 "triggered", 539 }; 540 541 static int stm32_enable_mode2sms(int mode) 542 { 543 switch (mode) { 544 case 0: 545 return 0; 546 case 1: 547 return 5; 548 case 2: 549 return 6; 550 } 551 552 return -EINVAL; 553 } 554 555 static int stm32_set_enable_mode(struct iio_dev *indio_dev, 556 const struct iio_chan_spec *chan, 557 unsigned int mode) 558 { 559 struct stm32_timer_trigger *priv = iio_priv(indio_dev); 560 int sms = stm32_enable_mode2sms(mode); 561 u32 val; 562 563 if (sms < 0) 564 return sms; 565 /* 566 * Triggered mode sets CEN bit automatically by hardware. So, first 567 * enable counter clock, so it can use it. Keeps it in sync with CEN. 568 */ 569 if (sms == 6) { 570 regmap_read(priv->regmap, TIM_CR1, &val); 571 if (!(val & TIM_CR1_CEN)) 572 clk_enable(priv->clk); 573 } 574 575 regmap_update_bits(priv->regmap, TIM_SMCR, TIM_SMCR_SMS, sms); 576 577 return 0; 578 } 579 580 static int stm32_sms2enable_mode(int mode) 581 { 582 switch (mode) { 583 case 0: 584 return 0; 585 case 5: 586 return 1; 587 case 6: 588 return 2; 589 } 590 591 return -EINVAL; 592 } 593 594 static int stm32_get_enable_mode(struct iio_dev *indio_dev, 595 const struct iio_chan_spec *chan) 596 { 597 struct stm32_timer_trigger *priv = iio_priv(indio_dev); 598 u32 smcr; 599 600 regmap_read(priv->regmap, TIM_SMCR, &smcr); 601 smcr &= TIM_SMCR_SMS; 602 603 return stm32_sms2enable_mode(smcr); 604 } 605 606 static const struct iio_enum stm32_enable_mode_enum = { 607 .items = stm32_enable_modes, 608 .num_items = ARRAY_SIZE(stm32_enable_modes), 609 .set = stm32_set_enable_mode, 610 .get = stm32_get_enable_mode 611 }; 612 613 static const char *const stm32_quadrature_modes[] = { 614 "channel_A", 615 "channel_B", 616 "quadrature", 617 }; 618 619 static int stm32_set_quadrature_mode(struct iio_dev *indio_dev, 620 const struct iio_chan_spec *chan, 621 unsigned int mode) 622 { 623 struct stm32_timer_trigger *priv = iio_priv(indio_dev); 624 625 regmap_update_bits(priv->regmap, TIM_SMCR, TIM_SMCR_SMS, mode + 1); 626 627 return 0; 628 } 629 630 static int stm32_get_quadrature_mode(struct iio_dev *indio_dev, 631 const struct iio_chan_spec *chan) 632 { 633 struct stm32_timer_trigger *priv = iio_priv(indio_dev); 634 u32 smcr; 635 int mode; 636 637 regmap_read(priv->regmap, TIM_SMCR, &smcr); 638 mode = (smcr & TIM_SMCR_SMS) - 1; 639 if ((mode < 0) || (mode > ARRAY_SIZE(stm32_quadrature_modes))) 640 return -EINVAL; 641 642 return mode; 643 } 644 645 static const struct iio_enum stm32_quadrature_mode_enum = { 646 .items = stm32_quadrature_modes, 647 .num_items = ARRAY_SIZE(stm32_quadrature_modes), 648 .set = stm32_set_quadrature_mode, 649 .get = stm32_get_quadrature_mode 650 }; 651 652 static const char *const stm32_count_direction_states[] = { 653 "up", 654 "down" 655 }; 656 657 static int stm32_set_count_direction(struct iio_dev *indio_dev, 658 const struct iio_chan_spec *chan, 659 unsigned int dir) 660 { 661 struct stm32_timer_trigger *priv = iio_priv(indio_dev); 662 u32 val; 663 int mode; 664 665 /* In encoder mode, direction is RO (given by TI1/TI2 signals) */ 666 regmap_read(priv->regmap, TIM_SMCR, &val); 667 mode = (val & TIM_SMCR_SMS) - 1; 668 if ((mode >= 0) || (mode < ARRAY_SIZE(stm32_quadrature_modes))) 669 return -EBUSY; 670 671 return regmap_update_bits(priv->regmap, TIM_CR1, TIM_CR1_DIR, 672 dir ? TIM_CR1_DIR : 0); 673 } 674 675 static int stm32_get_count_direction(struct iio_dev *indio_dev, 676 const struct iio_chan_spec *chan) 677 { 678 struct stm32_timer_trigger *priv = iio_priv(indio_dev); 679 u32 cr1; 680 681 regmap_read(priv->regmap, TIM_CR1, &cr1); 682 683 return ((cr1 & TIM_CR1_DIR) ? 1 : 0); 684 } 685 686 static const struct iio_enum stm32_count_direction_enum = { 687 .items = stm32_count_direction_states, 688 .num_items = ARRAY_SIZE(stm32_count_direction_states), 689 .set = stm32_set_count_direction, 690 .get = stm32_get_count_direction 691 }; 692 693 static ssize_t stm32_count_get_preset(struct iio_dev *indio_dev, 694 uintptr_t private, 695 const struct iio_chan_spec *chan, 696 char *buf) 697 { 698 struct stm32_timer_trigger *priv = iio_priv(indio_dev); 699 u32 arr; 700 701 regmap_read(priv->regmap, TIM_ARR, &arr); 702 703 return snprintf(buf, PAGE_SIZE, "%u\n", arr); 704 } 705 706 static ssize_t stm32_count_set_preset(struct iio_dev *indio_dev, 707 uintptr_t private, 708 const struct iio_chan_spec *chan, 709 const char *buf, size_t len) 710 { 711 struct stm32_timer_trigger *priv = iio_priv(indio_dev); 712 unsigned int preset; 713 int ret; 714 715 ret = kstrtouint(buf, 0, &preset); 716 if (ret) 717 return ret; 718 719 /* TIMx_ARR register shouldn't be buffered (ARPE=0) */ 720 regmap_update_bits(priv->regmap, TIM_CR1, TIM_CR1_ARPE, 0); 721 regmap_write(priv->regmap, TIM_ARR, preset); 722 723 return len; 724 } 725 726 static const struct iio_chan_spec_ext_info stm32_trigger_count_info[] = { 727 { 728 .name = "preset", 729 .shared = IIO_SEPARATE, 730 .read = stm32_count_get_preset, 731 .write = stm32_count_set_preset 732 }, 733 IIO_ENUM("count_direction", IIO_SEPARATE, &stm32_count_direction_enum), 734 IIO_ENUM_AVAILABLE("count_direction", &stm32_count_direction_enum), 735 IIO_ENUM("quadrature_mode", IIO_SEPARATE, &stm32_quadrature_mode_enum), 736 IIO_ENUM_AVAILABLE("quadrature_mode", &stm32_quadrature_mode_enum), 737 IIO_ENUM("enable_mode", IIO_SEPARATE, &stm32_enable_mode_enum), 738 IIO_ENUM_AVAILABLE("enable_mode", &stm32_enable_mode_enum), 739 IIO_ENUM("trigger_mode", IIO_SEPARATE, &stm32_trigger_mode_enum), 740 IIO_ENUM_AVAILABLE("trigger_mode", &stm32_trigger_mode_enum), 741 {} 742 }; 743 744 static const struct iio_chan_spec stm32_trigger_channel = { 745 .type = IIO_COUNT, 746 .channel = 0, 747 .info_mask_separate = BIT(IIO_CHAN_INFO_RAW) | 748 BIT(IIO_CHAN_INFO_ENABLE) | 749 BIT(IIO_CHAN_INFO_SCALE), 750 .ext_info = stm32_trigger_count_info, 751 .indexed = 1 752 }; 753 754 static struct stm32_timer_trigger *stm32_setup_counter_device(struct device *dev) 755 { 756 struct iio_dev *indio_dev; 757 int ret; 758 759 indio_dev = devm_iio_device_alloc(dev, 760 sizeof(struct stm32_timer_trigger)); 761 if (!indio_dev) 762 return NULL; 763 764 indio_dev->name = dev_name(dev); 765 indio_dev->dev.parent = dev; 766 indio_dev->info = &stm32_trigger_info; 767 indio_dev->modes = INDIO_HARDWARE_TRIGGERED; 768 indio_dev->num_channels = 1; 769 indio_dev->channels = &stm32_trigger_channel; 770 indio_dev->dev.of_node = dev->of_node; 771 772 ret = devm_iio_device_register(dev, indio_dev); 773 if (ret) 774 return NULL; 775 776 return iio_priv(indio_dev); 777 } 778 779 /** 780 * is_stm32_timer_trigger 781 * @trig: trigger to be checked 782 * 783 * return true if the trigger is a valid stm32 iio timer trigger 784 * either return false 785 */ 786 bool is_stm32_timer_trigger(struct iio_trigger *trig) 787 { 788 return (trig->ops == &timer_trigger_ops); 789 } 790 EXPORT_SYMBOL(is_stm32_timer_trigger); 791 792 static void stm32_timer_detect_trgo2(struct stm32_timer_trigger *priv) 793 { 794 u32 val; 795 796 /* 797 * Master mode selection 2 bits can only be written and read back when 798 * timer supports it. 799 */ 800 regmap_update_bits(priv->regmap, TIM_CR2, TIM_CR2_MMS2, TIM_CR2_MMS2); 801 regmap_read(priv->regmap, TIM_CR2, &val); 802 regmap_update_bits(priv->regmap, TIM_CR2, TIM_CR2_MMS2, 0); 803 priv->has_trgo2 = !!val; 804 } 805 806 static int stm32_timer_trigger_probe(struct platform_device *pdev) 807 { 808 struct device *dev = &pdev->dev; 809 struct stm32_timer_trigger *priv; 810 struct stm32_timers *ddata = dev_get_drvdata(pdev->dev.parent); 811 const struct stm32_timer_trigger_cfg *cfg; 812 unsigned int index; 813 int ret; 814 815 if (of_property_read_u32(dev->of_node, "reg", &index)) 816 return -EINVAL; 817 818 cfg = (const struct stm32_timer_trigger_cfg *) 819 of_match_device(dev->driver->of_match_table, dev)->data; 820 821 if (index >= ARRAY_SIZE(triggers_table) || 822 index >= cfg->num_valids_table) 823 return -EINVAL; 824 825 /* Create an IIO device only if we have triggers to be validated */ 826 if (*cfg->valids_table[index]) 827 priv = stm32_setup_counter_device(dev); 828 else 829 priv = devm_kzalloc(dev, sizeof(*priv), GFP_KERNEL); 830 831 if (!priv) 832 return -ENOMEM; 833 834 priv->dev = dev; 835 priv->regmap = ddata->regmap; 836 priv->clk = ddata->clk; 837 priv->max_arr = ddata->max_arr; 838 priv->triggers = triggers_table[index]; 839 priv->valids = cfg->valids_table[index]; 840 stm32_timer_detect_trgo2(priv); 841 842 ret = stm32_setup_iio_triggers(priv); 843 if (ret) 844 return ret; 845 846 platform_set_drvdata(pdev, priv); 847 848 return 0; 849 } 850 851 static const struct stm32_timer_trigger_cfg stm32_timer_trg_cfg = { 852 .valids_table = valids_table, 853 .num_valids_table = ARRAY_SIZE(valids_table), 854 }; 855 856 static const struct stm32_timer_trigger_cfg stm32h7_timer_trg_cfg = { 857 .valids_table = stm32h7_valids_table, 858 .num_valids_table = ARRAY_SIZE(stm32h7_valids_table), 859 }; 860 861 static const struct of_device_id stm32_trig_of_match[] = { 862 { 863 .compatible = "st,stm32-timer-trigger", 864 .data = (void *)&stm32_timer_trg_cfg, 865 }, { 866 .compatible = "st,stm32h7-timer-trigger", 867 .data = (void *)&stm32h7_timer_trg_cfg, 868 }, 869 { /* end node */ }, 870 }; 871 MODULE_DEVICE_TABLE(of, stm32_trig_of_match); 872 873 static struct platform_driver stm32_timer_trigger_driver = { 874 .probe = stm32_timer_trigger_probe, 875 .driver = { 876 .name = "stm32-timer-trigger", 877 .of_match_table = stm32_trig_of_match, 878 }, 879 }; 880 module_platform_driver(stm32_timer_trigger_driver); 881 882 MODULE_ALIAS("platform: stm32-timer-trigger"); 883 MODULE_DESCRIPTION("STMicroelectronics STM32 Timer Trigger driver"); 884 MODULE_LICENSE("GPL v2"); 885