1 /* 2 * Copyright (C) STMicroelectronics 2016 3 * 4 * Author: Benjamin Gaignard <benjamin.gaignard@st.com> 5 * 6 * License terms: GNU General Public License (GPL), version 2 7 */ 8 9 #include <linux/iio/iio.h> 10 #include <linux/iio/sysfs.h> 11 #include <linux/iio/timer/stm32-timer-trigger.h> 12 #include <linux/iio/trigger.h> 13 #include <linux/mfd/stm32-timers.h> 14 #include <linux/module.h> 15 #include <linux/platform_device.h> 16 17 #define MAX_TRIGGERS 6 18 #define MAX_VALIDS 5 19 20 /* List the triggers created by each timer */ 21 static const void *triggers_table[][MAX_TRIGGERS] = { 22 { TIM1_TRGO, TIM1_CH1, TIM1_CH2, TIM1_CH3, TIM1_CH4,}, 23 { TIM2_TRGO, TIM2_CH1, TIM2_CH2, TIM2_CH3, TIM2_CH4,}, 24 { TIM3_TRGO, TIM3_CH1, TIM3_CH2, TIM3_CH3, TIM3_CH4,}, 25 { TIM4_TRGO, TIM4_CH1, TIM4_CH2, TIM4_CH3, TIM4_CH4,}, 26 { TIM5_TRGO, TIM5_CH1, TIM5_CH2, TIM5_CH3, TIM5_CH4,}, 27 { TIM6_TRGO,}, 28 { TIM7_TRGO,}, 29 { TIM8_TRGO, TIM8_CH1, TIM8_CH2, TIM8_CH3, TIM8_CH4,}, 30 { TIM9_TRGO, TIM9_CH1, TIM9_CH2,}, 31 { }, /* timer 10 */ 32 { }, /* timer 11 */ 33 { TIM12_TRGO, TIM12_CH1, TIM12_CH2,}, 34 }; 35 36 /* List the triggers accepted by each timer */ 37 static const void *valids_table[][MAX_VALIDS] = { 38 { TIM5_TRGO, TIM2_TRGO, TIM3_TRGO, TIM4_TRGO,}, 39 { TIM1_TRGO, TIM8_TRGO, TIM3_TRGO, TIM4_TRGO,}, 40 { TIM1_TRGO, TIM2_TRGO, TIM5_TRGO, TIM4_TRGO,}, 41 { TIM1_TRGO, TIM2_TRGO, TIM3_TRGO, TIM8_TRGO,}, 42 { TIM2_TRGO, TIM3_TRGO, TIM4_TRGO, TIM8_TRGO,}, 43 { }, /* timer 6 */ 44 { }, /* timer 7 */ 45 { TIM1_TRGO, TIM2_TRGO, TIM4_TRGO, TIM5_TRGO,}, 46 { TIM2_TRGO, TIM3_TRGO,}, 47 { }, /* timer 10 */ 48 { }, /* timer 11 */ 49 { TIM4_TRGO, TIM5_TRGO,}, 50 }; 51 52 struct stm32_timer_trigger { 53 struct device *dev; 54 struct regmap *regmap; 55 struct clk *clk; 56 u32 max_arr; 57 const void *triggers; 58 const void *valids; 59 }; 60 61 static int stm32_timer_start(struct stm32_timer_trigger *priv, 62 unsigned int frequency) 63 { 64 unsigned long long prd, div; 65 int prescaler = 0; 66 u32 ccer, cr1; 67 68 /* Period and prescaler values depends of clock rate */ 69 div = (unsigned long long)clk_get_rate(priv->clk); 70 71 do_div(div, frequency); 72 73 prd = div; 74 75 /* 76 * Increase prescaler value until we get a result that fit 77 * with auto reload register maximum value. 78 */ 79 while (div > priv->max_arr) { 80 prescaler++; 81 div = prd; 82 do_div(div, (prescaler + 1)); 83 } 84 prd = div; 85 86 if (prescaler > MAX_TIM_PSC) { 87 dev_err(priv->dev, "prescaler exceeds the maximum value\n"); 88 return -EINVAL; 89 } 90 91 /* Check if nobody else use the timer */ 92 regmap_read(priv->regmap, TIM_CCER, &ccer); 93 if (ccer & TIM_CCER_CCXE) 94 return -EBUSY; 95 96 regmap_read(priv->regmap, TIM_CR1, &cr1); 97 if (!(cr1 & TIM_CR1_CEN)) 98 clk_enable(priv->clk); 99 100 regmap_write(priv->regmap, TIM_PSC, prescaler); 101 regmap_write(priv->regmap, TIM_ARR, prd - 1); 102 regmap_update_bits(priv->regmap, TIM_CR1, TIM_CR1_ARPE, TIM_CR1_ARPE); 103 104 /* Force master mode to update mode */ 105 regmap_update_bits(priv->regmap, TIM_CR2, TIM_CR2_MMS, 0x20); 106 107 /* Make sure that registers are updated */ 108 regmap_update_bits(priv->regmap, TIM_EGR, TIM_EGR_UG, TIM_EGR_UG); 109 110 /* Enable controller */ 111 regmap_update_bits(priv->regmap, TIM_CR1, TIM_CR1_CEN, TIM_CR1_CEN); 112 113 return 0; 114 } 115 116 static void stm32_timer_stop(struct stm32_timer_trigger *priv) 117 { 118 u32 ccer, cr1; 119 120 regmap_read(priv->regmap, TIM_CCER, &ccer); 121 if (ccer & TIM_CCER_CCXE) 122 return; 123 124 regmap_read(priv->regmap, TIM_CR1, &cr1); 125 if (cr1 & TIM_CR1_CEN) 126 clk_disable(priv->clk); 127 128 /* Stop timer */ 129 regmap_update_bits(priv->regmap, TIM_CR1, TIM_CR1_CEN, 0); 130 regmap_write(priv->regmap, TIM_PSC, 0); 131 regmap_write(priv->regmap, TIM_ARR, 0); 132 133 /* Make sure that registers are updated */ 134 regmap_update_bits(priv->regmap, TIM_EGR, TIM_EGR_UG, TIM_EGR_UG); 135 } 136 137 static ssize_t stm32_tt_store_frequency(struct device *dev, 138 struct device_attribute *attr, 139 const char *buf, size_t len) 140 { 141 struct iio_trigger *trig = to_iio_trigger(dev); 142 struct stm32_timer_trigger *priv = iio_trigger_get_drvdata(trig); 143 unsigned int freq; 144 int ret; 145 146 ret = kstrtouint(buf, 10, &freq); 147 if (ret) 148 return ret; 149 150 if (freq == 0) { 151 stm32_timer_stop(priv); 152 } else { 153 ret = stm32_timer_start(priv, freq); 154 if (ret) 155 return ret; 156 } 157 158 return len; 159 } 160 161 static ssize_t stm32_tt_read_frequency(struct device *dev, 162 struct device_attribute *attr, char *buf) 163 { 164 struct iio_trigger *trig = to_iio_trigger(dev); 165 struct stm32_timer_trigger *priv = iio_trigger_get_drvdata(trig); 166 u32 psc, arr, cr1; 167 unsigned long long freq = 0; 168 169 regmap_read(priv->regmap, TIM_CR1, &cr1); 170 regmap_read(priv->regmap, TIM_PSC, &psc); 171 regmap_read(priv->regmap, TIM_ARR, &arr); 172 173 if (cr1 & TIM_CR1_CEN) { 174 freq = (unsigned long long)clk_get_rate(priv->clk); 175 do_div(freq, psc + 1); 176 do_div(freq, arr + 1); 177 } 178 179 return sprintf(buf, "%d\n", (unsigned int)freq); 180 } 181 182 static IIO_DEV_ATTR_SAMP_FREQ(0660, 183 stm32_tt_read_frequency, 184 stm32_tt_store_frequency); 185 186 static char *master_mode_table[] = { 187 "reset", 188 "enable", 189 "update", 190 "compare_pulse", 191 "OC1REF", 192 "OC2REF", 193 "OC3REF", 194 "OC4REF" 195 }; 196 197 static ssize_t stm32_tt_show_master_mode(struct device *dev, 198 struct device_attribute *attr, 199 char *buf) 200 { 201 struct stm32_timer_trigger *priv = dev_get_drvdata(dev); 202 u32 cr2; 203 204 regmap_read(priv->regmap, TIM_CR2, &cr2); 205 cr2 = (cr2 & TIM_CR2_MMS) >> TIM_CR2_MMS_SHIFT; 206 207 return snprintf(buf, PAGE_SIZE, "%s\n", master_mode_table[cr2]); 208 } 209 210 static ssize_t stm32_tt_store_master_mode(struct device *dev, 211 struct device_attribute *attr, 212 const char *buf, size_t len) 213 { 214 struct stm32_timer_trigger *priv = dev_get_drvdata(dev); 215 int i; 216 217 for (i = 0; i < ARRAY_SIZE(master_mode_table); i++) { 218 if (!strncmp(master_mode_table[i], buf, 219 strlen(master_mode_table[i]))) { 220 regmap_update_bits(priv->regmap, TIM_CR2, 221 TIM_CR2_MMS, i << TIM_CR2_MMS_SHIFT); 222 /* Make sure that registers are updated */ 223 regmap_update_bits(priv->regmap, TIM_EGR, 224 TIM_EGR_UG, TIM_EGR_UG); 225 return len; 226 } 227 } 228 229 return -EINVAL; 230 } 231 232 static IIO_CONST_ATTR(master_mode_available, 233 "reset enable update compare_pulse OC1REF OC2REF OC3REF OC4REF"); 234 235 static IIO_DEVICE_ATTR(master_mode, 0660, 236 stm32_tt_show_master_mode, 237 stm32_tt_store_master_mode, 238 0); 239 240 static struct attribute *stm32_trigger_attrs[] = { 241 &iio_dev_attr_sampling_frequency.dev_attr.attr, 242 &iio_dev_attr_master_mode.dev_attr.attr, 243 &iio_const_attr_master_mode_available.dev_attr.attr, 244 NULL, 245 }; 246 247 static const struct attribute_group stm32_trigger_attr_group = { 248 .attrs = stm32_trigger_attrs, 249 }; 250 251 static const struct attribute_group *stm32_trigger_attr_groups[] = { 252 &stm32_trigger_attr_group, 253 NULL, 254 }; 255 256 static const struct iio_trigger_ops timer_trigger_ops = { 257 .owner = THIS_MODULE, 258 }; 259 260 static int stm32_setup_iio_triggers(struct stm32_timer_trigger *priv) 261 { 262 int ret; 263 const char * const *cur = priv->triggers; 264 265 while (cur && *cur) { 266 struct iio_trigger *trig; 267 268 trig = devm_iio_trigger_alloc(priv->dev, "%s", *cur); 269 if (!trig) 270 return -ENOMEM; 271 272 trig->dev.parent = priv->dev->parent; 273 trig->ops = &timer_trigger_ops; 274 275 /* 276 * sampling frequency and master mode attributes 277 * should only be available on trgo trigger which 278 * is always the first in the list. 279 */ 280 if (cur == priv->triggers) 281 trig->dev.groups = stm32_trigger_attr_groups; 282 283 iio_trigger_set_drvdata(trig, priv); 284 285 ret = devm_iio_trigger_register(priv->dev, trig); 286 if (ret) 287 return ret; 288 cur++; 289 } 290 291 return 0; 292 } 293 294 static int stm32_counter_read_raw(struct iio_dev *indio_dev, 295 struct iio_chan_spec const *chan, 296 int *val, int *val2, long mask) 297 { 298 struct stm32_timer_trigger *priv = iio_priv(indio_dev); 299 300 switch (mask) { 301 case IIO_CHAN_INFO_RAW: 302 { 303 u32 cnt; 304 305 regmap_read(priv->regmap, TIM_CNT, &cnt); 306 *val = cnt; 307 308 return IIO_VAL_INT; 309 } 310 case IIO_CHAN_INFO_SCALE: 311 { 312 u32 smcr; 313 314 regmap_read(priv->regmap, TIM_SMCR, &smcr); 315 smcr &= TIM_SMCR_SMS; 316 317 *val = 1; 318 *val2 = 0; 319 320 /* in quadrature case scale = 0.25 */ 321 if (smcr == 3) 322 *val2 = 2; 323 324 return IIO_VAL_FRACTIONAL_LOG2; 325 } 326 } 327 328 return -EINVAL; 329 } 330 331 static int stm32_counter_write_raw(struct iio_dev *indio_dev, 332 struct iio_chan_spec const *chan, 333 int val, int val2, long mask) 334 { 335 struct stm32_timer_trigger *priv = iio_priv(indio_dev); 336 337 switch (mask) { 338 case IIO_CHAN_INFO_RAW: 339 regmap_write(priv->regmap, TIM_CNT, val); 340 341 return IIO_VAL_INT; 342 case IIO_CHAN_INFO_SCALE: 343 /* fixed scale */ 344 return -EINVAL; 345 } 346 347 return -EINVAL; 348 } 349 350 static const struct iio_info stm32_trigger_info = { 351 .driver_module = THIS_MODULE, 352 .read_raw = stm32_counter_read_raw, 353 .write_raw = stm32_counter_write_raw 354 }; 355 356 static const char *const stm32_enable_modes[] = { 357 "always", 358 "gated", 359 "triggered", 360 }; 361 362 static int stm32_enable_mode2sms(int mode) 363 { 364 switch (mode) { 365 case 0: 366 return 0; 367 case 1: 368 return 5; 369 case 2: 370 return 6; 371 } 372 373 return -EINVAL; 374 } 375 376 static int stm32_set_enable_mode(struct iio_dev *indio_dev, 377 const struct iio_chan_spec *chan, 378 unsigned int mode) 379 { 380 struct stm32_timer_trigger *priv = iio_priv(indio_dev); 381 int sms = stm32_enable_mode2sms(mode); 382 383 if (sms < 0) 384 return sms; 385 386 regmap_update_bits(priv->regmap, TIM_SMCR, TIM_SMCR_SMS, sms); 387 388 return 0; 389 } 390 391 static int stm32_sms2enable_mode(int mode) 392 { 393 switch (mode) { 394 case 0: 395 return 0; 396 case 5: 397 return 1; 398 case 6: 399 return 2; 400 } 401 402 return -EINVAL; 403 } 404 405 static int stm32_get_enable_mode(struct iio_dev *indio_dev, 406 const struct iio_chan_spec *chan) 407 { 408 struct stm32_timer_trigger *priv = iio_priv(indio_dev); 409 u32 smcr; 410 411 regmap_read(priv->regmap, TIM_SMCR, &smcr); 412 smcr &= TIM_SMCR_SMS; 413 414 return stm32_sms2enable_mode(smcr); 415 } 416 417 static const struct iio_enum stm32_enable_mode_enum = { 418 .items = stm32_enable_modes, 419 .num_items = ARRAY_SIZE(stm32_enable_modes), 420 .set = stm32_set_enable_mode, 421 .get = stm32_get_enable_mode 422 }; 423 424 static const char *const stm32_quadrature_modes[] = { 425 "channel_A", 426 "channel_B", 427 "quadrature", 428 }; 429 430 static int stm32_set_quadrature_mode(struct iio_dev *indio_dev, 431 const struct iio_chan_spec *chan, 432 unsigned int mode) 433 { 434 struct stm32_timer_trigger *priv = iio_priv(indio_dev); 435 436 regmap_update_bits(priv->regmap, TIM_SMCR, TIM_SMCR_SMS, mode + 1); 437 438 return 0; 439 } 440 441 static int stm32_get_quadrature_mode(struct iio_dev *indio_dev, 442 const struct iio_chan_spec *chan) 443 { 444 struct stm32_timer_trigger *priv = iio_priv(indio_dev); 445 u32 smcr; 446 447 regmap_read(priv->regmap, TIM_SMCR, &smcr); 448 smcr &= TIM_SMCR_SMS; 449 450 return smcr - 1; 451 } 452 453 static const struct iio_enum stm32_quadrature_mode_enum = { 454 .items = stm32_quadrature_modes, 455 .num_items = ARRAY_SIZE(stm32_quadrature_modes), 456 .set = stm32_set_quadrature_mode, 457 .get = stm32_get_quadrature_mode 458 }; 459 460 static const char *const stm32_count_direction_states[] = { 461 "up", 462 "down" 463 }; 464 465 static int stm32_set_count_direction(struct iio_dev *indio_dev, 466 const struct iio_chan_spec *chan, 467 unsigned int mode) 468 { 469 struct stm32_timer_trigger *priv = iio_priv(indio_dev); 470 471 regmap_update_bits(priv->regmap, TIM_CR1, TIM_CR1_DIR, mode); 472 473 return 0; 474 } 475 476 static int stm32_get_count_direction(struct iio_dev *indio_dev, 477 const struct iio_chan_spec *chan) 478 { 479 struct stm32_timer_trigger *priv = iio_priv(indio_dev); 480 u32 cr1; 481 482 regmap_read(priv->regmap, TIM_CR1, &cr1); 483 484 return (cr1 & TIM_CR1_DIR); 485 } 486 487 static const struct iio_enum stm32_count_direction_enum = { 488 .items = stm32_count_direction_states, 489 .num_items = ARRAY_SIZE(stm32_count_direction_states), 490 .set = stm32_set_count_direction, 491 .get = stm32_get_count_direction 492 }; 493 494 static ssize_t stm32_count_get_preset(struct iio_dev *indio_dev, 495 uintptr_t private, 496 const struct iio_chan_spec *chan, 497 char *buf) 498 { 499 struct stm32_timer_trigger *priv = iio_priv(indio_dev); 500 u32 arr; 501 502 regmap_read(priv->regmap, TIM_ARR, &arr); 503 504 return snprintf(buf, PAGE_SIZE, "%u\n", arr); 505 } 506 507 static ssize_t stm32_count_set_preset(struct iio_dev *indio_dev, 508 uintptr_t private, 509 const struct iio_chan_spec *chan, 510 const char *buf, size_t len) 511 { 512 struct stm32_timer_trigger *priv = iio_priv(indio_dev); 513 unsigned int preset; 514 int ret; 515 516 ret = kstrtouint(buf, 0, &preset); 517 if (ret) 518 return ret; 519 520 regmap_write(priv->regmap, TIM_ARR, preset); 521 regmap_update_bits(priv->regmap, TIM_CR1, TIM_CR1_ARPE, TIM_CR1_ARPE); 522 523 return len; 524 } 525 526 static const struct iio_chan_spec_ext_info stm32_trigger_count_info[] = { 527 { 528 .name = "preset", 529 .shared = IIO_SEPARATE, 530 .read = stm32_count_get_preset, 531 .write = stm32_count_set_preset 532 }, 533 IIO_ENUM("count_direction", IIO_SEPARATE, &stm32_count_direction_enum), 534 IIO_ENUM_AVAILABLE("count_direction", &stm32_count_direction_enum), 535 IIO_ENUM("quadrature_mode", IIO_SEPARATE, &stm32_quadrature_mode_enum), 536 IIO_ENUM_AVAILABLE("quadrature_mode", &stm32_quadrature_mode_enum), 537 IIO_ENUM("enable_mode", IIO_SEPARATE, &stm32_enable_mode_enum), 538 IIO_ENUM_AVAILABLE("enable_mode", &stm32_enable_mode_enum), 539 {} 540 }; 541 542 static const struct iio_chan_spec stm32_trigger_channel = { 543 .type = IIO_COUNT, 544 .channel = 0, 545 .info_mask_separate = BIT(IIO_CHAN_INFO_RAW) | BIT(IIO_CHAN_INFO_SCALE), 546 .ext_info = stm32_trigger_count_info, 547 .indexed = 1 548 }; 549 550 static struct stm32_timer_trigger *stm32_setup_counter_device(struct device *dev) 551 { 552 struct iio_dev *indio_dev; 553 int ret; 554 555 indio_dev = devm_iio_device_alloc(dev, 556 sizeof(struct stm32_timer_trigger)); 557 if (!indio_dev) 558 return NULL; 559 560 indio_dev->name = dev_name(dev); 561 indio_dev->dev.parent = dev; 562 indio_dev->info = &stm32_trigger_info; 563 indio_dev->num_channels = 1; 564 indio_dev->channels = &stm32_trigger_channel; 565 indio_dev->dev.of_node = dev->of_node; 566 567 ret = devm_iio_device_register(dev, indio_dev); 568 if (ret) 569 return NULL; 570 571 return iio_priv(indio_dev); 572 } 573 574 /** 575 * is_stm32_timer_trigger 576 * @trig: trigger to be checked 577 * 578 * return true if the trigger is a valid stm32 iio timer trigger 579 * either return false 580 */ 581 bool is_stm32_timer_trigger(struct iio_trigger *trig) 582 { 583 return (trig->ops == &timer_trigger_ops); 584 } 585 EXPORT_SYMBOL(is_stm32_timer_trigger); 586 587 static int stm32_timer_trigger_probe(struct platform_device *pdev) 588 { 589 struct device *dev = &pdev->dev; 590 struct stm32_timer_trigger *priv; 591 struct stm32_timers *ddata = dev_get_drvdata(pdev->dev.parent); 592 unsigned int index; 593 int ret; 594 595 if (of_property_read_u32(dev->of_node, "reg", &index)) 596 return -EINVAL; 597 598 if (index >= ARRAY_SIZE(triggers_table) || 599 index >= ARRAY_SIZE(valids_table)) 600 return -EINVAL; 601 602 /* Create an IIO device only if we have triggers to be validated */ 603 if (*valids_table[index]) 604 priv = stm32_setup_counter_device(dev); 605 else 606 priv = devm_kzalloc(dev, sizeof(*priv), GFP_KERNEL); 607 608 if (!priv) 609 return -ENOMEM; 610 611 priv->dev = dev; 612 priv->regmap = ddata->regmap; 613 priv->clk = ddata->clk; 614 priv->max_arr = ddata->max_arr; 615 priv->triggers = triggers_table[index]; 616 priv->valids = valids_table[index]; 617 618 ret = stm32_setup_iio_triggers(priv); 619 if (ret) 620 return ret; 621 622 platform_set_drvdata(pdev, priv); 623 624 return 0; 625 } 626 627 static const struct of_device_id stm32_trig_of_match[] = { 628 { .compatible = "st,stm32-timer-trigger", }, 629 { /* end node */ }, 630 }; 631 MODULE_DEVICE_TABLE(of, stm32_trig_of_match); 632 633 static struct platform_driver stm32_timer_trigger_driver = { 634 .probe = stm32_timer_trigger_probe, 635 .driver = { 636 .name = "stm32-timer-trigger", 637 .of_match_table = stm32_trig_of_match, 638 }, 639 }; 640 module_platform_driver(stm32_timer_trigger_driver); 641 642 MODULE_ALIAS("platform: stm32-timer-trigger"); 643 MODULE_DESCRIPTION("STMicroelectronics STM32 Timer Trigger driver"); 644 MODULE_LICENSE("GPL v2"); 645