1 // SPDX-License-Identifier: GPL-2.0
2 /*
3  * Copyright (C) STMicroelectronics 2016
4  *
5  * Author: Benjamin Gaignard <benjamin.gaignard@st.com>
6  *
7  */
8 
9 #include <linux/iio/iio.h>
10 #include <linux/iio/sysfs.h>
11 #include <linux/iio/timer/stm32-timer-trigger.h>
12 #include <linux/iio/trigger.h>
13 #include <linux/mfd/stm32-timers.h>
14 #include <linux/module.h>
15 #include <linux/platform_device.h>
16 #include <linux/of_device.h>
17 
18 #define MAX_TRIGGERS 7
19 #define MAX_VALIDS 5
20 
21 /* List the triggers created by each timer */
22 static const void *triggers_table[][MAX_TRIGGERS] = {
23 	{ TIM1_TRGO, TIM1_TRGO2, TIM1_CH1, TIM1_CH2, TIM1_CH3, TIM1_CH4,},
24 	{ TIM2_TRGO, TIM2_CH1, TIM2_CH2, TIM2_CH3, TIM2_CH4,},
25 	{ TIM3_TRGO, TIM3_CH1, TIM3_CH2, TIM3_CH3, TIM3_CH4,},
26 	{ TIM4_TRGO, TIM4_CH1, TIM4_CH2, TIM4_CH3, TIM4_CH4,},
27 	{ TIM5_TRGO, TIM5_CH1, TIM5_CH2, TIM5_CH3, TIM5_CH4,},
28 	{ TIM6_TRGO,},
29 	{ TIM7_TRGO,},
30 	{ TIM8_TRGO, TIM8_TRGO2, TIM8_CH1, TIM8_CH2, TIM8_CH3, TIM8_CH4,},
31 	{ TIM9_TRGO, TIM9_CH1, TIM9_CH2,},
32 	{ TIM10_OC1,},
33 	{ TIM11_OC1,},
34 	{ TIM12_TRGO, TIM12_CH1, TIM12_CH2,},
35 	{ TIM13_OC1,},
36 	{ TIM14_OC1,},
37 	{ TIM15_TRGO,},
38 	{ TIM16_OC1,},
39 	{ TIM17_OC1,},
40 };
41 
42 /* List the triggers accepted by each timer */
43 static const void *valids_table[][MAX_VALIDS] = {
44 	{ TIM5_TRGO, TIM2_TRGO, TIM3_TRGO, TIM4_TRGO,},
45 	{ TIM1_TRGO, TIM8_TRGO, TIM3_TRGO, TIM4_TRGO,},
46 	{ TIM1_TRGO, TIM2_TRGO, TIM5_TRGO, TIM4_TRGO,},
47 	{ TIM1_TRGO, TIM2_TRGO, TIM3_TRGO, TIM8_TRGO,},
48 	{ TIM2_TRGO, TIM3_TRGO, TIM4_TRGO, TIM8_TRGO,},
49 	{ }, /* timer 6 */
50 	{ }, /* timer 7 */
51 	{ TIM1_TRGO, TIM2_TRGO, TIM4_TRGO, TIM5_TRGO,},
52 	{ TIM2_TRGO, TIM3_TRGO, TIM10_OC1, TIM11_OC1,},
53 	{ }, /* timer 10 */
54 	{ }, /* timer 11 */
55 	{ TIM4_TRGO, TIM5_TRGO, TIM13_OC1, TIM14_OC1,},
56 };
57 
58 static const void *stm32h7_valids_table[][MAX_VALIDS] = {
59 	{ TIM15_TRGO, TIM2_TRGO, TIM3_TRGO, TIM4_TRGO,},
60 	{ TIM1_TRGO, TIM8_TRGO, TIM3_TRGO, TIM4_TRGO,},
61 	{ TIM1_TRGO, TIM2_TRGO, TIM15_TRGO, TIM4_TRGO,},
62 	{ TIM1_TRGO, TIM2_TRGO, TIM3_TRGO, TIM8_TRGO,},
63 	{ TIM1_TRGO, TIM8_TRGO, TIM3_TRGO, TIM4_TRGO,},
64 	{ }, /* timer 6 */
65 	{ }, /* timer 7 */
66 	{ TIM1_TRGO, TIM2_TRGO, TIM4_TRGO, TIM5_TRGO,},
67 	{ }, /* timer 9 */
68 	{ }, /* timer 10 */
69 	{ }, /* timer 11 */
70 	{ TIM4_TRGO, TIM5_TRGO, TIM13_OC1, TIM14_OC1,},
71 	{ }, /* timer 13 */
72 	{ }, /* timer 14 */
73 	{ TIM1_TRGO, TIM3_TRGO, TIM16_OC1, TIM17_OC1,},
74 	{ }, /* timer 16 */
75 	{ }, /* timer 17 */
76 };
77 
78 struct stm32_timer_trigger_regs {
79 	u32 cr1;
80 	u32 cr2;
81 	u32 psc;
82 	u32 arr;
83 	u32 cnt;
84 	u32 smcr;
85 };
86 
87 struct stm32_timer_trigger {
88 	struct device *dev;
89 	struct regmap *regmap;
90 	struct clk *clk;
91 	bool enabled;
92 	u32 max_arr;
93 	const void *triggers;
94 	const void *valids;
95 	bool has_trgo2;
96 	struct mutex lock; /* concurrent sysfs configuration */
97 	struct list_head tr_list;
98 	struct stm32_timer_trigger_regs bak;
99 };
100 
101 struct stm32_timer_trigger_cfg {
102 	const void *(*valids_table)[MAX_VALIDS];
103 	const unsigned int num_valids_table;
104 };
105 
106 static bool stm32_timer_is_trgo2_name(const char *name)
107 {
108 	return !!strstr(name, "trgo2");
109 }
110 
111 static bool stm32_timer_is_trgo_name(const char *name)
112 {
113 	return (!!strstr(name, "trgo") && !strstr(name, "trgo2"));
114 }
115 
116 static int stm32_timer_start(struct stm32_timer_trigger *priv,
117 			     struct iio_trigger *trig,
118 			     unsigned int frequency)
119 {
120 	unsigned long long prd, div;
121 	int prescaler = 0;
122 	u32 ccer;
123 
124 	/* Period and prescaler values depends of clock rate */
125 	div = (unsigned long long)clk_get_rate(priv->clk);
126 
127 	do_div(div, frequency);
128 
129 	prd = div;
130 
131 	/*
132 	 * Increase prescaler value until we get a result that fit
133 	 * with auto reload register maximum value.
134 	 */
135 	while (div > priv->max_arr) {
136 		prescaler++;
137 		div = prd;
138 		do_div(div, (prescaler + 1));
139 	}
140 	prd = div;
141 
142 	if (prescaler > MAX_TIM_PSC) {
143 		dev_err(priv->dev, "prescaler exceeds the maximum value\n");
144 		return -EINVAL;
145 	}
146 
147 	/* Check if nobody else use the timer */
148 	regmap_read(priv->regmap, TIM_CCER, &ccer);
149 	if (ccer & TIM_CCER_CCXE)
150 		return -EBUSY;
151 
152 	mutex_lock(&priv->lock);
153 	if (!priv->enabled) {
154 		priv->enabled = true;
155 		clk_enable(priv->clk);
156 	}
157 
158 	regmap_write(priv->regmap, TIM_PSC, prescaler);
159 	regmap_write(priv->regmap, TIM_ARR, prd - 1);
160 	regmap_update_bits(priv->regmap, TIM_CR1, TIM_CR1_ARPE, TIM_CR1_ARPE);
161 
162 	/* Force master mode to update mode */
163 	if (stm32_timer_is_trgo2_name(trig->name))
164 		regmap_update_bits(priv->regmap, TIM_CR2, TIM_CR2_MMS2,
165 				   0x2 << TIM_CR2_MMS2_SHIFT);
166 	else
167 		regmap_update_bits(priv->regmap, TIM_CR2, TIM_CR2_MMS,
168 				   0x2 << TIM_CR2_MMS_SHIFT);
169 
170 	/* Make sure that registers are updated */
171 	regmap_update_bits(priv->regmap, TIM_EGR, TIM_EGR_UG, TIM_EGR_UG);
172 
173 	/* Enable controller */
174 	regmap_update_bits(priv->regmap, TIM_CR1, TIM_CR1_CEN, TIM_CR1_CEN);
175 	mutex_unlock(&priv->lock);
176 
177 	return 0;
178 }
179 
180 static void stm32_timer_stop(struct stm32_timer_trigger *priv,
181 			     struct iio_trigger *trig)
182 {
183 	u32 ccer;
184 
185 	regmap_read(priv->regmap, TIM_CCER, &ccer);
186 	if (ccer & TIM_CCER_CCXE)
187 		return;
188 
189 	mutex_lock(&priv->lock);
190 	/* Stop timer */
191 	regmap_update_bits(priv->regmap, TIM_CR1, TIM_CR1_ARPE, 0);
192 	regmap_update_bits(priv->regmap, TIM_CR1, TIM_CR1_CEN, 0);
193 	regmap_write(priv->regmap, TIM_PSC, 0);
194 	regmap_write(priv->regmap, TIM_ARR, 0);
195 
196 	/* Force disable master mode */
197 	if (stm32_timer_is_trgo2_name(trig->name))
198 		regmap_update_bits(priv->regmap, TIM_CR2, TIM_CR2_MMS2, 0);
199 	else
200 		regmap_update_bits(priv->regmap, TIM_CR2, TIM_CR2_MMS, 0);
201 
202 	/* Make sure that registers are updated */
203 	regmap_update_bits(priv->regmap, TIM_EGR, TIM_EGR_UG, TIM_EGR_UG);
204 
205 	if (priv->enabled) {
206 		priv->enabled = false;
207 		clk_disable(priv->clk);
208 	}
209 	mutex_unlock(&priv->lock);
210 }
211 
212 static ssize_t stm32_tt_store_frequency(struct device *dev,
213 					struct device_attribute *attr,
214 					const char *buf, size_t len)
215 {
216 	struct iio_trigger *trig = to_iio_trigger(dev);
217 	struct stm32_timer_trigger *priv = iio_trigger_get_drvdata(trig);
218 	unsigned int freq;
219 	int ret;
220 
221 	ret = kstrtouint(buf, 10, &freq);
222 	if (ret)
223 		return ret;
224 
225 	if (freq == 0) {
226 		stm32_timer_stop(priv, trig);
227 	} else {
228 		ret = stm32_timer_start(priv, trig, freq);
229 		if (ret)
230 			return ret;
231 	}
232 
233 	return len;
234 }
235 
236 static ssize_t stm32_tt_read_frequency(struct device *dev,
237 				       struct device_attribute *attr, char *buf)
238 {
239 	struct iio_trigger *trig = to_iio_trigger(dev);
240 	struct stm32_timer_trigger *priv = iio_trigger_get_drvdata(trig);
241 	u32 psc, arr, cr1;
242 	unsigned long long freq = 0;
243 
244 	regmap_read(priv->regmap, TIM_CR1, &cr1);
245 	regmap_read(priv->regmap, TIM_PSC, &psc);
246 	regmap_read(priv->regmap, TIM_ARR, &arr);
247 
248 	if (cr1 & TIM_CR1_CEN) {
249 		freq = (unsigned long long)clk_get_rate(priv->clk);
250 		do_div(freq, psc + 1);
251 		do_div(freq, arr + 1);
252 	}
253 
254 	return sprintf(buf, "%d\n", (unsigned int)freq);
255 }
256 
257 static IIO_DEV_ATTR_SAMP_FREQ(0660,
258 			      stm32_tt_read_frequency,
259 			      stm32_tt_store_frequency);
260 
261 #define MASTER_MODE_MAX		7
262 #define MASTER_MODE2_MAX	15
263 
264 static char *master_mode_table[] = {
265 	"reset",
266 	"enable",
267 	"update",
268 	"compare_pulse",
269 	"OC1REF",
270 	"OC2REF",
271 	"OC3REF",
272 	"OC4REF",
273 	/* Master mode selection 2 only */
274 	"OC5REF",
275 	"OC6REF",
276 	"compare_pulse_OC4REF",
277 	"compare_pulse_OC6REF",
278 	"compare_pulse_OC4REF_r_or_OC6REF_r",
279 	"compare_pulse_OC4REF_r_or_OC6REF_f",
280 	"compare_pulse_OC5REF_r_or_OC6REF_r",
281 	"compare_pulse_OC5REF_r_or_OC6REF_f",
282 };
283 
284 static ssize_t stm32_tt_show_master_mode(struct device *dev,
285 					 struct device_attribute *attr,
286 					 char *buf)
287 {
288 	struct stm32_timer_trigger *priv = dev_get_drvdata(dev);
289 	struct iio_trigger *trig = to_iio_trigger(dev);
290 	u32 cr2;
291 
292 	regmap_read(priv->regmap, TIM_CR2, &cr2);
293 
294 	if (stm32_timer_is_trgo2_name(trig->name))
295 		cr2 = (cr2 & TIM_CR2_MMS2) >> TIM_CR2_MMS2_SHIFT;
296 	else
297 		cr2 = (cr2 & TIM_CR2_MMS) >> TIM_CR2_MMS_SHIFT;
298 
299 	return sysfs_emit(buf, "%s\n", master_mode_table[cr2]);
300 }
301 
302 static ssize_t stm32_tt_store_master_mode(struct device *dev,
303 					  struct device_attribute *attr,
304 					  const char *buf, size_t len)
305 {
306 	struct stm32_timer_trigger *priv = dev_get_drvdata(dev);
307 	struct iio_trigger *trig = to_iio_trigger(dev);
308 	u32 mask, shift, master_mode_max;
309 	int i;
310 
311 	if (stm32_timer_is_trgo2_name(trig->name)) {
312 		mask = TIM_CR2_MMS2;
313 		shift = TIM_CR2_MMS2_SHIFT;
314 		master_mode_max = MASTER_MODE2_MAX;
315 	} else {
316 		mask = TIM_CR2_MMS;
317 		shift = TIM_CR2_MMS_SHIFT;
318 		master_mode_max = MASTER_MODE_MAX;
319 	}
320 
321 	for (i = 0; i <= master_mode_max; i++) {
322 		if (!strncmp(master_mode_table[i], buf,
323 			     strlen(master_mode_table[i]))) {
324 			mutex_lock(&priv->lock);
325 			if (!priv->enabled) {
326 				/* Clock should be enabled first */
327 				priv->enabled = true;
328 				clk_enable(priv->clk);
329 			}
330 			regmap_update_bits(priv->regmap, TIM_CR2, mask,
331 					   i << shift);
332 			mutex_unlock(&priv->lock);
333 			return len;
334 		}
335 	}
336 
337 	return -EINVAL;
338 }
339 
340 static ssize_t stm32_tt_show_master_mode_avail(struct device *dev,
341 					       struct device_attribute *attr,
342 					       char *buf)
343 {
344 	struct iio_trigger *trig = to_iio_trigger(dev);
345 	unsigned int i, master_mode_max;
346 	size_t len = 0;
347 
348 	if (stm32_timer_is_trgo2_name(trig->name))
349 		master_mode_max = MASTER_MODE2_MAX;
350 	else
351 		master_mode_max = MASTER_MODE_MAX;
352 
353 	for (i = 0; i <= master_mode_max; i++)
354 		len += scnprintf(buf + len, PAGE_SIZE - len,
355 			"%s ", master_mode_table[i]);
356 
357 	/* replace trailing space by newline */
358 	buf[len - 1] = '\n';
359 
360 	return len;
361 }
362 
363 static IIO_DEVICE_ATTR(master_mode_available, 0444,
364 		       stm32_tt_show_master_mode_avail, NULL, 0);
365 
366 static IIO_DEVICE_ATTR(master_mode, 0660,
367 		       stm32_tt_show_master_mode,
368 		       stm32_tt_store_master_mode,
369 		       0);
370 
371 static struct attribute *stm32_trigger_attrs[] = {
372 	&iio_dev_attr_sampling_frequency.dev_attr.attr,
373 	&iio_dev_attr_master_mode.dev_attr.attr,
374 	&iio_dev_attr_master_mode_available.dev_attr.attr,
375 	NULL,
376 };
377 
378 static const struct attribute_group stm32_trigger_attr_group = {
379 	.attrs = stm32_trigger_attrs,
380 };
381 
382 static const struct attribute_group *stm32_trigger_attr_groups[] = {
383 	&stm32_trigger_attr_group,
384 	NULL,
385 };
386 
387 static const struct iio_trigger_ops timer_trigger_ops = {
388 };
389 
390 static void stm32_unregister_iio_triggers(struct stm32_timer_trigger *priv)
391 {
392 	struct iio_trigger *tr;
393 
394 	list_for_each_entry(tr, &priv->tr_list, alloc_list)
395 		iio_trigger_unregister(tr);
396 }
397 
398 static int stm32_register_iio_triggers(struct stm32_timer_trigger *priv)
399 {
400 	int ret;
401 	const char * const *cur = priv->triggers;
402 
403 	INIT_LIST_HEAD(&priv->tr_list);
404 
405 	while (cur && *cur) {
406 		struct iio_trigger *trig;
407 		bool cur_is_trgo = stm32_timer_is_trgo_name(*cur);
408 		bool cur_is_trgo2 = stm32_timer_is_trgo2_name(*cur);
409 
410 		if (cur_is_trgo2 && !priv->has_trgo2) {
411 			cur++;
412 			continue;
413 		}
414 
415 		trig = devm_iio_trigger_alloc(priv->dev, "%s", *cur);
416 		if  (!trig)
417 			return -ENOMEM;
418 
419 		trig->dev.parent = priv->dev->parent;
420 		trig->ops = &timer_trigger_ops;
421 
422 		/*
423 		 * sampling frequency and master mode attributes
424 		 * should only be available on trgo/trgo2 triggers
425 		 */
426 		if (cur_is_trgo || cur_is_trgo2)
427 			trig->dev.groups = stm32_trigger_attr_groups;
428 
429 		iio_trigger_set_drvdata(trig, priv);
430 
431 		ret = iio_trigger_register(trig);
432 		if (ret) {
433 			stm32_unregister_iio_triggers(priv);
434 			return ret;
435 		}
436 
437 		list_add_tail(&trig->alloc_list, &priv->tr_list);
438 		cur++;
439 	}
440 
441 	return 0;
442 }
443 
444 static int stm32_counter_read_raw(struct iio_dev *indio_dev,
445 				  struct iio_chan_spec const *chan,
446 				  int *val, int *val2, long mask)
447 {
448 	struct stm32_timer_trigger *priv = iio_priv(indio_dev);
449 	u32 dat;
450 
451 	switch (mask) {
452 	case IIO_CHAN_INFO_RAW:
453 		regmap_read(priv->regmap, TIM_CNT, &dat);
454 		*val = dat;
455 		return IIO_VAL_INT;
456 
457 	case IIO_CHAN_INFO_ENABLE:
458 		regmap_read(priv->regmap, TIM_CR1, &dat);
459 		*val = (dat & TIM_CR1_CEN) ? 1 : 0;
460 		return IIO_VAL_INT;
461 
462 	case IIO_CHAN_INFO_SCALE:
463 		regmap_read(priv->regmap, TIM_SMCR, &dat);
464 		dat &= TIM_SMCR_SMS;
465 
466 		*val = 1;
467 		*val2 = 0;
468 
469 		/* in quadrature case scale = 0.25 */
470 		if (dat == 3)
471 			*val2 = 2;
472 
473 		return IIO_VAL_FRACTIONAL_LOG2;
474 	}
475 
476 	return -EINVAL;
477 }
478 
479 static int stm32_counter_write_raw(struct iio_dev *indio_dev,
480 				   struct iio_chan_spec const *chan,
481 				   int val, int val2, long mask)
482 {
483 	struct stm32_timer_trigger *priv = iio_priv(indio_dev);
484 
485 	switch (mask) {
486 	case IIO_CHAN_INFO_RAW:
487 		return regmap_write(priv->regmap, TIM_CNT, val);
488 
489 	case IIO_CHAN_INFO_SCALE:
490 		/* fixed scale */
491 		return -EINVAL;
492 
493 	case IIO_CHAN_INFO_ENABLE:
494 		mutex_lock(&priv->lock);
495 		if (val) {
496 			if (!priv->enabled) {
497 				priv->enabled = true;
498 				clk_enable(priv->clk);
499 			}
500 			regmap_update_bits(priv->regmap, TIM_CR1, TIM_CR1_CEN,
501 					   TIM_CR1_CEN);
502 		} else {
503 			regmap_update_bits(priv->regmap, TIM_CR1, TIM_CR1_CEN,
504 					   0);
505 			if (priv->enabled) {
506 				priv->enabled = false;
507 				clk_disable(priv->clk);
508 			}
509 		}
510 		mutex_unlock(&priv->lock);
511 		return 0;
512 	}
513 
514 	return -EINVAL;
515 }
516 
517 static int stm32_counter_validate_trigger(struct iio_dev *indio_dev,
518 					  struct iio_trigger *trig)
519 {
520 	struct stm32_timer_trigger *priv = iio_priv(indio_dev);
521 	const char * const *cur = priv->valids;
522 	unsigned int i = 0;
523 
524 	if (!is_stm32_timer_trigger(trig))
525 		return -EINVAL;
526 
527 	while (cur && *cur) {
528 		if (!strncmp(trig->name, *cur, strlen(trig->name))) {
529 			regmap_update_bits(priv->regmap,
530 					   TIM_SMCR, TIM_SMCR_TS,
531 					   i << TIM_SMCR_TS_SHIFT);
532 			return 0;
533 		}
534 		cur++;
535 		i++;
536 	}
537 
538 	return -EINVAL;
539 }
540 
541 static const struct iio_info stm32_trigger_info = {
542 	.validate_trigger = stm32_counter_validate_trigger,
543 	.read_raw = stm32_counter_read_raw,
544 	.write_raw = stm32_counter_write_raw
545 };
546 
547 static const char *const stm32_trigger_modes[] = {
548 	"trigger",
549 };
550 
551 static int stm32_set_trigger_mode(struct iio_dev *indio_dev,
552 				  const struct iio_chan_spec *chan,
553 				  unsigned int mode)
554 {
555 	struct stm32_timer_trigger *priv = iio_priv(indio_dev);
556 
557 	regmap_update_bits(priv->regmap, TIM_SMCR, TIM_SMCR_SMS, TIM_SMCR_SMS);
558 
559 	return 0;
560 }
561 
562 static int stm32_get_trigger_mode(struct iio_dev *indio_dev,
563 				  const struct iio_chan_spec *chan)
564 {
565 	struct stm32_timer_trigger *priv = iio_priv(indio_dev);
566 	u32 smcr;
567 
568 	regmap_read(priv->regmap, TIM_SMCR, &smcr);
569 
570 	return (smcr & TIM_SMCR_SMS) == TIM_SMCR_SMS ? 0 : -EINVAL;
571 }
572 
573 static const struct iio_enum stm32_trigger_mode_enum = {
574 	.items = stm32_trigger_modes,
575 	.num_items = ARRAY_SIZE(stm32_trigger_modes),
576 	.set = stm32_set_trigger_mode,
577 	.get = stm32_get_trigger_mode
578 };
579 
580 static const char *const stm32_enable_modes[] = {
581 	"always",
582 	"gated",
583 	"triggered",
584 };
585 
586 static int stm32_enable_mode2sms(int mode)
587 {
588 	switch (mode) {
589 	case 0:
590 		return 0;
591 	case 1:
592 		return 5;
593 	case 2:
594 		return 6;
595 	}
596 
597 	return -EINVAL;
598 }
599 
600 static int stm32_set_enable_mode(struct iio_dev *indio_dev,
601 				 const struct iio_chan_spec *chan,
602 				 unsigned int mode)
603 {
604 	struct stm32_timer_trigger *priv = iio_priv(indio_dev);
605 	int sms = stm32_enable_mode2sms(mode);
606 
607 	if (sms < 0)
608 		return sms;
609 	/*
610 	 * Triggered mode sets CEN bit automatically by hardware. So, first
611 	 * enable counter clock, so it can use it. Keeps it in sync with CEN.
612 	 */
613 	mutex_lock(&priv->lock);
614 	if (sms == 6 && !priv->enabled) {
615 		clk_enable(priv->clk);
616 		priv->enabled = true;
617 	}
618 	mutex_unlock(&priv->lock);
619 
620 	regmap_update_bits(priv->regmap, TIM_SMCR, TIM_SMCR_SMS, sms);
621 
622 	return 0;
623 }
624 
625 static int stm32_sms2enable_mode(int mode)
626 {
627 	switch (mode) {
628 	case 0:
629 		return 0;
630 	case 5:
631 		return 1;
632 	case 6:
633 		return 2;
634 	}
635 
636 	return -EINVAL;
637 }
638 
639 static int stm32_get_enable_mode(struct iio_dev *indio_dev,
640 				 const struct iio_chan_spec *chan)
641 {
642 	struct stm32_timer_trigger *priv = iio_priv(indio_dev);
643 	u32 smcr;
644 
645 	regmap_read(priv->regmap, TIM_SMCR, &smcr);
646 	smcr &= TIM_SMCR_SMS;
647 
648 	return stm32_sms2enable_mode(smcr);
649 }
650 
651 static const struct iio_enum stm32_enable_mode_enum = {
652 	.items = stm32_enable_modes,
653 	.num_items = ARRAY_SIZE(stm32_enable_modes),
654 	.set = stm32_set_enable_mode,
655 	.get = stm32_get_enable_mode
656 };
657 
658 static ssize_t stm32_count_get_preset(struct iio_dev *indio_dev,
659 				      uintptr_t private,
660 				      const struct iio_chan_spec *chan,
661 				      char *buf)
662 {
663 	struct stm32_timer_trigger *priv = iio_priv(indio_dev);
664 	u32 arr;
665 
666 	regmap_read(priv->regmap, TIM_ARR, &arr);
667 
668 	return snprintf(buf, PAGE_SIZE, "%u\n", arr);
669 }
670 
671 static ssize_t stm32_count_set_preset(struct iio_dev *indio_dev,
672 				      uintptr_t private,
673 				      const struct iio_chan_spec *chan,
674 				      const char *buf, size_t len)
675 {
676 	struct stm32_timer_trigger *priv = iio_priv(indio_dev);
677 	unsigned int preset;
678 	int ret;
679 
680 	ret = kstrtouint(buf, 0, &preset);
681 	if (ret)
682 		return ret;
683 
684 	/* TIMx_ARR register shouldn't be buffered (ARPE=0) */
685 	regmap_update_bits(priv->regmap, TIM_CR1, TIM_CR1_ARPE, 0);
686 	regmap_write(priv->regmap, TIM_ARR, preset);
687 
688 	return len;
689 }
690 
691 static const struct iio_chan_spec_ext_info stm32_trigger_count_info[] = {
692 	{
693 		.name = "preset",
694 		.shared = IIO_SEPARATE,
695 		.read = stm32_count_get_preset,
696 		.write = stm32_count_set_preset
697 	},
698 	IIO_ENUM("enable_mode", IIO_SEPARATE, &stm32_enable_mode_enum),
699 	IIO_ENUM_AVAILABLE("enable_mode", &stm32_enable_mode_enum),
700 	IIO_ENUM("trigger_mode", IIO_SEPARATE, &stm32_trigger_mode_enum),
701 	IIO_ENUM_AVAILABLE("trigger_mode", &stm32_trigger_mode_enum),
702 	{}
703 };
704 
705 static const struct iio_chan_spec stm32_trigger_channel = {
706 	.type = IIO_COUNT,
707 	.channel = 0,
708 	.info_mask_separate = BIT(IIO_CHAN_INFO_RAW) |
709 			      BIT(IIO_CHAN_INFO_ENABLE) |
710 			      BIT(IIO_CHAN_INFO_SCALE),
711 	.ext_info = stm32_trigger_count_info,
712 	.indexed = 1
713 };
714 
715 static struct stm32_timer_trigger *stm32_setup_counter_device(struct device *dev)
716 {
717 	struct iio_dev *indio_dev;
718 	int ret;
719 
720 	indio_dev = devm_iio_device_alloc(dev,
721 					  sizeof(struct stm32_timer_trigger));
722 	if (!indio_dev)
723 		return NULL;
724 
725 	indio_dev->name = dev_name(dev);
726 	indio_dev->info = &stm32_trigger_info;
727 	indio_dev->modes = INDIO_HARDWARE_TRIGGERED;
728 	indio_dev->num_channels = 1;
729 	indio_dev->channels = &stm32_trigger_channel;
730 
731 	ret = devm_iio_device_register(dev, indio_dev);
732 	if (ret)
733 		return NULL;
734 
735 	return iio_priv(indio_dev);
736 }
737 
738 /**
739  * is_stm32_timer_trigger
740  * @trig: trigger to be checked
741  *
742  * return true if the trigger is a valid stm32 iio timer trigger
743  * either return false
744  */
745 bool is_stm32_timer_trigger(struct iio_trigger *trig)
746 {
747 	return (trig->ops == &timer_trigger_ops);
748 }
749 EXPORT_SYMBOL(is_stm32_timer_trigger);
750 
751 static void stm32_timer_detect_trgo2(struct stm32_timer_trigger *priv)
752 {
753 	u32 val;
754 
755 	/*
756 	 * Master mode selection 2 bits can only be written and read back when
757 	 * timer supports it.
758 	 */
759 	regmap_update_bits(priv->regmap, TIM_CR2, TIM_CR2_MMS2, TIM_CR2_MMS2);
760 	regmap_read(priv->regmap, TIM_CR2, &val);
761 	regmap_update_bits(priv->regmap, TIM_CR2, TIM_CR2_MMS2, 0);
762 	priv->has_trgo2 = !!val;
763 }
764 
765 static int stm32_timer_trigger_probe(struct platform_device *pdev)
766 {
767 	struct device *dev = &pdev->dev;
768 	struct stm32_timer_trigger *priv;
769 	struct stm32_timers *ddata = dev_get_drvdata(pdev->dev.parent);
770 	const struct stm32_timer_trigger_cfg *cfg;
771 	unsigned int index;
772 	int ret;
773 
774 	if (of_property_read_u32(dev->of_node, "reg", &index))
775 		return -EINVAL;
776 
777 	cfg = (const struct stm32_timer_trigger_cfg *)
778 		of_match_device(dev->driver->of_match_table, dev)->data;
779 
780 	if (index >= ARRAY_SIZE(triggers_table) ||
781 	    index >= cfg->num_valids_table)
782 		return -EINVAL;
783 
784 	/* Create an IIO device only if we have triggers to be validated */
785 	if (*cfg->valids_table[index])
786 		priv = stm32_setup_counter_device(dev);
787 	else
788 		priv = devm_kzalloc(dev, sizeof(*priv), GFP_KERNEL);
789 
790 	if (!priv)
791 		return -ENOMEM;
792 
793 	priv->dev = dev;
794 	priv->regmap = ddata->regmap;
795 	priv->clk = ddata->clk;
796 	priv->max_arr = ddata->max_arr;
797 	priv->triggers = triggers_table[index];
798 	priv->valids = cfg->valids_table[index];
799 	stm32_timer_detect_trgo2(priv);
800 	mutex_init(&priv->lock);
801 
802 	ret = stm32_register_iio_triggers(priv);
803 	if (ret)
804 		return ret;
805 
806 	platform_set_drvdata(pdev, priv);
807 
808 	return 0;
809 }
810 
811 static int stm32_timer_trigger_remove(struct platform_device *pdev)
812 {
813 	struct stm32_timer_trigger *priv = platform_get_drvdata(pdev);
814 	u32 val;
815 
816 	/* Unregister triggers before everything can be safely turned off */
817 	stm32_unregister_iio_triggers(priv);
818 
819 	/* Check if nobody else use the timer, then disable it */
820 	regmap_read(priv->regmap, TIM_CCER, &val);
821 	if (!(val & TIM_CCER_CCXE))
822 		regmap_update_bits(priv->regmap, TIM_CR1, TIM_CR1_CEN, 0);
823 
824 	if (priv->enabled)
825 		clk_disable(priv->clk);
826 
827 	return 0;
828 }
829 
830 static int __maybe_unused stm32_timer_trigger_suspend(struct device *dev)
831 {
832 	struct stm32_timer_trigger *priv = dev_get_drvdata(dev);
833 
834 	/* Only take care of enabled timer: don't disturb other MFD child */
835 	if (priv->enabled) {
836 		/* Backup registers that may get lost in low power mode */
837 		regmap_read(priv->regmap, TIM_CR1, &priv->bak.cr1);
838 		regmap_read(priv->regmap, TIM_CR2, &priv->bak.cr2);
839 		regmap_read(priv->regmap, TIM_PSC, &priv->bak.psc);
840 		regmap_read(priv->regmap, TIM_ARR, &priv->bak.arr);
841 		regmap_read(priv->regmap, TIM_CNT, &priv->bak.cnt);
842 		regmap_read(priv->regmap, TIM_SMCR, &priv->bak.smcr);
843 
844 		/* Disable the timer */
845 		regmap_update_bits(priv->regmap, TIM_CR1, TIM_CR1_CEN, 0);
846 		clk_disable(priv->clk);
847 	}
848 
849 	return 0;
850 }
851 
852 static int __maybe_unused stm32_timer_trigger_resume(struct device *dev)
853 {
854 	struct stm32_timer_trigger *priv = dev_get_drvdata(dev);
855 	int ret;
856 
857 	if (priv->enabled) {
858 		ret = clk_enable(priv->clk);
859 		if (ret)
860 			return ret;
861 
862 		/* restore master/slave modes */
863 		regmap_write(priv->regmap, TIM_SMCR, priv->bak.smcr);
864 		regmap_write(priv->regmap, TIM_CR2, priv->bak.cr2);
865 
866 		/* restore sampling_frequency (trgo / trgo2 triggers) */
867 		regmap_write(priv->regmap, TIM_PSC, priv->bak.psc);
868 		regmap_write(priv->regmap, TIM_ARR, priv->bak.arr);
869 		regmap_write(priv->regmap, TIM_CNT, priv->bak.cnt);
870 
871 		/* Also re-enables the timer */
872 		regmap_write(priv->regmap, TIM_CR1, priv->bak.cr1);
873 	}
874 
875 	return 0;
876 }
877 
878 static SIMPLE_DEV_PM_OPS(stm32_timer_trigger_pm_ops,
879 			 stm32_timer_trigger_suspend,
880 			 stm32_timer_trigger_resume);
881 
882 static const struct stm32_timer_trigger_cfg stm32_timer_trg_cfg = {
883 	.valids_table = valids_table,
884 	.num_valids_table = ARRAY_SIZE(valids_table),
885 };
886 
887 static const struct stm32_timer_trigger_cfg stm32h7_timer_trg_cfg = {
888 	.valids_table = stm32h7_valids_table,
889 	.num_valids_table = ARRAY_SIZE(stm32h7_valids_table),
890 };
891 
892 static const struct of_device_id stm32_trig_of_match[] = {
893 	{
894 		.compatible = "st,stm32-timer-trigger",
895 		.data = (void *)&stm32_timer_trg_cfg,
896 	}, {
897 		.compatible = "st,stm32h7-timer-trigger",
898 		.data = (void *)&stm32h7_timer_trg_cfg,
899 	},
900 	{ /* end node */ },
901 };
902 MODULE_DEVICE_TABLE(of, stm32_trig_of_match);
903 
904 static struct platform_driver stm32_timer_trigger_driver = {
905 	.probe = stm32_timer_trigger_probe,
906 	.remove = stm32_timer_trigger_remove,
907 	.driver = {
908 		.name = "stm32-timer-trigger",
909 		.of_match_table = stm32_trig_of_match,
910 		.pm = &stm32_timer_trigger_pm_ops,
911 	},
912 };
913 module_platform_driver(stm32_timer_trigger_driver);
914 
915 MODULE_ALIAS("platform: stm32-timer-trigger");
916 MODULE_DESCRIPTION("STMicroelectronics STM32 Timer Trigger driver");
917 MODULE_LICENSE("GPL v2");
918