1 // SPDX-License-Identifier: GPL-2.0
2 /*
3  * Copyright (C) STMicroelectronics 2016
4  *
5  * Author: Benjamin Gaignard <benjamin.gaignard@st.com>
6  *
7  */
8 
9 #include <linux/iio/iio.h>
10 #include <linux/iio/sysfs.h>
11 #include <linux/iio/timer/stm32-timer-trigger.h>
12 #include <linux/iio/trigger.h>
13 #include <linux/mfd/stm32-timers.h>
14 #include <linux/module.h>
15 #include <linux/platform_device.h>
16 #include <linux/of_device.h>
17 
18 #define MAX_TRIGGERS 7
19 #define MAX_VALIDS 5
20 
21 /* List the triggers created by each timer */
22 static const void *triggers_table[][MAX_TRIGGERS] = {
23 	{ TIM1_TRGO, TIM1_TRGO2, TIM1_CH1, TIM1_CH2, TIM1_CH3, TIM1_CH4,},
24 	{ TIM2_TRGO, TIM2_CH1, TIM2_CH2, TIM2_CH3, TIM2_CH4,},
25 	{ TIM3_TRGO, TIM3_CH1, TIM3_CH2, TIM3_CH3, TIM3_CH4,},
26 	{ TIM4_TRGO, TIM4_CH1, TIM4_CH2, TIM4_CH3, TIM4_CH4,},
27 	{ TIM5_TRGO, TIM5_CH1, TIM5_CH2, TIM5_CH3, TIM5_CH4,},
28 	{ TIM6_TRGO,},
29 	{ TIM7_TRGO,},
30 	{ TIM8_TRGO, TIM8_TRGO2, TIM8_CH1, TIM8_CH2, TIM8_CH3, TIM8_CH4,},
31 	{ TIM9_TRGO, TIM9_CH1, TIM9_CH2,},
32 	{ TIM10_OC1,},
33 	{ TIM11_OC1,},
34 	{ TIM12_TRGO, TIM12_CH1, TIM12_CH2,},
35 	{ TIM13_OC1,},
36 	{ TIM14_OC1,},
37 	{ TIM15_TRGO,},
38 	{ TIM16_OC1,},
39 	{ TIM17_OC1,},
40 };
41 
42 /* List the triggers accepted by each timer */
43 static const void *valids_table[][MAX_VALIDS] = {
44 	{ TIM5_TRGO, TIM2_TRGO, TIM3_TRGO, TIM4_TRGO,},
45 	{ TIM1_TRGO, TIM8_TRGO, TIM3_TRGO, TIM4_TRGO,},
46 	{ TIM1_TRGO, TIM2_TRGO, TIM5_TRGO, TIM4_TRGO,},
47 	{ TIM1_TRGO, TIM2_TRGO, TIM3_TRGO, TIM8_TRGO,},
48 	{ TIM2_TRGO, TIM3_TRGO, TIM4_TRGO, TIM8_TRGO,},
49 	{ }, /* timer 6 */
50 	{ }, /* timer 7 */
51 	{ TIM1_TRGO, TIM2_TRGO, TIM4_TRGO, TIM5_TRGO,},
52 	{ TIM2_TRGO, TIM3_TRGO, TIM10_OC1, TIM11_OC1,},
53 	{ }, /* timer 10 */
54 	{ }, /* timer 11 */
55 	{ TIM4_TRGO, TIM5_TRGO, TIM13_OC1, TIM14_OC1,},
56 };
57 
58 static const void *stm32h7_valids_table[][MAX_VALIDS] = {
59 	{ TIM15_TRGO, TIM2_TRGO, TIM3_TRGO, TIM4_TRGO,},
60 	{ TIM1_TRGO, TIM8_TRGO, TIM3_TRGO, TIM4_TRGO,},
61 	{ TIM1_TRGO, TIM2_TRGO, TIM15_TRGO, TIM4_TRGO,},
62 	{ TIM1_TRGO, TIM2_TRGO, TIM3_TRGO, TIM8_TRGO,},
63 	{ TIM1_TRGO, TIM8_TRGO, TIM3_TRGO, TIM4_TRGO,},
64 	{ }, /* timer 6 */
65 	{ }, /* timer 7 */
66 	{ TIM1_TRGO, TIM2_TRGO, TIM4_TRGO, TIM5_TRGO,},
67 	{ }, /* timer 9 */
68 	{ }, /* timer 10 */
69 	{ }, /* timer 11 */
70 	{ TIM4_TRGO, TIM5_TRGO, TIM13_OC1, TIM14_OC1,},
71 	{ }, /* timer 13 */
72 	{ }, /* timer 14 */
73 	{ TIM1_TRGO, TIM3_TRGO, TIM16_OC1, TIM17_OC1,},
74 	{ }, /* timer 16 */
75 	{ }, /* timer 17 */
76 };
77 
78 struct stm32_timer_trigger {
79 	struct device *dev;
80 	struct regmap *regmap;
81 	struct clk *clk;
82 	u32 max_arr;
83 	const void *triggers;
84 	const void *valids;
85 	bool has_trgo2;
86 };
87 
88 struct stm32_timer_trigger_cfg {
89 	const void *(*valids_table)[MAX_VALIDS];
90 	const unsigned int num_valids_table;
91 };
92 
93 static bool stm32_timer_is_trgo2_name(const char *name)
94 {
95 	return !!strstr(name, "trgo2");
96 }
97 
98 static bool stm32_timer_is_trgo_name(const char *name)
99 {
100 	return (!!strstr(name, "trgo") && !strstr(name, "trgo2"));
101 }
102 
103 static int stm32_timer_start(struct stm32_timer_trigger *priv,
104 			     struct iio_trigger *trig,
105 			     unsigned int frequency)
106 {
107 	unsigned long long prd, div;
108 	int prescaler = 0;
109 	u32 ccer, cr1;
110 
111 	/* Period and prescaler values depends of clock rate */
112 	div = (unsigned long long)clk_get_rate(priv->clk);
113 
114 	do_div(div, frequency);
115 
116 	prd = div;
117 
118 	/*
119 	 * Increase prescaler value until we get a result that fit
120 	 * with auto reload register maximum value.
121 	 */
122 	while (div > priv->max_arr) {
123 		prescaler++;
124 		div = prd;
125 		do_div(div, (prescaler + 1));
126 	}
127 	prd = div;
128 
129 	if (prescaler > MAX_TIM_PSC) {
130 		dev_err(priv->dev, "prescaler exceeds the maximum value\n");
131 		return -EINVAL;
132 	}
133 
134 	/* Check if nobody else use the timer */
135 	regmap_read(priv->regmap, TIM_CCER, &ccer);
136 	if (ccer & TIM_CCER_CCXE)
137 		return -EBUSY;
138 
139 	regmap_read(priv->regmap, TIM_CR1, &cr1);
140 	if (!(cr1 & TIM_CR1_CEN))
141 		clk_enable(priv->clk);
142 
143 	regmap_write(priv->regmap, TIM_PSC, prescaler);
144 	regmap_write(priv->regmap, TIM_ARR, prd - 1);
145 	regmap_update_bits(priv->regmap, TIM_CR1, TIM_CR1_ARPE, TIM_CR1_ARPE);
146 
147 	/* Force master mode to update mode */
148 	if (stm32_timer_is_trgo2_name(trig->name))
149 		regmap_update_bits(priv->regmap, TIM_CR2, TIM_CR2_MMS2,
150 				   0x2 << TIM_CR2_MMS2_SHIFT);
151 	else
152 		regmap_update_bits(priv->regmap, TIM_CR2, TIM_CR2_MMS,
153 				   0x2 << TIM_CR2_MMS_SHIFT);
154 
155 	/* Make sure that registers are updated */
156 	regmap_update_bits(priv->regmap, TIM_EGR, TIM_EGR_UG, TIM_EGR_UG);
157 
158 	/* Enable controller */
159 	regmap_update_bits(priv->regmap, TIM_CR1, TIM_CR1_CEN, TIM_CR1_CEN);
160 
161 	return 0;
162 }
163 
164 static void stm32_timer_stop(struct stm32_timer_trigger *priv,
165 			     struct iio_trigger *trig)
166 {
167 	u32 ccer, cr1;
168 
169 	regmap_read(priv->regmap, TIM_CCER, &ccer);
170 	if (ccer & TIM_CCER_CCXE)
171 		return;
172 
173 	regmap_read(priv->regmap, TIM_CR1, &cr1);
174 	if (cr1 & TIM_CR1_CEN)
175 		clk_disable(priv->clk);
176 
177 	/* Stop timer */
178 	regmap_update_bits(priv->regmap, TIM_CR1, TIM_CR1_ARPE, 0);
179 	regmap_update_bits(priv->regmap, TIM_CR1, TIM_CR1_CEN, 0);
180 	regmap_write(priv->regmap, TIM_PSC, 0);
181 	regmap_write(priv->regmap, TIM_ARR, 0);
182 
183 	/* Force disable master mode */
184 	if (stm32_timer_is_trgo2_name(trig->name))
185 		regmap_update_bits(priv->regmap, TIM_CR2, TIM_CR2_MMS2, 0);
186 	else
187 		regmap_update_bits(priv->regmap, TIM_CR2, TIM_CR2_MMS, 0);
188 
189 	/* Make sure that registers are updated */
190 	regmap_update_bits(priv->regmap, TIM_EGR, TIM_EGR_UG, TIM_EGR_UG);
191 }
192 
193 static ssize_t stm32_tt_store_frequency(struct device *dev,
194 					struct device_attribute *attr,
195 					const char *buf, size_t len)
196 {
197 	struct iio_trigger *trig = to_iio_trigger(dev);
198 	struct stm32_timer_trigger *priv = iio_trigger_get_drvdata(trig);
199 	unsigned int freq;
200 	int ret;
201 
202 	ret = kstrtouint(buf, 10, &freq);
203 	if (ret)
204 		return ret;
205 
206 	if (freq == 0) {
207 		stm32_timer_stop(priv, trig);
208 	} else {
209 		ret = stm32_timer_start(priv, trig, freq);
210 		if (ret)
211 			return ret;
212 	}
213 
214 	return len;
215 }
216 
217 static ssize_t stm32_tt_read_frequency(struct device *dev,
218 				       struct device_attribute *attr, char *buf)
219 {
220 	struct iio_trigger *trig = to_iio_trigger(dev);
221 	struct stm32_timer_trigger *priv = iio_trigger_get_drvdata(trig);
222 	u32 psc, arr, cr1;
223 	unsigned long long freq = 0;
224 
225 	regmap_read(priv->regmap, TIM_CR1, &cr1);
226 	regmap_read(priv->regmap, TIM_PSC, &psc);
227 	regmap_read(priv->regmap, TIM_ARR, &arr);
228 
229 	if (cr1 & TIM_CR1_CEN) {
230 		freq = (unsigned long long)clk_get_rate(priv->clk);
231 		do_div(freq, psc + 1);
232 		do_div(freq, arr + 1);
233 	}
234 
235 	return sprintf(buf, "%d\n", (unsigned int)freq);
236 }
237 
238 static IIO_DEV_ATTR_SAMP_FREQ(0660,
239 			      stm32_tt_read_frequency,
240 			      stm32_tt_store_frequency);
241 
242 #define MASTER_MODE_MAX		7
243 #define MASTER_MODE2_MAX	15
244 
245 static char *master_mode_table[] = {
246 	"reset",
247 	"enable",
248 	"update",
249 	"compare_pulse",
250 	"OC1REF",
251 	"OC2REF",
252 	"OC3REF",
253 	"OC4REF",
254 	/* Master mode selection 2 only */
255 	"OC5REF",
256 	"OC6REF",
257 	"compare_pulse_OC4REF",
258 	"compare_pulse_OC6REF",
259 	"compare_pulse_OC4REF_r_or_OC6REF_r",
260 	"compare_pulse_OC4REF_r_or_OC6REF_f",
261 	"compare_pulse_OC5REF_r_or_OC6REF_r",
262 	"compare_pulse_OC5REF_r_or_OC6REF_f",
263 };
264 
265 static ssize_t stm32_tt_show_master_mode(struct device *dev,
266 					 struct device_attribute *attr,
267 					 char *buf)
268 {
269 	struct stm32_timer_trigger *priv = dev_get_drvdata(dev);
270 	struct iio_trigger *trig = to_iio_trigger(dev);
271 	u32 cr2;
272 
273 	regmap_read(priv->regmap, TIM_CR2, &cr2);
274 
275 	if (stm32_timer_is_trgo2_name(trig->name))
276 		cr2 = (cr2 & TIM_CR2_MMS2) >> TIM_CR2_MMS2_SHIFT;
277 	else
278 		cr2 = (cr2 & TIM_CR2_MMS) >> TIM_CR2_MMS_SHIFT;
279 
280 	return snprintf(buf, PAGE_SIZE, "%s\n", master_mode_table[cr2]);
281 }
282 
283 static ssize_t stm32_tt_store_master_mode(struct device *dev,
284 					  struct device_attribute *attr,
285 					  const char *buf, size_t len)
286 {
287 	struct stm32_timer_trigger *priv = dev_get_drvdata(dev);
288 	struct iio_trigger *trig = to_iio_trigger(dev);
289 	u32 mask, shift, master_mode_max;
290 	int i;
291 
292 	if (stm32_timer_is_trgo2_name(trig->name)) {
293 		mask = TIM_CR2_MMS2;
294 		shift = TIM_CR2_MMS2_SHIFT;
295 		master_mode_max = MASTER_MODE2_MAX;
296 	} else {
297 		mask = TIM_CR2_MMS;
298 		shift = TIM_CR2_MMS_SHIFT;
299 		master_mode_max = MASTER_MODE_MAX;
300 	}
301 
302 	for (i = 0; i <= master_mode_max; i++) {
303 		if (!strncmp(master_mode_table[i], buf,
304 			     strlen(master_mode_table[i]))) {
305 			regmap_update_bits(priv->regmap, TIM_CR2, mask,
306 					   i << shift);
307 			return len;
308 		}
309 	}
310 
311 	return -EINVAL;
312 }
313 
314 static ssize_t stm32_tt_show_master_mode_avail(struct device *dev,
315 					       struct device_attribute *attr,
316 					       char *buf)
317 {
318 	struct iio_trigger *trig = to_iio_trigger(dev);
319 	unsigned int i, master_mode_max;
320 	size_t len = 0;
321 
322 	if (stm32_timer_is_trgo2_name(trig->name))
323 		master_mode_max = MASTER_MODE2_MAX;
324 	else
325 		master_mode_max = MASTER_MODE_MAX;
326 
327 	for (i = 0; i <= master_mode_max; i++)
328 		len += scnprintf(buf + len, PAGE_SIZE - len,
329 			"%s ", master_mode_table[i]);
330 
331 	/* replace trailing space by newline */
332 	buf[len - 1] = '\n';
333 
334 	return len;
335 }
336 
337 static IIO_DEVICE_ATTR(master_mode_available, 0444,
338 		       stm32_tt_show_master_mode_avail, NULL, 0);
339 
340 static IIO_DEVICE_ATTR(master_mode, 0660,
341 		       stm32_tt_show_master_mode,
342 		       stm32_tt_store_master_mode,
343 		       0);
344 
345 static struct attribute *stm32_trigger_attrs[] = {
346 	&iio_dev_attr_sampling_frequency.dev_attr.attr,
347 	&iio_dev_attr_master_mode.dev_attr.attr,
348 	&iio_dev_attr_master_mode_available.dev_attr.attr,
349 	NULL,
350 };
351 
352 static const struct attribute_group stm32_trigger_attr_group = {
353 	.attrs = stm32_trigger_attrs,
354 };
355 
356 static const struct attribute_group *stm32_trigger_attr_groups[] = {
357 	&stm32_trigger_attr_group,
358 	NULL,
359 };
360 
361 static const struct iio_trigger_ops timer_trigger_ops = {
362 };
363 
364 static int stm32_setup_iio_triggers(struct stm32_timer_trigger *priv)
365 {
366 	int ret;
367 	const char * const *cur = priv->triggers;
368 
369 	while (cur && *cur) {
370 		struct iio_trigger *trig;
371 		bool cur_is_trgo = stm32_timer_is_trgo_name(*cur);
372 		bool cur_is_trgo2 = stm32_timer_is_trgo2_name(*cur);
373 
374 		if (cur_is_trgo2 && !priv->has_trgo2) {
375 			cur++;
376 			continue;
377 		}
378 
379 		trig = devm_iio_trigger_alloc(priv->dev, "%s", *cur);
380 		if  (!trig)
381 			return -ENOMEM;
382 
383 		trig->dev.parent = priv->dev->parent;
384 		trig->ops = &timer_trigger_ops;
385 
386 		/*
387 		 * sampling frequency and master mode attributes
388 		 * should only be available on trgo/trgo2 triggers
389 		 */
390 		if (cur_is_trgo || cur_is_trgo2)
391 			trig->dev.groups = stm32_trigger_attr_groups;
392 
393 		iio_trigger_set_drvdata(trig, priv);
394 
395 		ret = devm_iio_trigger_register(priv->dev, trig);
396 		if (ret)
397 			return ret;
398 		cur++;
399 	}
400 
401 	return 0;
402 }
403 
404 static int stm32_counter_read_raw(struct iio_dev *indio_dev,
405 				  struct iio_chan_spec const *chan,
406 				  int *val, int *val2, long mask)
407 {
408 	struct stm32_timer_trigger *priv = iio_priv(indio_dev);
409 	u32 dat;
410 
411 	switch (mask) {
412 	case IIO_CHAN_INFO_RAW:
413 		regmap_read(priv->regmap, TIM_CNT, &dat);
414 		*val = dat;
415 		return IIO_VAL_INT;
416 
417 	case IIO_CHAN_INFO_ENABLE:
418 		regmap_read(priv->regmap, TIM_CR1, &dat);
419 		*val = (dat & TIM_CR1_CEN) ? 1 : 0;
420 		return IIO_VAL_INT;
421 
422 	case IIO_CHAN_INFO_SCALE:
423 		regmap_read(priv->regmap, TIM_SMCR, &dat);
424 		dat &= TIM_SMCR_SMS;
425 
426 		*val = 1;
427 		*val2 = 0;
428 
429 		/* in quadrature case scale = 0.25 */
430 		if (dat == 3)
431 			*val2 = 2;
432 
433 		return IIO_VAL_FRACTIONAL_LOG2;
434 	}
435 
436 	return -EINVAL;
437 }
438 
439 static int stm32_counter_write_raw(struct iio_dev *indio_dev,
440 				   struct iio_chan_spec const *chan,
441 				   int val, int val2, long mask)
442 {
443 	struct stm32_timer_trigger *priv = iio_priv(indio_dev);
444 	u32 dat;
445 
446 	switch (mask) {
447 	case IIO_CHAN_INFO_RAW:
448 		return regmap_write(priv->regmap, TIM_CNT, val);
449 
450 	case IIO_CHAN_INFO_SCALE:
451 		/* fixed scale */
452 		return -EINVAL;
453 
454 	case IIO_CHAN_INFO_ENABLE:
455 		if (val) {
456 			regmap_read(priv->regmap, TIM_CR1, &dat);
457 			if (!(dat & TIM_CR1_CEN))
458 				clk_enable(priv->clk);
459 			regmap_update_bits(priv->regmap, TIM_CR1, TIM_CR1_CEN,
460 					   TIM_CR1_CEN);
461 		} else {
462 			regmap_read(priv->regmap, TIM_CR1, &dat);
463 			regmap_update_bits(priv->regmap, TIM_CR1, TIM_CR1_CEN,
464 					   0);
465 			if (dat & TIM_CR1_CEN)
466 				clk_disable(priv->clk);
467 		}
468 		return 0;
469 	}
470 
471 	return -EINVAL;
472 }
473 
474 static int stm32_counter_validate_trigger(struct iio_dev *indio_dev,
475 					  struct iio_trigger *trig)
476 {
477 	struct stm32_timer_trigger *priv = iio_priv(indio_dev);
478 	const char * const *cur = priv->valids;
479 	unsigned int i = 0;
480 
481 	if (!is_stm32_timer_trigger(trig))
482 		return -EINVAL;
483 
484 	while (cur && *cur) {
485 		if (!strncmp(trig->name, *cur, strlen(trig->name))) {
486 			regmap_update_bits(priv->regmap,
487 					   TIM_SMCR, TIM_SMCR_TS,
488 					   i << TIM_SMCR_TS_SHIFT);
489 			return 0;
490 		}
491 		cur++;
492 		i++;
493 	}
494 
495 	return -EINVAL;
496 }
497 
498 static const struct iio_info stm32_trigger_info = {
499 	.validate_trigger = stm32_counter_validate_trigger,
500 	.read_raw = stm32_counter_read_raw,
501 	.write_raw = stm32_counter_write_raw
502 };
503 
504 static const char *const stm32_trigger_modes[] = {
505 	"trigger",
506 };
507 
508 static int stm32_set_trigger_mode(struct iio_dev *indio_dev,
509 				  const struct iio_chan_spec *chan,
510 				  unsigned int mode)
511 {
512 	struct stm32_timer_trigger *priv = iio_priv(indio_dev);
513 
514 	regmap_update_bits(priv->regmap, TIM_SMCR, TIM_SMCR_SMS, TIM_SMCR_SMS);
515 
516 	return 0;
517 }
518 
519 static int stm32_get_trigger_mode(struct iio_dev *indio_dev,
520 				  const struct iio_chan_spec *chan)
521 {
522 	struct stm32_timer_trigger *priv = iio_priv(indio_dev);
523 	u32 smcr;
524 
525 	regmap_read(priv->regmap, TIM_SMCR, &smcr);
526 
527 	return (smcr & TIM_SMCR_SMS) == TIM_SMCR_SMS ? 0 : -EINVAL;
528 }
529 
530 static const struct iio_enum stm32_trigger_mode_enum = {
531 	.items = stm32_trigger_modes,
532 	.num_items = ARRAY_SIZE(stm32_trigger_modes),
533 	.set = stm32_set_trigger_mode,
534 	.get = stm32_get_trigger_mode
535 };
536 
537 static const char *const stm32_enable_modes[] = {
538 	"always",
539 	"gated",
540 	"triggered",
541 };
542 
543 static int stm32_enable_mode2sms(int mode)
544 {
545 	switch (mode) {
546 	case 0:
547 		return 0;
548 	case 1:
549 		return 5;
550 	case 2:
551 		return 6;
552 	}
553 
554 	return -EINVAL;
555 }
556 
557 static int stm32_set_enable_mode(struct iio_dev *indio_dev,
558 				 const struct iio_chan_spec *chan,
559 				 unsigned int mode)
560 {
561 	struct stm32_timer_trigger *priv = iio_priv(indio_dev);
562 	int sms = stm32_enable_mode2sms(mode);
563 	u32 val;
564 
565 	if (sms < 0)
566 		return sms;
567 	/*
568 	 * Triggered mode sets CEN bit automatically by hardware. So, first
569 	 * enable counter clock, so it can use it. Keeps it in sync with CEN.
570 	 */
571 	if (sms == 6) {
572 		regmap_read(priv->regmap, TIM_CR1, &val);
573 		if (!(val & TIM_CR1_CEN))
574 			clk_enable(priv->clk);
575 	}
576 
577 	regmap_update_bits(priv->regmap, TIM_SMCR, TIM_SMCR_SMS, sms);
578 
579 	return 0;
580 }
581 
582 static int stm32_sms2enable_mode(int mode)
583 {
584 	switch (mode) {
585 	case 0:
586 		return 0;
587 	case 5:
588 		return 1;
589 	case 6:
590 		return 2;
591 	}
592 
593 	return -EINVAL;
594 }
595 
596 static int stm32_get_enable_mode(struct iio_dev *indio_dev,
597 				 const struct iio_chan_spec *chan)
598 {
599 	struct stm32_timer_trigger *priv = iio_priv(indio_dev);
600 	u32 smcr;
601 
602 	regmap_read(priv->regmap, TIM_SMCR, &smcr);
603 	smcr &= TIM_SMCR_SMS;
604 
605 	return stm32_sms2enable_mode(smcr);
606 }
607 
608 static const struct iio_enum stm32_enable_mode_enum = {
609 	.items = stm32_enable_modes,
610 	.num_items = ARRAY_SIZE(stm32_enable_modes),
611 	.set = stm32_set_enable_mode,
612 	.get = stm32_get_enable_mode
613 };
614 
615 static ssize_t stm32_count_get_preset(struct iio_dev *indio_dev,
616 				      uintptr_t private,
617 				      const struct iio_chan_spec *chan,
618 				      char *buf)
619 {
620 	struct stm32_timer_trigger *priv = iio_priv(indio_dev);
621 	u32 arr;
622 
623 	regmap_read(priv->regmap, TIM_ARR, &arr);
624 
625 	return snprintf(buf, PAGE_SIZE, "%u\n", arr);
626 }
627 
628 static ssize_t stm32_count_set_preset(struct iio_dev *indio_dev,
629 				      uintptr_t private,
630 				      const struct iio_chan_spec *chan,
631 				      const char *buf, size_t len)
632 {
633 	struct stm32_timer_trigger *priv = iio_priv(indio_dev);
634 	unsigned int preset;
635 	int ret;
636 
637 	ret = kstrtouint(buf, 0, &preset);
638 	if (ret)
639 		return ret;
640 
641 	/* TIMx_ARR register shouldn't be buffered (ARPE=0) */
642 	regmap_update_bits(priv->regmap, TIM_CR1, TIM_CR1_ARPE, 0);
643 	regmap_write(priv->regmap, TIM_ARR, preset);
644 
645 	return len;
646 }
647 
648 static const struct iio_chan_spec_ext_info stm32_trigger_count_info[] = {
649 	{
650 		.name = "preset",
651 		.shared = IIO_SEPARATE,
652 		.read = stm32_count_get_preset,
653 		.write = stm32_count_set_preset
654 	},
655 	IIO_ENUM("enable_mode", IIO_SEPARATE, &stm32_enable_mode_enum),
656 	IIO_ENUM_AVAILABLE("enable_mode", &stm32_enable_mode_enum),
657 	IIO_ENUM("trigger_mode", IIO_SEPARATE, &stm32_trigger_mode_enum),
658 	IIO_ENUM_AVAILABLE("trigger_mode", &stm32_trigger_mode_enum),
659 	{}
660 };
661 
662 static const struct iio_chan_spec stm32_trigger_channel = {
663 	.type = IIO_COUNT,
664 	.channel = 0,
665 	.info_mask_separate = BIT(IIO_CHAN_INFO_RAW) |
666 			      BIT(IIO_CHAN_INFO_ENABLE) |
667 			      BIT(IIO_CHAN_INFO_SCALE),
668 	.ext_info = stm32_trigger_count_info,
669 	.indexed = 1
670 };
671 
672 static struct stm32_timer_trigger *stm32_setup_counter_device(struct device *dev)
673 {
674 	struct iio_dev *indio_dev;
675 	int ret;
676 
677 	indio_dev = devm_iio_device_alloc(dev,
678 					  sizeof(struct stm32_timer_trigger));
679 	if (!indio_dev)
680 		return NULL;
681 
682 	indio_dev->name = dev_name(dev);
683 	indio_dev->dev.parent = dev;
684 	indio_dev->info = &stm32_trigger_info;
685 	indio_dev->modes = INDIO_HARDWARE_TRIGGERED;
686 	indio_dev->num_channels = 1;
687 	indio_dev->channels = &stm32_trigger_channel;
688 	indio_dev->dev.of_node = dev->of_node;
689 
690 	ret = devm_iio_device_register(dev, indio_dev);
691 	if (ret)
692 		return NULL;
693 
694 	return iio_priv(indio_dev);
695 }
696 
697 /**
698  * is_stm32_timer_trigger
699  * @trig: trigger to be checked
700  *
701  * return true if the trigger is a valid stm32 iio timer trigger
702  * either return false
703  */
704 bool is_stm32_timer_trigger(struct iio_trigger *trig)
705 {
706 	return (trig->ops == &timer_trigger_ops);
707 }
708 EXPORT_SYMBOL(is_stm32_timer_trigger);
709 
710 static void stm32_timer_detect_trgo2(struct stm32_timer_trigger *priv)
711 {
712 	u32 val;
713 
714 	/*
715 	 * Master mode selection 2 bits can only be written and read back when
716 	 * timer supports it.
717 	 */
718 	regmap_update_bits(priv->regmap, TIM_CR2, TIM_CR2_MMS2, TIM_CR2_MMS2);
719 	regmap_read(priv->regmap, TIM_CR2, &val);
720 	regmap_update_bits(priv->regmap, TIM_CR2, TIM_CR2_MMS2, 0);
721 	priv->has_trgo2 = !!val;
722 }
723 
724 static int stm32_timer_trigger_probe(struct platform_device *pdev)
725 {
726 	struct device *dev = &pdev->dev;
727 	struct stm32_timer_trigger *priv;
728 	struct stm32_timers *ddata = dev_get_drvdata(pdev->dev.parent);
729 	const struct stm32_timer_trigger_cfg *cfg;
730 	unsigned int index;
731 	int ret;
732 
733 	if (of_property_read_u32(dev->of_node, "reg", &index))
734 		return -EINVAL;
735 
736 	cfg = (const struct stm32_timer_trigger_cfg *)
737 		of_match_device(dev->driver->of_match_table, dev)->data;
738 
739 	if (index >= ARRAY_SIZE(triggers_table) ||
740 	    index >= cfg->num_valids_table)
741 		return -EINVAL;
742 
743 	/* Create an IIO device only if we have triggers to be validated */
744 	if (*cfg->valids_table[index])
745 		priv = stm32_setup_counter_device(dev);
746 	else
747 		priv = devm_kzalloc(dev, sizeof(*priv), GFP_KERNEL);
748 
749 	if (!priv)
750 		return -ENOMEM;
751 
752 	priv->dev = dev;
753 	priv->regmap = ddata->regmap;
754 	priv->clk = ddata->clk;
755 	priv->max_arr = ddata->max_arr;
756 	priv->triggers = triggers_table[index];
757 	priv->valids = cfg->valids_table[index];
758 	stm32_timer_detect_trgo2(priv);
759 
760 	ret = stm32_setup_iio_triggers(priv);
761 	if (ret)
762 		return ret;
763 
764 	platform_set_drvdata(pdev, priv);
765 
766 	return 0;
767 }
768 
769 static const struct stm32_timer_trigger_cfg stm32_timer_trg_cfg = {
770 	.valids_table = valids_table,
771 	.num_valids_table = ARRAY_SIZE(valids_table),
772 };
773 
774 static const struct stm32_timer_trigger_cfg stm32h7_timer_trg_cfg = {
775 	.valids_table = stm32h7_valids_table,
776 	.num_valids_table = ARRAY_SIZE(stm32h7_valids_table),
777 };
778 
779 static const struct of_device_id stm32_trig_of_match[] = {
780 	{
781 		.compatible = "st,stm32-timer-trigger",
782 		.data = (void *)&stm32_timer_trg_cfg,
783 	}, {
784 		.compatible = "st,stm32h7-timer-trigger",
785 		.data = (void *)&stm32h7_timer_trg_cfg,
786 	},
787 	{ /* end node */ },
788 };
789 MODULE_DEVICE_TABLE(of, stm32_trig_of_match);
790 
791 static struct platform_driver stm32_timer_trigger_driver = {
792 	.probe = stm32_timer_trigger_probe,
793 	.driver = {
794 		.name = "stm32-timer-trigger",
795 		.of_match_table = stm32_trig_of_match,
796 	},
797 };
798 module_platform_driver(stm32_timer_trigger_driver);
799 
800 MODULE_ALIAS("platform: stm32-timer-trigger");
801 MODULE_DESCRIPTION("STMicroelectronics STM32 Timer Trigger driver");
802 MODULE_LICENSE("GPL v2");
803