1 /* 2 * Copyright (C) STMicroelectronics 2016 3 * 4 * Author: Benjamin Gaignard <benjamin.gaignard@st.com> 5 * 6 * License terms: GNU General Public License (GPL), version 2 7 */ 8 9 #include <linux/iio/iio.h> 10 #include <linux/iio/sysfs.h> 11 #include <linux/iio/timer/stm32-timer-trigger.h> 12 #include <linux/iio/trigger.h> 13 #include <linux/mfd/stm32-timers.h> 14 #include <linux/module.h> 15 #include <linux/platform_device.h> 16 17 #define MAX_TRIGGERS 7 18 #define MAX_VALIDS 5 19 20 /* List the triggers created by each timer */ 21 static const void *triggers_table[][MAX_TRIGGERS] = { 22 { TIM1_TRGO, TIM1_TRGO2, TIM1_CH1, TIM1_CH2, TIM1_CH3, TIM1_CH4,}, 23 { TIM2_TRGO, TIM2_CH1, TIM2_CH2, TIM2_CH3, TIM2_CH4,}, 24 { TIM3_TRGO, TIM3_CH1, TIM3_CH2, TIM3_CH3, TIM3_CH4,}, 25 { TIM4_TRGO, TIM4_CH1, TIM4_CH2, TIM4_CH3, TIM4_CH4,}, 26 { TIM5_TRGO, TIM5_CH1, TIM5_CH2, TIM5_CH3, TIM5_CH4,}, 27 { TIM6_TRGO,}, 28 { TIM7_TRGO,}, 29 { TIM8_TRGO, TIM8_TRGO2, TIM8_CH1, TIM8_CH2, TIM8_CH3, TIM8_CH4,}, 30 { TIM9_TRGO, TIM9_CH1, TIM9_CH2,}, 31 { }, /* timer 10 */ 32 { }, /* timer 11 */ 33 { TIM12_TRGO, TIM12_CH1, TIM12_CH2,}, 34 }; 35 36 /* List the triggers accepted by each timer */ 37 static const void *valids_table[][MAX_VALIDS] = { 38 { TIM5_TRGO, TIM2_TRGO, TIM3_TRGO, TIM4_TRGO,}, 39 { TIM1_TRGO, TIM8_TRGO, TIM3_TRGO, TIM4_TRGO,}, 40 { TIM1_TRGO, TIM2_TRGO, TIM5_TRGO, TIM4_TRGO,}, 41 { TIM1_TRGO, TIM2_TRGO, TIM3_TRGO, TIM8_TRGO,}, 42 { TIM2_TRGO, TIM3_TRGO, TIM4_TRGO, TIM8_TRGO,}, 43 { }, /* timer 6 */ 44 { }, /* timer 7 */ 45 { TIM1_TRGO, TIM2_TRGO, TIM4_TRGO, TIM5_TRGO,}, 46 { TIM2_TRGO, TIM3_TRGO,}, 47 { }, /* timer 10 */ 48 { }, /* timer 11 */ 49 { TIM4_TRGO, TIM5_TRGO,}, 50 }; 51 52 struct stm32_timer_trigger { 53 struct device *dev; 54 struct regmap *regmap; 55 struct clk *clk; 56 u32 max_arr; 57 const void *triggers; 58 const void *valids; 59 bool has_trgo2; 60 }; 61 62 static bool stm32_timer_is_trgo2_name(const char *name) 63 { 64 return !!strstr(name, "trgo2"); 65 } 66 67 static int stm32_timer_start(struct stm32_timer_trigger *priv, 68 struct iio_trigger *trig, 69 unsigned int frequency) 70 { 71 unsigned long long prd, div; 72 int prescaler = 0; 73 u32 ccer, cr1; 74 75 /* Period and prescaler values depends of clock rate */ 76 div = (unsigned long long)clk_get_rate(priv->clk); 77 78 do_div(div, frequency); 79 80 prd = div; 81 82 /* 83 * Increase prescaler value until we get a result that fit 84 * with auto reload register maximum value. 85 */ 86 while (div > priv->max_arr) { 87 prescaler++; 88 div = prd; 89 do_div(div, (prescaler + 1)); 90 } 91 prd = div; 92 93 if (prescaler > MAX_TIM_PSC) { 94 dev_err(priv->dev, "prescaler exceeds the maximum value\n"); 95 return -EINVAL; 96 } 97 98 /* Check if nobody else use the timer */ 99 regmap_read(priv->regmap, TIM_CCER, &ccer); 100 if (ccer & TIM_CCER_CCXE) 101 return -EBUSY; 102 103 regmap_read(priv->regmap, TIM_CR1, &cr1); 104 if (!(cr1 & TIM_CR1_CEN)) 105 clk_enable(priv->clk); 106 107 regmap_write(priv->regmap, TIM_PSC, prescaler); 108 regmap_write(priv->regmap, TIM_ARR, prd - 1); 109 regmap_update_bits(priv->regmap, TIM_CR1, TIM_CR1_ARPE, TIM_CR1_ARPE); 110 111 /* Force master mode to update mode */ 112 if (stm32_timer_is_trgo2_name(trig->name)) 113 regmap_update_bits(priv->regmap, TIM_CR2, TIM_CR2_MMS2, 114 0x2 << TIM_CR2_MMS2_SHIFT); 115 else 116 regmap_update_bits(priv->regmap, TIM_CR2, TIM_CR2_MMS, 117 0x2 << TIM_CR2_MMS_SHIFT); 118 119 /* Make sure that registers are updated */ 120 regmap_update_bits(priv->regmap, TIM_EGR, TIM_EGR_UG, TIM_EGR_UG); 121 122 /* Enable controller */ 123 regmap_update_bits(priv->regmap, TIM_CR1, TIM_CR1_CEN, TIM_CR1_CEN); 124 125 return 0; 126 } 127 128 static void stm32_timer_stop(struct stm32_timer_trigger *priv) 129 { 130 u32 ccer, cr1; 131 132 regmap_read(priv->regmap, TIM_CCER, &ccer); 133 if (ccer & TIM_CCER_CCXE) 134 return; 135 136 regmap_read(priv->regmap, TIM_CR1, &cr1); 137 if (cr1 & TIM_CR1_CEN) 138 clk_disable(priv->clk); 139 140 /* Stop timer */ 141 regmap_update_bits(priv->regmap, TIM_CR1, TIM_CR1_CEN, 0); 142 regmap_write(priv->regmap, TIM_PSC, 0); 143 regmap_write(priv->regmap, TIM_ARR, 0); 144 145 /* Make sure that registers are updated */ 146 regmap_update_bits(priv->regmap, TIM_EGR, TIM_EGR_UG, TIM_EGR_UG); 147 } 148 149 static ssize_t stm32_tt_store_frequency(struct device *dev, 150 struct device_attribute *attr, 151 const char *buf, size_t len) 152 { 153 struct iio_trigger *trig = to_iio_trigger(dev); 154 struct stm32_timer_trigger *priv = iio_trigger_get_drvdata(trig); 155 unsigned int freq; 156 int ret; 157 158 ret = kstrtouint(buf, 10, &freq); 159 if (ret) 160 return ret; 161 162 if (freq == 0) { 163 stm32_timer_stop(priv); 164 } else { 165 ret = stm32_timer_start(priv, trig, freq); 166 if (ret) 167 return ret; 168 } 169 170 return len; 171 } 172 173 static ssize_t stm32_tt_read_frequency(struct device *dev, 174 struct device_attribute *attr, char *buf) 175 { 176 struct iio_trigger *trig = to_iio_trigger(dev); 177 struct stm32_timer_trigger *priv = iio_trigger_get_drvdata(trig); 178 u32 psc, arr, cr1; 179 unsigned long long freq = 0; 180 181 regmap_read(priv->regmap, TIM_CR1, &cr1); 182 regmap_read(priv->regmap, TIM_PSC, &psc); 183 regmap_read(priv->regmap, TIM_ARR, &arr); 184 185 if (cr1 & TIM_CR1_CEN) { 186 freq = (unsigned long long)clk_get_rate(priv->clk); 187 do_div(freq, psc + 1); 188 do_div(freq, arr + 1); 189 } 190 191 return sprintf(buf, "%d\n", (unsigned int)freq); 192 } 193 194 static IIO_DEV_ATTR_SAMP_FREQ(0660, 195 stm32_tt_read_frequency, 196 stm32_tt_store_frequency); 197 198 #define MASTER_MODE_MAX 7 199 #define MASTER_MODE2_MAX 15 200 201 static char *master_mode_table[] = { 202 "reset", 203 "enable", 204 "update", 205 "compare_pulse", 206 "OC1REF", 207 "OC2REF", 208 "OC3REF", 209 "OC4REF", 210 /* Master mode selection 2 only */ 211 "OC5REF", 212 "OC6REF", 213 "compare_pulse_OC4REF", 214 "compare_pulse_OC6REF", 215 "compare_pulse_OC4REF_r_or_OC6REF_r", 216 "compare_pulse_OC4REF_r_or_OC6REF_f", 217 "compare_pulse_OC5REF_r_or_OC6REF_r", 218 "compare_pulse_OC5REF_r_or_OC6REF_f", 219 }; 220 221 static ssize_t stm32_tt_show_master_mode(struct device *dev, 222 struct device_attribute *attr, 223 char *buf) 224 { 225 struct stm32_timer_trigger *priv = dev_get_drvdata(dev); 226 struct iio_trigger *trig = to_iio_trigger(dev); 227 u32 cr2; 228 229 regmap_read(priv->regmap, TIM_CR2, &cr2); 230 231 if (stm32_timer_is_trgo2_name(trig->name)) 232 cr2 = (cr2 & TIM_CR2_MMS2) >> TIM_CR2_MMS2_SHIFT; 233 else 234 cr2 = (cr2 & TIM_CR2_MMS) >> TIM_CR2_MMS_SHIFT; 235 236 return snprintf(buf, PAGE_SIZE, "%s\n", master_mode_table[cr2]); 237 } 238 239 static ssize_t stm32_tt_store_master_mode(struct device *dev, 240 struct device_attribute *attr, 241 const char *buf, size_t len) 242 { 243 struct stm32_timer_trigger *priv = dev_get_drvdata(dev); 244 struct iio_trigger *trig = to_iio_trigger(dev); 245 u32 mask, shift, master_mode_max; 246 int i; 247 248 if (stm32_timer_is_trgo2_name(trig->name)) { 249 mask = TIM_CR2_MMS2; 250 shift = TIM_CR2_MMS2_SHIFT; 251 master_mode_max = MASTER_MODE2_MAX; 252 } else { 253 mask = TIM_CR2_MMS; 254 shift = TIM_CR2_MMS_SHIFT; 255 master_mode_max = MASTER_MODE_MAX; 256 } 257 258 for (i = 0; i <= master_mode_max; i++) { 259 if (!strncmp(master_mode_table[i], buf, 260 strlen(master_mode_table[i]))) { 261 regmap_update_bits(priv->regmap, TIM_CR2, mask, 262 i << shift); 263 /* Make sure that registers are updated */ 264 regmap_update_bits(priv->regmap, TIM_EGR, 265 TIM_EGR_UG, TIM_EGR_UG); 266 return len; 267 } 268 } 269 270 return -EINVAL; 271 } 272 273 static ssize_t stm32_tt_show_master_mode_avail(struct device *dev, 274 struct device_attribute *attr, 275 char *buf) 276 { 277 struct iio_trigger *trig = to_iio_trigger(dev); 278 unsigned int i, master_mode_max; 279 size_t len = 0; 280 281 if (stm32_timer_is_trgo2_name(trig->name)) 282 master_mode_max = MASTER_MODE2_MAX; 283 else 284 master_mode_max = MASTER_MODE_MAX; 285 286 for (i = 0; i <= master_mode_max; i++) 287 len += scnprintf(buf + len, PAGE_SIZE - len, 288 "%s ", master_mode_table[i]); 289 290 /* replace trailing space by newline */ 291 buf[len - 1] = '\n'; 292 293 return len; 294 } 295 296 static IIO_DEVICE_ATTR(master_mode_available, 0444, 297 stm32_tt_show_master_mode_avail, NULL, 0); 298 299 static IIO_DEVICE_ATTR(master_mode, 0660, 300 stm32_tt_show_master_mode, 301 stm32_tt_store_master_mode, 302 0); 303 304 static struct attribute *stm32_trigger_attrs[] = { 305 &iio_dev_attr_sampling_frequency.dev_attr.attr, 306 &iio_dev_attr_master_mode.dev_attr.attr, 307 &iio_dev_attr_master_mode_available.dev_attr.attr, 308 NULL, 309 }; 310 311 static const struct attribute_group stm32_trigger_attr_group = { 312 .attrs = stm32_trigger_attrs, 313 }; 314 315 static const struct attribute_group *stm32_trigger_attr_groups[] = { 316 &stm32_trigger_attr_group, 317 NULL, 318 }; 319 320 static const struct iio_trigger_ops timer_trigger_ops = { 321 .owner = THIS_MODULE, 322 }; 323 324 static int stm32_setup_iio_triggers(struct stm32_timer_trigger *priv) 325 { 326 int ret; 327 const char * const *cur = priv->triggers; 328 329 while (cur && *cur) { 330 struct iio_trigger *trig; 331 bool cur_is_trgo2 = stm32_timer_is_trgo2_name(*cur); 332 333 if (cur_is_trgo2 && !priv->has_trgo2) { 334 cur++; 335 continue; 336 } 337 338 trig = devm_iio_trigger_alloc(priv->dev, "%s", *cur); 339 if (!trig) 340 return -ENOMEM; 341 342 trig->dev.parent = priv->dev->parent; 343 trig->ops = &timer_trigger_ops; 344 345 /* 346 * sampling frequency and master mode attributes 347 * should only be available on trgo trigger which 348 * is always the first in the list. 349 */ 350 if (cur == priv->triggers || cur_is_trgo2) 351 trig->dev.groups = stm32_trigger_attr_groups; 352 353 iio_trigger_set_drvdata(trig, priv); 354 355 ret = devm_iio_trigger_register(priv->dev, trig); 356 if (ret) 357 return ret; 358 cur++; 359 } 360 361 return 0; 362 } 363 364 static int stm32_counter_read_raw(struct iio_dev *indio_dev, 365 struct iio_chan_spec const *chan, 366 int *val, int *val2, long mask) 367 { 368 struct stm32_timer_trigger *priv = iio_priv(indio_dev); 369 370 switch (mask) { 371 case IIO_CHAN_INFO_RAW: 372 { 373 u32 cnt; 374 375 regmap_read(priv->regmap, TIM_CNT, &cnt); 376 *val = cnt; 377 378 return IIO_VAL_INT; 379 } 380 case IIO_CHAN_INFO_SCALE: 381 { 382 u32 smcr; 383 384 regmap_read(priv->regmap, TIM_SMCR, &smcr); 385 smcr &= TIM_SMCR_SMS; 386 387 *val = 1; 388 *val2 = 0; 389 390 /* in quadrature case scale = 0.25 */ 391 if (smcr == 3) 392 *val2 = 2; 393 394 return IIO_VAL_FRACTIONAL_LOG2; 395 } 396 } 397 398 return -EINVAL; 399 } 400 401 static int stm32_counter_write_raw(struct iio_dev *indio_dev, 402 struct iio_chan_spec const *chan, 403 int val, int val2, long mask) 404 { 405 struct stm32_timer_trigger *priv = iio_priv(indio_dev); 406 407 switch (mask) { 408 case IIO_CHAN_INFO_RAW: 409 regmap_write(priv->regmap, TIM_CNT, val); 410 411 return IIO_VAL_INT; 412 case IIO_CHAN_INFO_SCALE: 413 /* fixed scale */ 414 return -EINVAL; 415 } 416 417 return -EINVAL; 418 } 419 420 static int stm32_counter_validate_trigger(struct iio_dev *indio_dev, 421 struct iio_trigger *trig) 422 { 423 struct stm32_timer_trigger *priv = iio_priv(indio_dev); 424 const char * const *cur = priv->valids; 425 unsigned int i = 0; 426 427 if (!is_stm32_timer_trigger(trig)) 428 return -EINVAL; 429 430 while (cur && *cur) { 431 if (!strncmp(trig->name, *cur, strlen(trig->name))) { 432 regmap_update_bits(priv->regmap, 433 TIM_SMCR, TIM_SMCR_TS, 434 i << TIM_SMCR_TS_SHIFT); 435 return 0; 436 } 437 cur++; 438 i++; 439 } 440 441 return -EINVAL; 442 } 443 444 static const struct iio_info stm32_trigger_info = { 445 .driver_module = THIS_MODULE, 446 .validate_trigger = stm32_counter_validate_trigger, 447 .read_raw = stm32_counter_read_raw, 448 .write_raw = stm32_counter_write_raw 449 }; 450 451 static const char *const stm32_trigger_modes[] = { 452 "trigger", 453 }; 454 455 static int stm32_set_trigger_mode(struct iio_dev *indio_dev, 456 const struct iio_chan_spec *chan, 457 unsigned int mode) 458 { 459 struct stm32_timer_trigger *priv = iio_priv(indio_dev); 460 461 regmap_update_bits(priv->regmap, TIM_SMCR, TIM_SMCR_SMS, TIM_SMCR_SMS); 462 463 return 0; 464 } 465 466 static int stm32_get_trigger_mode(struct iio_dev *indio_dev, 467 const struct iio_chan_spec *chan) 468 { 469 struct stm32_timer_trigger *priv = iio_priv(indio_dev); 470 u32 smcr; 471 472 regmap_read(priv->regmap, TIM_SMCR, &smcr); 473 474 return smcr == TIM_SMCR_SMS ? 0 : -EINVAL; 475 } 476 477 static const struct iio_enum stm32_trigger_mode_enum = { 478 .items = stm32_trigger_modes, 479 .num_items = ARRAY_SIZE(stm32_trigger_modes), 480 .set = stm32_set_trigger_mode, 481 .get = stm32_get_trigger_mode 482 }; 483 484 static const char *const stm32_enable_modes[] = { 485 "always", 486 "gated", 487 "triggered", 488 }; 489 490 static int stm32_enable_mode2sms(int mode) 491 { 492 switch (mode) { 493 case 0: 494 return 0; 495 case 1: 496 return 5; 497 case 2: 498 return 6; 499 } 500 501 return -EINVAL; 502 } 503 504 static int stm32_set_enable_mode(struct iio_dev *indio_dev, 505 const struct iio_chan_spec *chan, 506 unsigned int mode) 507 { 508 struct stm32_timer_trigger *priv = iio_priv(indio_dev); 509 int sms = stm32_enable_mode2sms(mode); 510 511 if (sms < 0) 512 return sms; 513 514 regmap_update_bits(priv->regmap, TIM_SMCR, TIM_SMCR_SMS, sms); 515 516 return 0; 517 } 518 519 static int stm32_sms2enable_mode(int mode) 520 { 521 switch (mode) { 522 case 0: 523 return 0; 524 case 5: 525 return 1; 526 case 6: 527 return 2; 528 } 529 530 return -EINVAL; 531 } 532 533 static int stm32_get_enable_mode(struct iio_dev *indio_dev, 534 const struct iio_chan_spec *chan) 535 { 536 struct stm32_timer_trigger *priv = iio_priv(indio_dev); 537 u32 smcr; 538 539 regmap_read(priv->regmap, TIM_SMCR, &smcr); 540 smcr &= TIM_SMCR_SMS; 541 542 return stm32_sms2enable_mode(smcr); 543 } 544 545 static const struct iio_enum stm32_enable_mode_enum = { 546 .items = stm32_enable_modes, 547 .num_items = ARRAY_SIZE(stm32_enable_modes), 548 .set = stm32_set_enable_mode, 549 .get = stm32_get_enable_mode 550 }; 551 552 static const char *const stm32_quadrature_modes[] = { 553 "channel_A", 554 "channel_B", 555 "quadrature", 556 }; 557 558 static int stm32_set_quadrature_mode(struct iio_dev *indio_dev, 559 const struct iio_chan_spec *chan, 560 unsigned int mode) 561 { 562 struct stm32_timer_trigger *priv = iio_priv(indio_dev); 563 564 regmap_update_bits(priv->regmap, TIM_SMCR, TIM_SMCR_SMS, mode + 1); 565 566 return 0; 567 } 568 569 static int stm32_get_quadrature_mode(struct iio_dev *indio_dev, 570 const struct iio_chan_spec *chan) 571 { 572 struct stm32_timer_trigger *priv = iio_priv(indio_dev); 573 u32 smcr; 574 575 regmap_read(priv->regmap, TIM_SMCR, &smcr); 576 smcr &= TIM_SMCR_SMS; 577 578 return smcr - 1; 579 } 580 581 static const struct iio_enum stm32_quadrature_mode_enum = { 582 .items = stm32_quadrature_modes, 583 .num_items = ARRAY_SIZE(stm32_quadrature_modes), 584 .set = stm32_set_quadrature_mode, 585 .get = stm32_get_quadrature_mode 586 }; 587 588 static const char *const stm32_count_direction_states[] = { 589 "up", 590 "down" 591 }; 592 593 static int stm32_set_count_direction(struct iio_dev *indio_dev, 594 const struct iio_chan_spec *chan, 595 unsigned int mode) 596 { 597 struct stm32_timer_trigger *priv = iio_priv(indio_dev); 598 599 regmap_update_bits(priv->regmap, TIM_CR1, TIM_CR1_DIR, mode); 600 601 return 0; 602 } 603 604 static int stm32_get_count_direction(struct iio_dev *indio_dev, 605 const struct iio_chan_spec *chan) 606 { 607 struct stm32_timer_trigger *priv = iio_priv(indio_dev); 608 u32 cr1; 609 610 regmap_read(priv->regmap, TIM_CR1, &cr1); 611 612 return (cr1 & TIM_CR1_DIR); 613 } 614 615 static const struct iio_enum stm32_count_direction_enum = { 616 .items = stm32_count_direction_states, 617 .num_items = ARRAY_SIZE(stm32_count_direction_states), 618 .set = stm32_set_count_direction, 619 .get = stm32_get_count_direction 620 }; 621 622 static ssize_t stm32_count_get_preset(struct iio_dev *indio_dev, 623 uintptr_t private, 624 const struct iio_chan_spec *chan, 625 char *buf) 626 { 627 struct stm32_timer_trigger *priv = iio_priv(indio_dev); 628 u32 arr; 629 630 regmap_read(priv->regmap, TIM_ARR, &arr); 631 632 return snprintf(buf, PAGE_SIZE, "%u\n", arr); 633 } 634 635 static ssize_t stm32_count_set_preset(struct iio_dev *indio_dev, 636 uintptr_t private, 637 const struct iio_chan_spec *chan, 638 const char *buf, size_t len) 639 { 640 struct stm32_timer_trigger *priv = iio_priv(indio_dev); 641 unsigned int preset; 642 int ret; 643 644 ret = kstrtouint(buf, 0, &preset); 645 if (ret) 646 return ret; 647 648 regmap_write(priv->regmap, TIM_ARR, preset); 649 regmap_update_bits(priv->regmap, TIM_CR1, TIM_CR1_ARPE, TIM_CR1_ARPE); 650 651 return len; 652 } 653 654 static const struct iio_chan_spec_ext_info stm32_trigger_count_info[] = { 655 { 656 .name = "preset", 657 .shared = IIO_SEPARATE, 658 .read = stm32_count_get_preset, 659 .write = stm32_count_set_preset 660 }, 661 IIO_ENUM("count_direction", IIO_SEPARATE, &stm32_count_direction_enum), 662 IIO_ENUM_AVAILABLE("count_direction", &stm32_count_direction_enum), 663 IIO_ENUM("quadrature_mode", IIO_SEPARATE, &stm32_quadrature_mode_enum), 664 IIO_ENUM_AVAILABLE("quadrature_mode", &stm32_quadrature_mode_enum), 665 IIO_ENUM("enable_mode", IIO_SEPARATE, &stm32_enable_mode_enum), 666 IIO_ENUM_AVAILABLE("enable_mode", &stm32_enable_mode_enum), 667 IIO_ENUM("trigger_mode", IIO_SEPARATE, &stm32_trigger_mode_enum), 668 IIO_ENUM_AVAILABLE("trigger_mode", &stm32_trigger_mode_enum), 669 {} 670 }; 671 672 static const struct iio_chan_spec stm32_trigger_channel = { 673 .type = IIO_COUNT, 674 .channel = 0, 675 .info_mask_separate = BIT(IIO_CHAN_INFO_RAW) | BIT(IIO_CHAN_INFO_SCALE), 676 .ext_info = stm32_trigger_count_info, 677 .indexed = 1 678 }; 679 680 static struct stm32_timer_trigger *stm32_setup_counter_device(struct device *dev) 681 { 682 struct iio_dev *indio_dev; 683 int ret; 684 685 indio_dev = devm_iio_device_alloc(dev, 686 sizeof(struct stm32_timer_trigger)); 687 if (!indio_dev) 688 return NULL; 689 690 indio_dev->name = dev_name(dev); 691 indio_dev->dev.parent = dev; 692 indio_dev->info = &stm32_trigger_info; 693 indio_dev->modes = INDIO_HARDWARE_TRIGGERED; 694 indio_dev->num_channels = 1; 695 indio_dev->channels = &stm32_trigger_channel; 696 indio_dev->dev.of_node = dev->of_node; 697 698 ret = devm_iio_device_register(dev, indio_dev); 699 if (ret) 700 return NULL; 701 702 return iio_priv(indio_dev); 703 } 704 705 /** 706 * is_stm32_timer_trigger 707 * @trig: trigger to be checked 708 * 709 * return true if the trigger is a valid stm32 iio timer trigger 710 * either return false 711 */ 712 bool is_stm32_timer_trigger(struct iio_trigger *trig) 713 { 714 return (trig->ops == &timer_trigger_ops); 715 } 716 EXPORT_SYMBOL(is_stm32_timer_trigger); 717 718 static void stm32_timer_detect_trgo2(struct stm32_timer_trigger *priv) 719 { 720 u32 val; 721 722 /* 723 * Master mode selection 2 bits can only be written and read back when 724 * timer supports it. 725 */ 726 regmap_update_bits(priv->regmap, TIM_CR2, TIM_CR2_MMS2, TIM_CR2_MMS2); 727 regmap_read(priv->regmap, TIM_CR2, &val); 728 regmap_update_bits(priv->regmap, TIM_CR2, TIM_CR2_MMS2, 0); 729 priv->has_trgo2 = !!val; 730 } 731 732 static int stm32_timer_trigger_probe(struct platform_device *pdev) 733 { 734 struct device *dev = &pdev->dev; 735 struct stm32_timer_trigger *priv; 736 struct stm32_timers *ddata = dev_get_drvdata(pdev->dev.parent); 737 unsigned int index; 738 int ret; 739 740 if (of_property_read_u32(dev->of_node, "reg", &index)) 741 return -EINVAL; 742 743 if (index >= ARRAY_SIZE(triggers_table) || 744 index >= ARRAY_SIZE(valids_table)) 745 return -EINVAL; 746 747 /* Create an IIO device only if we have triggers to be validated */ 748 if (*valids_table[index]) 749 priv = stm32_setup_counter_device(dev); 750 else 751 priv = devm_kzalloc(dev, sizeof(*priv), GFP_KERNEL); 752 753 if (!priv) 754 return -ENOMEM; 755 756 priv->dev = dev; 757 priv->regmap = ddata->regmap; 758 priv->clk = ddata->clk; 759 priv->max_arr = ddata->max_arr; 760 priv->triggers = triggers_table[index]; 761 priv->valids = valids_table[index]; 762 stm32_timer_detect_trgo2(priv); 763 764 ret = stm32_setup_iio_triggers(priv); 765 if (ret) 766 return ret; 767 768 platform_set_drvdata(pdev, priv); 769 770 return 0; 771 } 772 773 static const struct of_device_id stm32_trig_of_match[] = { 774 { .compatible = "st,stm32-timer-trigger", }, 775 { /* end node */ }, 776 }; 777 MODULE_DEVICE_TABLE(of, stm32_trig_of_match); 778 779 static struct platform_driver stm32_timer_trigger_driver = { 780 .probe = stm32_timer_trigger_probe, 781 .driver = { 782 .name = "stm32-timer-trigger", 783 .of_match_table = stm32_trig_of_match, 784 }, 785 }; 786 module_platform_driver(stm32_timer_trigger_driver); 787 788 MODULE_ALIAS("platform: stm32-timer-trigger"); 789 MODULE_DESCRIPTION("STMicroelectronics STM32 Timer Trigger driver"); 790 MODULE_LICENSE("GPL v2"); 791