1*e112dc4eSNavin Sankar Velliangiri // SPDX-License-Identifier: GPL-2.0-only 2*e112dc4eSNavin Sankar Velliangiri 3*e112dc4eSNavin Sankar Velliangiri /* 4*e112dc4eSNavin Sankar Velliangiri * Copyright (c) Linumiz 2021 5*e112dc4eSNavin Sankar Velliangiri * 6*e112dc4eSNavin Sankar Velliangiri * max31865.c - Maxim MAX31865 RTD-to-Digital Converter sensor driver 7*e112dc4eSNavin Sankar Velliangiri * 8*e112dc4eSNavin Sankar Velliangiri * Author: Navin Sankar Velliangiri <navin@linumiz.com> 9*e112dc4eSNavin Sankar Velliangiri */ 10*e112dc4eSNavin Sankar Velliangiri 11*e112dc4eSNavin Sankar Velliangiri #include <linux/ctype.h> 12*e112dc4eSNavin Sankar Velliangiri #include <linux/delay.h> 13*e112dc4eSNavin Sankar Velliangiri #include <linux/err.h> 14*e112dc4eSNavin Sankar Velliangiri #include <linux/init.h> 15*e112dc4eSNavin Sankar Velliangiri #include <linux/module.h> 16*e112dc4eSNavin Sankar Velliangiri #include <linux/iio/iio.h> 17*e112dc4eSNavin Sankar Velliangiri #include <linux/iio/sysfs.h> 18*e112dc4eSNavin Sankar Velliangiri #include <linux/spi/spi.h> 19*e112dc4eSNavin Sankar Velliangiri #include <asm/unaligned.h> 20*e112dc4eSNavin Sankar Velliangiri 21*e112dc4eSNavin Sankar Velliangiri /* 22*e112dc4eSNavin Sankar Velliangiri * The MSB of the register value determines whether the following byte will 23*e112dc4eSNavin Sankar Velliangiri * be written or read. If it is 0, read will follow and if it is 1, write 24*e112dc4eSNavin Sankar Velliangiri * will follow. 25*e112dc4eSNavin Sankar Velliangiri */ 26*e112dc4eSNavin Sankar Velliangiri #define MAX31865_RD_WR_BIT BIT(7) 27*e112dc4eSNavin Sankar Velliangiri 28*e112dc4eSNavin Sankar Velliangiri #define MAX31865_CFG_VBIAS BIT(7) 29*e112dc4eSNavin Sankar Velliangiri #define MAX31865_CFG_1SHOT BIT(5) 30*e112dc4eSNavin Sankar Velliangiri #define MAX31865_3WIRE_RTD BIT(4) 31*e112dc4eSNavin Sankar Velliangiri #define MAX31865_FAULT_STATUS_CLEAR BIT(1) 32*e112dc4eSNavin Sankar Velliangiri #define MAX31865_FILTER_50HZ BIT(0) 33*e112dc4eSNavin Sankar Velliangiri 34*e112dc4eSNavin Sankar Velliangiri /* The MAX31865 registers */ 35*e112dc4eSNavin Sankar Velliangiri #define MAX31865_CFG_REG 0x00 36*e112dc4eSNavin Sankar Velliangiri #define MAX31865_RTD_MSB 0x01 37*e112dc4eSNavin Sankar Velliangiri #define MAX31865_FAULT_STATUS 0x07 38*e112dc4eSNavin Sankar Velliangiri 39*e112dc4eSNavin Sankar Velliangiri #define MAX31865_FAULT_OVUV BIT(2) 40*e112dc4eSNavin Sankar Velliangiri 41*e112dc4eSNavin Sankar Velliangiri static const char max31865_show_samp_freq[] = "50 60"; 42*e112dc4eSNavin Sankar Velliangiri 43*e112dc4eSNavin Sankar Velliangiri static const struct iio_chan_spec max31865_channels[] = { 44*e112dc4eSNavin Sankar Velliangiri { /* RTD Temperature */ 45*e112dc4eSNavin Sankar Velliangiri .type = IIO_TEMP, 46*e112dc4eSNavin Sankar Velliangiri .info_mask_separate = 47*e112dc4eSNavin Sankar Velliangiri BIT(IIO_CHAN_INFO_RAW) | BIT(IIO_CHAN_INFO_SCALE) 48*e112dc4eSNavin Sankar Velliangiri }, 49*e112dc4eSNavin Sankar Velliangiri }; 50*e112dc4eSNavin Sankar Velliangiri 51*e112dc4eSNavin Sankar Velliangiri struct max31865_data { 52*e112dc4eSNavin Sankar Velliangiri struct spi_device *spi; 53*e112dc4eSNavin Sankar Velliangiri struct mutex lock; 54*e112dc4eSNavin Sankar Velliangiri bool filter_50hz; 55*e112dc4eSNavin Sankar Velliangiri bool three_wire; 56*e112dc4eSNavin Sankar Velliangiri u8 buf[2] ____cacheline_aligned; 57*e112dc4eSNavin Sankar Velliangiri }; 58*e112dc4eSNavin Sankar Velliangiri 59*e112dc4eSNavin Sankar Velliangiri static int max31865_read(struct max31865_data *data, u8 reg, 60*e112dc4eSNavin Sankar Velliangiri unsigned int read_size) 61*e112dc4eSNavin Sankar Velliangiri { 62*e112dc4eSNavin Sankar Velliangiri return spi_write_then_read(data->spi, ®, 1, data->buf, read_size); 63*e112dc4eSNavin Sankar Velliangiri } 64*e112dc4eSNavin Sankar Velliangiri 65*e112dc4eSNavin Sankar Velliangiri static int max31865_write(struct max31865_data *data, size_t len) 66*e112dc4eSNavin Sankar Velliangiri { 67*e112dc4eSNavin Sankar Velliangiri return spi_write(data->spi, data->buf, len); 68*e112dc4eSNavin Sankar Velliangiri } 69*e112dc4eSNavin Sankar Velliangiri 70*e112dc4eSNavin Sankar Velliangiri static int enable_bias(struct max31865_data *data) 71*e112dc4eSNavin Sankar Velliangiri { 72*e112dc4eSNavin Sankar Velliangiri u8 cfg; 73*e112dc4eSNavin Sankar Velliangiri int ret; 74*e112dc4eSNavin Sankar Velliangiri 75*e112dc4eSNavin Sankar Velliangiri ret = max31865_read(data, MAX31865_CFG_REG, 1); 76*e112dc4eSNavin Sankar Velliangiri if (ret) 77*e112dc4eSNavin Sankar Velliangiri return ret; 78*e112dc4eSNavin Sankar Velliangiri 79*e112dc4eSNavin Sankar Velliangiri cfg = data->buf[0]; 80*e112dc4eSNavin Sankar Velliangiri 81*e112dc4eSNavin Sankar Velliangiri data->buf[0] = MAX31865_CFG_REG | MAX31865_RD_WR_BIT; 82*e112dc4eSNavin Sankar Velliangiri data->buf[1] = cfg | MAX31865_CFG_VBIAS; 83*e112dc4eSNavin Sankar Velliangiri 84*e112dc4eSNavin Sankar Velliangiri return max31865_write(data, 2); 85*e112dc4eSNavin Sankar Velliangiri } 86*e112dc4eSNavin Sankar Velliangiri 87*e112dc4eSNavin Sankar Velliangiri static int disable_bias(struct max31865_data *data) 88*e112dc4eSNavin Sankar Velliangiri { 89*e112dc4eSNavin Sankar Velliangiri u8 cfg; 90*e112dc4eSNavin Sankar Velliangiri int ret; 91*e112dc4eSNavin Sankar Velliangiri 92*e112dc4eSNavin Sankar Velliangiri ret = max31865_read(data, MAX31865_CFG_REG, 1); 93*e112dc4eSNavin Sankar Velliangiri if (ret) 94*e112dc4eSNavin Sankar Velliangiri return ret; 95*e112dc4eSNavin Sankar Velliangiri 96*e112dc4eSNavin Sankar Velliangiri cfg = data->buf[0]; 97*e112dc4eSNavin Sankar Velliangiri cfg &= ~MAX31865_CFG_VBIAS; 98*e112dc4eSNavin Sankar Velliangiri 99*e112dc4eSNavin Sankar Velliangiri data->buf[0] = MAX31865_CFG_REG | MAX31865_RD_WR_BIT; 100*e112dc4eSNavin Sankar Velliangiri data->buf[1] = cfg; 101*e112dc4eSNavin Sankar Velliangiri 102*e112dc4eSNavin Sankar Velliangiri return max31865_write(data, 2); 103*e112dc4eSNavin Sankar Velliangiri } 104*e112dc4eSNavin Sankar Velliangiri 105*e112dc4eSNavin Sankar Velliangiri static int max31865_rtd_read(struct max31865_data *data, int *val) 106*e112dc4eSNavin Sankar Velliangiri { 107*e112dc4eSNavin Sankar Velliangiri u8 reg; 108*e112dc4eSNavin Sankar Velliangiri int ret; 109*e112dc4eSNavin Sankar Velliangiri 110*e112dc4eSNavin Sankar Velliangiri /* Enable BIAS to start the conversion */ 111*e112dc4eSNavin Sankar Velliangiri ret = enable_bias(data); 112*e112dc4eSNavin Sankar Velliangiri if (ret) 113*e112dc4eSNavin Sankar Velliangiri return ret; 114*e112dc4eSNavin Sankar Velliangiri 115*e112dc4eSNavin Sankar Velliangiri /* wait 10.5ms before initiating the conversion */ 116*e112dc4eSNavin Sankar Velliangiri msleep(11); 117*e112dc4eSNavin Sankar Velliangiri 118*e112dc4eSNavin Sankar Velliangiri ret = max31865_read(data, MAX31865_CFG_REG, 1); 119*e112dc4eSNavin Sankar Velliangiri if (ret) 120*e112dc4eSNavin Sankar Velliangiri return ret; 121*e112dc4eSNavin Sankar Velliangiri 122*e112dc4eSNavin Sankar Velliangiri reg = data->buf[0]; 123*e112dc4eSNavin Sankar Velliangiri reg |= MAX31865_CFG_1SHOT | MAX31865_FAULT_STATUS_CLEAR; 124*e112dc4eSNavin Sankar Velliangiri data->buf[0] = MAX31865_CFG_REG | MAX31865_RD_WR_BIT; 125*e112dc4eSNavin Sankar Velliangiri data->buf[1] = reg; 126*e112dc4eSNavin Sankar Velliangiri 127*e112dc4eSNavin Sankar Velliangiri ret = max31865_write(data, 2); 128*e112dc4eSNavin Sankar Velliangiri if (ret) 129*e112dc4eSNavin Sankar Velliangiri return ret; 130*e112dc4eSNavin Sankar Velliangiri 131*e112dc4eSNavin Sankar Velliangiri if (data->filter_50hz) { 132*e112dc4eSNavin Sankar Velliangiri /* 50Hz filter mode requires 62.5ms to complete */ 133*e112dc4eSNavin Sankar Velliangiri msleep(63); 134*e112dc4eSNavin Sankar Velliangiri } else { 135*e112dc4eSNavin Sankar Velliangiri /* 60Hz filter mode requires 52ms to complete */ 136*e112dc4eSNavin Sankar Velliangiri msleep(52); 137*e112dc4eSNavin Sankar Velliangiri } 138*e112dc4eSNavin Sankar Velliangiri 139*e112dc4eSNavin Sankar Velliangiri ret = max31865_read(data, MAX31865_RTD_MSB, 2); 140*e112dc4eSNavin Sankar Velliangiri if (ret) 141*e112dc4eSNavin Sankar Velliangiri return ret; 142*e112dc4eSNavin Sankar Velliangiri 143*e112dc4eSNavin Sankar Velliangiri *val = get_unaligned_be16(&data->buf) >> 1; 144*e112dc4eSNavin Sankar Velliangiri 145*e112dc4eSNavin Sankar Velliangiri return disable_bias(data); 146*e112dc4eSNavin Sankar Velliangiri } 147*e112dc4eSNavin Sankar Velliangiri 148*e112dc4eSNavin Sankar Velliangiri static int max31865_read_raw(struct iio_dev *indio_dev, 149*e112dc4eSNavin Sankar Velliangiri struct iio_chan_spec const *chan, 150*e112dc4eSNavin Sankar Velliangiri int *val, int *val2, long mask) 151*e112dc4eSNavin Sankar Velliangiri { 152*e112dc4eSNavin Sankar Velliangiri struct max31865_data *data = iio_priv(indio_dev); 153*e112dc4eSNavin Sankar Velliangiri int ret; 154*e112dc4eSNavin Sankar Velliangiri 155*e112dc4eSNavin Sankar Velliangiri switch (mask) { 156*e112dc4eSNavin Sankar Velliangiri case IIO_CHAN_INFO_RAW: 157*e112dc4eSNavin Sankar Velliangiri mutex_lock(&data->lock); 158*e112dc4eSNavin Sankar Velliangiri ret = max31865_rtd_read(data, val); 159*e112dc4eSNavin Sankar Velliangiri mutex_unlock(&data->lock); 160*e112dc4eSNavin Sankar Velliangiri if (ret) 161*e112dc4eSNavin Sankar Velliangiri return ret; 162*e112dc4eSNavin Sankar Velliangiri return IIO_VAL_INT; 163*e112dc4eSNavin Sankar Velliangiri case IIO_CHAN_INFO_SCALE: 164*e112dc4eSNavin Sankar Velliangiri /* Temp. Data resolution is 0.03125 degree centigrade */ 165*e112dc4eSNavin Sankar Velliangiri *val = 31; 166*e112dc4eSNavin Sankar Velliangiri *val2 = 250000; /* 1000 * 0.03125 */ 167*e112dc4eSNavin Sankar Velliangiri return IIO_VAL_INT_PLUS_MICRO; 168*e112dc4eSNavin Sankar Velliangiri default: 169*e112dc4eSNavin Sankar Velliangiri return -EINVAL; 170*e112dc4eSNavin Sankar Velliangiri } 171*e112dc4eSNavin Sankar Velliangiri } 172*e112dc4eSNavin Sankar Velliangiri 173*e112dc4eSNavin Sankar Velliangiri static int max31865_init(struct max31865_data *data) 174*e112dc4eSNavin Sankar Velliangiri { 175*e112dc4eSNavin Sankar Velliangiri u8 cfg; 176*e112dc4eSNavin Sankar Velliangiri int ret; 177*e112dc4eSNavin Sankar Velliangiri 178*e112dc4eSNavin Sankar Velliangiri ret = max31865_read(data, MAX31865_CFG_REG, 1); 179*e112dc4eSNavin Sankar Velliangiri if (ret) 180*e112dc4eSNavin Sankar Velliangiri return ret; 181*e112dc4eSNavin Sankar Velliangiri 182*e112dc4eSNavin Sankar Velliangiri cfg = data->buf[0]; 183*e112dc4eSNavin Sankar Velliangiri 184*e112dc4eSNavin Sankar Velliangiri if (data->three_wire) 185*e112dc4eSNavin Sankar Velliangiri /* 3-wire RTD connection */ 186*e112dc4eSNavin Sankar Velliangiri cfg |= MAX31865_3WIRE_RTD; 187*e112dc4eSNavin Sankar Velliangiri 188*e112dc4eSNavin Sankar Velliangiri if (data->filter_50hz) 189*e112dc4eSNavin Sankar Velliangiri /* 50Hz noise rejection filter */ 190*e112dc4eSNavin Sankar Velliangiri cfg |= MAX31865_FILTER_50HZ; 191*e112dc4eSNavin Sankar Velliangiri 192*e112dc4eSNavin Sankar Velliangiri data->buf[0] = MAX31865_CFG_REG | MAX31865_RD_WR_BIT; 193*e112dc4eSNavin Sankar Velliangiri data->buf[1] = cfg; 194*e112dc4eSNavin Sankar Velliangiri 195*e112dc4eSNavin Sankar Velliangiri return max31865_write(data, 2); 196*e112dc4eSNavin Sankar Velliangiri } 197*e112dc4eSNavin Sankar Velliangiri 198*e112dc4eSNavin Sankar Velliangiri static ssize_t show_fault(struct device *dev, u8 faultbit, char *buf) 199*e112dc4eSNavin Sankar Velliangiri { 200*e112dc4eSNavin Sankar Velliangiri int ret; 201*e112dc4eSNavin Sankar Velliangiri bool fault; 202*e112dc4eSNavin Sankar Velliangiri struct iio_dev *indio_dev = dev_to_iio_dev(dev); 203*e112dc4eSNavin Sankar Velliangiri struct max31865_data *data = iio_priv(indio_dev); 204*e112dc4eSNavin Sankar Velliangiri 205*e112dc4eSNavin Sankar Velliangiri ret = max31865_read(data, MAX31865_FAULT_STATUS, 1); 206*e112dc4eSNavin Sankar Velliangiri if (ret) 207*e112dc4eSNavin Sankar Velliangiri return ret; 208*e112dc4eSNavin Sankar Velliangiri 209*e112dc4eSNavin Sankar Velliangiri fault = data->buf[0] & faultbit; 210*e112dc4eSNavin Sankar Velliangiri 211*e112dc4eSNavin Sankar Velliangiri return sprintf(buf, "%d\n", fault); 212*e112dc4eSNavin Sankar Velliangiri } 213*e112dc4eSNavin Sankar Velliangiri 214*e112dc4eSNavin Sankar Velliangiri static ssize_t show_fault_ovuv(struct device *dev, 215*e112dc4eSNavin Sankar Velliangiri struct device_attribute *attr, 216*e112dc4eSNavin Sankar Velliangiri char *buf) 217*e112dc4eSNavin Sankar Velliangiri { 218*e112dc4eSNavin Sankar Velliangiri return show_fault(dev, MAX31865_FAULT_OVUV, buf); 219*e112dc4eSNavin Sankar Velliangiri } 220*e112dc4eSNavin Sankar Velliangiri 221*e112dc4eSNavin Sankar Velliangiri static ssize_t show_filter(struct device *dev, 222*e112dc4eSNavin Sankar Velliangiri struct device_attribute *attr, 223*e112dc4eSNavin Sankar Velliangiri char *buf) 224*e112dc4eSNavin Sankar Velliangiri { 225*e112dc4eSNavin Sankar Velliangiri struct iio_dev *indio_dev = dev_to_iio_dev(dev); 226*e112dc4eSNavin Sankar Velliangiri struct max31865_data *data = iio_priv(indio_dev); 227*e112dc4eSNavin Sankar Velliangiri 228*e112dc4eSNavin Sankar Velliangiri return sprintf(buf, "%d\n", data->filter_50hz ? 50 : 60); 229*e112dc4eSNavin Sankar Velliangiri } 230*e112dc4eSNavin Sankar Velliangiri 231*e112dc4eSNavin Sankar Velliangiri static ssize_t set_filter(struct device *dev, 232*e112dc4eSNavin Sankar Velliangiri struct device_attribute *attr, 233*e112dc4eSNavin Sankar Velliangiri const char *buf, 234*e112dc4eSNavin Sankar Velliangiri size_t len) 235*e112dc4eSNavin Sankar Velliangiri { 236*e112dc4eSNavin Sankar Velliangiri struct iio_dev *indio_dev = dev_to_iio_dev(dev); 237*e112dc4eSNavin Sankar Velliangiri struct max31865_data *data = iio_priv(indio_dev); 238*e112dc4eSNavin Sankar Velliangiri unsigned int freq; 239*e112dc4eSNavin Sankar Velliangiri int ret; 240*e112dc4eSNavin Sankar Velliangiri 241*e112dc4eSNavin Sankar Velliangiri ret = kstrtouint(buf, 10, &freq); 242*e112dc4eSNavin Sankar Velliangiri if (ret) 243*e112dc4eSNavin Sankar Velliangiri return ret; 244*e112dc4eSNavin Sankar Velliangiri 245*e112dc4eSNavin Sankar Velliangiri switch (freq) { 246*e112dc4eSNavin Sankar Velliangiri case 50: 247*e112dc4eSNavin Sankar Velliangiri data->filter_50hz = true; 248*e112dc4eSNavin Sankar Velliangiri break; 249*e112dc4eSNavin Sankar Velliangiri case 60: 250*e112dc4eSNavin Sankar Velliangiri data->filter_50hz = false; 251*e112dc4eSNavin Sankar Velliangiri break; 252*e112dc4eSNavin Sankar Velliangiri default: 253*e112dc4eSNavin Sankar Velliangiri return -EINVAL; 254*e112dc4eSNavin Sankar Velliangiri } 255*e112dc4eSNavin Sankar Velliangiri 256*e112dc4eSNavin Sankar Velliangiri mutex_lock(&data->lock); 257*e112dc4eSNavin Sankar Velliangiri ret = max31865_init(data); 258*e112dc4eSNavin Sankar Velliangiri mutex_unlock(&data->lock); 259*e112dc4eSNavin Sankar Velliangiri if (ret) 260*e112dc4eSNavin Sankar Velliangiri return ret; 261*e112dc4eSNavin Sankar Velliangiri 262*e112dc4eSNavin Sankar Velliangiri return len; 263*e112dc4eSNavin Sankar Velliangiri } 264*e112dc4eSNavin Sankar Velliangiri 265*e112dc4eSNavin Sankar Velliangiri static IIO_CONST_ATTR_SAMP_FREQ_AVAIL(max31865_show_samp_freq); 266*e112dc4eSNavin Sankar Velliangiri static IIO_DEVICE_ATTR(fault_ovuv, 0444, show_fault_ovuv, NULL, 0); 267*e112dc4eSNavin Sankar Velliangiri static IIO_DEVICE_ATTR(in_filter_notch_center_frequency, 0644, 268*e112dc4eSNavin Sankar Velliangiri show_filter, set_filter, 0); 269*e112dc4eSNavin Sankar Velliangiri 270*e112dc4eSNavin Sankar Velliangiri static struct attribute *max31865_attributes[] = { 271*e112dc4eSNavin Sankar Velliangiri &iio_dev_attr_fault_ovuv.dev_attr.attr, 272*e112dc4eSNavin Sankar Velliangiri &iio_const_attr_sampling_frequency_available.dev_attr.attr, 273*e112dc4eSNavin Sankar Velliangiri &iio_dev_attr_in_filter_notch_center_frequency.dev_attr.attr, 274*e112dc4eSNavin Sankar Velliangiri NULL, 275*e112dc4eSNavin Sankar Velliangiri }; 276*e112dc4eSNavin Sankar Velliangiri 277*e112dc4eSNavin Sankar Velliangiri static const struct attribute_group max31865_group = { 278*e112dc4eSNavin Sankar Velliangiri .attrs = max31865_attributes, 279*e112dc4eSNavin Sankar Velliangiri }; 280*e112dc4eSNavin Sankar Velliangiri 281*e112dc4eSNavin Sankar Velliangiri static const struct iio_info max31865_info = { 282*e112dc4eSNavin Sankar Velliangiri .read_raw = max31865_read_raw, 283*e112dc4eSNavin Sankar Velliangiri .attrs = &max31865_group, 284*e112dc4eSNavin Sankar Velliangiri }; 285*e112dc4eSNavin Sankar Velliangiri 286*e112dc4eSNavin Sankar Velliangiri static int max31865_probe(struct spi_device *spi) 287*e112dc4eSNavin Sankar Velliangiri { 288*e112dc4eSNavin Sankar Velliangiri const struct spi_device_id *id = spi_get_device_id(spi); 289*e112dc4eSNavin Sankar Velliangiri struct iio_dev *indio_dev; 290*e112dc4eSNavin Sankar Velliangiri struct max31865_data *data; 291*e112dc4eSNavin Sankar Velliangiri int ret; 292*e112dc4eSNavin Sankar Velliangiri 293*e112dc4eSNavin Sankar Velliangiri indio_dev = devm_iio_device_alloc(&spi->dev, sizeof(*data)); 294*e112dc4eSNavin Sankar Velliangiri if (!indio_dev) 295*e112dc4eSNavin Sankar Velliangiri return -ENOMEM; 296*e112dc4eSNavin Sankar Velliangiri 297*e112dc4eSNavin Sankar Velliangiri data = iio_priv(indio_dev); 298*e112dc4eSNavin Sankar Velliangiri data->spi = spi; 299*e112dc4eSNavin Sankar Velliangiri data->filter_50hz = false; 300*e112dc4eSNavin Sankar Velliangiri mutex_init(&data->lock); 301*e112dc4eSNavin Sankar Velliangiri 302*e112dc4eSNavin Sankar Velliangiri indio_dev->info = &max31865_info; 303*e112dc4eSNavin Sankar Velliangiri indio_dev->name = id->name; 304*e112dc4eSNavin Sankar Velliangiri indio_dev->modes = INDIO_DIRECT_MODE; 305*e112dc4eSNavin Sankar Velliangiri indio_dev->channels = max31865_channels; 306*e112dc4eSNavin Sankar Velliangiri indio_dev->num_channels = ARRAY_SIZE(max31865_channels); 307*e112dc4eSNavin Sankar Velliangiri 308*e112dc4eSNavin Sankar Velliangiri if (of_property_read_bool(spi->dev.of_node, "maxim,3-wire")) { 309*e112dc4eSNavin Sankar Velliangiri /* select 3 wire */ 310*e112dc4eSNavin Sankar Velliangiri data->three_wire = 1; 311*e112dc4eSNavin Sankar Velliangiri } else { 312*e112dc4eSNavin Sankar Velliangiri /* select 2 or 4 wire */ 313*e112dc4eSNavin Sankar Velliangiri data->three_wire = 0; 314*e112dc4eSNavin Sankar Velliangiri } 315*e112dc4eSNavin Sankar Velliangiri 316*e112dc4eSNavin Sankar Velliangiri ret = max31865_init(data); 317*e112dc4eSNavin Sankar Velliangiri if (ret) { 318*e112dc4eSNavin Sankar Velliangiri dev_err(&spi->dev, "error: Failed to configure max31865\n"); 319*e112dc4eSNavin Sankar Velliangiri return ret; 320*e112dc4eSNavin Sankar Velliangiri } 321*e112dc4eSNavin Sankar Velliangiri 322*e112dc4eSNavin Sankar Velliangiri return devm_iio_device_register(&spi->dev, indio_dev); 323*e112dc4eSNavin Sankar Velliangiri } 324*e112dc4eSNavin Sankar Velliangiri 325*e112dc4eSNavin Sankar Velliangiri static const struct spi_device_id max31865_id[] = { 326*e112dc4eSNavin Sankar Velliangiri { "max31865", 0 }, 327*e112dc4eSNavin Sankar Velliangiri { } 328*e112dc4eSNavin Sankar Velliangiri }; 329*e112dc4eSNavin Sankar Velliangiri MODULE_DEVICE_TABLE(spi, max31865_id); 330*e112dc4eSNavin Sankar Velliangiri 331*e112dc4eSNavin Sankar Velliangiri static const struct of_device_id max31865_of_match[] = { 332*e112dc4eSNavin Sankar Velliangiri { .compatible = "maxim,max31865" }, 333*e112dc4eSNavin Sankar Velliangiri { } 334*e112dc4eSNavin Sankar Velliangiri }; 335*e112dc4eSNavin Sankar Velliangiri MODULE_DEVICE_TABLE(of, max31865_of_match); 336*e112dc4eSNavin Sankar Velliangiri 337*e112dc4eSNavin Sankar Velliangiri static struct spi_driver max31865_driver = { 338*e112dc4eSNavin Sankar Velliangiri .driver = { 339*e112dc4eSNavin Sankar Velliangiri .name = "max31865", 340*e112dc4eSNavin Sankar Velliangiri .of_match_table = max31865_of_match, 341*e112dc4eSNavin Sankar Velliangiri }, 342*e112dc4eSNavin Sankar Velliangiri .probe = max31865_probe, 343*e112dc4eSNavin Sankar Velliangiri .id_table = max31865_id, 344*e112dc4eSNavin Sankar Velliangiri }; 345*e112dc4eSNavin Sankar Velliangiri module_spi_driver(max31865_driver); 346*e112dc4eSNavin Sankar Velliangiri 347*e112dc4eSNavin Sankar Velliangiri MODULE_AUTHOR("Navin Sankar Velliangiri <navin@linumiz.com>"); 348*e112dc4eSNavin Sankar Velliangiri MODULE_DESCRIPTION("Maxim MAX31865 RTD-to-Digital Converter sensor driver"); 349*e112dc4eSNavin Sankar Velliangiri MODULE_LICENSE("GPL v2"); 350