1 // SPDX-License-Identifier: GPL-2.0-only
2 /*
3  * Industrial I/O driver for Microchip digital potentiometers
4  *
5  * Copyright (c) 2016 Slawomir Stepien
6  * Based on: Peter Rosin's code from mcp4531.c
7  *
8  * Datasheet: http://ww1.microchip.com/downloads/en/DeviceDoc/22060b.pdf
9  *
10  * DEVID	#Wipers	#Positions	Resistor Opts (kOhm)
11  * mcp4131	1	129		5, 10, 50, 100
12  * mcp4132	1	129		5, 10, 50, 100
13  * mcp4141	1	129		5, 10, 50, 100
14  * mcp4142	1	129		5, 10, 50, 100
15  * mcp4151	1	257		5, 10, 50, 100
16  * mcp4152	1	257		5, 10, 50, 100
17  * mcp4161	1	257		5, 10, 50, 100
18  * mcp4162	1	257		5, 10, 50, 100
19  * mcp4231	2	129		5, 10, 50, 100
20  * mcp4232	2	129		5, 10, 50, 100
21  * mcp4241	2	129		5, 10, 50, 100
22  * mcp4242	2	129		5, 10, 50, 100
23  * mcp4251	2	257		5, 10, 50, 100
24  * mcp4252	2	257		5, 10, 50, 100
25  * mcp4261	2	257		5, 10, 50, 100
26  * mcp4262	2	257		5, 10, 50, 100
27  */
28 
29 /*
30  * TODO:
31  * 1. Write wiper setting to EEPROM for EEPROM capable models.
32  */
33 
34 #include <linux/cache.h>
35 #include <linux/err.h>
36 #include <linux/export.h>
37 #include <linux/iio/iio.h>
38 #include <linux/iio/types.h>
39 #include <linux/module.h>
40 #include <linux/mutex.h>
41 #include <linux/of.h>
42 #include <linux/of_device.h>
43 #include <linux/spi/spi.h>
44 
45 #define MCP4131_WRITE		(0x00 << 2)
46 #define MCP4131_READ		(0x03 << 2)
47 
48 #define MCP4131_WIPER_SHIFT	4
49 #define MCP4131_CMDERR(r)	((r[0]) & 0x02)
50 #define MCP4131_RAW(r)		((r[0]) == 0xff ? 0x100 : (r[1]))
51 
52 struct mcp4131_cfg {
53 	int wipers;
54 	int max_pos;
55 	int kohms;
56 };
57 
58 enum mcp4131_type {
59 	MCP413x_502 = 0,
60 	MCP413x_103,
61 	MCP413x_503,
62 	MCP413x_104,
63 	MCP414x_502,
64 	MCP414x_103,
65 	MCP414x_503,
66 	MCP414x_104,
67 	MCP415x_502,
68 	MCP415x_103,
69 	MCP415x_503,
70 	MCP415x_104,
71 	MCP416x_502,
72 	MCP416x_103,
73 	MCP416x_503,
74 	MCP416x_104,
75 	MCP423x_502,
76 	MCP423x_103,
77 	MCP423x_503,
78 	MCP423x_104,
79 	MCP424x_502,
80 	MCP424x_103,
81 	MCP424x_503,
82 	MCP424x_104,
83 	MCP425x_502,
84 	MCP425x_103,
85 	MCP425x_503,
86 	MCP425x_104,
87 	MCP426x_502,
88 	MCP426x_103,
89 	MCP426x_503,
90 	MCP426x_104,
91 };
92 
93 static const struct mcp4131_cfg mcp4131_cfg[] = {
94 	[MCP413x_502] = { .wipers = 1, .max_pos = 128, .kohms =   5, },
95 	[MCP413x_103] = { .wipers = 1, .max_pos = 128, .kohms =  10, },
96 	[MCP413x_503] = { .wipers = 1, .max_pos = 128, .kohms =  50, },
97 	[MCP413x_104] = { .wipers = 1, .max_pos = 128, .kohms = 100, },
98 	[MCP414x_502] = { .wipers = 1, .max_pos = 128, .kohms =   5, },
99 	[MCP414x_103] = { .wipers = 1, .max_pos = 128, .kohms =  10, },
100 	[MCP414x_503] = { .wipers = 1, .max_pos = 128, .kohms =  50, },
101 	[MCP414x_104] = { .wipers = 1, .max_pos = 128, .kohms = 100, },
102 	[MCP415x_502] = { .wipers = 1, .max_pos = 256, .kohms =   5, },
103 	[MCP415x_103] = { .wipers = 1, .max_pos = 256, .kohms =  10, },
104 	[MCP415x_503] = { .wipers = 1, .max_pos = 256, .kohms =  50, },
105 	[MCP415x_104] = { .wipers = 1, .max_pos = 256, .kohms = 100, },
106 	[MCP416x_502] = { .wipers = 1, .max_pos = 256, .kohms =   5, },
107 	[MCP416x_103] = { .wipers = 1, .max_pos = 256, .kohms =  10, },
108 	[MCP416x_503] = { .wipers = 1, .max_pos = 256, .kohms =  50, },
109 	[MCP416x_104] = { .wipers = 1, .max_pos = 256, .kohms = 100, },
110 	[MCP423x_502] = { .wipers = 2, .max_pos = 128, .kohms =   5, },
111 	[MCP423x_103] = { .wipers = 2, .max_pos = 128, .kohms =  10, },
112 	[MCP423x_503] = { .wipers = 2, .max_pos = 128, .kohms =  50, },
113 	[MCP423x_104] = { .wipers = 2, .max_pos = 128, .kohms = 100, },
114 	[MCP424x_502] = { .wipers = 2, .max_pos = 128, .kohms =   5, },
115 	[MCP424x_103] = { .wipers = 2, .max_pos = 128, .kohms =  10, },
116 	[MCP424x_503] = { .wipers = 2, .max_pos = 128, .kohms =  50, },
117 	[MCP424x_104] = { .wipers = 2, .max_pos = 128, .kohms = 100, },
118 	[MCP425x_502] = { .wipers = 2, .max_pos = 256, .kohms =   5, },
119 	[MCP425x_103] = { .wipers = 2, .max_pos = 256, .kohms =  10, },
120 	[MCP425x_503] = { .wipers = 2, .max_pos = 256, .kohms =  50, },
121 	[MCP425x_104] = { .wipers = 2, .max_pos = 256, .kohms = 100, },
122 	[MCP426x_502] = { .wipers = 2, .max_pos = 256, .kohms =   5, },
123 	[MCP426x_103] = { .wipers = 2, .max_pos = 256, .kohms =  10, },
124 	[MCP426x_503] = { .wipers = 2, .max_pos = 256, .kohms =  50, },
125 	[MCP426x_104] = { .wipers = 2, .max_pos = 256, .kohms = 100, },
126 };
127 
128 struct mcp4131_data {
129 	struct spi_device *spi;
130 	const struct mcp4131_cfg *cfg;
131 	struct mutex lock;
132 	u8 buf[2] ____cacheline_aligned;
133 };
134 
135 #define MCP4131_CHANNEL(ch) {					\
136 	.type = IIO_RESISTANCE,					\
137 	.indexed = 1,						\
138 	.output = 1,						\
139 	.channel = (ch),					\
140 	.info_mask_separate = BIT(IIO_CHAN_INFO_RAW),		\
141 	.info_mask_shared_by_type = BIT(IIO_CHAN_INFO_SCALE),	\
142 }
143 
144 static const struct iio_chan_spec mcp4131_channels[] = {
145 	MCP4131_CHANNEL(0),
146 	MCP4131_CHANNEL(1),
147 };
148 
149 static int mcp4131_read(struct spi_device *spi, void *buf, size_t len)
150 {
151 	struct spi_transfer t = {
152 		.tx_buf = buf, /* We need to send addr, cmd and 12 bits */
153 		.rx_buf	= buf,
154 		.len = len,
155 	};
156 	struct spi_message m;
157 
158 	spi_message_init(&m);
159 	spi_message_add_tail(&t, &m);
160 
161 	return spi_sync(spi, &m);
162 }
163 
164 static int mcp4131_read_raw(struct iio_dev *indio_dev,
165 			    struct iio_chan_spec const *chan,
166 			    int *val, int *val2, long mask)
167 {
168 	int err;
169 	struct mcp4131_data *data = iio_priv(indio_dev);
170 	int address = chan->channel;
171 
172 	switch (mask) {
173 	case IIO_CHAN_INFO_RAW:
174 		mutex_lock(&data->lock);
175 
176 		data->buf[0] = (address << MCP4131_WIPER_SHIFT) | MCP4131_READ;
177 		data->buf[1] = 0;
178 
179 		err = mcp4131_read(data->spi, data->buf, 2);
180 		if (err) {
181 			mutex_unlock(&data->lock);
182 			return err;
183 		}
184 
185 		/* Error, bad address/command combination */
186 		if (!MCP4131_CMDERR(data->buf)) {
187 			mutex_unlock(&data->lock);
188 			return -EIO;
189 		}
190 
191 		*val = MCP4131_RAW(data->buf);
192 		mutex_unlock(&data->lock);
193 
194 		return IIO_VAL_INT;
195 
196 	case IIO_CHAN_INFO_SCALE:
197 		*val = 1000 * data->cfg->kohms;
198 		*val2 = data->cfg->max_pos;
199 		return IIO_VAL_FRACTIONAL;
200 	}
201 
202 	return -EINVAL;
203 }
204 
205 static int mcp4131_write_raw(struct iio_dev *indio_dev,
206 			     struct iio_chan_spec const *chan,
207 			     int val, int val2, long mask)
208 {
209 	int err;
210 	struct mcp4131_data *data = iio_priv(indio_dev);
211 	int address = chan->channel << MCP4131_WIPER_SHIFT;
212 
213 	switch (mask) {
214 	case IIO_CHAN_INFO_RAW:
215 		if (val > data->cfg->max_pos || val < 0)
216 			return -EINVAL;
217 		break;
218 
219 	default:
220 		return -EINVAL;
221 	}
222 
223 	mutex_lock(&data->lock);
224 
225 	data->buf[0] = address << MCP4131_WIPER_SHIFT;
226 	data->buf[0] |= MCP4131_WRITE | (val >> 8);
227 	data->buf[1] = val & 0xFF; /* 8 bits here */
228 
229 	err = spi_write(data->spi, data->buf, 2);
230 	mutex_unlock(&data->lock);
231 
232 	return err;
233 }
234 
235 static const struct iio_info mcp4131_info = {
236 	.read_raw = mcp4131_read_raw,
237 	.write_raw = mcp4131_write_raw,
238 };
239 
240 static int mcp4131_probe(struct spi_device *spi)
241 {
242 	int err;
243 	struct device *dev = &spi->dev;
244 	unsigned long devid;
245 	struct mcp4131_data *data;
246 	struct iio_dev *indio_dev;
247 
248 	indio_dev = devm_iio_device_alloc(dev, sizeof(*data));
249 	if (!indio_dev)
250 		return -ENOMEM;
251 
252 	data = iio_priv(indio_dev);
253 	spi_set_drvdata(spi, indio_dev);
254 	data->spi = spi;
255 	data->cfg = of_device_get_match_data(&spi->dev);
256 	if (!data->cfg) {
257 		devid = spi_get_device_id(spi)->driver_data;
258 		data->cfg = &mcp4131_cfg[devid];
259 	}
260 
261 	mutex_init(&data->lock);
262 
263 	indio_dev->dev.parent = dev;
264 	indio_dev->info = &mcp4131_info;
265 	indio_dev->channels = mcp4131_channels;
266 	indio_dev->num_channels = data->cfg->wipers;
267 	indio_dev->name = spi_get_device_id(spi)->name;
268 
269 	err = devm_iio_device_register(dev, indio_dev);
270 	if (err) {
271 		dev_info(&spi->dev, "Unable to register %s\n", indio_dev->name);
272 		return err;
273 	}
274 
275 	return 0;
276 }
277 
278 static const struct of_device_id mcp4131_dt_ids[] = {
279 	{ .compatible = "microchip,mcp4131-502",
280 		.data = &mcp4131_cfg[MCP413x_502] },
281 	{ .compatible = "microchip,mcp4131-103",
282 		.data = &mcp4131_cfg[MCP413x_103] },
283 	{ .compatible = "microchip,mcp4131-503",
284 		.data = &mcp4131_cfg[MCP413x_503] },
285 	{ .compatible = "microchip,mcp4131-104",
286 		.data = &mcp4131_cfg[MCP413x_104] },
287 	{ .compatible = "microchip,mcp4132-502",
288 		.data = &mcp4131_cfg[MCP413x_502] },
289 	{ .compatible = "microchip,mcp4132-103",
290 		.data = &mcp4131_cfg[MCP413x_103] },
291 	{ .compatible = "microchip,mcp4132-503",
292 		.data = &mcp4131_cfg[MCP413x_503] },
293 	{ .compatible = "microchip,mcp4132-104",
294 		.data = &mcp4131_cfg[MCP413x_104] },
295 	{ .compatible = "microchip,mcp4141-502",
296 		.data = &mcp4131_cfg[MCP414x_502] },
297 	{ .compatible = "microchip,mcp4141-103",
298 		.data = &mcp4131_cfg[MCP414x_103] },
299 	{ .compatible = "microchip,mcp4141-503",
300 		.data = &mcp4131_cfg[MCP414x_503] },
301 	{ .compatible = "microchip,mcp4141-104",
302 		.data = &mcp4131_cfg[MCP414x_104] },
303 	{ .compatible = "microchip,mcp4142-502",
304 		.data = &mcp4131_cfg[MCP414x_502] },
305 	{ .compatible = "microchip,mcp4142-103",
306 		.data = &mcp4131_cfg[MCP414x_103] },
307 	{ .compatible = "microchip,mcp4142-503",
308 		.data = &mcp4131_cfg[MCP414x_503] },
309 	{ .compatible = "microchip,mcp4142-104",
310 		.data = &mcp4131_cfg[MCP414x_104] },
311 	{ .compatible = "microchip,mcp4151-502",
312 		.data = &mcp4131_cfg[MCP415x_502] },
313 	{ .compatible = "microchip,mcp4151-103",
314 		.data = &mcp4131_cfg[MCP415x_103] },
315 	{ .compatible = "microchip,mcp4151-503",
316 		.data = &mcp4131_cfg[MCP415x_503] },
317 	{ .compatible = "microchip,mcp4151-104",
318 		.data = &mcp4131_cfg[MCP415x_104] },
319 	{ .compatible = "microchip,mcp4152-502",
320 		.data = &mcp4131_cfg[MCP415x_502] },
321 	{ .compatible = "microchip,mcp4152-103",
322 		.data = &mcp4131_cfg[MCP415x_103] },
323 	{ .compatible = "microchip,mcp4152-503",
324 		.data = &mcp4131_cfg[MCP415x_503] },
325 	{ .compatible = "microchip,mcp4152-104",
326 		.data = &mcp4131_cfg[MCP415x_104] },
327 	{ .compatible = "microchip,mcp4161-502",
328 		.data = &mcp4131_cfg[MCP416x_502] },
329 	{ .compatible = "microchip,mcp4161-103",
330 		.data = &mcp4131_cfg[MCP416x_103] },
331 	{ .compatible = "microchip,mcp4161-503",
332 		.data = &mcp4131_cfg[MCP416x_503] },
333 	{ .compatible = "microchip,mcp4161-104",
334 		.data = &mcp4131_cfg[MCP416x_104] },
335 	{ .compatible = "microchip,mcp4162-502",
336 		.data = &mcp4131_cfg[MCP416x_502] },
337 	{ .compatible = "microchip,mcp4162-103",
338 		.data = &mcp4131_cfg[MCP416x_103] },
339 	{ .compatible = "microchip,mcp4162-503",
340 		.data = &mcp4131_cfg[MCP416x_503] },
341 	{ .compatible = "microchip,mcp4162-104",
342 		.data = &mcp4131_cfg[MCP416x_104] },
343 	{ .compatible = "microchip,mcp4231-502",
344 		.data = &mcp4131_cfg[MCP423x_502] },
345 	{ .compatible = "microchip,mcp4231-103",
346 		.data = &mcp4131_cfg[MCP423x_103] },
347 	{ .compatible = "microchip,mcp4231-503",
348 		.data = &mcp4131_cfg[MCP423x_503] },
349 	{ .compatible = "microchip,mcp4231-104",
350 		.data = &mcp4131_cfg[MCP423x_104] },
351 	{ .compatible = "microchip,mcp4232-502",
352 		.data = &mcp4131_cfg[MCP423x_502] },
353 	{ .compatible = "microchip,mcp4232-103",
354 		.data = &mcp4131_cfg[MCP423x_103] },
355 	{ .compatible = "microchip,mcp4232-503",
356 		.data = &mcp4131_cfg[MCP423x_503] },
357 	{ .compatible = "microchip,mcp4232-104",
358 		.data = &mcp4131_cfg[MCP423x_104] },
359 	{ .compatible = "microchip,mcp4241-502",
360 		.data = &mcp4131_cfg[MCP424x_502] },
361 	{ .compatible = "microchip,mcp4241-103",
362 		.data = &mcp4131_cfg[MCP424x_103] },
363 	{ .compatible = "microchip,mcp4241-503",
364 		.data = &mcp4131_cfg[MCP424x_503] },
365 	{ .compatible = "microchip,mcp4241-104",
366 		.data = &mcp4131_cfg[MCP424x_104] },
367 	{ .compatible = "microchip,mcp4242-502",
368 		.data = &mcp4131_cfg[MCP424x_502] },
369 	{ .compatible = "microchip,mcp4242-103",
370 		.data = &mcp4131_cfg[MCP424x_103] },
371 	{ .compatible = "microchip,mcp4242-503",
372 		.data = &mcp4131_cfg[MCP424x_503] },
373 	{ .compatible = "microchip,mcp4242-104",
374 		.data = &mcp4131_cfg[MCP424x_104] },
375 	{ .compatible = "microchip,mcp4251-502",
376 		.data = &mcp4131_cfg[MCP425x_502] },
377 	{ .compatible = "microchip,mcp4251-103",
378 		.data = &mcp4131_cfg[MCP425x_103] },
379 	{ .compatible = "microchip,mcp4251-503",
380 		.data = &mcp4131_cfg[MCP425x_503] },
381 	{ .compatible = "microchip,mcp4251-104",
382 		.data = &mcp4131_cfg[MCP425x_104] },
383 	{ .compatible = "microchip,mcp4252-502",
384 		.data = &mcp4131_cfg[MCP425x_502] },
385 	{ .compatible = "microchip,mcp4252-103",
386 		.data = &mcp4131_cfg[MCP425x_103] },
387 	{ .compatible = "microchip,mcp4252-503",
388 		.data = &mcp4131_cfg[MCP425x_503] },
389 	{ .compatible = "microchip,mcp4252-104",
390 		.data = &mcp4131_cfg[MCP425x_104] },
391 	{ .compatible = "microchip,mcp4261-502",
392 		.data = &mcp4131_cfg[MCP426x_502] },
393 	{ .compatible = "microchip,mcp4261-103",
394 		.data = &mcp4131_cfg[MCP426x_103] },
395 	{ .compatible = "microchip,mcp4261-503",
396 		.data = &mcp4131_cfg[MCP426x_503] },
397 	{ .compatible = "microchip,mcp4261-104",
398 		.data = &mcp4131_cfg[MCP426x_104] },
399 	{ .compatible = "microchip,mcp4262-502",
400 		.data = &mcp4131_cfg[MCP426x_502] },
401 	{ .compatible = "microchip,mcp4262-103",
402 		.data = &mcp4131_cfg[MCP426x_103] },
403 	{ .compatible = "microchip,mcp4262-503",
404 		.data = &mcp4131_cfg[MCP426x_503] },
405 	{ .compatible = "microchip,mcp4262-104",
406 		.data = &mcp4131_cfg[MCP426x_104] },
407 	{}
408 };
409 MODULE_DEVICE_TABLE(of, mcp4131_dt_ids);
410 
411 static const struct spi_device_id mcp4131_id[] = {
412 	{ "mcp4131-502", MCP413x_502 },
413 	{ "mcp4131-103", MCP413x_103 },
414 	{ "mcp4131-503", MCP413x_503 },
415 	{ "mcp4131-104", MCP413x_104 },
416 	{ "mcp4132-502", MCP413x_502 },
417 	{ "mcp4132-103", MCP413x_103 },
418 	{ "mcp4132-503", MCP413x_503 },
419 	{ "mcp4132-104", MCP413x_104 },
420 	{ "mcp4141-502", MCP414x_502 },
421 	{ "mcp4141-103", MCP414x_103 },
422 	{ "mcp4141-503", MCP414x_503 },
423 	{ "mcp4141-104", MCP414x_104 },
424 	{ "mcp4142-502", MCP414x_502 },
425 	{ "mcp4142-103", MCP414x_103 },
426 	{ "mcp4142-503", MCP414x_503 },
427 	{ "mcp4142-104", MCP414x_104 },
428 	{ "mcp4151-502", MCP415x_502 },
429 	{ "mcp4151-103", MCP415x_103 },
430 	{ "mcp4151-503", MCP415x_503 },
431 	{ "mcp4151-104", MCP415x_104 },
432 	{ "mcp4152-502", MCP415x_502 },
433 	{ "mcp4152-103", MCP415x_103 },
434 	{ "mcp4152-503", MCP415x_503 },
435 	{ "mcp4152-104", MCP415x_104 },
436 	{ "mcp4161-502", MCP416x_502 },
437 	{ "mcp4161-103", MCP416x_103 },
438 	{ "mcp4161-503", MCP416x_503 },
439 	{ "mcp4161-104", MCP416x_104 },
440 	{ "mcp4162-502", MCP416x_502 },
441 	{ "mcp4162-103", MCP416x_103 },
442 	{ "mcp4162-503", MCP416x_503 },
443 	{ "mcp4162-104", MCP416x_104 },
444 	{ "mcp4231-502", MCP423x_502 },
445 	{ "mcp4231-103", MCP423x_103 },
446 	{ "mcp4231-503", MCP423x_503 },
447 	{ "mcp4231-104", MCP423x_104 },
448 	{ "mcp4232-502", MCP423x_502 },
449 	{ "mcp4232-103", MCP423x_103 },
450 	{ "mcp4232-503", MCP423x_503 },
451 	{ "mcp4232-104", MCP423x_104 },
452 	{ "mcp4241-502", MCP424x_502 },
453 	{ "mcp4241-103", MCP424x_103 },
454 	{ "mcp4241-503", MCP424x_503 },
455 	{ "mcp4241-104", MCP424x_104 },
456 	{ "mcp4242-502", MCP424x_502 },
457 	{ "mcp4242-103", MCP424x_103 },
458 	{ "mcp4242-503", MCP424x_503 },
459 	{ "mcp4242-104", MCP424x_104 },
460 	{ "mcp4251-502", MCP425x_502 },
461 	{ "mcp4251-103", MCP425x_103 },
462 	{ "mcp4251-503", MCP425x_503 },
463 	{ "mcp4251-104", MCP425x_104 },
464 	{ "mcp4252-502", MCP425x_502 },
465 	{ "mcp4252-103", MCP425x_103 },
466 	{ "mcp4252-503", MCP425x_503 },
467 	{ "mcp4252-104", MCP425x_104 },
468 	{ "mcp4261-502", MCP426x_502 },
469 	{ "mcp4261-103", MCP426x_103 },
470 	{ "mcp4261-503", MCP426x_503 },
471 	{ "mcp4261-104", MCP426x_104 },
472 	{ "mcp4262-502", MCP426x_502 },
473 	{ "mcp4262-103", MCP426x_103 },
474 	{ "mcp4262-503", MCP426x_503 },
475 	{ "mcp4262-104", MCP426x_104 },
476 	{}
477 };
478 MODULE_DEVICE_TABLE(spi, mcp4131_id);
479 
480 static struct spi_driver mcp4131_driver = {
481 	.driver = {
482 		.name	= "mcp4131",
483 		.of_match_table = of_match_ptr(mcp4131_dt_ids),
484 	},
485 	.probe		= mcp4131_probe,
486 	.id_table	= mcp4131_id,
487 };
488 
489 module_spi_driver(mcp4131_driver);
490 
491 MODULE_AUTHOR("Slawomir Stepien <sst@poczta.fm>");
492 MODULE_DESCRIPTION("MCP4131 digital potentiometer");
493 MODULE_LICENSE("GPL v2");
494