1 // SPDX-License-Identifier: GPL-2.0-only 2 /* 3 * STMicroelectronics st_lsm6dsx sensor driver 4 * 5 * The ST LSM6DSx IMU MEMS series consists of 3D digital accelerometer 6 * and 3D digital gyroscope system-in-package with a digital I2C/SPI serial 7 * interface standard output. 8 * LSM6DSx IMU MEMS series has a dynamic user-selectable full-scale 9 * acceleration range of +-2/+-4/+-8/+-16 g and an angular rate range of 10 * +-125/+-245/+-500/+-1000/+-2000 dps 11 * LSM6DSx series has an integrated First-In-First-Out (FIFO) buffer 12 * allowing dynamic batching of sensor data. 13 * LSM9DSx series is similar but includes an additional magnetometer, handled 14 * by a different driver. 15 * 16 * Supported sensors: 17 * - LSM6DS3: 18 * - Accelerometer/Gyroscope supported ODR [Hz]: 13, 26, 52, 104, 208, 416 19 * - Accelerometer supported full-scale [g]: +-2/+-4/+-8/+-16 20 * - Gyroscope supported full-scale [dps]: +-125/+-245/+-500/+-1000/+-2000 21 * - FIFO size: 8KB 22 * 23 * - LSM6DS3H/LSM6DSL/LSM6DSM/ISM330DLC/LSM6DS3TR-C: 24 * - Accelerometer/Gyroscope supported ODR [Hz]: 13, 26, 52, 104, 208, 416 25 * - Accelerometer supported full-scale [g]: +-2/+-4/+-8/+-16 26 * - Gyroscope supported full-scale [dps]: +-125/+-245/+-500/+-1000/+-2000 27 * - FIFO size: 4KB 28 * 29 * - LSM6DSO/LSM6DSOX/ASM330LHH/LSM6DSR/ISM330DHCX: 30 * - Accelerometer/Gyroscope supported ODR [Hz]: 13, 26, 52, 104, 208, 416 31 * - Accelerometer supported full-scale [g]: +-2/+-4/+-8/+-16 32 * - Gyroscope supported full-scale [dps]: +-125/+-245/+-500/+-1000/+-2000 33 * - FIFO size: 3KB 34 * 35 * - LSM9DS1/LSM6DS0: 36 * - Accelerometer supported ODR [Hz]: 10, 50, 119, 238, 476, 952 37 * - Accelerometer supported full-scale [g]: +-2/+-4/+-8/+-16 38 * - Gyroscope supported ODR [Hz]: 15, 60, 119, 238, 476, 952 39 * - Gyroscope supported full-scale [dps]: +-245/+-500/+-2000 40 * - FIFO size: 32 41 * 42 * Copyright 2016 STMicroelectronics Inc. 43 * 44 * Lorenzo Bianconi <lorenzo.bianconi@st.com> 45 * Denis Ciocca <denis.ciocca@st.com> 46 */ 47 48 #include <linux/kernel.h> 49 #include <linux/module.h> 50 #include <linux/delay.h> 51 #include <linux/iio/events.h> 52 #include <linux/iio/iio.h> 53 #include <linux/iio/sysfs.h> 54 #include <linux/interrupt.h> 55 #include <linux/irq.h> 56 #include <linux/pm.h> 57 #include <linux/regmap.h> 58 #include <linux/bitfield.h> 59 60 #include <linux/platform_data/st_sensors_pdata.h> 61 62 #include "st_lsm6dsx.h" 63 64 #define ST_LSM6DSX_REG_WHOAMI_ADDR 0x0f 65 66 #define ST_LSM6DSX_TS_SENSITIVITY 25000UL /* 25us */ 67 68 static const struct iio_chan_spec st_lsm6dsx_acc_channels[] = { 69 ST_LSM6DSX_CHANNEL_ACC(IIO_ACCEL, 0x28, IIO_MOD_X, 0), 70 ST_LSM6DSX_CHANNEL_ACC(IIO_ACCEL, 0x2a, IIO_MOD_Y, 1), 71 ST_LSM6DSX_CHANNEL_ACC(IIO_ACCEL, 0x2c, IIO_MOD_Z, 2), 72 IIO_CHAN_SOFT_TIMESTAMP(3), 73 }; 74 75 static const struct iio_chan_spec st_lsm6dsx_gyro_channels[] = { 76 ST_LSM6DSX_CHANNEL(IIO_ANGL_VEL, 0x22, IIO_MOD_X, 0), 77 ST_LSM6DSX_CHANNEL(IIO_ANGL_VEL, 0x24, IIO_MOD_Y, 1), 78 ST_LSM6DSX_CHANNEL(IIO_ANGL_VEL, 0x26, IIO_MOD_Z, 2), 79 IIO_CHAN_SOFT_TIMESTAMP(3), 80 }; 81 82 static const struct iio_chan_spec st_lsm6ds0_gyro_channels[] = { 83 ST_LSM6DSX_CHANNEL(IIO_ANGL_VEL, 0x18, IIO_MOD_X, 0), 84 ST_LSM6DSX_CHANNEL(IIO_ANGL_VEL, 0x1a, IIO_MOD_Y, 1), 85 ST_LSM6DSX_CHANNEL(IIO_ANGL_VEL, 0x1c, IIO_MOD_Z, 2), 86 IIO_CHAN_SOFT_TIMESTAMP(3), 87 }; 88 89 static const struct st_lsm6dsx_settings st_lsm6dsx_sensor_settings[] = { 90 { 91 .wai = 0x68, 92 .reset = { 93 .addr = 0x22, 94 .mask = BIT(0), 95 }, 96 .boot = { 97 .addr = 0x22, 98 .mask = BIT(7), 99 }, 100 .bdu = { 101 .addr = 0x22, 102 .mask = BIT(6), 103 }, 104 .max_fifo_size = 32, 105 .id = { 106 { 107 .hw_id = ST_LSM9DS1_ID, 108 .name = ST_LSM9DS1_DEV_NAME, 109 }, { 110 .hw_id = ST_LSM6DS0_ID, 111 .name = ST_LSM6DS0_DEV_NAME, 112 }, 113 }, 114 .channels = { 115 [ST_LSM6DSX_ID_ACC] = { 116 .chan = st_lsm6dsx_acc_channels, 117 .len = ARRAY_SIZE(st_lsm6dsx_acc_channels), 118 }, 119 [ST_LSM6DSX_ID_GYRO] = { 120 .chan = st_lsm6ds0_gyro_channels, 121 .len = ARRAY_SIZE(st_lsm6ds0_gyro_channels), 122 }, 123 }, 124 .odr_table = { 125 [ST_LSM6DSX_ID_ACC] = { 126 .reg = { 127 .addr = 0x20, 128 .mask = GENMASK(7, 5), 129 }, 130 .odr_avl[0] = { 10, 0x01 }, 131 .odr_avl[1] = { 50, 0x02 }, 132 .odr_avl[2] = { 119, 0x03 }, 133 .odr_avl[3] = { 238, 0x04 }, 134 .odr_avl[4] = { 476, 0x05 }, 135 .odr_avl[5] = { 952, 0x06 }, 136 .odr_len = 6, 137 }, 138 [ST_LSM6DSX_ID_GYRO] = { 139 .reg = { 140 .addr = 0x10, 141 .mask = GENMASK(7, 5), 142 }, 143 .odr_avl[0] = { 15, 0x01 }, 144 .odr_avl[1] = { 60, 0x02 }, 145 .odr_avl[2] = { 119, 0x03 }, 146 .odr_avl[3] = { 238, 0x04 }, 147 .odr_avl[4] = { 476, 0x05 }, 148 .odr_avl[5] = { 952, 0x06 }, 149 .odr_len = 6, 150 }, 151 }, 152 .fs_table = { 153 [ST_LSM6DSX_ID_ACC] = { 154 .reg = { 155 .addr = 0x20, 156 .mask = GENMASK(4, 3), 157 }, 158 .fs_avl[0] = { IIO_G_TO_M_S_2(61), 0x0 }, 159 .fs_avl[1] = { IIO_G_TO_M_S_2(122), 0x2 }, 160 .fs_avl[2] = { IIO_G_TO_M_S_2(244), 0x3 }, 161 .fs_avl[3] = { IIO_G_TO_M_S_2(732), 0x1 }, 162 .fs_len = 4, 163 }, 164 [ST_LSM6DSX_ID_GYRO] = { 165 .reg = { 166 .addr = 0x10, 167 .mask = GENMASK(4, 3), 168 }, 169 170 .fs_avl[0] = { IIO_DEGREE_TO_RAD(8750), 0x0 }, 171 .fs_avl[1] = { IIO_DEGREE_TO_RAD(17500), 0x1 }, 172 .fs_avl[2] = { IIO_DEGREE_TO_RAD(70000), 0x3 }, 173 .fs_len = 3, 174 }, 175 }, 176 .irq_config = { 177 .irq1 = { 178 .addr = 0x0c, 179 .mask = BIT(3), 180 }, 181 .irq2 = { 182 .addr = 0x0d, 183 .mask = BIT(3), 184 }, 185 .hla = { 186 .addr = 0x22, 187 .mask = BIT(5), 188 }, 189 .od = { 190 .addr = 0x22, 191 .mask = BIT(4), 192 }, 193 }, 194 }, 195 { 196 .wai = 0x69, 197 .reset = { 198 .addr = 0x12, 199 .mask = BIT(0), 200 }, 201 .boot = { 202 .addr = 0x12, 203 .mask = BIT(7), 204 }, 205 .bdu = { 206 .addr = 0x12, 207 .mask = BIT(6), 208 }, 209 .max_fifo_size = 1365, 210 .id = { 211 { 212 .hw_id = ST_LSM6DS3_ID, 213 .name = ST_LSM6DS3_DEV_NAME, 214 }, 215 }, 216 .channels = { 217 [ST_LSM6DSX_ID_ACC] = { 218 .chan = st_lsm6dsx_acc_channels, 219 .len = ARRAY_SIZE(st_lsm6dsx_acc_channels), 220 }, 221 [ST_LSM6DSX_ID_GYRO] = { 222 .chan = st_lsm6dsx_gyro_channels, 223 .len = ARRAY_SIZE(st_lsm6dsx_gyro_channels), 224 }, 225 }, 226 .odr_table = { 227 [ST_LSM6DSX_ID_ACC] = { 228 .reg = { 229 .addr = 0x10, 230 .mask = GENMASK(7, 4), 231 }, 232 .odr_avl[0] = { 13, 0x01 }, 233 .odr_avl[1] = { 26, 0x02 }, 234 .odr_avl[2] = { 52, 0x03 }, 235 .odr_avl[3] = { 104, 0x04 }, 236 .odr_avl[4] = { 208, 0x05 }, 237 .odr_avl[5] = { 416, 0x06 }, 238 .odr_len = 6, 239 }, 240 [ST_LSM6DSX_ID_GYRO] = { 241 .reg = { 242 .addr = 0x11, 243 .mask = GENMASK(7, 4), 244 }, 245 .odr_avl[0] = { 13, 0x01 }, 246 .odr_avl[1] = { 26, 0x02 }, 247 .odr_avl[2] = { 52, 0x03 }, 248 .odr_avl[3] = { 104, 0x04 }, 249 .odr_avl[4] = { 208, 0x05 }, 250 .odr_avl[5] = { 416, 0x06 }, 251 .odr_len = 6, 252 }, 253 }, 254 .fs_table = { 255 [ST_LSM6DSX_ID_ACC] = { 256 .reg = { 257 .addr = 0x10, 258 .mask = GENMASK(3, 2), 259 }, 260 .fs_avl[0] = { IIO_G_TO_M_S_2(61), 0x0 }, 261 .fs_avl[1] = { IIO_G_TO_M_S_2(122), 0x2 }, 262 .fs_avl[2] = { IIO_G_TO_M_S_2(244), 0x3 }, 263 .fs_avl[3] = { IIO_G_TO_M_S_2(488), 0x1 }, 264 .fs_len = 4, 265 }, 266 [ST_LSM6DSX_ID_GYRO] = { 267 .reg = { 268 .addr = 0x11, 269 .mask = GENMASK(3, 2), 270 }, 271 .fs_avl[0] = { IIO_DEGREE_TO_RAD(8750), 0x0 }, 272 .fs_avl[1] = { IIO_DEGREE_TO_RAD(17500), 0x1 }, 273 .fs_avl[2] = { IIO_DEGREE_TO_RAD(35000), 0x2 }, 274 .fs_avl[3] = { IIO_DEGREE_TO_RAD(70000), 0x3 }, 275 .fs_len = 4, 276 }, 277 }, 278 .irq_config = { 279 .irq1 = { 280 .addr = 0x0d, 281 .mask = BIT(3), 282 }, 283 .irq2 = { 284 .addr = 0x0e, 285 .mask = BIT(3), 286 }, 287 .lir = { 288 .addr = 0x58, 289 .mask = BIT(0), 290 }, 291 .irq1_func = { 292 .addr = 0x5e, 293 .mask = BIT(5), 294 }, 295 .irq2_func = { 296 .addr = 0x5f, 297 .mask = BIT(5), 298 }, 299 .hla = { 300 .addr = 0x12, 301 .mask = BIT(5), 302 }, 303 .od = { 304 .addr = 0x12, 305 .mask = BIT(4), 306 }, 307 }, 308 .decimator = { 309 [ST_LSM6DSX_ID_ACC] = { 310 .addr = 0x08, 311 .mask = GENMASK(2, 0), 312 }, 313 [ST_LSM6DSX_ID_GYRO] = { 314 .addr = 0x08, 315 .mask = GENMASK(5, 3), 316 }, 317 }, 318 .fifo_ops = { 319 .update_fifo = st_lsm6dsx_update_fifo, 320 .read_fifo = st_lsm6dsx_read_fifo, 321 .fifo_th = { 322 .addr = 0x06, 323 .mask = GENMASK(11, 0), 324 }, 325 .fifo_diff = { 326 .addr = 0x3a, 327 .mask = GENMASK(11, 0), 328 }, 329 .th_wl = 3, /* 1LSB = 2B */ 330 }, 331 .ts_settings = { 332 .timer_en = { 333 .addr = 0x58, 334 .mask = BIT(7), 335 }, 336 .hr_timer = { 337 .addr = 0x5c, 338 .mask = BIT(4), 339 }, 340 .fifo_en = { 341 .addr = 0x07, 342 .mask = BIT(7), 343 }, 344 .decimator = { 345 .addr = 0x09, 346 .mask = GENMASK(5, 3), 347 }, 348 }, 349 .event_settings = { 350 .wakeup_reg = { 351 .addr = 0x5B, 352 .mask = GENMASK(5, 0), 353 }, 354 .wakeup_src_reg = 0x1b, 355 .wakeup_src_status_mask = BIT(3), 356 .wakeup_src_z_mask = BIT(0), 357 .wakeup_src_y_mask = BIT(1), 358 .wakeup_src_x_mask = BIT(2), 359 }, 360 }, 361 { 362 .wai = 0x69, 363 .reset = { 364 .addr = 0x12, 365 .mask = BIT(0), 366 }, 367 .boot = { 368 .addr = 0x12, 369 .mask = BIT(7), 370 }, 371 .bdu = { 372 .addr = 0x12, 373 .mask = BIT(6), 374 }, 375 .max_fifo_size = 682, 376 .id = { 377 { 378 .hw_id = ST_LSM6DS3H_ID, 379 .name = ST_LSM6DS3H_DEV_NAME, 380 }, 381 }, 382 .channels = { 383 [ST_LSM6DSX_ID_ACC] = { 384 .chan = st_lsm6dsx_acc_channels, 385 .len = ARRAY_SIZE(st_lsm6dsx_acc_channels), 386 }, 387 [ST_LSM6DSX_ID_GYRO] = { 388 .chan = st_lsm6dsx_gyro_channels, 389 .len = ARRAY_SIZE(st_lsm6dsx_gyro_channels), 390 }, 391 }, 392 .odr_table = { 393 [ST_LSM6DSX_ID_ACC] = { 394 .reg = { 395 .addr = 0x10, 396 .mask = GENMASK(7, 4), 397 }, 398 .odr_avl[0] = { 13, 0x01 }, 399 .odr_avl[1] = { 26, 0x02 }, 400 .odr_avl[2] = { 52, 0x03 }, 401 .odr_avl[3] = { 104, 0x04 }, 402 .odr_avl[4] = { 208, 0x05 }, 403 .odr_avl[5] = { 416, 0x06 }, 404 .odr_len = 6, 405 }, 406 [ST_LSM6DSX_ID_GYRO] = { 407 .reg = { 408 .addr = 0x11, 409 .mask = GENMASK(7, 4), 410 }, 411 .odr_avl[0] = { 13, 0x01 }, 412 .odr_avl[1] = { 26, 0x02 }, 413 .odr_avl[2] = { 52, 0x03 }, 414 .odr_avl[3] = { 104, 0x04 }, 415 .odr_avl[4] = { 208, 0x05 }, 416 .odr_avl[5] = { 416, 0x06 }, 417 .odr_len = 6, 418 }, 419 }, 420 .fs_table = { 421 [ST_LSM6DSX_ID_ACC] = { 422 .reg = { 423 .addr = 0x10, 424 .mask = GENMASK(3, 2), 425 }, 426 .fs_avl[0] = { IIO_G_TO_M_S_2(61), 0x0 }, 427 .fs_avl[1] = { IIO_G_TO_M_S_2(122), 0x2 }, 428 .fs_avl[2] = { IIO_G_TO_M_S_2(244), 0x3 }, 429 .fs_avl[3] = { IIO_G_TO_M_S_2(488), 0x1 }, 430 .fs_len = 4, 431 }, 432 [ST_LSM6DSX_ID_GYRO] = { 433 .reg = { 434 .addr = 0x11, 435 .mask = GENMASK(3, 2), 436 }, 437 .fs_avl[0] = { IIO_DEGREE_TO_RAD(8750), 0x0 }, 438 .fs_avl[1] = { IIO_DEGREE_TO_RAD(17500), 0x1 }, 439 .fs_avl[2] = { IIO_DEGREE_TO_RAD(35000), 0x2 }, 440 .fs_avl[3] = { IIO_DEGREE_TO_RAD(70000), 0x3 }, 441 .fs_len = 4, 442 }, 443 }, 444 .irq_config = { 445 .irq1 = { 446 .addr = 0x0d, 447 .mask = BIT(3), 448 }, 449 .irq2 = { 450 .addr = 0x0e, 451 .mask = BIT(3), 452 }, 453 .lir = { 454 .addr = 0x58, 455 .mask = BIT(0), 456 }, 457 .irq1_func = { 458 .addr = 0x5e, 459 .mask = BIT(5), 460 }, 461 .irq2_func = { 462 .addr = 0x5f, 463 .mask = BIT(5), 464 }, 465 .hla = { 466 .addr = 0x12, 467 .mask = BIT(5), 468 }, 469 .od = { 470 .addr = 0x12, 471 .mask = BIT(4), 472 }, 473 }, 474 .decimator = { 475 [ST_LSM6DSX_ID_ACC] = { 476 .addr = 0x08, 477 .mask = GENMASK(2, 0), 478 }, 479 [ST_LSM6DSX_ID_GYRO] = { 480 .addr = 0x08, 481 .mask = GENMASK(5, 3), 482 }, 483 }, 484 .fifo_ops = { 485 .update_fifo = st_lsm6dsx_update_fifo, 486 .read_fifo = st_lsm6dsx_read_fifo, 487 .fifo_th = { 488 .addr = 0x06, 489 .mask = GENMASK(11, 0), 490 }, 491 .fifo_diff = { 492 .addr = 0x3a, 493 .mask = GENMASK(11, 0), 494 }, 495 .th_wl = 3, /* 1LSB = 2B */ 496 }, 497 .ts_settings = { 498 .timer_en = { 499 .addr = 0x58, 500 .mask = BIT(7), 501 }, 502 .hr_timer = { 503 .addr = 0x5c, 504 .mask = BIT(4), 505 }, 506 .fifo_en = { 507 .addr = 0x07, 508 .mask = BIT(7), 509 }, 510 .decimator = { 511 .addr = 0x09, 512 .mask = GENMASK(5, 3), 513 }, 514 }, 515 .event_settings = { 516 .wakeup_reg = { 517 .addr = 0x5B, 518 .mask = GENMASK(5, 0), 519 }, 520 .wakeup_src_reg = 0x1b, 521 .wakeup_src_status_mask = BIT(3), 522 .wakeup_src_z_mask = BIT(0), 523 .wakeup_src_y_mask = BIT(1), 524 .wakeup_src_x_mask = BIT(2), 525 }, 526 }, 527 { 528 .wai = 0x6a, 529 .reset = { 530 .addr = 0x12, 531 .mask = BIT(0), 532 }, 533 .boot = { 534 .addr = 0x12, 535 .mask = BIT(7), 536 }, 537 .bdu = { 538 .addr = 0x12, 539 .mask = BIT(6), 540 }, 541 .max_fifo_size = 682, 542 .id = { 543 { 544 .hw_id = ST_LSM6DSL_ID, 545 .name = ST_LSM6DSL_DEV_NAME, 546 }, { 547 .hw_id = ST_LSM6DSM_ID, 548 .name = ST_LSM6DSM_DEV_NAME, 549 }, { 550 .hw_id = ST_ISM330DLC_ID, 551 .name = ST_ISM330DLC_DEV_NAME, 552 }, { 553 .hw_id = ST_LSM6DS3TRC_ID, 554 .name = ST_LSM6DS3TRC_DEV_NAME, 555 }, 556 }, 557 .channels = { 558 [ST_LSM6DSX_ID_ACC] = { 559 .chan = st_lsm6dsx_acc_channels, 560 .len = ARRAY_SIZE(st_lsm6dsx_acc_channels), 561 }, 562 [ST_LSM6DSX_ID_GYRO] = { 563 .chan = st_lsm6dsx_gyro_channels, 564 .len = ARRAY_SIZE(st_lsm6dsx_gyro_channels), 565 }, 566 }, 567 .odr_table = { 568 [ST_LSM6DSX_ID_ACC] = { 569 .reg = { 570 .addr = 0x10, 571 .mask = GENMASK(7, 4), 572 }, 573 .odr_avl[0] = { 13, 0x01 }, 574 .odr_avl[1] = { 26, 0x02 }, 575 .odr_avl[2] = { 52, 0x03 }, 576 .odr_avl[3] = { 104, 0x04 }, 577 .odr_avl[4] = { 208, 0x05 }, 578 .odr_avl[5] = { 416, 0x06 }, 579 .odr_len = 6, 580 }, 581 [ST_LSM6DSX_ID_GYRO] = { 582 .reg = { 583 .addr = 0x11, 584 .mask = GENMASK(7, 4), 585 }, 586 .odr_avl[0] = { 13, 0x01 }, 587 .odr_avl[1] = { 26, 0x02 }, 588 .odr_avl[2] = { 52, 0x03 }, 589 .odr_avl[3] = { 104, 0x04 }, 590 .odr_avl[4] = { 208, 0x05 }, 591 .odr_avl[5] = { 416, 0x06 }, 592 .odr_len = 6, 593 }, 594 }, 595 .fs_table = { 596 [ST_LSM6DSX_ID_ACC] = { 597 .reg = { 598 .addr = 0x10, 599 .mask = GENMASK(3, 2), 600 }, 601 .fs_avl[0] = { IIO_G_TO_M_S_2(61), 0x0 }, 602 .fs_avl[1] = { IIO_G_TO_M_S_2(122), 0x2 }, 603 .fs_avl[2] = { IIO_G_TO_M_S_2(244), 0x3 }, 604 .fs_avl[3] = { IIO_G_TO_M_S_2(488), 0x1 }, 605 .fs_len = 4, 606 }, 607 [ST_LSM6DSX_ID_GYRO] = { 608 .reg = { 609 .addr = 0x11, 610 .mask = GENMASK(3, 2), 611 }, 612 .fs_avl[0] = { IIO_DEGREE_TO_RAD(8750), 0x0 }, 613 .fs_avl[1] = { IIO_DEGREE_TO_RAD(17500), 0x1 }, 614 .fs_avl[2] = { IIO_DEGREE_TO_RAD(35000), 0x2 }, 615 .fs_avl[3] = { IIO_DEGREE_TO_RAD(70000), 0x3 }, 616 .fs_len = 4, 617 }, 618 }, 619 .irq_config = { 620 .irq1 = { 621 .addr = 0x0d, 622 .mask = BIT(3), 623 }, 624 .irq2 = { 625 .addr = 0x0e, 626 .mask = BIT(3), 627 }, 628 .lir = { 629 .addr = 0x58, 630 .mask = BIT(0), 631 }, 632 .irq1_func = { 633 .addr = 0x5e, 634 .mask = BIT(5), 635 }, 636 .irq2_func = { 637 .addr = 0x5f, 638 .mask = BIT(5), 639 }, 640 .hla = { 641 .addr = 0x12, 642 .mask = BIT(5), 643 }, 644 .od = { 645 .addr = 0x12, 646 .mask = BIT(4), 647 }, 648 }, 649 .decimator = { 650 [ST_LSM6DSX_ID_ACC] = { 651 .addr = 0x08, 652 .mask = GENMASK(2, 0), 653 }, 654 [ST_LSM6DSX_ID_GYRO] = { 655 .addr = 0x08, 656 .mask = GENMASK(5, 3), 657 }, 658 }, 659 .fifo_ops = { 660 .update_fifo = st_lsm6dsx_update_fifo, 661 .read_fifo = st_lsm6dsx_read_fifo, 662 .fifo_th = { 663 .addr = 0x06, 664 .mask = GENMASK(10, 0), 665 }, 666 .fifo_diff = { 667 .addr = 0x3a, 668 .mask = GENMASK(10, 0), 669 }, 670 .th_wl = 3, /* 1LSB = 2B */ 671 }, 672 .ts_settings = { 673 .timer_en = { 674 .addr = 0x19, 675 .mask = BIT(5), 676 }, 677 .hr_timer = { 678 .addr = 0x5c, 679 .mask = BIT(4), 680 }, 681 .fifo_en = { 682 .addr = 0x07, 683 .mask = BIT(7), 684 }, 685 .decimator = { 686 .addr = 0x09, 687 .mask = GENMASK(5, 3), 688 }, 689 }, 690 .event_settings = { 691 .enable_reg = { 692 .addr = 0x58, 693 .mask = BIT(7), 694 }, 695 .wakeup_reg = { 696 .addr = 0x5B, 697 .mask = GENMASK(5, 0), 698 }, 699 .wakeup_src_reg = 0x1b, 700 .wakeup_src_status_mask = BIT(3), 701 .wakeup_src_z_mask = BIT(0), 702 .wakeup_src_y_mask = BIT(1), 703 .wakeup_src_x_mask = BIT(2), 704 }, 705 }, 706 { 707 .wai = 0x6c, 708 .reset = { 709 .addr = 0x12, 710 .mask = BIT(0), 711 }, 712 .boot = { 713 .addr = 0x12, 714 .mask = BIT(7), 715 }, 716 .bdu = { 717 .addr = 0x12, 718 .mask = BIT(6), 719 }, 720 .max_fifo_size = 512, 721 .id = { 722 { 723 .hw_id = ST_LSM6DSO_ID, 724 .name = ST_LSM6DSO_DEV_NAME, 725 }, { 726 .hw_id = ST_LSM6DSOX_ID, 727 .name = ST_LSM6DSOX_DEV_NAME, 728 }, 729 }, 730 .channels = { 731 [ST_LSM6DSX_ID_ACC] = { 732 .chan = st_lsm6dsx_acc_channels, 733 .len = ARRAY_SIZE(st_lsm6dsx_acc_channels), 734 }, 735 [ST_LSM6DSX_ID_GYRO] = { 736 .chan = st_lsm6dsx_gyro_channels, 737 .len = ARRAY_SIZE(st_lsm6dsx_gyro_channels), 738 }, 739 }, 740 .drdy_mask = { 741 .addr = 0x13, 742 .mask = BIT(3), 743 }, 744 .odr_table = { 745 [ST_LSM6DSX_ID_ACC] = { 746 .reg = { 747 .addr = 0x10, 748 .mask = GENMASK(7, 4), 749 }, 750 .odr_avl[0] = { 13, 0x01 }, 751 .odr_avl[1] = { 26, 0x02 }, 752 .odr_avl[2] = { 52, 0x03 }, 753 .odr_avl[3] = { 104, 0x04 }, 754 .odr_avl[4] = { 208, 0x05 }, 755 .odr_avl[5] = { 416, 0x06 }, 756 .odr_len = 6, 757 }, 758 [ST_LSM6DSX_ID_GYRO] = { 759 .reg = { 760 .addr = 0x11, 761 .mask = GENMASK(7, 4), 762 }, 763 .odr_avl[0] = { 13, 0x01 }, 764 .odr_avl[1] = { 26, 0x02 }, 765 .odr_avl[2] = { 52, 0x03 }, 766 .odr_avl[3] = { 104, 0x04 }, 767 .odr_avl[4] = { 208, 0x05 }, 768 .odr_avl[5] = { 416, 0x06 }, 769 .odr_len = 6, 770 }, 771 }, 772 .fs_table = { 773 [ST_LSM6DSX_ID_ACC] = { 774 .reg = { 775 .addr = 0x10, 776 .mask = GENMASK(3, 2), 777 }, 778 .fs_avl[0] = { IIO_G_TO_M_S_2(61), 0x0 }, 779 .fs_avl[1] = { IIO_G_TO_M_S_2(122), 0x2 }, 780 .fs_avl[2] = { IIO_G_TO_M_S_2(244), 0x3 }, 781 .fs_avl[3] = { IIO_G_TO_M_S_2(488), 0x1 }, 782 .fs_len = 4, 783 }, 784 [ST_LSM6DSX_ID_GYRO] = { 785 .reg = { 786 .addr = 0x11, 787 .mask = GENMASK(3, 2), 788 }, 789 .fs_avl[0] = { IIO_DEGREE_TO_RAD(8750), 0x0 }, 790 .fs_avl[1] = { IIO_DEGREE_TO_RAD(17500), 0x1 }, 791 .fs_avl[2] = { IIO_DEGREE_TO_RAD(35000), 0x2 }, 792 .fs_avl[3] = { IIO_DEGREE_TO_RAD(70000), 0x3 }, 793 .fs_len = 4, 794 }, 795 }, 796 .irq_config = { 797 .irq1 = { 798 .addr = 0x0d, 799 .mask = BIT(3), 800 }, 801 .irq2 = { 802 .addr = 0x0e, 803 .mask = BIT(3), 804 }, 805 .lir = { 806 .addr = 0x56, 807 .mask = BIT(0), 808 }, 809 .clear_on_read = { 810 .addr = 0x56, 811 .mask = BIT(6), 812 }, 813 .irq1_func = { 814 .addr = 0x5e, 815 .mask = BIT(5), 816 }, 817 .irq2_func = { 818 .addr = 0x5f, 819 .mask = BIT(5), 820 }, 821 .hla = { 822 .addr = 0x12, 823 .mask = BIT(5), 824 }, 825 .od = { 826 .addr = 0x12, 827 .mask = BIT(4), 828 }, 829 }, 830 .batch = { 831 [ST_LSM6DSX_ID_ACC] = { 832 .addr = 0x09, 833 .mask = GENMASK(3, 0), 834 }, 835 [ST_LSM6DSX_ID_GYRO] = { 836 .addr = 0x09, 837 .mask = GENMASK(7, 4), 838 }, 839 }, 840 .fifo_ops = { 841 .update_fifo = st_lsm6dsx_update_fifo, 842 .read_fifo = st_lsm6dsx_read_tagged_fifo, 843 .fifo_th = { 844 .addr = 0x07, 845 .mask = GENMASK(8, 0), 846 }, 847 .fifo_diff = { 848 .addr = 0x3a, 849 .mask = GENMASK(9, 0), 850 }, 851 .th_wl = 1, 852 }, 853 .ts_settings = { 854 .timer_en = { 855 .addr = 0x19, 856 .mask = BIT(5), 857 }, 858 .decimator = { 859 .addr = 0x0a, 860 .mask = GENMASK(7, 6), 861 }, 862 .freq_fine = 0x63, 863 }, 864 .shub_settings = { 865 .page_mux = { 866 .addr = 0x01, 867 .mask = BIT(6), 868 }, 869 .master_en = { 870 .addr = 0x14, 871 .mask = BIT(2), 872 }, 873 .pullup_en = { 874 .addr = 0x14, 875 .mask = BIT(3), 876 }, 877 .aux_sens = { 878 .addr = 0x14, 879 .mask = GENMASK(1, 0), 880 }, 881 .wr_once = { 882 .addr = 0x14, 883 .mask = BIT(6), 884 }, 885 .shub_out = 0x02, 886 .slv0_addr = 0x15, 887 .dw_slv0_addr = 0x21, 888 .batch_en = BIT(3), 889 }, 890 .event_settings = { 891 .enable_reg = { 892 .addr = 0x58, 893 .mask = BIT(7), 894 }, 895 .wakeup_reg = { 896 .addr = 0x5b, 897 .mask = GENMASK(5, 0), 898 }, 899 .wakeup_src_reg = 0x1b, 900 .wakeup_src_status_mask = BIT(3), 901 .wakeup_src_z_mask = BIT(0), 902 .wakeup_src_y_mask = BIT(1), 903 .wakeup_src_x_mask = BIT(2), 904 }, 905 }, 906 { 907 .wai = 0x6b, 908 .reset = { 909 .addr = 0x12, 910 .mask = BIT(0), 911 }, 912 .boot = { 913 .addr = 0x12, 914 .mask = BIT(7), 915 }, 916 .bdu = { 917 .addr = 0x12, 918 .mask = BIT(6), 919 }, 920 .max_fifo_size = 512, 921 .id = { 922 { 923 .hw_id = ST_ASM330LHH_ID, 924 .name = ST_ASM330LHH_DEV_NAME, 925 }, 926 }, 927 .channels = { 928 [ST_LSM6DSX_ID_ACC] = { 929 .chan = st_lsm6dsx_acc_channels, 930 .len = ARRAY_SIZE(st_lsm6dsx_acc_channels), 931 }, 932 [ST_LSM6DSX_ID_GYRO] = { 933 .chan = st_lsm6dsx_gyro_channels, 934 .len = ARRAY_SIZE(st_lsm6dsx_gyro_channels), 935 }, 936 }, 937 .drdy_mask = { 938 .addr = 0x13, 939 .mask = BIT(3), 940 }, 941 .odr_table = { 942 [ST_LSM6DSX_ID_ACC] = { 943 .reg = { 944 .addr = 0x10, 945 .mask = GENMASK(7, 4), 946 }, 947 .odr_avl[0] = { 13, 0x01 }, 948 .odr_avl[1] = { 26, 0x02 }, 949 .odr_avl[2] = { 52, 0x03 }, 950 .odr_avl[3] = { 104, 0x04 }, 951 .odr_avl[4] = { 208, 0x05 }, 952 .odr_avl[5] = { 416, 0x06 }, 953 .odr_len = 6, 954 }, 955 [ST_LSM6DSX_ID_GYRO] = { 956 .reg = { 957 .addr = 0x11, 958 .mask = GENMASK(7, 4), 959 }, 960 .odr_avl[0] = { 13, 0x01 }, 961 .odr_avl[1] = { 26, 0x02 }, 962 .odr_avl[2] = { 52, 0x03 }, 963 .odr_avl[3] = { 104, 0x04 }, 964 .odr_avl[4] = { 208, 0x05 }, 965 .odr_avl[5] = { 416, 0x06 }, 966 .odr_len = 6, 967 }, 968 }, 969 .fs_table = { 970 [ST_LSM6DSX_ID_ACC] = { 971 .reg = { 972 .addr = 0x10, 973 .mask = GENMASK(3, 2), 974 }, 975 .fs_avl[0] = { IIO_G_TO_M_S_2(61), 0x0 }, 976 .fs_avl[1] = { IIO_G_TO_M_S_2(122), 0x2 }, 977 .fs_avl[2] = { IIO_G_TO_M_S_2(244), 0x3 }, 978 .fs_avl[3] = { IIO_G_TO_M_S_2(488), 0x1 }, 979 .fs_len = 4, 980 }, 981 [ST_LSM6DSX_ID_GYRO] = { 982 .reg = { 983 .addr = 0x11, 984 .mask = GENMASK(3, 2), 985 }, 986 .fs_avl[0] = { IIO_DEGREE_TO_RAD(8750), 0x0 }, 987 .fs_avl[1] = { IIO_DEGREE_TO_RAD(17500), 0x1 }, 988 .fs_avl[2] = { IIO_DEGREE_TO_RAD(35000), 0x2 }, 989 .fs_avl[3] = { IIO_DEGREE_TO_RAD(70000), 0x3 }, 990 .fs_len = 4, 991 }, 992 }, 993 .irq_config = { 994 .irq1 = { 995 .addr = 0x0d, 996 .mask = BIT(3), 997 }, 998 .irq2 = { 999 .addr = 0x0e, 1000 .mask = BIT(3), 1001 }, 1002 .lir = { 1003 .addr = 0x56, 1004 .mask = BIT(0), 1005 }, 1006 .clear_on_read = { 1007 .addr = 0x56, 1008 .mask = BIT(6), 1009 }, 1010 .irq1_func = { 1011 .addr = 0x5e, 1012 .mask = BIT(5), 1013 }, 1014 .irq2_func = { 1015 .addr = 0x5f, 1016 .mask = BIT(5), 1017 }, 1018 .hla = { 1019 .addr = 0x12, 1020 .mask = BIT(5), 1021 }, 1022 .od = { 1023 .addr = 0x12, 1024 .mask = BIT(4), 1025 }, 1026 }, 1027 .batch = { 1028 [ST_LSM6DSX_ID_ACC] = { 1029 .addr = 0x09, 1030 .mask = GENMASK(3, 0), 1031 }, 1032 [ST_LSM6DSX_ID_GYRO] = { 1033 .addr = 0x09, 1034 .mask = GENMASK(7, 4), 1035 }, 1036 }, 1037 .fifo_ops = { 1038 .update_fifo = st_lsm6dsx_update_fifo, 1039 .read_fifo = st_lsm6dsx_read_tagged_fifo, 1040 .fifo_th = { 1041 .addr = 0x07, 1042 .mask = GENMASK(8, 0), 1043 }, 1044 .fifo_diff = { 1045 .addr = 0x3a, 1046 .mask = GENMASK(9, 0), 1047 }, 1048 .th_wl = 1, 1049 }, 1050 .ts_settings = { 1051 .timer_en = { 1052 .addr = 0x19, 1053 .mask = BIT(5), 1054 }, 1055 .decimator = { 1056 .addr = 0x0a, 1057 .mask = GENMASK(7, 6), 1058 }, 1059 .freq_fine = 0x63, 1060 }, 1061 .event_settings = { 1062 .enable_reg = { 1063 .addr = 0x58, 1064 .mask = BIT(7), 1065 }, 1066 .wakeup_reg = { 1067 .addr = 0x5B, 1068 .mask = GENMASK(5, 0), 1069 }, 1070 .wakeup_src_reg = 0x1b, 1071 .wakeup_src_status_mask = BIT(3), 1072 .wakeup_src_z_mask = BIT(0), 1073 .wakeup_src_y_mask = BIT(1), 1074 .wakeup_src_x_mask = BIT(2), 1075 }, 1076 }, 1077 { 1078 .wai = 0x6b, 1079 .reset = { 1080 .addr = 0x12, 1081 .mask = BIT(0), 1082 }, 1083 .boot = { 1084 .addr = 0x12, 1085 .mask = BIT(7), 1086 }, 1087 .bdu = { 1088 .addr = 0x12, 1089 .mask = BIT(6), 1090 }, 1091 .max_fifo_size = 512, 1092 .id = { 1093 { 1094 .hw_id = ST_LSM6DSR_ID, 1095 .name = ST_LSM6DSR_DEV_NAME, 1096 }, { 1097 .hw_id = ST_ISM330DHCX_ID, 1098 .name = ST_ISM330DHCX_DEV_NAME, 1099 }, { 1100 .hw_id = ST_LSM6DSRX_ID, 1101 .name = ST_LSM6DSRX_DEV_NAME, 1102 }, 1103 }, 1104 .channels = { 1105 [ST_LSM6DSX_ID_ACC] = { 1106 .chan = st_lsm6dsx_acc_channels, 1107 .len = ARRAY_SIZE(st_lsm6dsx_acc_channels), 1108 }, 1109 [ST_LSM6DSX_ID_GYRO] = { 1110 .chan = st_lsm6dsx_gyro_channels, 1111 .len = ARRAY_SIZE(st_lsm6dsx_gyro_channels), 1112 }, 1113 }, 1114 .drdy_mask = { 1115 .addr = 0x13, 1116 .mask = BIT(3), 1117 }, 1118 .odr_table = { 1119 [ST_LSM6DSX_ID_ACC] = { 1120 .reg = { 1121 .addr = 0x10, 1122 .mask = GENMASK(7, 4), 1123 }, 1124 .odr_avl[0] = { 13, 0x01 }, 1125 .odr_avl[1] = { 26, 0x02 }, 1126 .odr_avl[2] = { 52, 0x03 }, 1127 .odr_avl[3] = { 104, 0x04 }, 1128 .odr_avl[4] = { 208, 0x05 }, 1129 .odr_avl[5] = { 416, 0x06 }, 1130 .odr_len = 6, 1131 }, 1132 [ST_LSM6DSX_ID_GYRO] = { 1133 .reg = { 1134 .addr = 0x11, 1135 .mask = GENMASK(7, 4), 1136 }, 1137 .odr_avl[0] = { 13, 0x01 }, 1138 .odr_avl[1] = { 26, 0x02 }, 1139 .odr_avl[2] = { 52, 0x03 }, 1140 .odr_avl[3] = { 104, 0x04 }, 1141 .odr_avl[4] = { 208, 0x05 }, 1142 .odr_avl[5] = { 416, 0x06 }, 1143 .odr_len = 6, 1144 }, 1145 }, 1146 .fs_table = { 1147 [ST_LSM6DSX_ID_ACC] = { 1148 .reg = { 1149 .addr = 0x10, 1150 .mask = GENMASK(3, 2), 1151 }, 1152 .fs_avl[0] = { IIO_G_TO_M_S_2(61), 0x0 }, 1153 .fs_avl[1] = { IIO_G_TO_M_S_2(122), 0x2 }, 1154 .fs_avl[2] = { IIO_G_TO_M_S_2(244), 0x3 }, 1155 .fs_avl[3] = { IIO_G_TO_M_S_2(488), 0x1 }, 1156 .fs_len = 4, 1157 }, 1158 [ST_LSM6DSX_ID_GYRO] = { 1159 .reg = { 1160 .addr = 0x11, 1161 .mask = GENMASK(3, 2), 1162 }, 1163 .fs_avl[0] = { IIO_DEGREE_TO_RAD(8750), 0x0 }, 1164 .fs_avl[1] = { IIO_DEGREE_TO_RAD(17500), 0x1 }, 1165 .fs_avl[2] = { IIO_DEGREE_TO_RAD(35000), 0x2 }, 1166 .fs_avl[3] = { IIO_DEGREE_TO_RAD(70000), 0x3 }, 1167 .fs_len = 4, 1168 }, 1169 }, 1170 .irq_config = { 1171 .irq1 = { 1172 .addr = 0x0d, 1173 .mask = BIT(3), 1174 }, 1175 .irq2 = { 1176 .addr = 0x0e, 1177 .mask = BIT(3), 1178 }, 1179 .lir = { 1180 .addr = 0x56, 1181 .mask = BIT(0), 1182 }, 1183 .clear_on_read = { 1184 .addr = 0x56, 1185 .mask = BIT(6), 1186 }, 1187 .irq1_func = { 1188 .addr = 0x5e, 1189 .mask = BIT(5), 1190 }, 1191 .irq2_func = { 1192 .addr = 0x5f, 1193 .mask = BIT(5), 1194 }, 1195 .hla = { 1196 .addr = 0x12, 1197 .mask = BIT(5), 1198 }, 1199 .od = { 1200 .addr = 0x12, 1201 .mask = BIT(4), 1202 }, 1203 }, 1204 .batch = { 1205 [ST_LSM6DSX_ID_ACC] = { 1206 .addr = 0x09, 1207 .mask = GENMASK(3, 0), 1208 }, 1209 [ST_LSM6DSX_ID_GYRO] = { 1210 .addr = 0x09, 1211 .mask = GENMASK(7, 4), 1212 }, 1213 }, 1214 .fifo_ops = { 1215 .update_fifo = st_lsm6dsx_update_fifo, 1216 .read_fifo = st_lsm6dsx_read_tagged_fifo, 1217 .fifo_th = { 1218 .addr = 0x07, 1219 .mask = GENMASK(8, 0), 1220 }, 1221 .fifo_diff = { 1222 .addr = 0x3a, 1223 .mask = GENMASK(9, 0), 1224 }, 1225 .th_wl = 1, 1226 }, 1227 .ts_settings = { 1228 .timer_en = { 1229 .addr = 0x19, 1230 .mask = BIT(5), 1231 }, 1232 .decimator = { 1233 .addr = 0x0a, 1234 .mask = GENMASK(7, 6), 1235 }, 1236 .freq_fine = 0x63, 1237 }, 1238 .shub_settings = { 1239 .page_mux = { 1240 .addr = 0x01, 1241 .mask = BIT(6), 1242 }, 1243 .master_en = { 1244 .addr = 0x14, 1245 .mask = BIT(2), 1246 }, 1247 .pullup_en = { 1248 .addr = 0x14, 1249 .mask = BIT(3), 1250 }, 1251 .aux_sens = { 1252 .addr = 0x14, 1253 .mask = GENMASK(1, 0), 1254 }, 1255 .wr_once = { 1256 .addr = 0x14, 1257 .mask = BIT(6), 1258 }, 1259 .shub_out = 0x02, 1260 .slv0_addr = 0x15, 1261 .dw_slv0_addr = 0x21, 1262 .batch_en = BIT(3), 1263 }, 1264 .event_settings = { 1265 .enable_reg = { 1266 .addr = 0x58, 1267 .mask = BIT(7), 1268 }, 1269 .wakeup_reg = { 1270 .addr = 0x5B, 1271 .mask = GENMASK(5, 0), 1272 }, 1273 .wakeup_src_reg = 0x1b, 1274 .wakeup_src_status_mask = BIT(3), 1275 .wakeup_src_z_mask = BIT(0), 1276 .wakeup_src_y_mask = BIT(1), 1277 .wakeup_src_x_mask = BIT(2), 1278 } 1279 }, 1280 }; 1281 1282 int st_lsm6dsx_set_page(struct st_lsm6dsx_hw *hw, bool enable) 1283 { 1284 const struct st_lsm6dsx_shub_settings *hub_settings; 1285 unsigned int data; 1286 int err; 1287 1288 hub_settings = &hw->settings->shub_settings; 1289 data = ST_LSM6DSX_SHIFT_VAL(enable, hub_settings->page_mux.mask); 1290 err = regmap_update_bits(hw->regmap, hub_settings->page_mux.addr, 1291 hub_settings->page_mux.mask, data); 1292 usleep_range(100, 150); 1293 1294 return err; 1295 } 1296 1297 static int st_lsm6dsx_check_whoami(struct st_lsm6dsx_hw *hw, int id, 1298 const char **name) 1299 { 1300 int err, i, j, data; 1301 1302 for (i = 0; i < ARRAY_SIZE(st_lsm6dsx_sensor_settings); i++) { 1303 for (j = 0; j < ST_LSM6DSX_MAX_ID; j++) { 1304 if (id == st_lsm6dsx_sensor_settings[i].id[j].hw_id) 1305 break; 1306 } 1307 if (j < ST_LSM6DSX_MAX_ID) 1308 break; 1309 } 1310 1311 if (i == ARRAY_SIZE(st_lsm6dsx_sensor_settings)) { 1312 dev_err(hw->dev, "unsupported hw id [%02x]\n", id); 1313 return -ENODEV; 1314 } 1315 1316 err = regmap_read(hw->regmap, ST_LSM6DSX_REG_WHOAMI_ADDR, &data); 1317 if (err < 0) { 1318 dev_err(hw->dev, "failed to read whoami register\n"); 1319 return err; 1320 } 1321 1322 if (data != st_lsm6dsx_sensor_settings[i].wai) { 1323 dev_err(hw->dev, "unsupported whoami [%02x]\n", data); 1324 return -ENODEV; 1325 } 1326 1327 *name = st_lsm6dsx_sensor_settings[i].id[j].name; 1328 hw->settings = &st_lsm6dsx_sensor_settings[i]; 1329 1330 return 0; 1331 } 1332 1333 static int st_lsm6dsx_set_full_scale(struct st_lsm6dsx_sensor *sensor, 1334 u32 gain) 1335 { 1336 const struct st_lsm6dsx_fs_table_entry *fs_table; 1337 unsigned int data; 1338 int i, err; 1339 1340 fs_table = &sensor->hw->settings->fs_table[sensor->id]; 1341 for (i = 0; i < fs_table->fs_len; i++) { 1342 if (fs_table->fs_avl[i].gain == gain) 1343 break; 1344 } 1345 1346 if (i == fs_table->fs_len) 1347 return -EINVAL; 1348 1349 data = ST_LSM6DSX_SHIFT_VAL(fs_table->fs_avl[i].val, 1350 fs_table->reg.mask); 1351 err = st_lsm6dsx_update_bits_locked(sensor->hw, fs_table->reg.addr, 1352 fs_table->reg.mask, data); 1353 if (err < 0) 1354 return err; 1355 1356 sensor->gain = gain; 1357 1358 return 0; 1359 } 1360 1361 int st_lsm6dsx_check_odr(struct st_lsm6dsx_sensor *sensor, u16 odr, u8 *val) 1362 { 1363 const struct st_lsm6dsx_odr_table_entry *odr_table; 1364 int i; 1365 1366 odr_table = &sensor->hw->settings->odr_table[sensor->id]; 1367 for (i = 0; i < odr_table->odr_len; i++) { 1368 /* 1369 * ext devices can run at different odr respect to 1370 * accel sensor 1371 */ 1372 if (odr_table->odr_avl[i].hz >= odr) 1373 break; 1374 } 1375 1376 if (i == odr_table->odr_len) 1377 return -EINVAL; 1378 1379 *val = odr_table->odr_avl[i].val; 1380 return odr_table->odr_avl[i].hz; 1381 } 1382 1383 static u16 st_lsm6dsx_check_odr_dependency(struct st_lsm6dsx_hw *hw, u16 odr, 1384 enum st_lsm6dsx_sensor_id id) 1385 { 1386 struct st_lsm6dsx_sensor *ref = iio_priv(hw->iio_devs[id]); 1387 1388 if (odr > 0) { 1389 if (hw->enable_mask & BIT(id)) 1390 return max_t(u16, ref->odr, odr); 1391 else 1392 return odr; 1393 } else { 1394 return (hw->enable_mask & BIT(id)) ? ref->odr : 0; 1395 } 1396 } 1397 1398 static int st_lsm6dsx_set_odr(struct st_lsm6dsx_sensor *sensor, u16 req_odr) 1399 { 1400 struct st_lsm6dsx_sensor *ref_sensor = sensor; 1401 struct st_lsm6dsx_hw *hw = sensor->hw; 1402 const struct st_lsm6dsx_reg *reg; 1403 unsigned int data; 1404 u8 val = 0; 1405 int err; 1406 1407 switch (sensor->id) { 1408 case ST_LSM6DSX_ID_EXT0: 1409 case ST_LSM6DSX_ID_EXT1: 1410 case ST_LSM6DSX_ID_EXT2: 1411 case ST_LSM6DSX_ID_ACC: { 1412 u16 odr; 1413 int i; 1414 1415 /* 1416 * i2c embedded controller relies on the accelerometer sensor as 1417 * bus read/write trigger so we need to enable accel device 1418 * at odr = max(accel_odr, ext_odr) in order to properly 1419 * communicate with i2c slave devices 1420 */ 1421 ref_sensor = iio_priv(hw->iio_devs[ST_LSM6DSX_ID_ACC]); 1422 for (i = ST_LSM6DSX_ID_ACC; i < ST_LSM6DSX_ID_MAX; i++) { 1423 if (!hw->iio_devs[i] || i == sensor->id) 1424 continue; 1425 1426 odr = st_lsm6dsx_check_odr_dependency(hw, req_odr, i); 1427 if (odr != req_odr) 1428 /* device already configured */ 1429 return 0; 1430 } 1431 break; 1432 } 1433 default: 1434 break; 1435 } 1436 1437 if (req_odr > 0) { 1438 err = st_lsm6dsx_check_odr(ref_sensor, req_odr, &val); 1439 if (err < 0) 1440 return err; 1441 } 1442 1443 reg = &hw->settings->odr_table[ref_sensor->id].reg; 1444 data = ST_LSM6DSX_SHIFT_VAL(val, reg->mask); 1445 return st_lsm6dsx_update_bits_locked(hw, reg->addr, reg->mask, data); 1446 } 1447 1448 int st_lsm6dsx_sensor_set_enable(struct st_lsm6dsx_sensor *sensor, 1449 bool enable) 1450 { 1451 struct st_lsm6dsx_hw *hw = sensor->hw; 1452 u16 odr = enable ? sensor->odr : 0; 1453 int err; 1454 1455 err = st_lsm6dsx_set_odr(sensor, odr); 1456 if (err < 0) 1457 return err; 1458 1459 if (enable) 1460 hw->enable_mask |= BIT(sensor->id); 1461 else 1462 hw->enable_mask &= ~BIT(sensor->id); 1463 1464 return 0; 1465 } 1466 1467 static int st_lsm6dsx_read_oneshot(struct st_lsm6dsx_sensor *sensor, 1468 u8 addr, int *val) 1469 { 1470 struct st_lsm6dsx_hw *hw = sensor->hw; 1471 int err, delay; 1472 __le16 data; 1473 1474 err = st_lsm6dsx_sensor_set_enable(sensor, true); 1475 if (err < 0) 1476 return err; 1477 1478 delay = 1000000 / sensor->odr; 1479 usleep_range(delay, 2 * delay); 1480 1481 err = st_lsm6dsx_read_locked(hw, addr, &data, sizeof(data)); 1482 if (err < 0) 1483 return err; 1484 1485 if (!hw->enable_event) 1486 st_lsm6dsx_sensor_set_enable(sensor, false); 1487 1488 *val = (s16)le16_to_cpu(data); 1489 1490 return IIO_VAL_INT; 1491 } 1492 1493 static int st_lsm6dsx_read_raw(struct iio_dev *iio_dev, 1494 struct iio_chan_spec const *ch, 1495 int *val, int *val2, long mask) 1496 { 1497 struct st_lsm6dsx_sensor *sensor = iio_priv(iio_dev); 1498 int ret; 1499 1500 switch (mask) { 1501 case IIO_CHAN_INFO_RAW: 1502 ret = iio_device_claim_direct_mode(iio_dev); 1503 if (ret) 1504 break; 1505 1506 ret = st_lsm6dsx_read_oneshot(sensor, ch->address, val); 1507 iio_device_release_direct_mode(iio_dev); 1508 break; 1509 case IIO_CHAN_INFO_SAMP_FREQ: 1510 *val = sensor->odr; 1511 ret = IIO_VAL_INT; 1512 break; 1513 case IIO_CHAN_INFO_SCALE: 1514 *val = 0; 1515 *val2 = sensor->gain; 1516 ret = IIO_VAL_INT_PLUS_MICRO; 1517 break; 1518 default: 1519 ret = -EINVAL; 1520 break; 1521 } 1522 1523 return ret; 1524 } 1525 1526 static int st_lsm6dsx_write_raw(struct iio_dev *iio_dev, 1527 struct iio_chan_spec const *chan, 1528 int val, int val2, long mask) 1529 { 1530 struct st_lsm6dsx_sensor *sensor = iio_priv(iio_dev); 1531 int err; 1532 1533 err = iio_device_claim_direct_mode(iio_dev); 1534 if (err) 1535 return err; 1536 1537 switch (mask) { 1538 case IIO_CHAN_INFO_SCALE: 1539 err = st_lsm6dsx_set_full_scale(sensor, val2); 1540 break; 1541 case IIO_CHAN_INFO_SAMP_FREQ: { 1542 u8 data; 1543 1544 val = st_lsm6dsx_check_odr(sensor, val, &data); 1545 if (val < 0) 1546 err = val; 1547 else 1548 sensor->odr = val; 1549 break; 1550 } 1551 default: 1552 err = -EINVAL; 1553 break; 1554 } 1555 1556 iio_device_release_direct_mode(iio_dev); 1557 1558 return err; 1559 } 1560 1561 static int st_lsm6dsx_event_setup(struct st_lsm6dsx_hw *hw, int state) 1562 { 1563 const struct st_lsm6dsx_reg *reg; 1564 unsigned int data; 1565 int err; 1566 1567 if (!hw->settings->irq_config.irq1_func.addr) 1568 return -ENOTSUPP; 1569 1570 reg = &hw->settings->event_settings.enable_reg; 1571 if (reg->addr) { 1572 data = ST_LSM6DSX_SHIFT_VAL(state, reg->mask); 1573 err = st_lsm6dsx_update_bits_locked(hw, reg->addr, 1574 reg->mask, data); 1575 if (err < 0) 1576 return err; 1577 } 1578 1579 /* Enable wakeup interrupt */ 1580 data = ST_LSM6DSX_SHIFT_VAL(state, hw->irq_routing->mask); 1581 return st_lsm6dsx_update_bits_locked(hw, hw->irq_routing->addr, 1582 hw->irq_routing->mask, data); 1583 } 1584 1585 static int st_lsm6dsx_read_event(struct iio_dev *iio_dev, 1586 const struct iio_chan_spec *chan, 1587 enum iio_event_type type, 1588 enum iio_event_direction dir, 1589 enum iio_event_info info, 1590 int *val, int *val2) 1591 { 1592 struct st_lsm6dsx_sensor *sensor = iio_priv(iio_dev); 1593 struct st_lsm6dsx_hw *hw = sensor->hw; 1594 1595 if (type != IIO_EV_TYPE_THRESH) 1596 return -EINVAL; 1597 1598 *val2 = 0; 1599 *val = hw->event_threshold; 1600 1601 return IIO_VAL_INT; 1602 } 1603 1604 static int 1605 st_lsm6dsx_write_event(struct iio_dev *iio_dev, 1606 const struct iio_chan_spec *chan, 1607 enum iio_event_type type, 1608 enum iio_event_direction dir, 1609 enum iio_event_info info, 1610 int val, int val2) 1611 { 1612 struct st_lsm6dsx_sensor *sensor = iio_priv(iio_dev); 1613 struct st_lsm6dsx_hw *hw = sensor->hw; 1614 const struct st_lsm6dsx_reg *reg; 1615 unsigned int data; 1616 int err; 1617 1618 if (type != IIO_EV_TYPE_THRESH) 1619 return -EINVAL; 1620 1621 if (val < 0 || val > 31) 1622 return -EINVAL; 1623 1624 reg = &hw->settings->event_settings.wakeup_reg; 1625 data = ST_LSM6DSX_SHIFT_VAL(val, reg->mask); 1626 err = st_lsm6dsx_update_bits_locked(hw, reg->addr, 1627 reg->mask, data); 1628 if (err < 0) 1629 return -EINVAL; 1630 1631 hw->event_threshold = val; 1632 1633 return 0; 1634 } 1635 1636 static int 1637 st_lsm6dsx_read_event_config(struct iio_dev *iio_dev, 1638 const struct iio_chan_spec *chan, 1639 enum iio_event_type type, 1640 enum iio_event_direction dir) 1641 { 1642 struct st_lsm6dsx_sensor *sensor = iio_priv(iio_dev); 1643 struct st_lsm6dsx_hw *hw = sensor->hw; 1644 1645 if (type != IIO_EV_TYPE_THRESH) 1646 return -EINVAL; 1647 1648 return !!(hw->enable_event & BIT(chan->channel2)); 1649 } 1650 1651 static int 1652 st_lsm6dsx_write_event_config(struct iio_dev *iio_dev, 1653 const struct iio_chan_spec *chan, 1654 enum iio_event_type type, 1655 enum iio_event_direction dir, int state) 1656 { 1657 struct st_lsm6dsx_sensor *sensor = iio_priv(iio_dev); 1658 struct st_lsm6dsx_hw *hw = sensor->hw; 1659 u8 enable_event; 1660 int err = 0; 1661 1662 if (type != IIO_EV_TYPE_THRESH) 1663 return -EINVAL; 1664 1665 if (state) { 1666 enable_event = hw->enable_event | BIT(chan->channel2); 1667 1668 /* do not enable events if they are already enabled */ 1669 if (hw->enable_event) 1670 goto out; 1671 } else { 1672 enable_event = hw->enable_event & ~BIT(chan->channel2); 1673 1674 /* only turn off sensor if no events is enabled */ 1675 if (enable_event) 1676 goto out; 1677 } 1678 1679 /* stop here if no changes have been made */ 1680 if (hw->enable_event == enable_event) 1681 return 0; 1682 1683 err = st_lsm6dsx_event_setup(hw, state); 1684 if (err < 0) 1685 return err; 1686 1687 mutex_lock(&hw->conf_lock); 1688 err = st_lsm6dsx_sensor_set_enable(sensor, state); 1689 mutex_unlock(&hw->conf_lock); 1690 if (err < 0) 1691 return err; 1692 1693 out: 1694 hw->enable_event = enable_event; 1695 1696 return 0; 1697 } 1698 1699 int st_lsm6dsx_set_watermark(struct iio_dev *iio_dev, unsigned int val) 1700 { 1701 struct st_lsm6dsx_sensor *sensor = iio_priv(iio_dev); 1702 struct st_lsm6dsx_hw *hw = sensor->hw; 1703 int err; 1704 1705 if (val < 1 || val > hw->settings->max_fifo_size) 1706 return -EINVAL; 1707 1708 mutex_lock(&hw->conf_lock); 1709 1710 err = st_lsm6dsx_update_watermark(sensor, val); 1711 1712 mutex_unlock(&hw->conf_lock); 1713 1714 if (err < 0) 1715 return err; 1716 1717 sensor->watermark = val; 1718 1719 return 0; 1720 } 1721 1722 static ssize_t 1723 st_lsm6dsx_sysfs_sampling_frequency_avail(struct device *dev, 1724 struct device_attribute *attr, 1725 char *buf) 1726 { 1727 struct st_lsm6dsx_sensor *sensor = iio_priv(dev_get_drvdata(dev)); 1728 const struct st_lsm6dsx_odr_table_entry *odr_table; 1729 int i, len = 0; 1730 1731 odr_table = &sensor->hw->settings->odr_table[sensor->id]; 1732 for (i = 0; i < odr_table->odr_len; i++) 1733 len += scnprintf(buf + len, PAGE_SIZE - len, "%d ", 1734 odr_table->odr_avl[i].hz); 1735 buf[len - 1] = '\n'; 1736 1737 return len; 1738 } 1739 1740 static ssize_t st_lsm6dsx_sysfs_scale_avail(struct device *dev, 1741 struct device_attribute *attr, 1742 char *buf) 1743 { 1744 struct st_lsm6dsx_sensor *sensor = iio_priv(dev_get_drvdata(dev)); 1745 const struct st_lsm6dsx_fs_table_entry *fs_table; 1746 struct st_lsm6dsx_hw *hw = sensor->hw; 1747 int i, len = 0; 1748 1749 fs_table = &hw->settings->fs_table[sensor->id]; 1750 for (i = 0; i < fs_table->fs_len; i++) 1751 len += scnprintf(buf + len, PAGE_SIZE - len, "0.%06u ", 1752 fs_table->fs_avl[i].gain); 1753 buf[len - 1] = '\n'; 1754 1755 return len; 1756 } 1757 1758 static IIO_DEV_ATTR_SAMP_FREQ_AVAIL(st_lsm6dsx_sysfs_sampling_frequency_avail); 1759 static IIO_DEVICE_ATTR(in_accel_scale_available, 0444, 1760 st_lsm6dsx_sysfs_scale_avail, NULL, 0); 1761 static IIO_DEVICE_ATTR(in_anglvel_scale_available, 0444, 1762 st_lsm6dsx_sysfs_scale_avail, NULL, 0); 1763 1764 static struct attribute *st_lsm6dsx_acc_attributes[] = { 1765 &iio_dev_attr_sampling_frequency_available.dev_attr.attr, 1766 &iio_dev_attr_in_accel_scale_available.dev_attr.attr, 1767 NULL, 1768 }; 1769 1770 static const struct attribute_group st_lsm6dsx_acc_attribute_group = { 1771 .attrs = st_lsm6dsx_acc_attributes, 1772 }; 1773 1774 static const struct iio_info st_lsm6dsx_acc_info = { 1775 .attrs = &st_lsm6dsx_acc_attribute_group, 1776 .read_raw = st_lsm6dsx_read_raw, 1777 .write_raw = st_lsm6dsx_write_raw, 1778 .read_event_value = st_lsm6dsx_read_event, 1779 .write_event_value = st_lsm6dsx_write_event, 1780 .read_event_config = st_lsm6dsx_read_event_config, 1781 .write_event_config = st_lsm6dsx_write_event_config, 1782 .hwfifo_set_watermark = st_lsm6dsx_set_watermark, 1783 }; 1784 1785 static struct attribute *st_lsm6dsx_gyro_attributes[] = { 1786 &iio_dev_attr_sampling_frequency_available.dev_attr.attr, 1787 &iio_dev_attr_in_anglvel_scale_available.dev_attr.attr, 1788 NULL, 1789 }; 1790 1791 static const struct attribute_group st_lsm6dsx_gyro_attribute_group = { 1792 .attrs = st_lsm6dsx_gyro_attributes, 1793 }; 1794 1795 static const struct iio_info st_lsm6dsx_gyro_info = { 1796 .attrs = &st_lsm6dsx_gyro_attribute_group, 1797 .read_raw = st_lsm6dsx_read_raw, 1798 .write_raw = st_lsm6dsx_write_raw, 1799 .hwfifo_set_watermark = st_lsm6dsx_set_watermark, 1800 }; 1801 1802 static int st_lsm6dsx_of_get_drdy_pin(struct st_lsm6dsx_hw *hw, int *drdy_pin) 1803 { 1804 struct device_node *np = hw->dev->of_node; 1805 1806 if (!np) 1807 return -EINVAL; 1808 1809 return of_property_read_u32(np, "st,drdy-int-pin", drdy_pin); 1810 } 1811 1812 static int 1813 st_lsm6dsx_get_drdy_reg(struct st_lsm6dsx_hw *hw, 1814 const struct st_lsm6dsx_reg **drdy_reg) 1815 { 1816 int err = 0, drdy_pin; 1817 1818 if (st_lsm6dsx_of_get_drdy_pin(hw, &drdy_pin) < 0) { 1819 struct st_sensors_platform_data *pdata; 1820 struct device *dev = hw->dev; 1821 1822 pdata = (struct st_sensors_platform_data *)dev->platform_data; 1823 drdy_pin = pdata ? pdata->drdy_int_pin : 1; 1824 } 1825 1826 switch (drdy_pin) { 1827 case 1: 1828 hw->irq_routing = &hw->settings->irq_config.irq1_func; 1829 *drdy_reg = &hw->settings->irq_config.irq1; 1830 break; 1831 case 2: 1832 hw->irq_routing = &hw->settings->irq_config.irq2_func; 1833 *drdy_reg = &hw->settings->irq_config.irq2; 1834 break; 1835 default: 1836 dev_err(hw->dev, "unsupported data ready pin\n"); 1837 err = -EINVAL; 1838 break; 1839 } 1840 1841 return err; 1842 } 1843 1844 static int st_lsm6dsx_init_shub(struct st_lsm6dsx_hw *hw) 1845 { 1846 const struct st_lsm6dsx_shub_settings *hub_settings; 1847 struct device_node *np = hw->dev->of_node; 1848 struct st_sensors_platform_data *pdata; 1849 unsigned int data; 1850 int err = 0; 1851 1852 hub_settings = &hw->settings->shub_settings; 1853 1854 pdata = (struct st_sensors_platform_data *)hw->dev->platform_data; 1855 if ((np && of_property_read_bool(np, "st,pullups")) || 1856 (pdata && pdata->pullups)) { 1857 err = st_lsm6dsx_set_page(hw, true); 1858 if (err < 0) 1859 return err; 1860 1861 data = ST_LSM6DSX_SHIFT_VAL(1, hub_settings->pullup_en.mask); 1862 err = regmap_update_bits(hw->regmap, 1863 hub_settings->pullup_en.addr, 1864 hub_settings->pullup_en.mask, data); 1865 1866 st_lsm6dsx_set_page(hw, false); 1867 1868 if (err < 0) 1869 return err; 1870 } 1871 1872 if (hub_settings->aux_sens.addr) { 1873 /* configure aux sensors */ 1874 err = st_lsm6dsx_set_page(hw, true); 1875 if (err < 0) 1876 return err; 1877 1878 data = ST_LSM6DSX_SHIFT_VAL(3, hub_settings->aux_sens.mask); 1879 err = regmap_update_bits(hw->regmap, 1880 hub_settings->aux_sens.addr, 1881 hub_settings->aux_sens.mask, data); 1882 1883 st_lsm6dsx_set_page(hw, false); 1884 } 1885 1886 return err; 1887 } 1888 1889 static int st_lsm6dsx_init_hw_timer(struct st_lsm6dsx_hw *hw) 1890 { 1891 const struct st_lsm6dsx_hw_ts_settings *ts_settings; 1892 int err, val; 1893 1894 ts_settings = &hw->settings->ts_settings; 1895 /* enable hw timestamp generation if necessary */ 1896 if (ts_settings->timer_en.addr) { 1897 val = ST_LSM6DSX_SHIFT_VAL(1, ts_settings->timer_en.mask); 1898 err = regmap_update_bits(hw->regmap, 1899 ts_settings->timer_en.addr, 1900 ts_settings->timer_en.mask, val); 1901 if (err < 0) 1902 return err; 1903 } 1904 1905 /* enable high resolution for hw ts timer if necessary */ 1906 if (ts_settings->hr_timer.addr) { 1907 val = ST_LSM6DSX_SHIFT_VAL(1, ts_settings->hr_timer.mask); 1908 err = regmap_update_bits(hw->regmap, 1909 ts_settings->hr_timer.addr, 1910 ts_settings->hr_timer.mask, val); 1911 if (err < 0) 1912 return err; 1913 } 1914 1915 /* enable ts queueing in FIFO if necessary */ 1916 if (ts_settings->fifo_en.addr) { 1917 val = ST_LSM6DSX_SHIFT_VAL(1, ts_settings->fifo_en.mask); 1918 err = regmap_update_bits(hw->regmap, 1919 ts_settings->fifo_en.addr, 1920 ts_settings->fifo_en.mask, val); 1921 if (err < 0) 1922 return err; 1923 } 1924 1925 /* calibrate timestamp sensitivity */ 1926 hw->ts_gain = ST_LSM6DSX_TS_SENSITIVITY; 1927 if (ts_settings->freq_fine) { 1928 err = regmap_read(hw->regmap, ts_settings->freq_fine, &val); 1929 if (err < 0) 1930 return err; 1931 1932 /* 1933 * linearize the AN5192 formula: 1934 * 1 / (1 + x) ~= 1 - x (Taylor’s Series) 1935 * ttrim[s] = 1 / (40000 * (1 + 0.0015 * val)) 1936 * ttrim[ns] ~= 25000 - 37.5 * val 1937 * ttrim[ns] ~= 25000 - (37500 * val) / 1000 1938 */ 1939 hw->ts_gain -= ((s8)val * 37500) / 1000; 1940 } 1941 1942 return 0; 1943 } 1944 1945 static int st_lsm6dsx_init_device(struct st_lsm6dsx_hw *hw) 1946 { 1947 const struct st_lsm6dsx_reg *reg; 1948 int err; 1949 1950 /* device sw reset */ 1951 reg = &hw->settings->reset; 1952 err = regmap_update_bits(hw->regmap, reg->addr, reg->mask, 1953 ST_LSM6DSX_SHIFT_VAL(1, reg->mask)); 1954 if (err < 0) 1955 return err; 1956 1957 msleep(50); 1958 1959 /* reload trimming parameter */ 1960 reg = &hw->settings->boot; 1961 err = regmap_update_bits(hw->regmap, reg->addr, reg->mask, 1962 ST_LSM6DSX_SHIFT_VAL(1, reg->mask)); 1963 if (err < 0) 1964 return err; 1965 1966 msleep(50); 1967 1968 /* enable Block Data Update */ 1969 reg = &hw->settings->bdu; 1970 err = regmap_update_bits(hw->regmap, reg->addr, reg->mask, 1971 ST_LSM6DSX_SHIFT_VAL(1, reg->mask)); 1972 if (err < 0) 1973 return err; 1974 1975 /* enable FIFO watermak interrupt */ 1976 err = st_lsm6dsx_get_drdy_reg(hw, ®); 1977 if (err < 0) 1978 return err; 1979 1980 err = regmap_update_bits(hw->regmap, reg->addr, reg->mask, 1981 ST_LSM6DSX_SHIFT_VAL(1, reg->mask)); 1982 if (err < 0) 1983 return err; 1984 1985 /* enable Latched interrupts for device events */ 1986 if (hw->settings->irq_config.lir.addr) { 1987 reg = &hw->settings->irq_config.lir; 1988 err = regmap_update_bits(hw->regmap, reg->addr, reg->mask, 1989 ST_LSM6DSX_SHIFT_VAL(1, reg->mask)); 1990 if (err < 0) 1991 return err; 1992 1993 /* enable clear on read for latched interrupts */ 1994 if (hw->settings->irq_config.clear_on_read.addr) { 1995 reg = &hw->settings->irq_config.clear_on_read; 1996 err = regmap_update_bits(hw->regmap, 1997 reg->addr, reg->mask, 1998 ST_LSM6DSX_SHIFT_VAL(1, reg->mask)); 1999 if (err < 0) 2000 return err; 2001 } 2002 } 2003 2004 /* enable drdy-mas if available */ 2005 if (hw->settings->drdy_mask.addr) { 2006 reg = &hw->settings->drdy_mask; 2007 err = regmap_update_bits(hw->regmap, reg->addr, reg->mask, 2008 ST_LSM6DSX_SHIFT_VAL(1, reg->mask)); 2009 if (err < 0) 2010 return err; 2011 } 2012 2013 err = st_lsm6dsx_init_shub(hw); 2014 if (err < 0) 2015 return err; 2016 2017 return st_lsm6dsx_init_hw_timer(hw); 2018 } 2019 2020 static struct iio_dev *st_lsm6dsx_alloc_iiodev(struct st_lsm6dsx_hw *hw, 2021 enum st_lsm6dsx_sensor_id id, 2022 const char *name) 2023 { 2024 struct st_lsm6dsx_sensor *sensor; 2025 struct iio_dev *iio_dev; 2026 2027 iio_dev = devm_iio_device_alloc(hw->dev, sizeof(*sensor)); 2028 if (!iio_dev) 2029 return NULL; 2030 2031 iio_dev->modes = INDIO_DIRECT_MODE; 2032 iio_dev->dev.parent = hw->dev; 2033 iio_dev->available_scan_masks = st_lsm6dsx_available_scan_masks; 2034 iio_dev->channels = hw->settings->channels[id].chan; 2035 iio_dev->num_channels = hw->settings->channels[id].len; 2036 2037 sensor = iio_priv(iio_dev); 2038 sensor->id = id; 2039 sensor->hw = hw; 2040 sensor->odr = hw->settings->odr_table[id].odr_avl[0].hz; 2041 sensor->gain = hw->settings->fs_table[id].fs_avl[0].gain; 2042 sensor->watermark = 1; 2043 2044 switch (id) { 2045 case ST_LSM6DSX_ID_ACC: 2046 iio_dev->info = &st_lsm6dsx_acc_info; 2047 scnprintf(sensor->name, sizeof(sensor->name), "%s_accel", 2048 name); 2049 break; 2050 case ST_LSM6DSX_ID_GYRO: 2051 iio_dev->info = &st_lsm6dsx_gyro_info; 2052 scnprintf(sensor->name, sizeof(sensor->name), "%s_gyro", 2053 name); 2054 break; 2055 default: 2056 return NULL; 2057 } 2058 iio_dev->name = sensor->name; 2059 2060 return iio_dev; 2061 } 2062 2063 static bool 2064 st_lsm6dsx_report_motion_event(struct st_lsm6dsx_hw *hw) 2065 { 2066 const struct st_lsm6dsx_event_settings *event_settings; 2067 int err, data; 2068 s64 timestamp; 2069 2070 if (!hw->enable_event) 2071 return false; 2072 2073 event_settings = &hw->settings->event_settings; 2074 err = st_lsm6dsx_read_locked(hw, event_settings->wakeup_src_reg, 2075 &data, sizeof(data)); 2076 if (err < 0) 2077 return false; 2078 2079 timestamp = iio_get_time_ns(hw->iio_devs[ST_LSM6DSX_ID_ACC]); 2080 if ((data & hw->settings->event_settings.wakeup_src_z_mask) && 2081 (hw->enable_event & BIT(IIO_MOD_Z))) 2082 iio_push_event(hw->iio_devs[ST_LSM6DSX_ID_ACC], 2083 IIO_MOD_EVENT_CODE(IIO_ACCEL, 2084 0, 2085 IIO_MOD_Z, 2086 IIO_EV_TYPE_THRESH, 2087 IIO_EV_DIR_EITHER), 2088 timestamp); 2089 2090 if ((data & hw->settings->event_settings.wakeup_src_y_mask) && 2091 (hw->enable_event & BIT(IIO_MOD_Y))) 2092 iio_push_event(hw->iio_devs[ST_LSM6DSX_ID_ACC], 2093 IIO_MOD_EVENT_CODE(IIO_ACCEL, 2094 0, 2095 IIO_MOD_Y, 2096 IIO_EV_TYPE_THRESH, 2097 IIO_EV_DIR_EITHER), 2098 timestamp); 2099 2100 if ((data & hw->settings->event_settings.wakeup_src_x_mask) && 2101 (hw->enable_event & BIT(IIO_MOD_X))) 2102 iio_push_event(hw->iio_devs[ST_LSM6DSX_ID_ACC], 2103 IIO_MOD_EVENT_CODE(IIO_ACCEL, 2104 0, 2105 IIO_MOD_X, 2106 IIO_EV_TYPE_THRESH, 2107 IIO_EV_DIR_EITHER), 2108 timestamp); 2109 2110 return data & event_settings->wakeup_src_status_mask; 2111 } 2112 2113 static irqreturn_t st_lsm6dsx_handler_thread(int irq, void *private) 2114 { 2115 struct st_lsm6dsx_hw *hw = private; 2116 bool event; 2117 int count; 2118 2119 event = st_lsm6dsx_report_motion_event(hw); 2120 2121 if (!hw->settings->fifo_ops.read_fifo) 2122 return event ? IRQ_HANDLED : IRQ_NONE; 2123 2124 mutex_lock(&hw->fifo_lock); 2125 count = hw->settings->fifo_ops.read_fifo(hw); 2126 mutex_unlock(&hw->fifo_lock); 2127 2128 return count || event ? IRQ_HANDLED : IRQ_NONE; 2129 } 2130 2131 static int st_lsm6dsx_irq_setup(struct st_lsm6dsx_hw *hw) 2132 { 2133 struct device_node *np = hw->dev->of_node; 2134 struct st_sensors_platform_data *pdata; 2135 const struct st_lsm6dsx_reg *reg; 2136 unsigned long irq_type; 2137 bool irq_active_low; 2138 int err; 2139 2140 irq_type = irqd_get_trigger_type(irq_get_irq_data(hw->irq)); 2141 2142 switch (irq_type) { 2143 case IRQF_TRIGGER_HIGH: 2144 case IRQF_TRIGGER_RISING: 2145 irq_active_low = false; 2146 break; 2147 case IRQF_TRIGGER_LOW: 2148 case IRQF_TRIGGER_FALLING: 2149 irq_active_low = true; 2150 break; 2151 default: 2152 dev_info(hw->dev, "mode %lx unsupported\n", irq_type); 2153 return -EINVAL; 2154 } 2155 2156 reg = &hw->settings->irq_config.hla; 2157 err = regmap_update_bits(hw->regmap, reg->addr, reg->mask, 2158 ST_LSM6DSX_SHIFT_VAL(irq_active_low, 2159 reg->mask)); 2160 if (err < 0) 2161 return err; 2162 2163 pdata = (struct st_sensors_platform_data *)hw->dev->platform_data; 2164 if ((np && of_property_read_bool(np, "drive-open-drain")) || 2165 (pdata && pdata->open_drain)) { 2166 reg = &hw->settings->irq_config.od; 2167 err = regmap_update_bits(hw->regmap, reg->addr, reg->mask, 2168 ST_LSM6DSX_SHIFT_VAL(1, reg->mask)); 2169 if (err < 0) 2170 return err; 2171 2172 irq_type |= IRQF_SHARED; 2173 } 2174 2175 err = devm_request_threaded_irq(hw->dev, hw->irq, 2176 NULL, 2177 st_lsm6dsx_handler_thread, 2178 irq_type | IRQF_ONESHOT, 2179 "lsm6dsx", hw); 2180 if (err) { 2181 dev_err(hw->dev, "failed to request trigger irq %d\n", 2182 hw->irq); 2183 return err; 2184 } 2185 2186 return 0; 2187 } 2188 2189 int st_lsm6dsx_probe(struct device *dev, int irq, int hw_id, 2190 struct regmap *regmap) 2191 { 2192 struct st_sensors_platform_data *pdata = dev->platform_data; 2193 const struct st_lsm6dsx_shub_settings *hub_settings; 2194 struct device_node *np = dev->of_node; 2195 struct st_lsm6dsx_hw *hw; 2196 const char *name = NULL; 2197 int i, err; 2198 2199 hw = devm_kzalloc(dev, sizeof(*hw), GFP_KERNEL); 2200 if (!hw) 2201 return -ENOMEM; 2202 2203 dev_set_drvdata(dev, (void *)hw); 2204 2205 mutex_init(&hw->fifo_lock); 2206 mutex_init(&hw->conf_lock); 2207 mutex_init(&hw->page_lock); 2208 2209 hw->buff = devm_kzalloc(dev, ST_LSM6DSX_BUFF_SIZE, GFP_KERNEL); 2210 if (!hw->buff) 2211 return -ENOMEM; 2212 2213 hw->dev = dev; 2214 hw->irq = irq; 2215 hw->regmap = regmap; 2216 2217 err = st_lsm6dsx_check_whoami(hw, hw_id, &name); 2218 if (err < 0) 2219 return err; 2220 2221 for (i = 0; i < ST_LSM6DSX_ID_EXT0; i++) { 2222 hw->iio_devs[i] = st_lsm6dsx_alloc_iiodev(hw, i, name); 2223 if (!hw->iio_devs[i]) 2224 return -ENOMEM; 2225 } 2226 2227 err = st_lsm6dsx_init_device(hw); 2228 if (err < 0) 2229 return err; 2230 2231 hub_settings = &hw->settings->shub_settings; 2232 if (hub_settings->master_en.addr) { 2233 err = st_lsm6dsx_shub_probe(hw, name); 2234 if (err < 0) 2235 return err; 2236 } 2237 2238 if (hw->irq > 0) { 2239 err = st_lsm6dsx_irq_setup(hw); 2240 if (err < 0) 2241 return err; 2242 2243 err = st_lsm6dsx_fifo_setup(hw); 2244 if (err < 0) 2245 return err; 2246 } 2247 2248 for (i = 0; i < ST_LSM6DSX_ID_MAX; i++) { 2249 if (!hw->iio_devs[i]) 2250 continue; 2251 2252 err = devm_iio_device_register(hw->dev, hw->iio_devs[i]); 2253 if (err) 2254 return err; 2255 } 2256 2257 if ((np && of_property_read_bool(np, "wakeup-source")) || 2258 (pdata && pdata->wakeup_source)) 2259 device_init_wakeup(dev, true); 2260 2261 return 0; 2262 } 2263 EXPORT_SYMBOL(st_lsm6dsx_probe); 2264 2265 static int __maybe_unused st_lsm6dsx_suspend(struct device *dev) 2266 { 2267 struct st_lsm6dsx_hw *hw = dev_get_drvdata(dev); 2268 struct st_lsm6dsx_sensor *sensor; 2269 int i, err = 0; 2270 2271 for (i = 0; i < ST_LSM6DSX_ID_MAX; i++) { 2272 if (!hw->iio_devs[i]) 2273 continue; 2274 2275 sensor = iio_priv(hw->iio_devs[i]); 2276 if (!(hw->enable_mask & BIT(sensor->id))) 2277 continue; 2278 2279 if (device_may_wakeup(dev) && 2280 sensor->id == ST_LSM6DSX_ID_ACC && hw->enable_event) { 2281 /* Enable wake from IRQ */ 2282 enable_irq_wake(hw->irq); 2283 continue; 2284 } 2285 2286 if (sensor->id == ST_LSM6DSX_ID_EXT0 || 2287 sensor->id == ST_LSM6DSX_ID_EXT1 || 2288 sensor->id == ST_LSM6DSX_ID_EXT2) 2289 err = st_lsm6dsx_shub_set_enable(sensor, false); 2290 else 2291 err = st_lsm6dsx_sensor_set_enable(sensor, false); 2292 if (err < 0) 2293 return err; 2294 2295 hw->suspend_mask |= BIT(sensor->id); 2296 } 2297 2298 if (hw->fifo_mode != ST_LSM6DSX_FIFO_BYPASS) 2299 err = st_lsm6dsx_flush_fifo(hw); 2300 2301 return err; 2302 } 2303 2304 static int __maybe_unused st_lsm6dsx_resume(struct device *dev) 2305 { 2306 struct st_lsm6dsx_hw *hw = dev_get_drvdata(dev); 2307 struct st_lsm6dsx_sensor *sensor; 2308 int i, err = 0; 2309 2310 for (i = 0; i < ST_LSM6DSX_ID_MAX; i++) { 2311 if (!hw->iio_devs[i]) 2312 continue; 2313 2314 sensor = iio_priv(hw->iio_devs[i]); 2315 if (device_may_wakeup(dev) && 2316 sensor->id == ST_LSM6DSX_ID_ACC && hw->enable_event) 2317 disable_irq_wake(hw->irq); 2318 2319 if (!(hw->suspend_mask & BIT(sensor->id))) 2320 continue; 2321 2322 if (sensor->id == ST_LSM6DSX_ID_EXT0 || 2323 sensor->id == ST_LSM6DSX_ID_EXT1 || 2324 sensor->id == ST_LSM6DSX_ID_EXT2) 2325 err = st_lsm6dsx_shub_set_enable(sensor, true); 2326 else 2327 err = st_lsm6dsx_sensor_set_enable(sensor, true); 2328 if (err < 0) 2329 return err; 2330 2331 hw->suspend_mask &= ~BIT(sensor->id); 2332 } 2333 2334 if (hw->enable_mask) 2335 err = st_lsm6dsx_set_fifo_mode(hw, ST_LSM6DSX_FIFO_CONT); 2336 2337 return err; 2338 } 2339 2340 const struct dev_pm_ops st_lsm6dsx_pm_ops = { 2341 SET_SYSTEM_SLEEP_PM_OPS(st_lsm6dsx_suspend, st_lsm6dsx_resume) 2342 }; 2343 EXPORT_SYMBOL(st_lsm6dsx_pm_ops); 2344 2345 MODULE_AUTHOR("Lorenzo Bianconi <lorenzo.bianconi@st.com>"); 2346 MODULE_AUTHOR("Denis Ciocca <denis.ciocca@st.com>"); 2347 MODULE_DESCRIPTION("STMicroelectronics st_lsm6dsx driver"); 2348 MODULE_LICENSE("GPL v2"); 2349