1 // SPDX-License-Identifier: GPL-2.0-only 2 /* 3 * STMicroelectronics st_lsm6dsx sensor driver 4 * 5 * The ST LSM6DSx IMU MEMS series consists of 3D digital accelerometer 6 * and 3D digital gyroscope system-in-package with a digital I2C/SPI serial 7 * interface standard output. 8 * LSM6DSx IMU MEMS series has a dynamic user-selectable full-scale 9 * acceleration range of +-2/+-4/+-8/+-16 g and an angular rate range of 10 * +-125/+-245/+-500/+-1000/+-2000 dps 11 * LSM6DSx series has an integrated First-In-First-Out (FIFO) buffer 12 * allowing dynamic batching of sensor data. 13 * LSM9DSx series is similar but includes an additional magnetometer, handled 14 * by a different driver. 15 * 16 * Supported sensors: 17 * - LSM6DS3: 18 * - Accelerometer/Gyroscope supported ODR [Hz]: 13, 26, 52, 104, 208, 416 19 * - Accelerometer supported full-scale [g]: +-2/+-4/+-8/+-16 20 * - Gyroscope supported full-scale [dps]: +-125/+-245/+-500/+-1000/+-2000 21 * - FIFO size: 8KB 22 * 23 * - LSM6DS3H/LSM6DSL/LSM6DSM/ISM330DLC/LSM6DS3TR-C: 24 * - Accelerometer/Gyroscope supported ODR [Hz]: 13, 26, 52, 104, 208, 416 25 * - Accelerometer supported full-scale [g]: +-2/+-4/+-8/+-16 26 * - Gyroscope supported full-scale [dps]: +-125/+-245/+-500/+-1000/+-2000 27 * - FIFO size: 4KB 28 * 29 * - LSM6DSO/LSM6DSOX/ASM330LHH/LSM6DSR/ISM330DHCX: 30 * - Accelerometer/Gyroscope supported ODR [Hz]: 13, 26, 52, 104, 208, 416 31 * - Accelerometer supported full-scale [g]: +-2/+-4/+-8/+-16 32 * - Gyroscope supported full-scale [dps]: +-125/+-245/+-500/+-1000/+-2000 33 * - FIFO size: 3KB 34 * 35 * - LSM9DS1/LSM6DS0: 36 * - Accelerometer supported ODR [Hz]: 10, 50, 119, 238, 476, 952 37 * - Accelerometer supported full-scale [g]: +-2/+-4/+-8/+-16 38 * - Gyroscope supported ODR [Hz]: 15, 60, 119, 238, 476, 952 39 * - Gyroscope supported full-scale [dps]: +-245/+-500/+-2000 40 * - FIFO size: 32 41 * 42 * Copyright 2016 STMicroelectronics Inc. 43 * 44 * Lorenzo Bianconi <lorenzo.bianconi@st.com> 45 * Denis Ciocca <denis.ciocca@st.com> 46 */ 47 48 #include <linux/kernel.h> 49 #include <linux/module.h> 50 #include <linux/delay.h> 51 #include <linux/iio/events.h> 52 #include <linux/iio/iio.h> 53 #include <linux/iio/sysfs.h> 54 #include <linux/interrupt.h> 55 #include <linux/irq.h> 56 #include <linux/pm.h> 57 #include <linux/regmap.h> 58 #include <linux/bitfield.h> 59 60 #include <linux/platform_data/st_sensors_pdata.h> 61 62 #include "st_lsm6dsx.h" 63 64 #define ST_LSM6DSX_REG_WHOAMI_ADDR 0x0f 65 66 #define ST_LSM6DSX_TS_SENSITIVITY 25000UL /* 25us */ 67 68 static const struct iio_chan_spec st_lsm6dsx_acc_channels[] = { 69 ST_LSM6DSX_CHANNEL_ACC(IIO_ACCEL, 0x28, IIO_MOD_X, 0), 70 ST_LSM6DSX_CHANNEL_ACC(IIO_ACCEL, 0x2a, IIO_MOD_Y, 1), 71 ST_LSM6DSX_CHANNEL_ACC(IIO_ACCEL, 0x2c, IIO_MOD_Z, 2), 72 IIO_CHAN_SOFT_TIMESTAMP(3), 73 }; 74 75 static const struct iio_chan_spec st_lsm6dsx_gyro_channels[] = { 76 ST_LSM6DSX_CHANNEL(IIO_ANGL_VEL, 0x22, IIO_MOD_X, 0), 77 ST_LSM6DSX_CHANNEL(IIO_ANGL_VEL, 0x24, IIO_MOD_Y, 1), 78 ST_LSM6DSX_CHANNEL(IIO_ANGL_VEL, 0x26, IIO_MOD_Z, 2), 79 IIO_CHAN_SOFT_TIMESTAMP(3), 80 }; 81 82 static const struct iio_chan_spec st_lsm6ds0_gyro_channels[] = { 83 ST_LSM6DSX_CHANNEL(IIO_ANGL_VEL, 0x18, IIO_MOD_X, 0), 84 ST_LSM6DSX_CHANNEL(IIO_ANGL_VEL, 0x1a, IIO_MOD_Y, 1), 85 ST_LSM6DSX_CHANNEL(IIO_ANGL_VEL, 0x1c, IIO_MOD_Z, 2), 86 IIO_CHAN_SOFT_TIMESTAMP(3), 87 }; 88 89 static const struct st_lsm6dsx_settings st_lsm6dsx_sensor_settings[] = { 90 { 91 .wai = 0x68, 92 .reset = { 93 .addr = 0x22, 94 .mask = BIT(0), 95 }, 96 .boot = { 97 .addr = 0x22, 98 .mask = BIT(7), 99 }, 100 .bdu = { 101 .addr = 0x22, 102 .mask = BIT(6), 103 }, 104 .max_fifo_size = 32, 105 .id = { 106 { 107 .hw_id = ST_LSM9DS1_ID, 108 .name = ST_LSM9DS1_DEV_NAME, 109 }, { 110 .hw_id = ST_LSM6DS0_ID, 111 .name = ST_LSM6DS0_DEV_NAME, 112 }, 113 }, 114 .channels = { 115 [ST_LSM6DSX_ID_ACC] = { 116 .chan = st_lsm6dsx_acc_channels, 117 .len = ARRAY_SIZE(st_lsm6dsx_acc_channels), 118 }, 119 [ST_LSM6DSX_ID_GYRO] = { 120 .chan = st_lsm6ds0_gyro_channels, 121 .len = ARRAY_SIZE(st_lsm6ds0_gyro_channels), 122 }, 123 }, 124 .odr_table = { 125 [ST_LSM6DSX_ID_ACC] = { 126 .reg = { 127 .addr = 0x20, 128 .mask = GENMASK(7, 5), 129 }, 130 .odr_avl[0] = { 10, 0x01 }, 131 .odr_avl[1] = { 50, 0x02 }, 132 .odr_avl[2] = { 119, 0x03 }, 133 .odr_avl[3] = { 238, 0x04 }, 134 .odr_avl[4] = { 476, 0x05 }, 135 .odr_avl[5] = { 952, 0x06 }, 136 }, 137 [ST_LSM6DSX_ID_GYRO] = { 138 .reg = { 139 .addr = 0x10, 140 .mask = GENMASK(7, 5), 141 }, 142 .odr_avl[0] = { 15, 0x01 }, 143 .odr_avl[1] = { 60, 0x02 }, 144 .odr_avl[2] = { 119, 0x03 }, 145 .odr_avl[3] = { 238, 0x04 }, 146 .odr_avl[4] = { 476, 0x05 }, 147 .odr_avl[5] = { 952, 0x06 }, 148 }, 149 }, 150 .fs_table = { 151 [ST_LSM6DSX_ID_ACC] = { 152 .reg = { 153 .addr = 0x20, 154 .mask = GENMASK(4, 3), 155 }, 156 .fs_avl[0] = { IIO_G_TO_M_S_2(61), 0x0 }, 157 .fs_avl[1] = { IIO_G_TO_M_S_2(122), 0x2 }, 158 .fs_avl[2] = { IIO_G_TO_M_S_2(244), 0x3 }, 159 .fs_avl[3] = { IIO_G_TO_M_S_2(732), 0x1 }, 160 .fs_len = 4, 161 }, 162 [ST_LSM6DSX_ID_GYRO] = { 163 .reg = { 164 .addr = 0x10, 165 .mask = GENMASK(4, 3), 166 }, 167 168 .fs_avl[0] = { IIO_DEGREE_TO_RAD(8750), 0x0 }, 169 .fs_avl[1] = { IIO_DEGREE_TO_RAD(17500), 0x1 }, 170 .fs_avl[2] = { IIO_DEGREE_TO_RAD(70000), 0x3 }, 171 .fs_len = 3, 172 }, 173 }, 174 .irq_config = { 175 .irq1 = { 176 .addr = 0x0c, 177 .mask = BIT(3), 178 }, 179 .irq2 = { 180 .addr = 0x0d, 181 .mask = BIT(3), 182 }, 183 .hla = { 184 .addr = 0x22, 185 .mask = BIT(5), 186 }, 187 .od = { 188 .addr = 0x22, 189 .mask = BIT(4), 190 }, 191 }, 192 }, 193 { 194 .wai = 0x69, 195 .reset = { 196 .addr = 0x12, 197 .mask = BIT(0), 198 }, 199 .boot = { 200 .addr = 0x12, 201 .mask = BIT(7), 202 }, 203 .bdu = { 204 .addr = 0x12, 205 .mask = BIT(6), 206 }, 207 .max_fifo_size = 1365, 208 .id = { 209 { 210 .hw_id = ST_LSM6DS3_ID, 211 .name = ST_LSM6DS3_DEV_NAME, 212 }, 213 }, 214 .channels = { 215 [ST_LSM6DSX_ID_ACC] = { 216 .chan = st_lsm6dsx_acc_channels, 217 .len = ARRAY_SIZE(st_lsm6dsx_acc_channels), 218 }, 219 [ST_LSM6DSX_ID_GYRO] = { 220 .chan = st_lsm6dsx_gyro_channels, 221 .len = ARRAY_SIZE(st_lsm6dsx_gyro_channels), 222 }, 223 }, 224 .odr_table = { 225 [ST_LSM6DSX_ID_ACC] = { 226 .reg = { 227 .addr = 0x10, 228 .mask = GENMASK(7, 4), 229 }, 230 .odr_avl[0] = { 13, 0x01 }, 231 .odr_avl[1] = { 26, 0x02 }, 232 .odr_avl[2] = { 52, 0x03 }, 233 .odr_avl[3] = { 104, 0x04 }, 234 .odr_avl[4] = { 208, 0x05 }, 235 .odr_avl[5] = { 416, 0x06 }, 236 }, 237 [ST_LSM6DSX_ID_GYRO] = { 238 .reg = { 239 .addr = 0x11, 240 .mask = GENMASK(7, 4), 241 }, 242 .odr_avl[0] = { 13, 0x01 }, 243 .odr_avl[1] = { 26, 0x02 }, 244 .odr_avl[2] = { 52, 0x03 }, 245 .odr_avl[3] = { 104, 0x04 }, 246 .odr_avl[4] = { 208, 0x05 }, 247 .odr_avl[5] = { 416, 0x06 }, 248 }, 249 }, 250 .fs_table = { 251 [ST_LSM6DSX_ID_ACC] = { 252 .reg = { 253 .addr = 0x10, 254 .mask = GENMASK(3, 2), 255 }, 256 .fs_avl[0] = { IIO_G_TO_M_S_2(61), 0x0 }, 257 .fs_avl[1] = { IIO_G_TO_M_S_2(122), 0x2 }, 258 .fs_avl[2] = { IIO_G_TO_M_S_2(244), 0x3 }, 259 .fs_avl[3] = { IIO_G_TO_M_S_2(488), 0x1 }, 260 .fs_len = 4, 261 }, 262 [ST_LSM6DSX_ID_GYRO] = { 263 .reg = { 264 .addr = 0x11, 265 .mask = GENMASK(3, 2), 266 }, 267 .fs_avl[0] = { IIO_DEGREE_TO_RAD(8750), 0x0 }, 268 .fs_avl[1] = { IIO_DEGREE_TO_RAD(17500), 0x1 }, 269 .fs_avl[2] = { IIO_DEGREE_TO_RAD(35000), 0x2 }, 270 .fs_avl[3] = { IIO_DEGREE_TO_RAD(70000), 0x3 }, 271 .fs_len = 4, 272 }, 273 }, 274 .irq_config = { 275 .irq1 = { 276 .addr = 0x0d, 277 .mask = BIT(3), 278 }, 279 .irq2 = { 280 .addr = 0x0e, 281 .mask = BIT(3), 282 }, 283 .lir = { 284 .addr = 0x58, 285 .mask = BIT(0), 286 }, 287 .irq1_func = { 288 .addr = 0x5e, 289 .mask = BIT(5), 290 }, 291 .irq2_func = { 292 .addr = 0x5f, 293 .mask = BIT(5), 294 }, 295 .hla = { 296 .addr = 0x12, 297 .mask = BIT(5), 298 }, 299 .od = { 300 .addr = 0x12, 301 .mask = BIT(4), 302 }, 303 }, 304 .decimator = { 305 [ST_LSM6DSX_ID_ACC] = { 306 .addr = 0x08, 307 .mask = GENMASK(2, 0), 308 }, 309 [ST_LSM6DSX_ID_GYRO] = { 310 .addr = 0x08, 311 .mask = GENMASK(5, 3), 312 }, 313 }, 314 .fifo_ops = { 315 .update_fifo = st_lsm6dsx_update_fifo, 316 .read_fifo = st_lsm6dsx_read_fifo, 317 .fifo_th = { 318 .addr = 0x06, 319 .mask = GENMASK(11, 0), 320 }, 321 .fifo_diff = { 322 .addr = 0x3a, 323 .mask = GENMASK(11, 0), 324 }, 325 .th_wl = 3, /* 1LSB = 2B */ 326 }, 327 .ts_settings = { 328 .timer_en = { 329 .addr = 0x58, 330 .mask = BIT(7), 331 }, 332 .hr_timer = { 333 .addr = 0x5c, 334 .mask = BIT(4), 335 }, 336 .fifo_en = { 337 .addr = 0x07, 338 .mask = BIT(7), 339 }, 340 .decimator = { 341 .addr = 0x09, 342 .mask = GENMASK(5, 3), 343 }, 344 }, 345 .event_settings = { 346 .wakeup_reg = { 347 .addr = 0x5B, 348 .mask = GENMASK(5, 0), 349 }, 350 .wakeup_src_reg = 0x1b, 351 .wakeup_src_status_mask = BIT(3), 352 .wakeup_src_z_mask = BIT(0), 353 .wakeup_src_y_mask = BIT(1), 354 .wakeup_src_x_mask = BIT(2), 355 }, 356 }, 357 { 358 .wai = 0x69, 359 .reset = { 360 .addr = 0x12, 361 .mask = BIT(0), 362 }, 363 .boot = { 364 .addr = 0x12, 365 .mask = BIT(7), 366 }, 367 .bdu = { 368 .addr = 0x12, 369 .mask = BIT(6), 370 }, 371 .max_fifo_size = 682, 372 .id = { 373 { 374 .hw_id = ST_LSM6DS3H_ID, 375 .name = ST_LSM6DS3H_DEV_NAME, 376 }, 377 }, 378 .channels = { 379 [ST_LSM6DSX_ID_ACC] = { 380 .chan = st_lsm6dsx_acc_channels, 381 .len = ARRAY_SIZE(st_lsm6dsx_acc_channels), 382 }, 383 [ST_LSM6DSX_ID_GYRO] = { 384 .chan = st_lsm6dsx_gyro_channels, 385 .len = ARRAY_SIZE(st_lsm6dsx_gyro_channels), 386 }, 387 }, 388 .odr_table = { 389 [ST_LSM6DSX_ID_ACC] = { 390 .reg = { 391 .addr = 0x10, 392 .mask = GENMASK(7, 4), 393 }, 394 .odr_avl[0] = { 13, 0x01 }, 395 .odr_avl[1] = { 26, 0x02 }, 396 .odr_avl[2] = { 52, 0x03 }, 397 .odr_avl[3] = { 104, 0x04 }, 398 .odr_avl[4] = { 208, 0x05 }, 399 .odr_avl[5] = { 416, 0x06 }, 400 }, 401 [ST_LSM6DSX_ID_GYRO] = { 402 .reg = { 403 .addr = 0x11, 404 .mask = GENMASK(7, 4), 405 }, 406 .odr_avl[0] = { 13, 0x01 }, 407 .odr_avl[1] = { 26, 0x02 }, 408 .odr_avl[2] = { 52, 0x03 }, 409 .odr_avl[3] = { 104, 0x04 }, 410 .odr_avl[4] = { 208, 0x05 }, 411 .odr_avl[5] = { 416, 0x06 }, 412 }, 413 }, 414 .fs_table = { 415 [ST_LSM6DSX_ID_ACC] = { 416 .reg = { 417 .addr = 0x10, 418 .mask = GENMASK(3, 2), 419 }, 420 .fs_avl[0] = { IIO_G_TO_M_S_2(61), 0x0 }, 421 .fs_avl[1] = { IIO_G_TO_M_S_2(122), 0x2 }, 422 .fs_avl[2] = { IIO_G_TO_M_S_2(244), 0x3 }, 423 .fs_avl[3] = { IIO_G_TO_M_S_2(488), 0x1 }, 424 .fs_len = 4, 425 }, 426 [ST_LSM6DSX_ID_GYRO] = { 427 .reg = { 428 .addr = 0x11, 429 .mask = GENMASK(3, 2), 430 }, 431 .fs_avl[0] = { IIO_DEGREE_TO_RAD(8750), 0x0 }, 432 .fs_avl[1] = { IIO_DEGREE_TO_RAD(17500), 0x1 }, 433 .fs_avl[2] = { IIO_DEGREE_TO_RAD(35000), 0x2 }, 434 .fs_avl[3] = { IIO_DEGREE_TO_RAD(70000), 0x3 }, 435 .fs_len = 4, 436 }, 437 }, 438 .irq_config = { 439 .irq1 = { 440 .addr = 0x0d, 441 .mask = BIT(3), 442 }, 443 .irq2 = { 444 .addr = 0x0e, 445 .mask = BIT(3), 446 }, 447 .lir = { 448 .addr = 0x58, 449 .mask = BIT(0), 450 }, 451 .irq1_func = { 452 .addr = 0x5e, 453 .mask = BIT(5), 454 }, 455 .irq2_func = { 456 .addr = 0x5f, 457 .mask = BIT(5), 458 }, 459 .hla = { 460 .addr = 0x12, 461 .mask = BIT(5), 462 }, 463 .od = { 464 .addr = 0x12, 465 .mask = BIT(4), 466 }, 467 }, 468 .decimator = { 469 [ST_LSM6DSX_ID_ACC] = { 470 .addr = 0x08, 471 .mask = GENMASK(2, 0), 472 }, 473 [ST_LSM6DSX_ID_GYRO] = { 474 .addr = 0x08, 475 .mask = GENMASK(5, 3), 476 }, 477 }, 478 .fifo_ops = { 479 .update_fifo = st_lsm6dsx_update_fifo, 480 .read_fifo = st_lsm6dsx_read_fifo, 481 .fifo_th = { 482 .addr = 0x06, 483 .mask = GENMASK(11, 0), 484 }, 485 .fifo_diff = { 486 .addr = 0x3a, 487 .mask = GENMASK(11, 0), 488 }, 489 .th_wl = 3, /* 1LSB = 2B */ 490 }, 491 .ts_settings = { 492 .timer_en = { 493 .addr = 0x58, 494 .mask = BIT(7), 495 }, 496 .hr_timer = { 497 .addr = 0x5c, 498 .mask = BIT(4), 499 }, 500 .fifo_en = { 501 .addr = 0x07, 502 .mask = BIT(7), 503 }, 504 .decimator = { 505 .addr = 0x09, 506 .mask = GENMASK(5, 3), 507 }, 508 }, 509 .event_settings = { 510 .wakeup_reg = { 511 .addr = 0x5B, 512 .mask = GENMASK(5, 0), 513 }, 514 .wakeup_src_reg = 0x1b, 515 .wakeup_src_status_mask = BIT(3), 516 .wakeup_src_z_mask = BIT(0), 517 .wakeup_src_y_mask = BIT(1), 518 .wakeup_src_x_mask = BIT(2), 519 }, 520 }, 521 { 522 .wai = 0x6a, 523 .reset = { 524 .addr = 0x12, 525 .mask = BIT(0), 526 }, 527 .boot = { 528 .addr = 0x12, 529 .mask = BIT(7), 530 }, 531 .bdu = { 532 .addr = 0x12, 533 .mask = BIT(6), 534 }, 535 .max_fifo_size = 682, 536 .id = { 537 { 538 .hw_id = ST_LSM6DSL_ID, 539 .name = ST_LSM6DSL_DEV_NAME, 540 }, { 541 .hw_id = ST_LSM6DSM_ID, 542 .name = ST_LSM6DSM_DEV_NAME, 543 }, { 544 .hw_id = ST_ISM330DLC_ID, 545 .name = ST_ISM330DLC_DEV_NAME, 546 }, { 547 .hw_id = ST_LSM6DS3TRC_ID, 548 .name = ST_LSM6DS3TRC_DEV_NAME, 549 }, 550 }, 551 .channels = { 552 [ST_LSM6DSX_ID_ACC] = { 553 .chan = st_lsm6dsx_acc_channels, 554 .len = ARRAY_SIZE(st_lsm6dsx_acc_channels), 555 }, 556 [ST_LSM6DSX_ID_GYRO] = { 557 .chan = st_lsm6dsx_gyro_channels, 558 .len = ARRAY_SIZE(st_lsm6dsx_gyro_channels), 559 }, 560 }, 561 .odr_table = { 562 [ST_LSM6DSX_ID_ACC] = { 563 .reg = { 564 .addr = 0x10, 565 .mask = GENMASK(7, 4), 566 }, 567 .odr_avl[0] = { 13, 0x01 }, 568 .odr_avl[1] = { 26, 0x02 }, 569 .odr_avl[2] = { 52, 0x03 }, 570 .odr_avl[3] = { 104, 0x04 }, 571 .odr_avl[4] = { 208, 0x05 }, 572 .odr_avl[5] = { 416, 0x06 }, 573 }, 574 [ST_LSM6DSX_ID_GYRO] = { 575 .reg = { 576 .addr = 0x11, 577 .mask = GENMASK(7, 4), 578 }, 579 .odr_avl[0] = { 13, 0x01 }, 580 .odr_avl[1] = { 26, 0x02 }, 581 .odr_avl[2] = { 52, 0x03 }, 582 .odr_avl[3] = { 104, 0x04 }, 583 .odr_avl[4] = { 208, 0x05 }, 584 .odr_avl[5] = { 416, 0x06 }, 585 }, 586 }, 587 .fs_table = { 588 [ST_LSM6DSX_ID_ACC] = { 589 .reg = { 590 .addr = 0x10, 591 .mask = GENMASK(3, 2), 592 }, 593 .fs_avl[0] = { IIO_G_TO_M_S_2(61), 0x0 }, 594 .fs_avl[1] = { IIO_G_TO_M_S_2(122), 0x2 }, 595 .fs_avl[2] = { IIO_G_TO_M_S_2(244), 0x3 }, 596 .fs_avl[3] = { IIO_G_TO_M_S_2(488), 0x1 }, 597 .fs_len = 4, 598 }, 599 [ST_LSM6DSX_ID_GYRO] = { 600 .reg = { 601 .addr = 0x11, 602 .mask = GENMASK(3, 2), 603 }, 604 .fs_avl[0] = { IIO_DEGREE_TO_RAD(8750), 0x0 }, 605 .fs_avl[1] = { IIO_DEGREE_TO_RAD(17500), 0x1 }, 606 .fs_avl[2] = { IIO_DEGREE_TO_RAD(35000), 0x2 }, 607 .fs_avl[3] = { IIO_DEGREE_TO_RAD(70000), 0x3 }, 608 .fs_len = 4, 609 }, 610 }, 611 .irq_config = { 612 .irq1 = { 613 .addr = 0x0d, 614 .mask = BIT(3), 615 }, 616 .irq2 = { 617 .addr = 0x0e, 618 .mask = BIT(3), 619 }, 620 .lir = { 621 .addr = 0x58, 622 .mask = BIT(0), 623 }, 624 .irq1_func = { 625 .addr = 0x5e, 626 .mask = BIT(5), 627 }, 628 .irq2_func = { 629 .addr = 0x5f, 630 .mask = BIT(5), 631 }, 632 .hla = { 633 .addr = 0x12, 634 .mask = BIT(5), 635 }, 636 .od = { 637 .addr = 0x12, 638 .mask = BIT(4), 639 }, 640 }, 641 .decimator = { 642 [ST_LSM6DSX_ID_ACC] = { 643 .addr = 0x08, 644 .mask = GENMASK(2, 0), 645 }, 646 [ST_LSM6DSX_ID_GYRO] = { 647 .addr = 0x08, 648 .mask = GENMASK(5, 3), 649 }, 650 }, 651 .fifo_ops = { 652 .update_fifo = st_lsm6dsx_update_fifo, 653 .read_fifo = st_lsm6dsx_read_fifo, 654 .fifo_th = { 655 .addr = 0x06, 656 .mask = GENMASK(10, 0), 657 }, 658 .fifo_diff = { 659 .addr = 0x3a, 660 .mask = GENMASK(10, 0), 661 }, 662 .th_wl = 3, /* 1LSB = 2B */ 663 }, 664 .ts_settings = { 665 .timer_en = { 666 .addr = 0x19, 667 .mask = BIT(5), 668 }, 669 .hr_timer = { 670 .addr = 0x5c, 671 .mask = BIT(4), 672 }, 673 .fifo_en = { 674 .addr = 0x07, 675 .mask = BIT(7), 676 }, 677 .decimator = { 678 .addr = 0x09, 679 .mask = GENMASK(5, 3), 680 }, 681 }, 682 .event_settings = { 683 .enable_reg = { 684 .addr = 0x58, 685 .mask = BIT(7), 686 }, 687 .wakeup_reg = { 688 .addr = 0x5B, 689 .mask = GENMASK(5, 0), 690 }, 691 .wakeup_src_reg = 0x1b, 692 .wakeup_src_status_mask = BIT(3), 693 .wakeup_src_z_mask = BIT(0), 694 .wakeup_src_y_mask = BIT(1), 695 .wakeup_src_x_mask = BIT(2), 696 }, 697 }, 698 { 699 .wai = 0x6c, 700 .reset = { 701 .addr = 0x12, 702 .mask = BIT(0), 703 }, 704 .boot = { 705 .addr = 0x12, 706 .mask = BIT(7), 707 }, 708 .bdu = { 709 .addr = 0x12, 710 .mask = BIT(6), 711 }, 712 .max_fifo_size = 512, 713 .id = { 714 { 715 .hw_id = ST_LSM6DSO_ID, 716 .name = ST_LSM6DSO_DEV_NAME, 717 }, { 718 .hw_id = ST_LSM6DSOX_ID, 719 .name = ST_LSM6DSOX_DEV_NAME, 720 }, 721 }, 722 .channels = { 723 [ST_LSM6DSX_ID_ACC] = { 724 .chan = st_lsm6dsx_acc_channels, 725 .len = ARRAY_SIZE(st_lsm6dsx_acc_channels), 726 }, 727 [ST_LSM6DSX_ID_GYRO] = { 728 .chan = st_lsm6dsx_gyro_channels, 729 .len = ARRAY_SIZE(st_lsm6dsx_gyro_channels), 730 }, 731 }, 732 .drdy_mask = { 733 .addr = 0x13, 734 .mask = BIT(3), 735 }, 736 .odr_table = { 737 [ST_LSM6DSX_ID_ACC] = { 738 .reg = { 739 .addr = 0x10, 740 .mask = GENMASK(7, 4), 741 }, 742 .odr_avl[0] = { 13, 0x01 }, 743 .odr_avl[1] = { 26, 0x02 }, 744 .odr_avl[2] = { 52, 0x03 }, 745 .odr_avl[3] = { 104, 0x04 }, 746 .odr_avl[4] = { 208, 0x05 }, 747 .odr_avl[5] = { 416, 0x06 }, 748 }, 749 [ST_LSM6DSX_ID_GYRO] = { 750 .reg = { 751 .addr = 0x11, 752 .mask = GENMASK(7, 4), 753 }, 754 .odr_avl[0] = { 13, 0x01 }, 755 .odr_avl[1] = { 26, 0x02 }, 756 .odr_avl[2] = { 52, 0x03 }, 757 .odr_avl[3] = { 104, 0x04 }, 758 .odr_avl[4] = { 208, 0x05 }, 759 .odr_avl[5] = { 416, 0x06 }, 760 }, 761 }, 762 .fs_table = { 763 [ST_LSM6DSX_ID_ACC] = { 764 .reg = { 765 .addr = 0x10, 766 .mask = GENMASK(3, 2), 767 }, 768 .fs_avl[0] = { IIO_G_TO_M_S_2(61), 0x0 }, 769 .fs_avl[1] = { IIO_G_TO_M_S_2(122), 0x2 }, 770 .fs_avl[2] = { IIO_G_TO_M_S_2(244), 0x3 }, 771 .fs_avl[3] = { IIO_G_TO_M_S_2(488), 0x1 }, 772 .fs_len = 4, 773 }, 774 [ST_LSM6DSX_ID_GYRO] = { 775 .reg = { 776 .addr = 0x11, 777 .mask = GENMASK(3, 2), 778 }, 779 .fs_avl[0] = { IIO_DEGREE_TO_RAD(8750), 0x0 }, 780 .fs_avl[1] = { IIO_DEGREE_TO_RAD(17500), 0x1 }, 781 .fs_avl[2] = { IIO_DEGREE_TO_RAD(35000), 0x2 }, 782 .fs_avl[3] = { IIO_DEGREE_TO_RAD(70000), 0x3 }, 783 .fs_len = 4, 784 }, 785 }, 786 .irq_config = { 787 .irq1 = { 788 .addr = 0x0d, 789 .mask = BIT(3), 790 }, 791 .irq2 = { 792 .addr = 0x0e, 793 .mask = BIT(3), 794 }, 795 .lir = { 796 .addr = 0x56, 797 .mask = BIT(0), 798 }, 799 .clear_on_read = { 800 .addr = 0x56, 801 .mask = BIT(6), 802 }, 803 .irq1_func = { 804 .addr = 0x5e, 805 .mask = BIT(5), 806 }, 807 .irq2_func = { 808 .addr = 0x5f, 809 .mask = BIT(5), 810 }, 811 .hla = { 812 .addr = 0x12, 813 .mask = BIT(5), 814 }, 815 .od = { 816 .addr = 0x12, 817 .mask = BIT(4), 818 }, 819 }, 820 .batch = { 821 [ST_LSM6DSX_ID_ACC] = { 822 .addr = 0x09, 823 .mask = GENMASK(3, 0), 824 }, 825 [ST_LSM6DSX_ID_GYRO] = { 826 .addr = 0x09, 827 .mask = GENMASK(7, 4), 828 }, 829 }, 830 .fifo_ops = { 831 .update_fifo = st_lsm6dsx_update_fifo, 832 .read_fifo = st_lsm6dsx_read_tagged_fifo, 833 .fifo_th = { 834 .addr = 0x07, 835 .mask = GENMASK(8, 0), 836 }, 837 .fifo_diff = { 838 .addr = 0x3a, 839 .mask = GENMASK(9, 0), 840 }, 841 .th_wl = 1, 842 }, 843 .ts_settings = { 844 .timer_en = { 845 .addr = 0x19, 846 .mask = BIT(5), 847 }, 848 .decimator = { 849 .addr = 0x0a, 850 .mask = GENMASK(7, 6), 851 }, 852 .freq_fine = 0x63, 853 }, 854 .shub_settings = { 855 .page_mux = { 856 .addr = 0x01, 857 .mask = BIT(6), 858 }, 859 .master_en = { 860 .addr = 0x14, 861 .mask = BIT(2), 862 }, 863 .pullup_en = { 864 .addr = 0x14, 865 .mask = BIT(3), 866 }, 867 .aux_sens = { 868 .addr = 0x14, 869 .mask = GENMASK(1, 0), 870 }, 871 .wr_once = { 872 .addr = 0x14, 873 .mask = BIT(6), 874 }, 875 .shub_out = 0x02, 876 .slv0_addr = 0x15, 877 .dw_slv0_addr = 0x21, 878 .batch_en = BIT(3), 879 }, 880 .event_settings = { 881 .enable_reg = { 882 .addr = 0x58, 883 .mask = BIT(7), 884 }, 885 .wakeup_reg = { 886 .addr = 0x5b, 887 .mask = GENMASK(5, 0), 888 }, 889 .wakeup_src_reg = 0x1b, 890 .wakeup_src_status_mask = BIT(3), 891 .wakeup_src_z_mask = BIT(0), 892 .wakeup_src_y_mask = BIT(1), 893 .wakeup_src_x_mask = BIT(2), 894 }, 895 }, 896 { 897 .wai = 0x6b, 898 .reset = { 899 .addr = 0x12, 900 .mask = BIT(0), 901 }, 902 .boot = { 903 .addr = 0x12, 904 .mask = BIT(7), 905 }, 906 .bdu = { 907 .addr = 0x12, 908 .mask = BIT(6), 909 }, 910 .max_fifo_size = 512, 911 .id = { 912 { 913 .hw_id = ST_ASM330LHH_ID, 914 .name = ST_ASM330LHH_DEV_NAME, 915 }, 916 }, 917 .channels = { 918 [ST_LSM6DSX_ID_ACC] = { 919 .chan = st_lsm6dsx_acc_channels, 920 .len = ARRAY_SIZE(st_lsm6dsx_acc_channels), 921 }, 922 [ST_LSM6DSX_ID_GYRO] = { 923 .chan = st_lsm6dsx_gyro_channels, 924 .len = ARRAY_SIZE(st_lsm6dsx_gyro_channels), 925 }, 926 }, 927 .drdy_mask = { 928 .addr = 0x13, 929 .mask = BIT(3), 930 }, 931 .odr_table = { 932 [ST_LSM6DSX_ID_ACC] = { 933 .reg = { 934 .addr = 0x10, 935 .mask = GENMASK(7, 4), 936 }, 937 .odr_avl[0] = { 13, 0x01 }, 938 .odr_avl[1] = { 26, 0x02 }, 939 .odr_avl[2] = { 52, 0x03 }, 940 .odr_avl[3] = { 104, 0x04 }, 941 .odr_avl[4] = { 208, 0x05 }, 942 .odr_avl[5] = { 416, 0x06 }, 943 }, 944 [ST_LSM6DSX_ID_GYRO] = { 945 .reg = { 946 .addr = 0x11, 947 .mask = GENMASK(7, 4), 948 }, 949 .odr_avl[0] = { 13, 0x01 }, 950 .odr_avl[1] = { 26, 0x02 }, 951 .odr_avl[2] = { 52, 0x03 }, 952 .odr_avl[3] = { 104, 0x04 }, 953 .odr_avl[4] = { 208, 0x05 }, 954 .odr_avl[5] = { 416, 0x06 }, 955 }, 956 }, 957 .fs_table = { 958 [ST_LSM6DSX_ID_ACC] = { 959 .reg = { 960 .addr = 0x10, 961 .mask = GENMASK(3, 2), 962 }, 963 .fs_avl[0] = { IIO_G_TO_M_S_2(61), 0x0 }, 964 .fs_avl[1] = { IIO_G_TO_M_S_2(122), 0x2 }, 965 .fs_avl[2] = { IIO_G_TO_M_S_2(244), 0x3 }, 966 .fs_avl[3] = { IIO_G_TO_M_S_2(488), 0x1 }, 967 .fs_len = 4, 968 }, 969 [ST_LSM6DSX_ID_GYRO] = { 970 .reg = { 971 .addr = 0x11, 972 .mask = GENMASK(3, 2), 973 }, 974 .fs_avl[0] = { IIO_DEGREE_TO_RAD(8750), 0x0 }, 975 .fs_avl[1] = { IIO_DEGREE_TO_RAD(17500), 0x1 }, 976 .fs_avl[2] = { IIO_DEGREE_TO_RAD(35000), 0x2 }, 977 .fs_avl[3] = { IIO_DEGREE_TO_RAD(70000), 0x3 }, 978 .fs_len = 4, 979 }, 980 }, 981 .irq_config = { 982 .irq1 = { 983 .addr = 0x0d, 984 .mask = BIT(3), 985 }, 986 .irq2 = { 987 .addr = 0x0e, 988 .mask = BIT(3), 989 }, 990 .lir = { 991 .addr = 0x56, 992 .mask = BIT(0), 993 }, 994 .clear_on_read = { 995 .addr = 0x56, 996 .mask = BIT(6), 997 }, 998 .irq1_func = { 999 .addr = 0x5e, 1000 .mask = BIT(5), 1001 }, 1002 .irq2_func = { 1003 .addr = 0x5f, 1004 .mask = BIT(5), 1005 }, 1006 .hla = { 1007 .addr = 0x12, 1008 .mask = BIT(5), 1009 }, 1010 .od = { 1011 .addr = 0x12, 1012 .mask = BIT(4), 1013 }, 1014 }, 1015 .batch = { 1016 [ST_LSM6DSX_ID_ACC] = { 1017 .addr = 0x09, 1018 .mask = GENMASK(3, 0), 1019 }, 1020 [ST_LSM6DSX_ID_GYRO] = { 1021 .addr = 0x09, 1022 .mask = GENMASK(7, 4), 1023 }, 1024 }, 1025 .fifo_ops = { 1026 .update_fifo = st_lsm6dsx_update_fifo, 1027 .read_fifo = st_lsm6dsx_read_tagged_fifo, 1028 .fifo_th = { 1029 .addr = 0x07, 1030 .mask = GENMASK(8, 0), 1031 }, 1032 .fifo_diff = { 1033 .addr = 0x3a, 1034 .mask = GENMASK(9, 0), 1035 }, 1036 .th_wl = 1, 1037 }, 1038 .ts_settings = { 1039 .timer_en = { 1040 .addr = 0x19, 1041 .mask = BIT(5), 1042 }, 1043 .decimator = { 1044 .addr = 0x0a, 1045 .mask = GENMASK(7, 6), 1046 }, 1047 .freq_fine = 0x63, 1048 }, 1049 .event_settings = { 1050 .enable_reg = { 1051 .addr = 0x58, 1052 .mask = BIT(7), 1053 }, 1054 .wakeup_reg = { 1055 .addr = 0x5B, 1056 .mask = GENMASK(5, 0), 1057 }, 1058 .wakeup_src_reg = 0x1b, 1059 .wakeup_src_status_mask = BIT(3), 1060 .wakeup_src_z_mask = BIT(0), 1061 .wakeup_src_y_mask = BIT(1), 1062 .wakeup_src_x_mask = BIT(2), 1063 }, 1064 }, 1065 { 1066 .wai = 0x6b, 1067 .reset = { 1068 .addr = 0x12, 1069 .mask = BIT(0), 1070 }, 1071 .boot = { 1072 .addr = 0x12, 1073 .mask = BIT(7), 1074 }, 1075 .bdu = { 1076 .addr = 0x12, 1077 .mask = BIT(6), 1078 }, 1079 .max_fifo_size = 512, 1080 .id = { 1081 { 1082 .hw_id = ST_LSM6DSR_ID, 1083 .name = ST_LSM6DSR_DEV_NAME, 1084 }, { 1085 .hw_id = ST_ISM330DHCX_ID, 1086 .name = ST_ISM330DHCX_DEV_NAME, 1087 }, 1088 }, 1089 .channels = { 1090 [ST_LSM6DSX_ID_ACC] = { 1091 .chan = st_lsm6dsx_acc_channels, 1092 .len = ARRAY_SIZE(st_lsm6dsx_acc_channels), 1093 }, 1094 [ST_LSM6DSX_ID_GYRO] = { 1095 .chan = st_lsm6dsx_gyro_channels, 1096 .len = ARRAY_SIZE(st_lsm6dsx_gyro_channels), 1097 }, 1098 }, 1099 .drdy_mask = { 1100 .addr = 0x13, 1101 .mask = BIT(3), 1102 }, 1103 .odr_table = { 1104 [ST_LSM6DSX_ID_ACC] = { 1105 .reg = { 1106 .addr = 0x10, 1107 .mask = GENMASK(7, 4), 1108 }, 1109 .odr_avl[0] = { 13, 0x01 }, 1110 .odr_avl[1] = { 26, 0x02 }, 1111 .odr_avl[2] = { 52, 0x03 }, 1112 .odr_avl[3] = { 104, 0x04 }, 1113 .odr_avl[4] = { 208, 0x05 }, 1114 .odr_avl[5] = { 416, 0x06 }, 1115 }, 1116 [ST_LSM6DSX_ID_GYRO] = { 1117 .reg = { 1118 .addr = 0x11, 1119 .mask = GENMASK(7, 4), 1120 }, 1121 .odr_avl[0] = { 13, 0x01 }, 1122 .odr_avl[1] = { 26, 0x02 }, 1123 .odr_avl[2] = { 52, 0x03 }, 1124 .odr_avl[3] = { 104, 0x04 }, 1125 .odr_avl[4] = { 208, 0x05 }, 1126 .odr_avl[5] = { 416, 0x06 }, 1127 }, 1128 }, 1129 .fs_table = { 1130 [ST_LSM6DSX_ID_ACC] = { 1131 .reg = { 1132 .addr = 0x10, 1133 .mask = GENMASK(3, 2), 1134 }, 1135 .fs_avl[0] = { IIO_G_TO_M_S_2(61), 0x0 }, 1136 .fs_avl[1] = { IIO_G_TO_M_S_2(122), 0x2 }, 1137 .fs_avl[2] = { IIO_G_TO_M_S_2(244), 0x3 }, 1138 .fs_avl[3] = { IIO_G_TO_M_S_2(488), 0x1 }, 1139 .fs_len = 4, 1140 }, 1141 [ST_LSM6DSX_ID_GYRO] = { 1142 .reg = { 1143 .addr = 0x11, 1144 .mask = GENMASK(3, 2), 1145 }, 1146 .fs_avl[0] = { IIO_DEGREE_TO_RAD(8750), 0x0 }, 1147 .fs_avl[1] = { IIO_DEGREE_TO_RAD(17500), 0x1 }, 1148 .fs_avl[2] = { IIO_DEGREE_TO_RAD(35000), 0x2 }, 1149 .fs_avl[3] = { IIO_DEGREE_TO_RAD(70000), 0x3 }, 1150 .fs_len = 4, 1151 }, 1152 }, 1153 .irq_config = { 1154 .irq1 = { 1155 .addr = 0x0d, 1156 .mask = BIT(3), 1157 }, 1158 .irq2 = { 1159 .addr = 0x0e, 1160 .mask = BIT(3), 1161 }, 1162 .lir = { 1163 .addr = 0x56, 1164 .mask = BIT(0), 1165 }, 1166 .clear_on_read = { 1167 .addr = 0x56, 1168 .mask = BIT(6), 1169 }, 1170 .irq1_func = { 1171 .addr = 0x5e, 1172 .mask = BIT(5), 1173 }, 1174 .irq2_func = { 1175 .addr = 0x5f, 1176 .mask = BIT(5), 1177 }, 1178 .hla = { 1179 .addr = 0x12, 1180 .mask = BIT(5), 1181 }, 1182 .od = { 1183 .addr = 0x12, 1184 .mask = BIT(4), 1185 }, 1186 }, 1187 .batch = { 1188 [ST_LSM6DSX_ID_ACC] = { 1189 .addr = 0x09, 1190 .mask = GENMASK(3, 0), 1191 }, 1192 [ST_LSM6DSX_ID_GYRO] = { 1193 .addr = 0x09, 1194 .mask = GENMASK(7, 4), 1195 }, 1196 }, 1197 .fifo_ops = { 1198 .update_fifo = st_lsm6dsx_update_fifo, 1199 .read_fifo = st_lsm6dsx_read_tagged_fifo, 1200 .fifo_th = { 1201 .addr = 0x07, 1202 .mask = GENMASK(8, 0), 1203 }, 1204 .fifo_diff = { 1205 .addr = 0x3a, 1206 .mask = GENMASK(9, 0), 1207 }, 1208 .th_wl = 1, 1209 }, 1210 .ts_settings = { 1211 .timer_en = { 1212 .addr = 0x19, 1213 .mask = BIT(5), 1214 }, 1215 .decimator = { 1216 .addr = 0x0a, 1217 .mask = GENMASK(7, 6), 1218 }, 1219 .freq_fine = 0x63, 1220 }, 1221 .shub_settings = { 1222 .page_mux = { 1223 .addr = 0x01, 1224 .mask = BIT(6), 1225 }, 1226 .master_en = { 1227 .addr = 0x14, 1228 .mask = BIT(2), 1229 }, 1230 .pullup_en = { 1231 .addr = 0x14, 1232 .mask = BIT(3), 1233 }, 1234 .aux_sens = { 1235 .addr = 0x14, 1236 .mask = GENMASK(1, 0), 1237 }, 1238 .wr_once = { 1239 .addr = 0x14, 1240 .mask = BIT(6), 1241 }, 1242 .shub_out = 0x02, 1243 .slv0_addr = 0x15, 1244 .dw_slv0_addr = 0x21, 1245 .batch_en = BIT(3), 1246 }, 1247 .event_settings = { 1248 .enable_reg = { 1249 .addr = 0x58, 1250 .mask = BIT(7), 1251 }, 1252 .wakeup_reg = { 1253 .addr = 0x5B, 1254 .mask = GENMASK(5, 0), 1255 }, 1256 .wakeup_src_reg = 0x1b, 1257 .wakeup_src_status_mask = BIT(3), 1258 .wakeup_src_z_mask = BIT(0), 1259 .wakeup_src_y_mask = BIT(1), 1260 .wakeup_src_x_mask = BIT(2), 1261 } 1262 }, 1263 }; 1264 1265 int st_lsm6dsx_set_page(struct st_lsm6dsx_hw *hw, bool enable) 1266 { 1267 const struct st_lsm6dsx_shub_settings *hub_settings; 1268 unsigned int data; 1269 int err; 1270 1271 hub_settings = &hw->settings->shub_settings; 1272 data = ST_LSM6DSX_SHIFT_VAL(enable, hub_settings->page_mux.mask); 1273 err = regmap_update_bits(hw->regmap, hub_settings->page_mux.addr, 1274 hub_settings->page_mux.mask, data); 1275 usleep_range(100, 150); 1276 1277 return err; 1278 } 1279 1280 static int st_lsm6dsx_check_whoami(struct st_lsm6dsx_hw *hw, int id, 1281 const char **name) 1282 { 1283 int err, i, j, data; 1284 1285 for (i = 0; i < ARRAY_SIZE(st_lsm6dsx_sensor_settings); i++) { 1286 for (j = 0; j < ST_LSM6DSX_MAX_ID; j++) { 1287 if (id == st_lsm6dsx_sensor_settings[i].id[j].hw_id) 1288 break; 1289 } 1290 if (j < ST_LSM6DSX_MAX_ID) 1291 break; 1292 } 1293 1294 if (i == ARRAY_SIZE(st_lsm6dsx_sensor_settings)) { 1295 dev_err(hw->dev, "unsupported hw id [%02x]\n", id); 1296 return -ENODEV; 1297 } 1298 1299 err = regmap_read(hw->regmap, ST_LSM6DSX_REG_WHOAMI_ADDR, &data); 1300 if (err < 0) { 1301 dev_err(hw->dev, "failed to read whoami register\n"); 1302 return err; 1303 } 1304 1305 if (data != st_lsm6dsx_sensor_settings[i].wai) { 1306 dev_err(hw->dev, "unsupported whoami [%02x]\n", data); 1307 return -ENODEV; 1308 } 1309 1310 *name = st_lsm6dsx_sensor_settings[i].id[j].name; 1311 hw->settings = &st_lsm6dsx_sensor_settings[i]; 1312 1313 return 0; 1314 } 1315 1316 static int st_lsm6dsx_set_full_scale(struct st_lsm6dsx_sensor *sensor, 1317 u32 gain) 1318 { 1319 const struct st_lsm6dsx_fs_table_entry *fs_table; 1320 unsigned int data; 1321 int i, err; 1322 1323 fs_table = &sensor->hw->settings->fs_table[sensor->id]; 1324 for (i = 0; i < fs_table->fs_len; i++) { 1325 if (fs_table->fs_avl[i].gain == gain) 1326 break; 1327 } 1328 1329 if (i == fs_table->fs_len) 1330 return -EINVAL; 1331 1332 data = ST_LSM6DSX_SHIFT_VAL(fs_table->fs_avl[i].val, 1333 fs_table->reg.mask); 1334 err = st_lsm6dsx_update_bits_locked(sensor->hw, fs_table->reg.addr, 1335 fs_table->reg.mask, data); 1336 if (err < 0) 1337 return err; 1338 1339 sensor->gain = gain; 1340 1341 return 0; 1342 } 1343 1344 int st_lsm6dsx_check_odr(struct st_lsm6dsx_sensor *sensor, u16 odr, u8 *val) 1345 { 1346 const struct st_lsm6dsx_odr_table_entry *odr_table; 1347 int i; 1348 1349 odr_table = &sensor->hw->settings->odr_table[sensor->id]; 1350 for (i = 0; i < ST_LSM6DSX_ODR_LIST_SIZE; i++) 1351 /* 1352 * ext devices can run at different odr respect to 1353 * accel sensor 1354 */ 1355 if (odr_table->odr_avl[i].hz >= odr) 1356 break; 1357 1358 if (i == ST_LSM6DSX_ODR_LIST_SIZE) 1359 return -EINVAL; 1360 1361 *val = odr_table->odr_avl[i].val; 1362 1363 return 0; 1364 } 1365 1366 static u16 st_lsm6dsx_check_odr_dependency(struct st_lsm6dsx_hw *hw, u16 odr, 1367 enum st_lsm6dsx_sensor_id id) 1368 { 1369 struct st_lsm6dsx_sensor *ref = iio_priv(hw->iio_devs[id]); 1370 1371 if (odr > 0) { 1372 if (hw->enable_mask & BIT(id)) 1373 return max_t(u16, ref->odr, odr); 1374 else 1375 return odr; 1376 } else { 1377 return (hw->enable_mask & BIT(id)) ? ref->odr : 0; 1378 } 1379 } 1380 1381 static int st_lsm6dsx_set_odr(struct st_lsm6dsx_sensor *sensor, u16 req_odr) 1382 { 1383 struct st_lsm6dsx_sensor *ref_sensor = sensor; 1384 struct st_lsm6dsx_hw *hw = sensor->hw; 1385 const struct st_lsm6dsx_reg *reg; 1386 unsigned int data; 1387 u8 val = 0; 1388 int err; 1389 1390 switch (sensor->id) { 1391 case ST_LSM6DSX_ID_EXT0: 1392 case ST_LSM6DSX_ID_EXT1: 1393 case ST_LSM6DSX_ID_EXT2: 1394 case ST_LSM6DSX_ID_ACC: { 1395 u16 odr; 1396 int i; 1397 1398 /* 1399 * i2c embedded controller relies on the accelerometer sensor as 1400 * bus read/write trigger so we need to enable accel device 1401 * at odr = max(accel_odr, ext_odr) in order to properly 1402 * communicate with i2c slave devices 1403 */ 1404 ref_sensor = iio_priv(hw->iio_devs[ST_LSM6DSX_ID_ACC]); 1405 for (i = ST_LSM6DSX_ID_ACC; i < ST_LSM6DSX_ID_MAX; i++) { 1406 if (!hw->iio_devs[i] || i == sensor->id) 1407 continue; 1408 1409 odr = st_lsm6dsx_check_odr_dependency(hw, req_odr, i); 1410 if (odr != req_odr) 1411 /* device already configured */ 1412 return 0; 1413 } 1414 break; 1415 } 1416 default: 1417 break; 1418 } 1419 1420 if (req_odr > 0) { 1421 err = st_lsm6dsx_check_odr(ref_sensor, req_odr, &val); 1422 if (err < 0) 1423 return err; 1424 } 1425 1426 reg = &hw->settings->odr_table[ref_sensor->id].reg; 1427 data = ST_LSM6DSX_SHIFT_VAL(val, reg->mask); 1428 return st_lsm6dsx_update_bits_locked(hw, reg->addr, reg->mask, data); 1429 } 1430 1431 int st_lsm6dsx_sensor_set_enable(struct st_lsm6dsx_sensor *sensor, 1432 bool enable) 1433 { 1434 struct st_lsm6dsx_hw *hw = sensor->hw; 1435 u16 odr = enable ? sensor->odr : 0; 1436 int err; 1437 1438 err = st_lsm6dsx_set_odr(sensor, odr); 1439 if (err < 0) 1440 return err; 1441 1442 if (enable) 1443 hw->enable_mask |= BIT(sensor->id); 1444 else 1445 hw->enable_mask &= ~BIT(sensor->id); 1446 1447 return 0; 1448 } 1449 1450 static int st_lsm6dsx_read_oneshot(struct st_lsm6dsx_sensor *sensor, 1451 u8 addr, int *val) 1452 { 1453 struct st_lsm6dsx_hw *hw = sensor->hw; 1454 int err, delay; 1455 __le16 data; 1456 1457 err = st_lsm6dsx_sensor_set_enable(sensor, true); 1458 if (err < 0) 1459 return err; 1460 1461 delay = 1000000 / sensor->odr; 1462 usleep_range(delay, 2 * delay); 1463 1464 err = st_lsm6dsx_read_locked(hw, addr, &data, sizeof(data)); 1465 if (err < 0) 1466 return err; 1467 1468 if (!hw->enable_event) 1469 st_lsm6dsx_sensor_set_enable(sensor, false); 1470 1471 *val = (s16)le16_to_cpu(data); 1472 1473 return IIO_VAL_INT; 1474 } 1475 1476 static int st_lsm6dsx_read_raw(struct iio_dev *iio_dev, 1477 struct iio_chan_spec const *ch, 1478 int *val, int *val2, long mask) 1479 { 1480 struct st_lsm6dsx_sensor *sensor = iio_priv(iio_dev); 1481 int ret; 1482 1483 switch (mask) { 1484 case IIO_CHAN_INFO_RAW: 1485 ret = iio_device_claim_direct_mode(iio_dev); 1486 if (ret) 1487 break; 1488 1489 ret = st_lsm6dsx_read_oneshot(sensor, ch->address, val); 1490 iio_device_release_direct_mode(iio_dev); 1491 break; 1492 case IIO_CHAN_INFO_SAMP_FREQ: 1493 *val = sensor->odr; 1494 ret = IIO_VAL_INT; 1495 break; 1496 case IIO_CHAN_INFO_SCALE: 1497 *val = 0; 1498 *val2 = sensor->gain; 1499 ret = IIO_VAL_INT_PLUS_MICRO; 1500 break; 1501 default: 1502 ret = -EINVAL; 1503 break; 1504 } 1505 1506 return ret; 1507 } 1508 1509 static int st_lsm6dsx_write_raw(struct iio_dev *iio_dev, 1510 struct iio_chan_spec const *chan, 1511 int val, int val2, long mask) 1512 { 1513 struct st_lsm6dsx_sensor *sensor = iio_priv(iio_dev); 1514 int err; 1515 1516 err = iio_device_claim_direct_mode(iio_dev); 1517 if (err) 1518 return err; 1519 1520 switch (mask) { 1521 case IIO_CHAN_INFO_SCALE: 1522 err = st_lsm6dsx_set_full_scale(sensor, val2); 1523 break; 1524 case IIO_CHAN_INFO_SAMP_FREQ: { 1525 u8 data; 1526 1527 err = st_lsm6dsx_check_odr(sensor, val, &data); 1528 if (!err) 1529 sensor->odr = val; 1530 break; 1531 } 1532 default: 1533 err = -EINVAL; 1534 break; 1535 } 1536 1537 iio_device_release_direct_mode(iio_dev); 1538 1539 return err; 1540 } 1541 1542 static int st_lsm6dsx_event_setup(struct st_lsm6dsx_hw *hw, int state) 1543 { 1544 const struct st_lsm6dsx_reg *reg; 1545 unsigned int data; 1546 int err; 1547 1548 if (!hw->settings->irq_config.irq1_func.addr) 1549 return -ENOTSUPP; 1550 1551 reg = &hw->settings->event_settings.enable_reg; 1552 if (reg->addr) { 1553 data = ST_LSM6DSX_SHIFT_VAL(state, reg->mask); 1554 err = st_lsm6dsx_update_bits_locked(hw, reg->addr, 1555 reg->mask, data); 1556 if (err < 0) 1557 return err; 1558 } 1559 1560 /* Enable wakeup interrupt */ 1561 data = ST_LSM6DSX_SHIFT_VAL(state, hw->irq_routing->mask); 1562 return st_lsm6dsx_update_bits_locked(hw, hw->irq_routing->addr, 1563 hw->irq_routing->mask, data); 1564 } 1565 1566 static int st_lsm6dsx_read_event(struct iio_dev *iio_dev, 1567 const struct iio_chan_spec *chan, 1568 enum iio_event_type type, 1569 enum iio_event_direction dir, 1570 enum iio_event_info info, 1571 int *val, int *val2) 1572 { 1573 struct st_lsm6dsx_sensor *sensor = iio_priv(iio_dev); 1574 struct st_lsm6dsx_hw *hw = sensor->hw; 1575 1576 if (type != IIO_EV_TYPE_THRESH) 1577 return -EINVAL; 1578 1579 *val2 = 0; 1580 *val = hw->event_threshold; 1581 1582 return IIO_VAL_INT; 1583 } 1584 1585 static int 1586 st_lsm6dsx_write_event(struct iio_dev *iio_dev, 1587 const struct iio_chan_spec *chan, 1588 enum iio_event_type type, 1589 enum iio_event_direction dir, 1590 enum iio_event_info info, 1591 int val, int val2) 1592 { 1593 struct st_lsm6dsx_sensor *sensor = iio_priv(iio_dev); 1594 struct st_lsm6dsx_hw *hw = sensor->hw; 1595 const struct st_lsm6dsx_reg *reg; 1596 unsigned int data; 1597 int err; 1598 1599 if (type != IIO_EV_TYPE_THRESH) 1600 return -EINVAL; 1601 1602 if (val < 0 || val > 31) 1603 return -EINVAL; 1604 1605 reg = &hw->settings->event_settings.wakeup_reg; 1606 data = ST_LSM6DSX_SHIFT_VAL(val, reg->mask); 1607 err = st_lsm6dsx_update_bits_locked(hw, reg->addr, 1608 reg->mask, data); 1609 if (err < 0) 1610 return -EINVAL; 1611 1612 hw->event_threshold = val; 1613 1614 return 0; 1615 } 1616 1617 static int 1618 st_lsm6dsx_read_event_config(struct iio_dev *iio_dev, 1619 const struct iio_chan_spec *chan, 1620 enum iio_event_type type, 1621 enum iio_event_direction dir) 1622 { 1623 struct st_lsm6dsx_sensor *sensor = iio_priv(iio_dev); 1624 struct st_lsm6dsx_hw *hw = sensor->hw; 1625 1626 if (type != IIO_EV_TYPE_THRESH) 1627 return -EINVAL; 1628 1629 return !!(hw->enable_event & BIT(chan->channel2)); 1630 } 1631 1632 static int 1633 st_lsm6dsx_write_event_config(struct iio_dev *iio_dev, 1634 const struct iio_chan_spec *chan, 1635 enum iio_event_type type, 1636 enum iio_event_direction dir, int state) 1637 { 1638 struct st_lsm6dsx_sensor *sensor = iio_priv(iio_dev); 1639 struct st_lsm6dsx_hw *hw = sensor->hw; 1640 u8 enable_event; 1641 int err = 0; 1642 1643 if (type != IIO_EV_TYPE_THRESH) 1644 return -EINVAL; 1645 1646 if (state) { 1647 enable_event = hw->enable_event | BIT(chan->channel2); 1648 1649 /* do not enable events if they are already enabled */ 1650 if (hw->enable_event) 1651 goto out; 1652 } else { 1653 enable_event = hw->enable_event & ~BIT(chan->channel2); 1654 1655 /* only turn off sensor if no events is enabled */ 1656 if (enable_event) 1657 goto out; 1658 } 1659 1660 /* stop here if no changes have been made */ 1661 if (hw->enable_event == enable_event) 1662 return 0; 1663 1664 err = st_lsm6dsx_event_setup(hw, state); 1665 if (err < 0) 1666 return err; 1667 1668 mutex_lock(&hw->conf_lock); 1669 err = st_lsm6dsx_sensor_set_enable(sensor, state); 1670 mutex_unlock(&hw->conf_lock); 1671 if (err < 0) 1672 return err; 1673 1674 out: 1675 hw->enable_event = enable_event; 1676 1677 return 0; 1678 } 1679 1680 int st_lsm6dsx_set_watermark(struct iio_dev *iio_dev, unsigned int val) 1681 { 1682 struct st_lsm6dsx_sensor *sensor = iio_priv(iio_dev); 1683 struct st_lsm6dsx_hw *hw = sensor->hw; 1684 int err; 1685 1686 if (val < 1 || val > hw->settings->max_fifo_size) 1687 return -EINVAL; 1688 1689 mutex_lock(&hw->conf_lock); 1690 1691 err = st_lsm6dsx_update_watermark(sensor, val); 1692 1693 mutex_unlock(&hw->conf_lock); 1694 1695 if (err < 0) 1696 return err; 1697 1698 sensor->watermark = val; 1699 1700 return 0; 1701 } 1702 1703 static ssize_t 1704 st_lsm6dsx_sysfs_sampling_frequency_avail(struct device *dev, 1705 struct device_attribute *attr, 1706 char *buf) 1707 { 1708 struct st_lsm6dsx_sensor *sensor = iio_priv(dev_get_drvdata(dev)); 1709 enum st_lsm6dsx_sensor_id id = sensor->id; 1710 struct st_lsm6dsx_hw *hw = sensor->hw; 1711 int i, len = 0; 1712 1713 for (i = 0; i < ST_LSM6DSX_ODR_LIST_SIZE; i++) 1714 len += scnprintf(buf + len, PAGE_SIZE - len, "%d ", 1715 hw->settings->odr_table[id].odr_avl[i].hz); 1716 buf[len - 1] = '\n'; 1717 1718 return len; 1719 } 1720 1721 static ssize_t st_lsm6dsx_sysfs_scale_avail(struct device *dev, 1722 struct device_attribute *attr, 1723 char *buf) 1724 { 1725 struct st_lsm6dsx_sensor *sensor = iio_priv(dev_get_drvdata(dev)); 1726 const struct st_lsm6dsx_fs_table_entry *fs_table; 1727 struct st_lsm6dsx_hw *hw = sensor->hw; 1728 int i, len = 0; 1729 1730 fs_table = &hw->settings->fs_table[sensor->id]; 1731 for (i = 0; i < fs_table->fs_len; i++) 1732 len += scnprintf(buf + len, PAGE_SIZE - len, "0.%06u ", 1733 fs_table->fs_avl[i].gain); 1734 buf[len - 1] = '\n'; 1735 1736 return len; 1737 } 1738 1739 static IIO_DEV_ATTR_SAMP_FREQ_AVAIL(st_lsm6dsx_sysfs_sampling_frequency_avail); 1740 static IIO_DEVICE_ATTR(in_accel_scale_available, 0444, 1741 st_lsm6dsx_sysfs_scale_avail, NULL, 0); 1742 static IIO_DEVICE_ATTR(in_anglvel_scale_available, 0444, 1743 st_lsm6dsx_sysfs_scale_avail, NULL, 0); 1744 1745 static struct attribute *st_lsm6dsx_acc_attributes[] = { 1746 &iio_dev_attr_sampling_frequency_available.dev_attr.attr, 1747 &iio_dev_attr_in_accel_scale_available.dev_attr.attr, 1748 NULL, 1749 }; 1750 1751 static const struct attribute_group st_lsm6dsx_acc_attribute_group = { 1752 .attrs = st_lsm6dsx_acc_attributes, 1753 }; 1754 1755 static const struct iio_info st_lsm6dsx_acc_info = { 1756 .attrs = &st_lsm6dsx_acc_attribute_group, 1757 .read_raw = st_lsm6dsx_read_raw, 1758 .write_raw = st_lsm6dsx_write_raw, 1759 .read_event_value = st_lsm6dsx_read_event, 1760 .write_event_value = st_lsm6dsx_write_event, 1761 .read_event_config = st_lsm6dsx_read_event_config, 1762 .write_event_config = st_lsm6dsx_write_event_config, 1763 .hwfifo_set_watermark = st_lsm6dsx_set_watermark, 1764 }; 1765 1766 static struct attribute *st_lsm6dsx_gyro_attributes[] = { 1767 &iio_dev_attr_sampling_frequency_available.dev_attr.attr, 1768 &iio_dev_attr_in_anglvel_scale_available.dev_attr.attr, 1769 NULL, 1770 }; 1771 1772 static const struct attribute_group st_lsm6dsx_gyro_attribute_group = { 1773 .attrs = st_lsm6dsx_gyro_attributes, 1774 }; 1775 1776 static const struct iio_info st_lsm6dsx_gyro_info = { 1777 .attrs = &st_lsm6dsx_gyro_attribute_group, 1778 .read_raw = st_lsm6dsx_read_raw, 1779 .write_raw = st_lsm6dsx_write_raw, 1780 .hwfifo_set_watermark = st_lsm6dsx_set_watermark, 1781 }; 1782 1783 static int st_lsm6dsx_of_get_drdy_pin(struct st_lsm6dsx_hw *hw, int *drdy_pin) 1784 { 1785 struct device_node *np = hw->dev->of_node; 1786 1787 if (!np) 1788 return -EINVAL; 1789 1790 return of_property_read_u32(np, "st,drdy-int-pin", drdy_pin); 1791 } 1792 1793 static int 1794 st_lsm6dsx_get_drdy_reg(struct st_lsm6dsx_hw *hw, 1795 const struct st_lsm6dsx_reg **drdy_reg) 1796 { 1797 int err = 0, drdy_pin; 1798 1799 if (st_lsm6dsx_of_get_drdy_pin(hw, &drdy_pin) < 0) { 1800 struct st_sensors_platform_data *pdata; 1801 struct device *dev = hw->dev; 1802 1803 pdata = (struct st_sensors_platform_data *)dev->platform_data; 1804 drdy_pin = pdata ? pdata->drdy_int_pin : 1; 1805 } 1806 1807 switch (drdy_pin) { 1808 case 1: 1809 hw->irq_routing = &hw->settings->irq_config.irq1_func; 1810 *drdy_reg = &hw->settings->irq_config.irq1; 1811 break; 1812 case 2: 1813 hw->irq_routing = &hw->settings->irq_config.irq2_func; 1814 *drdy_reg = &hw->settings->irq_config.irq2; 1815 break; 1816 default: 1817 dev_err(hw->dev, "unsupported data ready pin\n"); 1818 err = -EINVAL; 1819 break; 1820 } 1821 1822 return err; 1823 } 1824 1825 static int st_lsm6dsx_init_shub(struct st_lsm6dsx_hw *hw) 1826 { 1827 const struct st_lsm6dsx_shub_settings *hub_settings; 1828 struct device_node *np = hw->dev->of_node; 1829 struct st_sensors_platform_data *pdata; 1830 unsigned int data; 1831 int err = 0; 1832 1833 hub_settings = &hw->settings->shub_settings; 1834 1835 pdata = (struct st_sensors_platform_data *)hw->dev->platform_data; 1836 if ((np && of_property_read_bool(np, "st,pullups")) || 1837 (pdata && pdata->pullups)) { 1838 err = st_lsm6dsx_set_page(hw, true); 1839 if (err < 0) 1840 return err; 1841 1842 data = ST_LSM6DSX_SHIFT_VAL(1, hub_settings->pullup_en.mask); 1843 err = regmap_update_bits(hw->regmap, 1844 hub_settings->pullup_en.addr, 1845 hub_settings->pullup_en.mask, data); 1846 1847 st_lsm6dsx_set_page(hw, false); 1848 1849 if (err < 0) 1850 return err; 1851 } 1852 1853 if (hub_settings->aux_sens.addr) { 1854 /* configure aux sensors */ 1855 err = st_lsm6dsx_set_page(hw, true); 1856 if (err < 0) 1857 return err; 1858 1859 data = ST_LSM6DSX_SHIFT_VAL(3, hub_settings->aux_sens.mask); 1860 err = regmap_update_bits(hw->regmap, 1861 hub_settings->aux_sens.addr, 1862 hub_settings->aux_sens.mask, data); 1863 1864 st_lsm6dsx_set_page(hw, false); 1865 } 1866 1867 return err; 1868 } 1869 1870 static int st_lsm6dsx_init_hw_timer(struct st_lsm6dsx_hw *hw) 1871 { 1872 const struct st_lsm6dsx_hw_ts_settings *ts_settings; 1873 int err, val; 1874 1875 ts_settings = &hw->settings->ts_settings; 1876 /* enable hw timestamp generation if necessary */ 1877 if (ts_settings->timer_en.addr) { 1878 val = ST_LSM6DSX_SHIFT_VAL(1, ts_settings->timer_en.mask); 1879 err = regmap_update_bits(hw->regmap, 1880 ts_settings->timer_en.addr, 1881 ts_settings->timer_en.mask, val); 1882 if (err < 0) 1883 return err; 1884 } 1885 1886 /* enable high resolution for hw ts timer if necessary */ 1887 if (ts_settings->hr_timer.addr) { 1888 val = ST_LSM6DSX_SHIFT_VAL(1, ts_settings->hr_timer.mask); 1889 err = regmap_update_bits(hw->regmap, 1890 ts_settings->hr_timer.addr, 1891 ts_settings->hr_timer.mask, val); 1892 if (err < 0) 1893 return err; 1894 } 1895 1896 /* enable ts queueing in FIFO if necessary */ 1897 if (ts_settings->fifo_en.addr) { 1898 val = ST_LSM6DSX_SHIFT_VAL(1, ts_settings->fifo_en.mask); 1899 err = regmap_update_bits(hw->regmap, 1900 ts_settings->fifo_en.addr, 1901 ts_settings->fifo_en.mask, val); 1902 if (err < 0) 1903 return err; 1904 } 1905 1906 /* calibrate timestamp sensitivity */ 1907 hw->ts_gain = ST_LSM6DSX_TS_SENSITIVITY; 1908 if (ts_settings->freq_fine) { 1909 err = regmap_read(hw->regmap, ts_settings->freq_fine, &val); 1910 if (err < 0) 1911 return err; 1912 1913 /* 1914 * linearize the AN5192 formula: 1915 * 1 / (1 + x) ~= 1 - x (Taylor’s Series) 1916 * ttrim[s] = 1 / (40000 * (1 + 0.0015 * val)) 1917 * ttrim[ns] ~= 25000 - 37.5 * val 1918 * ttrim[ns] ~= 25000 - (37500 * val) / 1000 1919 */ 1920 hw->ts_gain -= ((s8)val * 37500) / 1000; 1921 } 1922 1923 return 0; 1924 } 1925 1926 static int st_lsm6dsx_init_device(struct st_lsm6dsx_hw *hw) 1927 { 1928 const struct st_lsm6dsx_reg *reg; 1929 int err; 1930 1931 /* device sw reset */ 1932 reg = &hw->settings->reset; 1933 err = regmap_update_bits(hw->regmap, reg->addr, reg->mask, 1934 ST_LSM6DSX_SHIFT_VAL(1, reg->mask)); 1935 if (err < 0) 1936 return err; 1937 1938 msleep(50); 1939 1940 /* reload trimming parameter */ 1941 reg = &hw->settings->boot; 1942 err = regmap_update_bits(hw->regmap, reg->addr, reg->mask, 1943 ST_LSM6DSX_SHIFT_VAL(1, reg->mask)); 1944 if (err < 0) 1945 return err; 1946 1947 msleep(50); 1948 1949 /* enable Block Data Update */ 1950 reg = &hw->settings->bdu; 1951 err = regmap_update_bits(hw->regmap, reg->addr, reg->mask, 1952 ST_LSM6DSX_SHIFT_VAL(1, reg->mask)); 1953 if (err < 0) 1954 return err; 1955 1956 /* enable FIFO watermak interrupt */ 1957 err = st_lsm6dsx_get_drdy_reg(hw, ®); 1958 if (err < 0) 1959 return err; 1960 1961 err = regmap_update_bits(hw->regmap, reg->addr, reg->mask, 1962 ST_LSM6DSX_SHIFT_VAL(1, reg->mask)); 1963 if (err < 0) 1964 return err; 1965 1966 /* enable Latched interrupts for device events */ 1967 if (hw->settings->irq_config.lir.addr) { 1968 reg = &hw->settings->irq_config.lir; 1969 err = regmap_update_bits(hw->regmap, reg->addr, reg->mask, 1970 ST_LSM6DSX_SHIFT_VAL(1, reg->mask)); 1971 if (err < 0) 1972 return err; 1973 1974 /* enable clear on read for latched interrupts */ 1975 if (hw->settings->irq_config.clear_on_read.addr) { 1976 reg = &hw->settings->irq_config.clear_on_read; 1977 err = regmap_update_bits(hw->regmap, 1978 reg->addr, reg->mask, 1979 ST_LSM6DSX_SHIFT_VAL(1, reg->mask)); 1980 if (err < 0) 1981 return err; 1982 } 1983 } 1984 1985 /* enable drdy-mas if available */ 1986 if (hw->settings->drdy_mask.addr) { 1987 reg = &hw->settings->drdy_mask; 1988 err = regmap_update_bits(hw->regmap, reg->addr, reg->mask, 1989 ST_LSM6DSX_SHIFT_VAL(1, reg->mask)); 1990 if (err < 0) 1991 return err; 1992 } 1993 1994 err = st_lsm6dsx_init_shub(hw); 1995 if (err < 0) 1996 return err; 1997 1998 return st_lsm6dsx_init_hw_timer(hw); 1999 } 2000 2001 static struct iio_dev *st_lsm6dsx_alloc_iiodev(struct st_lsm6dsx_hw *hw, 2002 enum st_lsm6dsx_sensor_id id, 2003 const char *name) 2004 { 2005 struct st_lsm6dsx_sensor *sensor; 2006 struct iio_dev *iio_dev; 2007 2008 iio_dev = devm_iio_device_alloc(hw->dev, sizeof(*sensor)); 2009 if (!iio_dev) 2010 return NULL; 2011 2012 iio_dev->modes = INDIO_DIRECT_MODE; 2013 iio_dev->dev.parent = hw->dev; 2014 iio_dev->available_scan_masks = st_lsm6dsx_available_scan_masks; 2015 iio_dev->channels = hw->settings->channels[id].chan; 2016 iio_dev->num_channels = hw->settings->channels[id].len; 2017 2018 sensor = iio_priv(iio_dev); 2019 sensor->id = id; 2020 sensor->hw = hw; 2021 sensor->odr = hw->settings->odr_table[id].odr_avl[0].hz; 2022 sensor->gain = hw->settings->fs_table[id].fs_avl[0].gain; 2023 sensor->watermark = 1; 2024 2025 switch (id) { 2026 case ST_LSM6DSX_ID_ACC: 2027 iio_dev->info = &st_lsm6dsx_acc_info; 2028 scnprintf(sensor->name, sizeof(sensor->name), "%s_accel", 2029 name); 2030 break; 2031 case ST_LSM6DSX_ID_GYRO: 2032 iio_dev->info = &st_lsm6dsx_gyro_info; 2033 scnprintf(sensor->name, sizeof(sensor->name), "%s_gyro", 2034 name); 2035 break; 2036 default: 2037 return NULL; 2038 } 2039 iio_dev->name = sensor->name; 2040 2041 return iio_dev; 2042 } 2043 2044 static bool 2045 st_lsm6dsx_report_motion_event(struct st_lsm6dsx_hw *hw) 2046 { 2047 const struct st_lsm6dsx_event_settings *event_settings; 2048 int err, data; 2049 s64 timestamp; 2050 2051 if (!hw->enable_event) 2052 return false; 2053 2054 event_settings = &hw->settings->event_settings; 2055 err = st_lsm6dsx_read_locked(hw, event_settings->wakeup_src_reg, 2056 &data, sizeof(data)); 2057 if (err < 0) 2058 return false; 2059 2060 timestamp = iio_get_time_ns(hw->iio_devs[ST_LSM6DSX_ID_ACC]); 2061 if ((data & hw->settings->event_settings.wakeup_src_z_mask) && 2062 (hw->enable_event & BIT(IIO_MOD_Z))) 2063 iio_push_event(hw->iio_devs[ST_LSM6DSX_ID_ACC], 2064 IIO_MOD_EVENT_CODE(IIO_ACCEL, 2065 0, 2066 IIO_MOD_Z, 2067 IIO_EV_TYPE_THRESH, 2068 IIO_EV_DIR_EITHER), 2069 timestamp); 2070 2071 if ((data & hw->settings->event_settings.wakeup_src_y_mask) && 2072 (hw->enable_event & BIT(IIO_MOD_Y))) 2073 iio_push_event(hw->iio_devs[ST_LSM6DSX_ID_ACC], 2074 IIO_MOD_EVENT_CODE(IIO_ACCEL, 2075 0, 2076 IIO_MOD_Y, 2077 IIO_EV_TYPE_THRESH, 2078 IIO_EV_DIR_EITHER), 2079 timestamp); 2080 2081 if ((data & hw->settings->event_settings.wakeup_src_x_mask) && 2082 (hw->enable_event & BIT(IIO_MOD_X))) 2083 iio_push_event(hw->iio_devs[ST_LSM6DSX_ID_ACC], 2084 IIO_MOD_EVENT_CODE(IIO_ACCEL, 2085 0, 2086 IIO_MOD_X, 2087 IIO_EV_TYPE_THRESH, 2088 IIO_EV_DIR_EITHER), 2089 timestamp); 2090 2091 return data & event_settings->wakeup_src_status_mask; 2092 } 2093 2094 static irqreturn_t st_lsm6dsx_handler_thread(int irq, void *private) 2095 { 2096 struct st_lsm6dsx_hw *hw = private; 2097 bool event; 2098 int count; 2099 2100 event = st_lsm6dsx_report_motion_event(hw); 2101 2102 if (!hw->settings->fifo_ops.read_fifo) 2103 return event ? IRQ_HANDLED : IRQ_NONE; 2104 2105 mutex_lock(&hw->fifo_lock); 2106 count = hw->settings->fifo_ops.read_fifo(hw); 2107 mutex_unlock(&hw->fifo_lock); 2108 2109 return count || event ? IRQ_HANDLED : IRQ_NONE; 2110 } 2111 2112 static int st_lsm6dsx_irq_setup(struct st_lsm6dsx_hw *hw) 2113 { 2114 struct device_node *np = hw->dev->of_node; 2115 struct st_sensors_platform_data *pdata; 2116 const struct st_lsm6dsx_reg *reg; 2117 unsigned long irq_type; 2118 bool irq_active_low; 2119 int err; 2120 2121 irq_type = irqd_get_trigger_type(irq_get_irq_data(hw->irq)); 2122 2123 switch (irq_type) { 2124 case IRQF_TRIGGER_HIGH: 2125 case IRQF_TRIGGER_RISING: 2126 irq_active_low = false; 2127 break; 2128 case IRQF_TRIGGER_LOW: 2129 case IRQF_TRIGGER_FALLING: 2130 irq_active_low = true; 2131 break; 2132 default: 2133 dev_info(hw->dev, "mode %lx unsupported\n", irq_type); 2134 return -EINVAL; 2135 } 2136 2137 reg = &hw->settings->irq_config.hla; 2138 err = regmap_update_bits(hw->regmap, reg->addr, reg->mask, 2139 ST_LSM6DSX_SHIFT_VAL(irq_active_low, 2140 reg->mask)); 2141 if (err < 0) 2142 return err; 2143 2144 pdata = (struct st_sensors_platform_data *)hw->dev->platform_data; 2145 if ((np && of_property_read_bool(np, "drive-open-drain")) || 2146 (pdata && pdata->open_drain)) { 2147 reg = &hw->settings->irq_config.od; 2148 err = regmap_update_bits(hw->regmap, reg->addr, reg->mask, 2149 ST_LSM6DSX_SHIFT_VAL(1, reg->mask)); 2150 if (err < 0) 2151 return err; 2152 2153 irq_type |= IRQF_SHARED; 2154 } 2155 2156 err = devm_request_threaded_irq(hw->dev, hw->irq, 2157 NULL, 2158 st_lsm6dsx_handler_thread, 2159 irq_type | IRQF_ONESHOT, 2160 "lsm6dsx", hw); 2161 if (err) { 2162 dev_err(hw->dev, "failed to request trigger irq %d\n", 2163 hw->irq); 2164 return err; 2165 } 2166 2167 return 0; 2168 } 2169 2170 int st_lsm6dsx_probe(struct device *dev, int irq, int hw_id, 2171 struct regmap *regmap) 2172 { 2173 struct st_sensors_platform_data *pdata = dev->platform_data; 2174 const struct st_lsm6dsx_shub_settings *hub_settings; 2175 struct device_node *np = dev->of_node; 2176 struct st_lsm6dsx_hw *hw; 2177 const char *name = NULL; 2178 int i, err; 2179 2180 hw = devm_kzalloc(dev, sizeof(*hw), GFP_KERNEL); 2181 if (!hw) 2182 return -ENOMEM; 2183 2184 dev_set_drvdata(dev, (void *)hw); 2185 2186 mutex_init(&hw->fifo_lock); 2187 mutex_init(&hw->conf_lock); 2188 mutex_init(&hw->page_lock); 2189 2190 hw->buff = devm_kzalloc(dev, ST_LSM6DSX_BUFF_SIZE, GFP_KERNEL); 2191 if (!hw->buff) 2192 return -ENOMEM; 2193 2194 hw->dev = dev; 2195 hw->irq = irq; 2196 hw->regmap = regmap; 2197 2198 err = st_lsm6dsx_check_whoami(hw, hw_id, &name); 2199 if (err < 0) 2200 return err; 2201 2202 for (i = 0; i < ST_LSM6DSX_ID_EXT0; i++) { 2203 hw->iio_devs[i] = st_lsm6dsx_alloc_iiodev(hw, i, name); 2204 if (!hw->iio_devs[i]) 2205 return -ENOMEM; 2206 } 2207 2208 err = st_lsm6dsx_init_device(hw); 2209 if (err < 0) 2210 return err; 2211 2212 hub_settings = &hw->settings->shub_settings; 2213 if (hub_settings->master_en.addr) { 2214 err = st_lsm6dsx_shub_probe(hw, name); 2215 if (err < 0) 2216 return err; 2217 } 2218 2219 if (hw->irq > 0) { 2220 err = st_lsm6dsx_irq_setup(hw); 2221 if (err < 0) 2222 return err; 2223 2224 err = st_lsm6dsx_fifo_setup(hw); 2225 if (err < 0) 2226 return err; 2227 } 2228 2229 for (i = 0; i < ST_LSM6DSX_ID_MAX; i++) { 2230 if (!hw->iio_devs[i]) 2231 continue; 2232 2233 err = devm_iio_device_register(hw->dev, hw->iio_devs[i]); 2234 if (err) 2235 return err; 2236 } 2237 2238 if ((np && of_property_read_bool(np, "wakeup-source")) || 2239 (pdata && pdata->wakeup_source)) 2240 device_init_wakeup(dev, true); 2241 2242 return 0; 2243 } 2244 EXPORT_SYMBOL(st_lsm6dsx_probe); 2245 2246 static int __maybe_unused st_lsm6dsx_suspend(struct device *dev) 2247 { 2248 struct st_lsm6dsx_hw *hw = dev_get_drvdata(dev); 2249 struct st_lsm6dsx_sensor *sensor; 2250 int i, err = 0; 2251 2252 for (i = 0; i < ST_LSM6DSX_ID_MAX; i++) { 2253 if (!hw->iio_devs[i]) 2254 continue; 2255 2256 sensor = iio_priv(hw->iio_devs[i]); 2257 if (!(hw->enable_mask & BIT(sensor->id))) 2258 continue; 2259 2260 if (device_may_wakeup(dev) && 2261 sensor->id == ST_LSM6DSX_ID_ACC && hw->enable_event) { 2262 /* Enable wake from IRQ */ 2263 enable_irq_wake(hw->irq); 2264 continue; 2265 } 2266 2267 if (sensor->id == ST_LSM6DSX_ID_EXT0 || 2268 sensor->id == ST_LSM6DSX_ID_EXT1 || 2269 sensor->id == ST_LSM6DSX_ID_EXT2) 2270 err = st_lsm6dsx_shub_set_enable(sensor, false); 2271 else 2272 err = st_lsm6dsx_sensor_set_enable(sensor, false); 2273 if (err < 0) 2274 return err; 2275 2276 hw->suspend_mask |= BIT(sensor->id); 2277 } 2278 2279 if (hw->fifo_mode != ST_LSM6DSX_FIFO_BYPASS) 2280 err = st_lsm6dsx_flush_fifo(hw); 2281 2282 return err; 2283 } 2284 2285 static int __maybe_unused st_lsm6dsx_resume(struct device *dev) 2286 { 2287 struct st_lsm6dsx_hw *hw = dev_get_drvdata(dev); 2288 struct st_lsm6dsx_sensor *sensor; 2289 int i, err = 0; 2290 2291 for (i = 0; i < ST_LSM6DSX_ID_MAX; i++) { 2292 if (!hw->iio_devs[i]) 2293 continue; 2294 2295 sensor = iio_priv(hw->iio_devs[i]); 2296 if (device_may_wakeup(dev) && 2297 sensor->id == ST_LSM6DSX_ID_ACC && hw->enable_event) 2298 disable_irq_wake(hw->irq); 2299 2300 if (!(hw->suspend_mask & BIT(sensor->id))) 2301 continue; 2302 2303 if (sensor->id == ST_LSM6DSX_ID_EXT0 || 2304 sensor->id == ST_LSM6DSX_ID_EXT1 || 2305 sensor->id == ST_LSM6DSX_ID_EXT2) 2306 err = st_lsm6dsx_shub_set_enable(sensor, true); 2307 else 2308 err = st_lsm6dsx_sensor_set_enable(sensor, true); 2309 if (err < 0) 2310 return err; 2311 2312 hw->suspend_mask &= ~BIT(sensor->id); 2313 } 2314 2315 if (hw->enable_mask) 2316 err = st_lsm6dsx_set_fifo_mode(hw, ST_LSM6DSX_FIFO_CONT); 2317 2318 return err; 2319 } 2320 2321 const struct dev_pm_ops st_lsm6dsx_pm_ops = { 2322 SET_SYSTEM_SLEEP_PM_OPS(st_lsm6dsx_suspend, st_lsm6dsx_resume) 2323 }; 2324 EXPORT_SYMBOL(st_lsm6dsx_pm_ops); 2325 2326 MODULE_AUTHOR("Lorenzo Bianconi <lorenzo.bianconi@st.com>"); 2327 MODULE_AUTHOR("Denis Ciocca <denis.ciocca@st.com>"); 2328 MODULE_DESCRIPTION("STMicroelectronics st_lsm6dsx driver"); 2329 MODULE_LICENSE("GPL v2"); 2330