1 // SPDX-License-Identifier: GPL-2.0-only 2 /* 3 * STMicroelectronics st_lsm6dsx sensor driver 4 * 5 * The ST LSM6DSx IMU MEMS series consists of 3D digital accelerometer 6 * and 3D digital gyroscope system-in-package with a digital I2C/SPI serial 7 * interface standard output. 8 * LSM6DSx IMU MEMS series has a dynamic user-selectable full-scale 9 * acceleration range of +-2/+-4/+-8/+-16 g and an angular rate range of 10 * +-125/+-245/+-500/+-1000/+-2000 dps 11 * LSM6DSx series has an integrated First-In-First-Out (FIFO) buffer 12 * allowing dynamic batching of sensor data. 13 * LSM9DSx series is similar but includes an additional magnetometer, handled 14 * by a different driver. 15 * 16 * Supported sensors: 17 * - LSM6DS3: 18 * - Accelerometer/Gyroscope supported ODR [Hz]: 13, 26, 52, 104, 208, 416 19 * - Accelerometer supported full-scale [g]: +-2/+-4/+-8/+-16 20 * - Gyroscope supported full-scale [dps]: +-125/+-245/+-500/+-1000/+-2000 21 * - FIFO size: 8KB 22 * 23 * - LSM6DS3H/LSM6DSL/LSM6DSM/ISM330DLC/LSM6DS3TR-C: 24 * - Accelerometer/Gyroscope supported ODR [Hz]: 13, 26, 52, 104, 208, 416 25 * - Accelerometer supported full-scale [g]: +-2/+-4/+-8/+-16 26 * - Gyroscope supported full-scale [dps]: +-125/+-245/+-500/+-1000/+-2000 27 * - FIFO size: 4KB 28 * 29 * - LSM6DSO/LSM6DSOX/ASM330LHH/LSM6DSR/ISM330DHCX: 30 * - Accelerometer/Gyroscope supported ODR [Hz]: 13, 26, 52, 104, 208, 416 31 * - Accelerometer supported full-scale [g]: +-2/+-4/+-8/+-16 32 * - Gyroscope supported full-scale [dps]: +-125/+-245/+-500/+-1000/+-2000 33 * - FIFO size: 3KB 34 * 35 * - LSM9DS1: 36 * - Accelerometer supported ODR [Hz]: 10, 50, 119, 238, 476, 952 37 * - Accelerometer supported full-scale [g]: +-2/+-4/+-8/+-16 38 * - Gyroscope supported ODR [Hz]: 15, 60, 119, 238, 476, 952 39 * - Gyroscope supported full-scale [dps]: +-245/+-500/+-2000 40 * - FIFO size: 32 41 * 42 * Copyright 2016 STMicroelectronics Inc. 43 * 44 * Lorenzo Bianconi <lorenzo.bianconi@st.com> 45 * Denis Ciocca <denis.ciocca@st.com> 46 */ 47 48 #include <linux/kernel.h> 49 #include <linux/module.h> 50 #include <linux/delay.h> 51 #include <linux/iio/iio.h> 52 #include <linux/iio/sysfs.h> 53 #include <linux/interrupt.h> 54 #include <linux/irq.h> 55 #include <linux/pm.h> 56 #include <linux/regmap.h> 57 #include <linux/bitfield.h> 58 59 #include <linux/platform_data/st_sensors_pdata.h> 60 61 #include "st_lsm6dsx.h" 62 63 #define ST_LSM6DSX_REG_FIFO_FTH_IRQ_MASK BIT(3) 64 #define ST_LSM6DSX_REG_WHOAMI_ADDR 0x0f 65 #define ST_LSM6DSX_REG_RESET_MASK BIT(0) 66 #define ST_LSM6DSX_REG_BOOT_MASK BIT(7) 67 #define ST_LSM6DSX_REG_BDU_ADDR 0x12 68 #define ST_LSM6DSX_REG_BDU_MASK BIT(6) 69 70 #define ST_LSM6DSX_REG_HLACTIVE_ADDR 0x12 71 #define ST_LSM6DSX_REG_HLACTIVE_MASK BIT(5) 72 #define ST_LSM6DSX_REG_PP_OD_ADDR 0x12 73 #define ST_LSM6DSX_REG_PP_OD_MASK BIT(4) 74 75 static const struct iio_chan_spec st_lsm6dsx_acc_channels[] = { 76 ST_LSM6DSX_CHANNEL_ACC(IIO_ACCEL, 0x28, IIO_MOD_X, 0), 77 ST_LSM6DSX_CHANNEL_ACC(IIO_ACCEL, 0x2a, IIO_MOD_Y, 1), 78 ST_LSM6DSX_CHANNEL_ACC(IIO_ACCEL, 0x2c, IIO_MOD_Z, 2), 79 IIO_CHAN_SOFT_TIMESTAMP(3), 80 }; 81 82 static const struct iio_chan_spec st_lsm6dsx_gyro_channels[] = { 83 ST_LSM6DSX_CHANNEL(IIO_ANGL_VEL, 0x22, IIO_MOD_X, 0), 84 ST_LSM6DSX_CHANNEL(IIO_ANGL_VEL, 0x24, IIO_MOD_Y, 1), 85 ST_LSM6DSX_CHANNEL(IIO_ANGL_VEL, 0x26, IIO_MOD_Z, 2), 86 IIO_CHAN_SOFT_TIMESTAMP(3), 87 }; 88 89 static const struct iio_chan_spec st_lsm6ds0_gyro_channels[] = { 90 ST_LSM6DSX_CHANNEL(IIO_ANGL_VEL, 0x18, IIO_MOD_X, 0), 91 ST_LSM6DSX_CHANNEL(IIO_ANGL_VEL, 0x1a, IIO_MOD_Y, 1), 92 ST_LSM6DSX_CHANNEL(IIO_ANGL_VEL, 0x1c, IIO_MOD_Z, 2), 93 IIO_CHAN_SOFT_TIMESTAMP(3), 94 }; 95 96 static const struct st_lsm6dsx_settings st_lsm6dsx_sensor_settings[] = { 97 { 98 .wai = 0x68, 99 .int1_addr = 0x0c, 100 .int2_addr = 0x0d, 101 .reset_addr = 0x22, 102 .max_fifo_size = 32, 103 .id = { 104 { 105 .hw_id = ST_LSM9DS1_ID, 106 .name = ST_LSM9DS1_DEV_NAME, 107 }, 108 }, 109 .channels = { 110 [ST_LSM6DSX_ID_ACC] = { 111 .chan = st_lsm6dsx_acc_channels, 112 .len = ARRAY_SIZE(st_lsm6dsx_acc_channels), 113 }, 114 [ST_LSM6DSX_ID_GYRO] = { 115 .chan = st_lsm6ds0_gyro_channels, 116 .len = ARRAY_SIZE(st_lsm6ds0_gyro_channels), 117 }, 118 }, 119 .odr_table = { 120 [ST_LSM6DSX_ID_ACC] = { 121 .reg = { 122 .addr = 0x20, 123 .mask = GENMASK(7, 5), 124 }, 125 .odr_avl[0] = { 10, 0x01 }, 126 .odr_avl[1] = { 50, 0x02 }, 127 .odr_avl[2] = { 119, 0x03 }, 128 .odr_avl[3] = { 238, 0x04 }, 129 .odr_avl[4] = { 476, 0x05 }, 130 .odr_avl[5] = { 952, 0x06 }, 131 }, 132 [ST_LSM6DSX_ID_GYRO] = { 133 .reg = { 134 .addr = 0x10, 135 .mask = GENMASK(7, 5), 136 }, 137 .odr_avl[0] = { 15, 0x01 }, 138 .odr_avl[1] = { 60, 0x02 }, 139 .odr_avl[2] = { 119, 0x03 }, 140 .odr_avl[3] = { 238, 0x04 }, 141 .odr_avl[4] = { 476, 0x05 }, 142 .odr_avl[5] = { 952, 0x06 }, 143 }, 144 }, 145 .fs_table = { 146 [ST_LSM6DSX_ID_ACC] = { 147 .reg = { 148 .addr = 0x20, 149 .mask = GENMASK(4, 3), 150 }, 151 .fs_avl[0] = { IIO_G_TO_M_S_2(61), 0x0 }, 152 .fs_avl[1] = { IIO_G_TO_M_S_2(122), 0x2 }, 153 .fs_avl[2] = { IIO_G_TO_M_S_2(244), 0x3 }, 154 .fs_avl[3] = { IIO_G_TO_M_S_2(732), 0x1 }, 155 }, 156 [ST_LSM6DSX_ID_GYRO] = { 157 .reg = { 158 .addr = 0x10, 159 .mask = GENMASK(4, 3), 160 }, 161 .fs_avl[0] = { IIO_DEGREE_TO_RAD(245), 0x0 }, 162 .fs_avl[1] = { IIO_DEGREE_TO_RAD(500), 0x1 }, 163 .fs_avl[2] = { IIO_DEGREE_TO_RAD(2000), 0x3 }, 164 }, 165 }, 166 }, 167 { 168 .wai = 0x69, 169 .int1_addr = 0x0d, 170 .int2_addr = 0x0e, 171 .int1_func_addr = 0x5e, 172 .int2_func_addr = 0x5f, 173 .int_func_mask = BIT(5), 174 .reset_addr = 0x12, 175 .max_fifo_size = 1365, 176 .id = { 177 { 178 .hw_id = ST_LSM6DS3_ID, 179 .name = ST_LSM6DS3_DEV_NAME, 180 }, 181 }, 182 .channels = { 183 [ST_LSM6DSX_ID_ACC] = { 184 .chan = st_lsm6dsx_acc_channels, 185 .len = ARRAY_SIZE(st_lsm6dsx_acc_channels), 186 }, 187 [ST_LSM6DSX_ID_GYRO] = { 188 .chan = st_lsm6dsx_gyro_channels, 189 .len = ARRAY_SIZE(st_lsm6dsx_gyro_channels), 190 }, 191 }, 192 .odr_table = { 193 [ST_LSM6DSX_ID_ACC] = { 194 .reg = { 195 .addr = 0x10, 196 .mask = GENMASK(7, 4), 197 }, 198 .odr_avl[0] = { 13, 0x01 }, 199 .odr_avl[1] = { 26, 0x02 }, 200 .odr_avl[2] = { 52, 0x03 }, 201 .odr_avl[3] = { 104, 0x04 }, 202 .odr_avl[4] = { 208, 0x05 }, 203 .odr_avl[5] = { 416, 0x06 }, 204 }, 205 [ST_LSM6DSX_ID_GYRO] = { 206 .reg = { 207 .addr = 0x11, 208 .mask = GENMASK(7, 4), 209 }, 210 .odr_avl[0] = { 13, 0x01 }, 211 .odr_avl[1] = { 26, 0x02 }, 212 .odr_avl[2] = { 52, 0x03 }, 213 .odr_avl[3] = { 104, 0x04 }, 214 .odr_avl[4] = { 208, 0x05 }, 215 .odr_avl[5] = { 416, 0x06 }, 216 }, 217 }, 218 .fs_table = { 219 [ST_LSM6DSX_ID_ACC] = { 220 .reg = { 221 .addr = 0x10, 222 .mask = GENMASK(3, 2), 223 }, 224 .fs_avl[0] = { IIO_G_TO_M_S_2(61), 0x0 }, 225 .fs_avl[1] = { IIO_G_TO_M_S_2(122), 0x2 }, 226 .fs_avl[2] = { IIO_G_TO_M_S_2(244), 0x3 }, 227 .fs_avl[3] = { IIO_G_TO_M_S_2(488), 0x1 }, 228 }, 229 [ST_LSM6DSX_ID_GYRO] = { 230 .reg = { 231 .addr = 0x11, 232 .mask = GENMASK(3, 2), 233 }, 234 .fs_avl[0] = { IIO_DEGREE_TO_RAD(8750), 0x0 }, 235 .fs_avl[1] = { IIO_DEGREE_TO_RAD(17500), 0x1 }, 236 .fs_avl[2] = { IIO_DEGREE_TO_RAD(35000), 0x2 }, 237 .fs_avl[3] = { IIO_DEGREE_TO_RAD(70000), 0x3 }, 238 }, 239 }, 240 .decimator = { 241 [ST_LSM6DSX_ID_ACC] = { 242 .addr = 0x08, 243 .mask = GENMASK(2, 0), 244 }, 245 [ST_LSM6DSX_ID_GYRO] = { 246 .addr = 0x08, 247 .mask = GENMASK(5, 3), 248 }, 249 }, 250 .lir = { 251 .addr = 0x58, 252 .mask = BIT(0), 253 }, 254 .fifo_ops = { 255 .update_fifo = st_lsm6dsx_update_fifo, 256 .read_fifo = st_lsm6dsx_read_fifo, 257 .fifo_th = { 258 .addr = 0x06, 259 .mask = GENMASK(11, 0), 260 }, 261 .fifo_diff = { 262 .addr = 0x3a, 263 .mask = GENMASK(11, 0), 264 }, 265 .th_wl = 3, /* 1LSB = 2B */ 266 }, 267 .ts_settings = { 268 .timer_en = { 269 .addr = 0x58, 270 .mask = BIT(7), 271 }, 272 .hr_timer = { 273 .addr = 0x5c, 274 .mask = BIT(4), 275 }, 276 .fifo_en = { 277 .addr = 0x07, 278 .mask = BIT(7), 279 }, 280 .decimator = { 281 .addr = 0x09, 282 .mask = GENMASK(5, 3), 283 }, 284 }, 285 .event_settings = { 286 .wakeup_reg = { 287 .addr = 0x5B, 288 .mask = GENMASK(5, 0), 289 }, 290 }, 291 }, 292 { 293 .wai = 0x69, 294 .int1_addr = 0x0d, 295 .int2_addr = 0x0e, 296 .int1_func_addr = 0x5e, 297 .int2_func_addr = 0x5f, 298 .int_func_mask = BIT(5), 299 .reset_addr = 0x12, 300 .max_fifo_size = 682, 301 .id = { 302 { 303 .hw_id = ST_LSM6DS3H_ID, 304 .name = ST_LSM6DS3H_DEV_NAME, 305 }, 306 }, 307 .channels = { 308 [ST_LSM6DSX_ID_ACC] = { 309 .chan = st_lsm6dsx_acc_channels, 310 .len = ARRAY_SIZE(st_lsm6dsx_acc_channels), 311 }, 312 [ST_LSM6DSX_ID_GYRO] = { 313 .chan = st_lsm6dsx_gyro_channels, 314 .len = ARRAY_SIZE(st_lsm6dsx_gyro_channels), 315 }, 316 }, 317 .odr_table = { 318 [ST_LSM6DSX_ID_ACC] = { 319 .reg = { 320 .addr = 0x10, 321 .mask = GENMASK(7, 4), 322 }, 323 .odr_avl[0] = { 13, 0x01 }, 324 .odr_avl[1] = { 26, 0x02 }, 325 .odr_avl[2] = { 52, 0x03 }, 326 .odr_avl[3] = { 104, 0x04 }, 327 .odr_avl[4] = { 208, 0x05 }, 328 .odr_avl[5] = { 416, 0x06 }, 329 }, 330 [ST_LSM6DSX_ID_GYRO] = { 331 .reg = { 332 .addr = 0x11, 333 .mask = GENMASK(7, 4), 334 }, 335 .odr_avl[0] = { 13, 0x01 }, 336 .odr_avl[1] = { 26, 0x02 }, 337 .odr_avl[2] = { 52, 0x03 }, 338 .odr_avl[3] = { 104, 0x04 }, 339 .odr_avl[4] = { 208, 0x05 }, 340 .odr_avl[5] = { 416, 0x06 }, 341 }, 342 }, 343 .fs_table = { 344 [ST_LSM6DSX_ID_ACC] = { 345 .reg = { 346 .addr = 0x10, 347 .mask = GENMASK(3, 2), 348 }, 349 .fs_avl[0] = { IIO_G_TO_M_S_2(61), 0x0 }, 350 .fs_avl[1] = { IIO_G_TO_M_S_2(122), 0x2 }, 351 .fs_avl[2] = { IIO_G_TO_M_S_2(244), 0x3 }, 352 .fs_avl[3] = { IIO_G_TO_M_S_2(488), 0x1 }, 353 }, 354 [ST_LSM6DSX_ID_GYRO] = { 355 .reg = { 356 .addr = 0x11, 357 .mask = GENMASK(3, 2), 358 }, 359 .fs_avl[0] = { IIO_DEGREE_TO_RAD(8750), 0x0 }, 360 .fs_avl[1] = { IIO_DEGREE_TO_RAD(17500), 0x1 }, 361 .fs_avl[2] = { IIO_DEGREE_TO_RAD(35000), 0x2 }, 362 .fs_avl[3] = { IIO_DEGREE_TO_RAD(70000), 0x3 }, 363 }, 364 }, 365 .decimator = { 366 [ST_LSM6DSX_ID_ACC] = { 367 .addr = 0x08, 368 .mask = GENMASK(2, 0), 369 }, 370 [ST_LSM6DSX_ID_GYRO] = { 371 .addr = 0x08, 372 .mask = GENMASK(5, 3), 373 }, 374 }, 375 .lir = { 376 .addr = 0x58, 377 .mask = BIT(0), 378 }, 379 .fifo_ops = { 380 .update_fifo = st_lsm6dsx_update_fifo, 381 .read_fifo = st_lsm6dsx_read_fifo, 382 .fifo_th = { 383 .addr = 0x06, 384 .mask = GENMASK(11, 0), 385 }, 386 .fifo_diff = { 387 .addr = 0x3a, 388 .mask = GENMASK(11, 0), 389 }, 390 .th_wl = 3, /* 1LSB = 2B */ 391 }, 392 .ts_settings = { 393 .timer_en = { 394 .addr = 0x58, 395 .mask = BIT(7), 396 }, 397 .hr_timer = { 398 .addr = 0x5c, 399 .mask = BIT(4), 400 }, 401 .fifo_en = { 402 .addr = 0x07, 403 .mask = BIT(7), 404 }, 405 .decimator = { 406 .addr = 0x09, 407 .mask = GENMASK(5, 3), 408 }, 409 }, 410 .event_settings = { 411 .wakeup_reg = { 412 .addr = 0x5B, 413 .mask = GENMASK(5, 0), 414 }, 415 }, 416 }, 417 { 418 .wai = 0x6a, 419 .int1_addr = 0x0d, 420 .int2_addr = 0x0e, 421 .int1_func_addr = 0x5e, 422 .int2_func_addr = 0x5f, 423 .int_func_mask = BIT(5), 424 .reset_addr = 0x12, 425 .max_fifo_size = 682, 426 .id = { 427 { 428 .hw_id = ST_LSM6DSL_ID, 429 .name = ST_LSM6DSL_DEV_NAME, 430 }, { 431 .hw_id = ST_LSM6DSM_ID, 432 .name = ST_LSM6DSM_DEV_NAME, 433 }, { 434 .hw_id = ST_ISM330DLC_ID, 435 .name = ST_ISM330DLC_DEV_NAME, 436 }, { 437 .hw_id = ST_LSM6DS3TRC_ID, 438 .name = ST_LSM6DS3TRC_DEV_NAME, 439 }, 440 }, 441 .channels = { 442 [ST_LSM6DSX_ID_ACC] = { 443 .chan = st_lsm6dsx_acc_channels, 444 .len = ARRAY_SIZE(st_lsm6dsx_acc_channels), 445 }, 446 [ST_LSM6DSX_ID_GYRO] = { 447 .chan = st_lsm6dsx_gyro_channels, 448 .len = ARRAY_SIZE(st_lsm6dsx_gyro_channels), 449 }, 450 }, 451 .odr_table = { 452 [ST_LSM6DSX_ID_ACC] = { 453 .reg = { 454 .addr = 0x10, 455 .mask = GENMASK(7, 4), 456 }, 457 .odr_avl[0] = { 13, 0x01 }, 458 .odr_avl[1] = { 26, 0x02 }, 459 .odr_avl[2] = { 52, 0x03 }, 460 .odr_avl[3] = { 104, 0x04 }, 461 .odr_avl[4] = { 208, 0x05 }, 462 .odr_avl[5] = { 416, 0x06 }, 463 }, 464 [ST_LSM6DSX_ID_GYRO] = { 465 .reg = { 466 .addr = 0x11, 467 .mask = GENMASK(7, 4), 468 }, 469 .odr_avl[0] = { 13, 0x01 }, 470 .odr_avl[1] = { 26, 0x02 }, 471 .odr_avl[2] = { 52, 0x03 }, 472 .odr_avl[3] = { 104, 0x04 }, 473 .odr_avl[4] = { 208, 0x05 }, 474 .odr_avl[5] = { 416, 0x06 }, 475 }, 476 }, 477 .fs_table = { 478 [ST_LSM6DSX_ID_ACC] = { 479 .reg = { 480 .addr = 0x10, 481 .mask = GENMASK(3, 2), 482 }, 483 .fs_avl[0] = { IIO_G_TO_M_S_2(61), 0x0 }, 484 .fs_avl[1] = { IIO_G_TO_M_S_2(122), 0x2 }, 485 .fs_avl[2] = { IIO_G_TO_M_S_2(244), 0x3 }, 486 .fs_avl[3] = { IIO_G_TO_M_S_2(488), 0x1 }, 487 }, 488 [ST_LSM6DSX_ID_GYRO] = { 489 .reg = { 490 .addr = 0x11, 491 .mask = GENMASK(3, 2), 492 }, 493 .fs_avl[0] = { IIO_DEGREE_TO_RAD(8750), 0x0 }, 494 .fs_avl[1] = { IIO_DEGREE_TO_RAD(17500), 0x1 }, 495 .fs_avl[2] = { IIO_DEGREE_TO_RAD(35000), 0x2 }, 496 .fs_avl[3] = { IIO_DEGREE_TO_RAD(70000), 0x3 }, 497 }, 498 }, 499 .decimator = { 500 [ST_LSM6DSX_ID_ACC] = { 501 .addr = 0x08, 502 .mask = GENMASK(2, 0), 503 }, 504 [ST_LSM6DSX_ID_GYRO] = { 505 .addr = 0x08, 506 .mask = GENMASK(5, 3), 507 }, 508 }, 509 .lir = { 510 .addr = 0x58, 511 .mask = BIT(0), 512 }, 513 .fifo_ops = { 514 .update_fifo = st_lsm6dsx_update_fifo, 515 .read_fifo = st_lsm6dsx_read_fifo, 516 .fifo_th = { 517 .addr = 0x06, 518 .mask = GENMASK(10, 0), 519 }, 520 .fifo_diff = { 521 .addr = 0x3a, 522 .mask = GENMASK(10, 0), 523 }, 524 .th_wl = 3, /* 1LSB = 2B */ 525 }, 526 .ts_settings = { 527 .timer_en = { 528 .addr = 0x19, 529 .mask = BIT(5), 530 }, 531 .hr_timer = { 532 .addr = 0x5c, 533 .mask = BIT(4), 534 }, 535 .fifo_en = { 536 .addr = 0x07, 537 .mask = BIT(7), 538 }, 539 .decimator = { 540 .addr = 0x09, 541 .mask = GENMASK(5, 3), 542 }, 543 }, 544 .event_settings = { 545 .enable_reg = { 546 .addr = 0x58, 547 .mask = BIT(7), 548 }, 549 .wakeup_reg = { 550 .addr = 0x5B, 551 .mask = GENMASK(5, 0), 552 }, 553 }, 554 }, 555 { 556 .wai = 0x6c, 557 .int1_addr = 0x0d, 558 .int2_addr = 0x0e, 559 .reset_addr = 0x12, 560 .max_fifo_size = 512, 561 .id = { 562 { 563 .hw_id = ST_LSM6DSO_ID, 564 .name = ST_LSM6DSO_DEV_NAME, 565 }, { 566 .hw_id = ST_LSM6DSOX_ID, 567 .name = ST_LSM6DSOX_DEV_NAME, 568 }, 569 }, 570 .channels = { 571 [ST_LSM6DSX_ID_ACC] = { 572 .chan = st_lsm6dsx_acc_channels, 573 .len = ARRAY_SIZE(st_lsm6dsx_acc_channels), 574 }, 575 [ST_LSM6DSX_ID_GYRO] = { 576 .chan = st_lsm6dsx_gyro_channels, 577 .len = ARRAY_SIZE(st_lsm6dsx_gyro_channels), 578 }, 579 }, 580 .odr_table = { 581 [ST_LSM6DSX_ID_ACC] = { 582 .reg = { 583 .addr = 0x10, 584 .mask = GENMASK(7, 4), 585 }, 586 .odr_avl[0] = { 13, 0x01 }, 587 .odr_avl[1] = { 26, 0x02 }, 588 .odr_avl[2] = { 52, 0x03 }, 589 .odr_avl[3] = { 104, 0x04 }, 590 .odr_avl[4] = { 208, 0x05 }, 591 .odr_avl[5] = { 416, 0x06 }, 592 }, 593 [ST_LSM6DSX_ID_GYRO] = { 594 .reg = { 595 .addr = 0x11, 596 .mask = GENMASK(7, 4), 597 }, 598 .odr_avl[0] = { 13, 0x01 }, 599 .odr_avl[1] = { 26, 0x02 }, 600 .odr_avl[2] = { 52, 0x03 }, 601 .odr_avl[3] = { 104, 0x04 }, 602 .odr_avl[4] = { 208, 0x05 }, 603 .odr_avl[5] = { 416, 0x06 }, 604 }, 605 }, 606 .fs_table = { 607 [ST_LSM6DSX_ID_ACC] = { 608 .reg = { 609 .addr = 0x10, 610 .mask = GENMASK(3, 2), 611 }, 612 .fs_avl[0] = { IIO_G_TO_M_S_2(61), 0x0 }, 613 .fs_avl[1] = { IIO_G_TO_M_S_2(122), 0x2 }, 614 .fs_avl[2] = { IIO_G_TO_M_S_2(244), 0x3 }, 615 .fs_avl[3] = { IIO_G_TO_M_S_2(488), 0x1 }, 616 }, 617 [ST_LSM6DSX_ID_GYRO] = { 618 .reg = { 619 .addr = 0x11, 620 .mask = GENMASK(3, 2), 621 }, 622 .fs_avl[0] = { IIO_DEGREE_TO_RAD(8750), 0x0 }, 623 .fs_avl[1] = { IIO_DEGREE_TO_RAD(17500), 0x1 }, 624 .fs_avl[2] = { IIO_DEGREE_TO_RAD(35000), 0x2 }, 625 .fs_avl[3] = { IIO_DEGREE_TO_RAD(70000), 0x3 }, 626 }, 627 }, 628 .batch = { 629 [ST_LSM6DSX_ID_ACC] = { 630 .addr = 0x09, 631 .mask = GENMASK(3, 0), 632 }, 633 [ST_LSM6DSX_ID_GYRO] = { 634 .addr = 0x09, 635 .mask = GENMASK(7, 4), 636 }, 637 }, 638 .lir = { 639 .addr = 0x56, 640 .mask = BIT(0), 641 }, 642 .clear_on_read = { 643 .addr = 0x56, 644 .mask = BIT(6), 645 }, 646 .fifo_ops = { 647 .update_fifo = st_lsm6dsx_update_fifo, 648 .read_fifo = st_lsm6dsx_read_tagged_fifo, 649 .fifo_th = { 650 .addr = 0x07, 651 .mask = GENMASK(8, 0), 652 }, 653 .fifo_diff = { 654 .addr = 0x3a, 655 .mask = GENMASK(9, 0), 656 }, 657 .th_wl = 1, 658 }, 659 .ts_settings = { 660 .timer_en = { 661 .addr = 0x19, 662 .mask = BIT(5), 663 }, 664 .decimator = { 665 .addr = 0x0a, 666 .mask = GENMASK(7, 6), 667 }, 668 }, 669 .shub_settings = { 670 .page_mux = { 671 .addr = 0x01, 672 .mask = BIT(6), 673 }, 674 .master_en = { 675 .addr = 0x14, 676 .mask = BIT(2), 677 }, 678 .pullup_en = { 679 .addr = 0x14, 680 .mask = BIT(3), 681 }, 682 .aux_sens = { 683 .addr = 0x14, 684 .mask = GENMASK(1, 0), 685 }, 686 .wr_once = { 687 .addr = 0x14, 688 .mask = BIT(6), 689 }, 690 .shub_out = 0x02, 691 .slv0_addr = 0x15, 692 .dw_slv0_addr = 0x21, 693 .batch_en = BIT(3), 694 } 695 }, 696 { 697 .wai = 0x6b, 698 .int1_addr = 0x0d, 699 .int2_addr = 0x0e, 700 .int1_func_addr = 0x5e, 701 .int2_func_addr = 0x5f, 702 .int_func_mask = BIT(5), 703 .reset_addr = 0x12, 704 .max_fifo_size = 512, 705 .id = { 706 { 707 .hw_id = ST_ASM330LHH_ID, 708 .name = ST_ASM330LHH_DEV_NAME, 709 }, 710 }, 711 .channels = { 712 [ST_LSM6DSX_ID_ACC] = { 713 .chan = st_lsm6dsx_acc_channels, 714 .len = ARRAY_SIZE(st_lsm6dsx_acc_channels), 715 }, 716 [ST_LSM6DSX_ID_GYRO] = { 717 .chan = st_lsm6dsx_gyro_channels, 718 .len = ARRAY_SIZE(st_lsm6dsx_gyro_channels), 719 }, 720 }, 721 .odr_table = { 722 [ST_LSM6DSX_ID_ACC] = { 723 .reg = { 724 .addr = 0x10, 725 .mask = GENMASK(7, 4), 726 }, 727 .odr_avl[0] = { 13, 0x01 }, 728 .odr_avl[1] = { 26, 0x02 }, 729 .odr_avl[2] = { 52, 0x03 }, 730 .odr_avl[3] = { 104, 0x04 }, 731 .odr_avl[4] = { 208, 0x05 }, 732 .odr_avl[5] = { 416, 0x06 }, 733 }, 734 [ST_LSM6DSX_ID_GYRO] = { 735 .reg = { 736 .addr = 0x11, 737 .mask = GENMASK(7, 4), 738 }, 739 .odr_avl[0] = { 13, 0x01 }, 740 .odr_avl[1] = { 26, 0x02 }, 741 .odr_avl[2] = { 52, 0x03 }, 742 .odr_avl[3] = { 104, 0x04 }, 743 .odr_avl[4] = { 208, 0x05 }, 744 .odr_avl[5] = { 416, 0x06 }, 745 }, 746 }, 747 .fs_table = { 748 [ST_LSM6DSX_ID_ACC] = { 749 .reg = { 750 .addr = 0x10, 751 .mask = GENMASK(3, 2), 752 }, 753 .fs_avl[0] = { IIO_G_TO_M_S_2(61), 0x0 }, 754 .fs_avl[1] = { IIO_G_TO_M_S_2(122), 0x2 }, 755 .fs_avl[2] = { IIO_G_TO_M_S_2(244), 0x3 }, 756 .fs_avl[3] = { IIO_G_TO_M_S_2(488), 0x1 }, 757 }, 758 [ST_LSM6DSX_ID_GYRO] = { 759 .reg = { 760 .addr = 0x11, 761 .mask = GENMASK(3, 2), 762 }, 763 .fs_avl[0] = { IIO_DEGREE_TO_RAD(8750), 0x0 }, 764 .fs_avl[1] = { IIO_DEGREE_TO_RAD(17500), 0x1 }, 765 .fs_avl[2] = { IIO_DEGREE_TO_RAD(35000), 0x2 }, 766 .fs_avl[3] = { IIO_DEGREE_TO_RAD(70000), 0x3 }, 767 }, 768 }, 769 .batch = { 770 [ST_LSM6DSX_ID_ACC] = { 771 .addr = 0x09, 772 .mask = GENMASK(3, 0), 773 }, 774 [ST_LSM6DSX_ID_GYRO] = { 775 .addr = 0x09, 776 .mask = GENMASK(7, 4), 777 }, 778 }, 779 .lir = { 780 .addr = 0x56, 781 .mask = BIT(0), 782 }, 783 .clear_on_read = { 784 .addr = 0x56, 785 .mask = BIT(6), 786 }, 787 .fifo_ops = { 788 .update_fifo = st_lsm6dsx_update_fifo, 789 .read_fifo = st_lsm6dsx_read_tagged_fifo, 790 .fifo_th = { 791 .addr = 0x07, 792 .mask = GENMASK(8, 0), 793 }, 794 .fifo_diff = { 795 .addr = 0x3a, 796 .mask = GENMASK(9, 0), 797 }, 798 .th_wl = 1, 799 }, 800 .ts_settings = { 801 .timer_en = { 802 .addr = 0x19, 803 .mask = BIT(5), 804 }, 805 .decimator = { 806 .addr = 0x0a, 807 .mask = GENMASK(7, 6), 808 }, 809 }, 810 .event_settings = { 811 .enable_reg = { 812 .addr = 0x58, 813 .mask = BIT(7), 814 }, 815 .wakeup_reg = { 816 .addr = 0x5B, 817 .mask = GENMASK(5, 0), 818 }, 819 }, 820 }, 821 { 822 .wai = 0x6b, 823 .int1_addr = 0x0d, 824 .int2_addr = 0x0e, 825 .int1_func_addr = 0x5e, 826 .int2_func_addr = 0x5f, 827 .int_func_mask = BIT(5), 828 .reset_addr = 0x12, 829 .max_fifo_size = 512, 830 .id = { 831 { 832 .hw_id = ST_LSM6DSR_ID, 833 .name = ST_LSM6DSR_DEV_NAME, 834 }, { 835 .hw_id = ST_ISM330DHCX_ID, 836 .name = ST_ISM330DHCX_DEV_NAME, 837 }, 838 }, 839 .channels = { 840 [ST_LSM6DSX_ID_ACC] = { 841 .chan = st_lsm6dsx_acc_channels, 842 .len = ARRAY_SIZE(st_lsm6dsx_acc_channels), 843 }, 844 [ST_LSM6DSX_ID_GYRO] = { 845 .chan = st_lsm6dsx_gyro_channels, 846 .len = ARRAY_SIZE(st_lsm6dsx_gyro_channels), 847 }, 848 }, 849 .odr_table = { 850 [ST_LSM6DSX_ID_ACC] = { 851 .reg = { 852 .addr = 0x10, 853 .mask = GENMASK(7, 4), 854 }, 855 .odr_avl[0] = { 13, 0x01 }, 856 .odr_avl[1] = { 26, 0x02 }, 857 .odr_avl[2] = { 52, 0x03 }, 858 .odr_avl[3] = { 104, 0x04 }, 859 .odr_avl[4] = { 208, 0x05 }, 860 .odr_avl[5] = { 416, 0x06 }, 861 }, 862 [ST_LSM6DSX_ID_GYRO] = { 863 .reg = { 864 .addr = 0x11, 865 .mask = GENMASK(7, 4), 866 }, 867 .odr_avl[0] = { 13, 0x01 }, 868 .odr_avl[1] = { 26, 0x02 }, 869 .odr_avl[2] = { 52, 0x03 }, 870 .odr_avl[3] = { 104, 0x04 }, 871 .odr_avl[4] = { 208, 0x05 }, 872 .odr_avl[5] = { 416, 0x06 }, 873 }, 874 }, 875 .fs_table = { 876 [ST_LSM6DSX_ID_ACC] = { 877 .reg = { 878 .addr = 0x10, 879 .mask = GENMASK(3, 2), 880 }, 881 .fs_avl[0] = { IIO_G_TO_M_S_2(61), 0x0 }, 882 .fs_avl[1] = { IIO_G_TO_M_S_2(122), 0x2 }, 883 .fs_avl[2] = { IIO_G_TO_M_S_2(244), 0x3 }, 884 .fs_avl[3] = { IIO_G_TO_M_S_2(488), 0x1 }, 885 }, 886 [ST_LSM6DSX_ID_GYRO] = { 887 .reg = { 888 .addr = 0x11, 889 .mask = GENMASK(3, 2), 890 }, 891 .fs_avl[0] = { IIO_DEGREE_TO_RAD(8750), 0x0 }, 892 .fs_avl[1] = { IIO_DEGREE_TO_RAD(17500), 0x1 }, 893 .fs_avl[2] = { IIO_DEGREE_TO_RAD(35000), 0x2 }, 894 .fs_avl[3] = { IIO_DEGREE_TO_RAD(70000), 0x3 }, 895 }, 896 }, 897 .batch = { 898 [ST_LSM6DSX_ID_ACC] = { 899 .addr = 0x09, 900 .mask = GENMASK(3, 0), 901 }, 902 [ST_LSM6DSX_ID_GYRO] = { 903 .addr = 0x09, 904 .mask = GENMASK(7, 4), 905 }, 906 }, 907 .lir = { 908 .addr = 0x56, 909 .mask = BIT(0), 910 }, 911 .clear_on_read = { 912 .addr = 0x56, 913 .mask = BIT(6), 914 }, 915 .fifo_ops = { 916 .update_fifo = st_lsm6dsx_update_fifo, 917 .read_fifo = st_lsm6dsx_read_tagged_fifo, 918 .fifo_th = { 919 .addr = 0x07, 920 .mask = GENMASK(8, 0), 921 }, 922 .fifo_diff = { 923 .addr = 0x3a, 924 .mask = GENMASK(9, 0), 925 }, 926 .th_wl = 1, 927 }, 928 .ts_settings = { 929 .timer_en = { 930 .addr = 0x19, 931 .mask = BIT(5), 932 }, 933 .decimator = { 934 .addr = 0x0a, 935 .mask = GENMASK(7, 6), 936 }, 937 }, 938 .shub_settings = { 939 .page_mux = { 940 .addr = 0x01, 941 .mask = BIT(6), 942 }, 943 .master_en = { 944 .addr = 0x14, 945 .mask = BIT(2), 946 }, 947 .pullup_en = { 948 .addr = 0x14, 949 .mask = BIT(3), 950 }, 951 .aux_sens = { 952 .addr = 0x14, 953 .mask = GENMASK(1, 0), 954 }, 955 .wr_once = { 956 .addr = 0x14, 957 .mask = BIT(6), 958 }, 959 .shub_out = 0x02, 960 .slv0_addr = 0x15, 961 .dw_slv0_addr = 0x21, 962 .batch_en = BIT(3), 963 }, 964 .event_settings = { 965 .enable_reg = { 966 .addr = 0x58, 967 .mask = BIT(7), 968 }, 969 .wakeup_reg = { 970 .addr = 0x5B, 971 .mask = GENMASK(5, 0), 972 }, 973 } 974 }, 975 }; 976 977 int st_lsm6dsx_set_page(struct st_lsm6dsx_hw *hw, bool enable) 978 { 979 const struct st_lsm6dsx_shub_settings *hub_settings; 980 unsigned int data; 981 int err; 982 983 hub_settings = &hw->settings->shub_settings; 984 data = ST_LSM6DSX_SHIFT_VAL(enable, hub_settings->page_mux.mask); 985 err = regmap_update_bits(hw->regmap, hub_settings->page_mux.addr, 986 hub_settings->page_mux.mask, data); 987 usleep_range(100, 150); 988 989 return err; 990 } 991 992 static int st_lsm6dsx_check_whoami(struct st_lsm6dsx_hw *hw, int id, 993 const char **name) 994 { 995 int err, i, j, data; 996 997 for (i = 0; i < ARRAY_SIZE(st_lsm6dsx_sensor_settings); i++) { 998 for (j = 0; j < ST_LSM6DSX_MAX_ID; j++) { 999 if (id == st_lsm6dsx_sensor_settings[i].id[j].hw_id) 1000 break; 1001 } 1002 if (j < ST_LSM6DSX_MAX_ID) 1003 break; 1004 } 1005 1006 if (i == ARRAY_SIZE(st_lsm6dsx_sensor_settings)) { 1007 dev_err(hw->dev, "unsupported hw id [%02x]\n", id); 1008 return -ENODEV; 1009 } 1010 1011 err = regmap_read(hw->regmap, ST_LSM6DSX_REG_WHOAMI_ADDR, &data); 1012 if (err < 0) { 1013 dev_err(hw->dev, "failed to read whoami register\n"); 1014 return err; 1015 } 1016 1017 if (data != st_lsm6dsx_sensor_settings[i].wai) { 1018 dev_err(hw->dev, "unsupported whoami [%02x]\n", data); 1019 return -ENODEV; 1020 } 1021 1022 *name = st_lsm6dsx_sensor_settings[i].id[j].name; 1023 hw->settings = &st_lsm6dsx_sensor_settings[i]; 1024 1025 return 0; 1026 } 1027 1028 static int st_lsm6dsx_set_full_scale(struct st_lsm6dsx_sensor *sensor, 1029 u32 gain) 1030 { 1031 const struct st_lsm6dsx_fs_table_entry *fs_table; 1032 unsigned int data; 1033 int i, err; 1034 1035 fs_table = &sensor->hw->settings->fs_table[sensor->id]; 1036 for (i = 0; i < ST_LSM6DSX_FS_LIST_SIZE; i++) 1037 if (fs_table->fs_avl[i].gain == gain) 1038 break; 1039 1040 if (i == ST_LSM6DSX_FS_LIST_SIZE) 1041 return -EINVAL; 1042 1043 data = ST_LSM6DSX_SHIFT_VAL(fs_table->fs_avl[i].val, 1044 fs_table->reg.mask); 1045 err = st_lsm6dsx_update_bits_locked(sensor->hw, fs_table->reg.addr, 1046 fs_table->reg.mask, data); 1047 if (err < 0) 1048 return err; 1049 1050 sensor->gain = gain; 1051 1052 return 0; 1053 } 1054 1055 int st_lsm6dsx_check_odr(struct st_lsm6dsx_sensor *sensor, u16 odr, u8 *val) 1056 { 1057 const struct st_lsm6dsx_odr_table_entry *odr_table; 1058 int i; 1059 1060 odr_table = &sensor->hw->settings->odr_table[sensor->id]; 1061 for (i = 0; i < ST_LSM6DSX_ODR_LIST_SIZE; i++) 1062 /* 1063 * ext devices can run at different odr respect to 1064 * accel sensor 1065 */ 1066 if (odr_table->odr_avl[i].hz >= odr) 1067 break; 1068 1069 if (i == ST_LSM6DSX_ODR_LIST_SIZE) 1070 return -EINVAL; 1071 1072 *val = odr_table->odr_avl[i].val; 1073 1074 return 0; 1075 } 1076 1077 static u16 st_lsm6dsx_check_odr_dependency(struct st_lsm6dsx_hw *hw, u16 odr, 1078 enum st_lsm6dsx_sensor_id id) 1079 { 1080 struct st_lsm6dsx_sensor *ref = iio_priv(hw->iio_devs[id]); 1081 1082 if (odr > 0) { 1083 if (hw->enable_mask & BIT(id)) 1084 return max_t(u16, ref->odr, odr); 1085 else 1086 return odr; 1087 } else { 1088 return (hw->enable_mask & BIT(id)) ? ref->odr : 0; 1089 } 1090 } 1091 1092 static int st_lsm6dsx_set_odr(struct st_lsm6dsx_sensor *sensor, u16 req_odr) 1093 { 1094 struct st_lsm6dsx_sensor *ref_sensor = sensor; 1095 struct st_lsm6dsx_hw *hw = sensor->hw; 1096 const struct st_lsm6dsx_reg *reg; 1097 unsigned int data; 1098 u8 val = 0; 1099 int err; 1100 1101 switch (sensor->id) { 1102 case ST_LSM6DSX_ID_EXT0: 1103 case ST_LSM6DSX_ID_EXT1: 1104 case ST_LSM6DSX_ID_EXT2: 1105 case ST_LSM6DSX_ID_ACC: { 1106 u16 odr; 1107 int i; 1108 1109 /* 1110 * i2c embedded controller relies on the accelerometer sensor as 1111 * bus read/write trigger so we need to enable accel device 1112 * at odr = max(accel_odr, ext_odr) in order to properly 1113 * communicate with i2c slave devices 1114 */ 1115 ref_sensor = iio_priv(hw->iio_devs[ST_LSM6DSX_ID_ACC]); 1116 for (i = ST_LSM6DSX_ID_ACC; i < ST_LSM6DSX_ID_MAX; i++) { 1117 if (!hw->iio_devs[i] || i == sensor->id) 1118 continue; 1119 1120 odr = st_lsm6dsx_check_odr_dependency(hw, req_odr, i); 1121 if (odr != req_odr) 1122 /* device already configured */ 1123 return 0; 1124 } 1125 break; 1126 } 1127 default: 1128 break; 1129 } 1130 1131 if (req_odr > 0) { 1132 err = st_lsm6dsx_check_odr(ref_sensor, req_odr, &val); 1133 if (err < 0) 1134 return err; 1135 } 1136 1137 reg = &hw->settings->odr_table[ref_sensor->id].reg; 1138 data = ST_LSM6DSX_SHIFT_VAL(val, reg->mask); 1139 return st_lsm6dsx_update_bits_locked(hw, reg->addr, reg->mask, data); 1140 } 1141 1142 int st_lsm6dsx_sensor_set_enable(struct st_lsm6dsx_sensor *sensor, 1143 bool enable) 1144 { 1145 struct st_lsm6dsx_hw *hw = sensor->hw; 1146 u16 odr = enable ? sensor->odr : 0; 1147 int err; 1148 1149 err = st_lsm6dsx_set_odr(sensor, odr); 1150 if (err < 0) 1151 return err; 1152 1153 if (enable) 1154 hw->enable_mask |= BIT(sensor->id); 1155 else 1156 hw->enable_mask &= ~BIT(sensor->id); 1157 1158 return 0; 1159 } 1160 1161 static int st_lsm6dsx_read_oneshot(struct st_lsm6dsx_sensor *sensor, 1162 u8 addr, int *val) 1163 { 1164 struct st_lsm6dsx_hw *hw = sensor->hw; 1165 int err, delay; 1166 __le16 data; 1167 1168 err = st_lsm6dsx_sensor_set_enable(sensor, true); 1169 if (err < 0) 1170 return err; 1171 1172 delay = 1000000 / sensor->odr; 1173 usleep_range(delay, 2 * delay); 1174 1175 err = st_lsm6dsx_read_locked(hw, addr, &data, sizeof(data)); 1176 if (err < 0) 1177 return err; 1178 1179 if (!hw->enable_event) 1180 st_lsm6dsx_sensor_set_enable(sensor, false); 1181 1182 *val = (s16)le16_to_cpu(data); 1183 1184 return IIO_VAL_INT; 1185 } 1186 1187 static int st_lsm6dsx_read_raw(struct iio_dev *iio_dev, 1188 struct iio_chan_spec const *ch, 1189 int *val, int *val2, long mask) 1190 { 1191 struct st_lsm6dsx_sensor *sensor = iio_priv(iio_dev); 1192 int ret; 1193 1194 switch (mask) { 1195 case IIO_CHAN_INFO_RAW: 1196 ret = iio_device_claim_direct_mode(iio_dev); 1197 if (ret) 1198 break; 1199 1200 ret = st_lsm6dsx_read_oneshot(sensor, ch->address, val); 1201 iio_device_release_direct_mode(iio_dev); 1202 break; 1203 case IIO_CHAN_INFO_SAMP_FREQ: 1204 *val = sensor->odr; 1205 ret = IIO_VAL_INT; 1206 break; 1207 case IIO_CHAN_INFO_SCALE: 1208 *val = 0; 1209 *val2 = sensor->gain; 1210 ret = IIO_VAL_INT_PLUS_MICRO; 1211 break; 1212 default: 1213 ret = -EINVAL; 1214 break; 1215 } 1216 1217 return ret; 1218 } 1219 1220 static int st_lsm6dsx_write_raw(struct iio_dev *iio_dev, 1221 struct iio_chan_spec const *chan, 1222 int val, int val2, long mask) 1223 { 1224 struct st_lsm6dsx_sensor *sensor = iio_priv(iio_dev); 1225 int err; 1226 1227 err = iio_device_claim_direct_mode(iio_dev); 1228 if (err) 1229 return err; 1230 1231 switch (mask) { 1232 case IIO_CHAN_INFO_SCALE: 1233 err = st_lsm6dsx_set_full_scale(sensor, val2); 1234 break; 1235 case IIO_CHAN_INFO_SAMP_FREQ: { 1236 u8 data; 1237 1238 err = st_lsm6dsx_check_odr(sensor, val, &data); 1239 if (!err) 1240 sensor->odr = val; 1241 break; 1242 } 1243 default: 1244 err = -EINVAL; 1245 break; 1246 } 1247 1248 iio_device_release_direct_mode(iio_dev); 1249 1250 return err; 1251 } 1252 1253 static int st_lsm6dsx_event_setup(struct st_lsm6dsx_hw *hw, int state) 1254 { 1255 int err; 1256 u8 enable = 0; 1257 1258 if (!hw->settings->int1_func_addr) 1259 return -ENOTSUPP; 1260 1261 enable = state ? hw->settings->event_settings.enable_reg.mask : 0; 1262 1263 err = regmap_update_bits(hw->regmap, 1264 hw->settings->event_settings.enable_reg.addr, 1265 hw->settings->event_settings.enable_reg.mask, 1266 enable); 1267 if (err < 0) 1268 return err; 1269 1270 enable = state ? hw->irq_routing.mask : 0; 1271 1272 /* Enable wakeup interrupt */ 1273 return regmap_update_bits(hw->regmap, hw->irq_routing.addr, 1274 hw->irq_routing.mask, 1275 enable); 1276 } 1277 1278 static int st_lsm6dsx_read_event(struct iio_dev *iio_dev, 1279 const struct iio_chan_spec *chan, 1280 enum iio_event_type type, 1281 enum iio_event_direction dir, 1282 enum iio_event_info info, 1283 int *val, int *val2) 1284 { 1285 struct st_lsm6dsx_sensor *sensor = iio_priv(iio_dev); 1286 struct st_lsm6dsx_hw *hw = sensor->hw; 1287 1288 if (type != IIO_EV_TYPE_THRESH) 1289 return -EINVAL; 1290 1291 *val2 = 0; 1292 *val = hw->event_threshold; 1293 1294 return IIO_VAL_INT; 1295 } 1296 1297 static int st_lsm6dsx_write_event(struct iio_dev *iio_dev, 1298 const struct iio_chan_spec *chan, 1299 enum iio_event_type type, 1300 enum iio_event_direction dir, 1301 enum iio_event_info info, 1302 int val, int val2) 1303 { 1304 struct st_lsm6dsx_sensor *sensor = iio_priv(iio_dev); 1305 struct st_lsm6dsx_hw *hw = sensor->hw; 1306 int err; 1307 1308 if (type != IIO_EV_TYPE_THRESH) 1309 return -EINVAL; 1310 1311 if (val < 0 || val > 31) 1312 return -EINVAL; 1313 1314 err = regmap_update_bits(hw->regmap, 1315 hw->settings->event_settings.wakeup_reg.addr, 1316 hw->settings->event_settings.wakeup_reg.mask, 1317 val); 1318 if (err) 1319 return -EINVAL; 1320 1321 hw->event_threshold = val; 1322 1323 return 0; 1324 } 1325 1326 static int st_lsm6dsx_read_event_config(struct iio_dev *iio_dev, 1327 const struct iio_chan_spec *chan, 1328 enum iio_event_type type, 1329 enum iio_event_direction dir) 1330 { 1331 struct st_lsm6dsx_sensor *sensor = iio_priv(iio_dev); 1332 struct st_lsm6dsx_hw *hw = sensor->hw; 1333 1334 if (type != IIO_EV_TYPE_THRESH) 1335 return -EINVAL; 1336 1337 return hw->enable_event; 1338 } 1339 1340 static int st_lsm6dsx_write_event_config(struct iio_dev *iio_dev, 1341 const struct iio_chan_spec *chan, 1342 enum iio_event_type type, 1343 enum iio_event_direction dir, 1344 int state) 1345 { 1346 struct st_lsm6dsx_sensor *sensor = iio_priv(iio_dev); 1347 struct st_lsm6dsx_hw *hw = sensor->hw; 1348 int err = 0; 1349 1350 if (type != IIO_EV_TYPE_THRESH) 1351 return -EINVAL; 1352 1353 /* do not enable events if they are already enabled */ 1354 if (state && hw->enable_event) 1355 return 0; 1356 1357 err = st_lsm6dsx_event_setup(hw, state); 1358 if (err < 0) 1359 return err; 1360 1361 err = st_lsm6dsx_sensor_set_enable(sensor, state); 1362 if (err < 0) 1363 return err; 1364 1365 hw->enable_event = state; 1366 1367 return 0; 1368 } 1369 1370 int st_lsm6dsx_set_watermark(struct iio_dev *iio_dev, unsigned int val) 1371 { 1372 struct st_lsm6dsx_sensor *sensor = iio_priv(iio_dev); 1373 struct st_lsm6dsx_hw *hw = sensor->hw; 1374 int err; 1375 1376 if (val < 1 || val > hw->settings->max_fifo_size) 1377 return -EINVAL; 1378 1379 mutex_lock(&hw->conf_lock); 1380 1381 err = st_lsm6dsx_update_watermark(sensor, val); 1382 1383 mutex_unlock(&hw->conf_lock); 1384 1385 if (err < 0) 1386 return err; 1387 1388 sensor->watermark = val; 1389 1390 return 0; 1391 } 1392 1393 static ssize_t 1394 st_lsm6dsx_sysfs_sampling_frequency_avail(struct device *dev, 1395 struct device_attribute *attr, 1396 char *buf) 1397 { 1398 struct st_lsm6dsx_sensor *sensor = iio_priv(dev_get_drvdata(dev)); 1399 enum st_lsm6dsx_sensor_id id = sensor->id; 1400 struct st_lsm6dsx_hw *hw = sensor->hw; 1401 int i, len = 0; 1402 1403 for (i = 0; i < ST_LSM6DSX_ODR_LIST_SIZE; i++) 1404 len += scnprintf(buf + len, PAGE_SIZE - len, "%d ", 1405 hw->settings->odr_table[id].odr_avl[i].hz); 1406 buf[len - 1] = '\n'; 1407 1408 return len; 1409 } 1410 1411 static ssize_t st_lsm6dsx_sysfs_scale_avail(struct device *dev, 1412 struct device_attribute *attr, 1413 char *buf) 1414 { 1415 struct st_lsm6dsx_sensor *sensor = iio_priv(dev_get_drvdata(dev)); 1416 const struct st_lsm6dsx_fs_table_entry *fs_table; 1417 enum st_lsm6dsx_sensor_id id = sensor->id; 1418 struct st_lsm6dsx_hw *hw = sensor->hw; 1419 int i, len = 0; 1420 1421 fs_table = &hw->settings->fs_table[id]; 1422 for (i = 0; i < ST_LSM6DSX_FS_LIST_SIZE; i++) { 1423 if (!fs_table->fs_avl[i].gain) 1424 break; 1425 1426 len += scnprintf(buf + len, PAGE_SIZE - len, "0.%06u ", 1427 fs_table->fs_avl[i].gain); 1428 } 1429 buf[len - 1] = '\n'; 1430 1431 return len; 1432 } 1433 1434 static IIO_DEV_ATTR_SAMP_FREQ_AVAIL(st_lsm6dsx_sysfs_sampling_frequency_avail); 1435 static IIO_DEVICE_ATTR(in_accel_scale_available, 0444, 1436 st_lsm6dsx_sysfs_scale_avail, NULL, 0); 1437 static IIO_DEVICE_ATTR(in_anglvel_scale_available, 0444, 1438 st_lsm6dsx_sysfs_scale_avail, NULL, 0); 1439 1440 static struct attribute *st_lsm6dsx_acc_attributes[] = { 1441 &iio_dev_attr_sampling_frequency_available.dev_attr.attr, 1442 &iio_dev_attr_in_accel_scale_available.dev_attr.attr, 1443 NULL, 1444 }; 1445 1446 static const struct attribute_group st_lsm6dsx_acc_attribute_group = { 1447 .attrs = st_lsm6dsx_acc_attributes, 1448 }; 1449 1450 static const struct iio_info st_lsm6dsx_acc_info = { 1451 .attrs = &st_lsm6dsx_acc_attribute_group, 1452 .read_raw = st_lsm6dsx_read_raw, 1453 .write_raw = st_lsm6dsx_write_raw, 1454 .read_event_value = st_lsm6dsx_read_event, 1455 .write_event_value = st_lsm6dsx_write_event, 1456 .read_event_config = st_lsm6dsx_read_event_config, 1457 .write_event_config = st_lsm6dsx_write_event_config, 1458 .hwfifo_set_watermark = st_lsm6dsx_set_watermark, 1459 }; 1460 1461 static struct attribute *st_lsm6dsx_gyro_attributes[] = { 1462 &iio_dev_attr_sampling_frequency_available.dev_attr.attr, 1463 &iio_dev_attr_in_anglvel_scale_available.dev_attr.attr, 1464 NULL, 1465 }; 1466 1467 static const struct attribute_group st_lsm6dsx_gyro_attribute_group = { 1468 .attrs = st_lsm6dsx_gyro_attributes, 1469 }; 1470 1471 static const struct iio_info st_lsm6dsx_gyro_info = { 1472 .attrs = &st_lsm6dsx_gyro_attribute_group, 1473 .read_raw = st_lsm6dsx_read_raw, 1474 .write_raw = st_lsm6dsx_write_raw, 1475 .hwfifo_set_watermark = st_lsm6dsx_set_watermark, 1476 }; 1477 1478 static int st_lsm6dsx_of_get_drdy_pin(struct st_lsm6dsx_hw *hw, int *drdy_pin) 1479 { 1480 struct device_node *np = hw->dev->of_node; 1481 1482 if (!np) 1483 return -EINVAL; 1484 1485 return of_property_read_u32(np, "st,drdy-int-pin", drdy_pin); 1486 } 1487 1488 static int st_lsm6dsx_get_drdy_reg(struct st_lsm6dsx_hw *hw, u8 *drdy_reg) 1489 { 1490 int err = 0, drdy_pin; 1491 1492 if (st_lsm6dsx_of_get_drdy_pin(hw, &drdy_pin) < 0) { 1493 struct st_sensors_platform_data *pdata; 1494 struct device *dev = hw->dev; 1495 1496 pdata = (struct st_sensors_platform_data *)dev->platform_data; 1497 drdy_pin = pdata ? pdata->drdy_int_pin : 1; 1498 } 1499 1500 switch (drdy_pin) { 1501 case 1: 1502 *drdy_reg = hw->settings->int1_addr; 1503 hw->irq_routing.addr = hw->settings->int1_func_addr; 1504 hw->irq_routing.mask = hw->settings->int_func_mask; 1505 break; 1506 case 2: 1507 *drdy_reg = hw->settings->int2_addr; 1508 hw->irq_routing.addr = hw->settings->int2_func_addr; 1509 hw->irq_routing.mask = hw->settings->int_func_mask; 1510 break; 1511 default: 1512 dev_err(hw->dev, "unsupported data ready pin\n"); 1513 err = -EINVAL; 1514 break; 1515 } 1516 1517 return err; 1518 } 1519 1520 static int st_lsm6dsx_init_shub(struct st_lsm6dsx_hw *hw) 1521 { 1522 const struct st_lsm6dsx_shub_settings *hub_settings; 1523 struct device_node *np = hw->dev->of_node; 1524 struct st_sensors_platform_data *pdata; 1525 unsigned int data; 1526 int err = 0; 1527 1528 hub_settings = &hw->settings->shub_settings; 1529 1530 pdata = (struct st_sensors_platform_data *)hw->dev->platform_data; 1531 if ((np && of_property_read_bool(np, "st,pullups")) || 1532 (pdata && pdata->pullups)) { 1533 err = st_lsm6dsx_set_page(hw, true); 1534 if (err < 0) 1535 return err; 1536 1537 data = ST_LSM6DSX_SHIFT_VAL(1, hub_settings->pullup_en.mask); 1538 err = regmap_update_bits(hw->regmap, 1539 hub_settings->pullup_en.addr, 1540 hub_settings->pullup_en.mask, data); 1541 1542 st_lsm6dsx_set_page(hw, false); 1543 1544 if (err < 0) 1545 return err; 1546 } 1547 1548 if (hub_settings->aux_sens.addr) { 1549 /* configure aux sensors */ 1550 err = st_lsm6dsx_set_page(hw, true); 1551 if (err < 0) 1552 return err; 1553 1554 data = ST_LSM6DSX_SHIFT_VAL(3, hub_settings->aux_sens.mask); 1555 err = regmap_update_bits(hw->regmap, 1556 hub_settings->aux_sens.addr, 1557 hub_settings->aux_sens.mask, data); 1558 1559 st_lsm6dsx_set_page(hw, false); 1560 } 1561 1562 return err; 1563 } 1564 1565 static int st_lsm6dsx_init_hw_timer(struct st_lsm6dsx_hw *hw) 1566 { 1567 const struct st_lsm6dsx_hw_ts_settings *ts_settings; 1568 int err, val; 1569 1570 ts_settings = &hw->settings->ts_settings; 1571 /* enable hw timestamp generation if necessary */ 1572 if (ts_settings->timer_en.addr) { 1573 val = ST_LSM6DSX_SHIFT_VAL(1, ts_settings->timer_en.mask); 1574 err = regmap_update_bits(hw->regmap, 1575 ts_settings->timer_en.addr, 1576 ts_settings->timer_en.mask, val); 1577 if (err < 0) 1578 return err; 1579 } 1580 1581 /* enable high resolution for hw ts timer if necessary */ 1582 if (ts_settings->hr_timer.addr) { 1583 val = ST_LSM6DSX_SHIFT_VAL(1, ts_settings->hr_timer.mask); 1584 err = regmap_update_bits(hw->regmap, 1585 ts_settings->hr_timer.addr, 1586 ts_settings->hr_timer.mask, val); 1587 if (err < 0) 1588 return err; 1589 } 1590 1591 /* enable ts queueing in FIFO if necessary */ 1592 if (ts_settings->fifo_en.addr) { 1593 val = ST_LSM6DSX_SHIFT_VAL(1, ts_settings->fifo_en.mask); 1594 err = regmap_update_bits(hw->regmap, 1595 ts_settings->fifo_en.addr, 1596 ts_settings->fifo_en.mask, val); 1597 if (err < 0) 1598 return err; 1599 } 1600 return 0; 1601 } 1602 1603 static int st_lsm6dsx_init_device(struct st_lsm6dsx_hw *hw) 1604 { 1605 u8 drdy_int_reg; 1606 int err; 1607 1608 /* device sw reset */ 1609 err = regmap_update_bits(hw->regmap, hw->settings->reset_addr, 1610 ST_LSM6DSX_REG_RESET_MASK, 1611 FIELD_PREP(ST_LSM6DSX_REG_RESET_MASK, 1)); 1612 if (err < 0) 1613 return err; 1614 1615 msleep(50); 1616 1617 /* reload trimming parameter */ 1618 err = regmap_update_bits(hw->regmap, hw->settings->reset_addr, 1619 ST_LSM6DSX_REG_BOOT_MASK, 1620 FIELD_PREP(ST_LSM6DSX_REG_BOOT_MASK, 1)); 1621 if (err < 0) 1622 return err; 1623 1624 msleep(50); 1625 1626 /* enable Block Data Update */ 1627 err = regmap_update_bits(hw->regmap, ST_LSM6DSX_REG_BDU_ADDR, 1628 ST_LSM6DSX_REG_BDU_MASK, 1629 FIELD_PREP(ST_LSM6DSX_REG_BDU_MASK, 1)); 1630 if (err < 0) 1631 return err; 1632 1633 /* enable FIFO watermak interrupt */ 1634 err = st_lsm6dsx_get_drdy_reg(hw, &drdy_int_reg); 1635 if (err < 0) 1636 return err; 1637 1638 err = regmap_update_bits(hw->regmap, drdy_int_reg, 1639 ST_LSM6DSX_REG_FIFO_FTH_IRQ_MASK, 1640 FIELD_PREP(ST_LSM6DSX_REG_FIFO_FTH_IRQ_MASK, 1641 1)); 1642 if (err < 0) 1643 return err; 1644 1645 /* enable Latched interrupts for device events */ 1646 if (hw->settings->lir.addr) { 1647 unsigned int data; 1648 1649 data = ST_LSM6DSX_SHIFT_VAL(1, hw->settings->lir.mask); 1650 err = regmap_update_bits(hw->regmap, hw->settings->lir.addr, 1651 hw->settings->lir.mask, data); 1652 if (err < 0) 1653 return err; 1654 1655 /* enable clear on read for latched interrupts */ 1656 if (hw->settings->clear_on_read.addr) { 1657 data = ST_LSM6DSX_SHIFT_VAL(1, 1658 hw->settings->clear_on_read.mask); 1659 err = regmap_update_bits(hw->regmap, 1660 hw->settings->clear_on_read.addr, 1661 hw->settings->clear_on_read.mask, 1662 data); 1663 if (err < 0) 1664 return err; 1665 } 1666 } 1667 1668 err = st_lsm6dsx_init_shub(hw); 1669 if (err < 0) 1670 return err; 1671 1672 return st_lsm6dsx_init_hw_timer(hw); 1673 } 1674 1675 static struct iio_dev *st_lsm6dsx_alloc_iiodev(struct st_lsm6dsx_hw *hw, 1676 enum st_lsm6dsx_sensor_id id, 1677 const char *name) 1678 { 1679 struct st_lsm6dsx_sensor *sensor; 1680 struct iio_dev *iio_dev; 1681 1682 iio_dev = devm_iio_device_alloc(hw->dev, sizeof(*sensor)); 1683 if (!iio_dev) 1684 return NULL; 1685 1686 iio_dev->modes = INDIO_DIRECT_MODE; 1687 iio_dev->dev.parent = hw->dev; 1688 iio_dev->available_scan_masks = st_lsm6dsx_available_scan_masks; 1689 iio_dev->channels = hw->settings->channels[id].chan; 1690 iio_dev->num_channels = hw->settings->channels[id].len; 1691 1692 sensor = iio_priv(iio_dev); 1693 sensor->id = id; 1694 sensor->hw = hw; 1695 sensor->odr = hw->settings->odr_table[id].odr_avl[0].hz; 1696 sensor->gain = hw->settings->fs_table[id].fs_avl[0].gain; 1697 sensor->watermark = 1; 1698 1699 switch (id) { 1700 case ST_LSM6DSX_ID_ACC: 1701 iio_dev->info = &st_lsm6dsx_acc_info; 1702 scnprintf(sensor->name, sizeof(sensor->name), "%s_accel", 1703 name); 1704 break; 1705 case ST_LSM6DSX_ID_GYRO: 1706 iio_dev->info = &st_lsm6dsx_gyro_info; 1707 scnprintf(sensor->name, sizeof(sensor->name), "%s_gyro", 1708 name); 1709 break; 1710 default: 1711 return NULL; 1712 } 1713 iio_dev->name = sensor->name; 1714 1715 return iio_dev; 1716 } 1717 1718 static irqreturn_t st_lsm6dsx_handler_thread(int irq, void *private) 1719 { 1720 struct st_lsm6dsx_hw *hw = private; 1721 int count; 1722 1723 mutex_lock(&hw->fifo_lock); 1724 count = hw->settings->fifo_ops.read_fifo(hw); 1725 mutex_unlock(&hw->fifo_lock); 1726 1727 return count ? IRQ_HANDLED : IRQ_NONE; 1728 } 1729 1730 static int st_lsm6dsx_irq_setup(struct st_lsm6dsx_hw *hw) 1731 { 1732 struct st_sensors_platform_data *pdata; 1733 struct device_node *np = hw->dev->of_node; 1734 unsigned long irq_type; 1735 bool irq_active_low; 1736 int err; 1737 1738 irq_type = irqd_get_trigger_type(irq_get_irq_data(hw->irq)); 1739 1740 switch (irq_type) { 1741 case IRQF_TRIGGER_HIGH: 1742 case IRQF_TRIGGER_RISING: 1743 irq_active_low = false; 1744 break; 1745 case IRQF_TRIGGER_LOW: 1746 case IRQF_TRIGGER_FALLING: 1747 irq_active_low = true; 1748 break; 1749 default: 1750 dev_info(hw->dev, "mode %lx unsupported\n", irq_type); 1751 return -EINVAL; 1752 } 1753 1754 err = regmap_update_bits(hw->regmap, ST_LSM6DSX_REG_HLACTIVE_ADDR, 1755 ST_LSM6DSX_REG_HLACTIVE_MASK, 1756 FIELD_PREP(ST_LSM6DSX_REG_HLACTIVE_MASK, 1757 irq_active_low)); 1758 if (err < 0) 1759 return err; 1760 1761 pdata = (struct st_sensors_platform_data *)hw->dev->platform_data; 1762 if ((np && of_property_read_bool(np, "drive-open-drain")) || 1763 (pdata && pdata->open_drain)) { 1764 err = regmap_update_bits(hw->regmap, ST_LSM6DSX_REG_PP_OD_ADDR, 1765 ST_LSM6DSX_REG_PP_OD_MASK, 1766 FIELD_PREP(ST_LSM6DSX_REG_PP_OD_MASK, 1767 1)); 1768 if (err < 0) 1769 return err; 1770 1771 irq_type |= IRQF_SHARED; 1772 } 1773 1774 err = devm_request_threaded_irq(hw->dev, hw->irq, 1775 NULL, 1776 st_lsm6dsx_handler_thread, 1777 irq_type | IRQF_ONESHOT, 1778 "lsm6dsx", hw); 1779 if (err) { 1780 dev_err(hw->dev, "failed to request trigger irq %d\n", 1781 hw->irq); 1782 return err; 1783 } 1784 1785 return 0; 1786 } 1787 1788 int st_lsm6dsx_probe(struct device *dev, int irq, int hw_id, 1789 struct regmap *regmap) 1790 { 1791 const struct st_lsm6dsx_shub_settings *hub_settings; 1792 struct st_lsm6dsx_hw *hw; 1793 const char *name = NULL; 1794 int i, err; 1795 1796 hw = devm_kzalloc(dev, sizeof(*hw), GFP_KERNEL); 1797 if (!hw) 1798 return -ENOMEM; 1799 1800 dev_set_drvdata(dev, (void *)hw); 1801 1802 mutex_init(&hw->fifo_lock); 1803 mutex_init(&hw->conf_lock); 1804 mutex_init(&hw->page_lock); 1805 1806 hw->buff = devm_kzalloc(dev, ST_LSM6DSX_BUFF_SIZE, GFP_KERNEL); 1807 if (!hw->buff) 1808 return -ENOMEM; 1809 1810 hw->dev = dev; 1811 hw->irq = irq; 1812 hw->regmap = regmap; 1813 1814 err = st_lsm6dsx_check_whoami(hw, hw_id, &name); 1815 if (err < 0) 1816 return err; 1817 1818 for (i = 0; i < ST_LSM6DSX_ID_EXT0; i++) { 1819 hw->iio_devs[i] = st_lsm6dsx_alloc_iiodev(hw, i, name); 1820 if (!hw->iio_devs[i]) 1821 return -ENOMEM; 1822 } 1823 1824 err = st_lsm6dsx_init_device(hw); 1825 if (err < 0) 1826 return err; 1827 1828 hub_settings = &hw->settings->shub_settings; 1829 if (hub_settings->master_en.addr) { 1830 err = st_lsm6dsx_shub_probe(hw, name); 1831 if (err < 0) 1832 return err; 1833 } 1834 1835 if (hw->irq > 0) { 1836 err = st_lsm6dsx_irq_setup(hw); 1837 if (err < 0) 1838 return err; 1839 1840 err = st_lsm6dsx_fifo_setup(hw); 1841 if (err < 0) 1842 return err; 1843 } 1844 1845 for (i = 0; i < ST_LSM6DSX_ID_MAX; i++) { 1846 if (!hw->iio_devs[i]) 1847 continue; 1848 1849 err = devm_iio_device_register(hw->dev, hw->iio_devs[i]); 1850 if (err) 1851 return err; 1852 } 1853 1854 if (dev->of_node && of_property_read_bool(dev->of_node, "wakeup-source")) 1855 device_init_wakeup(dev, true); 1856 1857 return 0; 1858 } 1859 EXPORT_SYMBOL(st_lsm6dsx_probe); 1860 1861 static int __maybe_unused st_lsm6dsx_suspend(struct device *dev) 1862 { 1863 struct st_lsm6dsx_hw *hw = dev_get_drvdata(dev); 1864 struct st_lsm6dsx_sensor *sensor; 1865 int i, err = 0; 1866 1867 for (i = 0; i < ST_LSM6DSX_ID_MAX; i++) { 1868 if (!hw->iio_devs[i]) 1869 continue; 1870 1871 sensor = iio_priv(hw->iio_devs[i]); 1872 if (!(hw->enable_mask & BIT(sensor->id))) 1873 continue; 1874 1875 if (device_may_wakeup(dev) && 1876 sensor->id == ST_LSM6DSX_ID_ACC && hw->enable_event) { 1877 /* Enable wake from IRQ */ 1878 enable_irq_wake(hw->irq); 1879 continue; 1880 } 1881 1882 if (sensor->id == ST_LSM6DSX_ID_EXT0 || 1883 sensor->id == ST_LSM6DSX_ID_EXT1 || 1884 sensor->id == ST_LSM6DSX_ID_EXT2) 1885 err = st_lsm6dsx_shub_set_enable(sensor, false); 1886 else 1887 err = st_lsm6dsx_sensor_set_enable(sensor, false); 1888 if (err < 0) 1889 return err; 1890 1891 hw->suspend_mask |= BIT(sensor->id); 1892 } 1893 1894 if (hw->fifo_mode != ST_LSM6DSX_FIFO_BYPASS) 1895 err = st_lsm6dsx_flush_fifo(hw); 1896 1897 return err; 1898 } 1899 1900 static int __maybe_unused st_lsm6dsx_resume(struct device *dev) 1901 { 1902 struct st_lsm6dsx_hw *hw = dev_get_drvdata(dev); 1903 struct st_lsm6dsx_sensor *sensor; 1904 int i, err = 0; 1905 1906 for (i = 0; i < ST_LSM6DSX_ID_MAX; i++) { 1907 if (!hw->iio_devs[i]) 1908 continue; 1909 1910 sensor = iio_priv(hw->iio_devs[i]); 1911 if (device_may_wakeup(dev) && 1912 sensor->id == ST_LSM6DSX_ID_ACC && hw->enable_event) 1913 disable_irq_wake(hw->irq); 1914 1915 if (!(hw->suspend_mask & BIT(sensor->id))) 1916 continue; 1917 1918 if (sensor->id == ST_LSM6DSX_ID_EXT0 || 1919 sensor->id == ST_LSM6DSX_ID_EXT1 || 1920 sensor->id == ST_LSM6DSX_ID_EXT2) 1921 err = st_lsm6dsx_shub_set_enable(sensor, true); 1922 else 1923 err = st_lsm6dsx_sensor_set_enable(sensor, true); 1924 if (err < 0) 1925 return err; 1926 1927 hw->suspend_mask &= ~BIT(sensor->id); 1928 } 1929 1930 if (hw->enable_mask) 1931 err = st_lsm6dsx_set_fifo_mode(hw, ST_LSM6DSX_FIFO_CONT); 1932 1933 return err; 1934 } 1935 1936 const struct dev_pm_ops st_lsm6dsx_pm_ops = { 1937 SET_SYSTEM_SLEEP_PM_OPS(st_lsm6dsx_suspend, st_lsm6dsx_resume) 1938 }; 1939 EXPORT_SYMBOL(st_lsm6dsx_pm_ops); 1940 1941 MODULE_AUTHOR("Lorenzo Bianconi <lorenzo.bianconi@st.com>"); 1942 MODULE_AUTHOR("Denis Ciocca <denis.ciocca@st.com>"); 1943 MODULE_DESCRIPTION("STMicroelectronics st_lsm6dsx driver"); 1944 MODULE_LICENSE("GPL v2"); 1945