1 // SPDX-License-Identifier: GPL-2.0-only 2 /* 3 * STMicroelectronics st_lsm6dsx sensor driver 4 * 5 * The ST LSM6DSx IMU MEMS series consists of 3D digital accelerometer 6 * and 3D digital gyroscope system-in-package with a digital I2C/SPI serial 7 * interface standard output. 8 * LSM6DSx IMU MEMS series has a dynamic user-selectable full-scale 9 * acceleration range of +-2/+-4/+-8/+-16 g and an angular rate range of 10 * +-125/+-245/+-500/+-1000/+-2000 dps 11 * LSM6DSx series has an integrated First-In-First-Out (FIFO) buffer 12 * allowing dynamic batching of sensor data. 13 * LSM9DSx series is similar but includes an additional magnetometer, handled 14 * by a different driver. 15 * 16 * Supported sensors: 17 * - LSM6DS3: 18 * - Accelerometer/Gyroscope supported ODR [Hz]: 13, 26, 52, 104, 208, 416 19 * - Accelerometer supported full-scale [g]: +-2/+-4/+-8/+-16 20 * - Gyroscope supported full-scale [dps]: +-125/+-245/+-500/+-1000/+-2000 21 * - FIFO size: 8KB 22 * 23 * - LSM6DS3H/LSM6DSL/LSM6DSM/ISM330DLC/LSM6DS3TR-C: 24 * - Accelerometer/Gyroscope supported ODR [Hz]: 13, 26, 52, 104, 208, 416 25 * - Accelerometer supported full-scale [g]: +-2/+-4/+-8/+-16 26 * - Gyroscope supported full-scale [dps]: +-125/+-245/+-500/+-1000/+-2000 27 * - FIFO size: 4KB 28 * 29 * - LSM6DSO/LSM6DSOX/ASM330LHH/LSM6DSR/ISM330DHCX: 30 * - Accelerometer/Gyroscope supported ODR [Hz]: 13, 26, 52, 104, 208, 416 31 * - Accelerometer supported full-scale [g]: +-2/+-4/+-8/+-16 32 * - Gyroscope supported full-scale [dps]: +-125/+-245/+-500/+-1000/+-2000 33 * - FIFO size: 3KB 34 * 35 * - LSM9DS1: 36 * - Accelerometer supported ODR [Hz]: 10, 50, 119, 238, 476, 952 37 * - Accelerometer supported full-scale [g]: +-2/+-4/+-8/+-16 38 * - Gyroscope supported ODR [Hz]: 15, 60, 119, 238, 476, 952 39 * - Gyroscope supported full-scale [dps]: +-245/+-500/+-2000 40 * - FIFO size: 32 41 * 42 * Copyright 2016 STMicroelectronics Inc. 43 * 44 * Lorenzo Bianconi <lorenzo.bianconi@st.com> 45 * Denis Ciocca <denis.ciocca@st.com> 46 */ 47 48 #include <linux/kernel.h> 49 #include <linux/module.h> 50 #include <linux/delay.h> 51 #include <linux/iio/events.h> 52 #include <linux/iio/iio.h> 53 #include <linux/iio/sysfs.h> 54 #include <linux/interrupt.h> 55 #include <linux/irq.h> 56 #include <linux/pm.h> 57 #include <linux/regmap.h> 58 #include <linux/bitfield.h> 59 60 #include <linux/platform_data/st_sensors_pdata.h> 61 62 #include "st_lsm6dsx.h" 63 64 #define ST_LSM6DSX_REG_WHOAMI_ADDR 0x0f 65 66 static const struct iio_chan_spec st_lsm6dsx_acc_channels[] = { 67 ST_LSM6DSX_CHANNEL_ACC(IIO_ACCEL, 0x28, IIO_MOD_X, 0), 68 ST_LSM6DSX_CHANNEL_ACC(IIO_ACCEL, 0x2a, IIO_MOD_Y, 1), 69 ST_LSM6DSX_CHANNEL_ACC(IIO_ACCEL, 0x2c, IIO_MOD_Z, 2), 70 IIO_CHAN_SOFT_TIMESTAMP(3), 71 }; 72 73 static const struct iio_chan_spec st_lsm6dsx_gyro_channels[] = { 74 ST_LSM6DSX_CHANNEL(IIO_ANGL_VEL, 0x22, IIO_MOD_X, 0), 75 ST_LSM6DSX_CHANNEL(IIO_ANGL_VEL, 0x24, IIO_MOD_Y, 1), 76 ST_LSM6DSX_CHANNEL(IIO_ANGL_VEL, 0x26, IIO_MOD_Z, 2), 77 IIO_CHAN_SOFT_TIMESTAMP(3), 78 }; 79 80 static const struct iio_chan_spec st_lsm6ds0_gyro_channels[] = { 81 ST_LSM6DSX_CHANNEL(IIO_ANGL_VEL, 0x18, IIO_MOD_X, 0), 82 ST_LSM6DSX_CHANNEL(IIO_ANGL_VEL, 0x1a, IIO_MOD_Y, 1), 83 ST_LSM6DSX_CHANNEL(IIO_ANGL_VEL, 0x1c, IIO_MOD_Z, 2), 84 IIO_CHAN_SOFT_TIMESTAMP(3), 85 }; 86 87 static const struct st_lsm6dsx_settings st_lsm6dsx_sensor_settings[] = { 88 { 89 .wai = 0x68, 90 .reset = { 91 .addr = 0x22, 92 .mask = BIT(0), 93 }, 94 .boot = { 95 .addr = 0x22, 96 .mask = BIT(7), 97 }, 98 .bdu = { 99 .addr = 0x22, 100 .mask = BIT(6), 101 }, 102 .max_fifo_size = 32, 103 .id = { 104 { 105 .hw_id = ST_LSM9DS1_ID, 106 .name = ST_LSM9DS1_DEV_NAME, 107 }, 108 }, 109 .channels = { 110 [ST_LSM6DSX_ID_ACC] = { 111 .chan = st_lsm6dsx_acc_channels, 112 .len = ARRAY_SIZE(st_lsm6dsx_acc_channels), 113 }, 114 [ST_LSM6DSX_ID_GYRO] = { 115 .chan = st_lsm6ds0_gyro_channels, 116 .len = ARRAY_SIZE(st_lsm6ds0_gyro_channels), 117 }, 118 }, 119 .odr_table = { 120 [ST_LSM6DSX_ID_ACC] = { 121 .reg = { 122 .addr = 0x20, 123 .mask = GENMASK(7, 5), 124 }, 125 .odr_avl[0] = { 10, 0x01 }, 126 .odr_avl[1] = { 50, 0x02 }, 127 .odr_avl[2] = { 119, 0x03 }, 128 .odr_avl[3] = { 238, 0x04 }, 129 .odr_avl[4] = { 476, 0x05 }, 130 .odr_avl[5] = { 952, 0x06 }, 131 }, 132 [ST_LSM6DSX_ID_GYRO] = { 133 .reg = { 134 .addr = 0x10, 135 .mask = GENMASK(7, 5), 136 }, 137 .odr_avl[0] = { 15, 0x01 }, 138 .odr_avl[1] = { 60, 0x02 }, 139 .odr_avl[2] = { 119, 0x03 }, 140 .odr_avl[3] = { 238, 0x04 }, 141 .odr_avl[4] = { 476, 0x05 }, 142 .odr_avl[5] = { 952, 0x06 }, 143 }, 144 }, 145 .fs_table = { 146 [ST_LSM6DSX_ID_ACC] = { 147 .reg = { 148 .addr = 0x20, 149 .mask = GENMASK(4, 3), 150 }, 151 .fs_avl[0] = { IIO_G_TO_M_S_2(61), 0x0 }, 152 .fs_avl[1] = { IIO_G_TO_M_S_2(122), 0x2 }, 153 .fs_avl[2] = { IIO_G_TO_M_S_2(244), 0x3 }, 154 .fs_avl[3] = { IIO_G_TO_M_S_2(732), 0x1 }, 155 .fs_len = 4, 156 }, 157 [ST_LSM6DSX_ID_GYRO] = { 158 .reg = { 159 .addr = 0x10, 160 .mask = GENMASK(4, 3), 161 }, 162 .fs_avl[0] = { IIO_DEGREE_TO_RAD(245), 0x0 }, 163 .fs_avl[1] = { IIO_DEGREE_TO_RAD(500), 0x1 }, 164 .fs_avl[2] = { IIO_DEGREE_TO_RAD(2000), 0x3 }, 165 .fs_len = 3, 166 }, 167 }, 168 .irq_config = { 169 .irq1 = { 170 .addr = 0x0c, 171 .mask = BIT(3), 172 }, 173 .irq2 = { 174 .addr = 0x0d, 175 .mask = BIT(3), 176 }, 177 .hla = { 178 .addr = 0x22, 179 .mask = BIT(5), 180 }, 181 .od = { 182 .addr = 0x22, 183 .mask = BIT(4), 184 }, 185 }, 186 }, 187 { 188 .wai = 0x69, 189 .reset = { 190 .addr = 0x12, 191 .mask = BIT(0), 192 }, 193 .boot = { 194 .addr = 0x12, 195 .mask = BIT(7), 196 }, 197 .bdu = { 198 .addr = 0x12, 199 .mask = BIT(6), 200 }, 201 .max_fifo_size = 1365, 202 .id = { 203 { 204 .hw_id = ST_LSM6DS3_ID, 205 .name = ST_LSM6DS3_DEV_NAME, 206 }, 207 }, 208 .channels = { 209 [ST_LSM6DSX_ID_ACC] = { 210 .chan = st_lsm6dsx_acc_channels, 211 .len = ARRAY_SIZE(st_lsm6dsx_acc_channels), 212 }, 213 [ST_LSM6DSX_ID_GYRO] = { 214 .chan = st_lsm6dsx_gyro_channels, 215 .len = ARRAY_SIZE(st_lsm6dsx_gyro_channels), 216 }, 217 }, 218 .odr_table = { 219 [ST_LSM6DSX_ID_ACC] = { 220 .reg = { 221 .addr = 0x10, 222 .mask = GENMASK(7, 4), 223 }, 224 .odr_avl[0] = { 13, 0x01 }, 225 .odr_avl[1] = { 26, 0x02 }, 226 .odr_avl[2] = { 52, 0x03 }, 227 .odr_avl[3] = { 104, 0x04 }, 228 .odr_avl[4] = { 208, 0x05 }, 229 .odr_avl[5] = { 416, 0x06 }, 230 }, 231 [ST_LSM6DSX_ID_GYRO] = { 232 .reg = { 233 .addr = 0x11, 234 .mask = GENMASK(7, 4), 235 }, 236 .odr_avl[0] = { 13, 0x01 }, 237 .odr_avl[1] = { 26, 0x02 }, 238 .odr_avl[2] = { 52, 0x03 }, 239 .odr_avl[3] = { 104, 0x04 }, 240 .odr_avl[4] = { 208, 0x05 }, 241 .odr_avl[5] = { 416, 0x06 }, 242 }, 243 }, 244 .fs_table = { 245 [ST_LSM6DSX_ID_ACC] = { 246 .reg = { 247 .addr = 0x10, 248 .mask = GENMASK(3, 2), 249 }, 250 .fs_avl[0] = { IIO_G_TO_M_S_2(61), 0x0 }, 251 .fs_avl[1] = { IIO_G_TO_M_S_2(122), 0x2 }, 252 .fs_avl[2] = { IIO_G_TO_M_S_2(244), 0x3 }, 253 .fs_avl[3] = { IIO_G_TO_M_S_2(488), 0x1 }, 254 .fs_len = 4, 255 }, 256 [ST_LSM6DSX_ID_GYRO] = { 257 .reg = { 258 .addr = 0x11, 259 .mask = GENMASK(3, 2), 260 }, 261 .fs_avl[0] = { IIO_DEGREE_TO_RAD(8750), 0x0 }, 262 .fs_avl[1] = { IIO_DEGREE_TO_RAD(17500), 0x1 }, 263 .fs_avl[2] = { IIO_DEGREE_TO_RAD(35000), 0x2 }, 264 .fs_avl[3] = { IIO_DEGREE_TO_RAD(70000), 0x3 }, 265 .fs_len = 4, 266 }, 267 }, 268 .irq_config = { 269 .irq1 = { 270 .addr = 0x0d, 271 .mask = BIT(3), 272 }, 273 .irq2 = { 274 .addr = 0x0e, 275 .mask = BIT(3), 276 }, 277 .lir = { 278 .addr = 0x58, 279 .mask = BIT(0), 280 }, 281 .irq1_func = { 282 .addr = 0x5e, 283 .mask = BIT(5), 284 }, 285 .irq2_func = { 286 .addr = 0x5f, 287 .mask = BIT(5), 288 }, 289 .hla = { 290 .addr = 0x12, 291 .mask = BIT(5), 292 }, 293 .od = { 294 .addr = 0x12, 295 .mask = BIT(4), 296 }, 297 }, 298 .decimator = { 299 [ST_LSM6DSX_ID_ACC] = { 300 .addr = 0x08, 301 .mask = GENMASK(2, 0), 302 }, 303 [ST_LSM6DSX_ID_GYRO] = { 304 .addr = 0x08, 305 .mask = GENMASK(5, 3), 306 }, 307 }, 308 .fifo_ops = { 309 .update_fifo = st_lsm6dsx_update_fifo, 310 .read_fifo = st_lsm6dsx_read_fifo, 311 .fifo_th = { 312 .addr = 0x06, 313 .mask = GENMASK(11, 0), 314 }, 315 .fifo_diff = { 316 .addr = 0x3a, 317 .mask = GENMASK(11, 0), 318 }, 319 .th_wl = 3, /* 1LSB = 2B */ 320 }, 321 .ts_settings = { 322 .timer_en = { 323 .addr = 0x58, 324 .mask = BIT(7), 325 }, 326 .hr_timer = { 327 .addr = 0x5c, 328 .mask = BIT(4), 329 }, 330 .fifo_en = { 331 .addr = 0x07, 332 .mask = BIT(7), 333 }, 334 .decimator = { 335 .addr = 0x09, 336 .mask = GENMASK(5, 3), 337 }, 338 }, 339 .event_settings = { 340 .wakeup_reg = { 341 .addr = 0x5B, 342 .mask = GENMASK(5, 0), 343 }, 344 .wakeup_src_reg = 0x1b, 345 .wakeup_src_status_mask = BIT(3), 346 .wakeup_src_z_mask = BIT(0), 347 .wakeup_src_y_mask = BIT(1), 348 .wakeup_src_x_mask = BIT(2), 349 }, 350 }, 351 { 352 .wai = 0x69, 353 .reset = { 354 .addr = 0x12, 355 .mask = BIT(0), 356 }, 357 .boot = { 358 .addr = 0x12, 359 .mask = BIT(7), 360 }, 361 .bdu = { 362 .addr = 0x12, 363 .mask = BIT(6), 364 }, 365 .max_fifo_size = 682, 366 .id = { 367 { 368 .hw_id = ST_LSM6DS3H_ID, 369 .name = ST_LSM6DS3H_DEV_NAME, 370 }, 371 }, 372 .channels = { 373 [ST_LSM6DSX_ID_ACC] = { 374 .chan = st_lsm6dsx_acc_channels, 375 .len = ARRAY_SIZE(st_lsm6dsx_acc_channels), 376 }, 377 [ST_LSM6DSX_ID_GYRO] = { 378 .chan = st_lsm6dsx_gyro_channels, 379 .len = ARRAY_SIZE(st_lsm6dsx_gyro_channels), 380 }, 381 }, 382 .odr_table = { 383 [ST_LSM6DSX_ID_ACC] = { 384 .reg = { 385 .addr = 0x10, 386 .mask = GENMASK(7, 4), 387 }, 388 .odr_avl[0] = { 13, 0x01 }, 389 .odr_avl[1] = { 26, 0x02 }, 390 .odr_avl[2] = { 52, 0x03 }, 391 .odr_avl[3] = { 104, 0x04 }, 392 .odr_avl[4] = { 208, 0x05 }, 393 .odr_avl[5] = { 416, 0x06 }, 394 }, 395 [ST_LSM6DSX_ID_GYRO] = { 396 .reg = { 397 .addr = 0x11, 398 .mask = GENMASK(7, 4), 399 }, 400 .odr_avl[0] = { 13, 0x01 }, 401 .odr_avl[1] = { 26, 0x02 }, 402 .odr_avl[2] = { 52, 0x03 }, 403 .odr_avl[3] = { 104, 0x04 }, 404 .odr_avl[4] = { 208, 0x05 }, 405 .odr_avl[5] = { 416, 0x06 }, 406 }, 407 }, 408 .fs_table = { 409 [ST_LSM6DSX_ID_ACC] = { 410 .reg = { 411 .addr = 0x10, 412 .mask = GENMASK(3, 2), 413 }, 414 .fs_avl[0] = { IIO_G_TO_M_S_2(61), 0x0 }, 415 .fs_avl[1] = { IIO_G_TO_M_S_2(122), 0x2 }, 416 .fs_avl[2] = { IIO_G_TO_M_S_2(244), 0x3 }, 417 .fs_avl[3] = { IIO_G_TO_M_S_2(488), 0x1 }, 418 .fs_len = 4, 419 }, 420 [ST_LSM6DSX_ID_GYRO] = { 421 .reg = { 422 .addr = 0x11, 423 .mask = GENMASK(3, 2), 424 }, 425 .fs_avl[0] = { IIO_DEGREE_TO_RAD(8750), 0x0 }, 426 .fs_avl[1] = { IIO_DEGREE_TO_RAD(17500), 0x1 }, 427 .fs_avl[2] = { IIO_DEGREE_TO_RAD(35000), 0x2 }, 428 .fs_avl[3] = { IIO_DEGREE_TO_RAD(70000), 0x3 }, 429 .fs_len = 4, 430 }, 431 }, 432 .irq_config = { 433 .irq1 = { 434 .addr = 0x0d, 435 .mask = BIT(3), 436 }, 437 .irq2 = { 438 .addr = 0x0e, 439 .mask = BIT(3), 440 }, 441 .lir = { 442 .addr = 0x58, 443 .mask = BIT(0), 444 }, 445 .irq1_func = { 446 .addr = 0x5e, 447 .mask = BIT(5), 448 }, 449 .irq2_func = { 450 .addr = 0x5f, 451 .mask = BIT(5), 452 }, 453 .hla = { 454 .addr = 0x12, 455 .mask = BIT(5), 456 }, 457 .od = { 458 .addr = 0x12, 459 .mask = BIT(4), 460 }, 461 }, 462 .decimator = { 463 [ST_LSM6DSX_ID_ACC] = { 464 .addr = 0x08, 465 .mask = GENMASK(2, 0), 466 }, 467 [ST_LSM6DSX_ID_GYRO] = { 468 .addr = 0x08, 469 .mask = GENMASK(5, 3), 470 }, 471 }, 472 .fifo_ops = { 473 .update_fifo = st_lsm6dsx_update_fifo, 474 .read_fifo = st_lsm6dsx_read_fifo, 475 .fifo_th = { 476 .addr = 0x06, 477 .mask = GENMASK(11, 0), 478 }, 479 .fifo_diff = { 480 .addr = 0x3a, 481 .mask = GENMASK(11, 0), 482 }, 483 .th_wl = 3, /* 1LSB = 2B */ 484 }, 485 .ts_settings = { 486 .timer_en = { 487 .addr = 0x58, 488 .mask = BIT(7), 489 }, 490 .hr_timer = { 491 .addr = 0x5c, 492 .mask = BIT(4), 493 }, 494 .fifo_en = { 495 .addr = 0x07, 496 .mask = BIT(7), 497 }, 498 .decimator = { 499 .addr = 0x09, 500 .mask = GENMASK(5, 3), 501 }, 502 }, 503 .event_settings = { 504 .wakeup_reg = { 505 .addr = 0x5B, 506 .mask = GENMASK(5, 0), 507 }, 508 .wakeup_src_reg = 0x1b, 509 .wakeup_src_status_mask = BIT(3), 510 .wakeup_src_z_mask = BIT(0), 511 .wakeup_src_y_mask = BIT(1), 512 .wakeup_src_x_mask = BIT(2), 513 }, 514 }, 515 { 516 .wai = 0x6a, 517 .reset = { 518 .addr = 0x12, 519 .mask = BIT(0), 520 }, 521 .boot = { 522 .addr = 0x12, 523 .mask = BIT(7), 524 }, 525 .bdu = { 526 .addr = 0x12, 527 .mask = BIT(6), 528 }, 529 .max_fifo_size = 682, 530 .id = { 531 { 532 .hw_id = ST_LSM6DSL_ID, 533 .name = ST_LSM6DSL_DEV_NAME, 534 }, { 535 .hw_id = ST_LSM6DSM_ID, 536 .name = ST_LSM6DSM_DEV_NAME, 537 }, { 538 .hw_id = ST_ISM330DLC_ID, 539 .name = ST_ISM330DLC_DEV_NAME, 540 }, { 541 .hw_id = ST_LSM6DS3TRC_ID, 542 .name = ST_LSM6DS3TRC_DEV_NAME, 543 }, 544 }, 545 .channels = { 546 [ST_LSM6DSX_ID_ACC] = { 547 .chan = st_lsm6dsx_acc_channels, 548 .len = ARRAY_SIZE(st_lsm6dsx_acc_channels), 549 }, 550 [ST_LSM6DSX_ID_GYRO] = { 551 .chan = st_lsm6dsx_gyro_channels, 552 .len = ARRAY_SIZE(st_lsm6dsx_gyro_channels), 553 }, 554 }, 555 .odr_table = { 556 [ST_LSM6DSX_ID_ACC] = { 557 .reg = { 558 .addr = 0x10, 559 .mask = GENMASK(7, 4), 560 }, 561 .odr_avl[0] = { 13, 0x01 }, 562 .odr_avl[1] = { 26, 0x02 }, 563 .odr_avl[2] = { 52, 0x03 }, 564 .odr_avl[3] = { 104, 0x04 }, 565 .odr_avl[4] = { 208, 0x05 }, 566 .odr_avl[5] = { 416, 0x06 }, 567 }, 568 [ST_LSM6DSX_ID_GYRO] = { 569 .reg = { 570 .addr = 0x11, 571 .mask = GENMASK(7, 4), 572 }, 573 .odr_avl[0] = { 13, 0x01 }, 574 .odr_avl[1] = { 26, 0x02 }, 575 .odr_avl[2] = { 52, 0x03 }, 576 .odr_avl[3] = { 104, 0x04 }, 577 .odr_avl[4] = { 208, 0x05 }, 578 .odr_avl[5] = { 416, 0x06 }, 579 }, 580 }, 581 .fs_table = { 582 [ST_LSM6DSX_ID_ACC] = { 583 .reg = { 584 .addr = 0x10, 585 .mask = GENMASK(3, 2), 586 }, 587 .fs_avl[0] = { IIO_G_TO_M_S_2(61), 0x0 }, 588 .fs_avl[1] = { IIO_G_TO_M_S_2(122), 0x2 }, 589 .fs_avl[2] = { IIO_G_TO_M_S_2(244), 0x3 }, 590 .fs_avl[3] = { IIO_G_TO_M_S_2(488), 0x1 }, 591 .fs_len = 4, 592 }, 593 [ST_LSM6DSX_ID_GYRO] = { 594 .reg = { 595 .addr = 0x11, 596 .mask = GENMASK(3, 2), 597 }, 598 .fs_avl[0] = { IIO_DEGREE_TO_RAD(8750), 0x0 }, 599 .fs_avl[1] = { IIO_DEGREE_TO_RAD(17500), 0x1 }, 600 .fs_avl[2] = { IIO_DEGREE_TO_RAD(35000), 0x2 }, 601 .fs_avl[3] = { IIO_DEGREE_TO_RAD(70000), 0x3 }, 602 .fs_len = 4, 603 }, 604 }, 605 .irq_config = { 606 .irq1 = { 607 .addr = 0x0d, 608 .mask = BIT(3), 609 }, 610 .irq2 = { 611 .addr = 0x0e, 612 .mask = BIT(3), 613 }, 614 .lir = { 615 .addr = 0x58, 616 .mask = BIT(0), 617 }, 618 .irq1_func = { 619 .addr = 0x5e, 620 .mask = BIT(5), 621 }, 622 .irq2_func = { 623 .addr = 0x5f, 624 .mask = BIT(5), 625 }, 626 .hla = { 627 .addr = 0x12, 628 .mask = BIT(5), 629 }, 630 .od = { 631 .addr = 0x12, 632 .mask = BIT(4), 633 }, 634 }, 635 .decimator = { 636 [ST_LSM6DSX_ID_ACC] = { 637 .addr = 0x08, 638 .mask = GENMASK(2, 0), 639 }, 640 [ST_LSM6DSX_ID_GYRO] = { 641 .addr = 0x08, 642 .mask = GENMASK(5, 3), 643 }, 644 }, 645 .fifo_ops = { 646 .update_fifo = st_lsm6dsx_update_fifo, 647 .read_fifo = st_lsm6dsx_read_fifo, 648 .fifo_th = { 649 .addr = 0x06, 650 .mask = GENMASK(10, 0), 651 }, 652 .fifo_diff = { 653 .addr = 0x3a, 654 .mask = GENMASK(10, 0), 655 }, 656 .th_wl = 3, /* 1LSB = 2B */ 657 }, 658 .ts_settings = { 659 .timer_en = { 660 .addr = 0x19, 661 .mask = BIT(5), 662 }, 663 .hr_timer = { 664 .addr = 0x5c, 665 .mask = BIT(4), 666 }, 667 .fifo_en = { 668 .addr = 0x07, 669 .mask = BIT(7), 670 }, 671 .decimator = { 672 .addr = 0x09, 673 .mask = GENMASK(5, 3), 674 }, 675 }, 676 .event_settings = { 677 .enable_reg = { 678 .addr = 0x58, 679 .mask = BIT(7), 680 }, 681 .wakeup_reg = { 682 .addr = 0x5B, 683 .mask = GENMASK(5, 0), 684 }, 685 .wakeup_src_reg = 0x1b, 686 .wakeup_src_status_mask = BIT(3), 687 .wakeup_src_z_mask = BIT(0), 688 .wakeup_src_y_mask = BIT(1), 689 .wakeup_src_x_mask = BIT(2), 690 }, 691 }, 692 { 693 .wai = 0x6c, 694 .reset = { 695 .addr = 0x12, 696 .mask = BIT(0), 697 }, 698 .boot = { 699 .addr = 0x12, 700 .mask = BIT(7), 701 }, 702 .bdu = { 703 .addr = 0x12, 704 .mask = BIT(6), 705 }, 706 .max_fifo_size = 512, 707 .id = { 708 { 709 .hw_id = ST_LSM6DSO_ID, 710 .name = ST_LSM6DSO_DEV_NAME, 711 }, { 712 .hw_id = ST_LSM6DSOX_ID, 713 .name = ST_LSM6DSOX_DEV_NAME, 714 }, 715 }, 716 .channels = { 717 [ST_LSM6DSX_ID_ACC] = { 718 .chan = st_lsm6dsx_acc_channels, 719 .len = ARRAY_SIZE(st_lsm6dsx_acc_channels), 720 }, 721 [ST_LSM6DSX_ID_GYRO] = { 722 .chan = st_lsm6dsx_gyro_channels, 723 .len = ARRAY_SIZE(st_lsm6dsx_gyro_channels), 724 }, 725 }, 726 .drdy_mask = { 727 .addr = 0x13, 728 .mask = BIT(3), 729 }, 730 .odr_table = { 731 [ST_LSM6DSX_ID_ACC] = { 732 .reg = { 733 .addr = 0x10, 734 .mask = GENMASK(7, 4), 735 }, 736 .odr_avl[0] = { 13, 0x01 }, 737 .odr_avl[1] = { 26, 0x02 }, 738 .odr_avl[2] = { 52, 0x03 }, 739 .odr_avl[3] = { 104, 0x04 }, 740 .odr_avl[4] = { 208, 0x05 }, 741 .odr_avl[5] = { 416, 0x06 }, 742 }, 743 [ST_LSM6DSX_ID_GYRO] = { 744 .reg = { 745 .addr = 0x11, 746 .mask = GENMASK(7, 4), 747 }, 748 .odr_avl[0] = { 13, 0x01 }, 749 .odr_avl[1] = { 26, 0x02 }, 750 .odr_avl[2] = { 52, 0x03 }, 751 .odr_avl[3] = { 104, 0x04 }, 752 .odr_avl[4] = { 208, 0x05 }, 753 .odr_avl[5] = { 416, 0x06 }, 754 }, 755 }, 756 .fs_table = { 757 [ST_LSM6DSX_ID_ACC] = { 758 .reg = { 759 .addr = 0x10, 760 .mask = GENMASK(3, 2), 761 }, 762 .fs_avl[0] = { IIO_G_TO_M_S_2(61), 0x0 }, 763 .fs_avl[1] = { IIO_G_TO_M_S_2(122), 0x2 }, 764 .fs_avl[2] = { IIO_G_TO_M_S_2(244), 0x3 }, 765 .fs_avl[3] = { IIO_G_TO_M_S_2(488), 0x1 }, 766 .fs_len = 4, 767 }, 768 [ST_LSM6DSX_ID_GYRO] = { 769 .reg = { 770 .addr = 0x11, 771 .mask = GENMASK(3, 2), 772 }, 773 .fs_avl[0] = { IIO_DEGREE_TO_RAD(8750), 0x0 }, 774 .fs_avl[1] = { IIO_DEGREE_TO_RAD(17500), 0x1 }, 775 .fs_avl[2] = { IIO_DEGREE_TO_RAD(35000), 0x2 }, 776 .fs_avl[3] = { IIO_DEGREE_TO_RAD(70000), 0x3 }, 777 .fs_len = 4, 778 }, 779 }, 780 .irq_config = { 781 .irq1 = { 782 .addr = 0x0d, 783 .mask = BIT(3), 784 }, 785 .irq2 = { 786 .addr = 0x0e, 787 .mask = BIT(3), 788 }, 789 .lir = { 790 .addr = 0x56, 791 .mask = BIT(0), 792 }, 793 .clear_on_read = { 794 .addr = 0x56, 795 .mask = BIT(6), 796 }, 797 .irq1_func = { 798 .addr = 0x5e, 799 .mask = BIT(5), 800 }, 801 .irq2_func = { 802 .addr = 0x5f, 803 .mask = BIT(5), 804 }, 805 .hla = { 806 .addr = 0x12, 807 .mask = BIT(5), 808 }, 809 .od = { 810 .addr = 0x12, 811 .mask = BIT(4), 812 }, 813 }, 814 .batch = { 815 [ST_LSM6DSX_ID_ACC] = { 816 .addr = 0x09, 817 .mask = GENMASK(3, 0), 818 }, 819 [ST_LSM6DSX_ID_GYRO] = { 820 .addr = 0x09, 821 .mask = GENMASK(7, 4), 822 }, 823 }, 824 .fifo_ops = { 825 .update_fifo = st_lsm6dsx_update_fifo, 826 .read_fifo = st_lsm6dsx_read_tagged_fifo, 827 .fifo_th = { 828 .addr = 0x07, 829 .mask = GENMASK(8, 0), 830 }, 831 .fifo_diff = { 832 .addr = 0x3a, 833 .mask = GENMASK(9, 0), 834 }, 835 .th_wl = 1, 836 }, 837 .ts_settings = { 838 .timer_en = { 839 .addr = 0x19, 840 .mask = BIT(5), 841 }, 842 .decimator = { 843 .addr = 0x0a, 844 .mask = GENMASK(7, 6), 845 }, 846 }, 847 .shub_settings = { 848 .page_mux = { 849 .addr = 0x01, 850 .mask = BIT(6), 851 }, 852 .master_en = { 853 .addr = 0x14, 854 .mask = BIT(2), 855 }, 856 .pullup_en = { 857 .addr = 0x14, 858 .mask = BIT(3), 859 }, 860 .aux_sens = { 861 .addr = 0x14, 862 .mask = GENMASK(1, 0), 863 }, 864 .wr_once = { 865 .addr = 0x14, 866 .mask = BIT(6), 867 }, 868 .shub_out = 0x02, 869 .slv0_addr = 0x15, 870 .dw_slv0_addr = 0x21, 871 .batch_en = BIT(3), 872 }, 873 .event_settings = { 874 .enable_reg = { 875 .addr = 0x58, 876 .mask = BIT(7), 877 }, 878 .wakeup_reg = { 879 .addr = 0x5b, 880 .mask = GENMASK(5, 0), 881 }, 882 .wakeup_src_reg = 0x1b, 883 .wakeup_src_status_mask = BIT(3), 884 .wakeup_src_z_mask = BIT(0), 885 .wakeup_src_y_mask = BIT(1), 886 .wakeup_src_x_mask = BIT(2), 887 }, 888 }, 889 { 890 .wai = 0x6b, 891 .reset = { 892 .addr = 0x12, 893 .mask = BIT(0), 894 }, 895 .boot = { 896 .addr = 0x12, 897 .mask = BIT(7), 898 }, 899 .bdu = { 900 .addr = 0x12, 901 .mask = BIT(6), 902 }, 903 .max_fifo_size = 512, 904 .id = { 905 { 906 .hw_id = ST_ASM330LHH_ID, 907 .name = ST_ASM330LHH_DEV_NAME, 908 }, 909 }, 910 .channels = { 911 [ST_LSM6DSX_ID_ACC] = { 912 .chan = st_lsm6dsx_acc_channels, 913 .len = ARRAY_SIZE(st_lsm6dsx_acc_channels), 914 }, 915 [ST_LSM6DSX_ID_GYRO] = { 916 .chan = st_lsm6dsx_gyro_channels, 917 .len = ARRAY_SIZE(st_lsm6dsx_gyro_channels), 918 }, 919 }, 920 .drdy_mask = { 921 .addr = 0x13, 922 .mask = BIT(3), 923 }, 924 .odr_table = { 925 [ST_LSM6DSX_ID_ACC] = { 926 .reg = { 927 .addr = 0x10, 928 .mask = GENMASK(7, 4), 929 }, 930 .odr_avl[0] = { 13, 0x01 }, 931 .odr_avl[1] = { 26, 0x02 }, 932 .odr_avl[2] = { 52, 0x03 }, 933 .odr_avl[3] = { 104, 0x04 }, 934 .odr_avl[4] = { 208, 0x05 }, 935 .odr_avl[5] = { 416, 0x06 }, 936 }, 937 [ST_LSM6DSX_ID_GYRO] = { 938 .reg = { 939 .addr = 0x11, 940 .mask = GENMASK(7, 4), 941 }, 942 .odr_avl[0] = { 13, 0x01 }, 943 .odr_avl[1] = { 26, 0x02 }, 944 .odr_avl[2] = { 52, 0x03 }, 945 .odr_avl[3] = { 104, 0x04 }, 946 .odr_avl[4] = { 208, 0x05 }, 947 .odr_avl[5] = { 416, 0x06 }, 948 }, 949 }, 950 .fs_table = { 951 [ST_LSM6DSX_ID_ACC] = { 952 .reg = { 953 .addr = 0x10, 954 .mask = GENMASK(3, 2), 955 }, 956 .fs_avl[0] = { IIO_G_TO_M_S_2(61), 0x0 }, 957 .fs_avl[1] = { IIO_G_TO_M_S_2(122), 0x2 }, 958 .fs_avl[2] = { IIO_G_TO_M_S_2(244), 0x3 }, 959 .fs_avl[3] = { IIO_G_TO_M_S_2(488), 0x1 }, 960 .fs_len = 4, 961 }, 962 [ST_LSM6DSX_ID_GYRO] = { 963 .reg = { 964 .addr = 0x11, 965 .mask = GENMASK(3, 2), 966 }, 967 .fs_avl[0] = { IIO_DEGREE_TO_RAD(8750), 0x0 }, 968 .fs_avl[1] = { IIO_DEGREE_TO_RAD(17500), 0x1 }, 969 .fs_avl[2] = { IIO_DEGREE_TO_RAD(35000), 0x2 }, 970 .fs_avl[3] = { IIO_DEGREE_TO_RAD(70000), 0x3 }, 971 .fs_len = 4, 972 }, 973 }, 974 .irq_config = { 975 .irq1 = { 976 .addr = 0x0d, 977 .mask = BIT(3), 978 }, 979 .irq2 = { 980 .addr = 0x0e, 981 .mask = BIT(3), 982 }, 983 .lir = { 984 .addr = 0x56, 985 .mask = BIT(0), 986 }, 987 .clear_on_read = { 988 .addr = 0x56, 989 .mask = BIT(6), 990 }, 991 .irq1_func = { 992 .addr = 0x5e, 993 .mask = BIT(5), 994 }, 995 .irq2_func = { 996 .addr = 0x5f, 997 .mask = BIT(5), 998 }, 999 .hla = { 1000 .addr = 0x12, 1001 .mask = BIT(5), 1002 }, 1003 .od = { 1004 .addr = 0x12, 1005 .mask = BIT(4), 1006 }, 1007 }, 1008 .batch = { 1009 [ST_LSM6DSX_ID_ACC] = { 1010 .addr = 0x09, 1011 .mask = GENMASK(3, 0), 1012 }, 1013 [ST_LSM6DSX_ID_GYRO] = { 1014 .addr = 0x09, 1015 .mask = GENMASK(7, 4), 1016 }, 1017 }, 1018 .fifo_ops = { 1019 .update_fifo = st_lsm6dsx_update_fifo, 1020 .read_fifo = st_lsm6dsx_read_tagged_fifo, 1021 .fifo_th = { 1022 .addr = 0x07, 1023 .mask = GENMASK(8, 0), 1024 }, 1025 .fifo_diff = { 1026 .addr = 0x3a, 1027 .mask = GENMASK(9, 0), 1028 }, 1029 .th_wl = 1, 1030 }, 1031 .ts_settings = { 1032 .timer_en = { 1033 .addr = 0x19, 1034 .mask = BIT(5), 1035 }, 1036 .decimator = { 1037 .addr = 0x0a, 1038 .mask = GENMASK(7, 6), 1039 }, 1040 }, 1041 .event_settings = { 1042 .enable_reg = { 1043 .addr = 0x58, 1044 .mask = BIT(7), 1045 }, 1046 .wakeup_reg = { 1047 .addr = 0x5B, 1048 .mask = GENMASK(5, 0), 1049 }, 1050 .wakeup_src_reg = 0x1b, 1051 .wakeup_src_status_mask = BIT(3), 1052 .wakeup_src_z_mask = BIT(0), 1053 .wakeup_src_y_mask = BIT(1), 1054 .wakeup_src_x_mask = BIT(2), 1055 }, 1056 }, 1057 { 1058 .wai = 0x6b, 1059 .reset = { 1060 .addr = 0x12, 1061 .mask = BIT(0), 1062 }, 1063 .boot = { 1064 .addr = 0x12, 1065 .mask = BIT(7), 1066 }, 1067 .bdu = { 1068 .addr = 0x12, 1069 .mask = BIT(6), 1070 }, 1071 .max_fifo_size = 512, 1072 .id = { 1073 { 1074 .hw_id = ST_LSM6DSR_ID, 1075 .name = ST_LSM6DSR_DEV_NAME, 1076 }, { 1077 .hw_id = ST_ISM330DHCX_ID, 1078 .name = ST_ISM330DHCX_DEV_NAME, 1079 }, 1080 }, 1081 .channels = { 1082 [ST_LSM6DSX_ID_ACC] = { 1083 .chan = st_lsm6dsx_acc_channels, 1084 .len = ARRAY_SIZE(st_lsm6dsx_acc_channels), 1085 }, 1086 [ST_LSM6DSX_ID_GYRO] = { 1087 .chan = st_lsm6dsx_gyro_channels, 1088 .len = ARRAY_SIZE(st_lsm6dsx_gyro_channels), 1089 }, 1090 }, 1091 .drdy_mask = { 1092 .addr = 0x13, 1093 .mask = BIT(3), 1094 }, 1095 .odr_table = { 1096 [ST_LSM6DSX_ID_ACC] = { 1097 .reg = { 1098 .addr = 0x10, 1099 .mask = GENMASK(7, 4), 1100 }, 1101 .odr_avl[0] = { 13, 0x01 }, 1102 .odr_avl[1] = { 26, 0x02 }, 1103 .odr_avl[2] = { 52, 0x03 }, 1104 .odr_avl[3] = { 104, 0x04 }, 1105 .odr_avl[4] = { 208, 0x05 }, 1106 .odr_avl[5] = { 416, 0x06 }, 1107 }, 1108 [ST_LSM6DSX_ID_GYRO] = { 1109 .reg = { 1110 .addr = 0x11, 1111 .mask = GENMASK(7, 4), 1112 }, 1113 .odr_avl[0] = { 13, 0x01 }, 1114 .odr_avl[1] = { 26, 0x02 }, 1115 .odr_avl[2] = { 52, 0x03 }, 1116 .odr_avl[3] = { 104, 0x04 }, 1117 .odr_avl[4] = { 208, 0x05 }, 1118 .odr_avl[5] = { 416, 0x06 }, 1119 }, 1120 }, 1121 .fs_table = { 1122 [ST_LSM6DSX_ID_ACC] = { 1123 .reg = { 1124 .addr = 0x10, 1125 .mask = GENMASK(3, 2), 1126 }, 1127 .fs_avl[0] = { IIO_G_TO_M_S_2(61), 0x0 }, 1128 .fs_avl[1] = { IIO_G_TO_M_S_2(122), 0x2 }, 1129 .fs_avl[2] = { IIO_G_TO_M_S_2(244), 0x3 }, 1130 .fs_avl[3] = { IIO_G_TO_M_S_2(488), 0x1 }, 1131 .fs_len = 4, 1132 }, 1133 [ST_LSM6DSX_ID_GYRO] = { 1134 .reg = { 1135 .addr = 0x11, 1136 .mask = GENMASK(3, 2), 1137 }, 1138 .fs_avl[0] = { IIO_DEGREE_TO_RAD(8750), 0x0 }, 1139 .fs_avl[1] = { IIO_DEGREE_TO_RAD(17500), 0x1 }, 1140 .fs_avl[2] = { IIO_DEGREE_TO_RAD(35000), 0x2 }, 1141 .fs_avl[3] = { IIO_DEGREE_TO_RAD(70000), 0x3 }, 1142 .fs_len = 4, 1143 }, 1144 }, 1145 .irq_config = { 1146 .irq1 = { 1147 .addr = 0x0d, 1148 .mask = BIT(3), 1149 }, 1150 .irq2 = { 1151 .addr = 0x0e, 1152 .mask = BIT(3), 1153 }, 1154 .lir = { 1155 .addr = 0x56, 1156 .mask = BIT(0), 1157 }, 1158 .clear_on_read = { 1159 .addr = 0x56, 1160 .mask = BIT(6), 1161 }, 1162 .irq1_func = { 1163 .addr = 0x5e, 1164 .mask = BIT(5), 1165 }, 1166 .irq2_func = { 1167 .addr = 0x5f, 1168 .mask = BIT(5), 1169 }, 1170 .hla = { 1171 .addr = 0x12, 1172 .mask = BIT(5), 1173 }, 1174 .od = { 1175 .addr = 0x12, 1176 .mask = BIT(4), 1177 }, 1178 }, 1179 .batch = { 1180 [ST_LSM6DSX_ID_ACC] = { 1181 .addr = 0x09, 1182 .mask = GENMASK(3, 0), 1183 }, 1184 [ST_LSM6DSX_ID_GYRO] = { 1185 .addr = 0x09, 1186 .mask = GENMASK(7, 4), 1187 }, 1188 }, 1189 .fifo_ops = { 1190 .update_fifo = st_lsm6dsx_update_fifo, 1191 .read_fifo = st_lsm6dsx_read_tagged_fifo, 1192 .fifo_th = { 1193 .addr = 0x07, 1194 .mask = GENMASK(8, 0), 1195 }, 1196 .fifo_diff = { 1197 .addr = 0x3a, 1198 .mask = GENMASK(9, 0), 1199 }, 1200 .th_wl = 1, 1201 }, 1202 .ts_settings = { 1203 .timer_en = { 1204 .addr = 0x19, 1205 .mask = BIT(5), 1206 }, 1207 .decimator = { 1208 .addr = 0x0a, 1209 .mask = GENMASK(7, 6), 1210 }, 1211 }, 1212 .shub_settings = { 1213 .page_mux = { 1214 .addr = 0x01, 1215 .mask = BIT(6), 1216 }, 1217 .master_en = { 1218 .addr = 0x14, 1219 .mask = BIT(2), 1220 }, 1221 .pullup_en = { 1222 .addr = 0x14, 1223 .mask = BIT(3), 1224 }, 1225 .aux_sens = { 1226 .addr = 0x14, 1227 .mask = GENMASK(1, 0), 1228 }, 1229 .wr_once = { 1230 .addr = 0x14, 1231 .mask = BIT(6), 1232 }, 1233 .shub_out = 0x02, 1234 .slv0_addr = 0x15, 1235 .dw_slv0_addr = 0x21, 1236 .batch_en = BIT(3), 1237 }, 1238 .event_settings = { 1239 .enable_reg = { 1240 .addr = 0x58, 1241 .mask = BIT(7), 1242 }, 1243 .wakeup_reg = { 1244 .addr = 0x5B, 1245 .mask = GENMASK(5, 0), 1246 }, 1247 .wakeup_src_reg = 0x1b, 1248 .wakeup_src_status_mask = BIT(3), 1249 .wakeup_src_z_mask = BIT(0), 1250 .wakeup_src_y_mask = BIT(1), 1251 .wakeup_src_x_mask = BIT(2), 1252 } 1253 }, 1254 }; 1255 1256 int st_lsm6dsx_set_page(struct st_lsm6dsx_hw *hw, bool enable) 1257 { 1258 const struct st_lsm6dsx_shub_settings *hub_settings; 1259 unsigned int data; 1260 int err; 1261 1262 hub_settings = &hw->settings->shub_settings; 1263 data = ST_LSM6DSX_SHIFT_VAL(enable, hub_settings->page_mux.mask); 1264 err = regmap_update_bits(hw->regmap, hub_settings->page_mux.addr, 1265 hub_settings->page_mux.mask, data); 1266 usleep_range(100, 150); 1267 1268 return err; 1269 } 1270 1271 static int st_lsm6dsx_check_whoami(struct st_lsm6dsx_hw *hw, int id, 1272 const char **name) 1273 { 1274 int err, i, j, data; 1275 1276 for (i = 0; i < ARRAY_SIZE(st_lsm6dsx_sensor_settings); i++) { 1277 for (j = 0; j < ST_LSM6DSX_MAX_ID; j++) { 1278 if (id == st_lsm6dsx_sensor_settings[i].id[j].hw_id) 1279 break; 1280 } 1281 if (j < ST_LSM6DSX_MAX_ID) 1282 break; 1283 } 1284 1285 if (i == ARRAY_SIZE(st_lsm6dsx_sensor_settings)) { 1286 dev_err(hw->dev, "unsupported hw id [%02x]\n", id); 1287 return -ENODEV; 1288 } 1289 1290 err = regmap_read(hw->regmap, ST_LSM6DSX_REG_WHOAMI_ADDR, &data); 1291 if (err < 0) { 1292 dev_err(hw->dev, "failed to read whoami register\n"); 1293 return err; 1294 } 1295 1296 if (data != st_lsm6dsx_sensor_settings[i].wai) { 1297 dev_err(hw->dev, "unsupported whoami [%02x]\n", data); 1298 return -ENODEV; 1299 } 1300 1301 *name = st_lsm6dsx_sensor_settings[i].id[j].name; 1302 hw->settings = &st_lsm6dsx_sensor_settings[i]; 1303 1304 return 0; 1305 } 1306 1307 static int st_lsm6dsx_set_full_scale(struct st_lsm6dsx_sensor *sensor, 1308 u32 gain) 1309 { 1310 const struct st_lsm6dsx_fs_table_entry *fs_table; 1311 unsigned int data; 1312 int i, err; 1313 1314 fs_table = &sensor->hw->settings->fs_table[sensor->id]; 1315 for (i = 0; i < fs_table->fs_len; i++) { 1316 if (fs_table->fs_avl[i].gain == gain) 1317 break; 1318 } 1319 1320 if (i == fs_table->fs_len) 1321 return -EINVAL; 1322 1323 data = ST_LSM6DSX_SHIFT_VAL(fs_table->fs_avl[i].val, 1324 fs_table->reg.mask); 1325 err = st_lsm6dsx_update_bits_locked(sensor->hw, fs_table->reg.addr, 1326 fs_table->reg.mask, data); 1327 if (err < 0) 1328 return err; 1329 1330 sensor->gain = gain; 1331 1332 return 0; 1333 } 1334 1335 int st_lsm6dsx_check_odr(struct st_lsm6dsx_sensor *sensor, u16 odr, u8 *val) 1336 { 1337 const struct st_lsm6dsx_odr_table_entry *odr_table; 1338 int i; 1339 1340 odr_table = &sensor->hw->settings->odr_table[sensor->id]; 1341 for (i = 0; i < ST_LSM6DSX_ODR_LIST_SIZE; i++) 1342 /* 1343 * ext devices can run at different odr respect to 1344 * accel sensor 1345 */ 1346 if (odr_table->odr_avl[i].hz >= odr) 1347 break; 1348 1349 if (i == ST_LSM6DSX_ODR_LIST_SIZE) 1350 return -EINVAL; 1351 1352 *val = odr_table->odr_avl[i].val; 1353 1354 return 0; 1355 } 1356 1357 static u16 st_lsm6dsx_check_odr_dependency(struct st_lsm6dsx_hw *hw, u16 odr, 1358 enum st_lsm6dsx_sensor_id id) 1359 { 1360 struct st_lsm6dsx_sensor *ref = iio_priv(hw->iio_devs[id]); 1361 1362 if (odr > 0) { 1363 if (hw->enable_mask & BIT(id)) 1364 return max_t(u16, ref->odr, odr); 1365 else 1366 return odr; 1367 } else { 1368 return (hw->enable_mask & BIT(id)) ? ref->odr : 0; 1369 } 1370 } 1371 1372 static int st_lsm6dsx_set_odr(struct st_lsm6dsx_sensor *sensor, u16 req_odr) 1373 { 1374 struct st_lsm6dsx_sensor *ref_sensor = sensor; 1375 struct st_lsm6dsx_hw *hw = sensor->hw; 1376 const struct st_lsm6dsx_reg *reg; 1377 unsigned int data; 1378 u8 val = 0; 1379 int err; 1380 1381 switch (sensor->id) { 1382 case ST_LSM6DSX_ID_EXT0: 1383 case ST_LSM6DSX_ID_EXT1: 1384 case ST_LSM6DSX_ID_EXT2: 1385 case ST_LSM6DSX_ID_ACC: { 1386 u16 odr; 1387 int i; 1388 1389 /* 1390 * i2c embedded controller relies on the accelerometer sensor as 1391 * bus read/write trigger so we need to enable accel device 1392 * at odr = max(accel_odr, ext_odr) in order to properly 1393 * communicate with i2c slave devices 1394 */ 1395 ref_sensor = iio_priv(hw->iio_devs[ST_LSM6DSX_ID_ACC]); 1396 for (i = ST_LSM6DSX_ID_ACC; i < ST_LSM6DSX_ID_MAX; i++) { 1397 if (!hw->iio_devs[i] || i == sensor->id) 1398 continue; 1399 1400 odr = st_lsm6dsx_check_odr_dependency(hw, req_odr, i); 1401 if (odr != req_odr) 1402 /* device already configured */ 1403 return 0; 1404 } 1405 break; 1406 } 1407 default: 1408 break; 1409 } 1410 1411 if (req_odr > 0) { 1412 err = st_lsm6dsx_check_odr(ref_sensor, req_odr, &val); 1413 if (err < 0) 1414 return err; 1415 } 1416 1417 reg = &hw->settings->odr_table[ref_sensor->id].reg; 1418 data = ST_LSM6DSX_SHIFT_VAL(val, reg->mask); 1419 return st_lsm6dsx_update_bits_locked(hw, reg->addr, reg->mask, data); 1420 } 1421 1422 int st_lsm6dsx_sensor_set_enable(struct st_lsm6dsx_sensor *sensor, 1423 bool enable) 1424 { 1425 struct st_lsm6dsx_hw *hw = sensor->hw; 1426 u16 odr = enable ? sensor->odr : 0; 1427 int err; 1428 1429 err = st_lsm6dsx_set_odr(sensor, odr); 1430 if (err < 0) 1431 return err; 1432 1433 if (enable) 1434 hw->enable_mask |= BIT(sensor->id); 1435 else 1436 hw->enable_mask &= ~BIT(sensor->id); 1437 1438 return 0; 1439 } 1440 1441 static int st_lsm6dsx_read_oneshot(struct st_lsm6dsx_sensor *sensor, 1442 u8 addr, int *val) 1443 { 1444 struct st_lsm6dsx_hw *hw = sensor->hw; 1445 int err, delay; 1446 __le16 data; 1447 1448 err = st_lsm6dsx_sensor_set_enable(sensor, true); 1449 if (err < 0) 1450 return err; 1451 1452 delay = 1000000 / sensor->odr; 1453 usleep_range(delay, 2 * delay); 1454 1455 err = st_lsm6dsx_read_locked(hw, addr, &data, sizeof(data)); 1456 if (err < 0) 1457 return err; 1458 1459 if (!hw->enable_event) 1460 st_lsm6dsx_sensor_set_enable(sensor, false); 1461 1462 *val = (s16)le16_to_cpu(data); 1463 1464 return IIO_VAL_INT; 1465 } 1466 1467 static int st_lsm6dsx_read_raw(struct iio_dev *iio_dev, 1468 struct iio_chan_spec const *ch, 1469 int *val, int *val2, long mask) 1470 { 1471 struct st_lsm6dsx_sensor *sensor = iio_priv(iio_dev); 1472 int ret; 1473 1474 switch (mask) { 1475 case IIO_CHAN_INFO_RAW: 1476 ret = iio_device_claim_direct_mode(iio_dev); 1477 if (ret) 1478 break; 1479 1480 ret = st_lsm6dsx_read_oneshot(sensor, ch->address, val); 1481 iio_device_release_direct_mode(iio_dev); 1482 break; 1483 case IIO_CHAN_INFO_SAMP_FREQ: 1484 *val = sensor->odr; 1485 ret = IIO_VAL_INT; 1486 break; 1487 case IIO_CHAN_INFO_SCALE: 1488 *val = 0; 1489 *val2 = sensor->gain; 1490 ret = IIO_VAL_INT_PLUS_MICRO; 1491 break; 1492 default: 1493 ret = -EINVAL; 1494 break; 1495 } 1496 1497 return ret; 1498 } 1499 1500 static int st_lsm6dsx_write_raw(struct iio_dev *iio_dev, 1501 struct iio_chan_spec const *chan, 1502 int val, int val2, long mask) 1503 { 1504 struct st_lsm6dsx_sensor *sensor = iio_priv(iio_dev); 1505 int err; 1506 1507 err = iio_device_claim_direct_mode(iio_dev); 1508 if (err) 1509 return err; 1510 1511 switch (mask) { 1512 case IIO_CHAN_INFO_SCALE: 1513 err = st_lsm6dsx_set_full_scale(sensor, val2); 1514 break; 1515 case IIO_CHAN_INFO_SAMP_FREQ: { 1516 u8 data; 1517 1518 err = st_lsm6dsx_check_odr(sensor, val, &data); 1519 if (!err) 1520 sensor->odr = val; 1521 break; 1522 } 1523 default: 1524 err = -EINVAL; 1525 break; 1526 } 1527 1528 iio_device_release_direct_mode(iio_dev); 1529 1530 return err; 1531 } 1532 1533 static int st_lsm6dsx_event_setup(struct st_lsm6dsx_hw *hw, int state) 1534 { 1535 const struct st_lsm6dsx_reg *reg; 1536 unsigned int data; 1537 int err; 1538 1539 if (!hw->settings->irq_config.irq1_func.addr) 1540 return -ENOTSUPP; 1541 1542 reg = &hw->settings->event_settings.enable_reg; 1543 if (reg->addr) { 1544 data = ST_LSM6DSX_SHIFT_VAL(state, reg->mask); 1545 err = st_lsm6dsx_update_bits_locked(hw, reg->addr, 1546 reg->mask, data); 1547 if (err < 0) 1548 return err; 1549 } 1550 1551 /* Enable wakeup interrupt */ 1552 data = ST_LSM6DSX_SHIFT_VAL(state, hw->irq_routing->mask); 1553 return st_lsm6dsx_update_bits_locked(hw, hw->irq_routing->addr, 1554 hw->irq_routing->mask, data); 1555 } 1556 1557 static int st_lsm6dsx_read_event(struct iio_dev *iio_dev, 1558 const struct iio_chan_spec *chan, 1559 enum iio_event_type type, 1560 enum iio_event_direction dir, 1561 enum iio_event_info info, 1562 int *val, int *val2) 1563 { 1564 struct st_lsm6dsx_sensor *sensor = iio_priv(iio_dev); 1565 struct st_lsm6dsx_hw *hw = sensor->hw; 1566 1567 if (type != IIO_EV_TYPE_THRESH) 1568 return -EINVAL; 1569 1570 *val2 = 0; 1571 *val = hw->event_threshold; 1572 1573 return IIO_VAL_INT; 1574 } 1575 1576 static int 1577 st_lsm6dsx_write_event(struct iio_dev *iio_dev, 1578 const struct iio_chan_spec *chan, 1579 enum iio_event_type type, 1580 enum iio_event_direction dir, 1581 enum iio_event_info info, 1582 int val, int val2) 1583 { 1584 struct st_lsm6dsx_sensor *sensor = iio_priv(iio_dev); 1585 struct st_lsm6dsx_hw *hw = sensor->hw; 1586 const struct st_lsm6dsx_reg *reg; 1587 unsigned int data; 1588 int err; 1589 1590 if (type != IIO_EV_TYPE_THRESH) 1591 return -EINVAL; 1592 1593 if (val < 0 || val > 31) 1594 return -EINVAL; 1595 1596 reg = &hw->settings->event_settings.wakeup_reg; 1597 data = ST_LSM6DSX_SHIFT_VAL(val, reg->mask); 1598 err = st_lsm6dsx_update_bits_locked(hw, reg->addr, 1599 reg->mask, data); 1600 if (err < 0) 1601 return -EINVAL; 1602 1603 hw->event_threshold = val; 1604 1605 return 0; 1606 } 1607 1608 static int 1609 st_lsm6dsx_read_event_config(struct iio_dev *iio_dev, 1610 const struct iio_chan_spec *chan, 1611 enum iio_event_type type, 1612 enum iio_event_direction dir) 1613 { 1614 struct st_lsm6dsx_sensor *sensor = iio_priv(iio_dev); 1615 struct st_lsm6dsx_hw *hw = sensor->hw; 1616 1617 if (type != IIO_EV_TYPE_THRESH) 1618 return -EINVAL; 1619 1620 return !!(hw->enable_event & BIT(chan->channel2)); 1621 } 1622 1623 static int 1624 st_lsm6dsx_write_event_config(struct iio_dev *iio_dev, 1625 const struct iio_chan_spec *chan, 1626 enum iio_event_type type, 1627 enum iio_event_direction dir, int state) 1628 { 1629 struct st_lsm6dsx_sensor *sensor = iio_priv(iio_dev); 1630 struct st_lsm6dsx_hw *hw = sensor->hw; 1631 u8 enable_event; 1632 int err = 0; 1633 1634 if (type != IIO_EV_TYPE_THRESH) 1635 return -EINVAL; 1636 1637 if (state) { 1638 enable_event = hw->enable_event | BIT(chan->channel2); 1639 1640 /* do not enable events if they are already enabled */ 1641 if (hw->enable_event) 1642 goto out; 1643 } else { 1644 enable_event = hw->enable_event & ~BIT(chan->channel2); 1645 1646 /* only turn off sensor if no events is enabled */ 1647 if (enable_event) 1648 goto out; 1649 } 1650 1651 /* stop here if no changes have been made */ 1652 if (hw->enable_event == enable_event) 1653 return 0; 1654 1655 err = st_lsm6dsx_event_setup(hw, state); 1656 if (err < 0) 1657 return err; 1658 1659 mutex_lock(&hw->conf_lock); 1660 err = st_lsm6dsx_sensor_set_enable(sensor, state); 1661 mutex_unlock(&hw->conf_lock); 1662 if (err < 0) 1663 return err; 1664 1665 out: 1666 hw->enable_event = enable_event; 1667 1668 return 0; 1669 } 1670 1671 int st_lsm6dsx_set_watermark(struct iio_dev *iio_dev, unsigned int val) 1672 { 1673 struct st_lsm6dsx_sensor *sensor = iio_priv(iio_dev); 1674 struct st_lsm6dsx_hw *hw = sensor->hw; 1675 int err; 1676 1677 if (val < 1 || val > hw->settings->max_fifo_size) 1678 return -EINVAL; 1679 1680 mutex_lock(&hw->conf_lock); 1681 1682 err = st_lsm6dsx_update_watermark(sensor, val); 1683 1684 mutex_unlock(&hw->conf_lock); 1685 1686 if (err < 0) 1687 return err; 1688 1689 sensor->watermark = val; 1690 1691 return 0; 1692 } 1693 1694 static ssize_t 1695 st_lsm6dsx_sysfs_sampling_frequency_avail(struct device *dev, 1696 struct device_attribute *attr, 1697 char *buf) 1698 { 1699 struct st_lsm6dsx_sensor *sensor = iio_priv(dev_get_drvdata(dev)); 1700 enum st_lsm6dsx_sensor_id id = sensor->id; 1701 struct st_lsm6dsx_hw *hw = sensor->hw; 1702 int i, len = 0; 1703 1704 for (i = 0; i < ST_LSM6DSX_ODR_LIST_SIZE; i++) 1705 len += scnprintf(buf + len, PAGE_SIZE - len, "%d ", 1706 hw->settings->odr_table[id].odr_avl[i].hz); 1707 buf[len - 1] = '\n'; 1708 1709 return len; 1710 } 1711 1712 static ssize_t st_lsm6dsx_sysfs_scale_avail(struct device *dev, 1713 struct device_attribute *attr, 1714 char *buf) 1715 { 1716 struct st_lsm6dsx_sensor *sensor = iio_priv(dev_get_drvdata(dev)); 1717 const struct st_lsm6dsx_fs_table_entry *fs_table; 1718 struct st_lsm6dsx_hw *hw = sensor->hw; 1719 int i, len = 0; 1720 1721 fs_table = &hw->settings->fs_table[sensor->id]; 1722 for (i = 0; i < fs_table->fs_len; i++) 1723 len += scnprintf(buf + len, PAGE_SIZE - len, "0.%06u ", 1724 fs_table->fs_avl[i].gain); 1725 buf[len - 1] = '\n'; 1726 1727 return len; 1728 } 1729 1730 static IIO_DEV_ATTR_SAMP_FREQ_AVAIL(st_lsm6dsx_sysfs_sampling_frequency_avail); 1731 static IIO_DEVICE_ATTR(in_accel_scale_available, 0444, 1732 st_lsm6dsx_sysfs_scale_avail, NULL, 0); 1733 static IIO_DEVICE_ATTR(in_anglvel_scale_available, 0444, 1734 st_lsm6dsx_sysfs_scale_avail, NULL, 0); 1735 1736 static struct attribute *st_lsm6dsx_acc_attributes[] = { 1737 &iio_dev_attr_sampling_frequency_available.dev_attr.attr, 1738 &iio_dev_attr_in_accel_scale_available.dev_attr.attr, 1739 NULL, 1740 }; 1741 1742 static const struct attribute_group st_lsm6dsx_acc_attribute_group = { 1743 .attrs = st_lsm6dsx_acc_attributes, 1744 }; 1745 1746 static const struct iio_info st_lsm6dsx_acc_info = { 1747 .attrs = &st_lsm6dsx_acc_attribute_group, 1748 .read_raw = st_lsm6dsx_read_raw, 1749 .write_raw = st_lsm6dsx_write_raw, 1750 .read_event_value = st_lsm6dsx_read_event, 1751 .write_event_value = st_lsm6dsx_write_event, 1752 .read_event_config = st_lsm6dsx_read_event_config, 1753 .write_event_config = st_lsm6dsx_write_event_config, 1754 .hwfifo_set_watermark = st_lsm6dsx_set_watermark, 1755 }; 1756 1757 static struct attribute *st_lsm6dsx_gyro_attributes[] = { 1758 &iio_dev_attr_sampling_frequency_available.dev_attr.attr, 1759 &iio_dev_attr_in_anglvel_scale_available.dev_attr.attr, 1760 NULL, 1761 }; 1762 1763 static const struct attribute_group st_lsm6dsx_gyro_attribute_group = { 1764 .attrs = st_lsm6dsx_gyro_attributes, 1765 }; 1766 1767 static const struct iio_info st_lsm6dsx_gyro_info = { 1768 .attrs = &st_lsm6dsx_gyro_attribute_group, 1769 .read_raw = st_lsm6dsx_read_raw, 1770 .write_raw = st_lsm6dsx_write_raw, 1771 .hwfifo_set_watermark = st_lsm6dsx_set_watermark, 1772 }; 1773 1774 static int st_lsm6dsx_of_get_drdy_pin(struct st_lsm6dsx_hw *hw, int *drdy_pin) 1775 { 1776 struct device_node *np = hw->dev->of_node; 1777 1778 if (!np) 1779 return -EINVAL; 1780 1781 return of_property_read_u32(np, "st,drdy-int-pin", drdy_pin); 1782 } 1783 1784 static int 1785 st_lsm6dsx_get_drdy_reg(struct st_lsm6dsx_hw *hw, 1786 const struct st_lsm6dsx_reg **drdy_reg) 1787 { 1788 int err = 0, drdy_pin; 1789 1790 if (st_lsm6dsx_of_get_drdy_pin(hw, &drdy_pin) < 0) { 1791 struct st_sensors_platform_data *pdata; 1792 struct device *dev = hw->dev; 1793 1794 pdata = (struct st_sensors_platform_data *)dev->platform_data; 1795 drdy_pin = pdata ? pdata->drdy_int_pin : 1; 1796 } 1797 1798 switch (drdy_pin) { 1799 case 1: 1800 hw->irq_routing = &hw->settings->irq_config.irq1_func; 1801 *drdy_reg = &hw->settings->irq_config.irq1; 1802 break; 1803 case 2: 1804 hw->irq_routing = &hw->settings->irq_config.irq2_func; 1805 *drdy_reg = &hw->settings->irq_config.irq2; 1806 break; 1807 default: 1808 dev_err(hw->dev, "unsupported data ready pin\n"); 1809 err = -EINVAL; 1810 break; 1811 } 1812 1813 return err; 1814 } 1815 1816 static int st_lsm6dsx_init_shub(struct st_lsm6dsx_hw *hw) 1817 { 1818 const struct st_lsm6dsx_shub_settings *hub_settings; 1819 struct device_node *np = hw->dev->of_node; 1820 struct st_sensors_platform_data *pdata; 1821 unsigned int data; 1822 int err = 0; 1823 1824 hub_settings = &hw->settings->shub_settings; 1825 1826 pdata = (struct st_sensors_platform_data *)hw->dev->platform_data; 1827 if ((np && of_property_read_bool(np, "st,pullups")) || 1828 (pdata && pdata->pullups)) { 1829 err = st_lsm6dsx_set_page(hw, true); 1830 if (err < 0) 1831 return err; 1832 1833 data = ST_LSM6DSX_SHIFT_VAL(1, hub_settings->pullup_en.mask); 1834 err = regmap_update_bits(hw->regmap, 1835 hub_settings->pullup_en.addr, 1836 hub_settings->pullup_en.mask, data); 1837 1838 st_lsm6dsx_set_page(hw, false); 1839 1840 if (err < 0) 1841 return err; 1842 } 1843 1844 if (hub_settings->aux_sens.addr) { 1845 /* configure aux sensors */ 1846 err = st_lsm6dsx_set_page(hw, true); 1847 if (err < 0) 1848 return err; 1849 1850 data = ST_LSM6DSX_SHIFT_VAL(3, hub_settings->aux_sens.mask); 1851 err = regmap_update_bits(hw->regmap, 1852 hub_settings->aux_sens.addr, 1853 hub_settings->aux_sens.mask, data); 1854 1855 st_lsm6dsx_set_page(hw, false); 1856 } 1857 1858 return err; 1859 } 1860 1861 static int st_lsm6dsx_init_hw_timer(struct st_lsm6dsx_hw *hw) 1862 { 1863 const struct st_lsm6dsx_hw_ts_settings *ts_settings; 1864 int err, val; 1865 1866 ts_settings = &hw->settings->ts_settings; 1867 /* enable hw timestamp generation if necessary */ 1868 if (ts_settings->timer_en.addr) { 1869 val = ST_LSM6DSX_SHIFT_VAL(1, ts_settings->timer_en.mask); 1870 err = regmap_update_bits(hw->regmap, 1871 ts_settings->timer_en.addr, 1872 ts_settings->timer_en.mask, val); 1873 if (err < 0) 1874 return err; 1875 } 1876 1877 /* enable high resolution for hw ts timer if necessary */ 1878 if (ts_settings->hr_timer.addr) { 1879 val = ST_LSM6DSX_SHIFT_VAL(1, ts_settings->hr_timer.mask); 1880 err = regmap_update_bits(hw->regmap, 1881 ts_settings->hr_timer.addr, 1882 ts_settings->hr_timer.mask, val); 1883 if (err < 0) 1884 return err; 1885 } 1886 1887 /* enable ts queueing in FIFO if necessary */ 1888 if (ts_settings->fifo_en.addr) { 1889 val = ST_LSM6DSX_SHIFT_VAL(1, ts_settings->fifo_en.mask); 1890 err = regmap_update_bits(hw->regmap, 1891 ts_settings->fifo_en.addr, 1892 ts_settings->fifo_en.mask, val); 1893 if (err < 0) 1894 return err; 1895 } 1896 return 0; 1897 } 1898 1899 static int st_lsm6dsx_init_device(struct st_lsm6dsx_hw *hw) 1900 { 1901 const struct st_lsm6dsx_reg *reg; 1902 int err; 1903 1904 /* device sw reset */ 1905 reg = &hw->settings->reset; 1906 err = regmap_update_bits(hw->regmap, reg->addr, reg->mask, 1907 ST_LSM6DSX_SHIFT_VAL(1, reg->mask)); 1908 if (err < 0) 1909 return err; 1910 1911 msleep(50); 1912 1913 /* reload trimming parameter */ 1914 reg = &hw->settings->boot; 1915 err = regmap_update_bits(hw->regmap, reg->addr, reg->mask, 1916 ST_LSM6DSX_SHIFT_VAL(1, reg->mask)); 1917 if (err < 0) 1918 return err; 1919 1920 msleep(50); 1921 1922 /* enable Block Data Update */ 1923 reg = &hw->settings->bdu; 1924 err = regmap_update_bits(hw->regmap, reg->addr, reg->mask, 1925 ST_LSM6DSX_SHIFT_VAL(1, reg->mask)); 1926 if (err < 0) 1927 return err; 1928 1929 /* enable FIFO watermak interrupt */ 1930 err = st_lsm6dsx_get_drdy_reg(hw, ®); 1931 if (err < 0) 1932 return err; 1933 1934 err = regmap_update_bits(hw->regmap, reg->addr, reg->mask, 1935 ST_LSM6DSX_SHIFT_VAL(1, reg->mask)); 1936 if (err < 0) 1937 return err; 1938 1939 /* enable Latched interrupts for device events */ 1940 if (hw->settings->irq_config.lir.addr) { 1941 reg = &hw->settings->irq_config.lir; 1942 err = regmap_update_bits(hw->regmap, reg->addr, reg->mask, 1943 ST_LSM6DSX_SHIFT_VAL(1, reg->mask)); 1944 if (err < 0) 1945 return err; 1946 1947 /* enable clear on read for latched interrupts */ 1948 if (hw->settings->irq_config.clear_on_read.addr) { 1949 reg = &hw->settings->irq_config.clear_on_read; 1950 err = regmap_update_bits(hw->regmap, 1951 reg->addr, reg->mask, 1952 ST_LSM6DSX_SHIFT_VAL(1, reg->mask)); 1953 if (err < 0) 1954 return err; 1955 } 1956 } 1957 1958 /* enable drdy-mas if available */ 1959 if (hw->settings->drdy_mask.addr) { 1960 reg = &hw->settings->drdy_mask; 1961 err = regmap_update_bits(hw->regmap, reg->addr, reg->mask, 1962 ST_LSM6DSX_SHIFT_VAL(1, reg->mask)); 1963 if (err < 0) 1964 return err; 1965 } 1966 1967 err = st_lsm6dsx_init_shub(hw); 1968 if (err < 0) 1969 return err; 1970 1971 return st_lsm6dsx_init_hw_timer(hw); 1972 } 1973 1974 static struct iio_dev *st_lsm6dsx_alloc_iiodev(struct st_lsm6dsx_hw *hw, 1975 enum st_lsm6dsx_sensor_id id, 1976 const char *name) 1977 { 1978 struct st_lsm6dsx_sensor *sensor; 1979 struct iio_dev *iio_dev; 1980 1981 iio_dev = devm_iio_device_alloc(hw->dev, sizeof(*sensor)); 1982 if (!iio_dev) 1983 return NULL; 1984 1985 iio_dev->modes = INDIO_DIRECT_MODE; 1986 iio_dev->dev.parent = hw->dev; 1987 iio_dev->available_scan_masks = st_lsm6dsx_available_scan_masks; 1988 iio_dev->channels = hw->settings->channels[id].chan; 1989 iio_dev->num_channels = hw->settings->channels[id].len; 1990 1991 sensor = iio_priv(iio_dev); 1992 sensor->id = id; 1993 sensor->hw = hw; 1994 sensor->odr = hw->settings->odr_table[id].odr_avl[0].hz; 1995 sensor->gain = hw->settings->fs_table[id].fs_avl[0].gain; 1996 sensor->watermark = 1; 1997 1998 switch (id) { 1999 case ST_LSM6DSX_ID_ACC: 2000 iio_dev->info = &st_lsm6dsx_acc_info; 2001 scnprintf(sensor->name, sizeof(sensor->name), "%s_accel", 2002 name); 2003 break; 2004 case ST_LSM6DSX_ID_GYRO: 2005 iio_dev->info = &st_lsm6dsx_gyro_info; 2006 scnprintf(sensor->name, sizeof(sensor->name), "%s_gyro", 2007 name); 2008 break; 2009 default: 2010 return NULL; 2011 } 2012 iio_dev->name = sensor->name; 2013 2014 return iio_dev; 2015 } 2016 2017 static bool 2018 st_lsm6dsx_report_motion_event(struct st_lsm6dsx_hw *hw) 2019 { 2020 const struct st_lsm6dsx_event_settings *event_settings; 2021 int err, data; 2022 s64 timestamp; 2023 2024 if (!hw->enable_event) 2025 return false; 2026 2027 event_settings = &hw->settings->event_settings; 2028 err = st_lsm6dsx_read_locked(hw, event_settings->wakeup_src_reg, 2029 &data, sizeof(data)); 2030 if (err < 0) 2031 return false; 2032 2033 timestamp = iio_get_time_ns(hw->iio_devs[ST_LSM6DSX_ID_ACC]); 2034 if ((data & hw->settings->event_settings.wakeup_src_z_mask) && 2035 (hw->enable_event & BIT(IIO_MOD_Z))) 2036 iio_push_event(hw->iio_devs[ST_LSM6DSX_ID_ACC], 2037 IIO_MOD_EVENT_CODE(IIO_ACCEL, 2038 0, 2039 IIO_MOD_Z, 2040 IIO_EV_TYPE_THRESH, 2041 IIO_EV_DIR_EITHER), 2042 timestamp); 2043 2044 if ((data & hw->settings->event_settings.wakeup_src_y_mask) && 2045 (hw->enable_event & BIT(IIO_MOD_Y))) 2046 iio_push_event(hw->iio_devs[ST_LSM6DSX_ID_ACC], 2047 IIO_MOD_EVENT_CODE(IIO_ACCEL, 2048 0, 2049 IIO_MOD_Y, 2050 IIO_EV_TYPE_THRESH, 2051 IIO_EV_DIR_EITHER), 2052 timestamp); 2053 2054 if ((data & hw->settings->event_settings.wakeup_src_x_mask) && 2055 (hw->enable_event & BIT(IIO_MOD_X))) 2056 iio_push_event(hw->iio_devs[ST_LSM6DSX_ID_ACC], 2057 IIO_MOD_EVENT_CODE(IIO_ACCEL, 2058 0, 2059 IIO_MOD_X, 2060 IIO_EV_TYPE_THRESH, 2061 IIO_EV_DIR_EITHER), 2062 timestamp); 2063 2064 return data & event_settings->wakeup_src_status_mask; 2065 } 2066 2067 static irqreturn_t st_lsm6dsx_handler_thread(int irq, void *private) 2068 { 2069 struct st_lsm6dsx_hw *hw = private; 2070 bool event; 2071 int count; 2072 2073 event = st_lsm6dsx_report_motion_event(hw); 2074 2075 if (!hw->settings->fifo_ops.read_fifo) 2076 return event ? IRQ_HANDLED : IRQ_NONE; 2077 2078 mutex_lock(&hw->fifo_lock); 2079 count = hw->settings->fifo_ops.read_fifo(hw); 2080 mutex_unlock(&hw->fifo_lock); 2081 2082 return count || event ? IRQ_HANDLED : IRQ_NONE; 2083 } 2084 2085 static int st_lsm6dsx_irq_setup(struct st_lsm6dsx_hw *hw) 2086 { 2087 struct device_node *np = hw->dev->of_node; 2088 struct st_sensors_platform_data *pdata; 2089 const struct st_lsm6dsx_reg *reg; 2090 unsigned long irq_type; 2091 bool irq_active_low; 2092 int err; 2093 2094 irq_type = irqd_get_trigger_type(irq_get_irq_data(hw->irq)); 2095 2096 switch (irq_type) { 2097 case IRQF_TRIGGER_HIGH: 2098 case IRQF_TRIGGER_RISING: 2099 irq_active_low = false; 2100 break; 2101 case IRQF_TRIGGER_LOW: 2102 case IRQF_TRIGGER_FALLING: 2103 irq_active_low = true; 2104 break; 2105 default: 2106 dev_info(hw->dev, "mode %lx unsupported\n", irq_type); 2107 return -EINVAL; 2108 } 2109 2110 reg = &hw->settings->irq_config.hla; 2111 err = regmap_update_bits(hw->regmap, reg->addr, reg->mask, 2112 ST_LSM6DSX_SHIFT_VAL(irq_active_low, 2113 reg->mask)); 2114 if (err < 0) 2115 return err; 2116 2117 pdata = (struct st_sensors_platform_data *)hw->dev->platform_data; 2118 if ((np && of_property_read_bool(np, "drive-open-drain")) || 2119 (pdata && pdata->open_drain)) { 2120 reg = &hw->settings->irq_config.od; 2121 err = regmap_update_bits(hw->regmap, reg->addr, reg->mask, 2122 ST_LSM6DSX_SHIFT_VAL(1, reg->mask)); 2123 if (err < 0) 2124 return err; 2125 2126 irq_type |= IRQF_SHARED; 2127 } 2128 2129 err = devm_request_threaded_irq(hw->dev, hw->irq, 2130 NULL, 2131 st_lsm6dsx_handler_thread, 2132 irq_type | IRQF_ONESHOT, 2133 "lsm6dsx", hw); 2134 if (err) { 2135 dev_err(hw->dev, "failed to request trigger irq %d\n", 2136 hw->irq); 2137 return err; 2138 } 2139 2140 return 0; 2141 } 2142 2143 int st_lsm6dsx_probe(struct device *dev, int irq, int hw_id, 2144 struct regmap *regmap) 2145 { 2146 struct st_sensors_platform_data *pdata = dev->platform_data; 2147 const struct st_lsm6dsx_shub_settings *hub_settings; 2148 struct device_node *np = dev->of_node; 2149 struct st_lsm6dsx_hw *hw; 2150 const char *name = NULL; 2151 int i, err; 2152 2153 hw = devm_kzalloc(dev, sizeof(*hw), GFP_KERNEL); 2154 if (!hw) 2155 return -ENOMEM; 2156 2157 dev_set_drvdata(dev, (void *)hw); 2158 2159 mutex_init(&hw->fifo_lock); 2160 mutex_init(&hw->conf_lock); 2161 mutex_init(&hw->page_lock); 2162 2163 hw->buff = devm_kzalloc(dev, ST_LSM6DSX_BUFF_SIZE, GFP_KERNEL); 2164 if (!hw->buff) 2165 return -ENOMEM; 2166 2167 hw->dev = dev; 2168 hw->irq = irq; 2169 hw->regmap = regmap; 2170 2171 err = st_lsm6dsx_check_whoami(hw, hw_id, &name); 2172 if (err < 0) 2173 return err; 2174 2175 for (i = 0; i < ST_LSM6DSX_ID_EXT0; i++) { 2176 hw->iio_devs[i] = st_lsm6dsx_alloc_iiodev(hw, i, name); 2177 if (!hw->iio_devs[i]) 2178 return -ENOMEM; 2179 } 2180 2181 err = st_lsm6dsx_init_device(hw); 2182 if (err < 0) 2183 return err; 2184 2185 hub_settings = &hw->settings->shub_settings; 2186 if (hub_settings->master_en.addr) { 2187 err = st_lsm6dsx_shub_probe(hw, name); 2188 if (err < 0) 2189 return err; 2190 } 2191 2192 if (hw->irq > 0) { 2193 err = st_lsm6dsx_irq_setup(hw); 2194 if (err < 0) 2195 return err; 2196 2197 err = st_lsm6dsx_fifo_setup(hw); 2198 if (err < 0) 2199 return err; 2200 } 2201 2202 for (i = 0; i < ST_LSM6DSX_ID_MAX; i++) { 2203 if (!hw->iio_devs[i]) 2204 continue; 2205 2206 err = devm_iio_device_register(hw->dev, hw->iio_devs[i]); 2207 if (err) 2208 return err; 2209 } 2210 2211 if ((np && of_property_read_bool(np, "wakeup-source")) || 2212 (pdata && pdata->wakeup_source)) 2213 device_init_wakeup(dev, true); 2214 2215 return 0; 2216 } 2217 EXPORT_SYMBOL(st_lsm6dsx_probe); 2218 2219 static int __maybe_unused st_lsm6dsx_suspend(struct device *dev) 2220 { 2221 struct st_lsm6dsx_hw *hw = dev_get_drvdata(dev); 2222 struct st_lsm6dsx_sensor *sensor; 2223 int i, err = 0; 2224 2225 for (i = 0; i < ST_LSM6DSX_ID_MAX; i++) { 2226 if (!hw->iio_devs[i]) 2227 continue; 2228 2229 sensor = iio_priv(hw->iio_devs[i]); 2230 if (!(hw->enable_mask & BIT(sensor->id))) 2231 continue; 2232 2233 if (device_may_wakeup(dev) && 2234 sensor->id == ST_LSM6DSX_ID_ACC && hw->enable_event) { 2235 /* Enable wake from IRQ */ 2236 enable_irq_wake(hw->irq); 2237 continue; 2238 } 2239 2240 if (sensor->id == ST_LSM6DSX_ID_EXT0 || 2241 sensor->id == ST_LSM6DSX_ID_EXT1 || 2242 sensor->id == ST_LSM6DSX_ID_EXT2) 2243 err = st_lsm6dsx_shub_set_enable(sensor, false); 2244 else 2245 err = st_lsm6dsx_sensor_set_enable(sensor, false); 2246 if (err < 0) 2247 return err; 2248 2249 hw->suspend_mask |= BIT(sensor->id); 2250 } 2251 2252 if (hw->fifo_mode != ST_LSM6DSX_FIFO_BYPASS) 2253 err = st_lsm6dsx_flush_fifo(hw); 2254 2255 return err; 2256 } 2257 2258 static int __maybe_unused st_lsm6dsx_resume(struct device *dev) 2259 { 2260 struct st_lsm6dsx_hw *hw = dev_get_drvdata(dev); 2261 struct st_lsm6dsx_sensor *sensor; 2262 int i, err = 0; 2263 2264 for (i = 0; i < ST_LSM6DSX_ID_MAX; i++) { 2265 if (!hw->iio_devs[i]) 2266 continue; 2267 2268 sensor = iio_priv(hw->iio_devs[i]); 2269 if (device_may_wakeup(dev) && 2270 sensor->id == ST_LSM6DSX_ID_ACC && hw->enable_event) 2271 disable_irq_wake(hw->irq); 2272 2273 if (!(hw->suspend_mask & BIT(sensor->id))) 2274 continue; 2275 2276 if (sensor->id == ST_LSM6DSX_ID_EXT0 || 2277 sensor->id == ST_LSM6DSX_ID_EXT1 || 2278 sensor->id == ST_LSM6DSX_ID_EXT2) 2279 err = st_lsm6dsx_shub_set_enable(sensor, true); 2280 else 2281 err = st_lsm6dsx_sensor_set_enable(sensor, true); 2282 if (err < 0) 2283 return err; 2284 2285 hw->suspend_mask &= ~BIT(sensor->id); 2286 } 2287 2288 if (hw->enable_mask) 2289 err = st_lsm6dsx_set_fifo_mode(hw, ST_LSM6DSX_FIFO_CONT); 2290 2291 return err; 2292 } 2293 2294 const struct dev_pm_ops st_lsm6dsx_pm_ops = { 2295 SET_SYSTEM_SLEEP_PM_OPS(st_lsm6dsx_suspend, st_lsm6dsx_resume) 2296 }; 2297 EXPORT_SYMBOL(st_lsm6dsx_pm_ops); 2298 2299 MODULE_AUTHOR("Lorenzo Bianconi <lorenzo.bianconi@st.com>"); 2300 MODULE_AUTHOR("Denis Ciocca <denis.ciocca@st.com>"); 2301 MODULE_DESCRIPTION("STMicroelectronics st_lsm6dsx driver"); 2302 MODULE_LICENSE("GPL v2"); 2303