1 // SPDX-License-Identifier: GPL-2.0-only 2 /* 3 * STMicroelectronics st_lsm6dsx sensor driver 4 * 5 * The ST LSM6DSx IMU MEMS series consists of 3D digital accelerometer 6 * and 3D digital gyroscope system-in-package with a digital I2C/SPI serial 7 * interface standard output. 8 * LSM6DSx IMU MEMS series has a dynamic user-selectable full-scale 9 * acceleration range of +-2/+-4/+-8/+-16 g and an angular rate range of 10 * +-125/+-245/+-500/+-1000/+-2000 dps 11 * LSM6DSx series has an integrated First-In-First-Out (FIFO) buffer 12 * allowing dynamic batching of sensor data. 13 * LSM9DSx series is similar but includes an additional magnetometer, handled 14 * by a different driver. 15 * 16 * Supported sensors: 17 * - LSM6DS3: 18 * - Accelerometer/Gyroscope supported ODR [Hz]: 13, 26, 52, 104, 208, 416 19 * - Accelerometer supported full-scale [g]: +-2/+-4/+-8/+-16 20 * - Gyroscope supported full-scale [dps]: +-125/+-245/+-500/+-1000/+-2000 21 * - FIFO size: 8KB 22 * 23 * - LSM6DS3H/LSM6DSL/LSM6DSM/ISM330DLC/LSM6DS3TR-C: 24 * - Accelerometer/Gyroscope supported ODR [Hz]: 13, 26, 52, 104, 208, 416 25 * - Accelerometer supported full-scale [g]: +-2/+-4/+-8/+-16 26 * - Gyroscope supported full-scale [dps]: +-125/+-245/+-500/+-1000/+-2000 27 * - FIFO size: 4KB 28 * 29 * - LSM6DSO/LSM6DSOX/ASM330LHH/LSM6DSR/ISM330DHCX: 30 * - Accelerometer/Gyroscope supported ODR [Hz]: 13, 26, 52, 104, 208, 416 31 * - Accelerometer supported full-scale [g]: +-2/+-4/+-8/+-16 32 * - Gyroscope supported full-scale [dps]: +-125/+-245/+-500/+-1000/+-2000 33 * - FIFO size: 3KB 34 * 35 * - LSM9DS1: 36 * - Accelerometer supported ODR [Hz]: 10, 50, 119, 238, 476, 952 37 * - Accelerometer supported full-scale [g]: +-2/+-4/+-8/+-16 38 * - Gyroscope supported ODR [Hz]: 15, 60, 119, 238, 476, 952 39 * - Gyroscope supported full-scale [dps]: +-245/+-500/+-2000 40 * - FIFO size: 32 41 * 42 * Copyright 2016 STMicroelectronics Inc. 43 * 44 * Lorenzo Bianconi <lorenzo.bianconi@st.com> 45 * Denis Ciocca <denis.ciocca@st.com> 46 */ 47 48 #include <linux/kernel.h> 49 #include <linux/module.h> 50 #include <linux/delay.h> 51 #include <linux/iio/events.h> 52 #include <linux/iio/iio.h> 53 #include <linux/iio/sysfs.h> 54 #include <linux/interrupt.h> 55 #include <linux/irq.h> 56 #include <linux/pm.h> 57 #include <linux/regmap.h> 58 #include <linux/bitfield.h> 59 60 #include <linux/platform_data/st_sensors_pdata.h> 61 62 #include "st_lsm6dsx.h" 63 64 #define ST_LSM6DSX_REG_WHOAMI_ADDR 0x0f 65 66 #define ST_LSM6DSX_TS_SENSITIVITY 25000UL /* 25us */ 67 68 static const struct iio_chan_spec st_lsm6dsx_acc_channels[] = { 69 ST_LSM6DSX_CHANNEL_ACC(IIO_ACCEL, 0x28, IIO_MOD_X, 0), 70 ST_LSM6DSX_CHANNEL_ACC(IIO_ACCEL, 0x2a, IIO_MOD_Y, 1), 71 ST_LSM6DSX_CHANNEL_ACC(IIO_ACCEL, 0x2c, IIO_MOD_Z, 2), 72 IIO_CHAN_SOFT_TIMESTAMP(3), 73 }; 74 75 static const struct iio_chan_spec st_lsm6dsx_gyro_channels[] = { 76 ST_LSM6DSX_CHANNEL(IIO_ANGL_VEL, 0x22, IIO_MOD_X, 0), 77 ST_LSM6DSX_CHANNEL(IIO_ANGL_VEL, 0x24, IIO_MOD_Y, 1), 78 ST_LSM6DSX_CHANNEL(IIO_ANGL_VEL, 0x26, IIO_MOD_Z, 2), 79 IIO_CHAN_SOFT_TIMESTAMP(3), 80 }; 81 82 static const struct iio_chan_spec st_lsm6ds0_gyro_channels[] = { 83 ST_LSM6DSX_CHANNEL(IIO_ANGL_VEL, 0x18, IIO_MOD_X, 0), 84 ST_LSM6DSX_CHANNEL(IIO_ANGL_VEL, 0x1a, IIO_MOD_Y, 1), 85 ST_LSM6DSX_CHANNEL(IIO_ANGL_VEL, 0x1c, IIO_MOD_Z, 2), 86 IIO_CHAN_SOFT_TIMESTAMP(3), 87 }; 88 89 static const struct st_lsm6dsx_settings st_lsm6dsx_sensor_settings[] = { 90 { 91 .wai = 0x68, 92 .reset = { 93 .addr = 0x22, 94 .mask = BIT(0), 95 }, 96 .boot = { 97 .addr = 0x22, 98 .mask = BIT(7), 99 }, 100 .bdu = { 101 .addr = 0x22, 102 .mask = BIT(6), 103 }, 104 .max_fifo_size = 32, 105 .id = { 106 { 107 .hw_id = ST_LSM9DS1_ID, 108 .name = ST_LSM9DS1_DEV_NAME, 109 }, 110 }, 111 .channels = { 112 [ST_LSM6DSX_ID_ACC] = { 113 .chan = st_lsm6dsx_acc_channels, 114 .len = ARRAY_SIZE(st_lsm6dsx_acc_channels), 115 }, 116 [ST_LSM6DSX_ID_GYRO] = { 117 .chan = st_lsm6ds0_gyro_channels, 118 .len = ARRAY_SIZE(st_lsm6ds0_gyro_channels), 119 }, 120 }, 121 .odr_table = { 122 [ST_LSM6DSX_ID_ACC] = { 123 .reg = { 124 .addr = 0x20, 125 .mask = GENMASK(7, 5), 126 }, 127 .odr_avl[0] = { 10, 0x01 }, 128 .odr_avl[1] = { 50, 0x02 }, 129 .odr_avl[2] = { 119, 0x03 }, 130 .odr_avl[3] = { 238, 0x04 }, 131 .odr_avl[4] = { 476, 0x05 }, 132 .odr_avl[5] = { 952, 0x06 }, 133 }, 134 [ST_LSM6DSX_ID_GYRO] = { 135 .reg = { 136 .addr = 0x10, 137 .mask = GENMASK(7, 5), 138 }, 139 .odr_avl[0] = { 15, 0x01 }, 140 .odr_avl[1] = { 60, 0x02 }, 141 .odr_avl[2] = { 119, 0x03 }, 142 .odr_avl[3] = { 238, 0x04 }, 143 .odr_avl[4] = { 476, 0x05 }, 144 .odr_avl[5] = { 952, 0x06 }, 145 }, 146 }, 147 .fs_table = { 148 [ST_LSM6DSX_ID_ACC] = { 149 .reg = { 150 .addr = 0x20, 151 .mask = GENMASK(4, 3), 152 }, 153 .fs_avl[0] = { IIO_G_TO_M_S_2(61), 0x0 }, 154 .fs_avl[1] = { IIO_G_TO_M_S_2(122), 0x2 }, 155 .fs_avl[2] = { IIO_G_TO_M_S_2(244), 0x3 }, 156 .fs_avl[3] = { IIO_G_TO_M_S_2(732), 0x1 }, 157 .fs_len = 4, 158 }, 159 [ST_LSM6DSX_ID_GYRO] = { 160 .reg = { 161 .addr = 0x10, 162 .mask = GENMASK(4, 3), 163 }, 164 165 .fs_avl[0] = { IIO_DEGREE_TO_RAD(8750), 0x0 }, 166 .fs_avl[1] = { IIO_DEGREE_TO_RAD(17500), 0x1 }, 167 .fs_avl[2] = { IIO_DEGREE_TO_RAD(70000), 0x3 }, 168 .fs_len = 3, 169 }, 170 }, 171 .irq_config = { 172 .irq1 = { 173 .addr = 0x0c, 174 .mask = BIT(3), 175 }, 176 .irq2 = { 177 .addr = 0x0d, 178 .mask = BIT(3), 179 }, 180 .hla = { 181 .addr = 0x22, 182 .mask = BIT(5), 183 }, 184 .od = { 185 .addr = 0x22, 186 .mask = BIT(4), 187 }, 188 }, 189 }, 190 { 191 .wai = 0x69, 192 .reset = { 193 .addr = 0x12, 194 .mask = BIT(0), 195 }, 196 .boot = { 197 .addr = 0x12, 198 .mask = BIT(7), 199 }, 200 .bdu = { 201 .addr = 0x12, 202 .mask = BIT(6), 203 }, 204 .max_fifo_size = 1365, 205 .id = { 206 { 207 .hw_id = ST_LSM6DS3_ID, 208 .name = ST_LSM6DS3_DEV_NAME, 209 }, 210 }, 211 .channels = { 212 [ST_LSM6DSX_ID_ACC] = { 213 .chan = st_lsm6dsx_acc_channels, 214 .len = ARRAY_SIZE(st_lsm6dsx_acc_channels), 215 }, 216 [ST_LSM6DSX_ID_GYRO] = { 217 .chan = st_lsm6dsx_gyro_channels, 218 .len = ARRAY_SIZE(st_lsm6dsx_gyro_channels), 219 }, 220 }, 221 .odr_table = { 222 [ST_LSM6DSX_ID_ACC] = { 223 .reg = { 224 .addr = 0x10, 225 .mask = GENMASK(7, 4), 226 }, 227 .odr_avl[0] = { 13, 0x01 }, 228 .odr_avl[1] = { 26, 0x02 }, 229 .odr_avl[2] = { 52, 0x03 }, 230 .odr_avl[3] = { 104, 0x04 }, 231 .odr_avl[4] = { 208, 0x05 }, 232 .odr_avl[5] = { 416, 0x06 }, 233 }, 234 [ST_LSM6DSX_ID_GYRO] = { 235 .reg = { 236 .addr = 0x11, 237 .mask = GENMASK(7, 4), 238 }, 239 .odr_avl[0] = { 13, 0x01 }, 240 .odr_avl[1] = { 26, 0x02 }, 241 .odr_avl[2] = { 52, 0x03 }, 242 .odr_avl[3] = { 104, 0x04 }, 243 .odr_avl[4] = { 208, 0x05 }, 244 .odr_avl[5] = { 416, 0x06 }, 245 }, 246 }, 247 .fs_table = { 248 [ST_LSM6DSX_ID_ACC] = { 249 .reg = { 250 .addr = 0x10, 251 .mask = GENMASK(3, 2), 252 }, 253 .fs_avl[0] = { IIO_G_TO_M_S_2(61), 0x0 }, 254 .fs_avl[1] = { IIO_G_TO_M_S_2(122), 0x2 }, 255 .fs_avl[2] = { IIO_G_TO_M_S_2(244), 0x3 }, 256 .fs_avl[3] = { IIO_G_TO_M_S_2(488), 0x1 }, 257 .fs_len = 4, 258 }, 259 [ST_LSM6DSX_ID_GYRO] = { 260 .reg = { 261 .addr = 0x11, 262 .mask = GENMASK(3, 2), 263 }, 264 .fs_avl[0] = { IIO_DEGREE_TO_RAD(8750), 0x0 }, 265 .fs_avl[1] = { IIO_DEGREE_TO_RAD(17500), 0x1 }, 266 .fs_avl[2] = { IIO_DEGREE_TO_RAD(35000), 0x2 }, 267 .fs_avl[3] = { IIO_DEGREE_TO_RAD(70000), 0x3 }, 268 .fs_len = 4, 269 }, 270 }, 271 .irq_config = { 272 .irq1 = { 273 .addr = 0x0d, 274 .mask = BIT(3), 275 }, 276 .irq2 = { 277 .addr = 0x0e, 278 .mask = BIT(3), 279 }, 280 .lir = { 281 .addr = 0x58, 282 .mask = BIT(0), 283 }, 284 .irq1_func = { 285 .addr = 0x5e, 286 .mask = BIT(5), 287 }, 288 .irq2_func = { 289 .addr = 0x5f, 290 .mask = BIT(5), 291 }, 292 .hla = { 293 .addr = 0x12, 294 .mask = BIT(5), 295 }, 296 .od = { 297 .addr = 0x12, 298 .mask = BIT(4), 299 }, 300 }, 301 .decimator = { 302 [ST_LSM6DSX_ID_ACC] = { 303 .addr = 0x08, 304 .mask = GENMASK(2, 0), 305 }, 306 [ST_LSM6DSX_ID_GYRO] = { 307 .addr = 0x08, 308 .mask = GENMASK(5, 3), 309 }, 310 }, 311 .fifo_ops = { 312 .update_fifo = st_lsm6dsx_update_fifo, 313 .read_fifo = st_lsm6dsx_read_fifo, 314 .fifo_th = { 315 .addr = 0x06, 316 .mask = GENMASK(11, 0), 317 }, 318 .fifo_diff = { 319 .addr = 0x3a, 320 .mask = GENMASK(11, 0), 321 }, 322 .th_wl = 3, /* 1LSB = 2B */ 323 }, 324 .ts_settings = { 325 .timer_en = { 326 .addr = 0x58, 327 .mask = BIT(7), 328 }, 329 .hr_timer = { 330 .addr = 0x5c, 331 .mask = BIT(4), 332 }, 333 .fifo_en = { 334 .addr = 0x07, 335 .mask = BIT(7), 336 }, 337 .decimator = { 338 .addr = 0x09, 339 .mask = GENMASK(5, 3), 340 }, 341 }, 342 .event_settings = { 343 .wakeup_reg = { 344 .addr = 0x5B, 345 .mask = GENMASK(5, 0), 346 }, 347 .wakeup_src_reg = 0x1b, 348 .wakeup_src_status_mask = BIT(3), 349 .wakeup_src_z_mask = BIT(0), 350 .wakeup_src_y_mask = BIT(1), 351 .wakeup_src_x_mask = BIT(2), 352 }, 353 }, 354 { 355 .wai = 0x69, 356 .reset = { 357 .addr = 0x12, 358 .mask = BIT(0), 359 }, 360 .boot = { 361 .addr = 0x12, 362 .mask = BIT(7), 363 }, 364 .bdu = { 365 .addr = 0x12, 366 .mask = BIT(6), 367 }, 368 .max_fifo_size = 682, 369 .id = { 370 { 371 .hw_id = ST_LSM6DS3H_ID, 372 .name = ST_LSM6DS3H_DEV_NAME, 373 }, 374 }, 375 .channels = { 376 [ST_LSM6DSX_ID_ACC] = { 377 .chan = st_lsm6dsx_acc_channels, 378 .len = ARRAY_SIZE(st_lsm6dsx_acc_channels), 379 }, 380 [ST_LSM6DSX_ID_GYRO] = { 381 .chan = st_lsm6dsx_gyro_channels, 382 .len = ARRAY_SIZE(st_lsm6dsx_gyro_channels), 383 }, 384 }, 385 .odr_table = { 386 [ST_LSM6DSX_ID_ACC] = { 387 .reg = { 388 .addr = 0x10, 389 .mask = GENMASK(7, 4), 390 }, 391 .odr_avl[0] = { 13, 0x01 }, 392 .odr_avl[1] = { 26, 0x02 }, 393 .odr_avl[2] = { 52, 0x03 }, 394 .odr_avl[3] = { 104, 0x04 }, 395 .odr_avl[4] = { 208, 0x05 }, 396 .odr_avl[5] = { 416, 0x06 }, 397 }, 398 [ST_LSM6DSX_ID_GYRO] = { 399 .reg = { 400 .addr = 0x11, 401 .mask = GENMASK(7, 4), 402 }, 403 .odr_avl[0] = { 13, 0x01 }, 404 .odr_avl[1] = { 26, 0x02 }, 405 .odr_avl[2] = { 52, 0x03 }, 406 .odr_avl[3] = { 104, 0x04 }, 407 .odr_avl[4] = { 208, 0x05 }, 408 .odr_avl[5] = { 416, 0x06 }, 409 }, 410 }, 411 .fs_table = { 412 [ST_LSM6DSX_ID_ACC] = { 413 .reg = { 414 .addr = 0x10, 415 .mask = GENMASK(3, 2), 416 }, 417 .fs_avl[0] = { IIO_G_TO_M_S_2(61), 0x0 }, 418 .fs_avl[1] = { IIO_G_TO_M_S_2(122), 0x2 }, 419 .fs_avl[2] = { IIO_G_TO_M_S_2(244), 0x3 }, 420 .fs_avl[3] = { IIO_G_TO_M_S_2(488), 0x1 }, 421 .fs_len = 4, 422 }, 423 [ST_LSM6DSX_ID_GYRO] = { 424 .reg = { 425 .addr = 0x11, 426 .mask = GENMASK(3, 2), 427 }, 428 .fs_avl[0] = { IIO_DEGREE_TO_RAD(8750), 0x0 }, 429 .fs_avl[1] = { IIO_DEGREE_TO_RAD(17500), 0x1 }, 430 .fs_avl[2] = { IIO_DEGREE_TO_RAD(35000), 0x2 }, 431 .fs_avl[3] = { IIO_DEGREE_TO_RAD(70000), 0x3 }, 432 .fs_len = 4, 433 }, 434 }, 435 .irq_config = { 436 .irq1 = { 437 .addr = 0x0d, 438 .mask = BIT(3), 439 }, 440 .irq2 = { 441 .addr = 0x0e, 442 .mask = BIT(3), 443 }, 444 .lir = { 445 .addr = 0x58, 446 .mask = BIT(0), 447 }, 448 .irq1_func = { 449 .addr = 0x5e, 450 .mask = BIT(5), 451 }, 452 .irq2_func = { 453 .addr = 0x5f, 454 .mask = BIT(5), 455 }, 456 .hla = { 457 .addr = 0x12, 458 .mask = BIT(5), 459 }, 460 .od = { 461 .addr = 0x12, 462 .mask = BIT(4), 463 }, 464 }, 465 .decimator = { 466 [ST_LSM6DSX_ID_ACC] = { 467 .addr = 0x08, 468 .mask = GENMASK(2, 0), 469 }, 470 [ST_LSM6DSX_ID_GYRO] = { 471 .addr = 0x08, 472 .mask = GENMASK(5, 3), 473 }, 474 }, 475 .fifo_ops = { 476 .update_fifo = st_lsm6dsx_update_fifo, 477 .read_fifo = st_lsm6dsx_read_fifo, 478 .fifo_th = { 479 .addr = 0x06, 480 .mask = GENMASK(11, 0), 481 }, 482 .fifo_diff = { 483 .addr = 0x3a, 484 .mask = GENMASK(11, 0), 485 }, 486 .th_wl = 3, /* 1LSB = 2B */ 487 }, 488 .ts_settings = { 489 .timer_en = { 490 .addr = 0x58, 491 .mask = BIT(7), 492 }, 493 .hr_timer = { 494 .addr = 0x5c, 495 .mask = BIT(4), 496 }, 497 .fifo_en = { 498 .addr = 0x07, 499 .mask = BIT(7), 500 }, 501 .decimator = { 502 .addr = 0x09, 503 .mask = GENMASK(5, 3), 504 }, 505 }, 506 .event_settings = { 507 .wakeup_reg = { 508 .addr = 0x5B, 509 .mask = GENMASK(5, 0), 510 }, 511 .wakeup_src_reg = 0x1b, 512 .wakeup_src_status_mask = BIT(3), 513 .wakeup_src_z_mask = BIT(0), 514 .wakeup_src_y_mask = BIT(1), 515 .wakeup_src_x_mask = BIT(2), 516 }, 517 }, 518 { 519 .wai = 0x6a, 520 .reset = { 521 .addr = 0x12, 522 .mask = BIT(0), 523 }, 524 .boot = { 525 .addr = 0x12, 526 .mask = BIT(7), 527 }, 528 .bdu = { 529 .addr = 0x12, 530 .mask = BIT(6), 531 }, 532 .max_fifo_size = 682, 533 .id = { 534 { 535 .hw_id = ST_LSM6DSL_ID, 536 .name = ST_LSM6DSL_DEV_NAME, 537 }, { 538 .hw_id = ST_LSM6DSM_ID, 539 .name = ST_LSM6DSM_DEV_NAME, 540 }, { 541 .hw_id = ST_ISM330DLC_ID, 542 .name = ST_ISM330DLC_DEV_NAME, 543 }, { 544 .hw_id = ST_LSM6DS3TRC_ID, 545 .name = ST_LSM6DS3TRC_DEV_NAME, 546 }, 547 }, 548 .channels = { 549 [ST_LSM6DSX_ID_ACC] = { 550 .chan = st_lsm6dsx_acc_channels, 551 .len = ARRAY_SIZE(st_lsm6dsx_acc_channels), 552 }, 553 [ST_LSM6DSX_ID_GYRO] = { 554 .chan = st_lsm6dsx_gyro_channels, 555 .len = ARRAY_SIZE(st_lsm6dsx_gyro_channels), 556 }, 557 }, 558 .odr_table = { 559 [ST_LSM6DSX_ID_ACC] = { 560 .reg = { 561 .addr = 0x10, 562 .mask = GENMASK(7, 4), 563 }, 564 .odr_avl[0] = { 13, 0x01 }, 565 .odr_avl[1] = { 26, 0x02 }, 566 .odr_avl[2] = { 52, 0x03 }, 567 .odr_avl[3] = { 104, 0x04 }, 568 .odr_avl[4] = { 208, 0x05 }, 569 .odr_avl[5] = { 416, 0x06 }, 570 }, 571 [ST_LSM6DSX_ID_GYRO] = { 572 .reg = { 573 .addr = 0x11, 574 .mask = GENMASK(7, 4), 575 }, 576 .odr_avl[0] = { 13, 0x01 }, 577 .odr_avl[1] = { 26, 0x02 }, 578 .odr_avl[2] = { 52, 0x03 }, 579 .odr_avl[3] = { 104, 0x04 }, 580 .odr_avl[4] = { 208, 0x05 }, 581 .odr_avl[5] = { 416, 0x06 }, 582 }, 583 }, 584 .fs_table = { 585 [ST_LSM6DSX_ID_ACC] = { 586 .reg = { 587 .addr = 0x10, 588 .mask = GENMASK(3, 2), 589 }, 590 .fs_avl[0] = { IIO_G_TO_M_S_2(61), 0x0 }, 591 .fs_avl[1] = { IIO_G_TO_M_S_2(122), 0x2 }, 592 .fs_avl[2] = { IIO_G_TO_M_S_2(244), 0x3 }, 593 .fs_avl[3] = { IIO_G_TO_M_S_2(488), 0x1 }, 594 .fs_len = 4, 595 }, 596 [ST_LSM6DSX_ID_GYRO] = { 597 .reg = { 598 .addr = 0x11, 599 .mask = GENMASK(3, 2), 600 }, 601 .fs_avl[0] = { IIO_DEGREE_TO_RAD(8750), 0x0 }, 602 .fs_avl[1] = { IIO_DEGREE_TO_RAD(17500), 0x1 }, 603 .fs_avl[2] = { IIO_DEGREE_TO_RAD(35000), 0x2 }, 604 .fs_avl[3] = { IIO_DEGREE_TO_RAD(70000), 0x3 }, 605 .fs_len = 4, 606 }, 607 }, 608 .irq_config = { 609 .irq1 = { 610 .addr = 0x0d, 611 .mask = BIT(3), 612 }, 613 .irq2 = { 614 .addr = 0x0e, 615 .mask = BIT(3), 616 }, 617 .lir = { 618 .addr = 0x58, 619 .mask = BIT(0), 620 }, 621 .irq1_func = { 622 .addr = 0x5e, 623 .mask = BIT(5), 624 }, 625 .irq2_func = { 626 .addr = 0x5f, 627 .mask = BIT(5), 628 }, 629 .hla = { 630 .addr = 0x12, 631 .mask = BIT(5), 632 }, 633 .od = { 634 .addr = 0x12, 635 .mask = BIT(4), 636 }, 637 }, 638 .decimator = { 639 [ST_LSM6DSX_ID_ACC] = { 640 .addr = 0x08, 641 .mask = GENMASK(2, 0), 642 }, 643 [ST_LSM6DSX_ID_GYRO] = { 644 .addr = 0x08, 645 .mask = GENMASK(5, 3), 646 }, 647 }, 648 .fifo_ops = { 649 .update_fifo = st_lsm6dsx_update_fifo, 650 .read_fifo = st_lsm6dsx_read_fifo, 651 .fifo_th = { 652 .addr = 0x06, 653 .mask = GENMASK(10, 0), 654 }, 655 .fifo_diff = { 656 .addr = 0x3a, 657 .mask = GENMASK(10, 0), 658 }, 659 .th_wl = 3, /* 1LSB = 2B */ 660 }, 661 .ts_settings = { 662 .timer_en = { 663 .addr = 0x19, 664 .mask = BIT(5), 665 }, 666 .hr_timer = { 667 .addr = 0x5c, 668 .mask = BIT(4), 669 }, 670 .fifo_en = { 671 .addr = 0x07, 672 .mask = BIT(7), 673 }, 674 .decimator = { 675 .addr = 0x09, 676 .mask = GENMASK(5, 3), 677 }, 678 }, 679 .event_settings = { 680 .enable_reg = { 681 .addr = 0x58, 682 .mask = BIT(7), 683 }, 684 .wakeup_reg = { 685 .addr = 0x5B, 686 .mask = GENMASK(5, 0), 687 }, 688 .wakeup_src_reg = 0x1b, 689 .wakeup_src_status_mask = BIT(3), 690 .wakeup_src_z_mask = BIT(0), 691 .wakeup_src_y_mask = BIT(1), 692 .wakeup_src_x_mask = BIT(2), 693 }, 694 }, 695 { 696 .wai = 0x6c, 697 .reset = { 698 .addr = 0x12, 699 .mask = BIT(0), 700 }, 701 .boot = { 702 .addr = 0x12, 703 .mask = BIT(7), 704 }, 705 .bdu = { 706 .addr = 0x12, 707 .mask = BIT(6), 708 }, 709 .max_fifo_size = 512, 710 .id = { 711 { 712 .hw_id = ST_LSM6DSO_ID, 713 .name = ST_LSM6DSO_DEV_NAME, 714 }, { 715 .hw_id = ST_LSM6DSOX_ID, 716 .name = ST_LSM6DSOX_DEV_NAME, 717 }, 718 }, 719 .channels = { 720 [ST_LSM6DSX_ID_ACC] = { 721 .chan = st_lsm6dsx_acc_channels, 722 .len = ARRAY_SIZE(st_lsm6dsx_acc_channels), 723 }, 724 [ST_LSM6DSX_ID_GYRO] = { 725 .chan = st_lsm6dsx_gyro_channels, 726 .len = ARRAY_SIZE(st_lsm6dsx_gyro_channels), 727 }, 728 }, 729 .drdy_mask = { 730 .addr = 0x13, 731 .mask = BIT(3), 732 }, 733 .odr_table = { 734 [ST_LSM6DSX_ID_ACC] = { 735 .reg = { 736 .addr = 0x10, 737 .mask = GENMASK(7, 4), 738 }, 739 .odr_avl[0] = { 13, 0x01 }, 740 .odr_avl[1] = { 26, 0x02 }, 741 .odr_avl[2] = { 52, 0x03 }, 742 .odr_avl[3] = { 104, 0x04 }, 743 .odr_avl[4] = { 208, 0x05 }, 744 .odr_avl[5] = { 416, 0x06 }, 745 }, 746 [ST_LSM6DSX_ID_GYRO] = { 747 .reg = { 748 .addr = 0x11, 749 .mask = GENMASK(7, 4), 750 }, 751 .odr_avl[0] = { 13, 0x01 }, 752 .odr_avl[1] = { 26, 0x02 }, 753 .odr_avl[2] = { 52, 0x03 }, 754 .odr_avl[3] = { 104, 0x04 }, 755 .odr_avl[4] = { 208, 0x05 }, 756 .odr_avl[5] = { 416, 0x06 }, 757 }, 758 }, 759 .fs_table = { 760 [ST_LSM6DSX_ID_ACC] = { 761 .reg = { 762 .addr = 0x10, 763 .mask = GENMASK(3, 2), 764 }, 765 .fs_avl[0] = { IIO_G_TO_M_S_2(61), 0x0 }, 766 .fs_avl[1] = { IIO_G_TO_M_S_2(122), 0x2 }, 767 .fs_avl[2] = { IIO_G_TO_M_S_2(244), 0x3 }, 768 .fs_avl[3] = { IIO_G_TO_M_S_2(488), 0x1 }, 769 .fs_len = 4, 770 }, 771 [ST_LSM6DSX_ID_GYRO] = { 772 .reg = { 773 .addr = 0x11, 774 .mask = GENMASK(3, 2), 775 }, 776 .fs_avl[0] = { IIO_DEGREE_TO_RAD(8750), 0x0 }, 777 .fs_avl[1] = { IIO_DEGREE_TO_RAD(17500), 0x1 }, 778 .fs_avl[2] = { IIO_DEGREE_TO_RAD(35000), 0x2 }, 779 .fs_avl[3] = { IIO_DEGREE_TO_RAD(70000), 0x3 }, 780 .fs_len = 4, 781 }, 782 }, 783 .irq_config = { 784 .irq1 = { 785 .addr = 0x0d, 786 .mask = BIT(3), 787 }, 788 .irq2 = { 789 .addr = 0x0e, 790 .mask = BIT(3), 791 }, 792 .lir = { 793 .addr = 0x56, 794 .mask = BIT(0), 795 }, 796 .clear_on_read = { 797 .addr = 0x56, 798 .mask = BIT(6), 799 }, 800 .irq1_func = { 801 .addr = 0x5e, 802 .mask = BIT(5), 803 }, 804 .irq2_func = { 805 .addr = 0x5f, 806 .mask = BIT(5), 807 }, 808 .hla = { 809 .addr = 0x12, 810 .mask = BIT(5), 811 }, 812 .od = { 813 .addr = 0x12, 814 .mask = BIT(4), 815 }, 816 }, 817 .batch = { 818 [ST_LSM6DSX_ID_ACC] = { 819 .addr = 0x09, 820 .mask = GENMASK(3, 0), 821 }, 822 [ST_LSM6DSX_ID_GYRO] = { 823 .addr = 0x09, 824 .mask = GENMASK(7, 4), 825 }, 826 }, 827 .fifo_ops = { 828 .update_fifo = st_lsm6dsx_update_fifo, 829 .read_fifo = st_lsm6dsx_read_tagged_fifo, 830 .fifo_th = { 831 .addr = 0x07, 832 .mask = GENMASK(8, 0), 833 }, 834 .fifo_diff = { 835 .addr = 0x3a, 836 .mask = GENMASK(9, 0), 837 }, 838 .th_wl = 1, 839 }, 840 .ts_settings = { 841 .timer_en = { 842 .addr = 0x19, 843 .mask = BIT(5), 844 }, 845 .decimator = { 846 .addr = 0x0a, 847 .mask = GENMASK(7, 6), 848 }, 849 .freq_fine = 0x63, 850 }, 851 .shub_settings = { 852 .page_mux = { 853 .addr = 0x01, 854 .mask = BIT(6), 855 }, 856 .master_en = { 857 .addr = 0x14, 858 .mask = BIT(2), 859 }, 860 .pullup_en = { 861 .addr = 0x14, 862 .mask = BIT(3), 863 }, 864 .aux_sens = { 865 .addr = 0x14, 866 .mask = GENMASK(1, 0), 867 }, 868 .wr_once = { 869 .addr = 0x14, 870 .mask = BIT(6), 871 }, 872 .shub_out = 0x02, 873 .slv0_addr = 0x15, 874 .dw_slv0_addr = 0x21, 875 .batch_en = BIT(3), 876 }, 877 .event_settings = { 878 .enable_reg = { 879 .addr = 0x58, 880 .mask = BIT(7), 881 }, 882 .wakeup_reg = { 883 .addr = 0x5b, 884 .mask = GENMASK(5, 0), 885 }, 886 .wakeup_src_reg = 0x1b, 887 .wakeup_src_status_mask = BIT(3), 888 .wakeup_src_z_mask = BIT(0), 889 .wakeup_src_y_mask = BIT(1), 890 .wakeup_src_x_mask = BIT(2), 891 }, 892 }, 893 { 894 .wai = 0x6b, 895 .reset = { 896 .addr = 0x12, 897 .mask = BIT(0), 898 }, 899 .boot = { 900 .addr = 0x12, 901 .mask = BIT(7), 902 }, 903 .bdu = { 904 .addr = 0x12, 905 .mask = BIT(6), 906 }, 907 .max_fifo_size = 512, 908 .id = { 909 { 910 .hw_id = ST_ASM330LHH_ID, 911 .name = ST_ASM330LHH_DEV_NAME, 912 }, 913 }, 914 .channels = { 915 [ST_LSM6DSX_ID_ACC] = { 916 .chan = st_lsm6dsx_acc_channels, 917 .len = ARRAY_SIZE(st_lsm6dsx_acc_channels), 918 }, 919 [ST_LSM6DSX_ID_GYRO] = { 920 .chan = st_lsm6dsx_gyro_channels, 921 .len = ARRAY_SIZE(st_lsm6dsx_gyro_channels), 922 }, 923 }, 924 .drdy_mask = { 925 .addr = 0x13, 926 .mask = BIT(3), 927 }, 928 .odr_table = { 929 [ST_LSM6DSX_ID_ACC] = { 930 .reg = { 931 .addr = 0x10, 932 .mask = GENMASK(7, 4), 933 }, 934 .odr_avl[0] = { 13, 0x01 }, 935 .odr_avl[1] = { 26, 0x02 }, 936 .odr_avl[2] = { 52, 0x03 }, 937 .odr_avl[3] = { 104, 0x04 }, 938 .odr_avl[4] = { 208, 0x05 }, 939 .odr_avl[5] = { 416, 0x06 }, 940 }, 941 [ST_LSM6DSX_ID_GYRO] = { 942 .reg = { 943 .addr = 0x11, 944 .mask = GENMASK(7, 4), 945 }, 946 .odr_avl[0] = { 13, 0x01 }, 947 .odr_avl[1] = { 26, 0x02 }, 948 .odr_avl[2] = { 52, 0x03 }, 949 .odr_avl[3] = { 104, 0x04 }, 950 .odr_avl[4] = { 208, 0x05 }, 951 .odr_avl[5] = { 416, 0x06 }, 952 }, 953 }, 954 .fs_table = { 955 [ST_LSM6DSX_ID_ACC] = { 956 .reg = { 957 .addr = 0x10, 958 .mask = GENMASK(3, 2), 959 }, 960 .fs_avl[0] = { IIO_G_TO_M_S_2(61), 0x0 }, 961 .fs_avl[1] = { IIO_G_TO_M_S_2(122), 0x2 }, 962 .fs_avl[2] = { IIO_G_TO_M_S_2(244), 0x3 }, 963 .fs_avl[3] = { IIO_G_TO_M_S_2(488), 0x1 }, 964 .fs_len = 4, 965 }, 966 [ST_LSM6DSX_ID_GYRO] = { 967 .reg = { 968 .addr = 0x11, 969 .mask = GENMASK(3, 2), 970 }, 971 .fs_avl[0] = { IIO_DEGREE_TO_RAD(8750), 0x0 }, 972 .fs_avl[1] = { IIO_DEGREE_TO_RAD(17500), 0x1 }, 973 .fs_avl[2] = { IIO_DEGREE_TO_RAD(35000), 0x2 }, 974 .fs_avl[3] = { IIO_DEGREE_TO_RAD(70000), 0x3 }, 975 .fs_len = 4, 976 }, 977 }, 978 .irq_config = { 979 .irq1 = { 980 .addr = 0x0d, 981 .mask = BIT(3), 982 }, 983 .irq2 = { 984 .addr = 0x0e, 985 .mask = BIT(3), 986 }, 987 .lir = { 988 .addr = 0x56, 989 .mask = BIT(0), 990 }, 991 .clear_on_read = { 992 .addr = 0x56, 993 .mask = BIT(6), 994 }, 995 .irq1_func = { 996 .addr = 0x5e, 997 .mask = BIT(5), 998 }, 999 .irq2_func = { 1000 .addr = 0x5f, 1001 .mask = BIT(5), 1002 }, 1003 .hla = { 1004 .addr = 0x12, 1005 .mask = BIT(5), 1006 }, 1007 .od = { 1008 .addr = 0x12, 1009 .mask = BIT(4), 1010 }, 1011 }, 1012 .batch = { 1013 [ST_LSM6DSX_ID_ACC] = { 1014 .addr = 0x09, 1015 .mask = GENMASK(3, 0), 1016 }, 1017 [ST_LSM6DSX_ID_GYRO] = { 1018 .addr = 0x09, 1019 .mask = GENMASK(7, 4), 1020 }, 1021 }, 1022 .fifo_ops = { 1023 .update_fifo = st_lsm6dsx_update_fifo, 1024 .read_fifo = st_lsm6dsx_read_tagged_fifo, 1025 .fifo_th = { 1026 .addr = 0x07, 1027 .mask = GENMASK(8, 0), 1028 }, 1029 .fifo_diff = { 1030 .addr = 0x3a, 1031 .mask = GENMASK(9, 0), 1032 }, 1033 .th_wl = 1, 1034 }, 1035 .ts_settings = { 1036 .timer_en = { 1037 .addr = 0x19, 1038 .mask = BIT(5), 1039 }, 1040 .decimator = { 1041 .addr = 0x0a, 1042 .mask = GENMASK(7, 6), 1043 }, 1044 .freq_fine = 0x63, 1045 }, 1046 .event_settings = { 1047 .enable_reg = { 1048 .addr = 0x58, 1049 .mask = BIT(7), 1050 }, 1051 .wakeup_reg = { 1052 .addr = 0x5B, 1053 .mask = GENMASK(5, 0), 1054 }, 1055 .wakeup_src_reg = 0x1b, 1056 .wakeup_src_status_mask = BIT(3), 1057 .wakeup_src_z_mask = BIT(0), 1058 .wakeup_src_y_mask = BIT(1), 1059 .wakeup_src_x_mask = BIT(2), 1060 }, 1061 }, 1062 { 1063 .wai = 0x6b, 1064 .reset = { 1065 .addr = 0x12, 1066 .mask = BIT(0), 1067 }, 1068 .boot = { 1069 .addr = 0x12, 1070 .mask = BIT(7), 1071 }, 1072 .bdu = { 1073 .addr = 0x12, 1074 .mask = BIT(6), 1075 }, 1076 .max_fifo_size = 512, 1077 .id = { 1078 { 1079 .hw_id = ST_LSM6DSR_ID, 1080 .name = ST_LSM6DSR_DEV_NAME, 1081 }, { 1082 .hw_id = ST_ISM330DHCX_ID, 1083 .name = ST_ISM330DHCX_DEV_NAME, 1084 }, 1085 }, 1086 .channels = { 1087 [ST_LSM6DSX_ID_ACC] = { 1088 .chan = st_lsm6dsx_acc_channels, 1089 .len = ARRAY_SIZE(st_lsm6dsx_acc_channels), 1090 }, 1091 [ST_LSM6DSX_ID_GYRO] = { 1092 .chan = st_lsm6dsx_gyro_channels, 1093 .len = ARRAY_SIZE(st_lsm6dsx_gyro_channels), 1094 }, 1095 }, 1096 .drdy_mask = { 1097 .addr = 0x13, 1098 .mask = BIT(3), 1099 }, 1100 .odr_table = { 1101 [ST_LSM6DSX_ID_ACC] = { 1102 .reg = { 1103 .addr = 0x10, 1104 .mask = GENMASK(7, 4), 1105 }, 1106 .odr_avl[0] = { 13, 0x01 }, 1107 .odr_avl[1] = { 26, 0x02 }, 1108 .odr_avl[2] = { 52, 0x03 }, 1109 .odr_avl[3] = { 104, 0x04 }, 1110 .odr_avl[4] = { 208, 0x05 }, 1111 .odr_avl[5] = { 416, 0x06 }, 1112 }, 1113 [ST_LSM6DSX_ID_GYRO] = { 1114 .reg = { 1115 .addr = 0x11, 1116 .mask = GENMASK(7, 4), 1117 }, 1118 .odr_avl[0] = { 13, 0x01 }, 1119 .odr_avl[1] = { 26, 0x02 }, 1120 .odr_avl[2] = { 52, 0x03 }, 1121 .odr_avl[3] = { 104, 0x04 }, 1122 .odr_avl[4] = { 208, 0x05 }, 1123 .odr_avl[5] = { 416, 0x06 }, 1124 }, 1125 }, 1126 .fs_table = { 1127 [ST_LSM6DSX_ID_ACC] = { 1128 .reg = { 1129 .addr = 0x10, 1130 .mask = GENMASK(3, 2), 1131 }, 1132 .fs_avl[0] = { IIO_G_TO_M_S_2(61), 0x0 }, 1133 .fs_avl[1] = { IIO_G_TO_M_S_2(122), 0x2 }, 1134 .fs_avl[2] = { IIO_G_TO_M_S_2(244), 0x3 }, 1135 .fs_avl[3] = { IIO_G_TO_M_S_2(488), 0x1 }, 1136 .fs_len = 4, 1137 }, 1138 [ST_LSM6DSX_ID_GYRO] = { 1139 .reg = { 1140 .addr = 0x11, 1141 .mask = GENMASK(3, 2), 1142 }, 1143 .fs_avl[0] = { IIO_DEGREE_TO_RAD(8750), 0x0 }, 1144 .fs_avl[1] = { IIO_DEGREE_TO_RAD(17500), 0x1 }, 1145 .fs_avl[2] = { IIO_DEGREE_TO_RAD(35000), 0x2 }, 1146 .fs_avl[3] = { IIO_DEGREE_TO_RAD(70000), 0x3 }, 1147 .fs_len = 4, 1148 }, 1149 }, 1150 .irq_config = { 1151 .irq1 = { 1152 .addr = 0x0d, 1153 .mask = BIT(3), 1154 }, 1155 .irq2 = { 1156 .addr = 0x0e, 1157 .mask = BIT(3), 1158 }, 1159 .lir = { 1160 .addr = 0x56, 1161 .mask = BIT(0), 1162 }, 1163 .clear_on_read = { 1164 .addr = 0x56, 1165 .mask = BIT(6), 1166 }, 1167 .irq1_func = { 1168 .addr = 0x5e, 1169 .mask = BIT(5), 1170 }, 1171 .irq2_func = { 1172 .addr = 0x5f, 1173 .mask = BIT(5), 1174 }, 1175 .hla = { 1176 .addr = 0x12, 1177 .mask = BIT(5), 1178 }, 1179 .od = { 1180 .addr = 0x12, 1181 .mask = BIT(4), 1182 }, 1183 }, 1184 .batch = { 1185 [ST_LSM6DSX_ID_ACC] = { 1186 .addr = 0x09, 1187 .mask = GENMASK(3, 0), 1188 }, 1189 [ST_LSM6DSX_ID_GYRO] = { 1190 .addr = 0x09, 1191 .mask = GENMASK(7, 4), 1192 }, 1193 }, 1194 .fifo_ops = { 1195 .update_fifo = st_lsm6dsx_update_fifo, 1196 .read_fifo = st_lsm6dsx_read_tagged_fifo, 1197 .fifo_th = { 1198 .addr = 0x07, 1199 .mask = GENMASK(8, 0), 1200 }, 1201 .fifo_diff = { 1202 .addr = 0x3a, 1203 .mask = GENMASK(9, 0), 1204 }, 1205 .th_wl = 1, 1206 }, 1207 .ts_settings = { 1208 .timer_en = { 1209 .addr = 0x19, 1210 .mask = BIT(5), 1211 }, 1212 .decimator = { 1213 .addr = 0x0a, 1214 .mask = GENMASK(7, 6), 1215 }, 1216 .freq_fine = 0x63, 1217 }, 1218 .shub_settings = { 1219 .page_mux = { 1220 .addr = 0x01, 1221 .mask = BIT(6), 1222 }, 1223 .master_en = { 1224 .addr = 0x14, 1225 .mask = BIT(2), 1226 }, 1227 .pullup_en = { 1228 .addr = 0x14, 1229 .mask = BIT(3), 1230 }, 1231 .aux_sens = { 1232 .addr = 0x14, 1233 .mask = GENMASK(1, 0), 1234 }, 1235 .wr_once = { 1236 .addr = 0x14, 1237 .mask = BIT(6), 1238 }, 1239 .shub_out = 0x02, 1240 .slv0_addr = 0x15, 1241 .dw_slv0_addr = 0x21, 1242 .batch_en = BIT(3), 1243 }, 1244 .event_settings = { 1245 .enable_reg = { 1246 .addr = 0x58, 1247 .mask = BIT(7), 1248 }, 1249 .wakeup_reg = { 1250 .addr = 0x5B, 1251 .mask = GENMASK(5, 0), 1252 }, 1253 .wakeup_src_reg = 0x1b, 1254 .wakeup_src_status_mask = BIT(3), 1255 .wakeup_src_z_mask = BIT(0), 1256 .wakeup_src_y_mask = BIT(1), 1257 .wakeup_src_x_mask = BIT(2), 1258 } 1259 }, 1260 }; 1261 1262 int st_lsm6dsx_set_page(struct st_lsm6dsx_hw *hw, bool enable) 1263 { 1264 const struct st_lsm6dsx_shub_settings *hub_settings; 1265 unsigned int data; 1266 int err; 1267 1268 hub_settings = &hw->settings->shub_settings; 1269 data = ST_LSM6DSX_SHIFT_VAL(enable, hub_settings->page_mux.mask); 1270 err = regmap_update_bits(hw->regmap, hub_settings->page_mux.addr, 1271 hub_settings->page_mux.mask, data); 1272 usleep_range(100, 150); 1273 1274 return err; 1275 } 1276 1277 static int st_lsm6dsx_check_whoami(struct st_lsm6dsx_hw *hw, int id, 1278 const char **name) 1279 { 1280 int err, i, j, data; 1281 1282 for (i = 0; i < ARRAY_SIZE(st_lsm6dsx_sensor_settings); i++) { 1283 for (j = 0; j < ST_LSM6DSX_MAX_ID; j++) { 1284 if (id == st_lsm6dsx_sensor_settings[i].id[j].hw_id) 1285 break; 1286 } 1287 if (j < ST_LSM6DSX_MAX_ID) 1288 break; 1289 } 1290 1291 if (i == ARRAY_SIZE(st_lsm6dsx_sensor_settings)) { 1292 dev_err(hw->dev, "unsupported hw id [%02x]\n", id); 1293 return -ENODEV; 1294 } 1295 1296 err = regmap_read(hw->regmap, ST_LSM6DSX_REG_WHOAMI_ADDR, &data); 1297 if (err < 0) { 1298 dev_err(hw->dev, "failed to read whoami register\n"); 1299 return err; 1300 } 1301 1302 if (data != st_lsm6dsx_sensor_settings[i].wai) { 1303 dev_err(hw->dev, "unsupported whoami [%02x]\n", data); 1304 return -ENODEV; 1305 } 1306 1307 *name = st_lsm6dsx_sensor_settings[i].id[j].name; 1308 hw->settings = &st_lsm6dsx_sensor_settings[i]; 1309 1310 return 0; 1311 } 1312 1313 static int st_lsm6dsx_set_full_scale(struct st_lsm6dsx_sensor *sensor, 1314 u32 gain) 1315 { 1316 const struct st_lsm6dsx_fs_table_entry *fs_table; 1317 unsigned int data; 1318 int i, err; 1319 1320 fs_table = &sensor->hw->settings->fs_table[sensor->id]; 1321 for (i = 0; i < fs_table->fs_len; i++) { 1322 if (fs_table->fs_avl[i].gain == gain) 1323 break; 1324 } 1325 1326 if (i == fs_table->fs_len) 1327 return -EINVAL; 1328 1329 data = ST_LSM6DSX_SHIFT_VAL(fs_table->fs_avl[i].val, 1330 fs_table->reg.mask); 1331 err = st_lsm6dsx_update_bits_locked(sensor->hw, fs_table->reg.addr, 1332 fs_table->reg.mask, data); 1333 if (err < 0) 1334 return err; 1335 1336 sensor->gain = gain; 1337 1338 return 0; 1339 } 1340 1341 int st_lsm6dsx_check_odr(struct st_lsm6dsx_sensor *sensor, u16 odr, u8 *val) 1342 { 1343 const struct st_lsm6dsx_odr_table_entry *odr_table; 1344 int i; 1345 1346 odr_table = &sensor->hw->settings->odr_table[sensor->id]; 1347 for (i = 0; i < ST_LSM6DSX_ODR_LIST_SIZE; i++) 1348 /* 1349 * ext devices can run at different odr respect to 1350 * accel sensor 1351 */ 1352 if (odr_table->odr_avl[i].hz >= odr) 1353 break; 1354 1355 if (i == ST_LSM6DSX_ODR_LIST_SIZE) 1356 return -EINVAL; 1357 1358 *val = odr_table->odr_avl[i].val; 1359 1360 return 0; 1361 } 1362 1363 static u16 st_lsm6dsx_check_odr_dependency(struct st_lsm6dsx_hw *hw, u16 odr, 1364 enum st_lsm6dsx_sensor_id id) 1365 { 1366 struct st_lsm6dsx_sensor *ref = iio_priv(hw->iio_devs[id]); 1367 1368 if (odr > 0) { 1369 if (hw->enable_mask & BIT(id)) 1370 return max_t(u16, ref->odr, odr); 1371 else 1372 return odr; 1373 } else { 1374 return (hw->enable_mask & BIT(id)) ? ref->odr : 0; 1375 } 1376 } 1377 1378 static int st_lsm6dsx_set_odr(struct st_lsm6dsx_sensor *sensor, u16 req_odr) 1379 { 1380 struct st_lsm6dsx_sensor *ref_sensor = sensor; 1381 struct st_lsm6dsx_hw *hw = sensor->hw; 1382 const struct st_lsm6dsx_reg *reg; 1383 unsigned int data; 1384 u8 val = 0; 1385 int err; 1386 1387 switch (sensor->id) { 1388 case ST_LSM6DSX_ID_EXT0: 1389 case ST_LSM6DSX_ID_EXT1: 1390 case ST_LSM6DSX_ID_EXT2: 1391 case ST_LSM6DSX_ID_ACC: { 1392 u16 odr; 1393 int i; 1394 1395 /* 1396 * i2c embedded controller relies on the accelerometer sensor as 1397 * bus read/write trigger so we need to enable accel device 1398 * at odr = max(accel_odr, ext_odr) in order to properly 1399 * communicate with i2c slave devices 1400 */ 1401 ref_sensor = iio_priv(hw->iio_devs[ST_LSM6DSX_ID_ACC]); 1402 for (i = ST_LSM6DSX_ID_ACC; i < ST_LSM6DSX_ID_MAX; i++) { 1403 if (!hw->iio_devs[i] || i == sensor->id) 1404 continue; 1405 1406 odr = st_lsm6dsx_check_odr_dependency(hw, req_odr, i); 1407 if (odr != req_odr) 1408 /* device already configured */ 1409 return 0; 1410 } 1411 break; 1412 } 1413 default: 1414 break; 1415 } 1416 1417 if (req_odr > 0) { 1418 err = st_lsm6dsx_check_odr(ref_sensor, req_odr, &val); 1419 if (err < 0) 1420 return err; 1421 } 1422 1423 reg = &hw->settings->odr_table[ref_sensor->id].reg; 1424 data = ST_LSM6DSX_SHIFT_VAL(val, reg->mask); 1425 return st_lsm6dsx_update_bits_locked(hw, reg->addr, reg->mask, data); 1426 } 1427 1428 int st_lsm6dsx_sensor_set_enable(struct st_lsm6dsx_sensor *sensor, 1429 bool enable) 1430 { 1431 struct st_lsm6dsx_hw *hw = sensor->hw; 1432 u16 odr = enable ? sensor->odr : 0; 1433 int err; 1434 1435 err = st_lsm6dsx_set_odr(sensor, odr); 1436 if (err < 0) 1437 return err; 1438 1439 if (enable) 1440 hw->enable_mask |= BIT(sensor->id); 1441 else 1442 hw->enable_mask &= ~BIT(sensor->id); 1443 1444 return 0; 1445 } 1446 1447 static int st_lsm6dsx_read_oneshot(struct st_lsm6dsx_sensor *sensor, 1448 u8 addr, int *val) 1449 { 1450 struct st_lsm6dsx_hw *hw = sensor->hw; 1451 int err, delay; 1452 __le16 data; 1453 1454 err = st_lsm6dsx_sensor_set_enable(sensor, true); 1455 if (err < 0) 1456 return err; 1457 1458 delay = 1000000 / sensor->odr; 1459 usleep_range(delay, 2 * delay); 1460 1461 err = st_lsm6dsx_read_locked(hw, addr, &data, sizeof(data)); 1462 if (err < 0) 1463 return err; 1464 1465 if (!hw->enable_event) 1466 st_lsm6dsx_sensor_set_enable(sensor, false); 1467 1468 *val = (s16)le16_to_cpu(data); 1469 1470 return IIO_VAL_INT; 1471 } 1472 1473 static int st_lsm6dsx_read_raw(struct iio_dev *iio_dev, 1474 struct iio_chan_spec const *ch, 1475 int *val, int *val2, long mask) 1476 { 1477 struct st_lsm6dsx_sensor *sensor = iio_priv(iio_dev); 1478 int ret; 1479 1480 switch (mask) { 1481 case IIO_CHAN_INFO_RAW: 1482 ret = iio_device_claim_direct_mode(iio_dev); 1483 if (ret) 1484 break; 1485 1486 ret = st_lsm6dsx_read_oneshot(sensor, ch->address, val); 1487 iio_device_release_direct_mode(iio_dev); 1488 break; 1489 case IIO_CHAN_INFO_SAMP_FREQ: 1490 *val = sensor->odr; 1491 ret = IIO_VAL_INT; 1492 break; 1493 case IIO_CHAN_INFO_SCALE: 1494 *val = 0; 1495 *val2 = sensor->gain; 1496 ret = IIO_VAL_INT_PLUS_MICRO; 1497 break; 1498 default: 1499 ret = -EINVAL; 1500 break; 1501 } 1502 1503 return ret; 1504 } 1505 1506 static int st_lsm6dsx_write_raw(struct iio_dev *iio_dev, 1507 struct iio_chan_spec const *chan, 1508 int val, int val2, long mask) 1509 { 1510 struct st_lsm6dsx_sensor *sensor = iio_priv(iio_dev); 1511 int err; 1512 1513 err = iio_device_claim_direct_mode(iio_dev); 1514 if (err) 1515 return err; 1516 1517 switch (mask) { 1518 case IIO_CHAN_INFO_SCALE: 1519 err = st_lsm6dsx_set_full_scale(sensor, val2); 1520 break; 1521 case IIO_CHAN_INFO_SAMP_FREQ: { 1522 u8 data; 1523 1524 err = st_lsm6dsx_check_odr(sensor, val, &data); 1525 if (!err) 1526 sensor->odr = val; 1527 break; 1528 } 1529 default: 1530 err = -EINVAL; 1531 break; 1532 } 1533 1534 iio_device_release_direct_mode(iio_dev); 1535 1536 return err; 1537 } 1538 1539 static int st_lsm6dsx_event_setup(struct st_lsm6dsx_hw *hw, int state) 1540 { 1541 const struct st_lsm6dsx_reg *reg; 1542 unsigned int data; 1543 int err; 1544 1545 if (!hw->settings->irq_config.irq1_func.addr) 1546 return -ENOTSUPP; 1547 1548 reg = &hw->settings->event_settings.enable_reg; 1549 if (reg->addr) { 1550 data = ST_LSM6DSX_SHIFT_VAL(state, reg->mask); 1551 err = st_lsm6dsx_update_bits_locked(hw, reg->addr, 1552 reg->mask, data); 1553 if (err < 0) 1554 return err; 1555 } 1556 1557 /* Enable wakeup interrupt */ 1558 data = ST_LSM6DSX_SHIFT_VAL(state, hw->irq_routing->mask); 1559 return st_lsm6dsx_update_bits_locked(hw, hw->irq_routing->addr, 1560 hw->irq_routing->mask, data); 1561 } 1562 1563 static int st_lsm6dsx_read_event(struct iio_dev *iio_dev, 1564 const struct iio_chan_spec *chan, 1565 enum iio_event_type type, 1566 enum iio_event_direction dir, 1567 enum iio_event_info info, 1568 int *val, int *val2) 1569 { 1570 struct st_lsm6dsx_sensor *sensor = iio_priv(iio_dev); 1571 struct st_lsm6dsx_hw *hw = sensor->hw; 1572 1573 if (type != IIO_EV_TYPE_THRESH) 1574 return -EINVAL; 1575 1576 *val2 = 0; 1577 *val = hw->event_threshold; 1578 1579 return IIO_VAL_INT; 1580 } 1581 1582 static int 1583 st_lsm6dsx_write_event(struct iio_dev *iio_dev, 1584 const struct iio_chan_spec *chan, 1585 enum iio_event_type type, 1586 enum iio_event_direction dir, 1587 enum iio_event_info info, 1588 int val, int val2) 1589 { 1590 struct st_lsm6dsx_sensor *sensor = iio_priv(iio_dev); 1591 struct st_lsm6dsx_hw *hw = sensor->hw; 1592 const struct st_lsm6dsx_reg *reg; 1593 unsigned int data; 1594 int err; 1595 1596 if (type != IIO_EV_TYPE_THRESH) 1597 return -EINVAL; 1598 1599 if (val < 0 || val > 31) 1600 return -EINVAL; 1601 1602 reg = &hw->settings->event_settings.wakeup_reg; 1603 data = ST_LSM6DSX_SHIFT_VAL(val, reg->mask); 1604 err = st_lsm6dsx_update_bits_locked(hw, reg->addr, 1605 reg->mask, data); 1606 if (err < 0) 1607 return -EINVAL; 1608 1609 hw->event_threshold = val; 1610 1611 return 0; 1612 } 1613 1614 static int 1615 st_lsm6dsx_read_event_config(struct iio_dev *iio_dev, 1616 const struct iio_chan_spec *chan, 1617 enum iio_event_type type, 1618 enum iio_event_direction dir) 1619 { 1620 struct st_lsm6dsx_sensor *sensor = iio_priv(iio_dev); 1621 struct st_lsm6dsx_hw *hw = sensor->hw; 1622 1623 if (type != IIO_EV_TYPE_THRESH) 1624 return -EINVAL; 1625 1626 return !!(hw->enable_event & BIT(chan->channel2)); 1627 } 1628 1629 static int 1630 st_lsm6dsx_write_event_config(struct iio_dev *iio_dev, 1631 const struct iio_chan_spec *chan, 1632 enum iio_event_type type, 1633 enum iio_event_direction dir, int state) 1634 { 1635 struct st_lsm6dsx_sensor *sensor = iio_priv(iio_dev); 1636 struct st_lsm6dsx_hw *hw = sensor->hw; 1637 u8 enable_event; 1638 int err = 0; 1639 1640 if (type != IIO_EV_TYPE_THRESH) 1641 return -EINVAL; 1642 1643 if (state) { 1644 enable_event = hw->enable_event | BIT(chan->channel2); 1645 1646 /* do not enable events if they are already enabled */ 1647 if (hw->enable_event) 1648 goto out; 1649 } else { 1650 enable_event = hw->enable_event & ~BIT(chan->channel2); 1651 1652 /* only turn off sensor if no events is enabled */ 1653 if (enable_event) 1654 goto out; 1655 } 1656 1657 /* stop here if no changes have been made */ 1658 if (hw->enable_event == enable_event) 1659 return 0; 1660 1661 err = st_lsm6dsx_event_setup(hw, state); 1662 if (err < 0) 1663 return err; 1664 1665 mutex_lock(&hw->conf_lock); 1666 err = st_lsm6dsx_sensor_set_enable(sensor, state); 1667 mutex_unlock(&hw->conf_lock); 1668 if (err < 0) 1669 return err; 1670 1671 out: 1672 hw->enable_event = enable_event; 1673 1674 return 0; 1675 } 1676 1677 int st_lsm6dsx_set_watermark(struct iio_dev *iio_dev, unsigned int val) 1678 { 1679 struct st_lsm6dsx_sensor *sensor = iio_priv(iio_dev); 1680 struct st_lsm6dsx_hw *hw = sensor->hw; 1681 int err; 1682 1683 if (val < 1 || val > hw->settings->max_fifo_size) 1684 return -EINVAL; 1685 1686 mutex_lock(&hw->conf_lock); 1687 1688 err = st_lsm6dsx_update_watermark(sensor, val); 1689 1690 mutex_unlock(&hw->conf_lock); 1691 1692 if (err < 0) 1693 return err; 1694 1695 sensor->watermark = val; 1696 1697 return 0; 1698 } 1699 1700 static ssize_t 1701 st_lsm6dsx_sysfs_sampling_frequency_avail(struct device *dev, 1702 struct device_attribute *attr, 1703 char *buf) 1704 { 1705 struct st_lsm6dsx_sensor *sensor = iio_priv(dev_get_drvdata(dev)); 1706 enum st_lsm6dsx_sensor_id id = sensor->id; 1707 struct st_lsm6dsx_hw *hw = sensor->hw; 1708 int i, len = 0; 1709 1710 for (i = 0; i < ST_LSM6DSX_ODR_LIST_SIZE; i++) 1711 len += scnprintf(buf + len, PAGE_SIZE - len, "%d ", 1712 hw->settings->odr_table[id].odr_avl[i].hz); 1713 buf[len - 1] = '\n'; 1714 1715 return len; 1716 } 1717 1718 static ssize_t st_lsm6dsx_sysfs_scale_avail(struct device *dev, 1719 struct device_attribute *attr, 1720 char *buf) 1721 { 1722 struct st_lsm6dsx_sensor *sensor = iio_priv(dev_get_drvdata(dev)); 1723 const struct st_lsm6dsx_fs_table_entry *fs_table; 1724 struct st_lsm6dsx_hw *hw = sensor->hw; 1725 int i, len = 0; 1726 1727 fs_table = &hw->settings->fs_table[sensor->id]; 1728 for (i = 0; i < fs_table->fs_len; i++) 1729 len += scnprintf(buf + len, PAGE_SIZE - len, "0.%06u ", 1730 fs_table->fs_avl[i].gain); 1731 buf[len - 1] = '\n'; 1732 1733 return len; 1734 } 1735 1736 static IIO_DEV_ATTR_SAMP_FREQ_AVAIL(st_lsm6dsx_sysfs_sampling_frequency_avail); 1737 static IIO_DEVICE_ATTR(in_accel_scale_available, 0444, 1738 st_lsm6dsx_sysfs_scale_avail, NULL, 0); 1739 static IIO_DEVICE_ATTR(in_anglvel_scale_available, 0444, 1740 st_lsm6dsx_sysfs_scale_avail, NULL, 0); 1741 1742 static struct attribute *st_lsm6dsx_acc_attributes[] = { 1743 &iio_dev_attr_sampling_frequency_available.dev_attr.attr, 1744 &iio_dev_attr_in_accel_scale_available.dev_attr.attr, 1745 NULL, 1746 }; 1747 1748 static const struct attribute_group st_lsm6dsx_acc_attribute_group = { 1749 .attrs = st_lsm6dsx_acc_attributes, 1750 }; 1751 1752 static const struct iio_info st_lsm6dsx_acc_info = { 1753 .attrs = &st_lsm6dsx_acc_attribute_group, 1754 .read_raw = st_lsm6dsx_read_raw, 1755 .write_raw = st_lsm6dsx_write_raw, 1756 .read_event_value = st_lsm6dsx_read_event, 1757 .write_event_value = st_lsm6dsx_write_event, 1758 .read_event_config = st_lsm6dsx_read_event_config, 1759 .write_event_config = st_lsm6dsx_write_event_config, 1760 .hwfifo_set_watermark = st_lsm6dsx_set_watermark, 1761 }; 1762 1763 static struct attribute *st_lsm6dsx_gyro_attributes[] = { 1764 &iio_dev_attr_sampling_frequency_available.dev_attr.attr, 1765 &iio_dev_attr_in_anglvel_scale_available.dev_attr.attr, 1766 NULL, 1767 }; 1768 1769 static const struct attribute_group st_lsm6dsx_gyro_attribute_group = { 1770 .attrs = st_lsm6dsx_gyro_attributes, 1771 }; 1772 1773 static const struct iio_info st_lsm6dsx_gyro_info = { 1774 .attrs = &st_lsm6dsx_gyro_attribute_group, 1775 .read_raw = st_lsm6dsx_read_raw, 1776 .write_raw = st_lsm6dsx_write_raw, 1777 .hwfifo_set_watermark = st_lsm6dsx_set_watermark, 1778 }; 1779 1780 static int st_lsm6dsx_of_get_drdy_pin(struct st_lsm6dsx_hw *hw, int *drdy_pin) 1781 { 1782 struct device_node *np = hw->dev->of_node; 1783 1784 if (!np) 1785 return -EINVAL; 1786 1787 return of_property_read_u32(np, "st,drdy-int-pin", drdy_pin); 1788 } 1789 1790 static int 1791 st_lsm6dsx_get_drdy_reg(struct st_lsm6dsx_hw *hw, 1792 const struct st_lsm6dsx_reg **drdy_reg) 1793 { 1794 int err = 0, drdy_pin; 1795 1796 if (st_lsm6dsx_of_get_drdy_pin(hw, &drdy_pin) < 0) { 1797 struct st_sensors_platform_data *pdata; 1798 struct device *dev = hw->dev; 1799 1800 pdata = (struct st_sensors_platform_data *)dev->platform_data; 1801 drdy_pin = pdata ? pdata->drdy_int_pin : 1; 1802 } 1803 1804 switch (drdy_pin) { 1805 case 1: 1806 hw->irq_routing = &hw->settings->irq_config.irq1_func; 1807 *drdy_reg = &hw->settings->irq_config.irq1; 1808 break; 1809 case 2: 1810 hw->irq_routing = &hw->settings->irq_config.irq2_func; 1811 *drdy_reg = &hw->settings->irq_config.irq2; 1812 break; 1813 default: 1814 dev_err(hw->dev, "unsupported data ready pin\n"); 1815 err = -EINVAL; 1816 break; 1817 } 1818 1819 return err; 1820 } 1821 1822 static int st_lsm6dsx_init_shub(struct st_lsm6dsx_hw *hw) 1823 { 1824 const struct st_lsm6dsx_shub_settings *hub_settings; 1825 struct device_node *np = hw->dev->of_node; 1826 struct st_sensors_platform_data *pdata; 1827 unsigned int data; 1828 int err = 0; 1829 1830 hub_settings = &hw->settings->shub_settings; 1831 1832 pdata = (struct st_sensors_platform_data *)hw->dev->platform_data; 1833 if ((np && of_property_read_bool(np, "st,pullups")) || 1834 (pdata && pdata->pullups)) { 1835 err = st_lsm6dsx_set_page(hw, true); 1836 if (err < 0) 1837 return err; 1838 1839 data = ST_LSM6DSX_SHIFT_VAL(1, hub_settings->pullup_en.mask); 1840 err = regmap_update_bits(hw->regmap, 1841 hub_settings->pullup_en.addr, 1842 hub_settings->pullup_en.mask, data); 1843 1844 st_lsm6dsx_set_page(hw, false); 1845 1846 if (err < 0) 1847 return err; 1848 } 1849 1850 if (hub_settings->aux_sens.addr) { 1851 /* configure aux sensors */ 1852 err = st_lsm6dsx_set_page(hw, true); 1853 if (err < 0) 1854 return err; 1855 1856 data = ST_LSM6DSX_SHIFT_VAL(3, hub_settings->aux_sens.mask); 1857 err = regmap_update_bits(hw->regmap, 1858 hub_settings->aux_sens.addr, 1859 hub_settings->aux_sens.mask, data); 1860 1861 st_lsm6dsx_set_page(hw, false); 1862 } 1863 1864 return err; 1865 } 1866 1867 static int st_lsm6dsx_init_hw_timer(struct st_lsm6dsx_hw *hw) 1868 { 1869 const struct st_lsm6dsx_hw_ts_settings *ts_settings; 1870 int err, val; 1871 1872 ts_settings = &hw->settings->ts_settings; 1873 /* enable hw timestamp generation if necessary */ 1874 if (ts_settings->timer_en.addr) { 1875 val = ST_LSM6DSX_SHIFT_VAL(1, ts_settings->timer_en.mask); 1876 err = regmap_update_bits(hw->regmap, 1877 ts_settings->timer_en.addr, 1878 ts_settings->timer_en.mask, val); 1879 if (err < 0) 1880 return err; 1881 } 1882 1883 /* enable high resolution for hw ts timer if necessary */ 1884 if (ts_settings->hr_timer.addr) { 1885 val = ST_LSM6DSX_SHIFT_VAL(1, ts_settings->hr_timer.mask); 1886 err = regmap_update_bits(hw->regmap, 1887 ts_settings->hr_timer.addr, 1888 ts_settings->hr_timer.mask, val); 1889 if (err < 0) 1890 return err; 1891 } 1892 1893 /* enable ts queueing in FIFO if necessary */ 1894 if (ts_settings->fifo_en.addr) { 1895 val = ST_LSM6DSX_SHIFT_VAL(1, ts_settings->fifo_en.mask); 1896 err = regmap_update_bits(hw->regmap, 1897 ts_settings->fifo_en.addr, 1898 ts_settings->fifo_en.mask, val); 1899 if (err < 0) 1900 return err; 1901 } 1902 1903 /* calibrate timestamp sensitivity */ 1904 hw->ts_gain = ST_LSM6DSX_TS_SENSITIVITY; 1905 if (ts_settings->freq_fine) { 1906 err = regmap_read(hw->regmap, ts_settings->freq_fine, &val); 1907 if (err < 0) 1908 return err; 1909 1910 /* 1911 * linearize the AN5192 formula: 1912 * 1 / (1 + x) ~= 1 - x (Taylor’s Series) 1913 * ttrim[s] = 1 / (40000 * (1 + 0.0015 * val)) 1914 * ttrim[ns] ~= 25000 - 37.5 * val 1915 * ttrim[ns] ~= 25000 - (37500 * val) / 1000 1916 */ 1917 hw->ts_gain -= ((s8)val * 37500) / 1000; 1918 } 1919 1920 return 0; 1921 } 1922 1923 static int st_lsm6dsx_init_device(struct st_lsm6dsx_hw *hw) 1924 { 1925 const struct st_lsm6dsx_reg *reg; 1926 int err; 1927 1928 /* device sw reset */ 1929 reg = &hw->settings->reset; 1930 err = regmap_update_bits(hw->regmap, reg->addr, reg->mask, 1931 ST_LSM6DSX_SHIFT_VAL(1, reg->mask)); 1932 if (err < 0) 1933 return err; 1934 1935 msleep(50); 1936 1937 /* reload trimming parameter */ 1938 reg = &hw->settings->boot; 1939 err = regmap_update_bits(hw->regmap, reg->addr, reg->mask, 1940 ST_LSM6DSX_SHIFT_VAL(1, reg->mask)); 1941 if (err < 0) 1942 return err; 1943 1944 msleep(50); 1945 1946 /* enable Block Data Update */ 1947 reg = &hw->settings->bdu; 1948 err = regmap_update_bits(hw->regmap, reg->addr, reg->mask, 1949 ST_LSM6DSX_SHIFT_VAL(1, reg->mask)); 1950 if (err < 0) 1951 return err; 1952 1953 /* enable FIFO watermak interrupt */ 1954 err = st_lsm6dsx_get_drdy_reg(hw, ®); 1955 if (err < 0) 1956 return err; 1957 1958 err = regmap_update_bits(hw->regmap, reg->addr, reg->mask, 1959 ST_LSM6DSX_SHIFT_VAL(1, reg->mask)); 1960 if (err < 0) 1961 return err; 1962 1963 /* enable Latched interrupts for device events */ 1964 if (hw->settings->irq_config.lir.addr) { 1965 reg = &hw->settings->irq_config.lir; 1966 err = regmap_update_bits(hw->regmap, reg->addr, reg->mask, 1967 ST_LSM6DSX_SHIFT_VAL(1, reg->mask)); 1968 if (err < 0) 1969 return err; 1970 1971 /* enable clear on read for latched interrupts */ 1972 if (hw->settings->irq_config.clear_on_read.addr) { 1973 reg = &hw->settings->irq_config.clear_on_read; 1974 err = regmap_update_bits(hw->regmap, 1975 reg->addr, reg->mask, 1976 ST_LSM6DSX_SHIFT_VAL(1, reg->mask)); 1977 if (err < 0) 1978 return err; 1979 } 1980 } 1981 1982 /* enable drdy-mas if available */ 1983 if (hw->settings->drdy_mask.addr) { 1984 reg = &hw->settings->drdy_mask; 1985 err = regmap_update_bits(hw->regmap, reg->addr, reg->mask, 1986 ST_LSM6DSX_SHIFT_VAL(1, reg->mask)); 1987 if (err < 0) 1988 return err; 1989 } 1990 1991 err = st_lsm6dsx_init_shub(hw); 1992 if (err < 0) 1993 return err; 1994 1995 return st_lsm6dsx_init_hw_timer(hw); 1996 } 1997 1998 static struct iio_dev *st_lsm6dsx_alloc_iiodev(struct st_lsm6dsx_hw *hw, 1999 enum st_lsm6dsx_sensor_id id, 2000 const char *name) 2001 { 2002 struct st_lsm6dsx_sensor *sensor; 2003 struct iio_dev *iio_dev; 2004 2005 iio_dev = devm_iio_device_alloc(hw->dev, sizeof(*sensor)); 2006 if (!iio_dev) 2007 return NULL; 2008 2009 iio_dev->modes = INDIO_DIRECT_MODE; 2010 iio_dev->dev.parent = hw->dev; 2011 iio_dev->available_scan_masks = st_lsm6dsx_available_scan_masks; 2012 iio_dev->channels = hw->settings->channels[id].chan; 2013 iio_dev->num_channels = hw->settings->channels[id].len; 2014 2015 sensor = iio_priv(iio_dev); 2016 sensor->id = id; 2017 sensor->hw = hw; 2018 sensor->odr = hw->settings->odr_table[id].odr_avl[0].hz; 2019 sensor->gain = hw->settings->fs_table[id].fs_avl[0].gain; 2020 sensor->watermark = 1; 2021 2022 switch (id) { 2023 case ST_LSM6DSX_ID_ACC: 2024 iio_dev->info = &st_lsm6dsx_acc_info; 2025 scnprintf(sensor->name, sizeof(sensor->name), "%s_accel", 2026 name); 2027 break; 2028 case ST_LSM6DSX_ID_GYRO: 2029 iio_dev->info = &st_lsm6dsx_gyro_info; 2030 scnprintf(sensor->name, sizeof(sensor->name), "%s_gyro", 2031 name); 2032 break; 2033 default: 2034 return NULL; 2035 } 2036 iio_dev->name = sensor->name; 2037 2038 return iio_dev; 2039 } 2040 2041 static bool 2042 st_lsm6dsx_report_motion_event(struct st_lsm6dsx_hw *hw) 2043 { 2044 const struct st_lsm6dsx_event_settings *event_settings; 2045 int err, data; 2046 s64 timestamp; 2047 2048 if (!hw->enable_event) 2049 return false; 2050 2051 event_settings = &hw->settings->event_settings; 2052 err = st_lsm6dsx_read_locked(hw, event_settings->wakeup_src_reg, 2053 &data, sizeof(data)); 2054 if (err < 0) 2055 return false; 2056 2057 timestamp = iio_get_time_ns(hw->iio_devs[ST_LSM6DSX_ID_ACC]); 2058 if ((data & hw->settings->event_settings.wakeup_src_z_mask) && 2059 (hw->enable_event & BIT(IIO_MOD_Z))) 2060 iio_push_event(hw->iio_devs[ST_LSM6DSX_ID_ACC], 2061 IIO_MOD_EVENT_CODE(IIO_ACCEL, 2062 0, 2063 IIO_MOD_Z, 2064 IIO_EV_TYPE_THRESH, 2065 IIO_EV_DIR_EITHER), 2066 timestamp); 2067 2068 if ((data & hw->settings->event_settings.wakeup_src_y_mask) && 2069 (hw->enable_event & BIT(IIO_MOD_Y))) 2070 iio_push_event(hw->iio_devs[ST_LSM6DSX_ID_ACC], 2071 IIO_MOD_EVENT_CODE(IIO_ACCEL, 2072 0, 2073 IIO_MOD_Y, 2074 IIO_EV_TYPE_THRESH, 2075 IIO_EV_DIR_EITHER), 2076 timestamp); 2077 2078 if ((data & hw->settings->event_settings.wakeup_src_x_mask) && 2079 (hw->enable_event & BIT(IIO_MOD_X))) 2080 iio_push_event(hw->iio_devs[ST_LSM6DSX_ID_ACC], 2081 IIO_MOD_EVENT_CODE(IIO_ACCEL, 2082 0, 2083 IIO_MOD_X, 2084 IIO_EV_TYPE_THRESH, 2085 IIO_EV_DIR_EITHER), 2086 timestamp); 2087 2088 return data & event_settings->wakeup_src_status_mask; 2089 } 2090 2091 static irqreturn_t st_lsm6dsx_handler_thread(int irq, void *private) 2092 { 2093 struct st_lsm6dsx_hw *hw = private; 2094 bool event; 2095 int count; 2096 2097 event = st_lsm6dsx_report_motion_event(hw); 2098 2099 if (!hw->settings->fifo_ops.read_fifo) 2100 return event ? IRQ_HANDLED : IRQ_NONE; 2101 2102 mutex_lock(&hw->fifo_lock); 2103 count = hw->settings->fifo_ops.read_fifo(hw); 2104 mutex_unlock(&hw->fifo_lock); 2105 2106 return count || event ? IRQ_HANDLED : IRQ_NONE; 2107 } 2108 2109 static int st_lsm6dsx_irq_setup(struct st_lsm6dsx_hw *hw) 2110 { 2111 struct device_node *np = hw->dev->of_node; 2112 struct st_sensors_platform_data *pdata; 2113 const struct st_lsm6dsx_reg *reg; 2114 unsigned long irq_type; 2115 bool irq_active_low; 2116 int err; 2117 2118 irq_type = irqd_get_trigger_type(irq_get_irq_data(hw->irq)); 2119 2120 switch (irq_type) { 2121 case IRQF_TRIGGER_HIGH: 2122 case IRQF_TRIGGER_RISING: 2123 irq_active_low = false; 2124 break; 2125 case IRQF_TRIGGER_LOW: 2126 case IRQF_TRIGGER_FALLING: 2127 irq_active_low = true; 2128 break; 2129 default: 2130 dev_info(hw->dev, "mode %lx unsupported\n", irq_type); 2131 return -EINVAL; 2132 } 2133 2134 reg = &hw->settings->irq_config.hla; 2135 err = regmap_update_bits(hw->regmap, reg->addr, reg->mask, 2136 ST_LSM6DSX_SHIFT_VAL(irq_active_low, 2137 reg->mask)); 2138 if (err < 0) 2139 return err; 2140 2141 pdata = (struct st_sensors_platform_data *)hw->dev->platform_data; 2142 if ((np && of_property_read_bool(np, "drive-open-drain")) || 2143 (pdata && pdata->open_drain)) { 2144 reg = &hw->settings->irq_config.od; 2145 err = regmap_update_bits(hw->regmap, reg->addr, reg->mask, 2146 ST_LSM6DSX_SHIFT_VAL(1, reg->mask)); 2147 if (err < 0) 2148 return err; 2149 2150 irq_type |= IRQF_SHARED; 2151 } 2152 2153 err = devm_request_threaded_irq(hw->dev, hw->irq, 2154 NULL, 2155 st_lsm6dsx_handler_thread, 2156 irq_type | IRQF_ONESHOT, 2157 "lsm6dsx", hw); 2158 if (err) { 2159 dev_err(hw->dev, "failed to request trigger irq %d\n", 2160 hw->irq); 2161 return err; 2162 } 2163 2164 return 0; 2165 } 2166 2167 int st_lsm6dsx_probe(struct device *dev, int irq, int hw_id, 2168 struct regmap *regmap) 2169 { 2170 struct st_sensors_platform_data *pdata = dev->platform_data; 2171 const struct st_lsm6dsx_shub_settings *hub_settings; 2172 struct device_node *np = dev->of_node; 2173 struct st_lsm6dsx_hw *hw; 2174 const char *name = NULL; 2175 int i, err; 2176 2177 hw = devm_kzalloc(dev, sizeof(*hw), GFP_KERNEL); 2178 if (!hw) 2179 return -ENOMEM; 2180 2181 dev_set_drvdata(dev, (void *)hw); 2182 2183 mutex_init(&hw->fifo_lock); 2184 mutex_init(&hw->conf_lock); 2185 mutex_init(&hw->page_lock); 2186 2187 hw->buff = devm_kzalloc(dev, ST_LSM6DSX_BUFF_SIZE, GFP_KERNEL); 2188 if (!hw->buff) 2189 return -ENOMEM; 2190 2191 hw->dev = dev; 2192 hw->irq = irq; 2193 hw->regmap = regmap; 2194 2195 err = st_lsm6dsx_check_whoami(hw, hw_id, &name); 2196 if (err < 0) 2197 return err; 2198 2199 for (i = 0; i < ST_LSM6DSX_ID_EXT0; i++) { 2200 hw->iio_devs[i] = st_lsm6dsx_alloc_iiodev(hw, i, name); 2201 if (!hw->iio_devs[i]) 2202 return -ENOMEM; 2203 } 2204 2205 err = st_lsm6dsx_init_device(hw); 2206 if (err < 0) 2207 return err; 2208 2209 hub_settings = &hw->settings->shub_settings; 2210 if (hub_settings->master_en.addr) { 2211 err = st_lsm6dsx_shub_probe(hw, name); 2212 if (err < 0) 2213 return err; 2214 } 2215 2216 if (hw->irq > 0) { 2217 err = st_lsm6dsx_irq_setup(hw); 2218 if (err < 0) 2219 return err; 2220 2221 err = st_lsm6dsx_fifo_setup(hw); 2222 if (err < 0) 2223 return err; 2224 } 2225 2226 for (i = 0; i < ST_LSM6DSX_ID_MAX; i++) { 2227 if (!hw->iio_devs[i]) 2228 continue; 2229 2230 err = devm_iio_device_register(hw->dev, hw->iio_devs[i]); 2231 if (err) 2232 return err; 2233 } 2234 2235 if ((np && of_property_read_bool(np, "wakeup-source")) || 2236 (pdata && pdata->wakeup_source)) 2237 device_init_wakeup(dev, true); 2238 2239 return 0; 2240 } 2241 EXPORT_SYMBOL(st_lsm6dsx_probe); 2242 2243 static int __maybe_unused st_lsm6dsx_suspend(struct device *dev) 2244 { 2245 struct st_lsm6dsx_hw *hw = dev_get_drvdata(dev); 2246 struct st_lsm6dsx_sensor *sensor; 2247 int i, err = 0; 2248 2249 for (i = 0; i < ST_LSM6DSX_ID_MAX; i++) { 2250 if (!hw->iio_devs[i]) 2251 continue; 2252 2253 sensor = iio_priv(hw->iio_devs[i]); 2254 if (!(hw->enable_mask & BIT(sensor->id))) 2255 continue; 2256 2257 if (device_may_wakeup(dev) && 2258 sensor->id == ST_LSM6DSX_ID_ACC && hw->enable_event) { 2259 /* Enable wake from IRQ */ 2260 enable_irq_wake(hw->irq); 2261 continue; 2262 } 2263 2264 if (sensor->id == ST_LSM6DSX_ID_EXT0 || 2265 sensor->id == ST_LSM6DSX_ID_EXT1 || 2266 sensor->id == ST_LSM6DSX_ID_EXT2) 2267 err = st_lsm6dsx_shub_set_enable(sensor, false); 2268 else 2269 err = st_lsm6dsx_sensor_set_enable(sensor, false); 2270 if (err < 0) 2271 return err; 2272 2273 hw->suspend_mask |= BIT(sensor->id); 2274 } 2275 2276 if (hw->fifo_mode != ST_LSM6DSX_FIFO_BYPASS) 2277 err = st_lsm6dsx_flush_fifo(hw); 2278 2279 return err; 2280 } 2281 2282 static int __maybe_unused st_lsm6dsx_resume(struct device *dev) 2283 { 2284 struct st_lsm6dsx_hw *hw = dev_get_drvdata(dev); 2285 struct st_lsm6dsx_sensor *sensor; 2286 int i, err = 0; 2287 2288 for (i = 0; i < ST_LSM6DSX_ID_MAX; i++) { 2289 if (!hw->iio_devs[i]) 2290 continue; 2291 2292 sensor = iio_priv(hw->iio_devs[i]); 2293 if (device_may_wakeup(dev) && 2294 sensor->id == ST_LSM6DSX_ID_ACC && hw->enable_event) 2295 disable_irq_wake(hw->irq); 2296 2297 if (!(hw->suspend_mask & BIT(sensor->id))) 2298 continue; 2299 2300 if (sensor->id == ST_LSM6DSX_ID_EXT0 || 2301 sensor->id == ST_LSM6DSX_ID_EXT1 || 2302 sensor->id == ST_LSM6DSX_ID_EXT2) 2303 err = st_lsm6dsx_shub_set_enable(sensor, true); 2304 else 2305 err = st_lsm6dsx_sensor_set_enable(sensor, true); 2306 if (err < 0) 2307 return err; 2308 2309 hw->suspend_mask &= ~BIT(sensor->id); 2310 } 2311 2312 if (hw->enable_mask) 2313 err = st_lsm6dsx_set_fifo_mode(hw, ST_LSM6DSX_FIFO_CONT); 2314 2315 return err; 2316 } 2317 2318 const struct dev_pm_ops st_lsm6dsx_pm_ops = { 2319 SET_SYSTEM_SLEEP_PM_OPS(st_lsm6dsx_suspend, st_lsm6dsx_resume) 2320 }; 2321 EXPORT_SYMBOL(st_lsm6dsx_pm_ops); 2322 2323 MODULE_AUTHOR("Lorenzo Bianconi <lorenzo.bianconi@st.com>"); 2324 MODULE_AUTHOR("Denis Ciocca <denis.ciocca@st.com>"); 2325 MODULE_DESCRIPTION("STMicroelectronics st_lsm6dsx driver"); 2326 MODULE_LICENSE("GPL v2"); 2327