1 // SPDX-License-Identifier: GPL-2.0-only 2 /* 3 * STMicroelectronics st_lsm6dsx sensor driver 4 * 5 * The ST LSM6DSx IMU MEMS series consists of 3D digital accelerometer 6 * and 3D digital gyroscope system-in-package with a digital I2C/SPI serial 7 * interface standard output. 8 * LSM6DSx IMU MEMS series has a dynamic user-selectable full-scale 9 * acceleration range of +-2/+-4/+-8/+-16 g and an angular rate range of 10 * +-125/+-245/+-500/+-1000/+-2000 dps 11 * LSM6DSx series has an integrated First-In-First-Out (FIFO) buffer 12 * allowing dynamic batching of sensor data. 13 * LSM9DSx series is similar but includes an additional magnetometer, handled 14 * by a different driver. 15 * 16 * Supported sensors: 17 * - LSM6DS3: 18 * - Accelerometer/Gyroscope supported ODR [Hz]: 12.5, 26, 52, 104, 208, 416 19 * - Accelerometer supported full-scale [g]: +-2/+-4/+-8/+-16 20 * - Gyroscope supported full-scale [dps]: +-125/+-245/+-500/+-1000/+-2000 21 * - FIFO size: 8KB 22 * 23 * - LSM6DS3H/LSM6DSL/LSM6DSM/ISM330DLC/LSM6DS3TR-C: 24 * - Accelerometer/Gyroscope supported ODR [Hz]: 12.5, 26, 52, 104, 208, 416 25 * - Accelerometer supported full-scale [g]: +-2/+-4/+-8/+-16 26 * - Gyroscope supported full-scale [dps]: +-125/+-245/+-500/+-1000/+-2000 27 * - FIFO size: 4KB 28 * 29 * - LSM6DSO/LSM6DSOX/ASM330LHH/LSM6DSR/ISM330DHCX/LSM6DST/LSM6DSOP: 30 * - Accelerometer/Gyroscope supported ODR [Hz]: 12.5, 26, 52, 104, 208, 416, 31 * 833 32 * - Accelerometer supported full-scale [g]: +-2/+-4/+-8/+-16 33 * - Gyroscope supported full-scale [dps]: +-125/+-245/+-500/+-1000/+-2000 34 * - FIFO size: 3KB 35 * 36 * - LSM9DS1/LSM6DS0: 37 * - Accelerometer supported ODR [Hz]: 10, 50, 119, 238, 476, 952 38 * - Accelerometer supported full-scale [g]: +-2/+-4/+-8/+-16 39 * - Gyroscope supported ODR [Hz]: 15, 60, 119, 238, 476, 952 40 * - Gyroscope supported full-scale [dps]: +-245/+-500/+-2000 41 * - FIFO size: 32 42 * 43 * Copyright 2016 STMicroelectronics Inc. 44 * 45 * Lorenzo Bianconi <lorenzo.bianconi@st.com> 46 * Denis Ciocca <denis.ciocca@st.com> 47 */ 48 49 #include <linux/kernel.h> 50 #include <linux/module.h> 51 #include <linux/delay.h> 52 #include <linux/iio/events.h> 53 #include <linux/iio/iio.h> 54 #include <linux/iio/sysfs.h> 55 #include <linux/interrupt.h> 56 #include <linux/irq.h> 57 #include <linux/pm.h> 58 #include <linux/property.h> 59 #include <linux/regmap.h> 60 #include <linux/bitfield.h> 61 62 #include <linux/platform_data/st_sensors_pdata.h> 63 64 #include "st_lsm6dsx.h" 65 66 #define ST_LSM6DSX_REG_WHOAMI_ADDR 0x0f 67 68 #define ST_LSM6DSX_TS_SENSITIVITY 25000UL /* 25us */ 69 70 static const struct iio_chan_spec st_lsm6dsx_acc_channels[] = { 71 ST_LSM6DSX_CHANNEL_ACC(IIO_ACCEL, 0x28, IIO_MOD_X, 0), 72 ST_LSM6DSX_CHANNEL_ACC(IIO_ACCEL, 0x2a, IIO_MOD_Y, 1), 73 ST_LSM6DSX_CHANNEL_ACC(IIO_ACCEL, 0x2c, IIO_MOD_Z, 2), 74 IIO_CHAN_SOFT_TIMESTAMP(3), 75 }; 76 77 static const struct iio_chan_spec st_lsm6dsx_gyro_channels[] = { 78 ST_LSM6DSX_CHANNEL(IIO_ANGL_VEL, 0x22, IIO_MOD_X, 0), 79 ST_LSM6DSX_CHANNEL(IIO_ANGL_VEL, 0x24, IIO_MOD_Y, 1), 80 ST_LSM6DSX_CHANNEL(IIO_ANGL_VEL, 0x26, IIO_MOD_Z, 2), 81 IIO_CHAN_SOFT_TIMESTAMP(3), 82 }; 83 84 static const struct iio_chan_spec st_lsm6ds0_gyro_channels[] = { 85 ST_LSM6DSX_CHANNEL(IIO_ANGL_VEL, 0x18, IIO_MOD_X, 0), 86 ST_LSM6DSX_CHANNEL(IIO_ANGL_VEL, 0x1a, IIO_MOD_Y, 1), 87 ST_LSM6DSX_CHANNEL(IIO_ANGL_VEL, 0x1c, IIO_MOD_Z, 2), 88 IIO_CHAN_SOFT_TIMESTAMP(3), 89 }; 90 91 static const struct st_lsm6dsx_settings st_lsm6dsx_sensor_settings[] = { 92 { 93 .reset = { 94 .addr = 0x22, 95 .mask = BIT(0), 96 }, 97 .boot = { 98 .addr = 0x22, 99 .mask = BIT(7), 100 }, 101 .bdu = { 102 .addr = 0x22, 103 .mask = BIT(6), 104 }, 105 .id = { 106 { 107 .hw_id = ST_LSM9DS1_ID, 108 .name = ST_LSM9DS1_DEV_NAME, 109 .wai = 0x68, 110 }, { 111 .hw_id = ST_LSM6DS0_ID, 112 .name = ST_LSM6DS0_DEV_NAME, 113 .wai = 0x68, 114 }, 115 }, 116 .channels = { 117 [ST_LSM6DSX_ID_ACC] = { 118 .chan = st_lsm6dsx_acc_channels, 119 .len = ARRAY_SIZE(st_lsm6dsx_acc_channels), 120 }, 121 [ST_LSM6DSX_ID_GYRO] = { 122 .chan = st_lsm6ds0_gyro_channels, 123 .len = ARRAY_SIZE(st_lsm6ds0_gyro_channels), 124 }, 125 }, 126 .odr_table = { 127 [ST_LSM6DSX_ID_ACC] = { 128 .reg = { 129 .addr = 0x20, 130 .mask = GENMASK(7, 5), 131 }, 132 .odr_avl[0] = { 10000, 0x01 }, 133 .odr_avl[1] = { 50000, 0x02 }, 134 .odr_avl[2] = { 119000, 0x03 }, 135 .odr_avl[3] = { 238000, 0x04 }, 136 .odr_avl[4] = { 476000, 0x05 }, 137 .odr_avl[5] = { 952000, 0x06 }, 138 .odr_len = 6, 139 }, 140 [ST_LSM6DSX_ID_GYRO] = { 141 .reg = { 142 .addr = 0x10, 143 .mask = GENMASK(7, 5), 144 }, 145 .odr_avl[0] = { 14900, 0x01 }, 146 .odr_avl[1] = { 59500, 0x02 }, 147 .odr_avl[2] = { 119000, 0x03 }, 148 .odr_avl[3] = { 238000, 0x04 }, 149 .odr_avl[4] = { 476000, 0x05 }, 150 .odr_avl[5] = { 952000, 0x06 }, 151 .odr_len = 6, 152 }, 153 }, 154 .fs_table = { 155 [ST_LSM6DSX_ID_ACC] = { 156 .reg = { 157 .addr = 0x20, 158 .mask = GENMASK(4, 3), 159 }, 160 .fs_avl[0] = { IIO_G_TO_M_S_2(61000), 0x0 }, 161 .fs_avl[1] = { IIO_G_TO_M_S_2(122000), 0x2 }, 162 .fs_avl[2] = { IIO_G_TO_M_S_2(244000), 0x3 }, 163 .fs_avl[3] = { IIO_G_TO_M_S_2(732000), 0x1 }, 164 .fs_len = 4, 165 }, 166 [ST_LSM6DSX_ID_GYRO] = { 167 .reg = { 168 .addr = 0x10, 169 .mask = GENMASK(4, 3), 170 }, 171 172 .fs_avl[0] = { IIO_DEGREE_TO_RAD(8750000), 0x0 }, 173 .fs_avl[1] = { IIO_DEGREE_TO_RAD(17500000), 0x1 }, 174 .fs_avl[2] = { IIO_DEGREE_TO_RAD(70000000), 0x3 }, 175 .fs_len = 3, 176 }, 177 }, 178 .irq_config = { 179 .irq1 = { 180 .addr = 0x0c, 181 .mask = BIT(3), 182 }, 183 .irq2 = { 184 .addr = 0x0d, 185 .mask = BIT(3), 186 }, 187 .hla = { 188 .addr = 0x22, 189 .mask = BIT(5), 190 }, 191 .od = { 192 .addr = 0x22, 193 .mask = BIT(4), 194 }, 195 }, 196 .fifo_ops = { 197 .max_size = 32, 198 }, 199 }, 200 { 201 .reset = { 202 .addr = 0x12, 203 .mask = BIT(0), 204 }, 205 .boot = { 206 .addr = 0x12, 207 .mask = BIT(7), 208 }, 209 .bdu = { 210 .addr = 0x12, 211 .mask = BIT(6), 212 }, 213 .id = { 214 { 215 .hw_id = ST_LSM6DS3_ID, 216 .name = ST_LSM6DS3_DEV_NAME, 217 .wai = 0x69, 218 }, 219 }, 220 .channels = { 221 [ST_LSM6DSX_ID_ACC] = { 222 .chan = st_lsm6dsx_acc_channels, 223 .len = ARRAY_SIZE(st_lsm6dsx_acc_channels), 224 }, 225 [ST_LSM6DSX_ID_GYRO] = { 226 .chan = st_lsm6dsx_gyro_channels, 227 .len = ARRAY_SIZE(st_lsm6dsx_gyro_channels), 228 }, 229 }, 230 .odr_table = { 231 [ST_LSM6DSX_ID_ACC] = { 232 .reg = { 233 .addr = 0x10, 234 .mask = GENMASK(7, 4), 235 }, 236 .odr_avl[0] = { 12500, 0x01 }, 237 .odr_avl[1] = { 26000, 0x02 }, 238 .odr_avl[2] = { 52000, 0x03 }, 239 .odr_avl[3] = { 104000, 0x04 }, 240 .odr_avl[4] = { 208000, 0x05 }, 241 .odr_avl[5] = { 416000, 0x06 }, 242 .odr_len = 6, 243 }, 244 [ST_LSM6DSX_ID_GYRO] = { 245 .reg = { 246 .addr = 0x11, 247 .mask = GENMASK(7, 4), 248 }, 249 .odr_avl[0] = { 12500, 0x01 }, 250 .odr_avl[1] = { 26000, 0x02 }, 251 .odr_avl[2] = { 52000, 0x03 }, 252 .odr_avl[3] = { 104000, 0x04 }, 253 .odr_avl[4] = { 208000, 0x05 }, 254 .odr_avl[5] = { 416000, 0x06 }, 255 .odr_len = 6, 256 }, 257 }, 258 .fs_table = { 259 [ST_LSM6DSX_ID_ACC] = { 260 .reg = { 261 .addr = 0x10, 262 .mask = GENMASK(3, 2), 263 }, 264 .fs_avl[0] = { IIO_G_TO_M_S_2(61000), 0x0 }, 265 .fs_avl[1] = { IIO_G_TO_M_S_2(122000), 0x2 }, 266 .fs_avl[2] = { IIO_G_TO_M_S_2(244000), 0x3 }, 267 .fs_avl[3] = { IIO_G_TO_M_S_2(488000), 0x1 }, 268 .fs_len = 4, 269 }, 270 [ST_LSM6DSX_ID_GYRO] = { 271 .reg = { 272 .addr = 0x11, 273 .mask = GENMASK(3, 2), 274 }, 275 .fs_avl[0] = { IIO_DEGREE_TO_RAD(8750000), 0x0 }, 276 .fs_avl[1] = { IIO_DEGREE_TO_RAD(17500000), 0x1 }, 277 .fs_avl[2] = { IIO_DEGREE_TO_RAD(35000000), 0x2 }, 278 .fs_avl[3] = { IIO_DEGREE_TO_RAD(70000000), 0x3 }, 279 .fs_len = 4, 280 }, 281 }, 282 .irq_config = { 283 .irq1 = { 284 .addr = 0x0d, 285 .mask = BIT(3), 286 }, 287 .irq2 = { 288 .addr = 0x0e, 289 .mask = BIT(3), 290 }, 291 .lir = { 292 .addr = 0x58, 293 .mask = BIT(0), 294 }, 295 .irq1_func = { 296 .addr = 0x5e, 297 .mask = BIT(5), 298 }, 299 .irq2_func = { 300 .addr = 0x5f, 301 .mask = BIT(5), 302 }, 303 .hla = { 304 .addr = 0x12, 305 .mask = BIT(5), 306 }, 307 .od = { 308 .addr = 0x12, 309 .mask = BIT(4), 310 }, 311 }, 312 .decimator = { 313 [ST_LSM6DSX_ID_ACC] = { 314 .addr = 0x08, 315 .mask = GENMASK(2, 0), 316 }, 317 [ST_LSM6DSX_ID_GYRO] = { 318 .addr = 0x08, 319 .mask = GENMASK(5, 3), 320 }, 321 }, 322 .fifo_ops = { 323 .update_fifo = st_lsm6dsx_update_fifo, 324 .read_fifo = st_lsm6dsx_read_fifo, 325 .fifo_th = { 326 .addr = 0x06, 327 .mask = GENMASK(11, 0), 328 }, 329 .fifo_diff = { 330 .addr = 0x3a, 331 .mask = GENMASK(11, 0), 332 }, 333 .max_size = 1365, 334 .th_wl = 3, /* 1LSB = 2B */ 335 }, 336 .ts_settings = { 337 .timer_en = { 338 .addr = 0x58, 339 .mask = BIT(7), 340 }, 341 .hr_timer = { 342 .addr = 0x5c, 343 .mask = BIT(4), 344 }, 345 .fifo_en = { 346 .addr = 0x07, 347 .mask = BIT(7), 348 }, 349 .decimator = { 350 .addr = 0x09, 351 .mask = GENMASK(5, 3), 352 }, 353 }, 354 .event_settings = { 355 .wakeup_reg = { 356 .addr = 0x5B, 357 .mask = GENMASK(5, 0), 358 }, 359 .wakeup_src_reg = 0x1b, 360 .wakeup_src_status_mask = BIT(3), 361 .wakeup_src_z_mask = BIT(0), 362 .wakeup_src_y_mask = BIT(1), 363 .wakeup_src_x_mask = BIT(2), 364 }, 365 }, 366 { 367 .reset = { 368 .addr = 0x12, 369 .mask = BIT(0), 370 }, 371 .boot = { 372 .addr = 0x12, 373 .mask = BIT(7), 374 }, 375 .bdu = { 376 .addr = 0x12, 377 .mask = BIT(6), 378 }, 379 .id = { 380 { 381 .hw_id = ST_LSM6DS3H_ID, 382 .name = ST_LSM6DS3H_DEV_NAME, 383 .wai = 0x69, 384 }, 385 }, 386 .channels = { 387 [ST_LSM6DSX_ID_ACC] = { 388 .chan = st_lsm6dsx_acc_channels, 389 .len = ARRAY_SIZE(st_lsm6dsx_acc_channels), 390 }, 391 [ST_LSM6DSX_ID_GYRO] = { 392 .chan = st_lsm6dsx_gyro_channels, 393 .len = ARRAY_SIZE(st_lsm6dsx_gyro_channels), 394 }, 395 }, 396 .odr_table = { 397 [ST_LSM6DSX_ID_ACC] = { 398 .reg = { 399 .addr = 0x10, 400 .mask = GENMASK(7, 4), 401 }, 402 .odr_avl[0] = { 12500, 0x01 }, 403 .odr_avl[1] = { 26000, 0x02 }, 404 .odr_avl[2] = { 52000, 0x03 }, 405 .odr_avl[3] = { 104000, 0x04 }, 406 .odr_avl[4] = { 208000, 0x05 }, 407 .odr_avl[5] = { 416000, 0x06 }, 408 .odr_len = 6, 409 }, 410 [ST_LSM6DSX_ID_GYRO] = { 411 .reg = { 412 .addr = 0x11, 413 .mask = GENMASK(7, 4), 414 }, 415 .odr_avl[0] = { 12500, 0x01 }, 416 .odr_avl[1] = { 26000, 0x02 }, 417 .odr_avl[2] = { 52000, 0x03 }, 418 .odr_avl[3] = { 104000, 0x04 }, 419 .odr_avl[4] = { 208000, 0x05 }, 420 .odr_avl[5] = { 416000, 0x06 }, 421 .odr_len = 6, 422 }, 423 }, 424 .fs_table = { 425 [ST_LSM6DSX_ID_ACC] = { 426 .reg = { 427 .addr = 0x10, 428 .mask = GENMASK(3, 2), 429 }, 430 .fs_avl[0] = { IIO_G_TO_M_S_2(61000), 0x0 }, 431 .fs_avl[1] = { IIO_G_TO_M_S_2(122000), 0x2 }, 432 .fs_avl[2] = { IIO_G_TO_M_S_2(244000), 0x3 }, 433 .fs_avl[3] = { IIO_G_TO_M_S_2(488000), 0x1 }, 434 .fs_len = 4, 435 }, 436 [ST_LSM6DSX_ID_GYRO] = { 437 .reg = { 438 .addr = 0x11, 439 .mask = GENMASK(3, 2), 440 }, 441 .fs_avl[0] = { IIO_DEGREE_TO_RAD(8750000), 0x0 }, 442 .fs_avl[1] = { IIO_DEGREE_TO_RAD(17500000), 0x1 }, 443 .fs_avl[2] = { IIO_DEGREE_TO_RAD(35000000), 0x2 }, 444 .fs_avl[3] = { IIO_DEGREE_TO_RAD(70000000), 0x3 }, 445 .fs_len = 4, 446 }, 447 }, 448 .irq_config = { 449 .irq1 = { 450 .addr = 0x0d, 451 .mask = BIT(3), 452 }, 453 .irq2 = { 454 .addr = 0x0e, 455 .mask = BIT(3), 456 }, 457 .lir = { 458 .addr = 0x58, 459 .mask = BIT(0), 460 }, 461 .irq1_func = { 462 .addr = 0x5e, 463 .mask = BIT(5), 464 }, 465 .irq2_func = { 466 .addr = 0x5f, 467 .mask = BIT(5), 468 }, 469 .hla = { 470 .addr = 0x12, 471 .mask = BIT(5), 472 }, 473 .od = { 474 .addr = 0x12, 475 .mask = BIT(4), 476 }, 477 }, 478 .decimator = { 479 [ST_LSM6DSX_ID_ACC] = { 480 .addr = 0x08, 481 .mask = GENMASK(2, 0), 482 }, 483 [ST_LSM6DSX_ID_GYRO] = { 484 .addr = 0x08, 485 .mask = GENMASK(5, 3), 486 }, 487 }, 488 .fifo_ops = { 489 .update_fifo = st_lsm6dsx_update_fifo, 490 .read_fifo = st_lsm6dsx_read_fifo, 491 .fifo_th = { 492 .addr = 0x06, 493 .mask = GENMASK(11, 0), 494 }, 495 .fifo_diff = { 496 .addr = 0x3a, 497 .mask = GENMASK(11, 0), 498 }, 499 .max_size = 682, 500 .th_wl = 3, /* 1LSB = 2B */ 501 }, 502 .ts_settings = { 503 .timer_en = { 504 .addr = 0x58, 505 .mask = BIT(7), 506 }, 507 .hr_timer = { 508 .addr = 0x5c, 509 .mask = BIT(4), 510 }, 511 .fifo_en = { 512 .addr = 0x07, 513 .mask = BIT(7), 514 }, 515 .decimator = { 516 .addr = 0x09, 517 .mask = GENMASK(5, 3), 518 }, 519 }, 520 .event_settings = { 521 .wakeup_reg = { 522 .addr = 0x5B, 523 .mask = GENMASK(5, 0), 524 }, 525 .wakeup_src_reg = 0x1b, 526 .wakeup_src_status_mask = BIT(3), 527 .wakeup_src_z_mask = BIT(0), 528 .wakeup_src_y_mask = BIT(1), 529 .wakeup_src_x_mask = BIT(2), 530 }, 531 }, 532 { 533 .reset = { 534 .addr = 0x12, 535 .mask = BIT(0), 536 }, 537 .boot = { 538 .addr = 0x12, 539 .mask = BIT(7), 540 }, 541 .bdu = { 542 .addr = 0x12, 543 .mask = BIT(6), 544 }, 545 .id = { 546 { 547 .hw_id = ST_LSM6DSL_ID, 548 .name = ST_LSM6DSL_DEV_NAME, 549 .wai = 0x6a, 550 }, { 551 .hw_id = ST_LSM6DSM_ID, 552 .name = ST_LSM6DSM_DEV_NAME, 553 .wai = 0x6a, 554 }, { 555 .hw_id = ST_ISM330DLC_ID, 556 .name = ST_ISM330DLC_DEV_NAME, 557 .wai = 0x6a, 558 }, { 559 .hw_id = ST_LSM6DS3TRC_ID, 560 .name = ST_LSM6DS3TRC_DEV_NAME, 561 .wai = 0x6a, 562 }, 563 }, 564 .channels = { 565 [ST_LSM6DSX_ID_ACC] = { 566 .chan = st_lsm6dsx_acc_channels, 567 .len = ARRAY_SIZE(st_lsm6dsx_acc_channels), 568 }, 569 [ST_LSM6DSX_ID_GYRO] = { 570 .chan = st_lsm6dsx_gyro_channels, 571 .len = ARRAY_SIZE(st_lsm6dsx_gyro_channels), 572 }, 573 }, 574 .odr_table = { 575 [ST_LSM6DSX_ID_ACC] = { 576 .reg = { 577 .addr = 0x10, 578 .mask = GENMASK(7, 4), 579 }, 580 .odr_avl[0] = { 12500, 0x01 }, 581 .odr_avl[1] = { 26000, 0x02 }, 582 .odr_avl[2] = { 52000, 0x03 }, 583 .odr_avl[3] = { 104000, 0x04 }, 584 .odr_avl[4] = { 208000, 0x05 }, 585 .odr_avl[5] = { 416000, 0x06 }, 586 .odr_len = 6, 587 }, 588 [ST_LSM6DSX_ID_GYRO] = { 589 .reg = { 590 .addr = 0x11, 591 .mask = GENMASK(7, 4), 592 }, 593 .odr_avl[0] = { 12500, 0x01 }, 594 .odr_avl[1] = { 26000, 0x02 }, 595 .odr_avl[2] = { 52000, 0x03 }, 596 .odr_avl[3] = { 104000, 0x04 }, 597 .odr_avl[4] = { 208000, 0x05 }, 598 .odr_avl[5] = { 416000, 0x06 }, 599 .odr_len = 6, 600 }, 601 }, 602 .fs_table = { 603 [ST_LSM6DSX_ID_ACC] = { 604 .reg = { 605 .addr = 0x10, 606 .mask = GENMASK(3, 2), 607 }, 608 .fs_avl[0] = { IIO_G_TO_M_S_2(61000), 0x0 }, 609 .fs_avl[1] = { IIO_G_TO_M_S_2(122000), 0x2 }, 610 .fs_avl[2] = { IIO_G_TO_M_S_2(244000), 0x3 }, 611 .fs_avl[3] = { IIO_G_TO_M_S_2(488000), 0x1 }, 612 .fs_len = 4, 613 }, 614 [ST_LSM6DSX_ID_GYRO] = { 615 .reg = { 616 .addr = 0x11, 617 .mask = GENMASK(3, 2), 618 }, 619 .fs_avl[0] = { IIO_DEGREE_TO_RAD(8750000), 0x0 }, 620 .fs_avl[1] = { IIO_DEGREE_TO_RAD(17500000), 0x1 }, 621 .fs_avl[2] = { IIO_DEGREE_TO_RAD(35000000), 0x2 }, 622 .fs_avl[3] = { IIO_DEGREE_TO_RAD(70000000), 0x3 }, 623 .fs_len = 4, 624 }, 625 }, 626 .irq_config = { 627 .irq1 = { 628 .addr = 0x0d, 629 .mask = BIT(3), 630 }, 631 .irq2 = { 632 .addr = 0x0e, 633 .mask = BIT(3), 634 }, 635 .lir = { 636 .addr = 0x58, 637 .mask = BIT(0), 638 }, 639 .irq1_func = { 640 .addr = 0x5e, 641 .mask = BIT(5), 642 }, 643 .irq2_func = { 644 .addr = 0x5f, 645 .mask = BIT(5), 646 }, 647 .hla = { 648 .addr = 0x12, 649 .mask = BIT(5), 650 }, 651 .od = { 652 .addr = 0x12, 653 .mask = BIT(4), 654 }, 655 }, 656 .decimator = { 657 [ST_LSM6DSX_ID_ACC] = { 658 .addr = 0x08, 659 .mask = GENMASK(2, 0), 660 }, 661 [ST_LSM6DSX_ID_GYRO] = { 662 .addr = 0x08, 663 .mask = GENMASK(5, 3), 664 }, 665 [ST_LSM6DSX_ID_EXT0] = { 666 .addr = 0x09, 667 .mask = GENMASK(2, 0), 668 }, 669 }, 670 .fifo_ops = { 671 .update_fifo = st_lsm6dsx_update_fifo, 672 .read_fifo = st_lsm6dsx_read_fifo, 673 .fifo_th = { 674 .addr = 0x06, 675 .mask = GENMASK(10, 0), 676 }, 677 .fifo_diff = { 678 .addr = 0x3a, 679 .mask = GENMASK(10, 0), 680 }, 681 .max_size = 682, 682 .th_wl = 3, /* 1LSB = 2B */ 683 }, 684 .ts_settings = { 685 .timer_en = { 686 .addr = 0x19, 687 .mask = BIT(5), 688 }, 689 .hr_timer = { 690 .addr = 0x5c, 691 .mask = BIT(4), 692 }, 693 .fifo_en = { 694 .addr = 0x07, 695 .mask = BIT(7), 696 }, 697 .decimator = { 698 .addr = 0x09, 699 .mask = GENMASK(5, 3), 700 }, 701 }, 702 .shub_settings = { 703 .page_mux = { 704 .addr = 0x01, 705 .mask = BIT(7), 706 }, 707 .master_en = { 708 .addr = 0x1a, 709 .mask = BIT(0), 710 }, 711 .pullup_en = { 712 .addr = 0x1a, 713 .mask = BIT(3), 714 }, 715 .aux_sens = { 716 .addr = 0x04, 717 .mask = GENMASK(5, 4), 718 }, 719 .wr_once = { 720 .addr = 0x07, 721 .mask = BIT(5), 722 }, 723 .emb_func = { 724 .addr = 0x19, 725 .mask = BIT(2), 726 }, 727 .num_ext_dev = 1, 728 .shub_out = { 729 .addr = 0x2e, 730 }, 731 .slv0_addr = 0x02, 732 .dw_slv0_addr = 0x0e, 733 .pause = 0x7, 734 }, 735 .event_settings = { 736 .enable_reg = { 737 .addr = 0x58, 738 .mask = BIT(7), 739 }, 740 .wakeup_reg = { 741 .addr = 0x5B, 742 .mask = GENMASK(5, 0), 743 }, 744 .wakeup_src_reg = 0x1b, 745 .wakeup_src_status_mask = BIT(3), 746 .wakeup_src_z_mask = BIT(0), 747 .wakeup_src_y_mask = BIT(1), 748 .wakeup_src_x_mask = BIT(2), 749 }, 750 }, 751 { 752 .reset = { 753 .addr = 0x12, 754 .mask = BIT(0), 755 }, 756 .boot = { 757 .addr = 0x12, 758 .mask = BIT(7), 759 }, 760 .bdu = { 761 .addr = 0x12, 762 .mask = BIT(6), 763 }, 764 .id = { 765 { 766 .hw_id = ST_LSM6DSR_ID, 767 .name = ST_LSM6DSR_DEV_NAME, 768 .wai = 0x6b, 769 }, { 770 .hw_id = ST_ISM330DHCX_ID, 771 .name = ST_ISM330DHCX_DEV_NAME, 772 .wai = 0x6b, 773 }, { 774 .hw_id = ST_LSM6DSRX_ID, 775 .name = ST_LSM6DSRX_DEV_NAME, 776 .wai = 0x6b, 777 }, { 778 .hw_id = ST_LSM6DSO_ID, 779 .name = ST_LSM6DSO_DEV_NAME, 780 .wai = 0x6c, 781 }, { 782 .hw_id = ST_LSM6DSOX_ID, 783 .name = ST_LSM6DSOX_DEV_NAME, 784 .wai = 0x6c, 785 }, { 786 .hw_id = ST_LSM6DST_ID, 787 .name = ST_LSM6DST_DEV_NAME, 788 .wai = 0x6d, 789 }, 790 }, 791 .channels = { 792 [ST_LSM6DSX_ID_ACC] = { 793 .chan = st_lsm6dsx_acc_channels, 794 .len = ARRAY_SIZE(st_lsm6dsx_acc_channels), 795 }, 796 [ST_LSM6DSX_ID_GYRO] = { 797 .chan = st_lsm6dsx_gyro_channels, 798 .len = ARRAY_SIZE(st_lsm6dsx_gyro_channels), 799 }, 800 }, 801 .drdy_mask = { 802 .addr = 0x13, 803 .mask = BIT(3), 804 }, 805 .odr_table = { 806 [ST_LSM6DSX_ID_ACC] = { 807 .reg = { 808 .addr = 0x10, 809 .mask = GENMASK(7, 4), 810 }, 811 .odr_avl[0] = { 12500, 0x01 }, 812 .odr_avl[1] = { 26000, 0x02 }, 813 .odr_avl[2] = { 52000, 0x03 }, 814 .odr_avl[3] = { 104000, 0x04 }, 815 .odr_avl[4] = { 208000, 0x05 }, 816 .odr_avl[5] = { 416000, 0x06 }, 817 .odr_avl[6] = { 833000, 0x07 }, 818 .odr_len = 7, 819 }, 820 [ST_LSM6DSX_ID_GYRO] = { 821 .reg = { 822 .addr = 0x11, 823 .mask = GENMASK(7, 4), 824 }, 825 .odr_avl[0] = { 12500, 0x01 }, 826 .odr_avl[1] = { 26000, 0x02 }, 827 .odr_avl[2] = { 52000, 0x03 }, 828 .odr_avl[3] = { 104000, 0x04 }, 829 .odr_avl[4] = { 208000, 0x05 }, 830 .odr_avl[5] = { 416000, 0x06 }, 831 .odr_avl[6] = { 833000, 0x07 }, 832 .odr_len = 7, 833 }, 834 }, 835 .fs_table = { 836 [ST_LSM6DSX_ID_ACC] = { 837 .reg = { 838 .addr = 0x10, 839 .mask = GENMASK(3, 2), 840 }, 841 .fs_avl[0] = { IIO_G_TO_M_S_2(61000), 0x0 }, 842 .fs_avl[1] = { IIO_G_TO_M_S_2(122000), 0x2 }, 843 .fs_avl[2] = { IIO_G_TO_M_S_2(244000), 0x3 }, 844 .fs_avl[3] = { IIO_G_TO_M_S_2(488000), 0x1 }, 845 .fs_len = 4, 846 }, 847 [ST_LSM6DSX_ID_GYRO] = { 848 .reg = { 849 .addr = 0x11, 850 .mask = GENMASK(3, 2), 851 }, 852 .fs_avl[0] = { IIO_DEGREE_TO_RAD(8750000), 0x0 }, 853 .fs_avl[1] = { IIO_DEGREE_TO_RAD(17500000), 0x1 }, 854 .fs_avl[2] = { IIO_DEGREE_TO_RAD(35000000), 0x2 }, 855 .fs_avl[3] = { IIO_DEGREE_TO_RAD(70000000), 0x3 }, 856 .fs_len = 4, 857 }, 858 }, 859 .irq_config = { 860 .irq1 = { 861 .addr = 0x0d, 862 .mask = BIT(3), 863 }, 864 .irq2 = { 865 .addr = 0x0e, 866 .mask = BIT(3), 867 }, 868 .lir = { 869 .addr = 0x56, 870 .mask = BIT(0), 871 }, 872 .clear_on_read = { 873 .addr = 0x56, 874 .mask = BIT(6), 875 }, 876 .irq1_func = { 877 .addr = 0x5e, 878 .mask = BIT(5), 879 }, 880 .irq2_func = { 881 .addr = 0x5f, 882 .mask = BIT(5), 883 }, 884 .hla = { 885 .addr = 0x12, 886 .mask = BIT(5), 887 }, 888 .od = { 889 .addr = 0x12, 890 .mask = BIT(4), 891 }, 892 }, 893 .batch = { 894 [ST_LSM6DSX_ID_ACC] = { 895 .addr = 0x09, 896 .mask = GENMASK(3, 0), 897 }, 898 [ST_LSM6DSX_ID_GYRO] = { 899 .addr = 0x09, 900 .mask = GENMASK(7, 4), 901 }, 902 }, 903 .fifo_ops = { 904 .update_fifo = st_lsm6dsx_update_fifo, 905 .read_fifo = st_lsm6dsx_read_tagged_fifo, 906 .fifo_th = { 907 .addr = 0x07, 908 .mask = GENMASK(8, 0), 909 }, 910 .fifo_diff = { 911 .addr = 0x3a, 912 .mask = GENMASK(9, 0), 913 }, 914 .max_size = 512, 915 .th_wl = 1, 916 }, 917 .ts_settings = { 918 .timer_en = { 919 .addr = 0x19, 920 .mask = BIT(5), 921 }, 922 .decimator = { 923 .addr = 0x0a, 924 .mask = GENMASK(7, 6), 925 }, 926 .freq_fine = 0x63, 927 }, 928 .shub_settings = { 929 .page_mux = { 930 .addr = 0x01, 931 .mask = BIT(6), 932 }, 933 .master_en = { 934 .sec_page = true, 935 .addr = 0x14, 936 .mask = BIT(2), 937 }, 938 .pullup_en = { 939 .sec_page = true, 940 .addr = 0x14, 941 .mask = BIT(3), 942 }, 943 .aux_sens = { 944 .addr = 0x14, 945 .mask = GENMASK(1, 0), 946 }, 947 .wr_once = { 948 .addr = 0x14, 949 .mask = BIT(6), 950 }, 951 .num_ext_dev = 3, 952 .shub_out = { 953 .sec_page = true, 954 .addr = 0x02, 955 }, 956 .slv0_addr = 0x15, 957 .dw_slv0_addr = 0x21, 958 .batch_en = BIT(3), 959 }, 960 .event_settings = { 961 .enable_reg = { 962 .addr = 0x58, 963 .mask = BIT(7), 964 }, 965 .wakeup_reg = { 966 .addr = 0x5b, 967 .mask = GENMASK(5, 0), 968 }, 969 .wakeup_src_reg = 0x1b, 970 .wakeup_src_status_mask = BIT(3), 971 .wakeup_src_z_mask = BIT(0), 972 .wakeup_src_y_mask = BIT(1), 973 .wakeup_src_x_mask = BIT(2), 974 }, 975 }, 976 { 977 .reset = { 978 .addr = 0x12, 979 .mask = BIT(0), 980 }, 981 .boot = { 982 .addr = 0x12, 983 .mask = BIT(7), 984 }, 985 .bdu = { 986 .addr = 0x12, 987 .mask = BIT(6), 988 }, 989 .id = { 990 { 991 .hw_id = ST_ASM330LHH_ID, 992 .name = ST_ASM330LHH_DEV_NAME, 993 .wai = 0x6b, 994 }, { 995 .hw_id = ST_LSM6DSOP_ID, 996 .name = ST_LSM6DSOP_DEV_NAME, 997 .wai = 0x6c, 998 }, 999 }, 1000 .channels = { 1001 [ST_LSM6DSX_ID_ACC] = { 1002 .chan = st_lsm6dsx_acc_channels, 1003 .len = ARRAY_SIZE(st_lsm6dsx_acc_channels), 1004 }, 1005 [ST_LSM6DSX_ID_GYRO] = { 1006 .chan = st_lsm6dsx_gyro_channels, 1007 .len = ARRAY_SIZE(st_lsm6dsx_gyro_channels), 1008 }, 1009 }, 1010 .drdy_mask = { 1011 .addr = 0x13, 1012 .mask = BIT(3), 1013 }, 1014 .odr_table = { 1015 [ST_LSM6DSX_ID_ACC] = { 1016 .reg = { 1017 .addr = 0x10, 1018 .mask = GENMASK(7, 4), 1019 }, 1020 .odr_avl[0] = { 12500, 0x01 }, 1021 .odr_avl[1] = { 26000, 0x02 }, 1022 .odr_avl[2] = { 52000, 0x03 }, 1023 .odr_avl[3] = { 104000, 0x04 }, 1024 .odr_avl[4] = { 208000, 0x05 }, 1025 .odr_avl[5] = { 416000, 0x06 }, 1026 .odr_avl[6] = { 833000, 0x07 }, 1027 .odr_len = 7, 1028 }, 1029 [ST_LSM6DSX_ID_GYRO] = { 1030 .reg = { 1031 .addr = 0x11, 1032 .mask = GENMASK(7, 4), 1033 }, 1034 .odr_avl[0] = { 12500, 0x01 }, 1035 .odr_avl[1] = { 26000, 0x02 }, 1036 .odr_avl[2] = { 52000, 0x03 }, 1037 .odr_avl[3] = { 104000, 0x04 }, 1038 .odr_avl[4] = { 208000, 0x05 }, 1039 .odr_avl[5] = { 416000, 0x06 }, 1040 .odr_avl[6] = { 833000, 0x07 }, 1041 .odr_len = 7, 1042 }, 1043 }, 1044 .fs_table = { 1045 [ST_LSM6DSX_ID_ACC] = { 1046 .reg = { 1047 .addr = 0x10, 1048 .mask = GENMASK(3, 2), 1049 }, 1050 .fs_avl[0] = { IIO_G_TO_M_S_2(61000), 0x0 }, 1051 .fs_avl[1] = { IIO_G_TO_M_S_2(122000), 0x2 }, 1052 .fs_avl[2] = { IIO_G_TO_M_S_2(244000), 0x3 }, 1053 .fs_avl[3] = { IIO_G_TO_M_S_2(488000), 0x1 }, 1054 .fs_len = 4, 1055 }, 1056 [ST_LSM6DSX_ID_GYRO] = { 1057 .reg = { 1058 .addr = 0x11, 1059 .mask = GENMASK(3, 2), 1060 }, 1061 .fs_avl[0] = { IIO_DEGREE_TO_RAD(8750000), 0x0 }, 1062 .fs_avl[1] = { IIO_DEGREE_TO_RAD(17500000), 0x1 }, 1063 .fs_avl[2] = { IIO_DEGREE_TO_RAD(35000000), 0x2 }, 1064 .fs_avl[3] = { IIO_DEGREE_TO_RAD(70000000), 0x3 }, 1065 .fs_len = 4, 1066 }, 1067 }, 1068 .irq_config = { 1069 .irq1 = { 1070 .addr = 0x0d, 1071 .mask = BIT(3), 1072 }, 1073 .irq2 = { 1074 .addr = 0x0e, 1075 .mask = BIT(3), 1076 }, 1077 .lir = { 1078 .addr = 0x56, 1079 .mask = BIT(0), 1080 }, 1081 .clear_on_read = { 1082 .addr = 0x56, 1083 .mask = BIT(6), 1084 }, 1085 .irq1_func = { 1086 .addr = 0x5e, 1087 .mask = BIT(5), 1088 }, 1089 .irq2_func = { 1090 .addr = 0x5f, 1091 .mask = BIT(5), 1092 }, 1093 .hla = { 1094 .addr = 0x12, 1095 .mask = BIT(5), 1096 }, 1097 .od = { 1098 .addr = 0x12, 1099 .mask = BIT(4), 1100 }, 1101 }, 1102 .batch = { 1103 [ST_LSM6DSX_ID_ACC] = { 1104 .addr = 0x09, 1105 .mask = GENMASK(3, 0), 1106 }, 1107 [ST_LSM6DSX_ID_GYRO] = { 1108 .addr = 0x09, 1109 .mask = GENMASK(7, 4), 1110 }, 1111 }, 1112 .fifo_ops = { 1113 .update_fifo = st_lsm6dsx_update_fifo, 1114 .read_fifo = st_lsm6dsx_read_tagged_fifo, 1115 .fifo_th = { 1116 .addr = 0x07, 1117 .mask = GENMASK(8, 0), 1118 }, 1119 .fifo_diff = { 1120 .addr = 0x3a, 1121 .mask = GENMASK(9, 0), 1122 }, 1123 .max_size = 512, 1124 .th_wl = 1, 1125 }, 1126 .ts_settings = { 1127 .timer_en = { 1128 .addr = 0x19, 1129 .mask = BIT(5), 1130 }, 1131 .decimator = { 1132 .addr = 0x0a, 1133 .mask = GENMASK(7, 6), 1134 }, 1135 .freq_fine = 0x63, 1136 }, 1137 .event_settings = { 1138 .enable_reg = { 1139 .addr = 0x58, 1140 .mask = BIT(7), 1141 }, 1142 .wakeup_reg = { 1143 .addr = 0x5B, 1144 .mask = GENMASK(5, 0), 1145 }, 1146 .wakeup_src_reg = 0x1b, 1147 .wakeup_src_status_mask = BIT(3), 1148 .wakeup_src_z_mask = BIT(0), 1149 .wakeup_src_y_mask = BIT(1), 1150 .wakeup_src_x_mask = BIT(2), 1151 }, 1152 }, 1153 }; 1154 1155 int st_lsm6dsx_set_page(struct st_lsm6dsx_hw *hw, bool enable) 1156 { 1157 const struct st_lsm6dsx_shub_settings *hub_settings; 1158 unsigned int data; 1159 int err; 1160 1161 hub_settings = &hw->settings->shub_settings; 1162 data = ST_LSM6DSX_SHIFT_VAL(enable, hub_settings->page_mux.mask); 1163 err = regmap_update_bits(hw->regmap, hub_settings->page_mux.addr, 1164 hub_settings->page_mux.mask, data); 1165 usleep_range(100, 150); 1166 1167 return err; 1168 } 1169 1170 static int st_lsm6dsx_check_whoami(struct st_lsm6dsx_hw *hw, int id, 1171 const char **name) 1172 { 1173 int err, i, j, data; 1174 1175 for (i = 0; i < ARRAY_SIZE(st_lsm6dsx_sensor_settings); i++) { 1176 for (j = 0; j < ST_LSM6DSX_MAX_ID; j++) { 1177 if (st_lsm6dsx_sensor_settings[i].id[j].name && 1178 id == st_lsm6dsx_sensor_settings[i].id[j].hw_id) 1179 break; 1180 } 1181 if (j < ST_LSM6DSX_MAX_ID) 1182 break; 1183 } 1184 1185 if (i == ARRAY_SIZE(st_lsm6dsx_sensor_settings)) { 1186 dev_err(hw->dev, "unsupported hw id [%02x]\n", id); 1187 return -ENODEV; 1188 } 1189 1190 err = regmap_read(hw->regmap, ST_LSM6DSX_REG_WHOAMI_ADDR, &data); 1191 if (err < 0) { 1192 dev_err(hw->dev, "failed to read whoami register\n"); 1193 return err; 1194 } 1195 1196 if (data != st_lsm6dsx_sensor_settings[i].id[j].wai) { 1197 dev_err(hw->dev, "unsupported whoami [%02x]\n", data); 1198 return -ENODEV; 1199 } 1200 1201 *name = st_lsm6dsx_sensor_settings[i].id[j].name; 1202 hw->settings = &st_lsm6dsx_sensor_settings[i]; 1203 1204 return 0; 1205 } 1206 1207 static int st_lsm6dsx_set_full_scale(struct st_lsm6dsx_sensor *sensor, 1208 u32 gain) 1209 { 1210 const struct st_lsm6dsx_fs_table_entry *fs_table; 1211 unsigned int data; 1212 int i, err; 1213 1214 fs_table = &sensor->hw->settings->fs_table[sensor->id]; 1215 for (i = 0; i < fs_table->fs_len; i++) { 1216 if (fs_table->fs_avl[i].gain == gain) 1217 break; 1218 } 1219 1220 if (i == fs_table->fs_len) 1221 return -EINVAL; 1222 1223 data = ST_LSM6DSX_SHIFT_VAL(fs_table->fs_avl[i].val, 1224 fs_table->reg.mask); 1225 err = st_lsm6dsx_update_bits_locked(sensor->hw, fs_table->reg.addr, 1226 fs_table->reg.mask, data); 1227 if (err < 0) 1228 return err; 1229 1230 sensor->gain = gain; 1231 1232 return 0; 1233 } 1234 1235 int st_lsm6dsx_check_odr(struct st_lsm6dsx_sensor *sensor, u32 odr, u8 *val) 1236 { 1237 const struct st_lsm6dsx_odr_table_entry *odr_table; 1238 int i; 1239 1240 odr_table = &sensor->hw->settings->odr_table[sensor->id]; 1241 for (i = 0; i < odr_table->odr_len; i++) { 1242 /* 1243 * ext devices can run at different odr respect to 1244 * accel sensor 1245 */ 1246 if (odr_table->odr_avl[i].milli_hz >= odr) 1247 break; 1248 } 1249 1250 if (i == odr_table->odr_len) 1251 return -EINVAL; 1252 1253 *val = odr_table->odr_avl[i].val; 1254 return odr_table->odr_avl[i].milli_hz; 1255 } 1256 1257 static int 1258 st_lsm6dsx_check_odr_dependency(struct st_lsm6dsx_hw *hw, u32 odr, 1259 enum st_lsm6dsx_sensor_id id) 1260 { 1261 struct st_lsm6dsx_sensor *ref = iio_priv(hw->iio_devs[id]); 1262 1263 if (odr > 0) { 1264 if (hw->enable_mask & BIT(id)) 1265 return max_t(u32, ref->odr, odr); 1266 else 1267 return odr; 1268 } else { 1269 return (hw->enable_mask & BIT(id)) ? ref->odr : 0; 1270 } 1271 } 1272 1273 static int 1274 st_lsm6dsx_set_odr(struct st_lsm6dsx_sensor *sensor, u32 req_odr) 1275 { 1276 struct st_lsm6dsx_sensor *ref_sensor = sensor; 1277 struct st_lsm6dsx_hw *hw = sensor->hw; 1278 const struct st_lsm6dsx_reg *reg; 1279 unsigned int data; 1280 u8 val = 0; 1281 int err; 1282 1283 switch (sensor->id) { 1284 case ST_LSM6DSX_ID_GYRO: 1285 break; 1286 case ST_LSM6DSX_ID_EXT0: 1287 case ST_LSM6DSX_ID_EXT1: 1288 case ST_LSM6DSX_ID_EXT2: 1289 case ST_LSM6DSX_ID_ACC: { 1290 u32 odr; 1291 int i; 1292 1293 /* 1294 * i2c embedded controller relies on the accelerometer sensor as 1295 * bus read/write trigger so we need to enable accel device 1296 * at odr = max(accel_odr, ext_odr) in order to properly 1297 * communicate with i2c slave devices 1298 */ 1299 ref_sensor = iio_priv(hw->iio_devs[ST_LSM6DSX_ID_ACC]); 1300 for (i = ST_LSM6DSX_ID_ACC; i < ST_LSM6DSX_ID_MAX; i++) { 1301 if (!hw->iio_devs[i] || i == sensor->id) 1302 continue; 1303 1304 odr = st_lsm6dsx_check_odr_dependency(hw, req_odr, i); 1305 if (odr != req_odr) 1306 /* device already configured */ 1307 return 0; 1308 } 1309 break; 1310 } 1311 default: /* should never occur */ 1312 return -EINVAL; 1313 } 1314 1315 if (req_odr > 0) { 1316 err = st_lsm6dsx_check_odr(ref_sensor, req_odr, &val); 1317 if (err < 0) 1318 return err; 1319 } 1320 1321 reg = &hw->settings->odr_table[ref_sensor->id].reg; 1322 data = ST_LSM6DSX_SHIFT_VAL(val, reg->mask); 1323 return st_lsm6dsx_update_bits_locked(hw, reg->addr, reg->mask, data); 1324 } 1325 1326 static int 1327 __st_lsm6dsx_sensor_set_enable(struct st_lsm6dsx_sensor *sensor, 1328 bool enable) 1329 { 1330 struct st_lsm6dsx_hw *hw = sensor->hw; 1331 u32 odr = enable ? sensor->odr : 0; 1332 int err; 1333 1334 err = st_lsm6dsx_set_odr(sensor, odr); 1335 if (err < 0) 1336 return err; 1337 1338 if (enable) 1339 hw->enable_mask |= BIT(sensor->id); 1340 else 1341 hw->enable_mask &= ~BIT(sensor->id); 1342 1343 return 0; 1344 } 1345 1346 static int 1347 st_lsm6dsx_check_events(struct st_lsm6dsx_sensor *sensor, bool enable) 1348 { 1349 struct st_lsm6dsx_hw *hw = sensor->hw; 1350 1351 if (sensor->id == ST_LSM6DSX_ID_GYRO || enable) 1352 return 0; 1353 1354 return hw->enable_event; 1355 } 1356 1357 int st_lsm6dsx_sensor_set_enable(struct st_lsm6dsx_sensor *sensor, 1358 bool enable) 1359 { 1360 if (st_lsm6dsx_check_events(sensor, enable)) 1361 return 0; 1362 1363 return __st_lsm6dsx_sensor_set_enable(sensor, enable); 1364 } 1365 1366 static int st_lsm6dsx_read_oneshot(struct st_lsm6dsx_sensor *sensor, 1367 u8 addr, int *val) 1368 { 1369 struct st_lsm6dsx_hw *hw = sensor->hw; 1370 int err, delay; 1371 __le16 data; 1372 1373 err = st_lsm6dsx_sensor_set_enable(sensor, true); 1374 if (err < 0) 1375 return err; 1376 1377 /* 1378 * we need to wait for sensor settling time before 1379 * reading data in order to avoid corrupted samples 1380 */ 1381 delay = 1000000000 / sensor->odr; 1382 usleep_range(3 * delay, 4 * delay); 1383 1384 err = st_lsm6dsx_read_locked(hw, addr, &data, sizeof(data)); 1385 if (err < 0) 1386 return err; 1387 1388 if (!hw->enable_event) { 1389 err = st_lsm6dsx_sensor_set_enable(sensor, false); 1390 if (err < 0) 1391 return err; 1392 } 1393 1394 *val = (s16)le16_to_cpu(data); 1395 1396 return IIO_VAL_INT; 1397 } 1398 1399 static int st_lsm6dsx_read_raw(struct iio_dev *iio_dev, 1400 struct iio_chan_spec const *ch, 1401 int *val, int *val2, long mask) 1402 { 1403 struct st_lsm6dsx_sensor *sensor = iio_priv(iio_dev); 1404 int ret; 1405 1406 switch (mask) { 1407 case IIO_CHAN_INFO_RAW: 1408 ret = iio_device_claim_direct_mode(iio_dev); 1409 if (ret) 1410 break; 1411 1412 ret = st_lsm6dsx_read_oneshot(sensor, ch->address, val); 1413 iio_device_release_direct_mode(iio_dev); 1414 break; 1415 case IIO_CHAN_INFO_SAMP_FREQ: 1416 *val = sensor->odr / 1000; 1417 *val2 = (sensor->odr % 1000) * 1000; 1418 ret = IIO_VAL_INT_PLUS_MICRO; 1419 break; 1420 case IIO_CHAN_INFO_SCALE: 1421 *val = 0; 1422 *val2 = sensor->gain; 1423 ret = IIO_VAL_INT_PLUS_NANO; 1424 break; 1425 default: 1426 ret = -EINVAL; 1427 break; 1428 } 1429 1430 return ret; 1431 } 1432 1433 static int st_lsm6dsx_write_raw(struct iio_dev *iio_dev, 1434 struct iio_chan_spec const *chan, 1435 int val, int val2, long mask) 1436 { 1437 struct st_lsm6dsx_sensor *sensor = iio_priv(iio_dev); 1438 int err; 1439 1440 err = iio_device_claim_direct_mode(iio_dev); 1441 if (err) 1442 return err; 1443 1444 switch (mask) { 1445 case IIO_CHAN_INFO_SCALE: 1446 err = st_lsm6dsx_set_full_scale(sensor, val2); 1447 break; 1448 case IIO_CHAN_INFO_SAMP_FREQ: { 1449 u8 data; 1450 1451 val = val * 1000 + val2 / 1000; 1452 val = st_lsm6dsx_check_odr(sensor, val, &data); 1453 if (val < 0) 1454 err = val; 1455 else 1456 sensor->odr = val; 1457 break; 1458 } 1459 default: 1460 err = -EINVAL; 1461 break; 1462 } 1463 1464 iio_device_release_direct_mode(iio_dev); 1465 1466 return err; 1467 } 1468 1469 static int st_lsm6dsx_event_setup(struct st_lsm6dsx_hw *hw, int state) 1470 { 1471 const struct st_lsm6dsx_reg *reg; 1472 unsigned int data; 1473 int err; 1474 1475 if (!hw->settings->irq_config.irq1_func.addr) 1476 return -ENOTSUPP; 1477 1478 reg = &hw->settings->event_settings.enable_reg; 1479 if (reg->addr) { 1480 data = ST_LSM6DSX_SHIFT_VAL(state, reg->mask); 1481 err = st_lsm6dsx_update_bits_locked(hw, reg->addr, 1482 reg->mask, data); 1483 if (err < 0) 1484 return err; 1485 } 1486 1487 /* Enable wakeup interrupt */ 1488 data = ST_LSM6DSX_SHIFT_VAL(state, hw->irq_routing->mask); 1489 return st_lsm6dsx_update_bits_locked(hw, hw->irq_routing->addr, 1490 hw->irq_routing->mask, data); 1491 } 1492 1493 static int st_lsm6dsx_read_event(struct iio_dev *iio_dev, 1494 const struct iio_chan_spec *chan, 1495 enum iio_event_type type, 1496 enum iio_event_direction dir, 1497 enum iio_event_info info, 1498 int *val, int *val2) 1499 { 1500 struct st_lsm6dsx_sensor *sensor = iio_priv(iio_dev); 1501 struct st_lsm6dsx_hw *hw = sensor->hw; 1502 1503 if (type != IIO_EV_TYPE_THRESH) 1504 return -EINVAL; 1505 1506 *val2 = 0; 1507 *val = hw->event_threshold; 1508 1509 return IIO_VAL_INT; 1510 } 1511 1512 static int 1513 st_lsm6dsx_write_event(struct iio_dev *iio_dev, 1514 const struct iio_chan_spec *chan, 1515 enum iio_event_type type, 1516 enum iio_event_direction dir, 1517 enum iio_event_info info, 1518 int val, int val2) 1519 { 1520 struct st_lsm6dsx_sensor *sensor = iio_priv(iio_dev); 1521 struct st_lsm6dsx_hw *hw = sensor->hw; 1522 const struct st_lsm6dsx_reg *reg; 1523 unsigned int data; 1524 int err; 1525 1526 if (type != IIO_EV_TYPE_THRESH) 1527 return -EINVAL; 1528 1529 if (val < 0 || val > 31) 1530 return -EINVAL; 1531 1532 reg = &hw->settings->event_settings.wakeup_reg; 1533 data = ST_LSM6DSX_SHIFT_VAL(val, reg->mask); 1534 err = st_lsm6dsx_update_bits_locked(hw, reg->addr, 1535 reg->mask, data); 1536 if (err < 0) 1537 return -EINVAL; 1538 1539 hw->event_threshold = val; 1540 1541 return 0; 1542 } 1543 1544 static int 1545 st_lsm6dsx_read_event_config(struct iio_dev *iio_dev, 1546 const struct iio_chan_spec *chan, 1547 enum iio_event_type type, 1548 enum iio_event_direction dir) 1549 { 1550 struct st_lsm6dsx_sensor *sensor = iio_priv(iio_dev); 1551 struct st_lsm6dsx_hw *hw = sensor->hw; 1552 1553 if (type != IIO_EV_TYPE_THRESH) 1554 return -EINVAL; 1555 1556 return !!(hw->enable_event & BIT(chan->channel2)); 1557 } 1558 1559 static int 1560 st_lsm6dsx_write_event_config(struct iio_dev *iio_dev, 1561 const struct iio_chan_spec *chan, 1562 enum iio_event_type type, 1563 enum iio_event_direction dir, int state) 1564 { 1565 struct st_lsm6dsx_sensor *sensor = iio_priv(iio_dev); 1566 struct st_lsm6dsx_hw *hw = sensor->hw; 1567 u8 enable_event; 1568 int err; 1569 1570 if (type != IIO_EV_TYPE_THRESH) 1571 return -EINVAL; 1572 1573 if (state) { 1574 enable_event = hw->enable_event | BIT(chan->channel2); 1575 1576 /* do not enable events if they are already enabled */ 1577 if (hw->enable_event) 1578 goto out; 1579 } else { 1580 enable_event = hw->enable_event & ~BIT(chan->channel2); 1581 1582 /* only turn off sensor if no events is enabled */ 1583 if (enable_event) 1584 goto out; 1585 } 1586 1587 /* stop here if no changes have been made */ 1588 if (hw->enable_event == enable_event) 1589 return 0; 1590 1591 err = st_lsm6dsx_event_setup(hw, state); 1592 if (err < 0) 1593 return err; 1594 1595 mutex_lock(&hw->conf_lock); 1596 if (enable_event || !(hw->fifo_mask & BIT(sensor->id))) 1597 err = __st_lsm6dsx_sensor_set_enable(sensor, state); 1598 mutex_unlock(&hw->conf_lock); 1599 if (err < 0) 1600 return err; 1601 1602 out: 1603 hw->enable_event = enable_event; 1604 1605 return 0; 1606 } 1607 1608 int st_lsm6dsx_set_watermark(struct iio_dev *iio_dev, unsigned int val) 1609 { 1610 struct st_lsm6dsx_sensor *sensor = iio_priv(iio_dev); 1611 struct st_lsm6dsx_hw *hw = sensor->hw; 1612 int err; 1613 1614 if (val < 1 || val > hw->settings->fifo_ops.max_size) 1615 return -EINVAL; 1616 1617 mutex_lock(&hw->conf_lock); 1618 1619 err = st_lsm6dsx_update_watermark(sensor, val); 1620 1621 mutex_unlock(&hw->conf_lock); 1622 1623 if (err < 0) 1624 return err; 1625 1626 sensor->watermark = val; 1627 1628 return 0; 1629 } 1630 1631 static ssize_t 1632 st_lsm6dsx_sysfs_sampling_frequency_avail(struct device *dev, 1633 struct device_attribute *attr, 1634 char *buf) 1635 { 1636 struct st_lsm6dsx_sensor *sensor = iio_priv(dev_to_iio_dev(dev)); 1637 const struct st_lsm6dsx_odr_table_entry *odr_table; 1638 int i, len = 0; 1639 1640 odr_table = &sensor->hw->settings->odr_table[sensor->id]; 1641 for (i = 0; i < odr_table->odr_len; i++) 1642 len += scnprintf(buf + len, PAGE_SIZE - len, "%d.%03d ", 1643 odr_table->odr_avl[i].milli_hz / 1000, 1644 odr_table->odr_avl[i].milli_hz % 1000); 1645 buf[len - 1] = '\n'; 1646 1647 return len; 1648 } 1649 1650 static ssize_t st_lsm6dsx_sysfs_scale_avail(struct device *dev, 1651 struct device_attribute *attr, 1652 char *buf) 1653 { 1654 struct st_lsm6dsx_sensor *sensor = iio_priv(dev_to_iio_dev(dev)); 1655 const struct st_lsm6dsx_fs_table_entry *fs_table; 1656 struct st_lsm6dsx_hw *hw = sensor->hw; 1657 int i, len = 0; 1658 1659 fs_table = &hw->settings->fs_table[sensor->id]; 1660 for (i = 0; i < fs_table->fs_len; i++) 1661 len += scnprintf(buf + len, PAGE_SIZE - len, "0.%09u ", 1662 fs_table->fs_avl[i].gain); 1663 buf[len - 1] = '\n'; 1664 1665 return len; 1666 } 1667 1668 static int st_lsm6dsx_write_raw_get_fmt(struct iio_dev *indio_dev, 1669 struct iio_chan_spec const *chan, 1670 long mask) 1671 { 1672 switch (mask) { 1673 case IIO_CHAN_INFO_SCALE: 1674 switch (chan->type) { 1675 case IIO_ANGL_VEL: 1676 case IIO_ACCEL: 1677 return IIO_VAL_INT_PLUS_NANO; 1678 default: 1679 return IIO_VAL_INT_PLUS_MICRO; 1680 } 1681 default: 1682 return IIO_VAL_INT_PLUS_MICRO; 1683 } 1684 } 1685 1686 static IIO_DEV_ATTR_SAMP_FREQ_AVAIL(st_lsm6dsx_sysfs_sampling_frequency_avail); 1687 static IIO_DEVICE_ATTR(in_accel_scale_available, 0444, 1688 st_lsm6dsx_sysfs_scale_avail, NULL, 0); 1689 static IIO_DEVICE_ATTR(in_anglvel_scale_available, 0444, 1690 st_lsm6dsx_sysfs_scale_avail, NULL, 0); 1691 1692 static struct attribute *st_lsm6dsx_acc_attributes[] = { 1693 &iio_dev_attr_sampling_frequency_available.dev_attr.attr, 1694 &iio_dev_attr_in_accel_scale_available.dev_attr.attr, 1695 NULL, 1696 }; 1697 1698 static const struct attribute_group st_lsm6dsx_acc_attribute_group = { 1699 .attrs = st_lsm6dsx_acc_attributes, 1700 }; 1701 1702 static const struct iio_info st_lsm6dsx_acc_info = { 1703 .attrs = &st_lsm6dsx_acc_attribute_group, 1704 .read_raw = st_lsm6dsx_read_raw, 1705 .write_raw = st_lsm6dsx_write_raw, 1706 .read_event_value = st_lsm6dsx_read_event, 1707 .write_event_value = st_lsm6dsx_write_event, 1708 .read_event_config = st_lsm6dsx_read_event_config, 1709 .write_event_config = st_lsm6dsx_write_event_config, 1710 .hwfifo_set_watermark = st_lsm6dsx_set_watermark, 1711 .write_raw_get_fmt = st_lsm6dsx_write_raw_get_fmt, 1712 }; 1713 1714 static struct attribute *st_lsm6dsx_gyro_attributes[] = { 1715 &iio_dev_attr_sampling_frequency_available.dev_attr.attr, 1716 &iio_dev_attr_in_anglvel_scale_available.dev_attr.attr, 1717 NULL, 1718 }; 1719 1720 static const struct attribute_group st_lsm6dsx_gyro_attribute_group = { 1721 .attrs = st_lsm6dsx_gyro_attributes, 1722 }; 1723 1724 static const struct iio_info st_lsm6dsx_gyro_info = { 1725 .attrs = &st_lsm6dsx_gyro_attribute_group, 1726 .read_raw = st_lsm6dsx_read_raw, 1727 .write_raw = st_lsm6dsx_write_raw, 1728 .hwfifo_set_watermark = st_lsm6dsx_set_watermark, 1729 .write_raw_get_fmt = st_lsm6dsx_write_raw_get_fmt, 1730 }; 1731 1732 static int st_lsm6dsx_get_drdy_pin(struct st_lsm6dsx_hw *hw, int *drdy_pin) 1733 { 1734 struct device *dev = hw->dev; 1735 1736 if (!dev_fwnode(dev)) 1737 return -EINVAL; 1738 1739 return device_property_read_u32(dev, "st,drdy-int-pin", drdy_pin); 1740 } 1741 1742 static int 1743 st_lsm6dsx_get_drdy_reg(struct st_lsm6dsx_hw *hw, 1744 const struct st_lsm6dsx_reg **drdy_reg) 1745 { 1746 int err = 0, drdy_pin; 1747 1748 if (st_lsm6dsx_get_drdy_pin(hw, &drdy_pin) < 0) { 1749 struct st_sensors_platform_data *pdata; 1750 struct device *dev = hw->dev; 1751 1752 pdata = (struct st_sensors_platform_data *)dev->platform_data; 1753 drdy_pin = pdata ? pdata->drdy_int_pin : 1; 1754 } 1755 1756 switch (drdy_pin) { 1757 case 1: 1758 hw->irq_routing = &hw->settings->irq_config.irq1_func; 1759 *drdy_reg = &hw->settings->irq_config.irq1; 1760 break; 1761 case 2: 1762 hw->irq_routing = &hw->settings->irq_config.irq2_func; 1763 *drdy_reg = &hw->settings->irq_config.irq2; 1764 break; 1765 default: 1766 dev_err(hw->dev, "unsupported data ready pin\n"); 1767 err = -EINVAL; 1768 break; 1769 } 1770 1771 return err; 1772 } 1773 1774 static int st_lsm6dsx_init_shub(struct st_lsm6dsx_hw *hw) 1775 { 1776 const struct st_lsm6dsx_shub_settings *hub_settings; 1777 struct st_sensors_platform_data *pdata; 1778 struct device *dev = hw->dev; 1779 unsigned int data; 1780 int err = 0; 1781 1782 hub_settings = &hw->settings->shub_settings; 1783 1784 pdata = (struct st_sensors_platform_data *)dev->platform_data; 1785 if ((dev_fwnode(dev) && device_property_read_bool(dev, "st,pullups")) || 1786 (pdata && pdata->pullups)) { 1787 if (hub_settings->pullup_en.sec_page) { 1788 err = st_lsm6dsx_set_page(hw, true); 1789 if (err < 0) 1790 return err; 1791 } 1792 1793 data = ST_LSM6DSX_SHIFT_VAL(1, hub_settings->pullup_en.mask); 1794 err = regmap_update_bits(hw->regmap, 1795 hub_settings->pullup_en.addr, 1796 hub_settings->pullup_en.mask, data); 1797 1798 if (hub_settings->pullup_en.sec_page) 1799 st_lsm6dsx_set_page(hw, false); 1800 1801 if (err < 0) 1802 return err; 1803 } 1804 1805 if (hub_settings->aux_sens.addr) { 1806 /* configure aux sensors */ 1807 err = st_lsm6dsx_set_page(hw, true); 1808 if (err < 0) 1809 return err; 1810 1811 data = ST_LSM6DSX_SHIFT_VAL(3, hub_settings->aux_sens.mask); 1812 err = regmap_update_bits(hw->regmap, 1813 hub_settings->aux_sens.addr, 1814 hub_settings->aux_sens.mask, data); 1815 1816 st_lsm6dsx_set_page(hw, false); 1817 1818 if (err < 0) 1819 return err; 1820 } 1821 1822 if (hub_settings->emb_func.addr) { 1823 data = ST_LSM6DSX_SHIFT_VAL(1, hub_settings->emb_func.mask); 1824 err = regmap_update_bits(hw->regmap, 1825 hub_settings->emb_func.addr, 1826 hub_settings->emb_func.mask, data); 1827 } 1828 1829 return err; 1830 } 1831 1832 static int st_lsm6dsx_init_hw_timer(struct st_lsm6dsx_hw *hw) 1833 { 1834 const struct st_lsm6dsx_hw_ts_settings *ts_settings; 1835 int err, val; 1836 1837 ts_settings = &hw->settings->ts_settings; 1838 /* enable hw timestamp generation if necessary */ 1839 if (ts_settings->timer_en.addr) { 1840 val = ST_LSM6DSX_SHIFT_VAL(1, ts_settings->timer_en.mask); 1841 err = regmap_update_bits(hw->regmap, 1842 ts_settings->timer_en.addr, 1843 ts_settings->timer_en.mask, val); 1844 if (err < 0) 1845 return err; 1846 } 1847 1848 /* enable high resolution for hw ts timer if necessary */ 1849 if (ts_settings->hr_timer.addr) { 1850 val = ST_LSM6DSX_SHIFT_VAL(1, ts_settings->hr_timer.mask); 1851 err = regmap_update_bits(hw->regmap, 1852 ts_settings->hr_timer.addr, 1853 ts_settings->hr_timer.mask, val); 1854 if (err < 0) 1855 return err; 1856 } 1857 1858 /* enable ts queueing in FIFO if necessary */ 1859 if (ts_settings->fifo_en.addr) { 1860 val = ST_LSM6DSX_SHIFT_VAL(1, ts_settings->fifo_en.mask); 1861 err = regmap_update_bits(hw->regmap, 1862 ts_settings->fifo_en.addr, 1863 ts_settings->fifo_en.mask, val); 1864 if (err < 0) 1865 return err; 1866 } 1867 1868 /* calibrate timestamp sensitivity */ 1869 hw->ts_gain = ST_LSM6DSX_TS_SENSITIVITY; 1870 if (ts_settings->freq_fine) { 1871 err = regmap_read(hw->regmap, ts_settings->freq_fine, &val); 1872 if (err < 0) 1873 return err; 1874 1875 /* 1876 * linearize the AN5192 formula: 1877 * 1 / (1 + x) ~= 1 - x (Taylor’s Series) 1878 * ttrim[s] = 1 / (40000 * (1 + 0.0015 * val)) 1879 * ttrim[ns] ~= 25000 - 37.5 * val 1880 * ttrim[ns] ~= 25000 - (37500 * val) / 1000 1881 */ 1882 hw->ts_gain -= ((s8)val * 37500) / 1000; 1883 } 1884 1885 return 0; 1886 } 1887 1888 static int st_lsm6dsx_reset_device(struct st_lsm6dsx_hw *hw) 1889 { 1890 const struct st_lsm6dsx_reg *reg; 1891 int err; 1892 1893 /* 1894 * flush hw FIFO before device reset in order to avoid 1895 * possible races on interrupt line 1. If the first interrupt 1896 * line is asserted during hw reset the device will work in 1897 * I3C-only mode (if it is supported) 1898 */ 1899 err = st_lsm6dsx_flush_fifo(hw); 1900 if (err < 0 && err != -ENOTSUPP) 1901 return err; 1902 1903 /* device sw reset */ 1904 reg = &hw->settings->reset; 1905 err = regmap_update_bits(hw->regmap, reg->addr, reg->mask, 1906 ST_LSM6DSX_SHIFT_VAL(1, reg->mask)); 1907 if (err < 0) 1908 return err; 1909 1910 msleep(50); 1911 1912 /* reload trimming parameter */ 1913 reg = &hw->settings->boot; 1914 err = regmap_update_bits(hw->regmap, reg->addr, reg->mask, 1915 ST_LSM6DSX_SHIFT_VAL(1, reg->mask)); 1916 if (err < 0) 1917 return err; 1918 1919 msleep(50); 1920 1921 return 0; 1922 } 1923 1924 static int st_lsm6dsx_init_device(struct st_lsm6dsx_hw *hw) 1925 { 1926 const struct st_lsm6dsx_reg *reg; 1927 int err; 1928 1929 err = st_lsm6dsx_reset_device(hw); 1930 if (err < 0) 1931 return err; 1932 1933 /* enable Block Data Update */ 1934 reg = &hw->settings->bdu; 1935 err = regmap_update_bits(hw->regmap, reg->addr, reg->mask, 1936 ST_LSM6DSX_SHIFT_VAL(1, reg->mask)); 1937 if (err < 0) 1938 return err; 1939 1940 /* enable FIFO watermak interrupt */ 1941 err = st_lsm6dsx_get_drdy_reg(hw, ®); 1942 if (err < 0) 1943 return err; 1944 1945 err = regmap_update_bits(hw->regmap, reg->addr, reg->mask, 1946 ST_LSM6DSX_SHIFT_VAL(1, reg->mask)); 1947 if (err < 0) 1948 return err; 1949 1950 /* enable Latched interrupts for device events */ 1951 if (hw->settings->irq_config.lir.addr) { 1952 reg = &hw->settings->irq_config.lir; 1953 err = regmap_update_bits(hw->regmap, reg->addr, reg->mask, 1954 ST_LSM6DSX_SHIFT_VAL(1, reg->mask)); 1955 if (err < 0) 1956 return err; 1957 1958 /* enable clear on read for latched interrupts */ 1959 if (hw->settings->irq_config.clear_on_read.addr) { 1960 reg = &hw->settings->irq_config.clear_on_read; 1961 err = regmap_update_bits(hw->regmap, 1962 reg->addr, reg->mask, 1963 ST_LSM6DSX_SHIFT_VAL(1, reg->mask)); 1964 if (err < 0) 1965 return err; 1966 } 1967 } 1968 1969 /* enable drdy-mas if available */ 1970 if (hw->settings->drdy_mask.addr) { 1971 reg = &hw->settings->drdy_mask; 1972 err = regmap_update_bits(hw->regmap, reg->addr, reg->mask, 1973 ST_LSM6DSX_SHIFT_VAL(1, reg->mask)); 1974 if (err < 0) 1975 return err; 1976 } 1977 1978 err = st_lsm6dsx_init_shub(hw); 1979 if (err < 0) 1980 return err; 1981 1982 return st_lsm6dsx_init_hw_timer(hw); 1983 } 1984 1985 static struct iio_dev *st_lsm6dsx_alloc_iiodev(struct st_lsm6dsx_hw *hw, 1986 enum st_lsm6dsx_sensor_id id, 1987 const char *name) 1988 { 1989 struct st_lsm6dsx_sensor *sensor; 1990 struct iio_dev *iio_dev; 1991 1992 iio_dev = devm_iio_device_alloc(hw->dev, sizeof(*sensor)); 1993 if (!iio_dev) 1994 return NULL; 1995 1996 iio_dev->modes = INDIO_DIRECT_MODE; 1997 iio_dev->available_scan_masks = st_lsm6dsx_available_scan_masks; 1998 iio_dev->channels = hw->settings->channels[id].chan; 1999 iio_dev->num_channels = hw->settings->channels[id].len; 2000 2001 sensor = iio_priv(iio_dev); 2002 sensor->id = id; 2003 sensor->hw = hw; 2004 sensor->odr = hw->settings->odr_table[id].odr_avl[0].milli_hz; 2005 sensor->gain = hw->settings->fs_table[id].fs_avl[0].gain; 2006 sensor->watermark = 1; 2007 2008 switch (id) { 2009 case ST_LSM6DSX_ID_ACC: 2010 iio_dev->info = &st_lsm6dsx_acc_info; 2011 scnprintf(sensor->name, sizeof(sensor->name), "%s_accel", 2012 name); 2013 break; 2014 case ST_LSM6DSX_ID_GYRO: 2015 iio_dev->info = &st_lsm6dsx_gyro_info; 2016 scnprintf(sensor->name, sizeof(sensor->name), "%s_gyro", 2017 name); 2018 break; 2019 default: 2020 return NULL; 2021 } 2022 iio_dev->name = sensor->name; 2023 2024 return iio_dev; 2025 } 2026 2027 static bool 2028 st_lsm6dsx_report_motion_event(struct st_lsm6dsx_hw *hw) 2029 { 2030 const struct st_lsm6dsx_event_settings *event_settings; 2031 int err, data; 2032 s64 timestamp; 2033 2034 if (!hw->enable_event) 2035 return false; 2036 2037 event_settings = &hw->settings->event_settings; 2038 err = st_lsm6dsx_read_locked(hw, event_settings->wakeup_src_reg, 2039 &data, sizeof(data)); 2040 if (err < 0) 2041 return false; 2042 2043 timestamp = iio_get_time_ns(hw->iio_devs[ST_LSM6DSX_ID_ACC]); 2044 if ((data & hw->settings->event_settings.wakeup_src_z_mask) && 2045 (hw->enable_event & BIT(IIO_MOD_Z))) 2046 iio_push_event(hw->iio_devs[ST_LSM6DSX_ID_ACC], 2047 IIO_MOD_EVENT_CODE(IIO_ACCEL, 2048 0, 2049 IIO_MOD_Z, 2050 IIO_EV_TYPE_THRESH, 2051 IIO_EV_DIR_EITHER), 2052 timestamp); 2053 2054 if ((data & hw->settings->event_settings.wakeup_src_y_mask) && 2055 (hw->enable_event & BIT(IIO_MOD_Y))) 2056 iio_push_event(hw->iio_devs[ST_LSM6DSX_ID_ACC], 2057 IIO_MOD_EVENT_CODE(IIO_ACCEL, 2058 0, 2059 IIO_MOD_Y, 2060 IIO_EV_TYPE_THRESH, 2061 IIO_EV_DIR_EITHER), 2062 timestamp); 2063 2064 if ((data & hw->settings->event_settings.wakeup_src_x_mask) && 2065 (hw->enable_event & BIT(IIO_MOD_X))) 2066 iio_push_event(hw->iio_devs[ST_LSM6DSX_ID_ACC], 2067 IIO_MOD_EVENT_CODE(IIO_ACCEL, 2068 0, 2069 IIO_MOD_X, 2070 IIO_EV_TYPE_THRESH, 2071 IIO_EV_DIR_EITHER), 2072 timestamp); 2073 2074 return data & event_settings->wakeup_src_status_mask; 2075 } 2076 2077 static irqreturn_t st_lsm6dsx_handler_thread(int irq, void *private) 2078 { 2079 struct st_lsm6dsx_hw *hw = private; 2080 int fifo_len = 0, len; 2081 bool event; 2082 2083 event = st_lsm6dsx_report_motion_event(hw); 2084 2085 if (!hw->settings->fifo_ops.read_fifo) 2086 return event ? IRQ_HANDLED : IRQ_NONE; 2087 2088 /* 2089 * If we are using edge IRQs, new samples can arrive while 2090 * processing current interrupt since there are no hw 2091 * guarantees the irq line stays "low" long enough to properly 2092 * detect the new interrupt. In this case the new sample will 2093 * be missed. 2094 * Polling FIFO status register allow us to read new 2095 * samples even if the interrupt arrives while processing 2096 * previous data and the timeslot where the line is "low" is 2097 * too short to be properly detected. 2098 */ 2099 do { 2100 mutex_lock(&hw->fifo_lock); 2101 len = hw->settings->fifo_ops.read_fifo(hw); 2102 mutex_unlock(&hw->fifo_lock); 2103 2104 if (len > 0) 2105 fifo_len += len; 2106 } while (len > 0); 2107 2108 return fifo_len || event ? IRQ_HANDLED : IRQ_NONE; 2109 } 2110 2111 static int st_lsm6dsx_irq_setup(struct st_lsm6dsx_hw *hw) 2112 { 2113 struct st_sensors_platform_data *pdata; 2114 const struct st_lsm6dsx_reg *reg; 2115 struct device *dev = hw->dev; 2116 unsigned long irq_type; 2117 bool irq_active_low; 2118 int err; 2119 2120 irq_type = irqd_get_trigger_type(irq_get_irq_data(hw->irq)); 2121 2122 switch (irq_type) { 2123 case IRQF_TRIGGER_HIGH: 2124 case IRQF_TRIGGER_RISING: 2125 irq_active_low = false; 2126 break; 2127 case IRQF_TRIGGER_LOW: 2128 case IRQF_TRIGGER_FALLING: 2129 irq_active_low = true; 2130 break; 2131 default: 2132 dev_info(hw->dev, "mode %lx unsupported\n", irq_type); 2133 return -EINVAL; 2134 } 2135 2136 reg = &hw->settings->irq_config.hla; 2137 err = regmap_update_bits(hw->regmap, reg->addr, reg->mask, 2138 ST_LSM6DSX_SHIFT_VAL(irq_active_low, 2139 reg->mask)); 2140 if (err < 0) 2141 return err; 2142 2143 pdata = (struct st_sensors_platform_data *)dev->platform_data; 2144 if ((dev_fwnode(dev) && device_property_read_bool(dev, "drive-open-drain")) || 2145 (pdata && pdata->open_drain)) { 2146 reg = &hw->settings->irq_config.od; 2147 err = regmap_update_bits(hw->regmap, reg->addr, reg->mask, 2148 ST_LSM6DSX_SHIFT_VAL(1, reg->mask)); 2149 if (err < 0) 2150 return err; 2151 2152 irq_type |= IRQF_SHARED; 2153 } 2154 2155 err = devm_request_threaded_irq(hw->dev, hw->irq, 2156 NULL, 2157 st_lsm6dsx_handler_thread, 2158 irq_type | IRQF_ONESHOT, 2159 "lsm6dsx", hw); 2160 if (err) { 2161 dev_err(hw->dev, "failed to request trigger irq %d\n", 2162 hw->irq); 2163 return err; 2164 } 2165 2166 return 0; 2167 } 2168 2169 static int st_lsm6dsx_init_regulators(struct device *dev) 2170 { 2171 struct st_lsm6dsx_hw *hw = dev_get_drvdata(dev); 2172 int err; 2173 2174 /* vdd-vddio power regulators */ 2175 hw->regulators[0].supply = "vdd"; 2176 hw->regulators[1].supply = "vddio"; 2177 err = devm_regulator_bulk_get(dev, ARRAY_SIZE(hw->regulators), 2178 hw->regulators); 2179 if (err) 2180 return dev_err_probe(dev, err, "failed to get regulators\n"); 2181 2182 err = regulator_bulk_enable(ARRAY_SIZE(hw->regulators), 2183 hw->regulators); 2184 if (err) { 2185 dev_err(dev, "failed to enable regulators: %d\n", err); 2186 return err; 2187 } 2188 2189 msleep(50); 2190 2191 return 0; 2192 } 2193 2194 static void st_lsm6dsx_chip_uninit(void *data) 2195 { 2196 struct st_lsm6dsx_hw *hw = data; 2197 2198 regulator_bulk_disable(ARRAY_SIZE(hw->regulators), hw->regulators); 2199 } 2200 2201 int st_lsm6dsx_probe(struct device *dev, int irq, int hw_id, 2202 struct regmap *regmap) 2203 { 2204 struct st_sensors_platform_data *pdata = dev->platform_data; 2205 const struct st_lsm6dsx_shub_settings *hub_settings; 2206 struct st_lsm6dsx_hw *hw; 2207 const char *name = NULL; 2208 int i, err; 2209 2210 hw = devm_kzalloc(dev, sizeof(*hw), GFP_KERNEL); 2211 if (!hw) 2212 return -ENOMEM; 2213 2214 dev_set_drvdata(dev, (void *)hw); 2215 2216 mutex_init(&hw->fifo_lock); 2217 mutex_init(&hw->conf_lock); 2218 mutex_init(&hw->page_lock); 2219 2220 err = st_lsm6dsx_init_regulators(dev); 2221 if (err) 2222 return err; 2223 2224 err = devm_add_action_or_reset(dev, st_lsm6dsx_chip_uninit, hw); 2225 if (err) 2226 return err; 2227 2228 hw->buff = devm_kzalloc(dev, ST_LSM6DSX_BUFF_SIZE, GFP_KERNEL); 2229 if (!hw->buff) 2230 return -ENOMEM; 2231 2232 hw->dev = dev; 2233 hw->irq = irq; 2234 hw->regmap = regmap; 2235 2236 err = st_lsm6dsx_check_whoami(hw, hw_id, &name); 2237 if (err < 0) 2238 return err; 2239 2240 for (i = 0; i < ST_LSM6DSX_ID_EXT0; i++) { 2241 hw->iio_devs[i] = st_lsm6dsx_alloc_iiodev(hw, i, name); 2242 if (!hw->iio_devs[i]) 2243 return -ENOMEM; 2244 } 2245 2246 err = st_lsm6dsx_init_device(hw); 2247 if (err < 0) 2248 return err; 2249 2250 hub_settings = &hw->settings->shub_settings; 2251 if (hub_settings->master_en.addr && 2252 (!dev_fwnode(dev) || 2253 !device_property_read_bool(dev, "st,disable-sensor-hub"))) { 2254 err = st_lsm6dsx_shub_probe(hw, name); 2255 if (err < 0) 2256 return err; 2257 } 2258 2259 if (hw->irq > 0) { 2260 err = st_lsm6dsx_irq_setup(hw); 2261 if (err < 0) 2262 return err; 2263 2264 err = st_lsm6dsx_fifo_setup(hw); 2265 if (err < 0) 2266 return err; 2267 } 2268 2269 err = iio_read_mount_matrix(hw->dev, &hw->orientation); 2270 if (err) 2271 return err; 2272 2273 for (i = 0; i < ST_LSM6DSX_ID_MAX; i++) { 2274 if (!hw->iio_devs[i]) 2275 continue; 2276 2277 err = devm_iio_device_register(hw->dev, hw->iio_devs[i]); 2278 if (err) 2279 return err; 2280 } 2281 2282 if ((dev_fwnode(dev) && device_property_read_bool(dev, "wakeup-source")) || 2283 (pdata && pdata->wakeup_source)) 2284 device_init_wakeup(dev, true); 2285 2286 return 0; 2287 } 2288 EXPORT_SYMBOL(st_lsm6dsx_probe); 2289 2290 static int __maybe_unused st_lsm6dsx_suspend(struct device *dev) 2291 { 2292 struct st_lsm6dsx_hw *hw = dev_get_drvdata(dev); 2293 struct st_lsm6dsx_sensor *sensor; 2294 int i, err = 0; 2295 2296 for (i = 0; i < ST_LSM6DSX_ID_MAX; i++) { 2297 if (!hw->iio_devs[i]) 2298 continue; 2299 2300 sensor = iio_priv(hw->iio_devs[i]); 2301 if (!(hw->enable_mask & BIT(sensor->id))) 2302 continue; 2303 2304 if (device_may_wakeup(dev) && 2305 sensor->id == ST_LSM6DSX_ID_ACC && hw->enable_event) { 2306 /* Enable wake from IRQ */ 2307 enable_irq_wake(hw->irq); 2308 continue; 2309 } 2310 2311 if (sensor->id == ST_LSM6DSX_ID_EXT0 || 2312 sensor->id == ST_LSM6DSX_ID_EXT1 || 2313 sensor->id == ST_LSM6DSX_ID_EXT2) 2314 err = st_lsm6dsx_shub_set_enable(sensor, false); 2315 else 2316 err = st_lsm6dsx_sensor_set_enable(sensor, false); 2317 if (err < 0) 2318 return err; 2319 2320 hw->suspend_mask |= BIT(sensor->id); 2321 } 2322 2323 if (hw->fifo_mask) 2324 err = st_lsm6dsx_flush_fifo(hw); 2325 2326 return err; 2327 } 2328 2329 static int __maybe_unused st_lsm6dsx_resume(struct device *dev) 2330 { 2331 struct st_lsm6dsx_hw *hw = dev_get_drvdata(dev); 2332 struct st_lsm6dsx_sensor *sensor; 2333 int i, err = 0; 2334 2335 for (i = 0; i < ST_LSM6DSX_ID_MAX; i++) { 2336 if (!hw->iio_devs[i]) 2337 continue; 2338 2339 sensor = iio_priv(hw->iio_devs[i]); 2340 if (device_may_wakeup(dev) && 2341 sensor->id == ST_LSM6DSX_ID_ACC && hw->enable_event) 2342 disable_irq_wake(hw->irq); 2343 2344 if (!(hw->suspend_mask & BIT(sensor->id))) 2345 continue; 2346 2347 if (sensor->id == ST_LSM6DSX_ID_EXT0 || 2348 sensor->id == ST_LSM6DSX_ID_EXT1 || 2349 sensor->id == ST_LSM6DSX_ID_EXT2) 2350 err = st_lsm6dsx_shub_set_enable(sensor, true); 2351 else 2352 err = st_lsm6dsx_sensor_set_enable(sensor, true); 2353 if (err < 0) 2354 return err; 2355 2356 hw->suspend_mask &= ~BIT(sensor->id); 2357 } 2358 2359 if (hw->fifo_mask) 2360 err = st_lsm6dsx_resume_fifo(hw); 2361 2362 return err; 2363 } 2364 2365 const struct dev_pm_ops st_lsm6dsx_pm_ops = { 2366 SET_SYSTEM_SLEEP_PM_OPS(st_lsm6dsx_suspend, st_lsm6dsx_resume) 2367 }; 2368 EXPORT_SYMBOL(st_lsm6dsx_pm_ops); 2369 2370 MODULE_AUTHOR("Lorenzo Bianconi <lorenzo.bianconi@st.com>"); 2371 MODULE_AUTHOR("Denis Ciocca <denis.ciocca@st.com>"); 2372 MODULE_DESCRIPTION("STMicroelectronics st_lsm6dsx driver"); 2373 MODULE_LICENSE("GPL v2"); 2374