1 /* 2 * Copyright (C) 2012 Invensense, Inc. 3 * 4 * This software is licensed under the terms of the GNU General Public 5 * License version 2, as published by the Free Software Foundation, and 6 * may be copied, distributed, and modified under those terms. 7 * 8 * This program is distributed in the hope that it will be useful, 9 * but WITHOUT ANY WARRANTY; without even the implied warranty of 10 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 11 * GNU General Public License for more details. 12 */ 13 #include <linux/i2c.h> 14 #include <linux/i2c-mux.h> 15 #include <linux/kfifo.h> 16 #include <linux/spinlock.h> 17 #include <linux/mutex.h> 18 #include <linux/iio/iio.h> 19 #include <linux/iio/buffer.h> 20 #include <linux/regmap.h> 21 #include <linux/iio/sysfs.h> 22 #include <linux/iio/kfifo_buf.h> 23 #include <linux/iio/trigger.h> 24 #include <linux/iio/triggered_buffer.h> 25 #include <linux/iio/trigger_consumer.h> 26 #include <linux/platform_data/invensense_mpu6050.h> 27 28 /** 29 * struct inv_mpu6050_reg_map - Notable registers. 30 * @sample_rate_div: Divider applied to gyro output rate. 31 * @lpf: Configures internal low pass filter. 32 * @accel_lpf: Configures accelerometer low pass filter. 33 * @user_ctrl: Enables/resets the FIFO. 34 * @fifo_en: Determines which data will appear in FIFO. 35 * @gyro_config: gyro config register. 36 * @accl_config: accel config register 37 * @fifo_count_h: Upper byte of FIFO count. 38 * @fifo_r_w: FIFO register. 39 * @raw_gyro: Address of first gyro register. 40 * @raw_accl: Address of first accel register. 41 * @temperature: temperature register 42 * @int_enable: Interrupt enable register. 43 * @int_status: Interrupt status register. 44 * @pwr_mgmt_1: Controls chip's power state and clock source. 45 * @pwr_mgmt_2: Controls power state of individual sensors. 46 * @int_pin_cfg; Controls interrupt pin configuration. 47 * @accl_offset: Controls the accelerometer calibration offset. 48 * @gyro_offset: Controls the gyroscope calibration offset. 49 */ 50 struct inv_mpu6050_reg_map { 51 u8 sample_rate_div; 52 u8 lpf; 53 u8 accel_lpf; 54 u8 user_ctrl; 55 u8 fifo_en; 56 u8 gyro_config; 57 u8 accl_config; 58 u8 fifo_count_h; 59 u8 fifo_r_w; 60 u8 raw_gyro; 61 u8 raw_accl; 62 u8 temperature; 63 u8 int_enable; 64 u8 int_status; 65 u8 pwr_mgmt_1; 66 u8 pwr_mgmt_2; 67 u8 int_pin_cfg; 68 u8 accl_offset; 69 u8 gyro_offset; 70 }; 71 72 /*device enum */ 73 enum inv_devices { 74 INV_MPU6050, 75 INV_MPU6500, 76 INV_MPU6000, 77 INV_MPU9150, 78 INV_MPU9250, 79 INV_MPU9255, 80 INV_ICM20608, 81 INV_NUM_PARTS 82 }; 83 84 /** 85 * struct inv_mpu6050_chip_config - Cached chip configuration data. 86 * @fsr: Full scale range. 87 * @lpf: Digital low pass filter frequency. 88 * @accl_fs: accel full scale range. 89 * @accl_fifo_enable: enable accel data output 90 * @gyro_fifo_enable: enable gyro data output 91 * @fifo_rate: FIFO update rate. 92 */ 93 struct inv_mpu6050_chip_config { 94 unsigned int fsr:2; 95 unsigned int lpf:3; 96 unsigned int accl_fs:2; 97 unsigned int accl_fifo_enable:1; 98 unsigned int gyro_fifo_enable:1; 99 u16 fifo_rate; 100 u8 user_ctrl; 101 }; 102 103 /** 104 * struct inv_mpu6050_hw - Other important hardware information. 105 * @whoami: Self identification byte from WHO_AM_I register 106 * @name: name of the chip. 107 * @reg: register map of the chip. 108 * @config: configuration of the chip. 109 */ 110 struct inv_mpu6050_hw { 111 u8 whoami; 112 u8 *name; 113 const struct inv_mpu6050_reg_map *reg; 114 const struct inv_mpu6050_chip_config *config; 115 }; 116 117 /* 118 * struct inv_mpu6050_state - Driver state variables. 119 * @TIMESTAMP_FIFO_SIZE: fifo size for timestamp. 120 * @lock: Chip access lock. 121 * @trig: IIO trigger. 122 * @chip_config: Cached attribute information. 123 * @reg: Map of important registers. 124 * @hw: Other hardware-specific information. 125 * @chip_type: chip type. 126 * @time_stamp_lock: spin lock to time stamp. 127 * @plat_data: platform data (deprecated in favor of @orientation). 128 * @orientation: sensor chip orientation relative to main hardware. 129 * @timestamps: kfifo queue to store time stamp. 130 * @map regmap pointer. 131 * @irq interrupt number. 132 * @irq_mask the int_pin_cfg mask to configure interrupt type. 133 */ 134 struct inv_mpu6050_state { 135 #define TIMESTAMP_FIFO_SIZE 16 136 struct mutex lock; 137 struct iio_trigger *trig; 138 struct inv_mpu6050_chip_config chip_config; 139 const struct inv_mpu6050_reg_map *reg; 140 const struct inv_mpu6050_hw *hw; 141 enum inv_devices chip_type; 142 spinlock_t time_stamp_lock; 143 struct i2c_mux_core *muxc; 144 struct i2c_client *mux_client; 145 unsigned int powerup_count; 146 struct inv_mpu6050_platform_data plat_data; 147 struct iio_mount_matrix orientation; 148 DECLARE_KFIFO(timestamps, long long, TIMESTAMP_FIFO_SIZE); 149 struct regmap *map; 150 int irq; 151 u8 irq_mask; 152 unsigned skip_samples; 153 }; 154 155 /*register and associated bit definition*/ 156 #define INV_MPU6050_REG_ACCEL_OFFSET 0x06 157 #define INV_MPU6050_REG_GYRO_OFFSET 0x13 158 159 #define INV_MPU6050_REG_SAMPLE_RATE_DIV 0x19 160 #define INV_MPU6050_REG_CONFIG 0x1A 161 #define INV_MPU6050_REG_GYRO_CONFIG 0x1B 162 #define INV_MPU6050_REG_ACCEL_CONFIG 0x1C 163 164 #define INV_MPU6050_REG_FIFO_EN 0x23 165 #define INV_MPU6050_BIT_ACCEL_OUT 0x08 166 #define INV_MPU6050_BITS_GYRO_OUT 0x70 167 168 #define INV_MPU6050_REG_INT_ENABLE 0x38 169 #define INV_MPU6050_BIT_DATA_RDY_EN 0x01 170 #define INV_MPU6050_BIT_DMP_INT_EN 0x02 171 172 #define INV_MPU6050_REG_RAW_ACCEL 0x3B 173 #define INV_MPU6050_REG_TEMPERATURE 0x41 174 #define INV_MPU6050_REG_RAW_GYRO 0x43 175 176 #define INV_MPU6050_REG_INT_STATUS 0x3A 177 #define INV_MPU6050_BIT_RAW_DATA_RDY_INT 0x01 178 179 #define INV_MPU6050_REG_USER_CTRL 0x6A 180 #define INV_MPU6050_BIT_FIFO_RST 0x04 181 #define INV_MPU6050_BIT_DMP_RST 0x08 182 #define INV_MPU6050_BIT_I2C_MST_EN 0x20 183 #define INV_MPU6050_BIT_FIFO_EN 0x40 184 #define INV_MPU6050_BIT_DMP_EN 0x80 185 #define INV_MPU6050_BIT_I2C_IF_DIS 0x10 186 187 #define INV_MPU6050_REG_PWR_MGMT_1 0x6B 188 #define INV_MPU6050_BIT_H_RESET 0x80 189 #define INV_MPU6050_BIT_SLEEP 0x40 190 #define INV_MPU6050_BIT_CLK_MASK 0x7 191 192 #define INV_MPU6050_REG_PWR_MGMT_2 0x6C 193 #define INV_MPU6050_BIT_PWR_ACCL_STBY 0x38 194 #define INV_MPU6050_BIT_PWR_GYRO_STBY 0x07 195 196 #define INV_MPU6050_REG_FIFO_COUNT_H 0x72 197 #define INV_MPU6050_REG_FIFO_R_W 0x74 198 199 #define INV_MPU6050_BYTES_PER_3AXIS_SENSOR 6 200 #define INV_MPU6050_FIFO_COUNT_BYTE 2 201 #define INV_MPU6050_FIFO_THRESHOLD 500 202 203 /* mpu6500 registers */ 204 #define INV_MPU6500_REG_ACCEL_CONFIG_2 0x1D 205 #define INV_MPU6500_REG_ACCEL_OFFSET 0x77 206 207 /* delay time in milliseconds */ 208 #define INV_MPU6050_POWER_UP_TIME 100 209 #define INV_MPU6050_TEMP_UP_TIME 100 210 #define INV_MPU6050_SENSOR_UP_TIME 30 211 212 /* delay time in microseconds */ 213 #define INV_MPU6050_REG_UP_TIME_MIN 5000 214 #define INV_MPU6050_REG_UP_TIME_MAX 10000 215 216 #define INV_MPU6050_TEMP_OFFSET 12421 217 #define INV_MPU6050_TEMP_SCALE 2941 218 #define INV_MPU6050_MAX_GYRO_FS_PARAM 3 219 #define INV_MPU6050_MAX_ACCL_FS_PARAM 3 220 #define INV_MPU6050_THREE_AXIS 3 221 #define INV_MPU6050_GYRO_CONFIG_FSR_SHIFT 3 222 #define INV_MPU6050_ACCL_CONFIG_FSR_SHIFT 3 223 224 /* 6 + 6 round up and plus 8 */ 225 #define INV_MPU6050_OUTPUT_DATA_SIZE 24 226 227 #define INV_MPU6050_REG_INT_PIN_CFG 0x37 228 #define INV_MPU6050_ACTIVE_HIGH 0x00 229 #define INV_MPU6050_ACTIVE_LOW 0x80 230 /* enable level triggering */ 231 #define INV_MPU6050_LATCH_INT_EN 0x20 232 #define INV_MPU6050_BIT_BYPASS_EN 0x2 233 234 235 /* init parameters */ 236 #define INV_MPU6050_INIT_FIFO_RATE 50 237 #define INV_MPU6050_TIME_STAMP_TOR 5 238 #define INV_MPU6050_MAX_FIFO_RATE 1000 239 #define INV_MPU6050_MIN_FIFO_RATE 4 240 #define INV_MPU6050_ONE_K_HZ 1000 241 242 #define INV_MPU6050_REG_WHOAMI 117 243 244 #define INV_MPU6000_WHOAMI_VALUE 0x68 245 #define INV_MPU6050_WHOAMI_VALUE 0x68 246 #define INV_MPU6500_WHOAMI_VALUE 0x70 247 #define INV_MPU9150_WHOAMI_VALUE 0x68 248 #define INV_MPU9250_WHOAMI_VALUE 0x71 249 #define INV_MPU9255_WHOAMI_VALUE 0x73 250 #define INV_ICM20608_WHOAMI_VALUE 0xAF 251 252 /* scan element definition */ 253 enum inv_mpu6050_scan { 254 INV_MPU6050_SCAN_ACCL_X, 255 INV_MPU6050_SCAN_ACCL_Y, 256 INV_MPU6050_SCAN_ACCL_Z, 257 INV_MPU6050_SCAN_GYRO_X, 258 INV_MPU6050_SCAN_GYRO_Y, 259 INV_MPU6050_SCAN_GYRO_Z, 260 INV_MPU6050_SCAN_TIMESTAMP, 261 }; 262 263 enum inv_mpu6050_filter_e { 264 INV_MPU6050_FILTER_256HZ_NOLPF2 = 0, 265 INV_MPU6050_FILTER_188HZ, 266 INV_MPU6050_FILTER_98HZ, 267 INV_MPU6050_FILTER_42HZ, 268 INV_MPU6050_FILTER_20HZ, 269 INV_MPU6050_FILTER_10HZ, 270 INV_MPU6050_FILTER_5HZ, 271 INV_MPU6050_FILTER_2100HZ_NOLPF, 272 NUM_MPU6050_FILTER 273 }; 274 275 /* IIO attribute address */ 276 enum INV_MPU6050_IIO_ATTR_ADDR { 277 ATTR_GYRO_MATRIX, 278 ATTR_ACCL_MATRIX, 279 }; 280 281 enum inv_mpu6050_accl_fs_e { 282 INV_MPU6050_FS_02G = 0, 283 INV_MPU6050_FS_04G, 284 INV_MPU6050_FS_08G, 285 INV_MPU6050_FS_16G, 286 NUM_ACCL_FSR 287 }; 288 289 enum inv_mpu6050_fsr_e { 290 INV_MPU6050_FSR_250DPS = 0, 291 INV_MPU6050_FSR_500DPS, 292 INV_MPU6050_FSR_1000DPS, 293 INV_MPU6050_FSR_2000DPS, 294 NUM_MPU6050_FSR 295 }; 296 297 enum inv_mpu6050_clock_sel_e { 298 INV_CLK_INTERNAL = 0, 299 INV_CLK_PLL, 300 NUM_CLK 301 }; 302 303 irqreturn_t inv_mpu6050_irq_handler(int irq, void *p); 304 irqreturn_t inv_mpu6050_read_fifo(int irq, void *p); 305 int inv_mpu6050_probe_trigger(struct iio_dev *indio_dev, int irq_type); 306 int inv_reset_fifo(struct iio_dev *indio_dev); 307 int inv_mpu6050_switch_engine(struct inv_mpu6050_state *st, bool en, u32 mask); 308 int inv_mpu6050_write_reg(struct inv_mpu6050_state *st, int reg, u8 val); 309 int inv_mpu6050_set_power_itg(struct inv_mpu6050_state *st, bool power_on); 310 int inv_mpu_acpi_create_mux_client(struct i2c_client *client); 311 void inv_mpu_acpi_delete_mux_client(struct i2c_client *client); 312 int inv_mpu_core_probe(struct regmap *regmap, int irq, const char *name, 313 int (*inv_mpu_bus_setup)(struct iio_dev *), int chip_type); 314 extern const struct dev_pm_ops inv_mpu_pmops; 315