1 /* SPDX-License-Identifier: GPL-2.0-only */ 2 /* 3 * Copyright (C) 2012 Invensense, Inc. 4 */ 5 6 #ifndef INV_MPU_IIO_H_ 7 #define INV_MPU_IIO_H_ 8 9 #include <linux/i2c.h> 10 #include <linux/i2c-mux.h> 11 #include <linux/mutex.h> 12 #include <linux/iio/iio.h> 13 #include <linux/iio/buffer.h> 14 #include <linux/regmap.h> 15 #include <linux/iio/sysfs.h> 16 #include <linux/iio/kfifo_buf.h> 17 #include <linux/iio/trigger.h> 18 #include <linux/iio/triggered_buffer.h> 19 #include <linux/iio/trigger_consumer.h> 20 #include <linux/platform_data/invensense_mpu6050.h> 21 22 /** 23 * struct inv_mpu6050_reg_map - Notable registers. 24 * @sample_rate_div: Divider applied to gyro output rate. 25 * @lpf: Configures internal low pass filter. 26 * @accel_lpf: Configures accelerometer low pass filter. 27 * @user_ctrl: Enables/resets the FIFO. 28 * @fifo_en: Determines which data will appear in FIFO. 29 * @gyro_config: gyro config register. 30 * @accl_config: accel config register 31 * @fifo_count_h: Upper byte of FIFO count. 32 * @fifo_r_w: FIFO register. 33 * @raw_gyro: Address of first gyro register. 34 * @raw_accl: Address of first accel register. 35 * @temperature: temperature register 36 * @int_enable: Interrupt enable register. 37 * @int_status: Interrupt status register. 38 * @pwr_mgmt_1: Controls chip's power state and clock source. 39 * @pwr_mgmt_2: Controls power state of individual sensors. 40 * @int_pin_cfg; Controls interrupt pin configuration. 41 * @accl_offset: Controls the accelerometer calibration offset. 42 * @gyro_offset: Controls the gyroscope calibration offset. 43 * @i2c_if: Controls the i2c interface 44 */ 45 struct inv_mpu6050_reg_map { 46 u8 sample_rate_div; 47 u8 lpf; 48 u8 accel_lpf; 49 u8 user_ctrl; 50 u8 fifo_en; 51 u8 gyro_config; 52 u8 accl_config; 53 u8 fifo_count_h; 54 u8 fifo_r_w; 55 u8 raw_gyro; 56 u8 raw_accl; 57 u8 temperature; 58 u8 int_enable; 59 u8 int_status; 60 u8 pwr_mgmt_1; 61 u8 pwr_mgmt_2; 62 u8 int_pin_cfg; 63 u8 accl_offset; 64 u8 gyro_offset; 65 u8 i2c_if; 66 }; 67 68 /*device enum */ 69 enum inv_devices { 70 INV_MPU6050, 71 INV_MPU6500, 72 INV_MPU6515, 73 INV_MPU6000, 74 INV_MPU9150, 75 INV_MPU9250, 76 INV_MPU9255, 77 INV_ICM20608, 78 INV_ICM20609, 79 INV_ICM20689, 80 INV_ICM20602, 81 INV_ICM20690, 82 INV_IAM20680, 83 INV_NUM_PARTS 84 }; 85 86 /* chip sensors mask: accelerometer, gyroscope, temperature, magnetometer */ 87 #define INV_MPU6050_SENSOR_ACCL BIT(0) 88 #define INV_MPU6050_SENSOR_GYRO BIT(1) 89 #define INV_MPU6050_SENSOR_TEMP BIT(2) 90 #define INV_MPU6050_SENSOR_MAGN BIT(3) 91 92 /** 93 * struct inv_mpu6050_chip_config - Cached chip configuration data. 94 * @clk: selected chip clock 95 * @fsr: Full scale range. 96 * @lpf: Digital low pass filter frequency. 97 * @accl_fs: accel full scale range. 98 * @accl_en: accel engine enabled 99 * @gyro_en: gyro engine enabled 100 * @temp_en: temperature sensor enabled 101 * @magn_en: magn engine (i2c master) enabled 102 * @accl_fifo_enable: enable accel data output 103 * @gyro_fifo_enable: enable gyro data output 104 * @temp_fifo_enable: enable temp data output 105 * @magn_fifo_enable: enable magn data output 106 * @divider: chip sample rate divider (sample rate divider - 1) 107 */ 108 struct inv_mpu6050_chip_config { 109 unsigned int clk:3; 110 unsigned int fsr:2; 111 unsigned int lpf:3; 112 unsigned int accl_fs:2; 113 unsigned int accl_en:1; 114 unsigned int gyro_en:1; 115 unsigned int temp_en:1; 116 unsigned int magn_en:1; 117 unsigned int accl_fifo_enable:1; 118 unsigned int gyro_fifo_enable:1; 119 unsigned int temp_fifo_enable:1; 120 unsigned int magn_fifo_enable:1; 121 u8 divider; 122 u8 user_ctrl; 123 }; 124 125 /* 126 * Maximum of 6 + 6 + 2 + 7 (for MPU9x50) = 21 round up to 24 and plus 8. 127 * May be less if fewer channels are enabled, as long as the timestamp 128 * remains 8 byte aligned 129 */ 130 #define INV_MPU6050_OUTPUT_DATA_SIZE 32 131 132 /** 133 * struct inv_mpu6050_hw - Other important hardware information. 134 * @whoami: Self identification byte from WHO_AM_I register 135 * @name: name of the chip. 136 * @reg: register map of the chip. 137 * @config: configuration of the chip. 138 * @fifo_size: size of the FIFO in bytes. 139 * @temp: offset and scale to apply to raw temperature. 140 */ 141 struct inv_mpu6050_hw { 142 u8 whoami; 143 u8 *name; 144 const struct inv_mpu6050_reg_map *reg; 145 const struct inv_mpu6050_chip_config *config; 146 size_t fifo_size; 147 struct { 148 int offset; 149 int scale; 150 } temp; 151 }; 152 153 /* 154 * struct inv_mpu6050_state - Driver state variables. 155 * @lock: Chip access lock. 156 * @trig: IIO trigger. 157 * @chip_config: Cached attribute information. 158 * @reg: Map of important registers. 159 * @hw: Other hardware-specific information. 160 * @chip_type: chip type. 161 * @plat_data: platform data (deprecated in favor of @orientation). 162 * @orientation: sensor chip orientation relative to main hardware. 163 * @map regmap pointer. 164 * @irq interrupt number. 165 * @irq_mask the int_pin_cfg mask to configure interrupt type. 166 * @chip_period: chip internal period estimation (~1kHz). 167 * @it_timestamp: timestamp from previous interrupt. 168 * @data_timestamp: timestamp for next data sample. 169 * @vdd_supply: VDD voltage regulator for the chip. 170 * @vddio_supply I/O voltage regulator for the chip. 171 * @magn_disabled: magnetometer disabled for backward compatibility reason. 172 * @magn_raw_to_gauss: coefficient to convert mag raw value to Gauss. 173 * @magn_orient: magnetometer sensor chip orientation if available. 174 * @suspended_sensors: sensors mask of sensors turned off for suspend 175 * @data: dma safe buffer used for bulk reads. 176 */ 177 struct inv_mpu6050_state { 178 struct mutex lock; 179 struct iio_trigger *trig; 180 struct inv_mpu6050_chip_config chip_config; 181 const struct inv_mpu6050_reg_map *reg; 182 const struct inv_mpu6050_hw *hw; 183 enum inv_devices chip_type; 184 struct i2c_mux_core *muxc; 185 struct i2c_client *mux_client; 186 struct inv_mpu6050_platform_data plat_data; 187 struct iio_mount_matrix orientation; 188 struct regmap *map; 189 int irq; 190 u8 irq_mask; 191 unsigned skip_samples; 192 s64 chip_period; 193 s64 it_timestamp; 194 s64 data_timestamp; 195 struct regulator *vdd_supply; 196 struct regulator *vddio_supply; 197 bool magn_disabled; 198 s32 magn_raw_to_gauss[3]; 199 struct iio_mount_matrix magn_orient; 200 unsigned int suspended_sensors; 201 u8 data[INV_MPU6050_OUTPUT_DATA_SIZE] ____cacheline_aligned; 202 }; 203 204 /*register and associated bit definition*/ 205 #define INV_MPU6050_REG_ACCEL_OFFSET 0x06 206 #define INV_MPU6050_REG_GYRO_OFFSET 0x13 207 208 #define INV_MPU6050_REG_SAMPLE_RATE_DIV 0x19 209 #define INV_MPU6050_REG_CONFIG 0x1A 210 #define INV_MPU6050_REG_GYRO_CONFIG 0x1B 211 #define INV_MPU6050_REG_ACCEL_CONFIG 0x1C 212 213 #define INV_MPU6050_REG_FIFO_EN 0x23 214 #define INV_MPU6050_BIT_SLAVE_0 0x01 215 #define INV_MPU6050_BIT_SLAVE_1 0x02 216 #define INV_MPU6050_BIT_SLAVE_2 0x04 217 #define INV_MPU6050_BIT_ACCEL_OUT 0x08 218 #define INV_MPU6050_BITS_GYRO_OUT 0x70 219 #define INV_MPU6050_BIT_TEMP_OUT 0x80 220 221 #define INV_MPU6050_REG_I2C_MST_CTRL 0x24 222 #define INV_MPU6050_BITS_I2C_MST_CLK_400KHZ 0x0D 223 #define INV_MPU6050_BIT_I2C_MST_P_NSR 0x10 224 #define INV_MPU6050_BIT_SLV3_FIFO_EN 0x20 225 #define INV_MPU6050_BIT_WAIT_FOR_ES 0x40 226 #define INV_MPU6050_BIT_MULT_MST_EN 0x80 227 228 /* control I2C slaves from 0 to 3 */ 229 #define INV_MPU6050_REG_I2C_SLV_ADDR(_x) (0x25 + 3 * (_x)) 230 #define INV_MPU6050_BIT_I2C_SLV_RNW 0x80 231 232 #define INV_MPU6050_REG_I2C_SLV_REG(_x) (0x26 + 3 * (_x)) 233 234 #define INV_MPU6050_REG_I2C_SLV_CTRL(_x) (0x27 + 3 * (_x)) 235 #define INV_MPU6050_BIT_SLV_GRP 0x10 236 #define INV_MPU6050_BIT_SLV_REG_DIS 0x20 237 #define INV_MPU6050_BIT_SLV_BYTE_SW 0x40 238 #define INV_MPU6050_BIT_SLV_EN 0x80 239 240 /* I2C master delay register */ 241 #define INV_MPU6050_REG_I2C_SLV4_CTRL 0x34 242 #define INV_MPU6050_BITS_I2C_MST_DLY(_x) ((_x) & 0x1F) 243 244 #define INV_MPU6050_REG_I2C_MST_STATUS 0x36 245 #define INV_MPU6050_BIT_I2C_SLV0_NACK 0x01 246 #define INV_MPU6050_BIT_I2C_SLV1_NACK 0x02 247 #define INV_MPU6050_BIT_I2C_SLV2_NACK 0x04 248 #define INV_MPU6050_BIT_I2C_SLV3_NACK 0x08 249 250 #define INV_MPU6050_REG_INT_ENABLE 0x38 251 #define INV_MPU6050_BIT_DATA_RDY_EN 0x01 252 #define INV_MPU6050_BIT_DMP_INT_EN 0x02 253 254 #define INV_MPU6050_REG_RAW_ACCEL 0x3B 255 #define INV_MPU6050_REG_TEMPERATURE 0x41 256 #define INV_MPU6050_REG_RAW_GYRO 0x43 257 258 #define INV_MPU6050_REG_INT_STATUS 0x3A 259 #define INV_MPU6050_BIT_FIFO_OVERFLOW_INT 0x10 260 #define INV_MPU6050_BIT_RAW_DATA_RDY_INT 0x01 261 262 #define INV_MPU6050_REG_EXT_SENS_DATA 0x49 263 264 /* I2C slaves data output from 0 to 3 */ 265 #define INV_MPU6050_REG_I2C_SLV_DO(_x) (0x63 + (_x)) 266 267 #define INV_MPU6050_REG_I2C_MST_DELAY_CTRL 0x67 268 #define INV_MPU6050_BIT_I2C_SLV0_DLY_EN 0x01 269 #define INV_MPU6050_BIT_I2C_SLV1_DLY_EN 0x02 270 #define INV_MPU6050_BIT_I2C_SLV2_DLY_EN 0x04 271 #define INV_MPU6050_BIT_I2C_SLV3_DLY_EN 0x08 272 #define INV_MPU6050_BIT_DELAY_ES_SHADOW 0x80 273 274 #define INV_MPU6050_REG_SIGNAL_PATH_RESET 0x68 275 #define INV_MPU6050_BIT_TEMP_RST BIT(0) 276 #define INV_MPU6050_BIT_ACCEL_RST BIT(1) 277 #define INV_MPU6050_BIT_GYRO_RST BIT(2) 278 279 #define INV_MPU6050_REG_USER_CTRL 0x6A 280 #define INV_MPU6050_BIT_SIG_COND_RST 0x01 281 #define INV_MPU6050_BIT_FIFO_RST 0x04 282 #define INV_MPU6050_BIT_DMP_RST 0x08 283 #define INV_MPU6050_BIT_I2C_MST_EN 0x20 284 #define INV_MPU6050_BIT_FIFO_EN 0x40 285 #define INV_MPU6050_BIT_DMP_EN 0x80 286 #define INV_MPU6050_BIT_I2C_IF_DIS 0x10 287 288 #define INV_MPU6050_REG_PWR_MGMT_1 0x6B 289 #define INV_MPU6050_BIT_H_RESET 0x80 290 #define INV_MPU6050_BIT_SLEEP 0x40 291 #define INV_MPU6050_BIT_TEMP_DIS 0x08 292 #define INV_MPU6050_BIT_CLK_MASK 0x7 293 294 #define INV_MPU6050_REG_PWR_MGMT_2 0x6C 295 #define INV_MPU6050_BIT_PWR_ACCL_STBY 0x38 296 #define INV_MPU6050_BIT_PWR_GYRO_STBY 0x07 297 298 /* ICM20602 register */ 299 #define INV_ICM20602_REG_I2C_IF 0x70 300 #define INV_ICM20602_BIT_I2C_IF_DIS 0x40 301 302 #define INV_MPU6050_REG_FIFO_COUNT_H 0x72 303 #define INV_MPU6050_REG_FIFO_R_W 0x74 304 305 #define INV_MPU6050_BYTES_PER_3AXIS_SENSOR 6 306 #define INV_MPU6050_FIFO_COUNT_BYTE 2 307 308 /* MPU9X50 9-axis magnetometer */ 309 #define INV_MPU9X50_BYTES_MAGN 7 310 311 /* FIFO temperature sample size */ 312 #define INV_MPU6050_BYTES_PER_TEMP_SENSOR 2 313 314 /* mpu6500 registers */ 315 #define INV_MPU6500_REG_ACCEL_CONFIG_2 0x1D 316 #define INV_ICM20689_BITS_FIFO_SIZE_MAX 0xC0 317 #define INV_MPU6500_REG_ACCEL_OFFSET 0x77 318 319 /* delay time in milliseconds */ 320 #define INV_MPU6050_POWER_UP_TIME 100 321 #define INV_MPU6050_TEMP_UP_TIME 100 322 #define INV_MPU6050_ACCEL_UP_TIME 20 323 #define INV_MPU6050_GYRO_UP_TIME 35 324 #define INV_MPU6050_GYRO_DOWN_TIME 150 325 #define INV_MPU6050_SUSPEND_DELAY_MS 2000 326 327 /* delay time in microseconds */ 328 #define INV_MPU6050_REG_UP_TIME_MIN 5000 329 #define INV_MPU6050_REG_UP_TIME_MAX 10000 330 331 #define INV_MPU6050_TEMP_OFFSET 12420 332 #define INV_MPU6050_TEMP_SCALE 2941176 333 #define INV_MPU6050_MAX_GYRO_FS_PARAM 3 334 #define INV_MPU6050_MAX_ACCL_FS_PARAM 3 335 #define INV_MPU6050_THREE_AXIS 3 336 #define INV_MPU6050_GYRO_CONFIG_FSR_SHIFT 3 337 #define INV_ICM20690_GYRO_CONFIG_FSR_SHIFT 2 338 #define INV_MPU6050_ACCL_CONFIG_FSR_SHIFT 3 339 340 #define INV_MPU6500_TEMP_OFFSET 7011 341 #define INV_MPU6500_TEMP_SCALE 2995178 342 343 #define INV_ICM20608_TEMP_OFFSET 8170 344 #define INV_ICM20608_TEMP_SCALE 3059976 345 346 #define INV_MPU6050_REG_INT_PIN_CFG 0x37 347 #define INV_MPU6050_ACTIVE_HIGH 0x00 348 #define INV_MPU6050_ACTIVE_LOW 0x80 349 /* enable level triggering */ 350 #define INV_MPU6050_LATCH_INT_EN 0x20 351 #define INV_MPU6050_BIT_BYPASS_EN 0x2 352 353 /* Allowed timestamp period jitter in percent */ 354 #define INV_MPU6050_TS_PERIOD_JITTER 4 355 356 /* init parameters */ 357 #define INV_MPU6050_MAX_FIFO_RATE 1000 358 #define INV_MPU6050_MIN_FIFO_RATE 4 359 360 /* chip internal frequency: 1KHz */ 361 #define INV_MPU6050_INTERNAL_FREQ_HZ 1000 362 /* return the frequency divider (chip sample rate divider + 1) */ 363 #define INV_MPU6050_FREQ_DIVIDER(st) \ 364 ((st)->chip_config.divider + 1) 365 /* chip sample rate divider to fifo rate */ 366 #define INV_MPU6050_FIFO_RATE_TO_DIVIDER(fifo_rate) \ 367 ((INV_MPU6050_INTERNAL_FREQ_HZ / (fifo_rate)) - 1) 368 #define INV_MPU6050_DIVIDER_TO_FIFO_RATE(divider) \ 369 (INV_MPU6050_INTERNAL_FREQ_HZ / ((divider) + 1)) 370 371 #define INV_MPU6050_REG_WHOAMI 117 372 373 #define INV_MPU6000_WHOAMI_VALUE 0x68 374 #define INV_MPU6050_WHOAMI_VALUE 0x68 375 #define INV_MPU6500_WHOAMI_VALUE 0x70 376 #define INV_MPU9150_WHOAMI_VALUE 0x68 377 #define INV_MPU9250_WHOAMI_VALUE 0x71 378 #define INV_MPU9255_WHOAMI_VALUE 0x73 379 #define INV_MPU6515_WHOAMI_VALUE 0x74 380 #define INV_ICM20608_WHOAMI_VALUE 0xAF 381 #define INV_ICM20609_WHOAMI_VALUE 0xA6 382 #define INV_ICM20689_WHOAMI_VALUE 0x98 383 #define INV_ICM20602_WHOAMI_VALUE 0x12 384 #define INV_ICM20690_WHOAMI_VALUE 0x20 385 #define INV_IAM20680_WHOAMI_VALUE 0xA9 386 387 /* scan element definition for generic MPU6xxx devices */ 388 enum inv_mpu6050_scan { 389 INV_MPU6050_SCAN_ACCL_X, 390 INV_MPU6050_SCAN_ACCL_Y, 391 INV_MPU6050_SCAN_ACCL_Z, 392 INV_MPU6050_SCAN_TEMP, 393 INV_MPU6050_SCAN_GYRO_X, 394 INV_MPU6050_SCAN_GYRO_Y, 395 INV_MPU6050_SCAN_GYRO_Z, 396 INV_MPU6050_SCAN_TIMESTAMP, 397 398 INV_MPU9X50_SCAN_MAGN_X = INV_MPU6050_SCAN_GYRO_Z + 1, 399 INV_MPU9X50_SCAN_MAGN_Y, 400 INV_MPU9X50_SCAN_MAGN_Z, 401 INV_MPU9X50_SCAN_TIMESTAMP, 402 }; 403 404 enum inv_mpu6050_filter_e { 405 INV_MPU6050_FILTER_NOLPF2 = 0, 406 INV_MPU6050_FILTER_200HZ, 407 INV_MPU6050_FILTER_100HZ, 408 INV_MPU6050_FILTER_45HZ, 409 INV_MPU6050_FILTER_20HZ, 410 INV_MPU6050_FILTER_10HZ, 411 INV_MPU6050_FILTER_5HZ, 412 INV_MPU6050_FILTER_NOLPF, 413 NUM_MPU6050_FILTER 414 }; 415 416 /* IIO attribute address */ 417 enum INV_MPU6050_IIO_ATTR_ADDR { 418 ATTR_GYRO_MATRIX, 419 ATTR_ACCL_MATRIX, 420 }; 421 422 enum inv_mpu6050_accl_fs_e { 423 INV_MPU6050_FS_02G = 0, 424 INV_MPU6050_FS_04G, 425 INV_MPU6050_FS_08G, 426 INV_MPU6050_FS_16G, 427 NUM_ACCL_FSR 428 }; 429 430 enum inv_mpu6050_fsr_e { 431 INV_MPU6050_FSR_250DPS = 0, 432 INV_MPU6050_FSR_500DPS, 433 INV_MPU6050_FSR_1000DPS, 434 INV_MPU6050_FSR_2000DPS, 435 NUM_MPU6050_FSR 436 }; 437 438 enum inv_mpu6050_clock_sel_e { 439 INV_CLK_INTERNAL = 0, 440 INV_CLK_PLL, 441 NUM_CLK 442 }; 443 444 irqreturn_t inv_mpu6050_read_fifo(int irq, void *p); 445 int inv_mpu6050_probe_trigger(struct iio_dev *indio_dev, int irq_type); 446 int inv_mpu6050_prepare_fifo(struct inv_mpu6050_state *st, bool enable); 447 int inv_mpu6050_switch_engine(struct inv_mpu6050_state *st, bool en, 448 unsigned int mask); 449 int inv_mpu6050_write_reg(struct inv_mpu6050_state *st, int reg, u8 val); 450 int inv_mpu_acpi_create_mux_client(struct i2c_client *client); 451 void inv_mpu_acpi_delete_mux_client(struct i2c_client *client); 452 int inv_mpu_core_probe(struct regmap *regmap, int irq, const char *name, 453 int (*inv_mpu_bus_setup)(struct iio_dev *), int chip_type); 454 extern const struct dev_pm_ops inv_mpu_pmops; 455 456 #endif 457